1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 #include "common-defs.h"
21 #include "common-regcache.h"
27 thumb_insn_size (unsigned short inst1
)
29 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
38 bitcount (unsigned long val
)
41 for (nbits
= 0; val
!= 0; nbits
++)
42 val
&= val
- 1; /* Delete rightmost 1-bit in val. */
49 condition_true (unsigned long cond
, unsigned long status_reg
)
51 if (cond
== INST_AL
|| cond
== INST_NV
)
57 return ((status_reg
& FLAG_Z
) != 0);
59 return ((status_reg
& FLAG_Z
) == 0);
61 return ((status_reg
& FLAG_C
) != 0);
63 return ((status_reg
& FLAG_C
) == 0);
65 return ((status_reg
& FLAG_N
) != 0);
67 return ((status_reg
& FLAG_N
) == 0);
69 return ((status_reg
& FLAG_V
) != 0);
71 return ((status_reg
& FLAG_V
) == 0);
73 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
75 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
77 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
79 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
81 return (((status_reg
& FLAG_Z
) == 0)
82 && (((status_reg
& FLAG_N
) == 0)
83 == ((status_reg
& FLAG_V
) == 0)));
85 return (((status_reg
& FLAG_Z
) != 0)
86 || (((status_reg
& FLAG_N
) == 0)
87 != ((status_reg
& FLAG_V
) == 0)));
96 thumb_advance_itstate (unsigned int itstate
)
98 /* Preserve IT[7:5], the first three bits of the condition. Shift
99 the upcoming condition flags left by one bit. */
100 itstate
= (itstate
& 0xe0) | ((itstate
<< 1) & 0x1f);
102 /* If we have finished the IT block, clear the state. */
103 if ((itstate
& 0x0f) == 0)
112 arm_instruction_changes_pc (uint32_t this_instr
)
114 if (bits (this_instr
, 28, 31) == INST_NV
)
115 /* Unconditional instructions. */
116 switch (bits (this_instr
, 24, 27))
120 /* Branch with Link and change to Thumb. */
125 /* Coprocessor register transfer. */
126 if (bits (this_instr
, 12, 15) == 15)
127 error (_("Invalid update to pc in instruction"));
133 switch (bits (this_instr
, 25, 27))
136 if (bits (this_instr
, 23, 24) == 2 && bit (this_instr
, 20) == 0)
138 /* Multiplies and extra load/stores. */
139 if (bit (this_instr
, 4) == 1 && bit (this_instr
, 7) == 1)
140 /* Neither multiplies nor extension load/stores are allowed
144 /* Otherwise, miscellaneous instructions. */
146 /* BX <reg>, BXJ <reg>, BLX <reg> */
147 if (bits (this_instr
, 4, 27) == 0x12fff1
148 || bits (this_instr
, 4, 27) == 0x12fff2
149 || bits (this_instr
, 4, 27) == 0x12fff3)
152 /* Other miscellaneous instructions are unpredictable if they
156 /* Data processing instruction. Fall through. */
159 if (bits (this_instr
, 12, 15) == 15)
166 /* Media instructions and architecturally undefined instructions. */
167 if (bits (this_instr
, 25, 27) == 3 && bit (this_instr
, 4) == 1)
171 if (bit (this_instr
, 20) == 0)
175 if (bits (this_instr
, 12, 15) == ARM_PC_REGNUM
)
181 /* Load/store multiple. */
182 if (bit (this_instr
, 20) == 1 && bit (this_instr
, 15) == 1)
188 /* Branch and branch with link. */
193 /* Coprocessor transfers or SWIs can not affect PC. */
197 internal_error (__FILE__
, __LINE__
, _("bad value in switch"));
204 thumb_instruction_changes_pc (unsigned short inst
)
206 if ((inst
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
209 if ((inst
& 0xf000) == 0xd000) /* conditional branch */
212 if ((inst
& 0xf800) == 0xe000) /* unconditional branch */
215 if ((inst
& 0xff00) == 0x4700) /* bx REG, blx REG */
218 if ((inst
& 0xff87) == 0x4687) /* mov pc, REG */
221 if ((inst
& 0xf500) == 0xb100) /* CBNZ or CBZ. */
231 thumb2_instruction_changes_pc (unsigned short inst1
, unsigned short inst2
)
233 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
235 /* Branches and miscellaneous control instructions. */
237 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
242 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
244 /* SUBS PC, LR, #imm8. */
247 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
249 /* Conditional branch. */
256 if ((inst1
& 0xfe50) == 0xe810)
258 /* Load multiple or RFE. */
260 if (bit (inst1
, 7) && !bit (inst1
, 8))
266 else if (!bit (inst1
, 7) && bit (inst1
, 8))
272 else if (bit (inst1
, 7) && bit (inst1
, 8))
277 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
286 if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
288 /* MOV PC or MOVS PC. */
292 if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
295 if (bits (inst1
, 0, 3) == 15)
301 if ((inst2
& 0x0fc0) == 0x0000)
307 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
313 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
325 shifted_reg_val (struct regcache
*regcache
, unsigned long inst
,
326 int carry
, unsigned long pc_val
, unsigned long status_reg
)
328 unsigned long res
, shift
;
329 int rm
= bits (inst
, 0, 3);
330 unsigned long shifttype
= bits (inst
, 5, 6);
334 int rs
= bits (inst
, 8, 11);
337 : regcache_raw_get_unsigned (regcache
, rs
)) & 0xFF;
340 shift
= bits (inst
, 7, 11);
342 res
= (rm
== ARM_PC_REGNUM
343 ? (pc_val
+ (bit (inst
, 4) ? 12 : 8))
344 : regcache_raw_get_unsigned (regcache
, rm
));
349 res
= shift
>= 32 ? 0 : res
<< shift
;
353 res
= shift
>= 32 ? 0 : res
>> shift
;
359 res
= ((res
& 0x80000000L
)
360 ? ~((~res
) >> shift
) : res
>> shift
);
363 case 3: /* ROR/RRX */
366 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
368 res
= (res
>> shift
) | (res
<< (32 - shift
));
372 return res
& 0xffffffff;
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