1 /* Print Acorn Risc Machine instructions for GDB, the GNU debugger.
2 Copyright 1986, 1989, 1991 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
25 #include "opcode/arm.h"
27 extern char *reg_names
[];
29 static char *shift_names
[] = {
30 "lsl", "lsr", "asr", "ror",
33 static char *cond_names
[] = {
34 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
35 "hi", "ls", "ge", "lt", "gt", "le", "", "nv"
38 static char float_precision
[] = "sdep";
39 static char float_rounding
[] = " pmz";
40 static float float_immed
[] = { 0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 0.5, 10.0 };
42 static void print_ldr_str_offset();
43 static void print_ldc_stc_offset();
44 static long immediate_value();
46 /* Print the ARM instruction at address MEMADDR in debugged memory,
47 on STREAM. Returns length of the instruction, in bytes. */
50 print_insn (memaddr
, stream
)
55 register struct opcode
*op
;
60 ins
= read_memory_integer(memaddr
, 4);
61 for (i
= 0, op
= opcodes
; i
< N_OPCODES
; i
++, op
++)
62 if ((ins
& op
->mask
) == op
->value
) break;
63 assert(i
!= N_OPCODES
);
65 for (p
= op
->assembler
; *p
;) {
70 s
= s
*10 + (*p
++ - '0');
74 e
= e
*10 + (*p
++ - '0');
77 assert(s
>= 0 && s
<= 31 && e
>= 0 && e
<= 31);
78 val
= (ins
>> s
) & ((1 << (e
+ 1 - s
)) - 1);
84 fprintf(stream
, "%d", val
);
87 fprintf(stream
, "%x", val
);
90 assert(val
>= 0 && val
<= 15);
91 fprintf(stream
, "%s", reg_names
[val
]);
94 fprintf(stream
, "%s", cond_names
[ins
>> 28]);
119 if (((ins
>> 12) & 0xf) == 0xf)
124 int immed
= immediate_value(ins
& 0xfff);
125 fprintf (stream
, "#%d (0x%x)", immed
, immed
);
127 int operand2
= ins
& 0xfff;
129 bits 0-3 are the base register
130 bits 5-6 are the shift (0=lsl, 1=lsr, 2=asr, 3=ror)
131 if bit 4 is zero then bits 7-11 are an immediate shift count
132 else bit 7 must be zero and bits 8-11 are the register
133 to be used as a shift count.
134 Note: no shift at all is encoded as "reg lsl #0" */
135 fprintf (stream
, "%s", reg_names
[operand2
& 0xf]);
136 if (operand2
& 0xff0) {
137 /* ror #0 is really rrx (rotate right extend) */
138 if ((operand2
& 0xff0) == 0x060)
139 fprintf (stream
, ", rrx");
141 fprintf (stream
, ", %s ",
142 shift_names
[(operand2
>> 5) & 3]);
143 if (operand2
& (1<<4)) /* register shift */
144 fprintf (stream
, "%s",
145 reg_names
[operand2
>> 8]);
146 else /* immediate shift */
147 fprintf (stream
, "#%d",
154 fprintf (stream
, "[%s", reg_names
[(ins
>> 16) & 0xf]);
156 fprintf (stream
, ", ");
157 print_ldr_str_offset (ins
, stream
);
159 if (ins
& (1<<21)) putc('!', stream
);
160 /* If it is a pc relative load, then it is probably
161 a constant so print it */
162 if (((ins
>> 16) & 0xf) == 15 &&
163 (ins
& (1<<25)) == 0 &&
165 int addr
= memaddr
+ 8 +
166 (ins
& 0xfff) * ((ins
& (1<<23)) ? 1 : -1);
167 fprintf (stream
, " (contents=");
168 print_address (read_memory_integer(addr
, 4), stream
);
169 fprintf (stream
, ")");
172 fprintf (stream
, "]," );
173 print_ldr_str_offset (ins
, stream
);
177 print_address (memaddr
+ 8 + (((int)ins
<< 8) >> 6), stream
);
180 fprintf (stream
, "[%s", reg_names
[(ins
>> 16) & 0xf]);
182 fprintf (stream
, ", ");
183 print_ldc_stc_offset (ins
, stream
);
188 fprintf (stream
, "], ");
189 print_ldc_stc_offset (ins
, stream
);
194 int regnum
, first
= 1;
196 for (regnum
= 0; regnum
< 16; regnum
++)
197 if (ins
& (1<<regnum
)) {
201 fprintf (stream
, "%s", reg_names
[regnum
]);
207 val
= ((ins
>> 18) & 2) | ((ins
>> 7) & 1);
208 putc(float_precision
[val
], stream
);
211 val
= ((ins
>> 21) & 2) | ((ins
>> 15) & 1);
212 putc(float_precision
[val
], stream
);
215 val
= ((ins
>> 5) & 3);
216 if (val
) putc(float_rounding
[val
], stream
);
219 assert(val
>= 0 && val
<= 15);
221 fprintf (stream
, "#%3.1f", float_immed
[val
- 8]);
223 fprintf (stream
, "f%d", val
);
235 immediate_value(operand
)
238 int val
= operand
& 0xff;
239 int shift
= 2*(operand
>> 8);
240 /* immediate value is (val ror shift) */
241 return (val
>> shift
) | (val
<< (32 - shift
));
245 print_ldr_str_offset(ins
, stream
)
249 if ((ins
& (1<<25)) == 0)
250 fprintf (stream
, "#%d",
251 (ins
& 0xfff) * ((ins
& (1<<23)) ? 1 : -1));
253 fprintf (stream
, "%s%s", reg_names
[ins
& 0xf],
254 (ins
& (1<<23)) ? "" : "-");
256 fprintf (stream
, ", %s #%d",
257 shift_names
[(ins
>> 5) & 3],
263 print_ldc_stc_offset(ins
, stream
)
267 fprintf (stream
, "#%d",
268 4 * (ins
& 0xff) * ((ins
& (1<<23)) ? 1 : -1));
This page took 0.035356 seconds and 4 git commands to generate.