1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
31 #include "reggroups.h"
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "arch/arm-get-next-pcs.h"
51 #include "gdb/sim-arm.h"
54 #include "coff/internal.h"
60 #include "record-full.h"
62 #include "features/arm-with-m.c"
63 #include "features/arm-with-m-fpa-layout.c"
64 #include "features/arm-with-m-vfp-d16.c"
65 #include "features/arm-with-iwmmxt.c"
66 #include "features/arm-with-vfpv2.c"
67 #include "features/arm-with-vfpv3.c"
68 #include "features/arm-with-neon.c"
72 /* Macros for setting and testing a bit in a minimal symbol that marks
73 it as Thumb function. The MSB of the minimal symbol's "info" field
74 is used for this purpose.
76 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
77 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
79 #define MSYMBOL_SET_SPECIAL(msym) \
80 MSYMBOL_TARGET_FLAG_1 (msym) = 1
82 #define MSYMBOL_IS_SPECIAL(msym) \
83 MSYMBOL_TARGET_FLAG_1 (msym)
85 /* Per-objfile data used for mapping symbols. */
86 static const struct objfile_data
*arm_objfile_data_key
;
88 struct arm_mapping_symbol
93 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
94 DEF_VEC_O(arm_mapping_symbol_s
);
96 struct arm_per_objfile
98 VEC(arm_mapping_symbol_s
) **section_maps
;
101 /* The list of available "set arm ..." and "show arm ..." commands. */
102 static struct cmd_list_element
*setarmcmdlist
= NULL
;
103 static struct cmd_list_element
*showarmcmdlist
= NULL
;
105 /* The type of floating-point to use. Keep this in sync with enum
106 arm_float_model, and the help string in _initialize_arm_tdep. */
107 static const char *const fp_model_strings
[] =
117 /* A variable that can be configured by the user. */
118 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
119 static const char *current_fp_model
= "auto";
121 /* The ABI to use. Keep this in sync with arm_abi_kind. */
122 static const char *const arm_abi_strings
[] =
130 /* A variable that can be configured by the user. */
131 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
132 static const char *arm_abi_string
= "auto";
134 /* The execution mode to assume. */
135 static const char *const arm_mode_strings
[] =
143 static const char *arm_fallback_mode_string
= "auto";
144 static const char *arm_force_mode_string
= "auto";
146 /* Internal override of the execution mode. -1 means no override,
147 0 means override to ARM mode, 1 means override to Thumb mode.
148 The effect is the same as if arm_force_mode has been set by the
149 user (except the internal override has precedence over a user's
150 arm_force_mode override). */
151 static int arm_override_mode
= -1;
153 /* Number of different reg name sets (options). */
154 static int num_disassembly_options
;
156 /* The standard register names, and all the valid aliases for them. Note
157 that `fp', `sp' and `pc' are not added in this alias list, because they
158 have been added as builtin user registers in
159 std-regs.c:_initialize_frame_reg. */
164 } arm_register_aliases
[] = {
165 /* Basic register numbers. */
182 /* Synonyms (argument and variable registers). */
195 /* Other platform-specific names for r9. */
201 /* Names used by GCC (not listed in the ARM EABI). */
203 /* A special name from the older ATPCS. */
207 static const char *const arm_register_names
[] =
208 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
209 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
210 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
211 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
212 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
213 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
214 "fps", "cpsr" }; /* 24 25 */
216 /* Valid register name styles. */
217 static const char **valid_disassembly_styles
;
219 /* Disassembly style to use. Default to "std" register names. */
220 static const char *disassembly_style
;
222 /* This is used to keep the bfd arch_info in sync with the disassembly
224 static void set_disassembly_style_sfunc(char *, int,
225 struct cmd_list_element
*);
226 static void set_disassembly_style (void);
228 static void convert_from_extended (const struct floatformat
*, const void *,
230 static void convert_to_extended (const struct floatformat
*, void *,
233 static enum register_status
arm_neon_quad_read (struct gdbarch
*gdbarch
,
234 struct regcache
*regcache
,
235 int regnum
, gdb_byte
*buf
);
236 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
237 struct regcache
*regcache
,
238 int regnum
, const gdb_byte
*buf
);
241 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
);
244 /* get_next_pcs operations. */
245 static struct arm_get_next_pcs_ops arm_get_next_pcs_ops
= {
246 arm_get_next_pcs_read_memory_unsigned_integer
,
247 arm_get_next_pcs_syscall_next_pc
,
248 arm_get_next_pcs_addr_bits_remove
,
249 arm_get_next_pcs_is_thumb
,
253 struct arm_prologue_cache
255 /* The stack pointer at the time this frame was created; i.e. the
256 caller's stack pointer when this function was called. It is used
257 to identify this frame. */
260 /* The frame base for this frame is just prev_sp - frame size.
261 FRAMESIZE is the distance from the frame pointer to the
262 initial stack pointer. */
266 /* The register used to hold the frame pointer for this frame. */
269 /* Saved register offsets. */
270 struct trad_frame_saved_reg
*saved_regs
;
273 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
274 CORE_ADDR prologue_start
,
275 CORE_ADDR prologue_end
,
276 struct arm_prologue_cache
*cache
);
278 /* Architecture version for displaced stepping. This effects the behaviour of
279 certain instructions, and really should not be hard-wired. */
281 #define DISPLACED_STEPPING_ARCH_VERSION 5
283 /* Set to true if the 32-bit mode is in use. */
287 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
290 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
292 if (gdbarch_tdep (gdbarch
)->is_m
)
298 /* Determine if the processor is currently executing in Thumb mode. */
301 arm_is_thumb (struct regcache
*regcache
)
304 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regcache
));
306 cpsr
= regcache_raw_get_unsigned (regcache
, ARM_PS_REGNUM
);
308 return (cpsr
& t_bit
) != 0;
311 /* Determine if FRAME is executing in Thumb mode. */
314 arm_frame_is_thumb (struct frame_info
*frame
)
317 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
319 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
320 directly (from a signal frame or dummy frame) or by interpreting
321 the saved LR (from a prologue or DWARF frame). So consult it and
322 trust the unwinders. */
323 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
325 return (cpsr
& t_bit
) != 0;
328 /* Callback for VEC_lower_bound. */
331 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
332 const struct arm_mapping_symbol
*rhs
)
334 return lhs
->value
< rhs
->value
;
337 /* Search for the mapping symbol covering MEMADDR. If one is found,
338 return its type. Otherwise, return 0. If START is non-NULL,
339 set *START to the location of the mapping symbol. */
342 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
344 struct obj_section
*sec
;
346 /* If there are mapping symbols, consult them. */
347 sec
= find_pc_section (memaddr
);
350 struct arm_per_objfile
*data
;
351 VEC(arm_mapping_symbol_s
) *map
;
352 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
356 data
= (struct arm_per_objfile
*) objfile_data (sec
->objfile
,
357 arm_objfile_data_key
);
360 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
361 if (!VEC_empty (arm_mapping_symbol_s
, map
))
363 struct arm_mapping_symbol
*map_sym
;
365 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
366 arm_compare_mapping_symbols
);
368 /* VEC_lower_bound finds the earliest ordered insertion
369 point. If the following symbol starts at this exact
370 address, we use that; otherwise, the preceding
371 mapping symbol covers this address. */
372 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
374 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
375 if (map_sym
->value
== map_key
.value
)
378 *start
= map_sym
->value
+ obj_section_addr (sec
);
379 return map_sym
->type
;
385 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
387 *start
= map_sym
->value
+ obj_section_addr (sec
);
388 return map_sym
->type
;
397 /* Determine if the program counter specified in MEMADDR is in a Thumb
398 function. This function should be called for addresses unrelated to
399 any executing frame; otherwise, prefer arm_frame_is_thumb. */
402 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
404 struct bound_minimal_symbol sym
;
406 struct displaced_step_closure
* dsc
407 = get_displaced_step_closure_by_addr(memaddr
);
409 /* If checking the mode of displaced instruction in copy area, the mode
410 should be determined by instruction on the original address. */
414 fprintf_unfiltered (gdb_stdlog
,
415 "displaced: check mode of %.8lx instead of %.8lx\n",
416 (unsigned long) dsc
->insn_addr
,
417 (unsigned long) memaddr
);
418 memaddr
= dsc
->insn_addr
;
421 /* If bit 0 of the address is set, assume this is a Thumb address. */
422 if (IS_THUMB_ADDR (memaddr
))
425 /* Respect internal mode override if active. */
426 if (arm_override_mode
!= -1)
427 return arm_override_mode
;
429 /* If the user wants to override the symbol table, let him. */
430 if (strcmp (arm_force_mode_string
, "arm") == 0)
432 if (strcmp (arm_force_mode_string
, "thumb") == 0)
435 /* ARM v6-M and v7-M are always in Thumb mode. */
436 if (gdbarch_tdep (gdbarch
)->is_m
)
439 /* If there are mapping symbols, consult them. */
440 type
= arm_find_mapping_symbol (memaddr
, NULL
);
444 /* Thumb functions have a "special" bit set in minimal symbols. */
445 sym
= lookup_minimal_symbol_by_pc (memaddr
);
447 return (MSYMBOL_IS_SPECIAL (sym
.minsym
));
449 /* If the user wants to override the fallback mode, let them. */
450 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
452 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
455 /* If we couldn't find any symbol, but we're talking to a running
456 target, then trust the current value of $cpsr. This lets
457 "display/i $pc" always show the correct mode (though if there is
458 a symbol table we will not reach here, so it still may not be
459 displayed in the mode it will be executed). */
460 if (target_has_registers
)
461 return arm_frame_is_thumb (get_current_frame ());
463 /* Otherwise we're out of luck; we assume ARM. */
467 /* Remove useless bits from addresses in a running program. */
469 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
471 /* On M-profile devices, do not strip the low bit from EXC_RETURN
472 (the magic exception return address). */
473 if (gdbarch_tdep (gdbarch
)->is_m
474 && (val
& 0xfffffff0) == 0xfffffff0)
478 return UNMAKE_THUMB_ADDR (val
);
480 return (val
& 0x03fffffc);
483 /* Return 1 if PC is the start of a compiler helper function which
484 can be safely ignored during prologue skipping. IS_THUMB is true
485 if the function is known to be a Thumb function due to the way it
488 skip_prologue_function (struct gdbarch
*gdbarch
, CORE_ADDR pc
, int is_thumb
)
490 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
491 struct bound_minimal_symbol msym
;
493 msym
= lookup_minimal_symbol_by_pc (pc
);
494 if (msym
.minsym
!= NULL
495 && BMSYMBOL_VALUE_ADDRESS (msym
) == pc
496 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
)
498 const char *name
= MSYMBOL_LINKAGE_NAME (msym
.minsym
);
500 /* The GNU linker's Thumb call stub to foo is named
502 if (strstr (name
, "_from_thumb") != NULL
)
505 /* On soft-float targets, __truncdfsf2 is called to convert promoted
506 arguments to their argument types in non-prototyped
508 if (startswith (name
, "__truncdfsf2"))
510 if (startswith (name
, "__aeabi_d2f"))
513 /* Internal functions related to thread-local storage. */
514 if (startswith (name
, "__tls_get_addr"))
516 if (startswith (name
, "__aeabi_read_tp"))
521 /* If we run against a stripped glibc, we may be unable to identify
522 special functions by name. Check for one important case,
523 __aeabi_read_tp, by comparing the *code* against the default
524 implementation (this is hand-written ARM assembler in glibc). */
527 && read_memory_unsigned_integer (pc
, 4, byte_order_for_code
)
528 == 0xe3e00a0f /* mov r0, #0xffff0fff */
529 && read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
)
530 == 0xe240f01f) /* sub pc, r0, #31 */
537 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
538 the first 16-bit of instruction, and INSN2 is the second 16-bit of
540 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
541 ((bits ((insn1), 0, 3) << 12) \
542 | (bits ((insn1), 10, 10) << 11) \
543 | (bits ((insn2), 12, 14) << 8) \
544 | bits ((insn2), 0, 7))
546 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
547 the 32-bit instruction. */
548 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
549 ((bits ((insn), 16, 19) << 12) \
550 | bits ((insn), 0, 11))
552 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
555 thumb_expand_immediate (unsigned int imm
)
557 unsigned int count
= imm
>> 7;
565 return (imm
& 0xff) | ((imm
& 0xff) << 16);
567 return ((imm
& 0xff) << 8) | ((imm
& 0xff) << 24);
569 return (imm
& 0xff) | ((imm
& 0xff) << 8)
570 | ((imm
& 0xff) << 16) | ((imm
& 0xff) << 24);
573 return (0x80 | (imm
& 0x7f)) << (32 - count
);
576 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
577 epilogue, 0 otherwise. */
580 thumb_instruction_restores_sp (unsigned short insn
)
582 return (insn
== 0x46bd /* mov sp, r7 */
583 || (insn
& 0xff80) == 0xb000 /* add sp, imm */
584 || (insn
& 0xfe00) == 0xbc00); /* pop <registers> */
587 /* Analyze a Thumb prologue, looking for a recognizable stack frame
588 and frame pointer. Scan until we encounter a store that could
589 clobber the stack frame unexpectedly, or an unknown instruction.
590 Return the last address which is definitely safe to skip for an
591 initial breakpoint. */
594 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
595 CORE_ADDR start
, CORE_ADDR limit
,
596 struct arm_prologue_cache
*cache
)
598 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
599 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
602 struct pv_area
*stack
;
603 struct cleanup
*back_to
;
605 CORE_ADDR unrecognized_pc
= 0;
607 for (i
= 0; i
< 16; i
++)
608 regs
[i
] = pv_register (i
, 0);
609 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
610 back_to
= make_cleanup_free_pv_area (stack
);
612 while (start
< limit
)
616 insn
= read_memory_unsigned_integer (start
, 2, byte_order_for_code
);
618 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
623 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
626 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
627 whether to save LR (R14). */
628 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
630 /* Calculate offsets of saved R0-R7 and LR. */
631 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
632 if (mask
& (1 << regno
))
634 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
636 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
639 else if ((insn
& 0xff80) == 0xb080) /* sub sp, #imm */
641 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
642 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
645 else if (thumb_instruction_restores_sp (insn
))
647 /* Don't scan past the epilogue. */
650 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
651 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
653 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
654 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
655 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
657 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
658 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
659 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
661 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
662 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
663 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
664 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
665 regs
[bits (insn
, 6, 8)]);
666 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
667 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
669 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
670 int rm
= bits (insn
, 3, 6);
671 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
673 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
675 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
676 int src_reg
= (insn
& 0x78) >> 3;
677 regs
[dst_reg
] = regs
[src_reg
];
679 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
681 /* Handle stores to the stack. Normally pushes are used,
682 but with GCC -mtpcs-frame, there may be other stores
683 in the prologue to create the frame. */
684 int regno
= (insn
>> 8) & 0x7;
687 offset
= (insn
& 0xff) << 2;
688 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
690 if (pv_area_store_would_trash (stack
, addr
))
693 pv_area_store (stack
, addr
, 4, regs
[regno
]);
695 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
697 int rd
= bits (insn
, 0, 2);
698 int rn
= bits (insn
, 3, 5);
701 offset
= bits (insn
, 6, 10) << 2;
702 addr
= pv_add_constant (regs
[rn
], offset
);
704 if (pv_area_store_would_trash (stack
, addr
))
707 pv_area_store (stack
, addr
, 4, regs
[rd
]);
709 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
710 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
711 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
712 /* Ignore stores of argument registers to the stack. */
714 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
715 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
716 /* Ignore block loads from the stack, potentially copying
717 parameters from memory. */
719 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
720 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
721 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
722 /* Similarly ignore single loads from the stack. */
724 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
725 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
726 /* Skip register copies, i.e. saves to another register
727 instead of the stack. */
729 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
730 /* Recognize constant loads; even with small stacks these are necessary
732 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
733 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
735 /* Constant pool loads, for the same reason. */
736 unsigned int constant
;
739 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
740 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
741 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
743 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instructions. */
745 unsigned short inst2
;
747 inst2
= read_memory_unsigned_integer (start
+ 2, 2,
748 byte_order_for_code
);
750 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
752 /* BL, BLX. Allow some special function calls when
753 skipping the prologue; GCC generates these before
754 storing arguments to the stack. */
756 int j1
, j2
, imm1
, imm2
;
758 imm1
= sbits (insn
, 0, 10);
759 imm2
= bits (inst2
, 0, 10);
760 j1
= bit (inst2
, 13);
761 j2
= bit (inst2
, 11);
763 offset
= ((imm1
<< 12) + (imm2
<< 1));
764 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
766 nextpc
= start
+ 4 + offset
;
767 /* For BLX make sure to clear the low bits. */
768 if (bit (inst2
, 12) == 0)
769 nextpc
= nextpc
& 0xfffffffc;
771 if (!skip_prologue_function (gdbarch
, nextpc
,
772 bit (inst2
, 12) != 0))
776 else if ((insn
& 0xffd0) == 0xe900 /* stmdb Rn{!},
778 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
780 pv_t addr
= regs
[bits (insn
, 0, 3)];
783 if (pv_area_store_would_trash (stack
, addr
))
786 /* Calculate offsets of saved registers. */
787 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
788 if (inst2
& (1 << regno
))
790 addr
= pv_add_constant (addr
, -4);
791 pv_area_store (stack
, addr
, 4, regs
[regno
]);
795 regs
[bits (insn
, 0, 3)] = addr
;
798 else if ((insn
& 0xff50) == 0xe940 /* strd Rt, Rt2,
800 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
802 int regno1
= bits (inst2
, 12, 15);
803 int regno2
= bits (inst2
, 8, 11);
804 pv_t addr
= regs
[bits (insn
, 0, 3)];
806 offset
= inst2
& 0xff;
808 addr
= pv_add_constant (addr
, offset
);
810 addr
= pv_add_constant (addr
, -offset
);
812 if (pv_area_store_would_trash (stack
, addr
))
815 pv_area_store (stack
, addr
, 4, regs
[regno1
]);
816 pv_area_store (stack
, pv_add_constant (addr
, 4),
820 regs
[bits (insn
, 0, 3)] = addr
;
823 else if ((insn
& 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
824 && (inst2
& 0x0c00) == 0x0c00
825 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
827 int regno
= bits (inst2
, 12, 15);
828 pv_t addr
= regs
[bits (insn
, 0, 3)];
830 offset
= inst2
& 0xff;
832 addr
= pv_add_constant (addr
, offset
);
834 addr
= pv_add_constant (addr
, -offset
);
836 if (pv_area_store_would_trash (stack
, addr
))
839 pv_area_store (stack
, addr
, 4, regs
[regno
]);
842 regs
[bits (insn
, 0, 3)] = addr
;
845 else if ((insn
& 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
846 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
848 int regno
= bits (inst2
, 12, 15);
851 offset
= inst2
& 0xfff;
852 addr
= pv_add_constant (regs
[bits (insn
, 0, 3)], offset
);
854 if (pv_area_store_would_trash (stack
, addr
))
857 pv_area_store (stack
, addr
, 4, regs
[regno
]);
860 else if ((insn
& 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
861 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
862 /* Ignore stores of argument registers to the stack. */
865 else if ((insn
& 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
866 && (inst2
& 0x0d00) == 0x0c00
867 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
868 /* Ignore stores of argument registers to the stack. */
871 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!],
873 && (inst2
& 0x8000) == 0x0000
874 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
875 /* Ignore block loads from the stack, potentially copying
876 parameters from memory. */
879 else if ((insn
& 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
881 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
882 /* Similarly ignore dual loads from the stack. */
885 else if ((insn
& 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
886 && (inst2
& 0x0d00) == 0x0c00
887 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
888 /* Similarly ignore single loads from the stack. */
891 else if ((insn
& 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
892 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
893 /* Similarly ignore single loads from the stack. */
896 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
897 && (inst2
& 0x8000) == 0x0000)
899 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
900 | (bits (inst2
, 12, 14) << 8)
901 | bits (inst2
, 0, 7));
903 regs
[bits (inst2
, 8, 11)]
904 = pv_add_constant (regs
[bits (insn
, 0, 3)],
905 thumb_expand_immediate (imm
));
908 else if ((insn
& 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
909 && (inst2
& 0x8000) == 0x0000)
911 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
912 | (bits (inst2
, 12, 14) << 8)
913 | bits (inst2
, 0, 7));
915 regs
[bits (inst2
, 8, 11)]
916 = pv_add_constant (regs
[bits (insn
, 0, 3)], imm
);
919 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
920 && (inst2
& 0x8000) == 0x0000)
922 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
923 | (bits (inst2
, 12, 14) << 8)
924 | bits (inst2
, 0, 7));
926 regs
[bits (inst2
, 8, 11)]
927 = pv_add_constant (regs
[bits (insn
, 0, 3)],
928 - (CORE_ADDR
) thumb_expand_immediate (imm
));
931 else if ((insn
& 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
932 && (inst2
& 0x8000) == 0x0000)
934 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
935 | (bits (inst2
, 12, 14) << 8)
936 | bits (inst2
, 0, 7));
938 regs
[bits (inst2
, 8, 11)]
939 = pv_add_constant (regs
[bits (insn
, 0, 3)], - (CORE_ADDR
) imm
);
942 else if ((insn
& 0xfbff) == 0xf04f) /* mov.w Rd, #const */
944 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
945 | (bits (inst2
, 12, 14) << 8)
946 | bits (inst2
, 0, 7));
948 regs
[bits (inst2
, 8, 11)]
949 = pv_constant (thumb_expand_immediate (imm
));
952 else if ((insn
& 0xfbf0) == 0xf240) /* movw Rd, #const */
955 = EXTRACT_MOVW_MOVT_IMM_T (insn
, inst2
);
957 regs
[bits (inst2
, 8, 11)] = pv_constant (imm
);
960 else if (insn
== 0xea5f /* mov.w Rd,Rm */
961 && (inst2
& 0xf0f0) == 0)
963 int dst_reg
= (inst2
& 0x0f00) >> 8;
964 int src_reg
= inst2
& 0xf;
965 regs
[dst_reg
] = regs
[src_reg
];
968 else if ((insn
& 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
970 /* Constant pool loads. */
971 unsigned int constant
;
974 offset
= bits (inst2
, 0, 11);
976 loc
= start
+ 4 + offset
;
978 loc
= start
+ 4 - offset
;
980 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
981 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
984 else if ((insn
& 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
986 /* Constant pool loads. */
987 unsigned int constant
;
990 offset
= bits (inst2
, 0, 7) << 2;
992 loc
= start
+ 4 + offset
;
994 loc
= start
+ 4 - offset
;
996 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
997 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
999 constant
= read_memory_unsigned_integer (loc
+ 4, 4, byte_order
);
1000 regs
[bits (inst2
, 8, 11)] = pv_constant (constant
);
1003 else if (thumb2_instruction_changes_pc (insn
, inst2
))
1005 /* Don't scan past anything that might change control flow. */
1010 /* The optimizer might shove anything into the prologue,
1011 so we just skip what we don't recognize. */
1012 unrecognized_pc
= start
;
1017 else if (thumb_instruction_changes_pc (insn
))
1019 /* Don't scan past anything that might change control flow. */
1024 /* The optimizer might shove anything into the prologue,
1025 so we just skip what we don't recognize. */
1026 unrecognized_pc
= start
;
1033 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1034 paddress (gdbarch
, start
));
1036 if (unrecognized_pc
== 0)
1037 unrecognized_pc
= start
;
1041 do_cleanups (back_to
);
1042 return unrecognized_pc
;
1045 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1047 /* Frame pointer is fp. Frame size is constant. */
1048 cache
->framereg
= ARM_FP_REGNUM
;
1049 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1051 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
1053 /* Frame pointer is r7. Frame size is constant. */
1054 cache
->framereg
= THUMB_FP_REGNUM
;
1055 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
1059 /* Try the stack pointer... this is a bit desperate. */
1060 cache
->framereg
= ARM_SP_REGNUM
;
1061 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1064 for (i
= 0; i
< 16; i
++)
1065 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
1066 cache
->saved_regs
[i
].addr
= offset
;
1068 do_cleanups (back_to
);
1069 return unrecognized_pc
;
1073 /* Try to analyze the instructions starting from PC, which load symbol
1074 __stack_chk_guard. Return the address of instruction after loading this
1075 symbol, set the dest register number to *BASEREG, and set the size of
1076 instructions for loading symbol in OFFSET. Return 0 if instructions are
1080 arm_analyze_load_stack_chk_guard(CORE_ADDR pc
, struct gdbarch
*gdbarch
,
1081 unsigned int *destreg
, int *offset
)
1083 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1084 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1085 unsigned int low
, high
, address
;
1090 unsigned short insn1
1091 = read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
1093 if ((insn1
& 0xf800) == 0x4800) /* ldr Rd, #immed */
1095 *destreg
= bits (insn1
, 8, 10);
1097 address
= (pc
& 0xfffffffc) + 4 + (bits (insn1
, 0, 7) << 2);
1098 address
= read_memory_unsigned_integer (address
, 4,
1099 byte_order_for_code
);
1101 else if ((insn1
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1103 unsigned short insn2
1104 = read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1106 low
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1109 = read_memory_unsigned_integer (pc
+ 4, 2, byte_order_for_code
);
1111 = read_memory_unsigned_integer (pc
+ 6, 2, byte_order_for_code
);
1113 /* movt Rd, #const */
1114 if ((insn1
& 0xfbc0) == 0xf2c0)
1116 high
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1117 *destreg
= bits (insn2
, 8, 11);
1119 address
= (high
<< 16 | low
);
1126 = read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
1128 if ((insn
& 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1130 address
= bits (insn
, 0, 11) + pc
+ 8;
1131 address
= read_memory_unsigned_integer (address
, 4,
1132 byte_order_for_code
);
1134 *destreg
= bits (insn
, 12, 15);
1137 else if ((insn
& 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1139 low
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1142 = read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
);
1144 if ((insn
& 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1146 high
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1147 *destreg
= bits (insn
, 12, 15);
1149 address
= (high
<< 16 | low
);
1157 /* Try to skip a sequence of instructions used for stack protector. If PC
1158 points to the first instruction of this sequence, return the address of
1159 first instruction after this sequence, otherwise, return original PC.
1161 On arm, this sequence of instructions is composed of mainly three steps,
1162 Step 1: load symbol __stack_chk_guard,
1163 Step 2: load from address of __stack_chk_guard,
1164 Step 3: store it to somewhere else.
1166 Usually, instructions on step 2 and step 3 are the same on various ARM
1167 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1168 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1169 instructions in step 1 vary from different ARM architectures. On ARMv7,
1172 movw Rn, #:lower16:__stack_chk_guard
1173 movt Rn, #:upper16:__stack_chk_guard
1180 .word __stack_chk_guard
1182 Since ldr/str is a very popular instruction, we can't use them as
1183 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1184 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1185 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1188 arm_skip_stack_protector(CORE_ADDR pc
, struct gdbarch
*gdbarch
)
1190 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1191 unsigned int basereg
;
1192 struct bound_minimal_symbol stack_chk_guard
;
1194 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1197 /* Try to parse the instructions in Step 1. */
1198 addr
= arm_analyze_load_stack_chk_guard (pc
, gdbarch
,
1203 stack_chk_guard
= lookup_minimal_symbol_by_pc (addr
);
1204 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1205 Otherwise, this sequence cannot be for stack protector. */
1206 if (stack_chk_guard
.minsym
== NULL
1207 || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard
.minsym
), "__stack_chk_guard"))
1212 unsigned int destreg
;
1214 = read_memory_unsigned_integer (pc
+ offset
, 2, byte_order_for_code
);
1216 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1217 if ((insn
& 0xf800) != 0x6800)
1219 if (bits (insn
, 3, 5) != basereg
)
1221 destreg
= bits (insn
, 0, 2);
1223 insn
= read_memory_unsigned_integer (pc
+ offset
+ 2, 2,
1224 byte_order_for_code
);
1225 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1226 if ((insn
& 0xf800) != 0x6000)
1228 if (destreg
!= bits (insn
, 0, 2))
1233 unsigned int destreg
;
1235 = read_memory_unsigned_integer (pc
+ offset
, 4, byte_order_for_code
);
1237 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1238 if ((insn
& 0x0e500000) != 0x04100000)
1240 if (bits (insn
, 16, 19) != basereg
)
1242 destreg
= bits (insn
, 12, 15);
1243 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1244 insn
= read_memory_unsigned_integer (pc
+ offset
+ 4,
1245 4, byte_order_for_code
);
1246 if ((insn
& 0x0e500000) != 0x04000000)
1248 if (bits (insn
, 12, 15) != destreg
)
1251 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1254 return pc
+ offset
+ 4;
1256 return pc
+ offset
+ 8;
1259 /* Advance the PC across any function entry prologue instructions to
1260 reach some "real" code.
1262 The APCS (ARM Procedure Call Standard) defines the following
1266 [stmfd sp!, {a1,a2,a3,a4}]
1267 stmfd sp!, {...,fp,ip,lr,pc}
1268 [stfe f7, [sp, #-12]!]
1269 [stfe f6, [sp, #-12]!]
1270 [stfe f5, [sp, #-12]!]
1271 [stfe f4, [sp, #-12]!]
1272 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1275 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1277 CORE_ADDR func_addr
, limit_pc
;
1279 /* See if we can determine the end of the prologue via the symbol table.
1280 If so, then return either PC, or the PC after the prologue, whichever
1282 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1284 CORE_ADDR post_prologue_pc
1285 = skip_prologue_using_sal (gdbarch
, func_addr
);
1286 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1288 if (post_prologue_pc
)
1290 = arm_skip_stack_protector (post_prologue_pc
, gdbarch
);
1293 /* GCC always emits a line note before the prologue and another
1294 one after, even if the two are at the same address or on the
1295 same line. Take advantage of this so that we do not need to
1296 know every instruction that might appear in the prologue. We
1297 will have producer information for most binaries; if it is
1298 missing (e.g. for -gstabs), assuming the GNU tools. */
1299 if (post_prologue_pc
1301 || COMPUNIT_PRODUCER (cust
) == NULL
1302 || startswith (COMPUNIT_PRODUCER (cust
), "GNU ")
1303 || startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
1304 return post_prologue_pc
;
1306 if (post_prologue_pc
!= 0)
1308 CORE_ADDR analyzed_limit
;
1310 /* For non-GCC compilers, make sure the entire line is an
1311 acceptable prologue; GDB will round this function's
1312 return value up to the end of the following line so we
1313 can not skip just part of a line (and we do not want to).
1315 RealView does not treat the prologue specially, but does
1316 associate prologue code with the opening brace; so this
1317 lets us skip the first line if we think it is the opening
1319 if (arm_pc_is_thumb (gdbarch
, func_addr
))
1320 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
1321 post_prologue_pc
, NULL
);
1323 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
1324 post_prologue_pc
, NULL
);
1326 if (analyzed_limit
!= post_prologue_pc
)
1329 return post_prologue_pc
;
1333 /* Can't determine prologue from the symbol table, need to examine
1336 /* Find an upper limit on the function prologue using the debug
1337 information. If the debug information could not be used to provide
1338 that bound, then use an arbitrary large number as the upper bound. */
1339 /* Like arm_scan_prologue, stop no later than pc + 64. */
1340 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1342 limit_pc
= pc
+ 64; /* Magic. */
1345 /* Check if this is Thumb code. */
1346 if (arm_pc_is_thumb (gdbarch
, pc
))
1347 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1349 return arm_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1353 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1354 This function decodes a Thumb function prologue to determine:
1355 1) the size of the stack frame
1356 2) which registers are saved on it
1357 3) the offsets of saved regs
1358 4) the offset from the stack pointer to the frame pointer
1360 A typical Thumb function prologue would create this stack frame
1361 (offsets relative to FP)
1362 old SP -> 24 stack parameters
1365 R7 -> 0 local variables (16 bytes)
1366 SP -> -12 additional stack space (12 bytes)
1367 The frame size would thus be 36 bytes, and the frame offset would be
1368 12 bytes. The frame register is R7.
1370 The comments for thumb_skip_prolog() describe the algorithm we use
1371 to detect the end of the prolog. */
1375 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
1376 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
1378 CORE_ADDR prologue_start
;
1379 CORE_ADDR prologue_end
;
1381 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1384 /* See comment in arm_scan_prologue for an explanation of
1386 if (prologue_end
> prologue_start
+ 64)
1388 prologue_end
= prologue_start
+ 64;
1392 /* We're in the boondocks: we have no idea where the start of the
1396 prologue_end
= min (prologue_end
, prev_pc
);
1398 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1401 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1405 arm_instruction_restores_sp (unsigned int insn
)
1407 if (bits (insn
, 28, 31) != INST_NV
)
1409 if ((insn
& 0x0df0f000) == 0x0080d000
1410 /* ADD SP (register or immediate). */
1411 || (insn
& 0x0df0f000) == 0x0040d000
1412 /* SUB SP (register or immediate). */
1413 || (insn
& 0x0ffffff0) == 0x01a0d000
1415 || (insn
& 0x0fff0000) == 0x08bd0000
1417 || (insn
& 0x0fff0000) == 0x049d0000)
1418 /* POP of a single register. */
1425 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1426 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1427 fill it in. Return the first address not recognized as a prologue
1430 We recognize all the instructions typically found in ARM prologues,
1431 plus harmless instructions which can be skipped (either for analysis
1432 purposes, or a more restrictive set that can be skipped when finding
1433 the end of the prologue). */
1436 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1437 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1438 struct arm_prologue_cache
*cache
)
1440 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1442 CORE_ADDR offset
, current_pc
;
1443 pv_t regs
[ARM_FPS_REGNUM
];
1444 struct pv_area
*stack
;
1445 struct cleanup
*back_to
;
1446 CORE_ADDR unrecognized_pc
= 0;
1448 /* Search the prologue looking for instructions that set up the
1449 frame pointer, adjust the stack pointer, and save registers.
1451 Be careful, however, and if it doesn't look like a prologue,
1452 don't try to scan it. If, for instance, a frameless function
1453 begins with stmfd sp!, then we will tell ourselves there is
1454 a frame, which will confuse stack traceback, as well as "finish"
1455 and other operations that rely on a knowledge of the stack
1458 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1459 regs
[regno
] = pv_register (regno
, 0);
1460 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1461 back_to
= make_cleanup_free_pv_area (stack
);
1463 for (current_pc
= prologue_start
;
1464 current_pc
< prologue_end
;
1468 = read_memory_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1470 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1472 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1475 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1476 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1478 unsigned imm
= insn
& 0xff; /* immediate value */
1479 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1480 int rd
= bits (insn
, 12, 15);
1481 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1482 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1485 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1486 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1488 unsigned imm
= insn
& 0xff; /* immediate value */
1489 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1490 int rd
= bits (insn
, 12, 15);
1491 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1492 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1495 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd,
1498 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1500 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1501 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4,
1502 regs
[bits (insn
, 12, 15)]);
1505 else if ((insn
& 0xffff0000) == 0xe92d0000)
1506 /* stmfd sp!, {..., fp, ip, lr, pc}
1508 stmfd sp!, {a1, a2, a3, a4} */
1510 int mask
= insn
& 0xffff;
1512 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1515 /* Calculate offsets of saved registers. */
1516 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1517 if (mask
& (1 << regno
))
1520 = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1521 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1524 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1525 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1526 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1528 /* No need to add this to saved_regs -- it's just an arg reg. */
1531 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1532 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1533 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1535 /* No need to add this to saved_regs -- it's just an arg reg. */
1538 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn,
1540 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1542 /* No need to add this to saved_regs -- it's just arg regs. */
1545 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1547 unsigned imm
= insn
& 0xff; /* immediate value */
1548 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1549 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1550 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1552 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1554 unsigned imm
= insn
& 0xff; /* immediate value */
1555 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1556 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1557 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1559 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?,
1561 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1563 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1566 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1567 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1568 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1570 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1572 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1574 int n_saved_fp_regs
;
1575 unsigned int fp_start_reg
, fp_bound_reg
;
1577 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1580 if ((insn
& 0x800) == 0x800) /* N0 is set */
1582 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1583 n_saved_fp_regs
= 3;
1585 n_saved_fp_regs
= 1;
1589 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1590 n_saved_fp_regs
= 2;
1592 n_saved_fp_regs
= 4;
1595 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1596 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1597 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1599 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1600 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
1601 regs
[fp_start_reg
++]);
1604 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1606 /* Allow some special function calls when skipping the
1607 prologue; GCC generates these before storing arguments to
1609 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1611 if (skip_prologue_function (gdbarch
, dest
, 0))
1616 else if ((insn
& 0xf0000000) != 0xe0000000)
1617 break; /* Condition not true, exit early. */
1618 else if (arm_instruction_changes_pc (insn
))
1619 /* Don't scan past anything that might change control flow. */
1621 else if (arm_instruction_restores_sp (insn
))
1623 /* Don't scan past the epilogue. */
1626 else if ((insn
& 0xfe500000) == 0xe8100000 /* ldm */
1627 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1628 /* Ignore block loads from the stack, potentially copying
1629 parameters from memory. */
1631 else if ((insn
& 0xfc500000) == 0xe4100000
1632 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1633 /* Similarly ignore single loads from the stack. */
1635 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1636 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1637 register instead of the stack. */
1641 /* The optimizer might shove anything into the prologue, if
1642 we build up cache (cache != NULL) from scanning prologue,
1643 we just skip what we don't recognize and scan further to
1644 make cache as complete as possible. However, if we skip
1645 prologue, we'll stop immediately on unrecognized
1647 unrecognized_pc
= current_pc
;
1655 if (unrecognized_pc
== 0)
1656 unrecognized_pc
= current_pc
;
1660 int framereg
, framesize
;
1662 /* The frame size is just the distance from the frame register
1663 to the original stack pointer. */
1664 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1666 /* Frame pointer is fp. */
1667 framereg
= ARM_FP_REGNUM
;
1668 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1672 /* Try the stack pointer... this is a bit desperate. */
1673 framereg
= ARM_SP_REGNUM
;
1674 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1677 cache
->framereg
= framereg
;
1678 cache
->framesize
= framesize
;
1680 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1681 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1682 cache
->saved_regs
[regno
].addr
= offset
;
1686 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1687 paddress (gdbarch
, unrecognized_pc
));
1689 do_cleanups (back_to
);
1690 return unrecognized_pc
;
1694 arm_scan_prologue (struct frame_info
*this_frame
,
1695 struct arm_prologue_cache
*cache
)
1697 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1698 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1699 CORE_ADDR prologue_start
, prologue_end
;
1700 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1701 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1703 /* Assume there is no frame until proven otherwise. */
1704 cache
->framereg
= ARM_SP_REGNUM
;
1705 cache
->framesize
= 0;
1707 /* Check for Thumb prologue. */
1708 if (arm_frame_is_thumb (this_frame
))
1710 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1714 /* Find the function prologue. If we can't find the function in
1715 the symbol table, peek in the stack frame to find the PC. */
1716 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1719 /* One way to find the end of the prologue (which works well
1720 for unoptimized code) is to do the following:
1722 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1725 prologue_end = prev_pc;
1726 else if (sal.end < prologue_end)
1727 prologue_end = sal.end;
1729 This mechanism is very accurate so long as the optimizer
1730 doesn't move any instructions from the function body into the
1731 prologue. If this happens, sal.end will be the last
1732 instruction in the first hunk of prologue code just before
1733 the first instruction that the scheduler has moved from
1734 the body to the prologue.
1736 In order to make sure that we scan all of the prologue
1737 instructions, we use a slightly less accurate mechanism which
1738 may scan more than necessary. To help compensate for this
1739 lack of accuracy, the prologue scanning loop below contains
1740 several clauses which'll cause the loop to terminate early if
1741 an implausible prologue instruction is encountered.
1747 is a suitable endpoint since it accounts for the largest
1748 possible prologue plus up to five instructions inserted by
1751 if (prologue_end
> prologue_start
+ 64)
1753 prologue_end
= prologue_start
+ 64; /* See above. */
1758 /* We have no symbol information. Our only option is to assume this
1759 function has a standard stack frame and the normal frame register.
1760 Then, we can find the value of our frame pointer on entrance to
1761 the callee (or at the present moment if this is the innermost frame).
1762 The value stored there should be the address of the stmfd + 8. */
1763 CORE_ADDR frame_loc
;
1764 LONGEST return_value
;
1766 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
1767 if (!safe_read_memory_integer (frame_loc
, 4, byte_order
, &return_value
))
1771 prologue_start
= gdbarch_addr_bits_remove
1772 (gdbarch
, return_value
) - 8;
1773 prologue_end
= prologue_start
+ 64; /* See above. */
1777 if (prev_pc
< prologue_end
)
1778 prologue_end
= prev_pc
;
1780 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1783 static struct arm_prologue_cache
*
1784 arm_make_prologue_cache (struct frame_info
*this_frame
)
1787 struct arm_prologue_cache
*cache
;
1788 CORE_ADDR unwound_fp
;
1790 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1791 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1793 arm_scan_prologue (this_frame
, cache
);
1795 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
1796 if (unwound_fp
== 0)
1799 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
1801 /* Calculate actual addresses of saved registers using offsets
1802 determined by arm_scan_prologue. */
1803 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
1804 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
1805 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
1810 /* Implementation of the stop_reason hook for arm_prologue frames. */
1812 static enum unwind_stop_reason
1813 arm_prologue_unwind_stop_reason (struct frame_info
*this_frame
,
1816 struct arm_prologue_cache
*cache
;
1819 if (*this_cache
== NULL
)
1820 *this_cache
= arm_make_prologue_cache (this_frame
);
1821 cache
= (struct arm_prologue_cache
*) *this_cache
;
1823 /* This is meant to halt the backtrace at "_start". */
1824 pc
= get_frame_pc (this_frame
);
1825 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1826 return UNWIND_OUTERMOST
;
1828 /* If we've hit a wall, stop. */
1829 if (cache
->prev_sp
== 0)
1830 return UNWIND_OUTERMOST
;
1832 return UNWIND_NO_REASON
;
1835 /* Our frame ID for a normal frame is the current function's starting PC
1836 and the caller's SP when we were called. */
1839 arm_prologue_this_id (struct frame_info
*this_frame
,
1841 struct frame_id
*this_id
)
1843 struct arm_prologue_cache
*cache
;
1847 if (*this_cache
== NULL
)
1848 *this_cache
= arm_make_prologue_cache (this_frame
);
1849 cache
= (struct arm_prologue_cache
*) *this_cache
;
1851 /* Use function start address as part of the frame ID. If we cannot
1852 identify the start address (due to missing symbol information),
1853 fall back to just using the current PC. */
1854 pc
= get_frame_pc (this_frame
);
1855 func
= get_frame_func (this_frame
);
1859 id
= frame_id_build (cache
->prev_sp
, func
);
1863 static struct value
*
1864 arm_prologue_prev_register (struct frame_info
*this_frame
,
1868 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1869 struct arm_prologue_cache
*cache
;
1871 if (*this_cache
== NULL
)
1872 *this_cache
= arm_make_prologue_cache (this_frame
);
1873 cache
= (struct arm_prologue_cache
*) *this_cache
;
1875 /* If we are asked to unwind the PC, then we need to return the LR
1876 instead. The prologue may save PC, but it will point into this
1877 frame's prologue, not the next frame's resume location. Also
1878 strip the saved T bit. A valid LR may have the low bit set, but
1879 a valid PC never does. */
1880 if (prev_regnum
== ARM_PC_REGNUM
)
1884 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1885 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1886 arm_addr_bits_remove (gdbarch
, lr
));
1889 /* SP is generally not saved to the stack, but this frame is
1890 identified by the next frame's stack pointer at the time of the call.
1891 The value was already reconstructed into PREV_SP. */
1892 if (prev_regnum
== ARM_SP_REGNUM
)
1893 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1895 /* The CPSR may have been changed by the call instruction and by the
1896 called function. The only bit we can reconstruct is the T bit,
1897 by checking the low bit of LR as of the call. This is a reliable
1898 indicator of Thumb-ness except for some ARM v4T pre-interworking
1899 Thumb code, which could get away with a clear low bit as long as
1900 the called function did not use bx. Guess that all other
1901 bits are unchanged; the condition flags are presumably lost,
1902 but the processor status is likely valid. */
1903 if (prev_regnum
== ARM_PS_REGNUM
)
1906 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
1908 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1909 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1910 if (IS_THUMB_ADDR (lr
))
1914 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1917 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1921 struct frame_unwind arm_prologue_unwind
= {
1923 arm_prologue_unwind_stop_reason
,
1924 arm_prologue_this_id
,
1925 arm_prologue_prev_register
,
1927 default_frame_sniffer
1930 /* Maintain a list of ARM exception table entries per objfile, similar to the
1931 list of mapping symbols. We only cache entries for standard ARM-defined
1932 personality routines; the cache will contain only the frame unwinding
1933 instructions associated with the entry (not the descriptors). */
1935 static const struct objfile_data
*arm_exidx_data_key
;
1937 struct arm_exidx_entry
1942 typedef struct arm_exidx_entry arm_exidx_entry_s
;
1943 DEF_VEC_O(arm_exidx_entry_s
);
1945 struct arm_exidx_data
1947 VEC(arm_exidx_entry_s
) **section_maps
;
1951 arm_exidx_data_free (struct objfile
*objfile
, void *arg
)
1953 struct arm_exidx_data
*data
= (struct arm_exidx_data
*) arg
;
1956 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
1957 VEC_free (arm_exidx_entry_s
, data
->section_maps
[i
]);
1961 arm_compare_exidx_entries (const struct arm_exidx_entry
*lhs
,
1962 const struct arm_exidx_entry
*rhs
)
1964 return lhs
->addr
< rhs
->addr
;
1967 static struct obj_section
*
1968 arm_obj_section_from_vma (struct objfile
*objfile
, bfd_vma vma
)
1970 struct obj_section
*osect
;
1972 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
1973 if (bfd_get_section_flags (objfile
->obfd
,
1974 osect
->the_bfd_section
) & SEC_ALLOC
)
1976 bfd_vma start
, size
;
1977 start
= bfd_get_section_vma (objfile
->obfd
, osect
->the_bfd_section
);
1978 size
= bfd_get_section_size (osect
->the_bfd_section
);
1980 if (start
<= vma
&& vma
< start
+ size
)
1987 /* Parse contents of exception table and exception index sections
1988 of OBJFILE, and fill in the exception table entry cache.
1990 For each entry that refers to a standard ARM-defined personality
1991 routine, extract the frame unwinding instructions (from either
1992 the index or the table section). The unwinding instructions
1994 - extracting them from the rest of the table data
1995 - converting to host endianness
1996 - appending the implicit 0xb0 ("Finish") code
1998 The extracted and normalized instructions are stored for later
1999 retrieval by the arm_find_exidx_entry routine. */
2002 arm_exidx_new_objfile (struct objfile
*objfile
)
2004 struct cleanup
*cleanups
;
2005 struct arm_exidx_data
*data
;
2006 asection
*exidx
, *extab
;
2007 bfd_vma exidx_vma
= 0, extab_vma
= 0;
2008 bfd_size_type exidx_size
= 0, extab_size
= 0;
2009 gdb_byte
*exidx_data
= NULL
, *extab_data
= NULL
;
2012 /* If we've already touched this file, do nothing. */
2013 if (!objfile
|| objfile_data (objfile
, arm_exidx_data_key
) != NULL
)
2015 cleanups
= make_cleanup (null_cleanup
, NULL
);
2017 /* Read contents of exception table and index. */
2018 exidx
= bfd_get_section_by_name (objfile
->obfd
, ELF_STRING_ARM_unwind
);
2021 exidx_vma
= bfd_section_vma (objfile
->obfd
, exidx
);
2022 exidx_size
= bfd_get_section_size (exidx
);
2023 exidx_data
= (gdb_byte
*) xmalloc (exidx_size
);
2024 make_cleanup (xfree
, exidx_data
);
2026 if (!bfd_get_section_contents (objfile
->obfd
, exidx
,
2027 exidx_data
, 0, exidx_size
))
2029 do_cleanups (cleanups
);
2034 extab
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.extab");
2037 extab_vma
= bfd_section_vma (objfile
->obfd
, extab
);
2038 extab_size
= bfd_get_section_size (extab
);
2039 extab_data
= (gdb_byte
*) xmalloc (extab_size
);
2040 make_cleanup (xfree
, extab_data
);
2042 if (!bfd_get_section_contents (objfile
->obfd
, extab
,
2043 extab_data
, 0, extab_size
))
2045 do_cleanups (cleanups
);
2050 /* Allocate exception table data structure. */
2051 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
, struct arm_exidx_data
);
2052 set_objfile_data (objfile
, arm_exidx_data_key
, data
);
2053 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2054 objfile
->obfd
->section_count
,
2055 VEC(arm_exidx_entry_s
) *);
2057 /* Fill in exception table. */
2058 for (i
= 0; i
< exidx_size
/ 8; i
++)
2060 struct arm_exidx_entry new_exidx_entry
;
2061 bfd_vma idx
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8);
2062 bfd_vma val
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8 + 4);
2063 bfd_vma addr
= 0, word
= 0;
2064 int n_bytes
= 0, n_words
= 0;
2065 struct obj_section
*sec
;
2066 gdb_byte
*entry
= NULL
;
2068 /* Extract address of start of function. */
2069 idx
= ((idx
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2070 idx
+= exidx_vma
+ i
* 8;
2072 /* Find section containing function and compute section offset. */
2073 sec
= arm_obj_section_from_vma (objfile
, idx
);
2076 idx
-= bfd_get_section_vma (objfile
->obfd
, sec
->the_bfd_section
);
2078 /* Determine address of exception table entry. */
2081 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2083 else if ((val
& 0xff000000) == 0x80000000)
2085 /* Exception table entry embedded in .ARM.exidx
2086 -- must be short form. */
2090 else if (!(val
& 0x80000000))
2092 /* Exception table entry in .ARM.extab. */
2093 addr
= ((val
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2094 addr
+= exidx_vma
+ i
* 8 + 4;
2096 if (addr
>= extab_vma
&& addr
+ 4 <= extab_vma
+ extab_size
)
2098 word
= bfd_h_get_32 (objfile
->obfd
,
2099 extab_data
+ addr
- extab_vma
);
2102 if ((word
& 0xff000000) == 0x80000000)
2107 else if ((word
& 0xff000000) == 0x81000000
2108 || (word
& 0xff000000) == 0x82000000)
2112 n_words
= ((word
>> 16) & 0xff);
2114 else if (!(word
& 0x80000000))
2117 struct obj_section
*pers_sec
;
2118 int gnu_personality
= 0;
2120 /* Custom personality routine. */
2121 pers
= ((word
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2122 pers
= UNMAKE_THUMB_ADDR (pers
+ addr
- 4);
2124 /* Check whether we've got one of the variants of the
2125 GNU personality routines. */
2126 pers_sec
= arm_obj_section_from_vma (objfile
, pers
);
2129 static const char *personality
[] =
2131 "__gcc_personality_v0",
2132 "__gxx_personality_v0",
2133 "__gcj_personality_v0",
2134 "__gnu_objc_personality_v0",
2138 CORE_ADDR pc
= pers
+ obj_section_offset (pers_sec
);
2141 for (k
= 0; personality
[k
]; k
++)
2142 if (lookup_minimal_symbol_by_pc_name
2143 (pc
, personality
[k
], objfile
))
2145 gnu_personality
= 1;
2150 /* If so, the next word contains a word count in the high
2151 byte, followed by the same unwind instructions as the
2152 pre-defined forms. */
2154 && addr
+ 4 <= extab_vma
+ extab_size
)
2156 word
= bfd_h_get_32 (objfile
->obfd
,
2157 extab_data
+ addr
- extab_vma
);
2160 n_words
= ((word
>> 24) & 0xff);
2166 /* Sanity check address. */
2168 if (addr
< extab_vma
|| addr
+ 4 * n_words
> extab_vma
+ extab_size
)
2169 n_words
= n_bytes
= 0;
2171 /* The unwind instructions reside in WORD (only the N_BYTES least
2172 significant bytes are valid), followed by N_WORDS words in the
2173 extab section starting at ADDR. */
2174 if (n_bytes
|| n_words
)
2177 = (gdb_byte
*) obstack_alloc (&objfile
->objfile_obstack
,
2178 n_bytes
+ n_words
* 4 + 1);
2181 *p
++ = (gdb_byte
) ((word
>> (8 * n_bytes
)) & 0xff);
2185 word
= bfd_h_get_32 (objfile
->obfd
,
2186 extab_data
+ addr
- extab_vma
);
2189 *p
++ = (gdb_byte
) ((word
>> 24) & 0xff);
2190 *p
++ = (gdb_byte
) ((word
>> 16) & 0xff);
2191 *p
++ = (gdb_byte
) ((word
>> 8) & 0xff);
2192 *p
++ = (gdb_byte
) (word
& 0xff);
2195 /* Implied "Finish" to terminate the list. */
2199 /* Push entry onto vector. They are guaranteed to always
2200 appear in order of increasing addresses. */
2201 new_exidx_entry
.addr
= idx
;
2202 new_exidx_entry
.entry
= entry
;
2203 VEC_safe_push (arm_exidx_entry_s
,
2204 data
->section_maps
[sec
->the_bfd_section
->index
],
2208 do_cleanups (cleanups
);
2211 /* Search for the exception table entry covering MEMADDR. If one is found,
2212 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2213 set *START to the start of the region covered by this entry. */
2216 arm_find_exidx_entry (CORE_ADDR memaddr
, CORE_ADDR
*start
)
2218 struct obj_section
*sec
;
2220 sec
= find_pc_section (memaddr
);
2223 struct arm_exidx_data
*data
;
2224 VEC(arm_exidx_entry_s
) *map
;
2225 struct arm_exidx_entry map_key
= { memaddr
- obj_section_addr (sec
), 0 };
2228 data
= ((struct arm_exidx_data
*)
2229 objfile_data (sec
->objfile
, arm_exidx_data_key
));
2232 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
2233 if (!VEC_empty (arm_exidx_entry_s
, map
))
2235 struct arm_exidx_entry
*map_sym
;
2237 idx
= VEC_lower_bound (arm_exidx_entry_s
, map
, &map_key
,
2238 arm_compare_exidx_entries
);
2240 /* VEC_lower_bound finds the earliest ordered insertion
2241 point. If the following symbol starts at this exact
2242 address, we use that; otherwise, the preceding
2243 exception table entry covers this address. */
2244 if (idx
< VEC_length (arm_exidx_entry_s
, map
))
2246 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
);
2247 if (map_sym
->addr
== map_key
.addr
)
2250 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2251 return map_sym
->entry
;
2257 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
- 1);
2259 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2260 return map_sym
->entry
;
2269 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2270 instruction list from the ARM exception table entry ENTRY, allocate and
2271 return a prologue cache structure describing how to unwind this frame.
2273 Return NULL if the unwinding instruction list contains a "spare",
2274 "reserved" or "refuse to unwind" instruction as defined in section
2275 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2276 for the ARM Architecture" document. */
2278 static struct arm_prologue_cache
*
2279 arm_exidx_fill_cache (struct frame_info
*this_frame
, gdb_byte
*entry
)
2284 struct arm_prologue_cache
*cache
;
2285 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2286 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2292 /* Whenever we reload SP, we actually have to retrieve its
2293 actual value in the current frame. */
2296 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2298 int reg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2299 vsp
= get_frame_register_unsigned (this_frame
, reg
);
2303 CORE_ADDR addr
= cache
->saved_regs
[ARM_SP_REGNUM
].addr
;
2304 vsp
= get_frame_memory_unsigned (this_frame
, addr
, 4);
2310 /* Decode next unwind instruction. */
2313 if ((insn
& 0xc0) == 0)
2315 int offset
= insn
& 0x3f;
2316 vsp
+= (offset
<< 2) + 4;
2318 else if ((insn
& 0xc0) == 0x40)
2320 int offset
= insn
& 0x3f;
2321 vsp
-= (offset
<< 2) + 4;
2323 else if ((insn
& 0xf0) == 0x80)
2325 int mask
= ((insn
& 0xf) << 8) | *entry
++;
2328 /* The special case of an all-zero mask identifies
2329 "Refuse to unwind". We return NULL to fall back
2330 to the prologue analyzer. */
2334 /* Pop registers r4..r15 under mask. */
2335 for (i
= 0; i
< 12; i
++)
2336 if (mask
& (1 << i
))
2338 cache
->saved_regs
[4 + i
].addr
= vsp
;
2342 /* Special-case popping SP -- we need to reload vsp. */
2343 if (mask
& (1 << (ARM_SP_REGNUM
- 4)))
2346 else if ((insn
& 0xf0) == 0x90)
2348 int reg
= insn
& 0xf;
2350 /* Reserved cases. */
2351 if (reg
== ARM_SP_REGNUM
|| reg
== ARM_PC_REGNUM
)
2354 /* Set SP from another register and mark VSP for reload. */
2355 cache
->saved_regs
[ARM_SP_REGNUM
] = cache
->saved_regs
[reg
];
2358 else if ((insn
& 0xf0) == 0xa0)
2360 int count
= insn
& 0x7;
2361 int pop_lr
= (insn
& 0x8) != 0;
2364 /* Pop r4..r[4+count]. */
2365 for (i
= 0; i
<= count
; i
++)
2367 cache
->saved_regs
[4 + i
].addr
= vsp
;
2371 /* If indicated by flag, pop LR as well. */
2374 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= vsp
;
2378 else if (insn
== 0xb0)
2380 /* We could only have updated PC by popping into it; if so, it
2381 will show up as address. Otherwise, copy LR into PC. */
2382 if (!trad_frame_addr_p (cache
->saved_regs
, ARM_PC_REGNUM
))
2383 cache
->saved_regs
[ARM_PC_REGNUM
]
2384 = cache
->saved_regs
[ARM_LR_REGNUM
];
2389 else if (insn
== 0xb1)
2391 int mask
= *entry
++;
2394 /* All-zero mask and mask >= 16 is "spare". */
2395 if (mask
== 0 || mask
>= 16)
2398 /* Pop r0..r3 under mask. */
2399 for (i
= 0; i
< 4; i
++)
2400 if (mask
& (1 << i
))
2402 cache
->saved_regs
[i
].addr
= vsp
;
2406 else if (insn
== 0xb2)
2408 ULONGEST offset
= 0;
2413 offset
|= (*entry
& 0x7f) << shift
;
2416 while (*entry
++ & 0x80);
2418 vsp
+= 0x204 + (offset
<< 2);
2420 else if (insn
== 0xb3)
2422 int start
= *entry
>> 4;
2423 int count
= (*entry
++) & 0xf;
2426 /* Only registers D0..D15 are valid here. */
2427 if (start
+ count
>= 16)
2430 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2431 for (i
= 0; i
<= count
; i
++)
2433 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2437 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2440 else if ((insn
& 0xf8) == 0xb8)
2442 int count
= insn
& 0x7;
2445 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2446 for (i
= 0; i
<= count
; i
++)
2448 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2452 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2455 else if (insn
== 0xc6)
2457 int start
= *entry
>> 4;
2458 int count
= (*entry
++) & 0xf;
2461 /* Only registers WR0..WR15 are valid. */
2462 if (start
+ count
>= 16)
2465 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2466 for (i
= 0; i
<= count
; i
++)
2468 cache
->saved_regs
[ARM_WR0_REGNUM
+ start
+ i
].addr
= vsp
;
2472 else if (insn
== 0xc7)
2474 int mask
= *entry
++;
2477 /* All-zero mask and mask >= 16 is "spare". */
2478 if (mask
== 0 || mask
>= 16)
2481 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2482 for (i
= 0; i
< 4; i
++)
2483 if (mask
& (1 << i
))
2485 cache
->saved_regs
[ARM_WCGR0_REGNUM
+ i
].addr
= vsp
;
2489 else if ((insn
& 0xf8) == 0xc0)
2491 int count
= insn
& 0x7;
2494 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2495 for (i
= 0; i
<= count
; i
++)
2497 cache
->saved_regs
[ARM_WR0_REGNUM
+ 10 + i
].addr
= vsp
;
2501 else if (insn
== 0xc8)
2503 int start
= *entry
>> 4;
2504 int count
= (*entry
++) & 0xf;
2507 /* Only registers D0..D31 are valid. */
2508 if (start
+ count
>= 16)
2511 /* Pop VFP double-precision registers
2512 D[16+start]..D[16+start+count]. */
2513 for (i
= 0; i
<= count
; i
++)
2515 cache
->saved_regs
[ARM_D0_REGNUM
+ 16 + start
+ i
].addr
= vsp
;
2519 else if (insn
== 0xc9)
2521 int start
= *entry
>> 4;
2522 int count
= (*entry
++) & 0xf;
2525 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2526 for (i
= 0; i
<= count
; i
++)
2528 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2532 else if ((insn
& 0xf8) == 0xd0)
2534 int count
= insn
& 0x7;
2537 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2538 for (i
= 0; i
<= count
; i
++)
2540 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2546 /* Everything else is "spare". */
2551 /* If we restore SP from a register, assume this was the frame register.
2552 Otherwise just fall back to SP as frame register. */
2553 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2554 cache
->framereg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2556 cache
->framereg
= ARM_SP_REGNUM
;
2558 /* Determine offset to previous frame. */
2560 = vsp
- get_frame_register_unsigned (this_frame
, cache
->framereg
);
2562 /* We already got the previous SP. */
2563 cache
->prev_sp
= vsp
;
2568 /* Unwinding via ARM exception table entries. Note that the sniffer
2569 already computes a filled-in prologue cache, which is then used
2570 with the same arm_prologue_this_id and arm_prologue_prev_register
2571 routines also used for prologue-parsing based unwinding. */
2574 arm_exidx_unwind_sniffer (const struct frame_unwind
*self
,
2575 struct frame_info
*this_frame
,
2576 void **this_prologue_cache
)
2578 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2579 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2580 CORE_ADDR addr_in_block
, exidx_region
, func_start
;
2581 struct arm_prologue_cache
*cache
;
2584 /* See if we have an ARM exception table entry covering this address. */
2585 addr_in_block
= get_frame_address_in_block (this_frame
);
2586 entry
= arm_find_exidx_entry (addr_in_block
, &exidx_region
);
2590 /* The ARM exception table does not describe unwind information
2591 for arbitrary PC values, but is guaranteed to be correct only
2592 at call sites. We have to decide here whether we want to use
2593 ARM exception table information for this frame, or fall back
2594 to using prologue parsing. (Note that if we have DWARF CFI,
2595 this sniffer isn't even called -- CFI is always preferred.)
2597 Before we make this decision, however, we check whether we
2598 actually have *symbol* information for the current frame.
2599 If not, prologue parsing would not work anyway, so we might
2600 as well use the exception table and hope for the best. */
2601 if (find_pc_partial_function (addr_in_block
, NULL
, &func_start
, NULL
))
2605 /* If the next frame is "normal", we are at a call site in this
2606 frame, so exception information is guaranteed to be valid. */
2607 if (get_next_frame (this_frame
)
2608 && get_frame_type (get_next_frame (this_frame
)) == NORMAL_FRAME
)
2611 /* We also assume exception information is valid if we're currently
2612 blocked in a system call. The system library is supposed to
2613 ensure this, so that e.g. pthread cancellation works. */
2614 if (arm_frame_is_thumb (this_frame
))
2618 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 2, 2,
2619 byte_order_for_code
, &insn
)
2620 && (insn
& 0xff00) == 0xdf00 /* svc */)
2627 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 4, 4,
2628 byte_order_for_code
, &insn
)
2629 && (insn
& 0x0f000000) == 0x0f000000 /* svc */)
2633 /* Bail out if we don't know that exception information is valid. */
2637 /* The ARM exception index does not mark the *end* of the region
2638 covered by the entry, and some functions will not have any entry.
2639 To correctly recognize the end of the covered region, the linker
2640 should have inserted dummy records with a CANTUNWIND marker.
2642 Unfortunately, current versions of GNU ld do not reliably do
2643 this, and thus we may have found an incorrect entry above.
2644 As a (temporary) sanity check, we only use the entry if it
2645 lies *within* the bounds of the function. Note that this check
2646 might reject perfectly valid entries that just happen to cover
2647 multiple functions; therefore this check ought to be removed
2648 once the linker is fixed. */
2649 if (func_start
> exidx_region
)
2653 /* Decode the list of unwinding instructions into a prologue cache.
2654 Note that this may fail due to e.g. a "refuse to unwind" code. */
2655 cache
= arm_exidx_fill_cache (this_frame
, entry
);
2659 *this_prologue_cache
= cache
;
2663 struct frame_unwind arm_exidx_unwind
= {
2665 default_frame_unwind_stop_reason
,
2666 arm_prologue_this_id
,
2667 arm_prologue_prev_register
,
2669 arm_exidx_unwind_sniffer
2672 static struct arm_prologue_cache
*
2673 arm_make_epilogue_frame_cache (struct frame_info
*this_frame
)
2675 struct arm_prologue_cache
*cache
;
2679 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2680 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2682 /* Still rely on the offset calculated from prologue. */
2683 arm_scan_prologue (this_frame
, cache
);
2685 /* Since we are in epilogue, the SP has been restored. */
2686 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2688 /* Calculate actual addresses of saved registers using offsets
2689 determined by arm_scan_prologue. */
2690 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
2691 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
2692 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
2697 /* Implementation of function hook 'this_id' in
2698 'struct frame_uwnind' for epilogue unwinder. */
2701 arm_epilogue_frame_this_id (struct frame_info
*this_frame
,
2703 struct frame_id
*this_id
)
2705 struct arm_prologue_cache
*cache
;
2708 if (*this_cache
== NULL
)
2709 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2710 cache
= (struct arm_prologue_cache
*) *this_cache
;
2712 /* Use function start address as part of the frame ID. If we cannot
2713 identify the start address (due to missing symbol information),
2714 fall back to just using the current PC. */
2715 pc
= get_frame_pc (this_frame
);
2716 func
= get_frame_func (this_frame
);
2720 (*this_id
) = frame_id_build (cache
->prev_sp
, pc
);
2723 /* Implementation of function hook 'prev_register' in
2724 'struct frame_uwnind' for epilogue unwinder. */
2726 static struct value
*
2727 arm_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2728 void **this_cache
, int regnum
)
2730 struct arm_prologue_cache
*cache
;
2732 if (*this_cache
== NULL
)
2733 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2734 cache
= (struct arm_prologue_cache
*) *this_cache
;
2736 return arm_prologue_prev_register (this_frame
, this_cache
, regnum
);
2739 static int arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
,
2741 static int thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
,
2744 /* Implementation of function hook 'sniffer' in
2745 'struct frame_uwnind' for epilogue unwinder. */
2748 arm_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2749 struct frame_info
*this_frame
,
2750 void **this_prologue_cache
)
2752 if (frame_relative_level (this_frame
) == 0)
2754 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2755 CORE_ADDR pc
= get_frame_pc (this_frame
);
2757 if (arm_frame_is_thumb (this_frame
))
2758 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
2760 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
2766 /* Frame unwinder from epilogue. */
2768 static const struct frame_unwind arm_epilogue_frame_unwind
=
2771 default_frame_unwind_stop_reason
,
2772 arm_epilogue_frame_this_id
,
2773 arm_epilogue_frame_prev_register
,
2775 arm_epilogue_frame_sniffer
,
2778 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2779 trampoline, return the target PC. Otherwise return 0.
2781 void call0a (char c, short s, int i, long l) {}
2785 (*pointer_to_call0a) (c, s, i, l);
2788 Instead of calling a stub library function _call_via_xx (xx is
2789 the register name), GCC may inline the trampoline in the object
2790 file as below (register r2 has the address of call0a).
2793 .type main, %function
2802 The trampoline 'bx r2' doesn't belong to main. */
2805 arm_skip_bx_reg (struct frame_info
*frame
, CORE_ADDR pc
)
2807 /* The heuristics of recognizing such trampoline is that FRAME is
2808 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2809 if (arm_frame_is_thumb (frame
))
2813 if (target_read_memory (pc
, buf
, 2) == 0)
2815 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2816 enum bfd_endian byte_order_for_code
2817 = gdbarch_byte_order_for_code (gdbarch
);
2819 = extract_unsigned_integer (buf
, 2, byte_order_for_code
);
2821 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
2824 = get_frame_register_unsigned (frame
, bits (insn
, 3, 6));
2826 /* Clear the LSB so that gdb core sets step-resume
2827 breakpoint at the right address. */
2828 return UNMAKE_THUMB_ADDR (dest
);
2836 static struct arm_prologue_cache
*
2837 arm_make_stub_cache (struct frame_info
*this_frame
)
2839 struct arm_prologue_cache
*cache
;
2841 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2842 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2844 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2849 /* Our frame ID for a stub frame is the current SP and LR. */
2852 arm_stub_this_id (struct frame_info
*this_frame
,
2854 struct frame_id
*this_id
)
2856 struct arm_prologue_cache
*cache
;
2858 if (*this_cache
== NULL
)
2859 *this_cache
= arm_make_stub_cache (this_frame
);
2860 cache
= (struct arm_prologue_cache
*) *this_cache
;
2862 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
2866 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
2867 struct frame_info
*this_frame
,
2868 void **this_prologue_cache
)
2870 CORE_ADDR addr_in_block
;
2872 CORE_ADDR pc
, start_addr
;
2875 addr_in_block
= get_frame_address_in_block (this_frame
);
2876 pc
= get_frame_pc (this_frame
);
2877 if (in_plt_section (addr_in_block
)
2878 /* We also use the stub winder if the target memory is unreadable
2879 to avoid having the prologue unwinder trying to read it. */
2880 || target_read_memory (pc
, dummy
, 4) != 0)
2883 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0
2884 && arm_skip_bx_reg (this_frame
, pc
) != 0)
2890 struct frame_unwind arm_stub_unwind
= {
2892 default_frame_unwind_stop_reason
,
2894 arm_prologue_prev_register
,
2896 arm_stub_unwind_sniffer
2899 /* Put here the code to store, into CACHE->saved_regs, the addresses
2900 of the saved registers of frame described by THIS_FRAME. CACHE is
2903 static struct arm_prologue_cache
*
2904 arm_m_exception_cache (struct frame_info
*this_frame
)
2906 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2907 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2908 struct arm_prologue_cache
*cache
;
2909 CORE_ADDR unwound_sp
;
2912 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2913 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2915 unwound_sp
= get_frame_register_unsigned (this_frame
,
2918 /* The hardware saves eight 32-bit words, comprising xPSR,
2919 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
2920 "B1.5.6 Exception entry behavior" in
2921 "ARMv7-M Architecture Reference Manual". */
2922 cache
->saved_regs
[0].addr
= unwound_sp
;
2923 cache
->saved_regs
[1].addr
= unwound_sp
+ 4;
2924 cache
->saved_regs
[2].addr
= unwound_sp
+ 8;
2925 cache
->saved_regs
[3].addr
= unwound_sp
+ 12;
2926 cache
->saved_regs
[12].addr
= unwound_sp
+ 16;
2927 cache
->saved_regs
[14].addr
= unwound_sp
+ 20;
2928 cache
->saved_regs
[15].addr
= unwound_sp
+ 24;
2929 cache
->saved_regs
[ARM_PS_REGNUM
].addr
= unwound_sp
+ 28;
2931 /* If bit 9 of the saved xPSR is set, then there is a four-byte
2932 aligner between the top of the 32-byte stack frame and the
2933 previous context's stack pointer. */
2934 cache
->prev_sp
= unwound_sp
+ 32;
2935 if (safe_read_memory_integer (unwound_sp
+ 28, 4, byte_order
, &xpsr
)
2936 && (xpsr
& (1 << 9)) != 0)
2937 cache
->prev_sp
+= 4;
2942 /* Implementation of function hook 'this_id' in
2943 'struct frame_uwnind'. */
2946 arm_m_exception_this_id (struct frame_info
*this_frame
,
2948 struct frame_id
*this_id
)
2950 struct arm_prologue_cache
*cache
;
2952 if (*this_cache
== NULL
)
2953 *this_cache
= arm_m_exception_cache (this_frame
);
2954 cache
= (struct arm_prologue_cache
*) *this_cache
;
2956 /* Our frame ID for a stub frame is the current SP and LR. */
2957 *this_id
= frame_id_build (cache
->prev_sp
,
2958 get_frame_pc (this_frame
));
2961 /* Implementation of function hook 'prev_register' in
2962 'struct frame_uwnind'. */
2964 static struct value
*
2965 arm_m_exception_prev_register (struct frame_info
*this_frame
,
2969 struct arm_prologue_cache
*cache
;
2971 if (*this_cache
== NULL
)
2972 *this_cache
= arm_m_exception_cache (this_frame
);
2973 cache
= (struct arm_prologue_cache
*) *this_cache
;
2975 /* The value was already reconstructed into PREV_SP. */
2976 if (prev_regnum
== ARM_SP_REGNUM
)
2977 return frame_unwind_got_constant (this_frame
, prev_regnum
,
2980 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
2984 /* Implementation of function hook 'sniffer' in
2985 'struct frame_uwnind'. */
2988 arm_m_exception_unwind_sniffer (const struct frame_unwind
*self
,
2989 struct frame_info
*this_frame
,
2990 void **this_prologue_cache
)
2992 CORE_ADDR this_pc
= get_frame_pc (this_frame
);
2994 /* No need to check is_m; this sniffer is only registered for
2995 M-profile architectures. */
2997 /* Exception frames return to one of these magic PCs. Other values
2998 are not defined as of v7-M. See details in "B1.5.8 Exception
2999 return behavior" in "ARMv7-M Architecture Reference Manual". */
3000 if (this_pc
== 0xfffffff1 || this_pc
== 0xfffffff9
3001 || this_pc
== 0xfffffffd)
3007 /* Frame unwinder for M-profile exceptions. */
3009 struct frame_unwind arm_m_exception_unwind
=
3012 default_frame_unwind_stop_reason
,
3013 arm_m_exception_this_id
,
3014 arm_m_exception_prev_register
,
3016 arm_m_exception_unwind_sniffer
3020 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
3022 struct arm_prologue_cache
*cache
;
3024 if (*this_cache
== NULL
)
3025 *this_cache
= arm_make_prologue_cache (this_frame
);
3026 cache
= (struct arm_prologue_cache
*) *this_cache
;
3028 return cache
->prev_sp
- cache
->framesize
;
3031 struct frame_base arm_normal_base
= {
3032 &arm_prologue_unwind
,
3033 arm_normal_frame_base
,
3034 arm_normal_frame_base
,
3035 arm_normal_frame_base
3038 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3039 dummy frame. The frame ID's base needs to match the TOS value
3040 saved by save_dummy_frame_tos() and returned from
3041 arm_push_dummy_call, and the PC needs to match the dummy frame's
3044 static struct frame_id
3045 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3047 return frame_id_build (get_frame_register_unsigned (this_frame
,
3049 get_frame_pc (this_frame
));
3052 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3053 be used to construct the previous frame's ID, after looking up the
3054 containing function). */
3057 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3060 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
3061 return arm_addr_bits_remove (gdbarch
, pc
);
3065 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3067 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
3070 static struct value
*
3071 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
3074 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
3076 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
3081 /* The PC is normally copied from the return column, which
3082 describes saves of LR. However, that version may have an
3083 extra bit set to indicate Thumb state. The bit is not
3085 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3086 return frame_unwind_got_constant (this_frame
, regnum
,
3087 arm_addr_bits_remove (gdbarch
, lr
));
3090 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3091 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
3092 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3093 if (IS_THUMB_ADDR (lr
))
3097 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
3100 internal_error (__FILE__
, __LINE__
,
3101 _("Unexpected register %d"), regnum
);
3106 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3107 struct dwarf2_frame_state_reg
*reg
,
3108 struct frame_info
*this_frame
)
3114 reg
->how
= DWARF2_FRAME_REG_FN
;
3115 reg
->loc
.fn
= arm_dwarf2_prev_register
;
3118 reg
->how
= DWARF2_FRAME_REG_CFA
;
3123 /* Implement the stack_frame_destroyed_p gdbarch method. */
3126 thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3128 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3129 unsigned int insn
, insn2
;
3130 int found_return
= 0, found_stack_adjust
= 0;
3131 CORE_ADDR func_start
, func_end
;
3135 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3138 /* The epilogue is a sequence of instructions along the following lines:
3140 - add stack frame size to SP or FP
3141 - [if frame pointer used] restore SP from FP
3142 - restore registers from SP [may include PC]
3143 - a return-type instruction [if PC wasn't already restored]
3145 In a first pass, we scan forward from the current PC and verify the
3146 instructions we find as compatible with this sequence, ending in a
3149 However, this is not sufficient to distinguish indirect function calls
3150 within a function from indirect tail calls in the epilogue in some cases.
3151 Therefore, if we didn't already find any SP-changing instruction during
3152 forward scan, we add a backward scanning heuristic to ensure we actually
3153 are in the epilogue. */
3156 while (scan_pc
< func_end
&& !found_return
)
3158 if (target_read_memory (scan_pc
, buf
, 2))
3162 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3164 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3166 else if (insn
== 0x46f7) /* mov pc, lr */
3168 else if (thumb_instruction_restores_sp (insn
))
3170 if ((insn
& 0xff00) == 0xbd00) /* pop <registers, PC> */
3173 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instruction */
3175 if (target_read_memory (scan_pc
, buf
, 2))
3179 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3181 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3183 if (insn2
& 0x8000) /* <registers> include PC. */
3186 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3187 && (insn2
& 0x0fff) == 0x0b04)
3189 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
3192 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3193 && (insn2
& 0x0e00) == 0x0a00)
3205 /* Since any instruction in the epilogue sequence, with the possible
3206 exception of return itself, updates the stack pointer, we need to
3207 scan backwards for at most one instruction. Try either a 16-bit or
3208 a 32-bit instruction. This is just a heuristic, so we do not worry
3209 too much about false positives. */
3211 if (pc
- 4 < func_start
)
3213 if (target_read_memory (pc
- 4, buf
, 4))
3216 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3217 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
3219 if (thumb_instruction_restores_sp (insn2
))
3220 found_stack_adjust
= 1;
3221 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3222 found_stack_adjust
= 1;
3223 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3224 && (insn2
& 0x0fff) == 0x0b04)
3225 found_stack_adjust
= 1;
3226 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3227 && (insn2
& 0x0e00) == 0x0a00)
3228 found_stack_adjust
= 1;
3230 return found_stack_adjust
;
3234 arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3236 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3239 CORE_ADDR func_start
, func_end
;
3241 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3244 /* We are in the epilogue if the previous instruction was a stack
3245 adjustment and the next instruction is a possible return (bx, mov
3246 pc, or pop). We could have to scan backwards to find the stack
3247 adjustment, or forwards to find the return, but this is a decent
3248 approximation. First scan forwards. */
3251 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3252 if (bits (insn
, 28, 31) != INST_NV
)
3254 if ((insn
& 0x0ffffff0) == 0x012fff10)
3257 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
3260 else if ((insn
& 0x0fff0000) == 0x08bd0000
3261 && (insn
& 0x0000c000) != 0)
3262 /* POP (LDMIA), including PC or LR. */
3269 /* Scan backwards. This is just a heuristic, so do not worry about
3270 false positives from mode changes. */
3272 if (pc
< func_start
+ 4)
3275 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
3276 if (arm_instruction_restores_sp (insn
))
3282 /* Implement the stack_frame_destroyed_p gdbarch method. */
3285 arm_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3287 if (arm_pc_is_thumb (gdbarch
, pc
))
3288 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
3290 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
3293 /* When arguments must be pushed onto the stack, they go on in reverse
3294 order. The code below implements a FILO (stack) to do this. */
3299 struct stack_item
*prev
;
3303 static struct stack_item
*
3304 push_stack_item (struct stack_item
*prev
, const gdb_byte
*contents
, int len
)
3306 struct stack_item
*si
;
3307 si
= XNEW (struct stack_item
);
3308 si
->data
= (gdb_byte
*) xmalloc (len
);
3311 memcpy (si
->data
, contents
, len
);
3315 static struct stack_item
*
3316 pop_stack_item (struct stack_item
*si
)
3318 struct stack_item
*dead
= si
;
3326 /* Return the alignment (in bytes) of the given type. */
3329 arm_type_align (struct type
*t
)
3335 t
= check_typedef (t
);
3336 switch (TYPE_CODE (t
))
3339 /* Should never happen. */
3340 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
3344 case TYPE_CODE_ENUM
:
3348 case TYPE_CODE_RANGE
:
3350 case TYPE_CODE_CHAR
:
3351 case TYPE_CODE_BOOL
:
3352 return TYPE_LENGTH (t
);
3354 case TYPE_CODE_ARRAY
:
3355 if (TYPE_VECTOR (t
))
3357 /* Use the natural alignment for vector types (the same for
3358 scalar type), but the maximum alignment is 64-bit. */
3359 if (TYPE_LENGTH (t
) > 8)
3362 return TYPE_LENGTH (t
);
3365 return arm_type_align (TYPE_TARGET_TYPE (t
));
3366 case TYPE_CODE_COMPLEX
:
3367 return arm_type_align (TYPE_TARGET_TYPE (t
));
3369 case TYPE_CODE_STRUCT
:
3370 case TYPE_CODE_UNION
:
3372 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
3374 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
3382 /* Possible base types for a candidate for passing and returning in
3385 enum arm_vfp_cprc_base_type
3394 /* The length of one element of base type B. */
3397 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
3401 case VFP_CPRC_SINGLE
:
3403 case VFP_CPRC_DOUBLE
:
3405 case VFP_CPRC_VEC64
:
3407 case VFP_CPRC_VEC128
:
3410 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3415 /* The character ('s', 'd' or 'q') for the type of VFP register used
3416 for passing base type B. */
3419 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
3423 case VFP_CPRC_SINGLE
:
3425 case VFP_CPRC_DOUBLE
:
3427 case VFP_CPRC_VEC64
:
3429 case VFP_CPRC_VEC128
:
3432 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3437 /* Determine whether T may be part of a candidate for passing and
3438 returning in VFP registers, ignoring the limit on the total number
3439 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3440 classification of the first valid component found; if it is not
3441 VFP_CPRC_UNKNOWN, all components must have the same classification
3442 as *BASE_TYPE. If it is found that T contains a type not permitted
3443 for passing and returning in VFP registers, a type differently
3444 classified from *BASE_TYPE, or two types differently classified
3445 from each other, return -1, otherwise return the total number of
3446 base-type elements found (possibly 0 in an empty structure or
3447 array). Vector types are not currently supported, matching the
3448 generic AAPCS support. */
3451 arm_vfp_cprc_sub_candidate (struct type
*t
,
3452 enum arm_vfp_cprc_base_type
*base_type
)
3454 t
= check_typedef (t
);
3455 switch (TYPE_CODE (t
))
3458 switch (TYPE_LENGTH (t
))
3461 if (*base_type
== VFP_CPRC_UNKNOWN
)
3462 *base_type
= VFP_CPRC_SINGLE
;
3463 else if (*base_type
!= VFP_CPRC_SINGLE
)
3468 if (*base_type
== VFP_CPRC_UNKNOWN
)
3469 *base_type
= VFP_CPRC_DOUBLE
;
3470 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3479 case TYPE_CODE_COMPLEX
:
3480 /* Arguments of complex T where T is one of the types float or
3481 double get treated as if they are implemented as:
3490 switch (TYPE_LENGTH (t
))
3493 if (*base_type
== VFP_CPRC_UNKNOWN
)
3494 *base_type
= VFP_CPRC_SINGLE
;
3495 else if (*base_type
!= VFP_CPRC_SINGLE
)
3500 if (*base_type
== VFP_CPRC_UNKNOWN
)
3501 *base_type
= VFP_CPRC_DOUBLE
;
3502 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3511 case TYPE_CODE_ARRAY
:
3513 if (TYPE_VECTOR (t
))
3515 /* A 64-bit or 128-bit containerized vector type are VFP
3517 switch (TYPE_LENGTH (t
))
3520 if (*base_type
== VFP_CPRC_UNKNOWN
)
3521 *base_type
= VFP_CPRC_VEC64
;
3524 if (*base_type
== VFP_CPRC_UNKNOWN
)
3525 *base_type
= VFP_CPRC_VEC128
;
3536 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
),
3540 if (TYPE_LENGTH (t
) == 0)
3542 gdb_assert (count
== 0);
3545 else if (count
== 0)
3547 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3548 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
3549 return TYPE_LENGTH (t
) / unitlen
;
3554 case TYPE_CODE_STRUCT
:
3559 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3561 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3563 if (sub_count
== -1)
3567 if (TYPE_LENGTH (t
) == 0)
3569 gdb_assert (count
== 0);
3572 else if (count
== 0)
3574 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3575 if (TYPE_LENGTH (t
) != unitlen
* count
)
3580 case TYPE_CODE_UNION
:
3585 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3587 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3589 if (sub_count
== -1)
3591 count
= (count
> sub_count
? count
: sub_count
);
3593 if (TYPE_LENGTH (t
) == 0)
3595 gdb_assert (count
== 0);
3598 else if (count
== 0)
3600 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3601 if (TYPE_LENGTH (t
) != unitlen
* count
)
3613 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3614 if passed to or returned from a non-variadic function with the VFP
3615 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3616 *BASE_TYPE to the base type for T and *COUNT to the number of
3617 elements of that base type before returning. */
3620 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
3623 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
3624 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
3625 if (c
<= 0 || c
> 4)
3632 /* Return 1 if the VFP ABI should be used for passing arguments to and
3633 returning values from a function of type FUNC_TYPE, 0
3637 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
3639 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3640 /* Variadic functions always use the base ABI. Assume that functions
3641 without debug info are not variadic. */
3642 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
3644 /* The VFP ABI is only supported as a variant of AAPCS. */
3645 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
3647 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
3650 /* We currently only support passing parameters in integer registers, which
3651 conforms with GCC's default model, and VFP argument passing following
3652 the VFP variant of AAPCS. Several other variants exist and
3653 we should probably support some of them based on the selected ABI. */
3656 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3657 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3658 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3659 CORE_ADDR struct_addr
)
3661 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3665 struct stack_item
*si
= NULL
;
3668 unsigned vfp_regs_free
= (1 << 16) - 1;
3670 /* Determine the type of this function and whether the VFP ABI
3672 ftype
= check_typedef (value_type (function
));
3673 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
3674 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
3675 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
3677 /* Set the return address. For the ARM, the return breakpoint is
3678 always at BP_ADDR. */
3679 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
3681 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
3683 /* Walk through the list of args and determine how large a temporary
3684 stack is required. Need to take care here as structs may be
3685 passed on the stack, and we have to push them. */
3688 argreg
= ARM_A1_REGNUM
;
3691 /* The struct_return pointer occupies the first parameter
3692 passing register. */
3696 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
3697 gdbarch_register_name (gdbarch
, argreg
),
3698 paddress (gdbarch
, struct_addr
));
3699 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
3703 for (argnum
= 0; argnum
< nargs
; argnum
++)
3706 struct type
*arg_type
;
3707 struct type
*target_type
;
3708 enum type_code typecode
;
3709 const bfd_byte
*val
;
3711 enum arm_vfp_cprc_base_type vfp_base_type
;
3713 int may_use_core_reg
= 1;
3715 arg_type
= check_typedef (value_type (args
[argnum
]));
3716 len
= TYPE_LENGTH (arg_type
);
3717 target_type
= TYPE_TARGET_TYPE (arg_type
);
3718 typecode
= TYPE_CODE (arg_type
);
3719 val
= value_contents (args
[argnum
]);
3721 align
= arm_type_align (arg_type
);
3722 /* Round alignment up to a whole number of words. */
3723 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
3724 /* Different ABIs have different maximum alignments. */
3725 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
3727 /* The APCS ABI only requires word alignment. */
3728 align
= INT_REGISTER_SIZE
;
3732 /* The AAPCS requires at most doubleword alignment. */
3733 if (align
> INT_REGISTER_SIZE
* 2)
3734 align
= INT_REGISTER_SIZE
* 2;
3738 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
3746 /* Because this is a CPRC it cannot go in a core register or
3747 cause a core register to be skipped for alignment.
3748 Either it goes in VFP registers and the rest of this loop
3749 iteration is skipped for this argument, or it goes on the
3750 stack (and the stack alignment code is correct for this
3752 may_use_core_reg
= 0;
3754 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
3755 shift
= unit_length
/ 4;
3756 mask
= (1 << (shift
* vfp_base_count
)) - 1;
3757 for (regno
= 0; regno
< 16; regno
+= shift
)
3758 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
3767 vfp_regs_free
&= ~(mask
<< regno
);
3768 reg_scaled
= regno
/ shift
;
3769 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
3770 for (i
= 0; i
< vfp_base_count
; i
++)
3774 if (reg_char
== 'q')
3775 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
3776 val
+ i
* unit_length
);
3779 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d",
3780 reg_char
, reg_scaled
+ i
);
3781 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3783 regcache_cooked_write (regcache
, regnum
,
3784 val
+ i
* unit_length
);
3791 /* This CPRC could not go in VFP registers, so all VFP
3792 registers are now marked as used. */
3797 /* Push stack padding for dowubleword alignment. */
3798 if (nstack
& (align
- 1))
3800 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3801 nstack
+= INT_REGISTER_SIZE
;
3804 /* Doubleword aligned quantities must go in even register pairs. */
3805 if (may_use_core_reg
3806 && argreg
<= ARM_LAST_ARG_REGNUM
3807 && align
> INT_REGISTER_SIZE
3811 /* If the argument is a pointer to a function, and it is a
3812 Thumb function, create a LOCAL copy of the value and set
3813 the THUMB bit in it. */
3814 if (TYPE_CODE_PTR
== typecode
3815 && target_type
!= NULL
3816 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
3818 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
3819 if (arm_pc_is_thumb (gdbarch
, regval
))
3821 bfd_byte
*copy
= (bfd_byte
*) alloca (len
);
3822 store_unsigned_integer (copy
, len
, byte_order
,
3823 MAKE_THUMB_ADDR (regval
));
3828 /* Copy the argument to general registers or the stack in
3829 register-sized pieces. Large arguments are split between
3830 registers and stack. */
3833 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
3835 = extract_unsigned_integer (val
, partial_len
, byte_order
);
3837 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
3839 /* The argument is being passed in a general purpose
3841 if (byte_order
== BFD_ENDIAN_BIG
)
3842 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
3844 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
3846 gdbarch_register_name
3848 phex (regval
, INT_REGISTER_SIZE
));
3849 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3854 gdb_byte buf
[INT_REGISTER_SIZE
];
3856 memset (buf
, 0, sizeof (buf
));
3857 store_unsigned_integer (buf
, partial_len
, byte_order
, regval
);
3859 /* Push the arguments onto the stack. */
3861 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
3863 si
= push_stack_item (si
, buf
, INT_REGISTER_SIZE
);
3864 nstack
+= INT_REGISTER_SIZE
;
3871 /* If we have an odd number of words to push, then decrement the stack
3872 by one word now, so first stack argument will be dword aligned. */
3879 write_memory (sp
, si
->data
, si
->len
);
3880 si
= pop_stack_item (si
);
3883 /* Finally, update teh SP register. */
3884 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
3890 /* Always align the frame to an 8-byte boundary. This is required on
3891 some platforms and harmless on the rest. */
3894 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3896 /* Align the stack to eight bytes. */
3897 return sp
& ~ (CORE_ADDR
) 7;
3901 print_fpu_flags (struct ui_file
*file
, int flags
)
3903 if (flags
& (1 << 0))
3904 fputs_filtered ("IVO ", file
);
3905 if (flags
& (1 << 1))
3906 fputs_filtered ("DVZ ", file
);
3907 if (flags
& (1 << 2))
3908 fputs_filtered ("OFL ", file
);
3909 if (flags
& (1 << 3))
3910 fputs_filtered ("UFL ", file
);
3911 if (flags
& (1 << 4))
3912 fputs_filtered ("INX ", file
);
3913 fputc_filtered ('\n', file
);
3916 /* Print interesting information about the floating point processor
3917 (if present) or emulator. */
3919 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
3920 struct frame_info
*frame
, const char *args
)
3922 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
3925 type
= (status
>> 24) & 127;
3926 if (status
& (1 << 31))
3927 fprintf_filtered (file
, _("Hardware FPU type %d\n"), type
);
3929 fprintf_filtered (file
, _("Software FPU type %d\n"), type
);
3930 /* i18n: [floating point unit] mask */
3931 fputs_filtered (_("mask: "), file
);
3932 print_fpu_flags (file
, status
>> 16);
3933 /* i18n: [floating point unit] flags */
3934 fputs_filtered (_("flags: "), file
);
3935 print_fpu_flags (file
, status
);
3938 /* Construct the ARM extended floating point type. */
3939 static struct type
*
3940 arm_ext_type (struct gdbarch
*gdbarch
)
3942 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3944 if (!tdep
->arm_ext_type
)
3946 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
3947 floatformats_arm_ext
);
3949 return tdep
->arm_ext_type
;
3952 static struct type
*
3953 arm_neon_double_type (struct gdbarch
*gdbarch
)
3955 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3957 if (tdep
->neon_double_type
== NULL
)
3959 struct type
*t
, *elem
;
3961 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
3963 elem
= builtin_type (gdbarch
)->builtin_uint8
;
3964 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
3965 elem
= builtin_type (gdbarch
)->builtin_uint16
;
3966 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
3967 elem
= builtin_type (gdbarch
)->builtin_uint32
;
3968 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
3969 elem
= builtin_type (gdbarch
)->builtin_uint64
;
3970 append_composite_type_field (t
, "u64", elem
);
3971 elem
= builtin_type (gdbarch
)->builtin_float
;
3972 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
3973 elem
= builtin_type (gdbarch
)->builtin_double
;
3974 append_composite_type_field (t
, "f64", elem
);
3976 TYPE_VECTOR (t
) = 1;
3977 TYPE_NAME (t
) = "neon_d";
3978 tdep
->neon_double_type
= t
;
3981 return tdep
->neon_double_type
;
3984 /* FIXME: The vector types are not correctly ordered on big-endian
3985 targets. Just as s0 is the low bits of d0, d0[0] is also the low
3986 bits of d0 - regardless of what unit size is being held in d0. So
3987 the offset of the first uint8 in d0 is 7, but the offset of the
3988 first float is 4. This code works as-is for little-endian
3991 static struct type
*
3992 arm_neon_quad_type (struct gdbarch
*gdbarch
)
3994 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3996 if (tdep
->neon_quad_type
== NULL
)
3998 struct type
*t
, *elem
;
4000 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
4002 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4003 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
4004 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4005 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
4006 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4007 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
4008 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4009 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
4010 elem
= builtin_type (gdbarch
)->builtin_float
;
4011 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
4012 elem
= builtin_type (gdbarch
)->builtin_double
;
4013 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
4015 TYPE_VECTOR (t
) = 1;
4016 TYPE_NAME (t
) = "neon_q";
4017 tdep
->neon_quad_type
= t
;
4020 return tdep
->neon_quad_type
;
4023 /* Return the GDB type object for the "standard" data type of data in
4026 static struct type
*
4027 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
4029 int num_regs
= gdbarch_num_regs (gdbarch
);
4031 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
4032 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
4033 return builtin_type (gdbarch
)->builtin_float
;
4035 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
4036 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
4037 return arm_neon_quad_type (gdbarch
);
4039 /* If the target description has register information, we are only
4040 in this function so that we can override the types of
4041 double-precision registers for NEON. */
4042 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
4044 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
4046 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
4047 && TYPE_CODE (t
) == TYPE_CODE_FLT
4048 && gdbarch_tdep (gdbarch
)->have_neon
)
4049 return arm_neon_double_type (gdbarch
);
4054 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
4056 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
4057 return builtin_type (gdbarch
)->builtin_void
;
4059 return arm_ext_type (gdbarch
);
4061 else if (regnum
== ARM_SP_REGNUM
)
4062 return builtin_type (gdbarch
)->builtin_data_ptr
;
4063 else if (regnum
== ARM_PC_REGNUM
)
4064 return builtin_type (gdbarch
)->builtin_func_ptr
;
4065 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
4066 /* These registers are only supported on targets which supply
4067 an XML description. */
4068 return builtin_type (gdbarch
)->builtin_int0
;
4070 return builtin_type (gdbarch
)->builtin_uint32
;
4073 /* Map a DWARF register REGNUM onto the appropriate GDB register
4077 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
4079 /* Core integer regs. */
4080 if (reg
>= 0 && reg
<= 15)
4083 /* Legacy FPA encoding. These were once used in a way which
4084 overlapped with VFP register numbering, so their use is
4085 discouraged, but GDB doesn't support the ARM toolchain
4086 which used them for VFP. */
4087 if (reg
>= 16 && reg
<= 23)
4088 return ARM_F0_REGNUM
+ reg
- 16;
4090 /* New assignments for the FPA registers. */
4091 if (reg
>= 96 && reg
<= 103)
4092 return ARM_F0_REGNUM
+ reg
- 96;
4094 /* WMMX register assignments. */
4095 if (reg
>= 104 && reg
<= 111)
4096 return ARM_WCGR0_REGNUM
+ reg
- 104;
4098 if (reg
>= 112 && reg
<= 127)
4099 return ARM_WR0_REGNUM
+ reg
- 112;
4101 if (reg
>= 192 && reg
<= 199)
4102 return ARM_WC0_REGNUM
+ reg
- 192;
4104 /* VFP v2 registers. A double precision value is actually
4105 in d1 rather than s2, but the ABI only defines numbering
4106 for the single precision registers. This will "just work"
4107 in GDB for little endian targets (we'll read eight bytes,
4108 starting in s0 and then progressing to s1), but will be
4109 reversed on big endian targets with VFP. This won't
4110 be a problem for the new Neon quad registers; you're supposed
4111 to use DW_OP_piece for those. */
4112 if (reg
>= 64 && reg
<= 95)
4116 xsnprintf (name_buf
, sizeof (name_buf
), "s%d", reg
- 64);
4117 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4121 /* VFP v3 / Neon registers. This range is also used for VFP v2
4122 registers, except that it now describes d0 instead of s0. */
4123 if (reg
>= 256 && reg
<= 287)
4127 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", reg
- 256);
4128 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4135 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4137 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
4140 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
4142 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
4143 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
4145 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
4146 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
4148 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
4149 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
4151 if (reg
< NUM_GREGS
)
4152 return SIM_ARM_R0_REGNUM
+ reg
;
4155 if (reg
< NUM_FREGS
)
4156 return SIM_ARM_FP0_REGNUM
+ reg
;
4159 if (reg
< NUM_SREGS
)
4160 return SIM_ARM_FPS_REGNUM
+ reg
;
4163 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
4166 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4167 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4168 It is thought that this is is the floating-point register format on
4169 little-endian systems. */
4172 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
4173 void *dbl
, int endianess
)
4177 if (endianess
== BFD_ENDIAN_BIG
)
4178 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
4180 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4182 floatformat_from_doublest (fmt
, &d
, dbl
);
4186 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
4191 floatformat_to_doublest (fmt
, ptr
, &d
);
4192 if (endianess
== BFD_ENDIAN_BIG
)
4193 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
4195 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4199 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
4200 of the appropriate mode (as encoded in the PC value), even if this
4201 differs from what would be expected according to the symbol tables. */
4204 arm_insert_single_step_breakpoint (struct gdbarch
*gdbarch
,
4205 struct address_space
*aspace
,
4208 struct cleanup
*old_chain
4209 = make_cleanup_restore_integer (&arm_override_mode
);
4211 arm_override_mode
= IS_THUMB_ADDR (pc
);
4212 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4214 insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
4216 do_cleanups (old_chain
);
4219 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
4220 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
4221 NULL if an error occurs. BUF is freed. */
4224 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
4225 int old_len
, int new_len
)
4228 int bytes_to_read
= new_len
- old_len
;
4230 new_buf
= (gdb_byte
*) xmalloc (new_len
);
4231 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
4233 if (target_read_memory (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
4241 /* An IT block is at most the 2-byte IT instruction followed by
4242 four 4-byte instructions. The furthest back we must search to
4243 find an IT block that affects the current instruction is thus
4244 2 + 3 * 4 == 14 bytes. */
4245 #define MAX_IT_BLOCK_PREFIX 14
4247 /* Use a quick scan if there are more than this many bytes of
4249 #define IT_SCAN_THRESHOLD 32
4251 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
4252 A breakpoint in an IT block may not be hit, depending on the
4255 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
4259 CORE_ADDR boundary
, func_start
;
4261 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
4262 int i
, any
, last_it
, last_it_count
;
4264 /* If we are using BKPT breakpoints, none of this is necessary. */
4265 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
4268 /* ARM mode does not have this problem. */
4269 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
4272 /* We are setting a breakpoint in Thumb code that could potentially
4273 contain an IT block. The first step is to find how much Thumb
4274 code there is; we do not need to read outside of known Thumb
4276 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
4278 /* Thumb-2 code must have mapping symbols to have a chance. */
4281 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
4283 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
4284 && func_start
> boundary
)
4285 boundary
= func_start
;
4287 /* Search for a candidate IT instruction. We have to do some fancy
4288 footwork to distinguish a real IT instruction from the second
4289 half of a 32-bit instruction, but there is no need for that if
4290 there's no candidate. */
4291 buf_len
= min (bpaddr
- boundary
, MAX_IT_BLOCK_PREFIX
);
4293 /* No room for an IT instruction. */
4296 buf
= (gdb_byte
*) xmalloc (buf_len
);
4297 if (target_read_memory (bpaddr
- buf_len
, buf
, buf_len
) != 0)
4300 for (i
= 0; i
< buf_len
; i
+= 2)
4302 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4303 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4316 /* OK, the code bytes before this instruction contain at least one
4317 halfword which resembles an IT instruction. We know that it's
4318 Thumb code, but there are still two possibilities. Either the
4319 halfword really is an IT instruction, or it is the second half of
4320 a 32-bit Thumb instruction. The only way we can tell is to
4321 scan forwards from a known instruction boundary. */
4322 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
4326 /* There's a lot of code before this instruction. Start with an
4327 optimistic search; it's easy to recognize halfwords that can
4328 not be the start of a 32-bit instruction, and use that to
4329 lock on to the instruction boundaries. */
4330 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
4333 buf_len
= IT_SCAN_THRESHOLD
;
4336 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
4338 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4339 if (thumb_insn_size (inst1
) == 2)
4346 /* At this point, if DEFINITE, BUF[I] is the first place we
4347 are sure that we know the instruction boundaries, and it is far
4348 enough from BPADDR that we could not miss an IT instruction
4349 affecting BPADDR. If ! DEFINITE, give up - start from a
4353 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
,
4357 buf_len
= bpaddr
- boundary
;
4363 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
4366 buf_len
= bpaddr
- boundary
;
4370 /* Scan forwards. Find the last IT instruction before BPADDR. */
4375 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4377 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4382 else if (inst1
& 0x0002)
4384 else if (inst1
& 0x0004)
4389 i
+= thumb_insn_size (inst1
);
4395 /* There wasn't really an IT instruction after all. */
4398 if (last_it_count
< 1)
4399 /* It was too far away. */
4402 /* This really is a trouble spot. Move the breakpoint to the IT
4404 return bpaddr
- buf_len
+ last_it
;
4407 /* ARM displaced stepping support.
4409 Generally ARM displaced stepping works as follows:
4411 1. When an instruction is to be single-stepped, it is first decoded by
4412 arm_process_displaced_insn. Depending on the type of instruction, it is
4413 then copied to a scratch location, possibly in a modified form. The
4414 copy_* set of functions performs such modification, as necessary. A
4415 breakpoint is placed after the modified instruction in the scratch space
4416 to return control to GDB. Note in particular that instructions which
4417 modify the PC will no longer do so after modification.
4419 2. The instruction is single-stepped, by setting the PC to the scratch
4420 location address, and resuming. Control returns to GDB when the
4423 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
4424 function used for the current instruction. This function's job is to
4425 put the CPU/memory state back to what it would have been if the
4426 instruction had been executed unmodified in its original location. */
4428 /* NOP instruction (mov r0, r0). */
4429 #define ARM_NOP 0xe1a00000
4430 #define THUMB_NOP 0x4600
4432 /* Helper for register reads for displaced stepping. In particular, this
4433 returns the PC as it would be seen by the instruction at its original
4437 displaced_read_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4441 CORE_ADDR from
= dsc
->insn_addr
;
4443 if (regno
== ARM_PC_REGNUM
)
4445 /* Compute pipeline offset:
4446 - When executing an ARM instruction, PC reads as the address of the
4447 current instruction plus 8.
4448 - When executing a Thumb instruction, PC reads as the address of the
4449 current instruction plus 4. */
4456 if (debug_displaced
)
4457 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
4458 (unsigned long) from
);
4459 return (ULONGEST
) from
;
4463 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
4464 if (debug_displaced
)
4465 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
4466 regno
, (unsigned long) ret
);
4472 displaced_in_arm_mode (struct regcache
*regs
)
4475 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
4477 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4479 return (ps
& t_bit
) == 0;
4482 /* Write to the PC as from a branch instruction. */
4485 branch_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4489 /* Note: If bits 0/1 are set, this branch would be unpredictable for
4490 architecture versions < 6. */
4491 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4492 val
& ~(ULONGEST
) 0x3);
4494 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4495 val
& ~(ULONGEST
) 0x1);
4498 /* Write to the PC as from a branch-exchange instruction. */
4501 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
4504 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
4506 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4510 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
4511 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
4513 else if ((val
& 2) == 0)
4515 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4516 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
4520 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
4521 mode, align dest to 4 bytes). */
4522 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
4523 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4524 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
4528 /* Write to the PC as if from a load instruction. */
4531 load_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4534 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
4535 bx_write_pc (regs
, val
);
4537 branch_write_pc (regs
, dsc
, val
);
4540 /* Write to the PC as if from an ALU instruction. */
4543 alu_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4546 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && !dsc
->is_thumb
)
4547 bx_write_pc (regs
, val
);
4549 branch_write_pc (regs
, dsc
, val
);
4552 /* Helper for writing to registers for displaced stepping. Writing to the PC
4553 has a varying effects depending on the instruction which does the write:
4554 this is controlled by the WRITE_PC argument. */
4557 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4558 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
4560 if (regno
== ARM_PC_REGNUM
)
4562 if (debug_displaced
)
4563 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
4564 (unsigned long) val
);
4567 case BRANCH_WRITE_PC
:
4568 branch_write_pc (regs
, dsc
, val
);
4572 bx_write_pc (regs
, val
);
4576 load_write_pc (regs
, dsc
, val
);
4580 alu_write_pc (regs
, dsc
, val
);
4583 case CANNOT_WRITE_PC
:
4584 warning (_("Instruction wrote to PC in an unexpected way when "
4585 "single-stepping"));
4589 internal_error (__FILE__
, __LINE__
,
4590 _("Invalid argument to displaced_write_reg"));
4593 dsc
->wrote_to_pc
= 1;
4597 if (debug_displaced
)
4598 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
4599 regno
, (unsigned long) val
);
4600 regcache_cooked_write_unsigned (regs
, regno
, val
);
4604 /* This function is used to concisely determine if an instruction INSN
4605 references PC. Register fields of interest in INSN should have the
4606 corresponding fields of BITMASK set to 0b1111. The function
4607 returns return 1 if any of these fields in INSN reference the PC
4608 (also 0b1111, r15), else it returns 0. */
4611 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
4613 uint32_t lowbit
= 1;
4615 while (bitmask
!= 0)
4619 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
4625 mask
= lowbit
* 0xf;
4627 if ((insn
& mask
) == mask
)
4636 /* The simplest copy function. Many instructions have the same effect no
4637 matter what address they are executed at: in those cases, use this. */
4640 arm_copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
4641 const char *iname
, struct displaced_step_closure
*dsc
)
4643 if (debug_displaced
)
4644 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
4645 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
4648 dsc
->modinsn
[0] = insn
;
4654 thumb_copy_unmodified_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
4655 uint16_t insn2
, const char *iname
,
4656 struct displaced_step_closure
*dsc
)
4658 if (debug_displaced
)
4659 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x %.4x, "
4660 "opcode/class '%s' unmodified\n", insn1
, insn2
,
4663 dsc
->modinsn
[0] = insn1
;
4664 dsc
->modinsn
[1] = insn2
;
4670 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
4673 thumb_copy_unmodified_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
4675 struct displaced_step_closure
*dsc
)
4677 if (debug_displaced
)
4678 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x, "
4679 "opcode/class '%s' unmodified\n", insn
,
4682 dsc
->modinsn
[0] = insn
;
4687 /* Preload instructions with immediate offset. */
4690 cleanup_preload (struct gdbarch
*gdbarch
,
4691 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4693 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4694 if (!dsc
->u
.preload
.immed
)
4695 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
4699 install_preload (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4700 struct displaced_step_closure
*dsc
, unsigned int rn
)
4703 /* Preload instructions:
4705 {pli/pld} [rn, #+/-imm]
4707 {pli/pld} [r0, #+/-imm]. */
4709 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4710 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4711 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4712 dsc
->u
.preload
.immed
= 1;
4714 dsc
->cleanup
= &cleanup_preload
;
4718 arm_copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4719 struct displaced_step_closure
*dsc
)
4721 unsigned int rn
= bits (insn
, 16, 19);
4723 if (!insn_references_pc (insn
, 0x000f0000ul
))
4724 return arm_copy_unmodified (gdbarch
, insn
, "preload", dsc
);
4726 if (debug_displaced
)
4727 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4728 (unsigned long) insn
);
4730 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4732 install_preload (gdbarch
, regs
, dsc
, rn
);
4738 thumb2_copy_preload (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
4739 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4741 unsigned int rn
= bits (insn1
, 0, 3);
4742 unsigned int u_bit
= bit (insn1
, 7);
4743 int imm12
= bits (insn2
, 0, 11);
4746 if (rn
!= ARM_PC_REGNUM
)
4747 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "preload", dsc
);
4749 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
4750 PLD (literal) Encoding T1. */
4751 if (debug_displaced
)
4752 fprintf_unfiltered (gdb_stdlog
,
4753 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
4754 (unsigned int) dsc
->insn_addr
, u_bit
? '+' : '-',
4760 /* Rewrite instruction {pli/pld} PC imm12 into:
4761 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
4765 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
4767 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4768 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4770 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
4772 displaced_write_reg (regs
, dsc
, 0, pc_val
, CANNOT_WRITE_PC
);
4773 displaced_write_reg (regs
, dsc
, 1, imm12
, CANNOT_WRITE_PC
);
4774 dsc
->u
.preload
.immed
= 0;
4776 /* {pli/pld} [r0, r1] */
4777 dsc
->modinsn
[0] = insn1
& 0xfff0;
4778 dsc
->modinsn
[1] = 0xf001;
4781 dsc
->cleanup
= &cleanup_preload
;
4785 /* Preload instructions with register offset. */
4788 install_preload_reg(struct gdbarch
*gdbarch
, struct regcache
*regs
,
4789 struct displaced_step_closure
*dsc
, unsigned int rn
,
4792 ULONGEST rn_val
, rm_val
;
4794 /* Preload register-offset instructions:
4796 {pli/pld} [rn, rm {, shift}]
4798 {pli/pld} [r0, r1 {, shift}]. */
4800 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4801 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4802 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4803 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
4804 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4805 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
4806 dsc
->u
.preload
.immed
= 0;
4808 dsc
->cleanup
= &cleanup_preload
;
4812 arm_copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
4813 struct regcache
*regs
,
4814 struct displaced_step_closure
*dsc
)
4816 unsigned int rn
= bits (insn
, 16, 19);
4817 unsigned int rm
= bits (insn
, 0, 3);
4820 if (!insn_references_pc (insn
, 0x000f000ful
))
4821 return arm_copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
4823 if (debug_displaced
)
4824 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4825 (unsigned long) insn
);
4827 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
4829 install_preload_reg (gdbarch
, regs
, dsc
, rn
, rm
);
4833 /* Copy/cleanup coprocessor load and store instructions. */
4836 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
4837 struct regcache
*regs
,
4838 struct displaced_step_closure
*dsc
)
4840 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 0);
4842 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4844 if (dsc
->u
.ldst
.writeback
)
4845 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
4849 install_copro_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4850 struct displaced_step_closure
*dsc
,
4851 int writeback
, unsigned int rn
)
4855 /* Coprocessor load/store instructions:
4857 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
4859 {stc/stc2} [r0, #+/-imm].
4861 ldc/ldc2 are handled identically. */
4863 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4864 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4865 /* PC should be 4-byte aligned. */
4866 rn_val
= rn_val
& 0xfffffffc;
4867 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4869 dsc
->u
.ldst
.writeback
= writeback
;
4870 dsc
->u
.ldst
.rn
= rn
;
4872 dsc
->cleanup
= &cleanup_copro_load_store
;
4876 arm_copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
4877 struct regcache
*regs
,
4878 struct displaced_step_closure
*dsc
)
4880 unsigned int rn
= bits (insn
, 16, 19);
4882 if (!insn_references_pc (insn
, 0x000f0000ul
))
4883 return arm_copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
4885 if (debug_displaced
)
4886 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4887 "load/store insn %.8lx\n", (unsigned long) insn
);
4889 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4891 install_copro_load_store (gdbarch
, regs
, dsc
, bit (insn
, 25), rn
);
4897 thumb2_copy_copro_load_store (struct gdbarch
*gdbarch
, uint16_t insn1
,
4898 uint16_t insn2
, struct regcache
*regs
,
4899 struct displaced_step_closure
*dsc
)
4901 unsigned int rn
= bits (insn1
, 0, 3);
4903 if (rn
!= ARM_PC_REGNUM
)
4904 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
4905 "copro load/store", dsc
);
4907 if (debug_displaced
)
4908 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4909 "load/store insn %.4x%.4x\n", insn1
, insn2
);
4911 dsc
->modinsn
[0] = insn1
& 0xfff0;
4912 dsc
->modinsn
[1] = insn2
;
4915 /* This function is called for copying instruction LDC/LDC2/VLDR, which
4916 doesn't support writeback, so pass 0. */
4917 install_copro_load_store (gdbarch
, regs
, dsc
, 0, rn
);
4922 /* Clean up branch instructions (actually perform the branch, by setting
4926 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4927 struct displaced_step_closure
*dsc
)
4929 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
4930 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
4931 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
4932 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
4937 if (dsc
->u
.branch
.link
)
4939 /* The value of LR should be the next insn of current one. In order
4940 not to confuse logic hanlding later insn `bx lr', if current insn mode
4941 is Thumb, the bit 0 of LR value should be set to 1. */
4942 ULONGEST next_insn_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
4945 next_insn_addr
|= 0x1;
4947 displaced_write_reg (regs
, dsc
, ARM_LR_REGNUM
, next_insn_addr
,
4951 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, dsc
->u
.branch
.dest
, write_pc
);
4954 /* Copy B/BL/BLX instructions with immediate destinations. */
4957 install_b_bl_blx (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4958 struct displaced_step_closure
*dsc
,
4959 unsigned int cond
, int exchange
, int link
, long offset
)
4961 /* Implement "BL<cond> <label>" as:
4963 Preparation: cond <- instruction condition
4964 Insn: mov r0, r0 (nop)
4965 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
4967 B<cond> similar, but don't set r14 in cleanup. */
4969 dsc
->u
.branch
.cond
= cond
;
4970 dsc
->u
.branch
.link
= link
;
4971 dsc
->u
.branch
.exchange
= exchange
;
4973 dsc
->u
.branch
.dest
= dsc
->insn_addr
;
4974 if (link
&& exchange
)
4975 /* For BLX, offset is computed from the Align (PC, 4). */
4976 dsc
->u
.branch
.dest
= dsc
->u
.branch
.dest
& 0xfffffffc;
4979 dsc
->u
.branch
.dest
+= 4 + offset
;
4981 dsc
->u
.branch
.dest
+= 8 + offset
;
4983 dsc
->cleanup
= &cleanup_branch
;
4986 arm_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
4987 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4989 unsigned int cond
= bits (insn
, 28, 31);
4990 int exchange
= (cond
== 0xf);
4991 int link
= exchange
|| bit (insn
, 24);
4994 if (debug_displaced
)
4995 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
4996 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
4997 (unsigned long) insn
);
4999 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
5000 then arrange the switch into Thumb mode. */
5001 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
5003 offset
= bits (insn
, 0, 23) << 2;
5005 if (bit (offset
, 25))
5006 offset
= offset
| ~0x3ffffff;
5008 dsc
->modinsn
[0] = ARM_NOP
;
5010 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5015 thumb2_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint16_t insn1
,
5016 uint16_t insn2
, struct regcache
*regs
,
5017 struct displaced_step_closure
*dsc
)
5019 int link
= bit (insn2
, 14);
5020 int exchange
= link
&& !bit (insn2
, 12);
5023 int j1
= bit (insn2
, 13);
5024 int j2
= bit (insn2
, 11);
5025 int s
= sbits (insn1
, 10, 10);
5026 int i1
= !(j1
^ bit (insn1
, 10));
5027 int i2
= !(j2
^ bit (insn1
, 10));
5029 if (!link
&& !exchange
) /* B */
5031 offset
= (bits (insn2
, 0, 10) << 1);
5032 if (bit (insn2
, 12)) /* Encoding T4 */
5034 offset
|= (bits (insn1
, 0, 9) << 12)
5040 else /* Encoding T3 */
5042 offset
|= (bits (insn1
, 0, 5) << 12)
5046 cond
= bits (insn1
, 6, 9);
5051 offset
= (bits (insn1
, 0, 9) << 12);
5052 offset
|= ((i2
<< 22) | (i1
<< 23) | (s
<< 24));
5053 offset
|= exchange
?
5054 (bits (insn2
, 1, 10) << 2) : (bits (insn2
, 0, 10) << 1);
5057 if (debug_displaced
)
5058 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s insn "
5059 "%.4x %.4x with offset %.8lx\n",
5060 link
? (exchange
) ? "blx" : "bl" : "b",
5061 insn1
, insn2
, offset
);
5063 dsc
->modinsn
[0] = THUMB_NOP
;
5065 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5069 /* Copy B Thumb instructions. */
5071 thumb_copy_b (struct gdbarch
*gdbarch
, uint16_t insn
,
5072 struct displaced_step_closure
*dsc
)
5074 unsigned int cond
= 0;
5076 unsigned short bit_12_15
= bits (insn
, 12, 15);
5077 CORE_ADDR from
= dsc
->insn_addr
;
5079 if (bit_12_15
== 0xd)
5081 /* offset = SignExtend (imm8:0, 32) */
5082 offset
= sbits ((insn
<< 1), 0, 8);
5083 cond
= bits (insn
, 8, 11);
5085 else if (bit_12_15
== 0xe) /* Encoding T2 */
5087 offset
= sbits ((insn
<< 1), 0, 11);
5091 if (debug_displaced
)
5092 fprintf_unfiltered (gdb_stdlog
,
5093 "displaced: copying b immediate insn %.4x "
5094 "with offset %d\n", insn
, offset
);
5096 dsc
->u
.branch
.cond
= cond
;
5097 dsc
->u
.branch
.link
= 0;
5098 dsc
->u
.branch
.exchange
= 0;
5099 dsc
->u
.branch
.dest
= from
+ 4 + offset
;
5101 dsc
->modinsn
[0] = THUMB_NOP
;
5103 dsc
->cleanup
= &cleanup_branch
;
5108 /* Copy BX/BLX with register-specified destinations. */
5111 install_bx_blx_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5112 struct displaced_step_closure
*dsc
, int link
,
5113 unsigned int cond
, unsigned int rm
)
5115 /* Implement {BX,BLX}<cond> <reg>" as:
5117 Preparation: cond <- instruction condition
5118 Insn: mov r0, r0 (nop)
5119 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
5121 Don't set r14 in cleanup for BX. */
5123 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, dsc
, rm
);
5125 dsc
->u
.branch
.cond
= cond
;
5126 dsc
->u
.branch
.link
= link
;
5128 dsc
->u
.branch
.exchange
= 1;
5130 dsc
->cleanup
= &cleanup_branch
;
5134 arm_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5135 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5137 unsigned int cond
= bits (insn
, 28, 31);
5140 int link
= bit (insn
, 5);
5141 unsigned int rm
= bits (insn
, 0, 3);
5143 if (debug_displaced
)
5144 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx",
5145 (unsigned long) insn
);
5147 dsc
->modinsn
[0] = ARM_NOP
;
5149 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, cond
, rm
);
5154 thumb_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5155 struct regcache
*regs
,
5156 struct displaced_step_closure
*dsc
)
5158 int link
= bit (insn
, 7);
5159 unsigned int rm
= bits (insn
, 3, 6);
5161 if (debug_displaced
)
5162 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x",
5163 (unsigned short) insn
);
5165 dsc
->modinsn
[0] = THUMB_NOP
;
5167 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, INST_AL
, rm
);
5173 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
5176 cleanup_alu_imm (struct gdbarch
*gdbarch
,
5177 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5179 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5180 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5181 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5182 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5186 arm_copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5187 struct displaced_step_closure
*dsc
)
5189 unsigned int rn
= bits (insn
, 16, 19);
5190 unsigned int rd
= bits (insn
, 12, 15);
5191 unsigned int op
= bits (insn
, 21, 24);
5192 int is_mov
= (op
== 0xd);
5193 ULONGEST rd_val
, rn_val
;
5195 if (!insn_references_pc (insn
, 0x000ff000ul
))
5196 return arm_copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
5198 if (debug_displaced
)
5199 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
5200 "%.8lx\n", is_mov
? "move" : "ALU",
5201 (unsigned long) insn
);
5203 /* Instruction is of form:
5205 <op><cond> rd, [rn,] #imm
5209 Preparation: tmp1, tmp2 <- r0, r1;
5211 Insn: <op><cond> r0, r1, #imm
5212 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5215 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5216 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5217 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5218 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5219 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5220 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5224 dsc
->modinsn
[0] = insn
& 0xfff00fff;
5226 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
5228 dsc
->cleanup
= &cleanup_alu_imm
;
5234 thumb2_copy_alu_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5235 uint16_t insn2
, struct regcache
*regs
,
5236 struct displaced_step_closure
*dsc
)
5238 unsigned int op
= bits (insn1
, 5, 8);
5239 unsigned int rn
, rm
, rd
;
5240 ULONGEST rd_val
, rn_val
;
5242 rn
= bits (insn1
, 0, 3); /* Rn */
5243 rm
= bits (insn2
, 0, 3); /* Rm */
5244 rd
= bits (insn2
, 8, 11); /* Rd */
5246 /* This routine is only called for instruction MOV. */
5247 gdb_assert (op
== 0x2 && rn
== 0xf);
5249 if (rm
!= ARM_PC_REGNUM
&& rd
!= ARM_PC_REGNUM
)
5250 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ALU imm", dsc
);
5252 if (debug_displaced
)
5253 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x%.4x\n",
5254 "ALU", insn1
, insn2
);
5256 /* Instruction is of form:
5258 <op><cond> rd, [rn,] #imm
5262 Preparation: tmp1, tmp2 <- r0, r1;
5264 Insn: <op><cond> r0, r1, #imm
5265 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5268 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5269 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5270 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5271 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5272 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5273 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5276 dsc
->modinsn
[0] = insn1
;
5277 dsc
->modinsn
[1] = ((insn2
& 0xf0f0) | 0x1);
5280 dsc
->cleanup
= &cleanup_alu_imm
;
5285 /* Copy/cleanup arithmetic/logic insns with register RHS. */
5288 cleanup_alu_reg (struct gdbarch
*gdbarch
,
5289 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5294 rd_val
= displaced_read_reg (regs
, dsc
, 0);
5296 for (i
= 0; i
< 3; i
++)
5297 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5299 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5303 install_alu_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5304 struct displaced_step_closure
*dsc
,
5305 unsigned int rd
, unsigned int rn
, unsigned int rm
)
5307 ULONGEST rd_val
, rn_val
, rm_val
;
5309 /* Instruction is of form:
5311 <op><cond> rd, [rn,] rm [, <shift>]
5315 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
5316 r0, r1, r2 <- rd, rn, rm
5317 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
5318 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
5321 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5322 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5323 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5324 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5325 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5326 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5327 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5328 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5329 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5332 dsc
->cleanup
= &cleanup_alu_reg
;
5336 arm_copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5337 struct displaced_step_closure
*dsc
)
5339 unsigned int op
= bits (insn
, 21, 24);
5340 int is_mov
= (op
== 0xd);
5342 if (!insn_references_pc (insn
, 0x000ff00ful
))
5343 return arm_copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
5345 if (debug_displaced
)
5346 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
5347 is_mov
? "move" : "ALU", (unsigned long) insn
);
5350 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
5352 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
5354 install_alu_reg (gdbarch
, regs
, dsc
, bits (insn
, 12, 15), bits (insn
, 16, 19),
5360 thumb_copy_alu_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5361 struct regcache
*regs
,
5362 struct displaced_step_closure
*dsc
)
5366 rm
= bits (insn
, 3, 6);
5367 rd
= (bit (insn
, 7) << 3) | bits (insn
, 0, 2);
5369 if (rd
!= ARM_PC_REGNUM
&& rm
!= ARM_PC_REGNUM
)
5370 return thumb_copy_unmodified_16bit (gdbarch
, insn
, "ALU reg", dsc
);
5372 if (debug_displaced
)
5373 fprintf_unfiltered (gdb_stdlog
, "displaced: copying ALU reg insn %.4x\n",
5374 (unsigned short) insn
);
5376 dsc
->modinsn
[0] = ((insn
& 0xff00) | 0x10);
5378 install_alu_reg (gdbarch
, regs
, dsc
, rd
, rd
, rm
);
5383 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
5386 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
5387 struct regcache
*regs
,
5388 struct displaced_step_closure
*dsc
)
5390 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5393 for (i
= 0; i
< 4; i
++)
5394 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5396 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5400 install_alu_shifted_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5401 struct displaced_step_closure
*dsc
,
5402 unsigned int rd
, unsigned int rn
, unsigned int rm
,
5406 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
5408 /* Instruction is of form:
5410 <op><cond> rd, [rn,] rm, <shift> rs
5414 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
5415 r0, r1, r2, r3 <- rd, rn, rm, rs
5416 Insn: <op><cond> r0, r1, r2, <shift> r3
5418 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
5422 for (i
= 0; i
< 4; i
++)
5423 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
5425 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5426 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5427 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5428 rs_val
= displaced_read_reg (regs
, dsc
, rs
);
5429 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5430 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5431 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5432 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
5434 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
5438 arm_copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5439 struct regcache
*regs
,
5440 struct displaced_step_closure
*dsc
)
5442 unsigned int op
= bits (insn
, 21, 24);
5443 int is_mov
= (op
== 0xd);
5444 unsigned int rd
, rn
, rm
, rs
;
5446 if (!insn_references_pc (insn
, 0x000fff0ful
))
5447 return arm_copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
5449 if (debug_displaced
)
5450 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
5451 "%.8lx\n", is_mov
? "move" : "ALU",
5452 (unsigned long) insn
);
5454 rn
= bits (insn
, 16, 19);
5455 rm
= bits (insn
, 0, 3);
5456 rs
= bits (insn
, 8, 11);
5457 rd
= bits (insn
, 12, 15);
5460 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
5462 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
5464 install_alu_shifted_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
, rs
);
5469 /* Clean up load instructions. */
5472 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5473 struct displaced_step_closure
*dsc
)
5475 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
5477 rt_val
= displaced_read_reg (regs
, dsc
, 0);
5478 if (dsc
->u
.ldst
.xfersize
== 8)
5479 rt_val2
= displaced_read_reg (regs
, dsc
, 1);
5480 rn_val
= displaced_read_reg (regs
, dsc
, 2);
5482 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5483 if (dsc
->u
.ldst
.xfersize
> 4)
5484 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5485 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5486 if (!dsc
->u
.ldst
.immed
)
5487 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5489 /* Handle register writeback. */
5490 if (dsc
->u
.ldst
.writeback
)
5491 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5492 /* Put result in right place. */
5493 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
5494 if (dsc
->u
.ldst
.xfersize
== 8)
5495 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
5498 /* Clean up store instructions. */
5501 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5502 struct displaced_step_closure
*dsc
)
5504 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 2);
5506 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5507 if (dsc
->u
.ldst
.xfersize
> 4)
5508 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5509 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5510 if (!dsc
->u
.ldst
.immed
)
5511 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5512 if (!dsc
->u
.ldst
.restore_r4
)
5513 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
5516 if (dsc
->u
.ldst
.writeback
)
5517 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5520 /* Copy "extra" load/store instructions. These are halfword/doubleword
5521 transfers, which have a different encoding to byte/word transfers. */
5524 arm_copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unprivileged
,
5525 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5527 unsigned int op1
= bits (insn
, 20, 24);
5528 unsigned int op2
= bits (insn
, 5, 6);
5529 unsigned int rt
= bits (insn
, 12, 15);
5530 unsigned int rn
= bits (insn
, 16, 19);
5531 unsigned int rm
= bits (insn
, 0, 3);
5532 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
5533 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
5534 int immed
= (op1
& 0x4) != 0;
5536 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
5538 if (!insn_references_pc (insn
, 0x000ff00ful
))
5539 return arm_copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
5541 if (debug_displaced
)
5542 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
5543 "insn %.8lx\n", unprivileged
? "unprivileged " : "",
5544 (unsigned long) insn
);
5546 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
5549 internal_error (__FILE__
, __LINE__
,
5550 _("copy_extra_ld_st: instruction decode error"));
5552 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5553 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5554 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5556 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5558 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5559 if (bytesize
[opcode
] == 8)
5560 rt_val2
= displaced_read_reg (regs
, dsc
, rt
+ 1);
5561 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5563 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5565 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5566 if (bytesize
[opcode
] == 8)
5567 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
5568 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5570 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5573 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
5574 dsc
->u
.ldst
.rn
= rn
;
5575 dsc
->u
.ldst
.immed
= immed
;
5576 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
5577 dsc
->u
.ldst
.restore_r4
= 0;
5580 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
5582 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
5583 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5585 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
5587 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
5588 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5590 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
5595 /* Copy byte/half word/word loads and stores. */
5598 install_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5599 struct displaced_step_closure
*dsc
, int load
,
5600 int immed
, int writeback
, int size
, int usermode
,
5601 int rt
, int rm
, int rn
)
5603 ULONGEST rt_val
, rn_val
, rm_val
= 0;
5605 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5606 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5608 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5610 dsc
->tmp
[4] = displaced_read_reg (regs
, dsc
, 4);
5612 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5613 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5615 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5617 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5618 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5620 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5622 dsc
->u
.ldst
.xfersize
= size
;
5623 dsc
->u
.ldst
.rn
= rn
;
5624 dsc
->u
.ldst
.immed
= immed
;
5625 dsc
->u
.ldst
.writeback
= writeback
;
5627 /* To write PC we can do:
5629 Before this sequence of instructions:
5630 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
5631 r2 is the Rn value got from dispalced_read_reg.
5633 Insn1: push {pc} Write address of STR instruction + offset on stack
5634 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
5635 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
5636 = addr(Insn1) + offset - addr(Insn3) - 8
5638 Insn4: add r4, r4, #8 r4 = offset - 8
5639 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
5641 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
5643 Otherwise we don't know what value to write for PC, since the offset is
5644 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
5645 of this can be found in Section "Saving from r15" in
5646 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
5648 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5653 thumb2_copy_load_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
5654 uint16_t insn2
, struct regcache
*regs
,
5655 struct displaced_step_closure
*dsc
, int size
)
5657 unsigned int u_bit
= bit (insn1
, 7);
5658 unsigned int rt
= bits (insn2
, 12, 15);
5659 int imm12
= bits (insn2
, 0, 11);
5662 if (debug_displaced
)
5663 fprintf_unfiltered (gdb_stdlog
,
5664 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
5665 (unsigned int) dsc
->insn_addr
, rt
, u_bit
? '+' : '-',
5671 /* Rewrite instruction LDR Rt imm12 into:
5673 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
5677 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
5680 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5681 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5682 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5684 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
5686 pc_val
= pc_val
& 0xfffffffc;
5688 displaced_write_reg (regs
, dsc
, 2, pc_val
, CANNOT_WRITE_PC
);
5689 displaced_write_reg (regs
, dsc
, 3, imm12
, CANNOT_WRITE_PC
);
5693 dsc
->u
.ldst
.xfersize
= size
;
5694 dsc
->u
.ldst
.immed
= 0;
5695 dsc
->u
.ldst
.writeback
= 0;
5696 dsc
->u
.ldst
.restore_r4
= 0;
5698 /* LDR R0, R2, R3 */
5699 dsc
->modinsn
[0] = 0xf852;
5700 dsc
->modinsn
[1] = 0x3;
5703 dsc
->cleanup
= &cleanup_load
;
5709 thumb2_copy_load_reg_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5710 uint16_t insn2
, struct regcache
*regs
,
5711 struct displaced_step_closure
*dsc
,
5712 int writeback
, int immed
)
5714 unsigned int rt
= bits (insn2
, 12, 15);
5715 unsigned int rn
= bits (insn1
, 0, 3);
5716 unsigned int rm
= bits (insn2
, 0, 3); /* Only valid if !immed. */
5717 /* In LDR (register), there is also a register Rm, which is not allowed to
5718 be PC, so we don't have to check it. */
5720 if (rt
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
5721 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "load",
5724 if (debug_displaced
)
5725 fprintf_unfiltered (gdb_stdlog
,
5726 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
5727 rt
, rn
, insn1
, insn2
);
5729 install_load_store (gdbarch
, regs
, dsc
, 1, immed
, writeback
, 4,
5732 dsc
->u
.ldst
.restore_r4
= 0;
5735 /* ldr[b]<cond> rt, [rn, #imm], etc.
5737 ldr[b]<cond> r0, [r2, #imm]. */
5739 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5740 dsc
->modinsn
[1] = insn2
& 0x0fff;
5743 /* ldr[b]<cond> rt, [rn, rm], etc.
5745 ldr[b]<cond> r0, [r2, r3]. */
5747 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5748 dsc
->modinsn
[1] = (insn2
& 0x0ff0) | 0x3;
5758 arm_copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
5759 struct regcache
*regs
,
5760 struct displaced_step_closure
*dsc
,
5761 int load
, int size
, int usermode
)
5763 int immed
= !bit (insn
, 25);
5764 int writeback
= (bit (insn
, 24) == 0 || bit (insn
, 21) != 0);
5765 unsigned int rt
= bits (insn
, 12, 15);
5766 unsigned int rn
= bits (insn
, 16, 19);
5767 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
5769 if (!insn_references_pc (insn
, 0x000ff00ful
))
5770 return arm_copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
5772 if (debug_displaced
)
5773 fprintf_unfiltered (gdb_stdlog
,
5774 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
5775 load
? (size
== 1 ? "ldrb" : "ldr")
5776 : (size
== 1 ? "strb" : "str"), usermode
? "t" : "",
5778 (unsigned long) insn
);
5780 install_load_store (gdbarch
, regs
, dsc
, load
, immed
, writeback
, size
,
5781 usermode
, rt
, rm
, rn
);
5783 if (load
|| rt
!= ARM_PC_REGNUM
)
5785 dsc
->u
.ldst
.restore_r4
= 0;
5788 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
5790 {ldr,str}[b]<cond> r0, [r2, #imm]. */
5791 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5793 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
5795 {ldr,str}[b]<cond> r0, [r2, r3]. */
5796 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5800 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
5801 dsc
->u
.ldst
.restore_r4
= 1;
5802 dsc
->modinsn
[0] = 0xe92d8000; /* push {pc} */
5803 dsc
->modinsn
[1] = 0xe8bd0010; /* pop {r4} */
5804 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
5805 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
5806 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
5810 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
5812 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
5817 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5822 /* Cleanup LDM instructions with fully-populated register list. This is an
5823 unfortunate corner case: it's impossible to implement correctly by modifying
5824 the instruction. The issue is as follows: we have an instruction,
5828 which we must rewrite to avoid loading PC. A possible solution would be to
5829 do the load in two halves, something like (with suitable cleanup
5833 ldm[id][ab] r8!, {r0-r7}
5835 ldm[id][ab] r8, {r7-r14}
5838 but at present there's no suitable place for <temp>, since the scratch space
5839 is overwritten before the cleanup routine is called. For now, we simply
5840 emulate the instruction. */
5843 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5844 struct displaced_step_closure
*dsc
)
5846 int inc
= dsc
->u
.block
.increment
;
5847 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
5848 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
5849 uint32_t regmask
= dsc
->u
.block
.regmask
;
5850 int regno
= inc
? 0 : 15;
5851 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
5852 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
5853 && (regmask
& 0x8000) != 0;
5854 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5855 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
5856 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5861 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
5862 sensible we can do here. Complain loudly. */
5863 if (exception_return
)
5864 error (_("Cannot single-step exception return"));
5866 /* We don't handle any stores here for now. */
5867 gdb_assert (dsc
->u
.block
.load
!= 0);
5869 if (debug_displaced
)
5870 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
5871 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
5872 dsc
->u
.block
.increment
? "inc" : "dec",
5873 dsc
->u
.block
.before
? "before" : "after");
5880 while (regno
<= ARM_PC_REGNUM
&& (regmask
& (1 << regno
)) == 0)
5883 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
5886 xfer_addr
+= bump_before
;
5888 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
5889 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
5891 xfer_addr
+= bump_after
;
5893 regmask
&= ~(1 << regno
);
5896 if (dsc
->u
.block
.writeback
)
5897 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
5901 /* Clean up an STM which included the PC in the register list. */
5904 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5905 struct displaced_step_closure
*dsc
)
5907 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5908 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
5909 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
5910 CORE_ADDR stm_insn_addr
;
5913 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5915 /* If condition code fails, there's nothing else to do. */
5916 if (!store_executed
)
5919 if (dsc
->u
.block
.increment
)
5921 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
5923 if (dsc
->u
.block
.before
)
5928 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
5930 if (dsc
->u
.block
.before
)
5934 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
5935 stm_insn_addr
= dsc
->scratch_base
;
5936 offset
= pc_val
- stm_insn_addr
;
5938 if (debug_displaced
)
5939 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
5940 "STM instruction\n", offset
);
5942 /* Rewrite the stored PC to the proper value for the non-displaced original
5944 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
5945 dsc
->insn_addr
+ offset
);
5948 /* Clean up an LDM which includes the PC in the register list. We clumped all
5949 the registers in the transferred list into a contiguous range r0...rX (to
5950 avoid loading PC directly and losing control of the debugged program), so we
5951 must undo that here. */
5954 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
5955 struct regcache
*regs
,
5956 struct displaced_step_closure
*dsc
)
5958 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5959 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
);
5960 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= ARM_PC_REGNUM
;
5961 unsigned int regs_loaded
= bitcount (mask
);
5962 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
5964 /* The method employed here will fail if the register list is fully populated
5965 (we need to avoid loading PC directly). */
5966 gdb_assert (num_to_shuffle
< 16);
5971 clobbered
= (1 << num_to_shuffle
) - 1;
5973 while (num_to_shuffle
> 0)
5975 if ((mask
& (1 << write_reg
)) != 0)
5977 unsigned int read_reg
= num_to_shuffle
- 1;
5979 if (read_reg
!= write_reg
)
5981 ULONGEST rval
= displaced_read_reg (regs
, dsc
, read_reg
);
5982 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
5983 if (debug_displaced
)
5984 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
5985 "loaded register r%d to r%d\n"), read_reg
,
5988 else if (debug_displaced
)
5989 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
5990 "r%d already in the right place\n"),
5993 clobbered
&= ~(1 << write_reg
);
6001 /* Restore any registers we scribbled over. */
6002 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
6004 if ((clobbered
& (1 << write_reg
)) != 0)
6006 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
6008 if (debug_displaced
)
6009 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
6010 "clobbered register r%d\n"), write_reg
);
6011 clobbered
&= ~(1 << write_reg
);
6015 /* Perform register writeback manually. */
6016 if (dsc
->u
.block
.writeback
)
6018 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
6020 if (dsc
->u
.block
.increment
)
6021 new_rn_val
+= regs_loaded
* 4;
6023 new_rn_val
-= regs_loaded
* 4;
6025 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
6030 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
6031 in user-level code (in particular exception return, ldm rn, {...pc}^). */
6034 arm_copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
,
6035 struct regcache
*regs
,
6036 struct displaced_step_closure
*dsc
)
6038 int load
= bit (insn
, 20);
6039 int user
= bit (insn
, 22);
6040 int increment
= bit (insn
, 23);
6041 int before
= bit (insn
, 24);
6042 int writeback
= bit (insn
, 21);
6043 int rn
= bits (insn
, 16, 19);
6045 /* Block transfers which don't mention PC can be run directly
6047 if (rn
!= ARM_PC_REGNUM
&& (insn
& 0x8000) == 0)
6048 return arm_copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
6050 if (rn
== ARM_PC_REGNUM
)
6052 warning (_("displaced: Unpredictable LDM or STM with "
6053 "base register r15"));
6054 return arm_copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
6057 if (debug_displaced
)
6058 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6059 "%.8lx\n", (unsigned long) insn
);
6061 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6062 dsc
->u
.block
.rn
= rn
;
6064 dsc
->u
.block
.load
= load
;
6065 dsc
->u
.block
.user
= user
;
6066 dsc
->u
.block
.increment
= increment
;
6067 dsc
->u
.block
.before
= before
;
6068 dsc
->u
.block
.writeback
= writeback
;
6069 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
6071 dsc
->u
.block
.regmask
= insn
& 0xffff;
6075 if ((insn
& 0xffff) == 0xffff)
6077 /* LDM with a fully-populated register list. This case is
6078 particularly tricky. Implement for now by fully emulating the
6079 instruction (which might not behave perfectly in all cases, but
6080 these instructions should be rare enough for that not to matter
6082 dsc
->modinsn
[0] = ARM_NOP
;
6084 dsc
->cleanup
= &cleanup_block_load_all
;
6088 /* LDM of a list of registers which includes PC. Implement by
6089 rewriting the list of registers to be transferred into a
6090 contiguous chunk r0...rX before doing the transfer, then shuffling
6091 registers into the correct places in the cleanup routine. */
6092 unsigned int regmask
= insn
& 0xffff;
6093 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
6096 for (i
= 0; i
< num_in_list
; i
++)
6097 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6099 /* Writeback makes things complicated. We need to avoid clobbering
6100 the base register with one of the registers in our modified
6101 register list, but just using a different register can't work in
6104 ldm r14!, {r0-r13,pc}
6106 which would need to be rewritten as:
6110 but that can't work, because there's no free register for N.
6112 Solve this by turning off the writeback bit, and emulating
6113 writeback manually in the cleanup routine. */
6118 new_regmask
= (1 << num_in_list
) - 1;
6120 if (debug_displaced
)
6121 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6122 "{..., pc}: original reg list %.4x, modified "
6123 "list %.4x\n"), rn
, writeback
? "!" : "",
6124 (int) insn
& 0xffff, new_regmask
);
6126 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
6128 dsc
->cleanup
= &cleanup_block_load_pc
;
6133 /* STM of a list of registers which includes PC. Run the instruction
6134 as-is, but out of line: this will store the wrong value for the PC,
6135 so we must manually fix up the memory in the cleanup routine.
6136 Doing things this way has the advantage that we can auto-detect
6137 the offset of the PC write (which is architecture-dependent) in
6138 the cleanup routine. */
6139 dsc
->modinsn
[0] = insn
;
6141 dsc
->cleanup
= &cleanup_block_store_pc
;
6148 thumb2_copy_block_xfer (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6149 struct regcache
*regs
,
6150 struct displaced_step_closure
*dsc
)
6152 int rn
= bits (insn1
, 0, 3);
6153 int load
= bit (insn1
, 4);
6154 int writeback
= bit (insn1
, 5);
6156 /* Block transfers which don't mention PC can be run directly
6158 if (rn
!= ARM_PC_REGNUM
&& (insn2
& 0x8000) == 0)
6159 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ldm/stm", dsc
);
6161 if (rn
== ARM_PC_REGNUM
)
6163 warning (_("displaced: Unpredictable LDM or STM with "
6164 "base register r15"));
6165 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6166 "unpredictable ldm/stm", dsc
);
6169 if (debug_displaced
)
6170 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6171 "%.4x%.4x\n", insn1
, insn2
);
6173 /* Clear bit 13, since it should be always zero. */
6174 dsc
->u
.block
.regmask
= (insn2
& 0xdfff);
6175 dsc
->u
.block
.rn
= rn
;
6177 dsc
->u
.block
.load
= load
;
6178 dsc
->u
.block
.user
= 0;
6179 dsc
->u
.block
.increment
= bit (insn1
, 7);
6180 dsc
->u
.block
.before
= bit (insn1
, 8);
6181 dsc
->u
.block
.writeback
= writeback
;
6182 dsc
->u
.block
.cond
= INST_AL
;
6183 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6187 if (dsc
->u
.block
.regmask
== 0xffff)
6189 /* This branch is impossible to happen. */
6194 unsigned int regmask
= dsc
->u
.block
.regmask
;
6195 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
6198 for (i
= 0; i
< num_in_list
; i
++)
6199 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6204 new_regmask
= (1 << num_in_list
) - 1;
6206 if (debug_displaced
)
6207 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6208 "{..., pc}: original reg list %.4x, modified "
6209 "list %.4x\n"), rn
, writeback
? "!" : "",
6210 (int) dsc
->u
.block
.regmask
, new_regmask
);
6212 dsc
->modinsn
[0] = insn1
;
6213 dsc
->modinsn
[1] = (new_regmask
& 0xffff);
6216 dsc
->cleanup
= &cleanup_block_load_pc
;
6221 dsc
->modinsn
[0] = insn1
;
6222 dsc
->modinsn
[1] = insn2
;
6224 dsc
->cleanup
= &cleanup_block_store_pc
;
6229 /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs.
6230 This is used to avoid a dependency on BFD's bfd_endian enum. */
6233 arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr
, int len
,
6236 return read_memory_unsigned_integer (memaddr
, len
,
6237 (enum bfd_endian
) byte_order
);
6240 /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */
6243 arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs
*self
,
6246 return gdbarch_addr_bits_remove (get_regcache_arch (self
->regcache
), val
);
6249 /* Wrapper over syscall_next_pc for use in get_next_pcs. */
6252 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
)
6257 /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */
6260 arm_get_next_pcs_is_thumb (struct arm_get_next_pcs
*self
)
6262 return arm_is_thumb (self
->regcache
);
6265 /* single_step() is called just before we want to resume the inferior,
6266 if we want to single-step it but there is no hardware or kernel
6267 single-step support. We find the target of the coming instructions
6268 and breakpoint them. */
6271 arm_software_single_step (struct frame_info
*frame
)
6273 struct regcache
*regcache
= get_current_regcache ();
6274 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
6275 struct address_space
*aspace
= get_regcache_aspace (regcache
);
6276 struct arm_get_next_pcs next_pcs_ctx
;
6279 VEC (CORE_ADDR
) *next_pcs
= NULL
;
6280 struct cleanup
*old_chain
= make_cleanup (VEC_cleanup (CORE_ADDR
), &next_pcs
);
6282 arm_get_next_pcs_ctor (&next_pcs_ctx
,
6283 &arm_get_next_pcs_ops
,
6284 gdbarch_byte_order (gdbarch
),
6285 gdbarch_byte_order_for_code (gdbarch
),
6289 next_pcs
= arm_get_next_pcs (&next_pcs_ctx
);
6291 for (i
= 0; VEC_iterate (CORE_ADDR
, next_pcs
, i
, pc
); i
++)
6292 arm_insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
6294 do_cleanups (old_chain
);
6299 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
6300 for Linux, where some SVC instructions must be treated specially. */
6303 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6304 struct displaced_step_closure
*dsc
)
6306 CORE_ADDR resume_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
6308 if (debug_displaced
)
6309 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
6310 "%.8lx\n", (unsigned long) resume_addr
);
6312 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
6316 /* Common copy routine for svc instruciton. */
6319 install_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6320 struct displaced_step_closure
*dsc
)
6322 /* Preparation: none.
6323 Insn: unmodified svc.
6324 Cleanup: pc <- insn_addr + insn_size. */
6326 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
6328 dsc
->wrote_to_pc
= 1;
6330 /* Allow OS-specific code to override SVC handling. */
6331 if (dsc
->u
.svc
.copy_svc_os
)
6332 return dsc
->u
.svc
.copy_svc_os (gdbarch
, regs
, dsc
);
6335 dsc
->cleanup
= &cleanup_svc
;
6341 arm_copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
,
6342 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6345 if (debug_displaced
)
6346 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
6347 (unsigned long) insn
);
6349 dsc
->modinsn
[0] = insn
;
6351 return install_svc (gdbarch
, regs
, dsc
);
6355 thumb_copy_svc (struct gdbarch
*gdbarch
, uint16_t insn
,
6356 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6359 if (debug_displaced
)
6360 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.4x\n",
6363 dsc
->modinsn
[0] = insn
;
6365 return install_svc (gdbarch
, regs
, dsc
);
6368 /* Copy undefined instructions. */
6371 arm_copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
6372 struct displaced_step_closure
*dsc
)
6374 if (debug_displaced
)
6375 fprintf_unfiltered (gdb_stdlog
,
6376 "displaced: copying undefined insn %.8lx\n",
6377 (unsigned long) insn
);
6379 dsc
->modinsn
[0] = insn
;
6385 thumb_32bit_copy_undef (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6386 struct displaced_step_closure
*dsc
)
6389 if (debug_displaced
)
6390 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn "
6391 "%.4x %.4x\n", (unsigned short) insn1
,
6392 (unsigned short) insn2
);
6394 dsc
->modinsn
[0] = insn1
;
6395 dsc
->modinsn
[1] = insn2
;
6401 /* Copy unpredictable instructions. */
6404 arm_copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
6405 struct displaced_step_closure
*dsc
)
6407 if (debug_displaced
)
6408 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
6409 "%.8lx\n", (unsigned long) insn
);
6411 dsc
->modinsn
[0] = insn
;
6416 /* The decode_* functions are instruction decoding helpers. They mostly follow
6417 the presentation in the ARM ARM. */
6420 arm_decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
6421 struct regcache
*regs
,
6422 struct displaced_step_closure
*dsc
)
6424 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
6425 unsigned int rn
= bits (insn
, 16, 19);
6427 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
6428 return arm_copy_unmodified (gdbarch
, insn
, "cps", dsc
);
6429 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
6430 return arm_copy_unmodified (gdbarch
, insn
, "setend", dsc
);
6431 else if ((op1
& 0x60) == 0x20)
6432 return arm_copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
6433 else if ((op1
& 0x71) == 0x40)
6434 return arm_copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store",
6436 else if ((op1
& 0x77) == 0x41)
6437 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6438 else if ((op1
& 0x77) == 0x45)
6439 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
6440 else if ((op1
& 0x77) == 0x51)
6443 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6445 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6447 else if ((op1
& 0x77) == 0x55)
6448 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6449 else if (op1
== 0x57)
6452 case 0x1: return arm_copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
6453 case 0x4: return arm_copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
6454 case 0x5: return arm_copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
6455 case 0x6: return arm_copy_unmodified (gdbarch
, insn
, "isb", dsc
);
6456 default: return arm_copy_unpred (gdbarch
, insn
, dsc
);
6458 else if ((op1
& 0x63) == 0x43)
6459 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6460 else if ((op2
& 0x1) == 0x0)
6461 switch (op1
& ~0x80)
6464 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6466 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
6467 case 0x71: case 0x75:
6469 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
6470 case 0x63: case 0x67: case 0x73: case 0x77:
6471 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6473 return arm_copy_undef (gdbarch
, insn
, dsc
);
6476 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
6480 arm_decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
6481 struct regcache
*regs
,
6482 struct displaced_step_closure
*dsc
)
6484 if (bit (insn
, 27) == 0)
6485 return arm_decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
6486 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
6487 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
6490 return arm_copy_unmodified (gdbarch
, insn
, "srs", dsc
);
6493 return arm_copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
6495 case 0x4: case 0x5: case 0x6: case 0x7:
6496 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6499 switch ((insn
& 0xe00000) >> 21)
6501 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
6503 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6506 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6509 return arm_copy_undef (gdbarch
, insn
, dsc
);
6514 int rn_f
= (bits (insn
, 16, 19) == 0xf);
6515 switch ((insn
& 0xe00000) >> 21)
6518 /* ldc/ldc2 imm (undefined for rn == pc). */
6519 return rn_f
? arm_copy_undef (gdbarch
, insn
, dsc
)
6520 : arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6523 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6525 case 0x4: case 0x5: case 0x6: case 0x7:
6526 /* ldc/ldc2 lit (undefined for rn != pc). */
6527 return rn_f
? arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
6528 : arm_copy_undef (gdbarch
, insn
, dsc
);
6531 return arm_copy_undef (gdbarch
, insn
, dsc
);
6536 return arm_copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
6539 if (bits (insn
, 16, 19) == 0xf)
6541 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6543 return arm_copy_undef (gdbarch
, insn
, dsc
);
6547 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6549 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6553 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6555 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6558 return arm_copy_undef (gdbarch
, insn
, dsc
);
6562 /* Decode miscellaneous instructions in dp/misc encoding space. */
6565 arm_decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
6566 struct regcache
*regs
,
6567 struct displaced_step_closure
*dsc
)
6569 unsigned int op2
= bits (insn
, 4, 6);
6570 unsigned int op
= bits (insn
, 21, 22);
6575 return arm_copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
6578 if (op
== 0x1) /* bx. */
6579 return arm_copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
6581 return arm_copy_unmodified (gdbarch
, insn
, "clz", dsc
);
6583 return arm_copy_undef (gdbarch
, insn
, dsc
);
6587 /* Not really supported. */
6588 return arm_copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
6590 return arm_copy_undef (gdbarch
, insn
, dsc
);
6594 return arm_copy_bx_blx_reg (gdbarch
, insn
,
6595 regs
, dsc
); /* blx register. */
6597 return arm_copy_undef (gdbarch
, insn
, dsc
);
6600 return arm_copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
6604 return arm_copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
6606 /* Not really supported. */
6607 return arm_copy_unmodified (gdbarch
, insn
, "smc", dsc
);
6610 return arm_copy_undef (gdbarch
, insn
, dsc
);
6615 arm_decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
,
6616 struct regcache
*regs
,
6617 struct displaced_step_closure
*dsc
)
6620 switch (bits (insn
, 20, 24))
6623 return arm_copy_unmodified (gdbarch
, insn
, "movw", dsc
);
6626 return arm_copy_unmodified (gdbarch
, insn
, "movt", dsc
);
6628 case 0x12: case 0x16:
6629 return arm_copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
6632 return arm_copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
6636 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
6638 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
6639 return arm_copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
6640 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
6641 return arm_copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
6642 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
6643 return arm_decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
6644 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
6645 return arm_copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
6646 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
6647 return arm_copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
6648 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
6649 return arm_copy_unmodified (gdbarch
, insn
, "synch", dsc
);
6650 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
6651 /* 2nd arg means "unprivileged". */
6652 return arm_copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
6656 /* Should be unreachable. */
6661 arm_decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
6662 struct regcache
*regs
,
6663 struct displaced_step_closure
*dsc
)
6665 int a
= bit (insn
, 25), b
= bit (insn
, 4);
6666 uint32_t op1
= bits (insn
, 20, 24);
6668 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
6669 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
6670 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 0);
6671 else if ((!a
&& (op1
& 0x17) == 0x02)
6672 || (a
&& (op1
& 0x17) == 0x02 && !b
))
6673 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 1);
6674 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
6675 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
6676 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 0);
6677 else if ((!a
&& (op1
& 0x17) == 0x03)
6678 || (a
&& (op1
& 0x17) == 0x03 && !b
))
6679 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 1);
6680 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
6681 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
6682 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
6683 else if ((!a
&& (op1
& 0x17) == 0x06)
6684 || (a
&& (op1
& 0x17) == 0x06 && !b
))
6685 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
6686 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
6687 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
6688 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
6689 else if ((!a
&& (op1
& 0x17) == 0x07)
6690 || (a
&& (op1
& 0x17) == 0x07 && !b
))
6691 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
6693 /* Should be unreachable. */
6698 arm_decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
6699 struct displaced_step_closure
*dsc
)
6701 switch (bits (insn
, 20, 24))
6703 case 0x00: case 0x01: case 0x02: case 0x03:
6704 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
6706 case 0x04: case 0x05: case 0x06: case 0x07:
6707 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
6709 case 0x08: case 0x09: case 0x0a: case 0x0b:
6710 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
6711 return arm_copy_unmodified (gdbarch
, insn
,
6712 "decode/pack/unpack/saturate/reverse", dsc
);
6715 if (bits (insn
, 5, 7) == 0) /* op2. */
6717 if (bits (insn
, 12, 15) == 0xf)
6718 return arm_copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
6720 return arm_copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
6723 return arm_copy_undef (gdbarch
, insn
, dsc
);
6725 case 0x1a: case 0x1b:
6726 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6727 return arm_copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
6729 return arm_copy_undef (gdbarch
, insn
, dsc
);
6731 case 0x1c: case 0x1d:
6732 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
6734 if (bits (insn
, 0, 3) == 0xf)
6735 return arm_copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
6737 return arm_copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
6740 return arm_copy_undef (gdbarch
, insn
, dsc
);
6742 case 0x1e: case 0x1f:
6743 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6744 return arm_copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
6746 return arm_copy_undef (gdbarch
, insn
, dsc
);
6749 /* Should be unreachable. */
6754 arm_decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, uint32_t insn
,
6755 struct regcache
*regs
,
6756 struct displaced_step_closure
*dsc
)
6759 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6761 return arm_copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
6765 arm_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
6766 struct regcache
*regs
,
6767 struct displaced_step_closure
*dsc
)
6769 unsigned int opcode
= bits (insn
, 20, 24);
6773 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
6774 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
6776 case 0x08: case 0x0a: case 0x0c: case 0x0e:
6777 case 0x12: case 0x16:
6778 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
6780 case 0x09: case 0x0b: case 0x0d: case 0x0f:
6781 case 0x13: case 0x17:
6782 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
6784 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6785 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6786 /* Note: no writeback for these instructions. Bit 25 will always be
6787 zero though (via caller), so the following works OK. */
6788 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6791 /* Should be unreachable. */
6795 /* Decode shifted register instructions. */
6798 thumb2_decode_dp_shift_reg (struct gdbarch
*gdbarch
, uint16_t insn1
,
6799 uint16_t insn2
, struct regcache
*regs
,
6800 struct displaced_step_closure
*dsc
)
6802 /* PC is only allowed to be used in instruction MOV. */
6804 unsigned int op
= bits (insn1
, 5, 8);
6805 unsigned int rn
= bits (insn1
, 0, 3);
6807 if (op
== 0x2 && rn
== 0xf) /* MOV */
6808 return thumb2_copy_alu_imm (gdbarch
, insn1
, insn2
, regs
, dsc
);
6810 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6811 "dp (shift reg)", dsc
);
6815 /* Decode extension register load/store. Exactly the same as
6816 arm_decode_ext_reg_ld_st. */
6819 thumb2_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint16_t insn1
,
6820 uint16_t insn2
, struct regcache
*regs
,
6821 struct displaced_step_closure
*dsc
)
6823 unsigned int opcode
= bits (insn1
, 4, 8);
6827 case 0x04: case 0x05:
6828 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6829 "vfp/neon vmov", dsc
);
6831 case 0x08: case 0x0c: /* 01x00 */
6832 case 0x0a: case 0x0e: /* 01x10 */
6833 case 0x12: case 0x16: /* 10x10 */
6834 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6835 "vfp/neon vstm/vpush", dsc
);
6837 case 0x09: case 0x0d: /* 01x01 */
6838 case 0x0b: case 0x0f: /* 01x11 */
6839 case 0x13: case 0x17: /* 10x11 */
6840 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6841 "vfp/neon vldm/vpop", dsc
);
6843 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6844 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6846 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6847 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
, regs
, dsc
);
6850 /* Should be unreachable. */
6855 arm_decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
,
6856 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6858 unsigned int op1
= bits (insn
, 20, 25);
6859 int op
= bit (insn
, 4);
6860 unsigned int coproc
= bits (insn
, 8, 11);
6862 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
6863 return arm_decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
6864 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
6865 && (coproc
& 0xe) != 0xa)
6867 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6868 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
6869 && (coproc
& 0xe) != 0xa)
6870 /* ldc/ldc2 imm/lit. */
6871 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6872 else if ((op1
& 0x3e) == 0x00)
6873 return arm_copy_undef (gdbarch
, insn
, dsc
);
6874 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
6875 return arm_copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
6876 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
6877 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6878 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
6879 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6880 else if ((op1
& 0x30) == 0x20 && !op
)
6882 if ((coproc
& 0xe) == 0xa)
6883 return arm_copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
6885 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6887 else if ((op1
& 0x30) == 0x20 && op
)
6888 return arm_copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
6889 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
6890 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6891 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
6892 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6893 else if ((op1
& 0x30) == 0x30)
6894 return arm_copy_svc (gdbarch
, insn
, regs
, dsc
);
6896 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
6900 thumb2_decode_svc_copro (struct gdbarch
*gdbarch
, uint16_t insn1
,
6901 uint16_t insn2
, struct regcache
*regs
,
6902 struct displaced_step_closure
*dsc
)
6904 unsigned int coproc
= bits (insn2
, 8, 11);
6905 unsigned int bit_5_8
= bits (insn1
, 5, 8);
6906 unsigned int bit_9
= bit (insn1
, 9);
6907 unsigned int bit_4
= bit (insn1
, 4);
6912 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6913 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
6915 else if (bit_5_8
== 0) /* UNDEFINED. */
6916 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
6919 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
6920 if ((coproc
& 0xe) == 0xa)
6921 return thumb2_decode_ext_reg_ld_st (gdbarch
, insn1
, insn2
, regs
,
6923 else /* coproc is not 101x. */
6925 if (bit_4
== 0) /* STC/STC2. */
6926 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6928 else /* LDC/LDC2 {literal, immeidate}. */
6929 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
,
6935 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "coproc", dsc
);
6941 install_pc_relative (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6942 struct displaced_step_closure
*dsc
, int rd
)
6948 Preparation: Rd <- PC
6954 int val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
6955 displaced_write_reg (regs
, dsc
, rd
, val
, CANNOT_WRITE_PC
);
6959 thumb_copy_pc_relative_16bit (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6960 struct displaced_step_closure
*dsc
,
6961 int rd
, unsigned int imm
)
6964 /* Encoding T2: ADDS Rd, #imm */
6965 dsc
->modinsn
[0] = (0x3000 | (rd
<< 8) | imm
);
6967 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
6973 thumb_decode_pc_relative_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
6974 struct regcache
*regs
,
6975 struct displaced_step_closure
*dsc
)
6977 unsigned int rd
= bits (insn
, 8, 10);
6978 unsigned int imm8
= bits (insn
, 0, 7);
6980 if (debug_displaced
)
6981 fprintf_unfiltered (gdb_stdlog
,
6982 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
6985 return thumb_copy_pc_relative_16bit (gdbarch
, regs
, dsc
, rd
, imm8
);
6989 thumb_copy_pc_relative_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
6990 uint16_t insn2
, struct regcache
*regs
,
6991 struct displaced_step_closure
*dsc
)
6993 unsigned int rd
= bits (insn2
, 8, 11);
6994 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
6995 extract raw immediate encoding rather than computing immediate. When
6996 generating ADD or SUB instruction, we can simply perform OR operation to
6997 set immediate into ADD. */
6998 unsigned int imm_3_8
= insn2
& 0x70ff;
6999 unsigned int imm_i
= insn1
& 0x0400; /* Clear all bits except bit 10. */
7001 if (debug_displaced
)
7002 fprintf_unfiltered (gdb_stdlog
,
7003 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
7004 rd
, imm_i
, imm_3_8
, insn1
, insn2
);
7006 if (bit (insn1
, 7)) /* Encoding T2 */
7008 /* Encoding T3: SUB Rd, Rd, #imm */
7009 dsc
->modinsn
[0] = (0xf1a0 | rd
| imm_i
);
7010 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7012 else /* Encoding T3 */
7014 /* Encoding T3: ADD Rd, Rd, #imm */
7015 dsc
->modinsn
[0] = (0xf100 | rd
| imm_i
);
7016 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7020 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
7026 thumb_copy_16bit_ldr_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
7027 struct regcache
*regs
,
7028 struct displaced_step_closure
*dsc
)
7030 unsigned int rt
= bits (insn1
, 8, 10);
7032 int imm8
= (bits (insn1
, 0, 7) << 2);
7038 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
7040 Insn: LDR R0, [R2, R3];
7041 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
7043 if (debug_displaced
)
7044 fprintf_unfiltered (gdb_stdlog
,
7045 "displaced: copying thumb ldr r%d [pc #%d]\n"
7048 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
7049 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
7050 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
7051 pc
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
7052 /* The assembler calculates the required value of the offset from the
7053 Align(PC,4) value of this instruction to the label. */
7054 pc
= pc
& 0xfffffffc;
7056 displaced_write_reg (regs
, dsc
, 2, pc
, CANNOT_WRITE_PC
);
7057 displaced_write_reg (regs
, dsc
, 3, imm8
, CANNOT_WRITE_PC
);
7060 dsc
->u
.ldst
.xfersize
= 4;
7062 dsc
->u
.ldst
.immed
= 0;
7063 dsc
->u
.ldst
.writeback
= 0;
7064 dsc
->u
.ldst
.restore_r4
= 0;
7066 dsc
->modinsn
[0] = 0x58d0; /* ldr r0, [r2, r3]*/
7068 dsc
->cleanup
= &cleanup_load
;
7073 /* Copy Thumb cbnz/cbz insruction. */
7076 thumb_copy_cbnz_cbz (struct gdbarch
*gdbarch
, uint16_t insn1
,
7077 struct regcache
*regs
,
7078 struct displaced_step_closure
*dsc
)
7080 int non_zero
= bit (insn1
, 11);
7081 unsigned int imm5
= (bit (insn1
, 9) << 6) | (bits (insn1
, 3, 7) << 1);
7082 CORE_ADDR from
= dsc
->insn_addr
;
7083 int rn
= bits (insn1
, 0, 2);
7084 int rn_val
= displaced_read_reg (regs
, dsc
, rn
);
7086 dsc
->u
.branch
.cond
= (rn_val
&& non_zero
) || (!rn_val
&& !non_zero
);
7087 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
7088 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
7089 condition is false, let it be, cleanup_branch will do nothing. */
7090 if (dsc
->u
.branch
.cond
)
7092 dsc
->u
.branch
.cond
= INST_AL
;
7093 dsc
->u
.branch
.dest
= from
+ 4 + imm5
;
7096 dsc
->u
.branch
.dest
= from
+ 2;
7098 dsc
->u
.branch
.link
= 0;
7099 dsc
->u
.branch
.exchange
= 0;
7101 if (debug_displaced
)
7102 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s [r%d = 0x%x]"
7103 " insn %.4x to %.8lx\n", non_zero
? "cbnz" : "cbz",
7104 rn
, rn_val
, insn1
, dsc
->u
.branch
.dest
);
7106 dsc
->modinsn
[0] = THUMB_NOP
;
7108 dsc
->cleanup
= &cleanup_branch
;
7112 /* Copy Table Branch Byte/Halfword */
7114 thumb2_copy_table_branch (struct gdbarch
*gdbarch
, uint16_t insn1
,
7115 uint16_t insn2
, struct regcache
*regs
,
7116 struct displaced_step_closure
*dsc
)
7118 ULONGEST rn_val
, rm_val
;
7119 int is_tbh
= bit (insn2
, 4);
7120 CORE_ADDR halfwords
= 0;
7121 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7123 rn_val
= displaced_read_reg (regs
, dsc
, bits (insn1
, 0, 3));
7124 rm_val
= displaced_read_reg (regs
, dsc
, bits (insn2
, 0, 3));
7130 target_read_memory (rn_val
+ 2 * rm_val
, buf
, 2);
7131 halfwords
= extract_unsigned_integer (buf
, 2, byte_order
);
7137 target_read_memory (rn_val
+ rm_val
, buf
, 1);
7138 halfwords
= extract_unsigned_integer (buf
, 1, byte_order
);
7141 if (debug_displaced
)
7142 fprintf_unfiltered (gdb_stdlog
, "displaced: %s base 0x%x offset 0x%x"
7143 " offset 0x%x\n", is_tbh
? "tbh" : "tbb",
7144 (unsigned int) rn_val
, (unsigned int) rm_val
,
7145 (unsigned int) halfwords
);
7147 dsc
->u
.branch
.cond
= INST_AL
;
7148 dsc
->u
.branch
.link
= 0;
7149 dsc
->u
.branch
.exchange
= 0;
7150 dsc
->u
.branch
.dest
= dsc
->insn_addr
+ 4 + 2 * halfwords
;
7152 dsc
->cleanup
= &cleanup_branch
;
7158 cleanup_pop_pc_16bit_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7159 struct displaced_step_closure
*dsc
)
7162 int val
= displaced_read_reg (regs
, dsc
, 7);
7163 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, val
, BX_WRITE_PC
);
7166 val
= displaced_read_reg (regs
, dsc
, 8);
7167 displaced_write_reg (regs
, dsc
, 7, val
, CANNOT_WRITE_PC
);
7170 displaced_write_reg (regs
, dsc
, 8, dsc
->tmp
[0], CANNOT_WRITE_PC
);
7175 thumb_copy_pop_pc_16bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
7176 struct regcache
*regs
,
7177 struct displaced_step_closure
*dsc
)
7179 dsc
->u
.block
.regmask
= insn1
& 0x00ff;
7181 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
7184 (1) register list is full, that is, r0-r7 are used.
7185 Prepare: tmp[0] <- r8
7187 POP {r0, r1, ...., r6, r7}; remove PC from reglist
7188 MOV r8, r7; Move value of r7 to r8;
7189 POP {r7}; Store PC value into r7.
7191 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
7193 (2) register list is not full, supposing there are N registers in
7194 register list (except PC, 0 <= N <= 7).
7195 Prepare: for each i, 0 - N, tmp[i] <- ri.
7197 POP {r0, r1, ...., rN};
7199 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
7200 from tmp[] properly.
7202 if (debug_displaced
)
7203 fprintf_unfiltered (gdb_stdlog
,
7204 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
7205 dsc
->u
.block
.regmask
, insn1
);
7207 if (dsc
->u
.block
.regmask
== 0xff)
7209 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 8);
7211 dsc
->modinsn
[0] = (insn1
& 0xfeff); /* POP {r0,r1,...,r6, r7} */
7212 dsc
->modinsn
[1] = 0x46b8; /* MOV r8, r7 */
7213 dsc
->modinsn
[2] = 0xbc80; /* POP {r7} */
7216 dsc
->cleanup
= &cleanup_pop_pc_16bit_all
;
7220 unsigned int num_in_list
= bitcount (dsc
->u
.block
.regmask
);
7222 unsigned int new_regmask
;
7224 for (i
= 0; i
< num_in_list
+ 1; i
++)
7225 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7227 new_regmask
= (1 << (num_in_list
+ 1)) - 1;
7229 if (debug_displaced
)
7230 fprintf_unfiltered (gdb_stdlog
, _("displaced: POP "
7231 "{..., pc}: original reg list %.4x,"
7232 " modified list %.4x\n"),
7233 (int) dsc
->u
.block
.regmask
, new_regmask
);
7235 dsc
->u
.block
.regmask
|= 0x8000;
7236 dsc
->u
.block
.writeback
= 0;
7237 dsc
->u
.block
.cond
= INST_AL
;
7239 dsc
->modinsn
[0] = (insn1
& ~0x1ff) | (new_regmask
& 0xff);
7241 dsc
->cleanup
= &cleanup_block_load_pc
;
7248 thumb_process_displaced_16bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7249 struct regcache
*regs
,
7250 struct displaced_step_closure
*dsc
)
7252 unsigned short op_bit_12_15
= bits (insn1
, 12, 15);
7253 unsigned short op_bit_10_11
= bits (insn1
, 10, 11);
7256 /* 16-bit thumb instructions. */
7257 switch (op_bit_12_15
)
7259 /* Shift (imme), add, subtract, move and compare. */
7260 case 0: case 1: case 2: case 3:
7261 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7262 "shift/add/sub/mov/cmp",
7266 switch (op_bit_10_11
)
7268 case 0: /* Data-processing */
7269 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7273 case 1: /* Special data instructions and branch and exchange. */
7275 unsigned short op
= bits (insn1
, 7, 9);
7276 if (op
== 6 || op
== 7) /* BX or BLX */
7277 err
= thumb_copy_bx_blx_reg (gdbarch
, insn1
, regs
, dsc
);
7278 else if (bits (insn1
, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
7279 err
= thumb_copy_alu_reg (gdbarch
, insn1
, regs
, dsc
);
7281 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "special data",
7285 default: /* LDR (literal) */
7286 err
= thumb_copy_16bit_ldr_literal (gdbarch
, insn1
, regs
, dsc
);
7289 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
7290 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldr/str", dsc
);
7293 if (op_bit_10_11
< 2) /* Generate PC-relative address */
7294 err
= thumb_decode_pc_relative_16bit (gdbarch
, insn1
, regs
, dsc
);
7295 else /* Generate SP-relative address */
7296 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "sp-relative", dsc
);
7298 case 11: /* Misc 16-bit instructions */
7300 switch (bits (insn1
, 8, 11))
7302 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
7303 err
= thumb_copy_cbnz_cbz (gdbarch
, insn1
, regs
, dsc
);
7305 case 12: case 13: /* POP */
7306 if (bit (insn1
, 8)) /* PC is in register list. */
7307 err
= thumb_copy_pop_pc_16bit (gdbarch
, insn1
, regs
, dsc
);
7309 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "pop", dsc
);
7311 case 15: /* If-Then, and hints */
7312 if (bits (insn1
, 0, 3))
7313 /* If-Then makes up to four following instructions conditional.
7314 IT instruction itself is not conditional, so handle it as a
7315 common unmodified instruction. */
7316 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "If-Then",
7319 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "hints", dsc
);
7322 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "misc", dsc
);
7327 if (op_bit_10_11
< 2) /* Store multiple registers */
7328 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "stm", dsc
);
7329 else /* Load multiple registers */
7330 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldm", dsc
);
7332 case 13: /* Conditional branch and supervisor call */
7333 if (bits (insn1
, 9, 11) != 7) /* conditional branch */
7334 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7336 err
= thumb_copy_svc (gdbarch
, insn1
, regs
, dsc
);
7338 case 14: /* Unconditional branch */
7339 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7346 internal_error (__FILE__
, __LINE__
,
7347 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
7351 decode_thumb_32bit_ld_mem_hints (struct gdbarch
*gdbarch
,
7352 uint16_t insn1
, uint16_t insn2
,
7353 struct regcache
*regs
,
7354 struct displaced_step_closure
*dsc
)
7356 int rt
= bits (insn2
, 12, 15);
7357 int rn
= bits (insn1
, 0, 3);
7358 int op1
= bits (insn1
, 7, 8);
7360 switch (bits (insn1
, 5, 6))
7362 case 0: /* Load byte and memory hints */
7363 if (rt
== 0xf) /* PLD/PLI */
7366 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
7367 return thumb2_copy_preload (gdbarch
, insn1
, insn2
, regs
, dsc
);
7369 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7374 if (rn
== 0xf) /* LDRB/LDRSB (literal) */
7375 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7378 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7379 "ldrb{reg, immediate}/ldrbt",
7384 case 1: /* Load halfword and memory hints. */
7385 if (rt
== 0xf) /* PLD{W} and Unalloc memory hint. */
7386 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7387 "pld/unalloc memhint", dsc
);
7391 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7394 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7398 case 2: /* Load word */
7400 int insn2_bit_8_11
= bits (insn2
, 8, 11);
7403 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
, 4);
7404 else if (op1
== 0x1) /* Encoding T3 */
7405 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
, dsc
,
7407 else /* op1 == 0x0 */
7409 if (insn2_bit_8_11
== 0xc || (insn2_bit_8_11
& 0x9) == 0x9)
7410 /* LDR (immediate) */
7411 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7412 dsc
, bit (insn2
, 8), 1);
7413 else if (insn2_bit_8_11
== 0xe) /* LDRT */
7414 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7417 /* LDR (register) */
7418 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7424 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
7431 thumb_process_displaced_32bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7432 uint16_t insn2
, struct regcache
*regs
,
7433 struct displaced_step_closure
*dsc
)
7436 unsigned short op
= bit (insn2
, 15);
7437 unsigned int op1
= bits (insn1
, 11, 12);
7443 switch (bits (insn1
, 9, 10))
7448 /* Load/store {dual, execlusive}, table branch. */
7449 if (bits (insn1
, 7, 8) == 1 && bits (insn1
, 4, 5) == 1
7450 && bits (insn2
, 5, 7) == 0)
7451 err
= thumb2_copy_table_branch (gdbarch
, insn1
, insn2
, regs
,
7454 /* PC is not allowed to use in load/store {dual, exclusive}
7456 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7457 "load/store dual/ex", dsc
);
7459 else /* load/store multiple */
7461 switch (bits (insn1
, 7, 8))
7463 case 0: case 3: /* SRS, RFE */
7464 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7467 case 1: case 2: /* LDM/STM/PUSH/POP */
7468 err
= thumb2_copy_block_xfer (gdbarch
, insn1
, insn2
, regs
, dsc
);
7475 /* Data-processing (shift register). */
7476 err
= thumb2_decode_dp_shift_reg (gdbarch
, insn1
, insn2
, regs
,
7479 default: /* Coprocessor instructions. */
7480 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7485 case 2: /* op1 = 2 */
7486 if (op
) /* Branch and misc control. */
7488 if (bit (insn2
, 14) /* BLX/BL */
7489 || bit (insn2
, 12) /* Unconditional branch */
7490 || (bits (insn1
, 7, 9) != 0x7)) /* Conditional branch */
7491 err
= thumb2_copy_b_bl_blx (gdbarch
, insn1
, insn2
, regs
, dsc
);
7493 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7498 if (bit (insn1
, 9)) /* Data processing (plain binary imm). */
7500 int op
= bits (insn1
, 4, 8);
7501 int rn
= bits (insn1
, 0, 3);
7502 if ((op
== 0 || op
== 0xa) && rn
== 0xf)
7503 err
= thumb_copy_pc_relative_32bit (gdbarch
, insn1
, insn2
,
7506 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7509 else /* Data processing (modified immeidate) */
7510 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7514 case 3: /* op1 = 3 */
7515 switch (bits (insn1
, 9, 10))
7519 err
= decode_thumb_32bit_ld_mem_hints (gdbarch
, insn1
, insn2
,
7521 else /* NEON Load/Store and Store single data item */
7522 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7523 "neon elt/struct load/store",
7526 case 1: /* op1 = 3, bits (9, 10) == 1 */
7527 switch (bits (insn1
, 7, 8))
7529 case 0: case 1: /* Data processing (register) */
7530 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7533 case 2: /* Multiply and absolute difference */
7534 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7535 "mul/mua/diff", dsc
);
7537 case 3: /* Long multiply and divide */
7538 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7543 default: /* Coprocessor instructions */
7544 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7553 internal_error (__FILE__
, __LINE__
,
7554 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
7559 thumb_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7560 struct regcache
*regs
,
7561 struct displaced_step_closure
*dsc
)
7563 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7565 = read_memory_unsigned_integer (from
, 2, byte_order_for_code
);
7567 if (debug_displaced
)
7568 fprintf_unfiltered (gdb_stdlog
, "displaced: process thumb insn %.4x "
7569 "at %.8lx\n", insn1
, (unsigned long) from
);
7572 dsc
->insn_size
= thumb_insn_size (insn1
);
7573 if (thumb_insn_size (insn1
) == 4)
7576 = read_memory_unsigned_integer (from
+ 2, 2, byte_order_for_code
);
7577 thumb_process_displaced_32bit_insn (gdbarch
, insn1
, insn2
, regs
, dsc
);
7580 thumb_process_displaced_16bit_insn (gdbarch
, insn1
, regs
, dsc
);
7584 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7585 CORE_ADDR to
, struct regcache
*regs
,
7586 struct displaced_step_closure
*dsc
)
7589 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7592 /* Most displaced instructions use a 1-instruction scratch space, so set this
7593 here and override below if/when necessary. */
7595 dsc
->insn_addr
= from
;
7596 dsc
->scratch_base
= to
;
7597 dsc
->cleanup
= NULL
;
7598 dsc
->wrote_to_pc
= 0;
7600 if (!displaced_in_arm_mode (regs
))
7601 return thumb_process_displaced_insn (gdbarch
, from
, regs
, dsc
);
7605 insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
7606 if (debug_displaced
)
7607 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
7608 "at %.8lx\n", (unsigned long) insn
,
7609 (unsigned long) from
);
7611 if ((insn
& 0xf0000000) == 0xf0000000)
7612 err
= arm_decode_unconditional (gdbarch
, insn
, regs
, dsc
);
7613 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
7615 case 0x0: case 0x1: case 0x2: case 0x3:
7616 err
= arm_decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
7619 case 0x4: case 0x5: case 0x6:
7620 err
= arm_decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
7624 err
= arm_decode_media (gdbarch
, insn
, dsc
);
7627 case 0x8: case 0x9: case 0xa: case 0xb:
7628 err
= arm_decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
7631 case 0xc: case 0xd: case 0xe: case 0xf:
7632 err
= arm_decode_svc_copro (gdbarch
, insn
, regs
, dsc
);
7637 internal_error (__FILE__
, __LINE__
,
7638 _("arm_process_displaced_insn: Instruction decode error"));
7641 /* Actually set up the scratch space for a displaced instruction. */
7644 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7645 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
7647 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7648 unsigned int i
, len
, offset
;
7649 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7650 int size
= dsc
->is_thumb
? 2 : 4;
7651 const gdb_byte
*bkp_insn
;
7654 /* Poke modified instruction(s). */
7655 for (i
= 0; i
< dsc
->numinsns
; i
++)
7657 if (debug_displaced
)
7659 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn ");
7661 fprintf_unfiltered (gdb_stdlog
, "%.8lx",
7664 fprintf_unfiltered (gdb_stdlog
, "%.4x",
7665 (unsigned short)dsc
->modinsn
[i
]);
7667 fprintf_unfiltered (gdb_stdlog
, " at %.8lx\n",
7668 (unsigned long) to
+ offset
);
7671 write_memory_unsigned_integer (to
+ offset
, size
,
7672 byte_order_for_code
,
7677 /* Choose the correct breakpoint instruction. */
7680 bkp_insn
= tdep
->thumb_breakpoint
;
7681 len
= tdep
->thumb_breakpoint_size
;
7685 bkp_insn
= tdep
->arm_breakpoint
;
7686 len
= tdep
->arm_breakpoint_size
;
7689 /* Put breakpoint afterwards. */
7690 write_memory (to
+ offset
, bkp_insn
, len
);
7692 if (debug_displaced
)
7693 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
7694 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
7697 /* Entry point for cleaning things up after a displaced instruction has been
7701 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
7702 struct displaced_step_closure
*dsc
,
7703 CORE_ADDR from
, CORE_ADDR to
,
7704 struct regcache
*regs
)
7707 dsc
->cleanup (gdbarch
, regs
, dsc
);
7709 if (!dsc
->wrote_to_pc
)
7710 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
7711 dsc
->insn_addr
+ dsc
->insn_size
);
7715 #include "bfd-in2.h"
7716 #include "libcoff.h"
7719 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
7721 struct gdbarch
*gdbarch
= (struct gdbarch
*) info
->application_data
;
7723 if (arm_pc_is_thumb (gdbarch
, memaddr
))
7725 static asymbol
*asym
;
7726 static combined_entry_type ce
;
7727 static struct coff_symbol_struct csym
;
7728 static struct bfd fake_bfd
;
7729 static bfd_target fake_target
;
7731 if (csym
.native
== NULL
)
7733 /* Create a fake symbol vector containing a Thumb symbol.
7734 This is solely so that the code in print_insn_little_arm()
7735 and print_insn_big_arm() in opcodes/arm-dis.c will detect
7736 the presence of a Thumb symbol and switch to decoding
7737 Thumb instructions. */
7739 fake_target
.flavour
= bfd_target_coff_flavour
;
7740 fake_bfd
.xvec
= &fake_target
;
7741 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
7743 csym
.symbol
.the_bfd
= &fake_bfd
;
7744 csym
.symbol
.name
= "fake";
7745 asym
= (asymbol
*) & csym
;
7748 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
7749 info
->symbols
= &asym
;
7752 info
->symbols
= NULL
;
7754 if (info
->endian
== BFD_ENDIAN_BIG
)
7755 return print_insn_big_arm (memaddr
, info
);
7757 return print_insn_little_arm (memaddr
, info
);
7760 /* The following define instruction sequences that will cause ARM
7761 cpu's to take an undefined instruction trap. These are used to
7762 signal a breakpoint to GDB.
7764 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
7765 modes. A different instruction is required for each mode. The ARM
7766 cpu's can also be big or little endian. Thus four different
7767 instructions are needed to support all cases.
7769 Note: ARMv4 defines several new instructions that will take the
7770 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
7771 not in fact add the new instructions. The new undefined
7772 instructions in ARMv4 are all instructions that had no defined
7773 behaviour in earlier chips. There is no guarantee that they will
7774 raise an exception, but may be treated as NOP's. In practice, it
7775 may only safe to rely on instructions matching:
7777 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
7778 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
7779 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
7781 Even this may only true if the condition predicate is true. The
7782 following use a condition predicate of ALWAYS so it is always TRUE.
7784 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
7785 and NetBSD all use a software interrupt rather than an undefined
7786 instruction to force a trap. This can be handled by by the
7787 abi-specific code during establishment of the gdbarch vector. */
7789 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
7790 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
7791 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
7792 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
7794 static const gdb_byte arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
7795 static const gdb_byte arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
7796 static const gdb_byte arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
7797 static const gdb_byte arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
7799 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
7800 the program counter value to determine whether a 16-bit or 32-bit
7801 breakpoint should be used. It returns a pointer to a string of
7802 bytes that encode a breakpoint instruction, stores the length of
7803 the string to *lenptr, and adjusts the program counter (if
7804 necessary) to point to the actual memory location where the
7805 breakpoint should be inserted. */
7807 static const unsigned char *
7808 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
7810 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7811 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7813 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
7815 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
7817 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
7818 check whether we are replacing a 32-bit instruction. */
7819 if (tdep
->thumb2_breakpoint
!= NULL
)
7822 if (target_read_memory (*pcptr
, buf
, 2) == 0)
7824 unsigned short inst1
;
7825 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
7826 if (thumb_insn_size (inst1
) == 4)
7828 *lenptr
= tdep
->thumb2_breakpoint_size
;
7829 return tdep
->thumb2_breakpoint
;
7834 *lenptr
= tdep
->thumb_breakpoint_size
;
7835 return tdep
->thumb_breakpoint
;
7839 *lenptr
= tdep
->arm_breakpoint_size
;
7840 return tdep
->arm_breakpoint
;
7845 arm_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
7848 arm_breakpoint_from_pc (gdbarch
, pcptr
, kindptr
);
7850 if (arm_pc_is_thumb (gdbarch
, *pcptr
) && *kindptr
== 4)
7851 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
7852 that this is not confused with a 32-bit ARM breakpoint. */
7856 /* Extract from an array REGBUF containing the (raw) register state a
7857 function return value of type TYPE, and copy that, in virtual
7858 format, into VALBUF. */
7861 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
7864 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
7865 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7867 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
7869 switch (gdbarch_tdep (gdbarch
)->fp_model
)
7873 /* The value is in register F0 in internal format. We need to
7874 extract the raw value and then convert it to the desired
7876 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
7878 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
7879 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
7880 valbuf
, gdbarch_byte_order (gdbarch
));
7884 case ARM_FLOAT_SOFT_FPA
:
7885 case ARM_FLOAT_SOFT_VFP
:
7886 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7887 not using the VFP ABI code. */
7889 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
7890 if (TYPE_LENGTH (type
) > 4)
7891 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
7892 valbuf
+ INT_REGISTER_SIZE
);
7896 internal_error (__FILE__
, __LINE__
,
7897 _("arm_extract_return_value: "
7898 "Floating point model not supported"));
7902 else if (TYPE_CODE (type
) == TYPE_CODE_INT
7903 || TYPE_CODE (type
) == TYPE_CODE_CHAR
7904 || TYPE_CODE (type
) == TYPE_CODE_BOOL
7905 || TYPE_CODE (type
) == TYPE_CODE_PTR
7906 || TYPE_CODE (type
) == TYPE_CODE_REF
7907 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
7909 /* If the type is a plain integer, then the access is
7910 straight-forward. Otherwise we have to play around a bit
7912 int len
= TYPE_LENGTH (type
);
7913 int regno
= ARM_A1_REGNUM
;
7918 /* By using store_unsigned_integer we avoid having to do
7919 anything special for small big-endian values. */
7920 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
7921 store_unsigned_integer (valbuf
,
7922 (len
> INT_REGISTER_SIZE
7923 ? INT_REGISTER_SIZE
: len
),
7925 len
-= INT_REGISTER_SIZE
;
7926 valbuf
+= INT_REGISTER_SIZE
;
7931 /* For a structure or union the behaviour is as if the value had
7932 been stored to word-aligned memory and then loaded into
7933 registers with 32-bit load instruction(s). */
7934 int len
= TYPE_LENGTH (type
);
7935 int regno
= ARM_A1_REGNUM
;
7936 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
7940 regcache_cooked_read (regs
, regno
++, tmpbuf
);
7941 memcpy (valbuf
, tmpbuf
,
7942 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
7943 len
-= INT_REGISTER_SIZE
;
7944 valbuf
+= INT_REGISTER_SIZE
;
7950 /* Will a function return an aggregate type in memory or in a
7951 register? Return 0 if an aggregate type can be returned in a
7952 register, 1 if it must be returned in memory. */
7955 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
7957 enum type_code code
;
7959 type
= check_typedef (type
);
7961 /* Simple, non-aggregate types (ie not including vectors and
7962 complex) are always returned in a register (or registers). */
7963 code
= TYPE_CODE (type
);
7964 if (TYPE_CODE_STRUCT
!= code
&& TYPE_CODE_UNION
!= code
7965 && TYPE_CODE_ARRAY
!= code
&& TYPE_CODE_COMPLEX
!= code
)
7968 if (TYPE_CODE_ARRAY
== code
&& TYPE_VECTOR (type
))
7970 /* Vector values should be returned using ARM registers if they
7971 are not over 16 bytes. */
7972 return (TYPE_LENGTH (type
) > 16);
7975 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
7977 /* The AAPCS says all aggregates not larger than a word are returned
7979 if (TYPE_LENGTH (type
) <= INT_REGISTER_SIZE
)
7988 /* All aggregate types that won't fit in a register must be returned
7990 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
7993 /* In the ARM ABI, "integer" like aggregate types are returned in
7994 registers. For an aggregate type to be integer like, its size
7995 must be less than or equal to INT_REGISTER_SIZE and the
7996 offset of each addressable subfield must be zero. Note that bit
7997 fields are not addressable, and all addressable subfields of
7998 unions always start at offset zero.
8000 This function is based on the behaviour of GCC 2.95.1.
8001 See: gcc/arm.c: arm_return_in_memory() for details.
8003 Note: All versions of GCC before GCC 2.95.2 do not set up the
8004 parameters correctly for a function returning the following
8005 structure: struct { float f;}; This should be returned in memory,
8006 not a register. Richard Earnshaw sent me a patch, but I do not
8007 know of any way to detect if a function like the above has been
8008 compiled with the correct calling convention. */
8010 /* Assume all other aggregate types can be returned in a register.
8011 Run a check for structures, unions and arrays. */
8014 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
8017 /* Need to check if this struct/union is "integer" like. For
8018 this to be true, its size must be less than or equal to
8019 INT_REGISTER_SIZE and the offset of each addressable
8020 subfield must be zero. Note that bit fields are not
8021 addressable, and unions always start at offset zero. If any
8022 of the subfields is a floating point type, the struct/union
8023 cannot be an integer type. */
8025 /* For each field in the object, check:
8026 1) Is it FP? --> yes, nRc = 1;
8027 2) Is it addressable (bitpos != 0) and
8028 not packed (bitsize == 0)?
8032 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
8034 enum type_code field_type_code
;
8037 = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
,
8040 /* Is it a floating point type field? */
8041 if (field_type_code
== TYPE_CODE_FLT
)
8047 /* If bitpos != 0, then we have to care about it. */
8048 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
8050 /* Bitfields are not addressable. If the field bitsize is
8051 zero, then the field is not packed. Hence it cannot be
8052 a bitfield or any other packed type. */
8053 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
8066 /* Write into appropriate registers a function return value of type
8067 TYPE, given in virtual format. */
8070 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
8071 const gdb_byte
*valbuf
)
8073 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
8074 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8076 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
8078 gdb_byte buf
[MAX_REGISTER_SIZE
];
8080 switch (gdbarch_tdep (gdbarch
)->fp_model
)
8084 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
8085 gdbarch_byte_order (gdbarch
));
8086 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
8089 case ARM_FLOAT_SOFT_FPA
:
8090 case ARM_FLOAT_SOFT_VFP
:
8091 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8092 not using the VFP ABI code. */
8094 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
8095 if (TYPE_LENGTH (type
) > 4)
8096 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
8097 valbuf
+ INT_REGISTER_SIZE
);
8101 internal_error (__FILE__
, __LINE__
,
8102 _("arm_store_return_value: Floating "
8103 "point model not supported"));
8107 else if (TYPE_CODE (type
) == TYPE_CODE_INT
8108 || TYPE_CODE (type
) == TYPE_CODE_CHAR
8109 || TYPE_CODE (type
) == TYPE_CODE_BOOL
8110 || TYPE_CODE (type
) == TYPE_CODE_PTR
8111 || TYPE_CODE (type
) == TYPE_CODE_REF
8112 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
8114 if (TYPE_LENGTH (type
) <= 4)
8116 /* Values of one word or less are zero/sign-extended and
8118 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8119 LONGEST val
= unpack_long (type
, valbuf
);
8121 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
8122 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
8126 /* Integral values greater than one word are stored in consecutive
8127 registers starting with r0. This will always be a multiple of
8128 the regiser size. */
8129 int len
= TYPE_LENGTH (type
);
8130 int regno
= ARM_A1_REGNUM
;
8134 regcache_cooked_write (regs
, regno
++, valbuf
);
8135 len
-= INT_REGISTER_SIZE
;
8136 valbuf
+= INT_REGISTER_SIZE
;
8142 /* For a structure or union the behaviour is as if the value had
8143 been stored to word-aligned memory and then loaded into
8144 registers with 32-bit load instruction(s). */
8145 int len
= TYPE_LENGTH (type
);
8146 int regno
= ARM_A1_REGNUM
;
8147 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8151 memcpy (tmpbuf
, valbuf
,
8152 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
8153 regcache_cooked_write (regs
, regno
++, tmpbuf
);
8154 len
-= INT_REGISTER_SIZE
;
8155 valbuf
+= INT_REGISTER_SIZE
;
8161 /* Handle function return values. */
8163 static enum return_value_convention
8164 arm_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
8165 struct type
*valtype
, struct regcache
*regcache
,
8166 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
8168 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8169 struct type
*func_type
= function
? value_type (function
) : NULL
;
8170 enum arm_vfp_cprc_base_type vfp_base_type
;
8173 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
8174 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
8176 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
8177 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
8179 for (i
= 0; i
< vfp_base_count
; i
++)
8181 if (reg_char
== 'q')
8184 arm_neon_quad_write (gdbarch
, regcache
, i
,
8185 writebuf
+ i
* unit_length
);
8188 arm_neon_quad_read (gdbarch
, regcache
, i
,
8189 readbuf
+ i
* unit_length
);
8196 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d", reg_char
, i
);
8197 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8200 regcache_cooked_write (regcache
, regnum
,
8201 writebuf
+ i
* unit_length
);
8203 regcache_cooked_read (regcache
, regnum
,
8204 readbuf
+ i
* unit_length
);
8207 return RETURN_VALUE_REGISTER_CONVENTION
;
8210 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
8211 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
8212 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
8214 if (tdep
->struct_return
== pcc_struct_return
8215 || arm_return_in_memory (gdbarch
, valtype
))
8216 return RETURN_VALUE_STRUCT_CONVENTION
;
8218 else if (TYPE_CODE (valtype
) == TYPE_CODE_COMPLEX
)
8220 if (arm_return_in_memory (gdbarch
, valtype
))
8221 return RETURN_VALUE_STRUCT_CONVENTION
;
8225 arm_store_return_value (valtype
, regcache
, writebuf
);
8228 arm_extract_return_value (valtype
, regcache
, readbuf
);
8230 return RETURN_VALUE_REGISTER_CONVENTION
;
8235 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
8237 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
8238 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8239 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8241 gdb_byte buf
[INT_REGISTER_SIZE
];
8243 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
8245 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
8249 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
8253 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
8254 return the target PC. Otherwise return 0. */
8257 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
8261 CORE_ADDR start_addr
;
8263 /* Find the starting address and name of the function containing the PC. */
8264 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
8266 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
8268 start_addr
= arm_skip_bx_reg (frame
, pc
);
8269 if (start_addr
!= 0)
8275 /* If PC is in a Thumb call or return stub, return the address of the
8276 target PC, which is in a register. The thunk functions are called
8277 _call_via_xx, where x is the register name. The possible names
8278 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
8279 functions, named __ARM_call_via_r[0-7]. */
8280 if (startswith (name
, "_call_via_")
8281 || startswith (name
, "__ARM_call_via_"))
8283 /* Use the name suffix to determine which register contains the
8285 static char *table
[15] =
8286 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8287 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
8290 int offset
= strlen (name
) - 2;
8292 for (regno
= 0; regno
<= 14; regno
++)
8293 if (strcmp (&name
[offset
], table
[regno
]) == 0)
8294 return get_frame_register_unsigned (frame
, regno
);
8297 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
8298 non-interworking calls to foo. We could decode the stubs
8299 to find the target but it's easier to use the symbol table. */
8300 namelen
= strlen (name
);
8301 if (name
[0] == '_' && name
[1] == '_'
8302 && ((namelen
> 2 + strlen ("_from_thumb")
8303 && startswith (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb"))
8304 || (namelen
> 2 + strlen ("_from_arm")
8305 && startswith (name
+ namelen
- strlen ("_from_arm"), "_from_arm"))))
8308 int target_len
= namelen
- 2;
8309 struct bound_minimal_symbol minsym
;
8310 struct objfile
*objfile
;
8311 struct obj_section
*sec
;
8313 if (name
[namelen
- 1] == 'b')
8314 target_len
-= strlen ("_from_thumb");
8316 target_len
-= strlen ("_from_arm");
8318 target_name
= (char *) alloca (target_len
+ 1);
8319 memcpy (target_name
, name
+ 2, target_len
);
8320 target_name
[target_len
] = '\0';
8322 sec
= find_pc_section (pc
);
8323 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
8324 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
8325 if (minsym
.minsym
!= NULL
)
8326 return BMSYMBOL_VALUE_ADDRESS (minsym
);
8331 return 0; /* not a stub */
8335 set_arm_command (char *args
, int from_tty
)
8337 printf_unfiltered (_("\
8338 \"set arm\" must be followed by an apporpriate subcommand.\n"));
8339 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
8343 show_arm_command (char *args
, int from_tty
)
8345 cmd_show_list (showarmcmdlist
, from_tty
, "");
8349 arm_update_current_architecture (void)
8351 struct gdbarch_info info
;
8353 /* If the current architecture is not ARM, we have nothing to do. */
8354 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_arm
)
8357 /* Update the architecture. */
8358 gdbarch_info_init (&info
);
8360 if (!gdbarch_update_p (info
))
8361 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
8365 set_fp_model_sfunc (char *args
, int from_tty
,
8366 struct cmd_list_element
*c
)
8370 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
8371 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
8373 arm_fp_model
= (enum arm_float_model
) fp_model
;
8377 if (fp_model
== ARM_FLOAT_LAST
)
8378 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
8381 arm_update_current_architecture ();
8385 show_fp_model (struct ui_file
*file
, int from_tty
,
8386 struct cmd_list_element
*c
, const char *value
)
8388 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8390 if (arm_fp_model
== ARM_FLOAT_AUTO
8391 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8392 fprintf_filtered (file
, _("\
8393 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
8394 fp_model_strings
[tdep
->fp_model
]);
8396 fprintf_filtered (file
, _("\
8397 The current ARM floating point model is \"%s\".\n"),
8398 fp_model_strings
[arm_fp_model
]);
8402 arm_set_abi (char *args
, int from_tty
,
8403 struct cmd_list_element
*c
)
8407 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
8408 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
8410 arm_abi_global
= (enum arm_abi_kind
) arm_abi
;
8414 if (arm_abi
== ARM_ABI_LAST
)
8415 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
8418 arm_update_current_architecture ();
8422 arm_show_abi (struct ui_file
*file
, int from_tty
,
8423 struct cmd_list_element
*c
, const char *value
)
8425 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8427 if (arm_abi_global
== ARM_ABI_AUTO
8428 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8429 fprintf_filtered (file
, _("\
8430 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
8431 arm_abi_strings
[tdep
->arm_abi
]);
8433 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
8438 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
8439 struct cmd_list_element
*c
, const char *value
)
8441 fprintf_filtered (file
,
8442 _("The current execution mode assumed "
8443 "(when symbols are unavailable) is \"%s\".\n"),
8444 arm_fallback_mode_string
);
8448 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
8449 struct cmd_list_element
*c
, const char *value
)
8451 fprintf_filtered (file
,
8452 _("The current execution mode assumed "
8453 "(even when symbols are available) is \"%s\".\n"),
8454 arm_force_mode_string
);
8457 /* If the user changes the register disassembly style used for info
8458 register and other commands, we have to also switch the style used
8459 in opcodes for disassembly output. This function is run in the "set
8460 arm disassembly" command, and does that. */
8463 set_disassembly_style_sfunc (char *args
, int from_tty
,
8464 struct cmd_list_element
*c
)
8466 set_disassembly_style ();
8469 /* Return the ARM register name corresponding to register I. */
8471 arm_register_name (struct gdbarch
*gdbarch
, int i
)
8473 const int num_regs
= gdbarch_num_regs (gdbarch
);
8475 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
8476 && i
>= num_regs
&& i
< num_regs
+ 32)
8478 static const char *const vfp_pseudo_names
[] = {
8479 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
8480 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
8481 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
8482 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
8485 return vfp_pseudo_names
[i
- num_regs
];
8488 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
8489 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
8491 static const char *const neon_pseudo_names
[] = {
8492 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
8493 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
8496 return neon_pseudo_names
[i
- num_regs
- 32];
8499 if (i
>= ARRAY_SIZE (arm_register_names
))
8500 /* These registers are only supported on targets which supply
8501 an XML description. */
8504 return arm_register_names
[i
];
8508 set_disassembly_style (void)
8512 /* Find the style that the user wants. */
8513 for (current
= 0; current
< num_disassembly_options
; current
++)
8514 if (disassembly_style
== valid_disassembly_styles
[current
])
8516 gdb_assert (current
< num_disassembly_options
);
8518 /* Synchronize the disassembler. */
8519 set_arm_regname_option (current
);
8522 /* Test whether the coff symbol specific value corresponds to a Thumb
8526 coff_sym_is_thumb (int val
)
8528 return (val
== C_THUMBEXT
8529 || val
== C_THUMBSTAT
8530 || val
== C_THUMBEXTFUNC
8531 || val
== C_THUMBSTATFUNC
8532 || val
== C_THUMBLABEL
);
8535 /* arm_coff_make_msymbol_special()
8536 arm_elf_make_msymbol_special()
8538 These functions test whether the COFF or ELF symbol corresponds to
8539 an address in thumb code, and set a "special" bit in a minimal
8540 symbol to indicate that it does. */
8543 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
8545 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type
*)sym
)->internal_elf_sym
)
8546 == ST_BRANCH_TO_THUMB
)
8547 MSYMBOL_SET_SPECIAL (msym
);
8551 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
8553 if (coff_sym_is_thumb (val
))
8554 MSYMBOL_SET_SPECIAL (msym
);
8558 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
8560 struct arm_per_objfile
*data
= (struct arm_per_objfile
*) arg
;
8563 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
8564 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
8568 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
8571 const char *name
= bfd_asymbol_name (sym
);
8572 struct arm_per_objfile
*data
;
8573 VEC(arm_mapping_symbol_s
) **map_p
;
8574 struct arm_mapping_symbol new_map_sym
;
8576 gdb_assert (name
[0] == '$');
8577 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
8580 data
= (struct arm_per_objfile
*) objfile_data (objfile
,
8581 arm_objfile_data_key
);
8584 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
8585 struct arm_per_objfile
);
8586 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
8587 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
8588 objfile
->obfd
->section_count
,
8589 VEC(arm_mapping_symbol_s
) *);
8591 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
8593 new_map_sym
.value
= sym
->value
;
8594 new_map_sym
.type
= name
[1];
8596 /* Assume that most mapping symbols appear in order of increasing
8597 value. If they were randomly distributed, it would be faster to
8598 always push here and then sort at first use. */
8599 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
8601 struct arm_mapping_symbol
*prev_map_sym
;
8603 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
8604 if (prev_map_sym
->value
>= sym
->value
)
8607 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
8608 arm_compare_mapping_symbols
);
8609 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
8614 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
8618 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
8620 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
8621 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
8623 /* If necessary, set the T bit. */
8626 ULONGEST val
, t_bit
;
8627 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
8628 t_bit
= arm_psr_thumb_bit (gdbarch
);
8629 if (arm_pc_is_thumb (gdbarch
, pc
))
8630 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8633 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8638 /* Read the contents of a NEON quad register, by reading from two
8639 double registers. This is used to implement the quad pseudo
8640 registers, and for argument passing in case the quad registers are
8641 missing; vectors are passed in quad registers when using the VFP
8642 ABI, even if a NEON unit is not present. REGNUM is the index of
8643 the quad register, in [0, 15]. */
8645 static enum register_status
8646 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8647 int regnum
, gdb_byte
*buf
)
8650 gdb_byte reg_buf
[8];
8651 int offset
, double_regnum
;
8652 enum register_status status
;
8654 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8655 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8658 /* d0 is always the least significant half of q0. */
8659 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8664 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8665 if (status
!= REG_VALID
)
8667 memcpy (buf
+ offset
, reg_buf
, 8);
8669 offset
= 8 - offset
;
8670 status
= regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
8671 if (status
!= REG_VALID
)
8673 memcpy (buf
+ offset
, reg_buf
, 8);
8678 static enum register_status
8679 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8680 int regnum
, gdb_byte
*buf
)
8682 const int num_regs
= gdbarch_num_regs (gdbarch
);
8684 gdb_byte reg_buf
[8];
8685 int offset
, double_regnum
;
8687 gdb_assert (regnum
>= num_regs
);
8690 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8691 /* Quad-precision register. */
8692 return arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
8695 enum register_status status
;
8697 /* Single-precision register. */
8698 gdb_assert (regnum
< 32);
8700 /* s0 is always the least significant half of d0. */
8701 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8702 offset
= (regnum
& 1) ? 0 : 4;
8704 offset
= (regnum
& 1) ? 4 : 0;
8706 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8707 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8710 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8711 if (status
== REG_VALID
)
8712 memcpy (buf
, reg_buf
+ offset
, 4);
8717 /* Store the contents of BUF to a NEON quad register, by writing to
8718 two double registers. This is used to implement the quad pseudo
8719 registers, and for argument passing in case the quad registers are
8720 missing; vectors are passed in quad registers when using the VFP
8721 ABI, even if a NEON unit is not present. REGNUM is the index
8722 of the quad register, in [0, 15]. */
8725 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8726 int regnum
, const gdb_byte
*buf
)
8729 int offset
, double_regnum
;
8731 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8732 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8735 /* d0 is always the least significant half of q0. */
8736 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8741 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
8742 offset
= 8 - offset
;
8743 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
8747 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8748 int regnum
, const gdb_byte
*buf
)
8750 const int num_regs
= gdbarch_num_regs (gdbarch
);
8752 gdb_byte reg_buf
[8];
8753 int offset
, double_regnum
;
8755 gdb_assert (regnum
>= num_regs
);
8758 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8759 /* Quad-precision register. */
8760 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
8763 /* Single-precision register. */
8764 gdb_assert (regnum
< 32);
8766 /* s0 is always the least significant half of d0. */
8767 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8768 offset
= (regnum
& 1) ? 0 : 4;
8770 offset
= (regnum
& 1) ? 4 : 0;
8772 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8773 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8776 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8777 memcpy (reg_buf
+ offset
, buf
, 4);
8778 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
8782 static struct value
*
8783 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
8785 const int *reg_p
= (const int *) baton
;
8786 return value_of_register (*reg_p
, frame
);
8789 static enum gdb_osabi
8790 arm_elf_osabi_sniffer (bfd
*abfd
)
8792 unsigned int elfosabi
;
8793 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
8795 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
8797 if (elfosabi
== ELFOSABI_ARM
)
8798 /* GNU tools use this value. Check note sections in this case,
8800 bfd_map_over_sections (abfd
,
8801 generic_elf_osabi_sniff_abi_tag_sections
,
8804 /* Anything else will be handled by the generic ELF sniffer. */
8809 arm_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
8810 struct reggroup
*group
)
8812 /* FPS register's type is INT, but belongs to float_reggroup. Beside
8813 this, FPS register belongs to save_regroup, restore_reggroup, and
8814 all_reggroup, of course. */
8815 if (regnum
== ARM_FPS_REGNUM
)
8816 return (group
== float_reggroup
8817 || group
== save_reggroup
8818 || group
== restore_reggroup
8819 || group
== all_reggroup
);
8821 return default_register_reggroup_p (gdbarch
, regnum
, group
);
8825 /* For backward-compatibility we allow two 'g' packet lengths with
8826 the remote protocol depending on whether FPA registers are
8827 supplied. M-profile targets do not have FPA registers, but some
8828 stubs already exist in the wild which use a 'g' packet which
8829 supplies them albeit with dummy values. The packet format which
8830 includes FPA registers should be considered deprecated for
8831 M-profile targets. */
8834 arm_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8836 if (gdbarch_tdep (gdbarch
)->is_m
)
8838 /* If we know from the executable this is an M-profile target,
8839 cater for remote targets whose register set layout is the
8840 same as the FPA layout. */
8841 register_remote_g_packet_guess (gdbarch
,
8842 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
8843 (16 * INT_REGISTER_SIZE
)
8844 + (8 * FP_REGISTER_SIZE
)
8845 + (2 * INT_REGISTER_SIZE
),
8846 tdesc_arm_with_m_fpa_layout
);
8848 /* The regular M-profile layout. */
8849 register_remote_g_packet_guess (gdbarch
,
8850 /* r0-r12,sp,lr,pc; xpsr */
8851 (16 * INT_REGISTER_SIZE
)
8852 + INT_REGISTER_SIZE
,
8855 /* M-profile plus M4F VFP. */
8856 register_remote_g_packet_guess (gdbarch
,
8857 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
8858 (16 * INT_REGISTER_SIZE
)
8859 + (16 * VFP_REGISTER_SIZE
)
8860 + (2 * INT_REGISTER_SIZE
),
8861 tdesc_arm_with_m_vfp_d16
);
8864 /* Otherwise we don't have a useful guess. */
8868 /* Initialize the current architecture based on INFO. If possible,
8869 re-use an architecture from ARCHES, which is a list of
8870 architectures already created during this debugging session.
8872 Called e.g. at program startup, when reading a core file, and when
8873 reading a binary file. */
8875 static struct gdbarch
*
8876 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8878 struct gdbarch_tdep
*tdep
;
8879 struct gdbarch
*gdbarch
;
8880 struct gdbarch_list
*best_arch
;
8881 enum arm_abi_kind arm_abi
= arm_abi_global
;
8882 enum arm_float_model fp_model
= arm_fp_model
;
8883 struct tdesc_arch_data
*tdesc_data
= NULL
;
8885 int vfp_register_count
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
8886 int have_wmmx_registers
= 0;
8888 int have_fpa_registers
= 1;
8889 const struct target_desc
*tdesc
= info
.target_desc
;
8891 /* If we have an object to base this architecture on, try to determine
8894 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
8896 int ei_osabi
, e_flags
;
8898 switch (bfd_get_flavour (info
.abfd
))
8900 case bfd_target_aout_flavour
:
8901 /* Assume it's an old APCS-style ABI. */
8902 arm_abi
= ARM_ABI_APCS
;
8905 case bfd_target_coff_flavour
:
8906 /* Assume it's an old APCS-style ABI. */
8908 arm_abi
= ARM_ABI_APCS
;
8911 case bfd_target_elf_flavour
:
8912 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
8913 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8915 if (ei_osabi
== ELFOSABI_ARM
)
8917 /* GNU tools used to use this value, but do not for EABI
8918 objects. There's nowhere to tag an EABI version
8919 anyway, so assume APCS. */
8920 arm_abi
= ARM_ABI_APCS
;
8922 else if (ei_osabi
== ELFOSABI_NONE
|| ei_osabi
== ELFOSABI_GNU
)
8924 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
8925 int attr_arch
, attr_profile
;
8929 case EF_ARM_EABI_UNKNOWN
:
8930 /* Assume GNU tools. */
8931 arm_abi
= ARM_ABI_APCS
;
8934 case EF_ARM_EABI_VER4
:
8935 case EF_ARM_EABI_VER5
:
8936 arm_abi
= ARM_ABI_AAPCS
;
8937 /* EABI binaries default to VFP float ordering.
8938 They may also contain build attributes that can
8939 be used to identify if the VFP argument-passing
8941 if (fp_model
== ARM_FLOAT_AUTO
)
8944 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
8948 case AEABI_VFP_args_base
:
8949 /* "The user intended FP parameter/result
8950 passing to conform to AAPCS, base
8952 fp_model
= ARM_FLOAT_SOFT_VFP
;
8954 case AEABI_VFP_args_vfp
:
8955 /* "The user intended FP parameter/result
8956 passing to conform to AAPCS, VFP
8958 fp_model
= ARM_FLOAT_VFP
;
8960 case AEABI_VFP_args_toolchain
:
8961 /* "The user intended FP parameter/result
8962 passing to conform to tool chain-specific
8963 conventions" - we don't know any such
8964 conventions, so leave it as "auto". */
8966 case AEABI_VFP_args_compatible
:
8967 /* "Code is compatible with both the base
8968 and VFP variants; the user did not permit
8969 non-variadic functions to pass FP
8970 parameters/results" - leave it as
8974 /* Attribute value not mentioned in the
8975 November 2012 ABI, so leave it as
8980 fp_model
= ARM_FLOAT_SOFT_VFP
;
8986 /* Leave it as "auto". */
8987 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
8992 /* Detect M-profile programs. This only works if the
8993 executable file includes build attributes; GCC does
8994 copy them to the executable, but e.g. RealView does
8996 attr_arch
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
8998 attr_profile
= bfd_elf_get_obj_attr_int (info
.abfd
,
9000 Tag_CPU_arch_profile
);
9001 /* GCC specifies the profile for v6-M; RealView only
9002 specifies the profile for architectures starting with
9003 V7 (as opposed to architectures with a tag
9004 numerically greater than TAG_CPU_ARCH_V7). */
9005 if (!tdesc_has_registers (tdesc
)
9006 && (attr_arch
== TAG_CPU_ARCH_V6_M
9007 || attr_arch
== TAG_CPU_ARCH_V6S_M
9008 || attr_profile
== 'M'))
9013 if (fp_model
== ARM_FLOAT_AUTO
)
9015 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9017 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
9020 /* Leave it as "auto". Strictly speaking this case
9021 means FPA, but almost nobody uses that now, and
9022 many toolchains fail to set the appropriate bits
9023 for the floating-point model they use. */
9025 case EF_ARM_SOFT_FLOAT
:
9026 fp_model
= ARM_FLOAT_SOFT_FPA
;
9028 case EF_ARM_VFP_FLOAT
:
9029 fp_model
= ARM_FLOAT_VFP
;
9031 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
9032 fp_model
= ARM_FLOAT_SOFT_VFP
;
9037 if (e_flags
& EF_ARM_BE8
)
9038 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
9043 /* Leave it as "auto". */
9048 /* Check any target description for validity. */
9049 if (tdesc_has_registers (tdesc
))
9051 /* For most registers we require GDB's default names; but also allow
9052 the numeric names for sp / lr / pc, as a convenience. */
9053 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
9054 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
9055 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
9057 const struct tdesc_feature
*feature
;
9060 feature
= tdesc_find_feature (tdesc
,
9061 "org.gnu.gdb.arm.core");
9062 if (feature
== NULL
)
9064 feature
= tdesc_find_feature (tdesc
,
9065 "org.gnu.gdb.arm.m-profile");
9066 if (feature
== NULL
)
9072 tdesc_data
= tdesc_data_alloc ();
9075 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
9076 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9077 arm_register_names
[i
]);
9078 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9081 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9084 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9088 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9089 ARM_PS_REGNUM
, "xpsr");
9091 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9092 ARM_PS_REGNUM
, "cpsr");
9096 tdesc_data_cleanup (tdesc_data
);
9100 feature
= tdesc_find_feature (tdesc
,
9101 "org.gnu.gdb.arm.fpa");
9102 if (feature
!= NULL
)
9105 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
9106 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9107 arm_register_names
[i
]);
9110 tdesc_data_cleanup (tdesc_data
);
9115 have_fpa_registers
= 0;
9117 feature
= tdesc_find_feature (tdesc
,
9118 "org.gnu.gdb.xscale.iwmmxt");
9119 if (feature
!= NULL
)
9121 static const char *const iwmmxt_names
[] = {
9122 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
9123 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
9124 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
9125 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
9129 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
9131 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9132 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9134 /* Check for the control registers, but do not fail if they
9136 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
9137 tdesc_numbered_register (feature
, tdesc_data
, i
,
9138 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9140 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
9142 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9143 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9147 tdesc_data_cleanup (tdesc_data
);
9151 have_wmmx_registers
= 1;
9154 /* If we have a VFP unit, check whether the single precision registers
9155 are present. If not, then we will synthesize them as pseudo
9157 feature
= tdesc_find_feature (tdesc
,
9158 "org.gnu.gdb.arm.vfp");
9159 if (feature
!= NULL
)
9161 static const char *const vfp_double_names
[] = {
9162 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
9163 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
9164 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
9165 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
9168 /* Require the double precision registers. There must be either
9171 for (i
= 0; i
< 32; i
++)
9173 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9175 vfp_double_names
[i
]);
9179 if (!valid_p
&& i
== 16)
9182 /* Also require FPSCR. */
9183 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9184 ARM_FPSCR_REGNUM
, "fpscr");
9187 tdesc_data_cleanup (tdesc_data
);
9191 if (tdesc_unnumbered_register (feature
, "s0") == 0)
9192 have_vfp_pseudos
= 1;
9194 vfp_register_count
= i
;
9196 /* If we have VFP, also check for NEON. The architecture allows
9197 NEON without VFP (integer vector operations only), but GDB
9198 does not support that. */
9199 feature
= tdesc_find_feature (tdesc
,
9200 "org.gnu.gdb.arm.neon");
9201 if (feature
!= NULL
)
9203 /* NEON requires 32 double-precision registers. */
9206 tdesc_data_cleanup (tdesc_data
);
9210 /* If there are quad registers defined by the stub, use
9211 their type; otherwise (normally) provide them with
9212 the default type. */
9213 if (tdesc_unnumbered_register (feature
, "q0") == 0)
9214 have_neon_pseudos
= 1;
9221 /* If there is already a candidate, use it. */
9222 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
9224 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
9226 if (arm_abi
!= ARM_ABI_AUTO
9227 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
9230 if (fp_model
!= ARM_FLOAT_AUTO
9231 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
9234 /* There are various other properties in tdep that we do not
9235 need to check here: those derived from a target description,
9236 since gdbarches with a different target description are
9237 automatically disqualified. */
9239 /* Do check is_m, though, since it might come from the binary. */
9240 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
9243 /* Found a match. */
9247 if (best_arch
!= NULL
)
9249 if (tdesc_data
!= NULL
)
9250 tdesc_data_cleanup (tdesc_data
);
9251 return best_arch
->gdbarch
;
9254 tdep
= XCNEW (struct gdbarch_tdep
);
9255 gdbarch
= gdbarch_alloc (&info
, tdep
);
9257 /* Record additional information about the architecture we are defining.
9258 These are gdbarch discriminators, like the OSABI. */
9259 tdep
->arm_abi
= arm_abi
;
9260 tdep
->fp_model
= fp_model
;
9262 tdep
->have_fpa_registers
= have_fpa_registers
;
9263 tdep
->have_wmmx_registers
= have_wmmx_registers
;
9264 gdb_assert (vfp_register_count
== 0
9265 || vfp_register_count
== 16
9266 || vfp_register_count
== 32);
9267 tdep
->vfp_register_count
= vfp_register_count
;
9268 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
9269 tdep
->have_neon_pseudos
= have_neon_pseudos
;
9270 tdep
->have_neon
= have_neon
;
9272 arm_register_g_packet_guesses (gdbarch
);
9275 switch (info
.byte_order_for_code
)
9277 case BFD_ENDIAN_BIG
:
9278 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
9279 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
9280 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
9281 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
9285 case BFD_ENDIAN_LITTLE
:
9286 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
9287 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
9288 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
9289 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
9294 internal_error (__FILE__
, __LINE__
,
9295 _("arm_gdbarch_init: bad byte order for float format"));
9298 /* On ARM targets char defaults to unsigned. */
9299 set_gdbarch_char_signed (gdbarch
, 0);
9301 /* Note: for displaced stepping, this includes the breakpoint, and one word
9302 of additional scratch space. This setting isn't used for anything beside
9303 displaced stepping at present. */
9304 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
9306 /* This should be low enough for everything. */
9307 tdep
->lowest_pc
= 0x20;
9308 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
9310 /* The default, for both APCS and AAPCS, is to return small
9311 structures in registers. */
9312 tdep
->struct_return
= reg_struct_return
;
9314 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
9315 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
9317 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
9319 /* Frame handling. */
9320 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
9321 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
9322 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
9324 frame_base_set_default (gdbarch
, &arm_normal_base
);
9326 /* Address manipulation. */
9327 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
9329 /* Advance PC across function entry code. */
9330 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
9332 /* Detect whether PC is at a point where the stack has been destroyed. */
9333 set_gdbarch_stack_frame_destroyed_p (gdbarch
, arm_stack_frame_destroyed_p
);
9335 /* Skip trampolines. */
9336 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
9338 /* The stack grows downward. */
9339 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
9341 /* Breakpoint manipulation. */
9342 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
9343 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
9344 arm_remote_breakpoint_from_pc
);
9346 /* Information about registers, etc. */
9347 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
9348 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
9349 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
9350 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9351 set_gdbarch_register_reggroup_p (gdbarch
, arm_register_reggroup_p
);
9353 /* This "info float" is FPA-specific. Use the generic version if we
9355 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
9356 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
9358 /* Internal <-> external register number maps. */
9359 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
9360 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
9362 set_gdbarch_register_name (gdbarch
, arm_register_name
);
9364 /* Returning results. */
9365 set_gdbarch_return_value (gdbarch
, arm_return_value
);
9368 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
9370 /* Minsymbol frobbing. */
9371 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
9372 set_gdbarch_coff_make_msymbol_special (gdbarch
,
9373 arm_coff_make_msymbol_special
);
9374 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
9376 /* Thumb-2 IT block support. */
9377 set_gdbarch_adjust_breakpoint_address (gdbarch
,
9378 arm_adjust_breakpoint_address
);
9380 /* Virtual tables. */
9381 set_gdbarch_vbit_in_delta (gdbarch
, 1);
9383 /* Hook in the ABI-specific overrides, if they have been registered. */
9384 gdbarch_init_osabi (info
, gdbarch
);
9386 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
9388 /* Add some default predicates. */
9390 frame_unwind_append_unwinder (gdbarch
, &arm_m_exception_unwind
);
9391 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
9392 dwarf2_append_unwinders (gdbarch
);
9393 frame_unwind_append_unwinder (gdbarch
, &arm_exidx_unwind
);
9394 frame_unwind_append_unwinder (gdbarch
, &arm_epilogue_frame_unwind
);
9395 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
9397 /* Now we have tuned the configuration, set a few final things,
9398 based on what the OS ABI has told us. */
9400 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
9401 binaries are always marked. */
9402 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
9403 tdep
->arm_abi
= ARM_ABI_APCS
;
9405 /* Watchpoints are not steppable. */
9406 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
9408 /* We used to default to FPA for generic ARM, but almost nobody
9409 uses that now, and we now provide a way for the user to force
9410 the model. So default to the most useful variant. */
9411 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
9412 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
9414 if (tdep
->jb_pc
>= 0)
9415 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
9417 /* Floating point sizes and format. */
9418 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
9419 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
9421 set_gdbarch_double_format
9422 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9423 set_gdbarch_long_double_format
9424 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9428 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
9429 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
9432 if (have_vfp_pseudos
)
9434 /* NOTE: These are the only pseudo registers used by
9435 the ARM target at the moment. If more are added, a
9436 little more care in numbering will be needed. */
9438 int num_pseudos
= 32;
9439 if (have_neon_pseudos
)
9441 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
9442 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
9443 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
9448 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
9450 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
9452 /* Override tdesc_register_type to adjust the types of VFP
9453 registers for NEON. */
9454 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9457 /* Add standard register aliases. We add aliases even for those
9458 nanes which are used by the current architecture - it's simpler,
9459 and does no harm, since nothing ever lists user registers. */
9460 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
9461 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
9462 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
9468 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
9470 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9475 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
9476 (unsigned long) tdep
->lowest_pc
);
9479 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
9482 _initialize_arm_tdep (void)
9484 struct ui_file
*stb
;
9486 const char *setname
;
9487 const char *setdesc
;
9488 const char *const *regnames
;
9490 static char *helptext
;
9491 char regdesc
[1024], *rdptr
= regdesc
;
9492 size_t rest
= sizeof (regdesc
);
9494 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
9496 arm_objfile_data_key
9497 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
9499 /* Add ourselves to objfile event chain. */
9500 observer_attach_new_objfile (arm_exidx_new_objfile
);
9502 = register_objfile_data_with_cleanup (NULL
, arm_exidx_data_free
);
9504 /* Register an ELF OS ABI sniffer for ARM binaries. */
9505 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
9506 bfd_target_elf_flavour
,
9507 arm_elf_osabi_sniffer
);
9509 /* Initialize the standard target descriptions. */
9510 initialize_tdesc_arm_with_m ();
9511 initialize_tdesc_arm_with_m_fpa_layout ();
9512 initialize_tdesc_arm_with_m_vfp_d16 ();
9513 initialize_tdesc_arm_with_iwmmxt ();
9514 initialize_tdesc_arm_with_vfpv2 ();
9515 initialize_tdesc_arm_with_vfpv3 ();
9516 initialize_tdesc_arm_with_neon ();
9518 /* Get the number of possible sets of register names defined in opcodes. */
9519 num_disassembly_options
= get_arm_regname_num_options ();
9521 /* Add root prefix command for all "set arm"/"show arm" commands. */
9522 add_prefix_cmd ("arm", no_class
, set_arm_command
,
9523 _("Various ARM-specific commands."),
9524 &setarmcmdlist
, "set arm ", 0, &setlist
);
9526 add_prefix_cmd ("arm", no_class
, show_arm_command
,
9527 _("Various ARM-specific commands."),
9528 &showarmcmdlist
, "show arm ", 0, &showlist
);
9530 /* Sync the opcode insn printer with our register viewer. */
9531 parse_arm_disassembler_option ("reg-names-std");
9533 /* Initialize the array that will be passed to
9534 add_setshow_enum_cmd(). */
9535 valid_disassembly_styles
= XNEWVEC (const char *,
9536 num_disassembly_options
+ 1);
9537 for (i
= 0; i
< num_disassembly_options
; i
++)
9539 get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
9540 valid_disassembly_styles
[i
] = setname
;
9541 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
9544 /* When we find the default names, tell the disassembler to use
9546 if (!strcmp (setname
, "std"))
9548 disassembly_style
= setname
;
9549 set_arm_regname_option (i
);
9552 /* Mark the end of valid options. */
9553 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
9555 /* Create the help text. */
9556 stb
= mem_fileopen ();
9557 fprintf_unfiltered (stb
, "%s%s%s",
9558 _("The valid values are:\n"),
9560 _("The default is \"std\"."));
9561 helptext
= ui_file_xstrdup (stb
, NULL
);
9562 ui_file_delete (stb
);
9564 add_setshow_enum_cmd("disassembler", no_class
,
9565 valid_disassembly_styles
, &disassembly_style
,
9566 _("Set the disassembly style."),
9567 _("Show the disassembly style."),
9569 set_disassembly_style_sfunc
,
9570 NULL
, /* FIXME: i18n: The disassembly style is
9572 &setarmcmdlist
, &showarmcmdlist
);
9574 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
9575 _("Set usage of ARM 32-bit mode."),
9576 _("Show usage of ARM 32-bit mode."),
9577 _("When off, a 26-bit PC will be used."),
9579 NULL
, /* FIXME: i18n: Usage of ARM 32-bit
9581 &setarmcmdlist
, &showarmcmdlist
);
9583 /* Add a command to allow the user to force the FPU model. */
9584 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
9585 _("Set the floating point type."),
9586 _("Show the floating point type."),
9587 _("auto - Determine the FP typefrom the OS-ABI.\n\
9588 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
9589 fpa - FPA co-processor (GCC compiled).\n\
9590 softvfp - Software FP with pure-endian doubles.\n\
9591 vfp - VFP co-processor."),
9592 set_fp_model_sfunc
, show_fp_model
,
9593 &setarmcmdlist
, &showarmcmdlist
);
9595 /* Add a command to allow the user to force the ABI. */
9596 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
9599 NULL
, arm_set_abi
, arm_show_abi
,
9600 &setarmcmdlist
, &showarmcmdlist
);
9602 /* Add two commands to allow the user to force the assumed
9604 add_setshow_enum_cmd ("fallback-mode", class_support
,
9605 arm_mode_strings
, &arm_fallback_mode_string
,
9606 _("Set the mode assumed when symbols are unavailable."),
9607 _("Show the mode assumed when symbols are unavailable."),
9608 NULL
, NULL
, arm_show_fallback_mode
,
9609 &setarmcmdlist
, &showarmcmdlist
);
9610 add_setshow_enum_cmd ("force-mode", class_support
,
9611 arm_mode_strings
, &arm_force_mode_string
,
9612 _("Set the mode assumed even when symbols are available."),
9613 _("Show the mode assumed even when symbols are available."),
9614 NULL
, NULL
, arm_show_force_mode
,
9615 &setarmcmdlist
, &showarmcmdlist
);
9617 /* Debugging flag. */
9618 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
9619 _("Set ARM debugging."),
9620 _("Show ARM debugging."),
9621 _("When on, arm-specific debugging is enabled."),
9623 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
9624 &setdebuglist
, &showdebuglist
);
9627 /* ARM-reversible process record data structures. */
9629 #define ARM_INSN_SIZE_BYTES 4
9630 #define THUMB_INSN_SIZE_BYTES 2
9631 #define THUMB2_INSN_SIZE_BYTES 4
9634 /* Position of the bit within a 32-bit ARM instruction
9635 that defines whether the instruction is a load or store. */
9636 #define INSN_S_L_BIT_NUM 20
9638 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
9641 unsigned int reg_len = LENGTH; \
9644 REGS = XNEWVEC (uint32_t, reg_len); \
9645 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
9650 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
9653 unsigned int mem_len = LENGTH; \
9656 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
9657 memcpy(&MEMS->len, &RECORD_BUF[0], \
9658 sizeof(struct arm_mem_r) * LENGTH); \
9663 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
9664 #define INSN_RECORDED(ARM_RECORD) \
9665 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
9667 /* ARM memory record structure. */
9670 uint32_t len
; /* Record length. */
9671 uint32_t addr
; /* Memory address. */
9674 /* ARM instruction record contains opcode of current insn
9675 and execution state (before entry to decode_insn()),
9676 contains list of to-be-modified registers and
9677 memory blocks (on return from decode_insn()). */
9679 typedef struct insn_decode_record_t
9681 struct gdbarch
*gdbarch
;
9682 struct regcache
*regcache
;
9683 CORE_ADDR this_addr
; /* Address of the insn being decoded. */
9684 uint32_t arm_insn
; /* Should accommodate thumb. */
9685 uint32_t cond
; /* Condition code. */
9686 uint32_t opcode
; /* Insn opcode. */
9687 uint32_t decode
; /* Insn decode bits. */
9688 uint32_t mem_rec_count
; /* No of mem records. */
9689 uint32_t reg_rec_count
; /* No of reg records. */
9690 uint32_t *arm_regs
; /* Registers to be saved for this record. */
9691 struct arm_mem_r
*arm_mems
; /* Memory to be saved for this record. */
9692 } insn_decode_record
;
9695 /* Checks ARM SBZ and SBO mandatory fields. */
9698 sbo_sbz (uint32_t insn
, uint32_t bit_num
, uint32_t len
, uint32_t sbo
)
9700 uint32_t ones
= bits (insn
, bit_num
- 1, (bit_num
-1) + (len
- 1));
9719 enum arm_record_result
9721 ARM_RECORD_SUCCESS
= 0,
9722 ARM_RECORD_FAILURE
= 1
9729 } arm_record_strx_t
;
9740 arm_record_strx (insn_decode_record
*arm_insn_r
, uint32_t *record_buf
,
9741 uint32_t *record_buf_mem
, arm_record_strx_t str_type
)
9744 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
9745 ULONGEST u_regval
[2]= {0};
9747 uint32_t reg_src1
= 0, reg_src2
= 0;
9748 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
9750 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
9751 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
9753 if (14 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
9755 /* 1) Handle misc store, immediate offset. */
9756 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9757 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9758 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9759 regcache_raw_read_unsigned (reg_cache
, reg_src1
,
9761 if (ARM_PC_REGNUM
== reg_src1
)
9763 /* If R15 was used as Rn, hence current PC+8. */
9764 u_regval
[0] = u_regval
[0] + 8;
9766 offset_8
= (immed_high
<< 4) | immed_low
;
9767 /* Calculate target store address. */
9768 if (14 == arm_insn_r
->opcode
)
9770 tgt_mem_addr
= u_regval
[0] + offset_8
;
9774 tgt_mem_addr
= u_regval
[0] - offset_8
;
9776 if (ARM_RECORD_STRH
== str_type
)
9778 record_buf_mem
[0] = 2;
9779 record_buf_mem
[1] = tgt_mem_addr
;
9780 arm_insn_r
->mem_rec_count
= 1;
9782 else if (ARM_RECORD_STRD
== str_type
)
9784 record_buf_mem
[0] = 4;
9785 record_buf_mem
[1] = tgt_mem_addr
;
9786 record_buf_mem
[2] = 4;
9787 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9788 arm_insn_r
->mem_rec_count
= 2;
9791 else if (12 == arm_insn_r
->opcode
|| 8 == arm_insn_r
->opcode
)
9793 /* 2) Store, register offset. */
9795 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9797 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9798 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9799 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9802 /* If R15 was used as Rn, hence current PC+8. */
9803 u_regval
[0] = u_regval
[0] + 8;
9805 /* Calculate target store address, Rn +/- Rm, register offset. */
9806 if (12 == arm_insn_r
->opcode
)
9808 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9812 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9814 if (ARM_RECORD_STRH
== str_type
)
9816 record_buf_mem
[0] = 2;
9817 record_buf_mem
[1] = tgt_mem_addr
;
9818 arm_insn_r
->mem_rec_count
= 1;
9820 else if (ARM_RECORD_STRD
== str_type
)
9822 record_buf_mem
[0] = 4;
9823 record_buf_mem
[1] = tgt_mem_addr
;
9824 record_buf_mem
[2] = 4;
9825 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9826 arm_insn_r
->mem_rec_count
= 2;
9829 else if (11 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
9830 || 2 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9832 /* 3) Store, immediate pre-indexed. */
9833 /* 5) Store, immediate post-indexed. */
9834 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9835 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9836 offset_8
= (immed_high
<< 4) | immed_low
;
9837 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9838 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9839 /* Calculate target store address, Rn +/- Rm, register offset. */
9840 if (15 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9842 tgt_mem_addr
= u_regval
[0] + offset_8
;
9846 tgt_mem_addr
= u_regval
[0] - offset_8
;
9848 if (ARM_RECORD_STRH
== str_type
)
9850 record_buf_mem
[0] = 2;
9851 record_buf_mem
[1] = tgt_mem_addr
;
9852 arm_insn_r
->mem_rec_count
= 1;
9854 else if (ARM_RECORD_STRD
== str_type
)
9856 record_buf_mem
[0] = 4;
9857 record_buf_mem
[1] = tgt_mem_addr
;
9858 record_buf_mem
[2] = 4;
9859 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9860 arm_insn_r
->mem_rec_count
= 2;
9862 /* Record Rn also as it changes. */
9863 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
9864 arm_insn_r
->reg_rec_count
= 1;
9866 else if (9 == arm_insn_r
->opcode
|| 13 == arm_insn_r
->opcode
9867 || 0 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9869 /* 4) Store, register pre-indexed. */
9870 /* 6) Store, register post -indexed. */
9871 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9872 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9873 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9874 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9875 /* Calculate target store address, Rn +/- Rm, register offset. */
9876 if (13 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9878 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9882 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9884 if (ARM_RECORD_STRH
== str_type
)
9886 record_buf_mem
[0] = 2;
9887 record_buf_mem
[1] = tgt_mem_addr
;
9888 arm_insn_r
->mem_rec_count
= 1;
9890 else if (ARM_RECORD_STRD
== str_type
)
9892 record_buf_mem
[0] = 4;
9893 record_buf_mem
[1] = tgt_mem_addr
;
9894 record_buf_mem
[2] = 4;
9895 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9896 arm_insn_r
->mem_rec_count
= 2;
9898 /* Record Rn also as it changes. */
9899 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
9900 arm_insn_r
->reg_rec_count
= 1;
9905 /* Handling ARM extension space insns. */
9908 arm_record_extension_space (insn_decode_record
*arm_insn_r
)
9910 uint32_t ret
= 0; /* Return value: -1:record failure ; 0:success */
9911 uint32_t opcode1
= 0, opcode2
= 0, insn_op1
= 0;
9912 uint32_t record_buf
[8], record_buf_mem
[8];
9913 uint32_t reg_src1
= 0;
9914 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
9915 ULONGEST u_regval
= 0;
9917 gdb_assert (!INSN_RECORDED(arm_insn_r
));
9918 /* Handle unconditional insn extension space. */
9920 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 27);
9921 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
9922 if (arm_insn_r
->cond
)
9924 /* PLD has no affect on architectural state, it just affects
9926 if (5 == ((opcode1
& 0xE0) >> 5))
9929 record_buf
[0] = ARM_PS_REGNUM
;
9930 record_buf
[1] = ARM_LR_REGNUM
;
9931 arm_insn_r
->reg_rec_count
= 2;
9933 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
9937 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
9938 if (3 == opcode1
&& bit (arm_insn_r
->arm_insn
, 4))
9941 /* Undefined instruction on ARM V5; need to handle if later
9942 versions define it. */
9945 opcode1
= bits (arm_insn_r
->arm_insn
, 24, 27);
9946 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
9947 insn_op1
= bits (arm_insn_r
->arm_insn
, 20, 23);
9949 /* Handle arithmetic insn extension space. */
9950 if (!opcode1
&& 9 == opcode2
&& 1 != arm_insn_r
->cond
9951 && !INSN_RECORDED(arm_insn_r
))
9953 /* Handle MLA(S) and MUL(S). */
9954 if (0 <= insn_op1
&& 3 >= insn_op1
)
9956 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
9957 record_buf
[1] = ARM_PS_REGNUM
;
9958 arm_insn_r
->reg_rec_count
= 2;
9960 else if (4 <= insn_op1
&& 15 >= insn_op1
)
9962 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
9963 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
9964 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
9965 record_buf
[2] = ARM_PS_REGNUM
;
9966 arm_insn_r
->reg_rec_count
= 3;
9970 opcode1
= bits (arm_insn_r
->arm_insn
, 26, 27);
9971 opcode2
= bits (arm_insn_r
->arm_insn
, 23, 24);
9972 insn_op1
= bits (arm_insn_r
->arm_insn
, 21, 22);
9974 /* Handle control insn extension space. */
9976 if (!opcode1
&& 2 == opcode2
&& !bit (arm_insn_r
->arm_insn
, 20)
9977 && 1 != arm_insn_r
->cond
&& !INSN_RECORDED(arm_insn_r
))
9979 if (!bit (arm_insn_r
->arm_insn
,25))
9981 if (!bits (arm_insn_r
->arm_insn
, 4, 7))
9983 if ((0 == insn_op1
) || (2 == insn_op1
))
9986 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
9987 arm_insn_r
->reg_rec_count
= 1;
9989 else if (1 == insn_op1
)
9991 /* CSPR is going to be changed. */
9992 record_buf
[0] = ARM_PS_REGNUM
;
9993 arm_insn_r
->reg_rec_count
= 1;
9995 else if (3 == insn_op1
)
9997 /* SPSR is going to be changed. */
9998 /* We need to get SPSR value, which is yet to be done. */
10002 else if (1 == bits (arm_insn_r
->arm_insn
, 4, 7))
10007 record_buf
[0] = ARM_PS_REGNUM
;
10008 arm_insn_r
->reg_rec_count
= 1;
10010 else if (3 == insn_op1
)
10013 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10014 arm_insn_r
->reg_rec_count
= 1;
10017 else if (3 == bits (arm_insn_r
->arm_insn
, 4, 7))
10020 record_buf
[0] = ARM_PS_REGNUM
;
10021 record_buf
[1] = ARM_LR_REGNUM
;
10022 arm_insn_r
->reg_rec_count
= 2;
10024 else if (5 == bits (arm_insn_r
->arm_insn
, 4, 7))
10026 /* QADD, QSUB, QDADD, QDSUB */
10027 record_buf
[0] = ARM_PS_REGNUM
;
10028 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10029 arm_insn_r
->reg_rec_count
= 2;
10031 else if (7 == bits (arm_insn_r
->arm_insn
, 4, 7))
10034 record_buf
[0] = ARM_PS_REGNUM
;
10035 record_buf
[1] = ARM_LR_REGNUM
;
10036 arm_insn_r
->reg_rec_count
= 2;
10038 /* Save SPSR also;how? */
10041 else if(8 == bits (arm_insn_r
->arm_insn
, 4, 7)
10042 || 10 == bits (arm_insn_r
->arm_insn
, 4, 7)
10043 || 12 == bits (arm_insn_r
->arm_insn
, 4, 7)
10044 || 14 == bits (arm_insn_r
->arm_insn
, 4, 7)
10047 if (0 == insn_op1
|| 1 == insn_op1
)
10049 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
10050 /* We dont do optimization for SMULW<y> where we
10052 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10053 record_buf
[1] = ARM_PS_REGNUM
;
10054 arm_insn_r
->reg_rec_count
= 2;
10056 else if (2 == insn_op1
)
10059 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10060 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
10061 arm_insn_r
->reg_rec_count
= 2;
10063 else if (3 == insn_op1
)
10066 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10067 arm_insn_r
->reg_rec_count
= 1;
10073 /* MSR : immediate form. */
10076 /* CSPR is going to be changed. */
10077 record_buf
[0] = ARM_PS_REGNUM
;
10078 arm_insn_r
->reg_rec_count
= 1;
10080 else if (3 == insn_op1
)
10082 /* SPSR is going to be changed. */
10083 /* we need to get SPSR value, which is yet to be done */
10089 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10090 opcode2
= bits (arm_insn_r
->arm_insn
, 20, 24);
10091 insn_op1
= bits (arm_insn_r
->arm_insn
, 5, 6);
10093 /* Handle load/store insn extension space. */
10095 if (!opcode1
&& bit (arm_insn_r
->arm_insn
, 7)
10096 && bit (arm_insn_r
->arm_insn
, 4) && 1 != arm_insn_r
->cond
10097 && !INSN_RECORDED(arm_insn_r
))
10102 /* These insn, changes register and memory as well. */
10103 /* SWP or SWPB insn. */
10104 /* Get memory address given by Rn. */
10105 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10106 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
10107 /* SWP insn ?, swaps word. */
10108 if (8 == arm_insn_r
->opcode
)
10110 record_buf_mem
[0] = 4;
10114 /* SWPB insn, swaps only byte. */
10115 record_buf_mem
[0] = 1;
10117 record_buf_mem
[1] = u_regval
;
10118 arm_insn_r
->mem_rec_count
= 1;
10119 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10120 arm_insn_r
->reg_rec_count
= 1;
10122 else if (1 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10125 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10128 else if (2 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10131 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10132 record_buf
[1] = record_buf
[0] + 1;
10133 arm_insn_r
->reg_rec_count
= 2;
10135 else if (3 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10138 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10141 else if (bit (arm_insn_r
->arm_insn
, 20) && insn_op1
<= 3)
10143 /* LDRH, LDRSB, LDRSH. */
10144 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10145 arm_insn_r
->reg_rec_count
= 1;
10150 opcode1
= bits (arm_insn_r
->arm_insn
, 23, 27);
10151 if (24 == opcode1
&& bit (arm_insn_r
->arm_insn
, 21)
10152 && !INSN_RECORDED(arm_insn_r
))
10155 /* Handle coprocessor insn extension space. */
10158 /* To be done for ARMv5 and later; as of now we return -1. */
10162 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10163 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10168 /* Handling opcode 000 insns. */
10171 arm_record_data_proc_misc_ld_str (insn_decode_record
*arm_insn_r
)
10173 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10174 uint32_t record_buf
[8], record_buf_mem
[8];
10175 ULONGEST u_regval
[2] = {0};
10177 uint32_t reg_src1
= 0, reg_dest
= 0;
10178 uint32_t opcode1
= 0;
10180 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10181 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10182 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
10184 /* Data processing insn /multiply insn. */
10185 if (9 == arm_insn_r
->decode
10186 && ((4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
10187 || (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)))
10189 /* Handle multiply instructions. */
10190 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
10191 if (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)
10193 /* Handle MLA and MUL. */
10194 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10195 record_buf
[1] = ARM_PS_REGNUM
;
10196 arm_insn_r
->reg_rec_count
= 2;
10198 else if (4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
10200 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
10201 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10202 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10203 record_buf
[2] = ARM_PS_REGNUM
;
10204 arm_insn_r
->reg_rec_count
= 3;
10207 else if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
10208 && (11 == arm_insn_r
->decode
|| 13 == arm_insn_r
->decode
))
10210 /* Handle misc load insns, as 20th bit (L = 1). */
10211 /* LDR insn has a capability to do branching, if
10212 MOV LR, PC is precceded by LDR insn having Rn as R15
10213 in that case, it emulates branch and link insn, and hence we
10214 need to save CSPR and PC as well. I am not sure this is right
10215 place; as opcode = 010 LDR insn make this happen, if R15 was
10217 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10218 if (15 != reg_dest
)
10220 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10221 arm_insn_r
->reg_rec_count
= 1;
10225 record_buf
[0] = reg_dest
;
10226 record_buf
[1] = ARM_PS_REGNUM
;
10227 arm_insn_r
->reg_rec_count
= 2;
10230 else if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
10231 && sbo_sbz (arm_insn_r
->arm_insn
, 5, 12, 0)
10232 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
10233 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21))
10235 /* Handle MSR insn. */
10236 if (9 == arm_insn_r
->opcode
)
10238 /* CSPR is going to be changed. */
10239 record_buf
[0] = ARM_PS_REGNUM
;
10240 arm_insn_r
->reg_rec_count
= 1;
10244 /* SPSR is going to be changed. */
10245 /* How to read SPSR value? */
10249 else if (9 == arm_insn_r
->decode
10250 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10251 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10253 /* Handling SWP, SWPB. */
10254 /* These insn, changes register and memory as well. */
10255 /* SWP or SWPB insn. */
10257 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10258 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10259 /* SWP insn ?, swaps word. */
10260 if (8 == arm_insn_r
->opcode
)
10262 record_buf_mem
[0] = 4;
10266 /* SWPB insn, swaps only byte. */
10267 record_buf_mem
[0] = 1;
10269 record_buf_mem
[1] = u_regval
[0];
10270 arm_insn_r
->mem_rec_count
= 1;
10271 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10272 arm_insn_r
->reg_rec_count
= 1;
10274 else if (3 == arm_insn_r
->decode
&& 0x12 == opcode1
10275 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10277 /* Handle BLX, branch and link/exchange. */
10278 if (9 == arm_insn_r
->opcode
)
10280 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
10281 and R14 stores the return address. */
10282 record_buf
[0] = ARM_PS_REGNUM
;
10283 record_buf
[1] = ARM_LR_REGNUM
;
10284 arm_insn_r
->reg_rec_count
= 2;
10287 else if (7 == arm_insn_r
->decode
&& 0x12 == opcode1
)
10289 /* Handle enhanced software breakpoint insn, BKPT. */
10290 /* CPSR is changed to be executed in ARM state, disabling normal
10291 interrupts, entering abort mode. */
10292 /* According to high vector configuration PC is set. */
10293 /* user hit breakpoint and type reverse, in
10294 that case, we need to go back with previous CPSR and
10295 Program Counter. */
10296 record_buf
[0] = ARM_PS_REGNUM
;
10297 record_buf
[1] = ARM_LR_REGNUM
;
10298 arm_insn_r
->reg_rec_count
= 2;
10300 /* Save SPSR also; how? */
10303 else if (11 == arm_insn_r
->decode
10304 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10306 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
10308 /* Handle str(x) insn */
10309 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10312 else if (1 == arm_insn_r
->decode
&& 0x12 == opcode1
10313 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10315 /* Handle BX, branch and link/exchange. */
10316 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
10317 record_buf
[0] = ARM_PS_REGNUM
;
10318 arm_insn_r
->reg_rec_count
= 1;
10320 else if (1 == arm_insn_r
->decode
&& 0x16 == opcode1
10321 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 4, 1)
10322 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1))
10324 /* Count leading zeros: CLZ. */
10325 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10326 arm_insn_r
->reg_rec_count
= 1;
10328 else if (!bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
10329 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10330 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1)
10331 && sbo_sbz (arm_insn_r
->arm_insn
, 1, 12, 0)
10334 /* Handle MRS insn. */
10335 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10336 arm_insn_r
->reg_rec_count
= 1;
10338 else if (arm_insn_r
->opcode
<= 15)
10340 /* Normal data processing insns. */
10341 /* Out of 11 shifter operands mode, all the insn modifies destination
10342 register, which is specified by 13-16 decode. */
10343 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10344 record_buf
[1] = ARM_PS_REGNUM
;
10345 arm_insn_r
->reg_rec_count
= 2;
10352 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10353 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10357 /* Handling opcode 001 insns. */
10360 arm_record_data_proc_imm (insn_decode_record
*arm_insn_r
)
10362 uint32_t record_buf
[8], record_buf_mem
[8];
10364 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10365 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10367 if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
10368 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21)
10369 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
10372 /* Handle MSR insn. */
10373 if (9 == arm_insn_r
->opcode
)
10375 /* CSPR is going to be changed. */
10376 record_buf
[0] = ARM_PS_REGNUM
;
10377 arm_insn_r
->reg_rec_count
= 1;
10381 /* SPSR is going to be changed. */
10384 else if (arm_insn_r
->opcode
<= 15)
10386 /* Normal data processing insns. */
10387 /* Out of 11 shifter operands mode, all the insn modifies destination
10388 register, which is specified by 13-16 decode. */
10389 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10390 record_buf
[1] = ARM_PS_REGNUM
;
10391 arm_insn_r
->reg_rec_count
= 2;
10398 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10399 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10404 arm_record_media (insn_decode_record
*arm_insn_r
)
10406 uint32_t record_buf
[8];
10408 switch (bits (arm_insn_r
->arm_insn
, 22, 24))
10411 /* Parallel addition and subtraction, signed */
10413 /* Parallel addition and subtraction, unsigned */
10416 /* Packing, unpacking, saturation and reversal */
10418 int rd
= bits (arm_insn_r
->arm_insn
, 12, 15);
10420 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10426 /* Signed multiplies */
10428 int rd
= bits (arm_insn_r
->arm_insn
, 16, 19);
10429 unsigned int op1
= bits (arm_insn_r
->arm_insn
, 20, 22);
10431 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10433 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10434 else if (op1
== 0x4)
10435 record_buf
[arm_insn_r
->reg_rec_count
++]
10436 = bits (arm_insn_r
->arm_insn
, 12, 15);
10442 if (bit (arm_insn_r
->arm_insn
, 21)
10443 && bits (arm_insn_r
->arm_insn
, 5, 6) == 0x2)
10446 record_buf
[arm_insn_r
->reg_rec_count
++]
10447 = bits (arm_insn_r
->arm_insn
, 12, 15);
10449 else if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x0
10450 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x0)
10452 /* USAD8 and USADA8 */
10453 record_buf
[arm_insn_r
->reg_rec_count
++]
10454 = bits (arm_insn_r
->arm_insn
, 16, 19);
10461 if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x3
10462 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x7)
10464 /* Permanently UNDEFINED */
10469 /* BFC, BFI and UBFX */
10470 record_buf
[arm_insn_r
->reg_rec_count
++]
10471 = bits (arm_insn_r
->arm_insn
, 12, 15);
10480 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10485 /* Handle ARM mode instructions with opcode 010. */
10488 arm_record_ld_st_imm_offset (insn_decode_record
*arm_insn_r
)
10490 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10492 uint32_t reg_base
, reg_dest
;
10493 uint32_t offset_12
, tgt_mem_addr
;
10494 uint32_t record_buf
[8], record_buf_mem
[8];
10495 unsigned char wback
;
10498 /* Calculate wback. */
10499 wback
= (bit (arm_insn_r
->arm_insn
, 24) == 0)
10500 || (bit (arm_insn_r
->arm_insn
, 21) == 1);
10502 arm_insn_r
->reg_rec_count
= 0;
10503 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
10505 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10507 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
10510 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10511 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_dest
;
10513 /* The LDR instruction is capable of doing branching. If MOV LR, PC
10514 preceeds a LDR instruction having R15 as reg_base, it
10515 emulates a branch and link instruction, and hence we need to save
10516 CPSR and PC as well. */
10517 if (ARM_PC_REGNUM
== reg_dest
)
10518 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10520 /* If wback is true, also save the base register, which is going to be
10523 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10527 /* STR (immediate), STRB (immediate), STRBT and STRT. */
10529 offset_12
= bits (arm_insn_r
->arm_insn
, 0, 11);
10530 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
10532 /* Handle bit U. */
10533 if (bit (arm_insn_r
->arm_insn
, 23))
10535 /* U == 1: Add the offset. */
10536 tgt_mem_addr
= (uint32_t) u_regval
+ offset_12
;
10540 /* U == 0: subtract the offset. */
10541 tgt_mem_addr
= (uint32_t) u_regval
- offset_12
;
10544 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
10546 if (bit (arm_insn_r
->arm_insn
, 22))
10548 /* STRB and STRBT: 1 byte. */
10549 record_buf_mem
[0] = 1;
10553 /* STR and STRT: 4 bytes. */
10554 record_buf_mem
[0] = 4;
10557 /* Handle bit P. */
10558 if (bit (arm_insn_r
->arm_insn
, 24))
10559 record_buf_mem
[1] = tgt_mem_addr
;
10561 record_buf_mem
[1] = (uint32_t) u_regval
;
10563 arm_insn_r
->mem_rec_count
= 1;
10565 /* If wback is true, also save the base register, which is going to be
10568 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10571 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10572 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10576 /* Handling opcode 011 insns. */
10579 arm_record_ld_st_reg_offset (insn_decode_record
*arm_insn_r
)
10581 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10583 uint32_t shift_imm
= 0;
10584 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
10585 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
10586 uint32_t record_buf
[8], record_buf_mem
[8];
10589 ULONGEST u_regval
[2];
10591 if (bit (arm_insn_r
->arm_insn
, 4))
10592 return arm_record_media (arm_insn_r
);
10594 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10595 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10597 /* Handle enhanced store insns and LDRD DSP insn,
10598 order begins according to addressing modes for store insns
10602 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10604 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10605 /* LDR insn has a capability to do branching, if
10606 MOV LR, PC is precedded by LDR insn having Rn as R15
10607 in that case, it emulates branch and link insn, and hence we
10608 need to save CSPR and PC as well. */
10609 if (15 != reg_dest
)
10611 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10612 arm_insn_r
->reg_rec_count
= 1;
10616 record_buf
[0] = reg_dest
;
10617 record_buf
[1] = ARM_PS_REGNUM
;
10618 arm_insn_r
->reg_rec_count
= 2;
10623 if (! bits (arm_insn_r
->arm_insn
, 4, 11))
10625 /* Store insn, register offset and register pre-indexed,
10626 register post-indexed. */
10628 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10630 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10631 regcache_raw_read_unsigned (reg_cache
, reg_src1
10633 regcache_raw_read_unsigned (reg_cache
, reg_src2
10635 if (15 == reg_src2
)
10637 /* If R15 was used as Rn, hence current PC+8. */
10638 /* Pre-indexed mode doesnt reach here ; illegal insn. */
10639 u_regval
[0] = u_regval
[0] + 8;
10641 /* Calculate target store address, Rn +/- Rm, register offset. */
10643 if (bit (arm_insn_r
->arm_insn
, 23))
10645 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10649 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10652 switch (arm_insn_r
->opcode
)
10666 record_buf_mem
[0] = 4;
10681 record_buf_mem
[0] = 1;
10685 gdb_assert_not_reached ("no decoding pattern found");
10688 record_buf_mem
[1] = tgt_mem_addr
;
10689 arm_insn_r
->mem_rec_count
= 1;
10691 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10692 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10693 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10694 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10695 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10696 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10699 /* Rn is going to be changed in pre-indexed mode and
10700 post-indexed mode as well. */
10701 record_buf
[0] = reg_src2
;
10702 arm_insn_r
->reg_rec_count
= 1;
10707 /* Store insn, scaled register offset; scaled pre-indexed. */
10708 offset_12
= bits (arm_insn_r
->arm_insn
, 5, 6);
10710 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10712 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10713 /* Get shift_imm. */
10714 shift_imm
= bits (arm_insn_r
->arm_insn
, 7, 11);
10715 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10716 regcache_raw_read_signed (reg_cache
, reg_src1
, &s_word
);
10717 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10718 /* Offset_12 used as shift. */
10722 /* Offset_12 used as index. */
10723 offset_12
= u_regval
[0] << shift_imm
;
10727 offset_12
= (!shift_imm
)?0:u_regval
[0] >> shift_imm
;
10733 if (bit (u_regval
[0], 31))
10735 offset_12
= 0xFFFFFFFF;
10744 /* This is arithmetic shift. */
10745 offset_12
= s_word
>> shift_imm
;
10752 regcache_raw_read_unsigned (reg_cache
, ARM_PS_REGNUM
,
10754 /* Get C flag value and shift it by 31. */
10755 offset_12
= (((bit (u_regval
[1], 29)) << 31) \
10756 | (u_regval
[0]) >> 1);
10760 offset_12
= (u_regval
[0] >> shift_imm
) \
10762 (sizeof(uint32_t) - shift_imm
));
10767 gdb_assert_not_reached ("no decoding pattern found");
10771 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10773 if (bit (arm_insn_r
->arm_insn
, 23))
10775 tgt_mem_addr
= u_regval
[1] + offset_12
;
10779 tgt_mem_addr
= u_regval
[1] - offset_12
;
10782 switch (arm_insn_r
->opcode
)
10796 record_buf_mem
[0] = 4;
10811 record_buf_mem
[0] = 1;
10815 gdb_assert_not_reached ("no decoding pattern found");
10818 record_buf_mem
[1] = tgt_mem_addr
;
10819 arm_insn_r
->mem_rec_count
= 1;
10821 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10822 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10823 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10824 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10825 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10826 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10829 /* Rn is going to be changed in register scaled pre-indexed
10830 mode,and scaled post indexed mode. */
10831 record_buf
[0] = reg_src2
;
10832 arm_insn_r
->reg_rec_count
= 1;
10837 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10838 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10842 /* Handle ARM mode instructions with opcode 100. */
10845 arm_record_ld_st_multiple (insn_decode_record
*arm_insn_r
)
10847 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10848 uint32_t register_count
= 0, register_bits
;
10849 uint32_t reg_base
, addr_mode
;
10850 uint32_t record_buf
[24], record_buf_mem
[48];
10854 /* Fetch the list of registers. */
10855 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
10856 arm_insn_r
->reg_rec_count
= 0;
10858 /* Fetch the base register that contains the address we are loading data
10860 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
10862 /* Calculate wback. */
10863 wback
= (bit (arm_insn_r
->arm_insn
, 21) == 1);
10865 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10867 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
10869 /* Find out which registers are going to be loaded from memory. */
10870 while (register_bits
)
10872 if (register_bits
& 0x00000001)
10873 record_buf
[arm_insn_r
->reg_rec_count
++] = register_count
;
10874 register_bits
= register_bits
>> 1;
10879 /* If wback is true, also save the base register, which is going to be
10882 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10884 /* Save the CPSR register. */
10885 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10889 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
10891 addr_mode
= bits (arm_insn_r
->arm_insn
, 23, 24);
10893 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
10895 /* Find out how many registers are going to be stored to memory. */
10896 while (register_bits
)
10898 if (register_bits
& 0x00000001)
10900 register_bits
= register_bits
>> 1;
10905 /* STMDA (STMED): Decrement after. */
10907 record_buf_mem
[1] = (uint32_t) u_regval
10908 - register_count
* INT_REGISTER_SIZE
+ 4;
10910 /* STM (STMIA, STMEA): Increment after. */
10912 record_buf_mem
[1] = (uint32_t) u_regval
;
10914 /* STMDB (STMFD): Decrement before. */
10916 record_buf_mem
[1] = (uint32_t) u_regval
10917 - register_count
* INT_REGISTER_SIZE
;
10919 /* STMIB (STMFA): Increment before. */
10921 record_buf_mem
[1] = (uint32_t) u_regval
+ INT_REGISTER_SIZE
;
10924 gdb_assert_not_reached ("no decoding pattern found");
10928 record_buf_mem
[0] = register_count
* INT_REGISTER_SIZE
;
10929 arm_insn_r
->mem_rec_count
= 1;
10931 /* If wback is true, also save the base register, which is going to be
10934 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10937 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10938 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10942 /* Handling opcode 101 insns. */
10945 arm_record_b_bl (insn_decode_record
*arm_insn_r
)
10947 uint32_t record_buf
[8];
10949 /* Handle B, BL, BLX(1) insns. */
10950 /* B simply branches so we do nothing here. */
10951 /* Note: BLX(1) doesnt fall here but instead it falls into
10952 extension space. */
10953 if (bit (arm_insn_r
->arm_insn
, 24))
10955 record_buf
[0] = ARM_LR_REGNUM
;
10956 arm_insn_r
->reg_rec_count
= 1;
10959 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10965 arm_record_unsupported_insn (insn_decode_record
*arm_insn_r
)
10967 printf_unfiltered (_("Process record does not support instruction "
10968 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
10969 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
10974 /* Record handler for vector data transfer instructions. */
10977 arm_record_vdata_transfer_insn (insn_decode_record
*arm_insn_r
)
10979 uint32_t bits_a
, bit_c
, bit_l
, reg_t
, reg_v
;
10980 uint32_t record_buf
[4];
10982 const int num_regs
= gdbarch_num_regs (arm_insn_r
->gdbarch
);
10983 reg_t
= bits (arm_insn_r
->arm_insn
, 12, 15);
10984 reg_v
= bits (arm_insn_r
->arm_insn
, 21, 23);
10985 bits_a
= bits (arm_insn_r
->arm_insn
, 21, 23);
10986 bit_l
= bit (arm_insn_r
->arm_insn
, 20);
10987 bit_c
= bit (arm_insn_r
->arm_insn
, 8);
10989 /* Handle VMOV instruction. */
10990 if (bit_l
&& bit_c
)
10992 record_buf
[0] = reg_t
;
10993 arm_insn_r
->reg_rec_count
= 1;
10995 else if (bit_l
&& !bit_c
)
10997 /* Handle VMOV instruction. */
10998 if (bits_a
== 0x00)
11000 record_buf
[0] = reg_t
;
11001 arm_insn_r
->reg_rec_count
= 1;
11003 /* Handle VMRS instruction. */
11004 else if (bits_a
== 0x07)
11007 reg_t
= ARM_PS_REGNUM
;
11009 record_buf
[0] = reg_t
;
11010 arm_insn_r
->reg_rec_count
= 1;
11013 else if (!bit_l
&& !bit_c
)
11015 /* Handle VMOV instruction. */
11016 if (bits_a
== 0x00)
11018 record_buf
[0] = ARM_D0_REGNUM
+ reg_v
;
11020 arm_insn_r
->reg_rec_count
= 1;
11022 /* Handle VMSR instruction. */
11023 else if (bits_a
== 0x07)
11025 record_buf
[0] = ARM_FPSCR_REGNUM
;
11026 arm_insn_r
->reg_rec_count
= 1;
11029 else if (!bit_l
&& bit_c
)
11031 /* Handle VMOV instruction. */
11032 if (!(bits_a
& 0x04))
11034 record_buf
[0] = (reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4))
11036 arm_insn_r
->reg_rec_count
= 1;
11038 /* Handle VDUP instruction. */
11041 if (bit (arm_insn_r
->arm_insn
, 21))
11043 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11044 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11045 record_buf
[1] = reg_v
+ ARM_D0_REGNUM
+ 1;
11046 arm_insn_r
->reg_rec_count
= 2;
11050 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11051 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11052 arm_insn_r
->reg_rec_count
= 1;
11057 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11061 /* Record handler for extension register load/store instructions. */
11064 arm_record_exreg_ld_st_insn (insn_decode_record
*arm_insn_r
)
11066 uint32_t opcode
, single_reg
;
11067 uint8_t op_vldm_vstm
;
11068 uint32_t record_buf
[8], record_buf_mem
[128];
11069 ULONGEST u_regval
= 0;
11071 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11072 const int num_regs
= gdbarch_num_regs (arm_insn_r
->gdbarch
);
11074 opcode
= bits (arm_insn_r
->arm_insn
, 20, 24);
11075 single_reg
= !bit (arm_insn_r
->arm_insn
, 8);
11076 op_vldm_vstm
= opcode
& 0x1b;
11078 /* Handle VMOV instructions. */
11079 if ((opcode
& 0x1e) == 0x04)
11081 if (bit (arm_insn_r
->arm_insn
, 20)) /* to_arm_registers bit 20? */
11083 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11084 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11085 arm_insn_r
->reg_rec_count
= 2;
11089 uint8_t reg_m
= bits (arm_insn_r
->arm_insn
, 0, 3);
11090 uint8_t bit_m
= bit (arm_insn_r
->arm_insn
, 5);
11094 /* The first S register number m is REG_M:M (M is bit 5),
11095 the corresponding D register number is REG_M:M / 2, which
11097 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_D0_REGNUM
+ reg_m
;
11098 /* The second S register number is REG_M:M + 1, the
11099 corresponding D register number is (REG_M:M + 1) / 2.
11100 IOW, if bit M is 1, the first and second S registers
11101 are mapped to different D registers, otherwise, they are
11102 in the same D register. */
11105 record_buf
[arm_insn_r
->reg_rec_count
++]
11106 = ARM_D0_REGNUM
+ reg_m
+ 1;
11111 record_buf
[0] = ((bit_m
<< 4) + reg_m
+ ARM_D0_REGNUM
);
11112 arm_insn_r
->reg_rec_count
= 1;
11116 /* Handle VSTM and VPUSH instructions. */
11117 else if (op_vldm_vstm
== 0x08 || op_vldm_vstm
== 0x0a
11118 || op_vldm_vstm
== 0x12)
11120 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
11121 uint32_t memory_index
= 0;
11123 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11124 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11125 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11126 imm_off32
= imm_off8
<< 2;
11127 memory_count
= imm_off8
;
11129 if (bit (arm_insn_r
->arm_insn
, 23))
11130 start_address
= u_regval
;
11132 start_address
= u_regval
- imm_off32
;
11134 if (bit (arm_insn_r
->arm_insn
, 21))
11136 record_buf
[0] = reg_rn
;
11137 arm_insn_r
->reg_rec_count
= 1;
11140 while (memory_count
> 0)
11144 record_buf_mem
[memory_index
] = 4;
11145 record_buf_mem
[memory_index
+ 1] = start_address
;
11146 start_address
= start_address
+ 4;
11147 memory_index
= memory_index
+ 2;
11151 record_buf_mem
[memory_index
] = 4;
11152 record_buf_mem
[memory_index
+ 1] = start_address
;
11153 record_buf_mem
[memory_index
+ 2] = 4;
11154 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11155 start_address
= start_address
+ 8;
11156 memory_index
= memory_index
+ 4;
11160 arm_insn_r
->mem_rec_count
= (memory_index
>> 1);
11162 /* Handle VLDM instructions. */
11163 else if (op_vldm_vstm
== 0x09 || op_vldm_vstm
== 0x0b
11164 || op_vldm_vstm
== 0x13)
11166 uint32_t reg_count
, reg_vd
;
11167 uint32_t reg_index
= 0;
11168 uint32_t bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11170 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11171 reg_count
= bits (arm_insn_r
->arm_insn
, 0, 7);
11173 /* REG_VD is the first D register number. If the instruction
11174 loads memory to S registers (SINGLE_REG is TRUE), the register
11175 number is (REG_VD << 1 | bit D), so the corresponding D
11176 register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */
11178 reg_vd
= reg_vd
| (bit_d
<< 4);
11180 if (bit (arm_insn_r
->arm_insn
, 21) /* write back */)
11181 record_buf
[reg_index
++] = bits (arm_insn_r
->arm_insn
, 16, 19);
11183 /* If the instruction loads memory to D register, REG_COUNT should
11184 be divided by 2, according to the ARM Architecture Reference
11185 Manual. If the instruction loads memory to S register, divide by
11186 2 as well because two S registers are mapped to D register. */
11187 reg_count
= reg_count
/ 2;
11188 if (single_reg
&& bit_d
)
11190 /* Increase the register count if S register list starts from
11191 an odd number (bit d is one). */
11195 while (reg_count
> 0)
11197 record_buf
[reg_index
++] = ARM_D0_REGNUM
+ reg_vd
+ reg_count
- 1;
11200 arm_insn_r
->reg_rec_count
= reg_index
;
11202 /* VSTR Vector store register. */
11203 else if ((opcode
& 0x13) == 0x10)
11205 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
;
11206 uint32_t memory_index
= 0;
11208 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11209 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11210 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11211 imm_off32
= imm_off8
<< 2;
11213 if (bit (arm_insn_r
->arm_insn
, 23))
11214 start_address
= u_regval
+ imm_off32
;
11216 start_address
= u_regval
- imm_off32
;
11220 record_buf_mem
[memory_index
] = 4;
11221 record_buf_mem
[memory_index
+ 1] = start_address
;
11222 arm_insn_r
->mem_rec_count
= 1;
11226 record_buf_mem
[memory_index
] = 4;
11227 record_buf_mem
[memory_index
+ 1] = start_address
;
11228 record_buf_mem
[memory_index
+ 2] = 4;
11229 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11230 arm_insn_r
->mem_rec_count
= 2;
11233 /* VLDR Vector load register. */
11234 else if ((opcode
& 0x13) == 0x11)
11236 uint32_t reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11240 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
11241 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
;
11245 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
11246 /* Record register D rather than pseudo register S. */
11247 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
/ 2;
11249 arm_insn_r
->reg_rec_count
= 1;
11252 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11253 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11257 /* Record handler for arm/thumb mode VFP data processing instructions. */
11260 arm_record_vfp_data_proc_insn (insn_decode_record
*arm_insn_r
)
11262 uint32_t opc1
, opc2
, opc3
, dp_op_sz
, bit_d
, reg_vd
;
11263 uint32_t record_buf
[4];
11264 enum insn_types
{INSN_T0
, INSN_T1
, INSN_T2
, INSN_T3
, INSN_INV
};
11265 enum insn_types curr_insn_type
= INSN_INV
;
11267 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11268 opc1
= bits (arm_insn_r
->arm_insn
, 20, 23);
11269 opc2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11270 opc3
= bits (arm_insn_r
->arm_insn
, 6, 7);
11271 dp_op_sz
= bit (arm_insn_r
->arm_insn
, 8);
11272 bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11273 opc1
= opc1
& 0x04;
11275 /* Handle VMLA, VMLS. */
11278 if (bit (arm_insn_r
->arm_insn
, 10))
11280 if (bit (arm_insn_r
->arm_insn
, 6))
11281 curr_insn_type
= INSN_T0
;
11283 curr_insn_type
= INSN_T1
;
11288 curr_insn_type
= INSN_T1
;
11290 curr_insn_type
= INSN_T2
;
11293 /* Handle VNMLA, VNMLS, VNMUL. */
11294 else if (opc1
== 0x01)
11297 curr_insn_type
= INSN_T1
;
11299 curr_insn_type
= INSN_T2
;
11302 else if (opc1
== 0x02 && !(opc3
& 0x01))
11304 if (bit (arm_insn_r
->arm_insn
, 10))
11306 if (bit (arm_insn_r
->arm_insn
, 6))
11307 curr_insn_type
= INSN_T0
;
11309 curr_insn_type
= INSN_T1
;
11314 curr_insn_type
= INSN_T1
;
11316 curr_insn_type
= INSN_T2
;
11319 /* Handle VADD, VSUB. */
11320 else if (opc1
== 0x03)
11322 if (!bit (arm_insn_r
->arm_insn
, 9))
11324 if (bit (arm_insn_r
->arm_insn
, 6))
11325 curr_insn_type
= INSN_T0
;
11327 curr_insn_type
= INSN_T1
;
11332 curr_insn_type
= INSN_T1
;
11334 curr_insn_type
= INSN_T2
;
11338 else if (opc1
== 0x0b)
11341 curr_insn_type
= INSN_T1
;
11343 curr_insn_type
= INSN_T2
;
11345 /* Handle all other vfp data processing instructions. */
11346 else if (opc1
== 0x0b)
11349 if (!(opc3
& 0x01) || (opc2
== 0x00 && opc3
== 0x01))
11351 if (bit (arm_insn_r
->arm_insn
, 4))
11353 if (bit (arm_insn_r
->arm_insn
, 6))
11354 curr_insn_type
= INSN_T0
;
11356 curr_insn_type
= INSN_T1
;
11361 curr_insn_type
= INSN_T1
;
11363 curr_insn_type
= INSN_T2
;
11366 /* Handle VNEG and VABS. */
11367 else if ((opc2
== 0x01 && opc3
== 0x01)
11368 || (opc2
== 0x00 && opc3
== 0x03))
11370 if (!bit (arm_insn_r
->arm_insn
, 11))
11372 if (bit (arm_insn_r
->arm_insn
, 6))
11373 curr_insn_type
= INSN_T0
;
11375 curr_insn_type
= INSN_T1
;
11380 curr_insn_type
= INSN_T1
;
11382 curr_insn_type
= INSN_T2
;
11385 /* Handle VSQRT. */
11386 else if (opc2
== 0x01 && opc3
== 0x03)
11389 curr_insn_type
= INSN_T1
;
11391 curr_insn_type
= INSN_T2
;
11394 else if (opc2
== 0x07 && opc3
== 0x03)
11397 curr_insn_type
= INSN_T1
;
11399 curr_insn_type
= INSN_T2
;
11401 else if (opc3
& 0x01)
11404 if ((opc2
== 0x08) || (opc2
& 0x0e) == 0x0c)
11406 if (!bit (arm_insn_r
->arm_insn
, 18))
11407 curr_insn_type
= INSN_T2
;
11411 curr_insn_type
= INSN_T1
;
11413 curr_insn_type
= INSN_T2
;
11417 else if ((opc2
& 0x0e) == 0x0a || (opc2
& 0x0e) == 0x0e)
11420 curr_insn_type
= INSN_T1
;
11422 curr_insn_type
= INSN_T2
;
11424 /* Handle VCVTB, VCVTT. */
11425 else if ((opc2
& 0x0e) == 0x02)
11426 curr_insn_type
= INSN_T2
;
11427 /* Handle VCMP, VCMPE. */
11428 else if ((opc2
& 0x0e) == 0x04)
11429 curr_insn_type
= INSN_T3
;
11433 switch (curr_insn_type
)
11436 reg_vd
= reg_vd
| (bit_d
<< 4);
11437 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11438 record_buf
[1] = reg_vd
+ ARM_D0_REGNUM
+ 1;
11439 arm_insn_r
->reg_rec_count
= 2;
11443 reg_vd
= reg_vd
| (bit_d
<< 4);
11444 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11445 arm_insn_r
->reg_rec_count
= 1;
11449 reg_vd
= (reg_vd
<< 1) | bit_d
;
11450 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11451 arm_insn_r
->reg_rec_count
= 1;
11455 record_buf
[0] = ARM_FPSCR_REGNUM
;
11456 arm_insn_r
->reg_rec_count
= 1;
11460 gdb_assert_not_reached ("no decoding pattern found");
11464 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11468 /* Handling opcode 110 insns. */
11471 arm_record_asimd_vfp_coproc (insn_decode_record
*arm_insn_r
)
11473 uint32_t op1
, op1_ebit
, coproc
;
11475 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11476 op1
= bits (arm_insn_r
->arm_insn
, 20, 25);
11477 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11479 if ((coproc
& 0x0e) == 0x0a)
11481 /* Handle extension register ld/st instructions. */
11483 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11485 /* 64-bit transfers between arm core and extension registers. */
11486 if ((op1
& 0x3e) == 0x04)
11487 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11491 /* Handle coprocessor ld/st instructions. */
11496 return arm_record_unsupported_insn (arm_insn_r
);
11499 return arm_record_unsupported_insn (arm_insn_r
);
11502 /* Move to coprocessor from two arm core registers. */
11504 return arm_record_unsupported_insn (arm_insn_r
);
11506 /* Move to two arm core registers from coprocessor. */
11511 reg_t
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11512 reg_t
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11513 arm_insn_r
->reg_rec_count
= 2;
11515 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, reg_t
);
11519 return arm_record_unsupported_insn (arm_insn_r
);
11522 /* Handling opcode 111 insns. */
11525 arm_record_coproc_data_proc (insn_decode_record
*arm_insn_r
)
11527 uint32_t op
, op1_sbit
, op1_ebit
, coproc
;
11528 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arm_insn_r
->gdbarch
);
11529 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11531 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 24, 27);
11532 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11533 op1_sbit
= bit (arm_insn_r
->arm_insn
, 24);
11534 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11535 op
= bit (arm_insn_r
->arm_insn
, 4);
11537 /* Handle arm SWI/SVC system call instructions. */
11540 if (tdep
->arm_syscall_record
!= NULL
)
11542 ULONGEST svc_operand
, svc_number
;
11544 svc_operand
= (0x00ffffff & arm_insn_r
->arm_insn
);
11546 if (svc_operand
) /* OABI. */
11547 svc_number
= svc_operand
- 0x900000;
11549 regcache_raw_read_unsigned (reg_cache
, 7, &svc_number
);
11551 return tdep
->arm_syscall_record (reg_cache
, svc_number
);
11555 printf_unfiltered (_("no syscall record support\n"));
11560 if ((coproc
& 0x0e) == 0x0a)
11562 /* VFP data-processing instructions. */
11563 if (!op1_sbit
&& !op
)
11564 return arm_record_vfp_data_proc_insn (arm_insn_r
);
11566 /* Advanced SIMD, VFP instructions. */
11567 if (!op1_sbit
&& op
)
11568 return arm_record_vdata_transfer_insn (arm_insn_r
);
11572 /* Coprocessor data operations. */
11573 if (!op1_sbit
&& !op
)
11574 return arm_record_unsupported_insn (arm_insn_r
);
11576 /* Move to Coprocessor from ARM core register. */
11577 if (!op1_sbit
&& !op1_ebit
&& op
)
11578 return arm_record_unsupported_insn (arm_insn_r
);
11580 /* Move to arm core register from coprocessor. */
11581 if (!op1_sbit
&& op1_ebit
&& op
)
11583 uint32_t record_buf
[1];
11585 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11586 if (record_buf
[0] == 15)
11587 record_buf
[0] = ARM_PS_REGNUM
;
11589 arm_insn_r
->reg_rec_count
= 1;
11590 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
,
11596 return arm_record_unsupported_insn (arm_insn_r
);
11599 /* Handling opcode 000 insns. */
11602 thumb_record_shift_add_sub (insn_decode_record
*thumb_insn_r
)
11604 uint32_t record_buf
[8];
11605 uint32_t reg_src1
= 0;
11607 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11609 record_buf
[0] = ARM_PS_REGNUM
;
11610 record_buf
[1] = reg_src1
;
11611 thumb_insn_r
->reg_rec_count
= 2;
11613 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11619 /* Handling opcode 001 insns. */
11622 thumb_record_add_sub_cmp_mov (insn_decode_record
*thumb_insn_r
)
11624 uint32_t record_buf
[8];
11625 uint32_t reg_src1
= 0;
11627 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11629 record_buf
[0] = ARM_PS_REGNUM
;
11630 record_buf
[1] = reg_src1
;
11631 thumb_insn_r
->reg_rec_count
= 2;
11633 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11638 /* Handling opcode 010 insns. */
11641 thumb_record_ld_st_reg_offset (insn_decode_record
*thumb_insn_r
)
11643 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11644 uint32_t record_buf
[8], record_buf_mem
[8];
11646 uint32_t reg_src1
= 0, reg_src2
= 0;
11647 uint32_t opcode1
= 0, opcode2
= 0, opcode3
= 0;
11649 ULONGEST u_regval
[2] = {0};
11651 opcode1
= bits (thumb_insn_r
->arm_insn
, 10, 12);
11653 if (bit (thumb_insn_r
->arm_insn
, 12))
11655 /* Handle load/store register offset. */
11656 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 10);
11657 if (opcode2
>= 12 && opcode2
<= 15)
11659 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
11660 reg_src1
= bits (thumb_insn_r
->arm_insn
,0, 2);
11661 record_buf
[0] = reg_src1
;
11662 thumb_insn_r
->reg_rec_count
= 1;
11664 else if (opcode2
>= 8 && opcode2
<= 10)
11666 /* STR(2), STRB(2), STRH(2) . */
11667 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11668 reg_src2
= bits (thumb_insn_r
->arm_insn
, 6, 8);
11669 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11670 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11672 record_buf_mem
[0] = 4; /* STR (2). */
11673 else if (10 == opcode2
)
11674 record_buf_mem
[0] = 1; /* STRB (2). */
11675 else if (9 == opcode2
)
11676 record_buf_mem
[0] = 2; /* STRH (2). */
11677 record_buf_mem
[1] = u_regval
[0] + u_regval
[1];
11678 thumb_insn_r
->mem_rec_count
= 1;
11681 else if (bit (thumb_insn_r
->arm_insn
, 11))
11683 /* Handle load from literal pool. */
11685 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11686 record_buf
[0] = reg_src1
;
11687 thumb_insn_r
->reg_rec_count
= 1;
11691 opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 9);
11692 opcode3
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11693 if ((3 == opcode2
) && (!opcode3
))
11695 /* Branch with exchange. */
11696 record_buf
[0] = ARM_PS_REGNUM
;
11697 thumb_insn_r
->reg_rec_count
= 1;
11701 /* Format 8; special data processing insns. */
11702 record_buf
[0] = ARM_PS_REGNUM
;
11703 record_buf
[1] = (bit (thumb_insn_r
->arm_insn
, 7) << 3
11704 | bits (thumb_insn_r
->arm_insn
, 0, 2));
11705 thumb_insn_r
->reg_rec_count
= 2;
11710 /* Format 5; data processing insns. */
11711 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11712 if (bit (thumb_insn_r
->arm_insn
, 7))
11714 reg_src1
= reg_src1
+ 8;
11716 record_buf
[0] = ARM_PS_REGNUM
;
11717 record_buf
[1] = reg_src1
;
11718 thumb_insn_r
->reg_rec_count
= 2;
11721 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11722 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11728 /* Handling opcode 001 insns. */
11731 thumb_record_ld_st_imm_offset (insn_decode_record
*thumb_insn_r
)
11733 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11734 uint32_t record_buf
[8], record_buf_mem
[8];
11736 uint32_t reg_src1
= 0;
11737 uint32_t opcode
= 0, immed_5
= 0;
11739 ULONGEST u_regval
= 0;
11741 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11746 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11747 record_buf
[0] = reg_src1
;
11748 thumb_insn_r
->reg_rec_count
= 1;
11753 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11754 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11755 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11756 record_buf_mem
[0] = 4;
11757 record_buf_mem
[1] = u_regval
+ (immed_5
* 4);
11758 thumb_insn_r
->mem_rec_count
= 1;
11761 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11762 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11768 /* Handling opcode 100 insns. */
11771 thumb_record_ld_st_stack (insn_decode_record
*thumb_insn_r
)
11773 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11774 uint32_t record_buf
[8], record_buf_mem
[8];
11776 uint32_t reg_src1
= 0;
11777 uint32_t opcode
= 0, immed_8
= 0, immed_5
= 0;
11779 ULONGEST u_regval
= 0;
11781 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11786 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11787 record_buf
[0] = reg_src1
;
11788 thumb_insn_r
->reg_rec_count
= 1;
11790 else if (1 == opcode
)
11793 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11794 record_buf
[0] = reg_src1
;
11795 thumb_insn_r
->reg_rec_count
= 1;
11797 else if (2 == opcode
)
11800 immed_8
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11801 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
11802 record_buf_mem
[0] = 4;
11803 record_buf_mem
[1] = u_regval
+ (immed_8
* 4);
11804 thumb_insn_r
->mem_rec_count
= 1;
11806 else if (0 == opcode
)
11809 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11810 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11811 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11812 record_buf_mem
[0] = 2;
11813 record_buf_mem
[1] = u_regval
+ (immed_5
* 2);
11814 thumb_insn_r
->mem_rec_count
= 1;
11817 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11818 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11824 /* Handling opcode 101 insns. */
11827 thumb_record_misc (insn_decode_record
*thumb_insn_r
)
11829 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11831 uint32_t opcode
= 0, opcode1
= 0, opcode2
= 0;
11832 uint32_t register_bits
= 0, register_count
= 0;
11833 uint32_t index
= 0, start_address
= 0;
11834 uint32_t record_buf
[24], record_buf_mem
[48];
11837 ULONGEST u_regval
= 0;
11839 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11840 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
11841 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 12);
11846 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11847 while (register_bits
)
11849 if (register_bits
& 0x00000001)
11850 record_buf
[index
++] = register_count
;
11851 register_bits
= register_bits
>> 1;
11854 record_buf
[index
++] = ARM_PS_REGNUM
;
11855 record_buf
[index
++] = ARM_SP_REGNUM
;
11856 thumb_insn_r
->reg_rec_count
= index
;
11858 else if (10 == opcode2
)
11861 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11862 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
11863 while (register_bits
)
11865 if (register_bits
& 0x00000001)
11867 register_bits
= register_bits
>> 1;
11869 start_address
= u_regval
- \
11870 (4 * (bit (thumb_insn_r
->arm_insn
, 8) + register_count
));
11871 thumb_insn_r
->mem_rec_count
= register_count
;
11872 while (register_count
)
11874 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11875 record_buf_mem
[(register_count
* 2) - 2] = 4;
11876 start_address
= start_address
+ 4;
11879 record_buf
[0] = ARM_SP_REGNUM
;
11880 thumb_insn_r
->reg_rec_count
= 1;
11882 else if (0x1E == opcode1
)
11885 /* Handle enhanced software breakpoint insn, BKPT. */
11886 /* CPSR is changed to be executed in ARM state, disabling normal
11887 interrupts, entering abort mode. */
11888 /* According to high vector configuration PC is set. */
11889 /* User hits breakpoint and type reverse, in that case, we need to go back with
11890 previous CPSR and Program Counter. */
11891 record_buf
[0] = ARM_PS_REGNUM
;
11892 record_buf
[1] = ARM_LR_REGNUM
;
11893 thumb_insn_r
->reg_rec_count
= 2;
11894 /* We need to save SPSR value, which is not yet done. */
11895 printf_unfiltered (_("Process record does not support instruction "
11896 "0x%0x at address %s.\n"),
11897 thumb_insn_r
->arm_insn
,
11898 paddress (thumb_insn_r
->gdbarch
,
11899 thumb_insn_r
->this_addr
));
11902 else if ((0 == opcode
) || (1 == opcode
))
11904 /* ADD(5), ADD(6). */
11905 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11906 record_buf
[0] = reg_src1
;
11907 thumb_insn_r
->reg_rec_count
= 1;
11909 else if (2 == opcode
)
11911 /* ADD(7), SUB(4). */
11912 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11913 record_buf
[0] = ARM_SP_REGNUM
;
11914 thumb_insn_r
->reg_rec_count
= 1;
11917 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11918 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11924 /* Handling opcode 110 insns. */
11927 thumb_record_ldm_stm_swi (insn_decode_record
*thumb_insn_r
)
11929 struct gdbarch_tdep
*tdep
= gdbarch_tdep (thumb_insn_r
->gdbarch
);
11930 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11932 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
11933 uint32_t reg_src1
= 0;
11934 uint32_t opcode1
= 0, opcode2
= 0, register_bits
= 0, register_count
= 0;
11935 uint32_t index
= 0, start_address
= 0;
11936 uint32_t record_buf
[24], record_buf_mem
[48];
11938 ULONGEST u_regval
= 0;
11940 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
11941 opcode2
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11947 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11949 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11950 while (register_bits
)
11952 if (register_bits
& 0x00000001)
11953 record_buf
[index
++] = register_count
;
11954 register_bits
= register_bits
>> 1;
11957 record_buf
[index
++] = reg_src1
;
11958 thumb_insn_r
->reg_rec_count
= index
;
11960 else if (0 == opcode2
)
11962 /* It handles both STMIA. */
11963 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11965 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11966 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11967 while (register_bits
)
11969 if (register_bits
& 0x00000001)
11971 register_bits
= register_bits
>> 1;
11973 start_address
= u_regval
;
11974 thumb_insn_r
->mem_rec_count
= register_count
;
11975 while (register_count
)
11977 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11978 record_buf_mem
[(register_count
* 2) - 2] = 4;
11979 start_address
= start_address
+ 4;
11983 else if (0x1F == opcode1
)
11985 /* Handle arm syscall insn. */
11986 if (tdep
->arm_syscall_record
!= NULL
)
11988 regcache_raw_read_unsigned (reg_cache
, 7, &u_regval
);
11989 ret
= tdep
->arm_syscall_record (reg_cache
, u_regval
);
11993 printf_unfiltered (_("no syscall record support\n"));
11998 /* B (1), conditional branch is automatically taken care in process_record,
11999 as PC is saved there. */
12001 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12002 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12008 /* Handling opcode 111 insns. */
12011 thumb_record_branch (insn_decode_record
*thumb_insn_r
)
12013 uint32_t record_buf
[8];
12014 uint32_t bits_h
= 0;
12016 bits_h
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12018 if (2 == bits_h
|| 3 == bits_h
)
12021 record_buf
[0] = ARM_LR_REGNUM
;
12022 thumb_insn_r
->reg_rec_count
= 1;
12024 else if (1 == bits_h
)
12027 record_buf
[0] = ARM_PS_REGNUM
;
12028 record_buf
[1] = ARM_LR_REGNUM
;
12029 thumb_insn_r
->reg_rec_count
= 2;
12032 /* B(2) is automatically taken care in process_record, as PC is
12035 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12040 /* Handler for thumb2 load/store multiple instructions. */
12043 thumb2_record_ld_st_multiple (insn_decode_record
*thumb2_insn_r
)
12045 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12047 uint32_t reg_rn
, op
;
12048 uint32_t register_bits
= 0, register_count
= 0;
12049 uint32_t index
= 0, start_address
= 0;
12050 uint32_t record_buf
[24], record_buf_mem
[48];
12052 ULONGEST u_regval
= 0;
12054 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12055 op
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12057 if (0 == op
|| 3 == op
)
12059 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12061 /* Handle RFE instruction. */
12062 record_buf
[0] = ARM_PS_REGNUM
;
12063 thumb2_insn_r
->reg_rec_count
= 1;
12067 /* Handle SRS instruction after reading banked SP. */
12068 return arm_record_unsupported_insn (thumb2_insn_r
);
12071 else if (1 == op
|| 2 == op
)
12073 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12075 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
12076 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12077 while (register_bits
)
12079 if (register_bits
& 0x00000001)
12080 record_buf
[index
++] = register_count
;
12083 register_bits
= register_bits
>> 1;
12085 record_buf
[index
++] = reg_rn
;
12086 record_buf
[index
++] = ARM_PS_REGNUM
;
12087 thumb2_insn_r
->reg_rec_count
= index
;
12091 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
12092 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12093 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12094 while (register_bits
)
12096 if (register_bits
& 0x00000001)
12099 register_bits
= register_bits
>> 1;
12104 /* Start address calculation for LDMDB/LDMEA. */
12105 start_address
= u_regval
;
12109 /* Start address calculation for LDMDB/LDMEA. */
12110 start_address
= u_regval
- register_count
* 4;
12113 thumb2_insn_r
->mem_rec_count
= register_count
;
12114 while (register_count
)
12116 record_buf_mem
[register_count
* 2 - 1] = start_address
;
12117 record_buf_mem
[register_count
* 2 - 2] = 4;
12118 start_address
= start_address
+ 4;
12121 record_buf
[0] = reg_rn
;
12122 record_buf
[1] = ARM_PS_REGNUM
;
12123 thumb2_insn_r
->reg_rec_count
= 2;
12127 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12129 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12131 return ARM_RECORD_SUCCESS
;
12134 /* Handler for thumb2 load/store (dual/exclusive) and table branch
12138 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record
*thumb2_insn_r
)
12140 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12142 uint32_t reg_rd
, reg_rn
, offset_imm
;
12143 uint32_t reg_dest1
, reg_dest2
;
12144 uint32_t address
, offset_addr
;
12145 uint32_t record_buf
[8], record_buf_mem
[8];
12146 uint32_t op1
, op2
, op3
;
12148 ULONGEST u_regval
[2];
12150 op1
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12151 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 21);
12152 op3
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12154 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12156 if(!(1 == op1
&& 1 == op2
&& (0 == op3
|| 1 == op3
)))
12158 reg_dest1
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12159 record_buf
[0] = reg_dest1
;
12160 record_buf
[1] = ARM_PS_REGNUM
;
12161 thumb2_insn_r
->reg_rec_count
= 2;
12164 if (3 == op2
|| (op1
& 2) || (1 == op1
&& 1 == op2
&& 7 == op3
))
12166 reg_dest2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12167 record_buf
[2] = reg_dest2
;
12168 thumb2_insn_r
->reg_rec_count
= 3;
12173 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12174 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12176 if (0 == op1
&& 0 == op2
)
12178 /* Handle STREX. */
12179 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12180 address
= u_regval
[0] + (offset_imm
* 4);
12181 record_buf_mem
[0] = 4;
12182 record_buf_mem
[1] = address
;
12183 thumb2_insn_r
->mem_rec_count
= 1;
12184 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12185 record_buf
[0] = reg_rd
;
12186 thumb2_insn_r
->reg_rec_count
= 1;
12188 else if (1 == op1
&& 0 == op2
)
12190 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12191 record_buf
[0] = reg_rd
;
12192 thumb2_insn_r
->reg_rec_count
= 1;
12193 address
= u_regval
[0];
12194 record_buf_mem
[1] = address
;
12198 /* Handle STREXB. */
12199 record_buf_mem
[0] = 1;
12200 thumb2_insn_r
->mem_rec_count
= 1;
12204 /* Handle STREXH. */
12205 record_buf_mem
[0] = 2 ;
12206 thumb2_insn_r
->mem_rec_count
= 1;
12210 /* Handle STREXD. */
12211 address
= u_regval
[0];
12212 record_buf_mem
[0] = 4;
12213 record_buf_mem
[2] = 4;
12214 record_buf_mem
[3] = address
+ 4;
12215 thumb2_insn_r
->mem_rec_count
= 2;
12220 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12222 if (bit (thumb2_insn_r
->arm_insn
, 24))
12224 if (bit (thumb2_insn_r
->arm_insn
, 23))
12225 offset_addr
= u_regval
[0] + (offset_imm
* 4);
12227 offset_addr
= u_regval
[0] - (offset_imm
* 4);
12229 address
= offset_addr
;
12232 address
= u_regval
[0];
12234 record_buf_mem
[0] = 4;
12235 record_buf_mem
[1] = address
;
12236 record_buf_mem
[2] = 4;
12237 record_buf_mem
[3] = address
+ 4;
12238 thumb2_insn_r
->mem_rec_count
= 2;
12239 record_buf
[0] = reg_rn
;
12240 thumb2_insn_r
->reg_rec_count
= 1;
12244 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12246 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12248 return ARM_RECORD_SUCCESS
;
12251 /* Handler for thumb2 data processing (shift register and modified immediate)
12255 thumb2_record_data_proc_sreg_mimm (insn_decode_record
*thumb2_insn_r
)
12257 uint32_t reg_rd
, op
;
12258 uint32_t record_buf
[8];
12260 op
= bits (thumb2_insn_r
->arm_insn
, 21, 24);
12261 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12263 if ((0 == op
|| 4 == op
|| 8 == op
|| 13 == op
) && 15 == reg_rd
)
12265 record_buf
[0] = ARM_PS_REGNUM
;
12266 thumb2_insn_r
->reg_rec_count
= 1;
12270 record_buf
[0] = reg_rd
;
12271 record_buf
[1] = ARM_PS_REGNUM
;
12272 thumb2_insn_r
->reg_rec_count
= 2;
12275 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12277 return ARM_RECORD_SUCCESS
;
12280 /* Generic handler for thumb2 instructions which effect destination and PS
12284 thumb2_record_ps_dest_generic (insn_decode_record
*thumb2_insn_r
)
12287 uint32_t record_buf
[8];
12289 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12291 record_buf
[0] = reg_rd
;
12292 record_buf
[1] = ARM_PS_REGNUM
;
12293 thumb2_insn_r
->reg_rec_count
= 2;
12295 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12297 return ARM_RECORD_SUCCESS
;
12300 /* Handler for thumb2 branch and miscellaneous control instructions. */
12303 thumb2_record_branch_misc_cntrl (insn_decode_record
*thumb2_insn_r
)
12305 uint32_t op
, op1
, op2
;
12306 uint32_t record_buf
[8];
12308 op
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12309 op1
= bits (thumb2_insn_r
->arm_insn
, 12, 14);
12310 op2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12312 /* Handle MSR insn. */
12313 if (!(op1
& 0x2) && 0x38 == op
)
12317 /* CPSR is going to be changed. */
12318 record_buf
[0] = ARM_PS_REGNUM
;
12319 thumb2_insn_r
->reg_rec_count
= 1;
12323 arm_record_unsupported_insn(thumb2_insn_r
);
12327 else if (4 == (op1
& 0x5) || 5 == (op1
& 0x5))
12330 record_buf
[0] = ARM_PS_REGNUM
;
12331 record_buf
[1] = ARM_LR_REGNUM
;
12332 thumb2_insn_r
->reg_rec_count
= 2;
12335 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12337 return ARM_RECORD_SUCCESS
;
12340 /* Handler for thumb2 store single data item instructions. */
12343 thumb2_record_str_single_data (insn_decode_record
*thumb2_insn_r
)
12345 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12347 uint32_t reg_rn
, reg_rm
, offset_imm
, shift_imm
;
12348 uint32_t address
, offset_addr
;
12349 uint32_t record_buf
[8], record_buf_mem
[8];
12352 ULONGEST u_regval
[2];
12354 op1
= bits (thumb2_insn_r
->arm_insn
, 21, 23);
12355 op2
= bits (thumb2_insn_r
->arm_insn
, 6, 11);
12356 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12357 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12359 if (bit (thumb2_insn_r
->arm_insn
, 23))
12362 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 11);
12363 offset_addr
= u_regval
[0] + offset_imm
;
12364 address
= offset_addr
;
12369 if ((0 == op1
|| 1 == op1
|| 2 == op1
) && !(op2
& 0x20))
12371 /* Handle STRB (register). */
12372 reg_rm
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12373 regcache_raw_read_unsigned (reg_cache
, reg_rm
, &u_regval
[1]);
12374 shift_imm
= bits (thumb2_insn_r
->arm_insn
, 4, 5);
12375 offset_addr
= u_regval
[1] << shift_imm
;
12376 address
= u_regval
[0] + offset_addr
;
12380 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12381 if (bit (thumb2_insn_r
->arm_insn
, 10))
12383 if (bit (thumb2_insn_r
->arm_insn
, 9))
12384 offset_addr
= u_regval
[0] + offset_imm
;
12386 offset_addr
= u_regval
[0] - offset_imm
;
12388 address
= offset_addr
;
12391 address
= u_regval
[0];
12397 /* Store byte instructions. */
12400 record_buf_mem
[0] = 1;
12402 /* Store half word instructions. */
12405 record_buf_mem
[0] = 2;
12407 /* Store word instructions. */
12410 record_buf_mem
[0] = 4;
12414 gdb_assert_not_reached ("no decoding pattern found");
12418 record_buf_mem
[1] = address
;
12419 thumb2_insn_r
->mem_rec_count
= 1;
12420 record_buf
[0] = reg_rn
;
12421 thumb2_insn_r
->reg_rec_count
= 1;
12423 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12425 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12427 return ARM_RECORD_SUCCESS
;
12430 /* Handler for thumb2 load memory hints instructions. */
12433 thumb2_record_ld_mem_hints (insn_decode_record
*thumb2_insn_r
)
12435 uint32_t record_buf
[8];
12436 uint32_t reg_rt
, reg_rn
;
12438 reg_rt
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12439 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12441 if (ARM_PC_REGNUM
!= reg_rt
)
12443 record_buf
[0] = reg_rt
;
12444 record_buf
[1] = reg_rn
;
12445 record_buf
[2] = ARM_PS_REGNUM
;
12446 thumb2_insn_r
->reg_rec_count
= 3;
12448 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12450 return ARM_RECORD_SUCCESS
;
12453 return ARM_RECORD_FAILURE
;
12456 /* Handler for thumb2 load word instructions. */
12459 thumb2_record_ld_word (insn_decode_record
*thumb2_insn_r
)
12461 uint32_t record_buf
[8];
12463 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12464 record_buf
[1] = ARM_PS_REGNUM
;
12465 thumb2_insn_r
->reg_rec_count
= 2;
12467 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12469 return ARM_RECORD_SUCCESS
;
12472 /* Handler for thumb2 long multiply, long multiply accumulate, and
12473 divide instructions. */
12476 thumb2_record_lmul_lmla_div (insn_decode_record
*thumb2_insn_r
)
12478 uint32_t opcode1
= 0, opcode2
= 0;
12479 uint32_t record_buf
[8];
12481 opcode1
= bits (thumb2_insn_r
->arm_insn
, 20, 22);
12482 opcode2
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12484 if (0 == opcode1
|| 2 == opcode1
|| (opcode1
>= 4 && opcode1
<= 6))
12486 /* Handle SMULL, UMULL, SMULAL. */
12487 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
12488 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12489 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12490 record_buf
[2] = ARM_PS_REGNUM
;
12491 thumb2_insn_r
->reg_rec_count
= 3;
12493 else if (1 == opcode1
|| 3 == opcode2
)
12495 /* Handle SDIV and UDIV. */
12496 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12497 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12498 record_buf
[2] = ARM_PS_REGNUM
;
12499 thumb2_insn_r
->reg_rec_count
= 3;
12502 return ARM_RECORD_FAILURE
;
12504 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12506 return ARM_RECORD_SUCCESS
;
12509 /* Record handler for thumb32 coprocessor instructions. */
12512 thumb2_record_coproc_insn (insn_decode_record
*thumb2_insn_r
)
12514 if (bit (thumb2_insn_r
->arm_insn
, 25))
12515 return arm_record_coproc_data_proc (thumb2_insn_r
);
12517 return arm_record_asimd_vfp_coproc (thumb2_insn_r
);
12520 /* Record handler for advance SIMD structure load/store instructions. */
12523 thumb2_record_asimd_struct_ld_st (insn_decode_record
*thumb2_insn_r
)
12525 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12526 uint32_t l_bit
, a_bit
, b_bits
;
12527 uint32_t record_buf
[128], record_buf_mem
[128];
12528 uint32_t reg_rn
, reg_vd
, address
, f_elem
;
12529 uint32_t index_r
= 0, index_e
= 0, bf_regs
= 0, index_m
= 0, loop_t
= 0;
12532 l_bit
= bit (thumb2_insn_r
->arm_insn
, 21);
12533 a_bit
= bit (thumb2_insn_r
->arm_insn
, 23);
12534 b_bits
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12535 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12536 reg_vd
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12537 reg_vd
= (bit (thumb2_insn_r
->arm_insn
, 22) << 4) | reg_vd
;
12538 f_ebytes
= (1 << bits (thumb2_insn_r
->arm_insn
, 6, 7));
12539 f_elem
= 8 / f_ebytes
;
12543 ULONGEST u_regval
= 0;
12544 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12545 address
= u_regval
;
12550 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12552 if (b_bits
== 0x07)
12554 else if (b_bits
== 0x0a)
12556 else if (b_bits
== 0x06)
12558 else if (b_bits
== 0x02)
12563 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12565 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12567 record_buf_mem
[index_m
++] = f_ebytes
;
12568 record_buf_mem
[index_m
++] = address
;
12569 address
= address
+ f_ebytes
;
12570 thumb2_insn_r
->mem_rec_count
+= 1;
12575 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12577 if (b_bits
== 0x09 || b_bits
== 0x08)
12579 else if (b_bits
== 0x03)
12584 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12585 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12587 for (loop_t
= 0; loop_t
< 2; loop_t
++)
12589 record_buf_mem
[index_m
++] = f_ebytes
;
12590 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12591 thumb2_insn_r
->mem_rec_count
+= 1;
12593 address
= address
+ (2 * f_ebytes
);
12597 else if ((b_bits
& 0x0e) == 0x04)
12599 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12601 for (loop_t
= 0; loop_t
< 3; loop_t
++)
12603 record_buf_mem
[index_m
++] = f_ebytes
;
12604 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12605 thumb2_insn_r
->mem_rec_count
+= 1;
12607 address
= address
+ (3 * f_ebytes
);
12611 else if (!(b_bits
& 0x0e))
12613 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12615 for (loop_t
= 0; loop_t
< 4; loop_t
++)
12617 record_buf_mem
[index_m
++] = f_ebytes
;
12618 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12619 thumb2_insn_r
->mem_rec_count
+= 1;
12621 address
= address
+ (4 * f_ebytes
);
12627 uint8_t bft_size
= bits (thumb2_insn_r
->arm_insn
, 10, 11);
12629 if (bft_size
== 0x00)
12631 else if (bft_size
== 0x01)
12633 else if (bft_size
== 0x02)
12639 if (!(b_bits
& 0x0b) || b_bits
== 0x08)
12640 thumb2_insn_r
->mem_rec_count
= 1;
12642 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09)
12643 thumb2_insn_r
->mem_rec_count
= 2;
12645 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a)
12646 thumb2_insn_r
->mem_rec_count
= 3;
12648 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b)
12649 thumb2_insn_r
->mem_rec_count
= 4;
12651 for (index_m
= 0; index_m
< thumb2_insn_r
->mem_rec_count
; index_m
++)
12653 record_buf_mem
[index_m
] = f_ebytes
;
12654 record_buf_mem
[index_m
] = address
+ (index_m
* f_ebytes
);
12663 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12664 thumb2_insn_r
->reg_rec_count
= 1;
12666 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12667 thumb2_insn_r
->reg_rec_count
= 2;
12669 else if ((b_bits
& 0x0e) == 0x04)
12670 thumb2_insn_r
->reg_rec_count
= 3;
12672 else if (!(b_bits
& 0x0e))
12673 thumb2_insn_r
->reg_rec_count
= 4;
12678 if (!(b_bits
& 0x0b) || b_bits
== 0x08 || b_bits
== 0x0c)
12679 thumb2_insn_r
->reg_rec_count
= 1;
12681 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09 || b_bits
== 0x0d)
12682 thumb2_insn_r
->reg_rec_count
= 2;
12684 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a || b_bits
== 0x0e)
12685 thumb2_insn_r
->reg_rec_count
= 3;
12687 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b || b_bits
== 0x0f)
12688 thumb2_insn_r
->reg_rec_count
= 4;
12690 for (index_r
= 0; index_r
< thumb2_insn_r
->reg_rec_count
; index_r
++)
12691 record_buf
[index_r
] = reg_vd
+ ARM_D0_REGNUM
+ index_r
;
12695 if (bits (thumb2_insn_r
->arm_insn
, 0, 3) != 15)
12697 record_buf
[index_r
] = reg_rn
;
12698 thumb2_insn_r
->reg_rec_count
+= 1;
12701 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12703 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12708 /* Decodes thumb2 instruction type and invokes its record handler. */
12710 static unsigned int
12711 thumb2_record_decode_insn_handler (insn_decode_record
*thumb2_insn_r
)
12713 uint32_t op
, op1
, op2
;
12715 op
= bit (thumb2_insn_r
->arm_insn
, 15);
12716 op1
= bits (thumb2_insn_r
->arm_insn
, 27, 28);
12717 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12721 if (!(op2
& 0x64 ))
12723 /* Load/store multiple instruction. */
12724 return thumb2_record_ld_st_multiple (thumb2_insn_r
);
12726 else if (!((op2
& 0x64) ^ 0x04))
12728 /* Load/store (dual/exclusive) and table branch instruction. */
12729 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r
);
12731 else if (!((op2
& 0x20) ^ 0x20))
12733 /* Data-processing (shifted register). */
12734 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12736 else if (op2
& 0x40)
12738 /* Co-processor instructions. */
12739 return thumb2_record_coproc_insn (thumb2_insn_r
);
12742 else if (op1
== 0x02)
12746 /* Branches and miscellaneous control instructions. */
12747 return thumb2_record_branch_misc_cntrl (thumb2_insn_r
);
12749 else if (op2
& 0x20)
12751 /* Data-processing (plain binary immediate) instruction. */
12752 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12756 /* Data-processing (modified immediate). */
12757 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12760 else if (op1
== 0x03)
12762 if (!(op2
& 0x71 ))
12764 /* Store single data item. */
12765 return thumb2_record_str_single_data (thumb2_insn_r
);
12767 else if (!((op2
& 0x71) ^ 0x10))
12769 /* Advanced SIMD or structure load/store instructions. */
12770 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r
);
12772 else if (!((op2
& 0x67) ^ 0x01))
12774 /* Load byte, memory hints instruction. */
12775 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
12777 else if (!((op2
& 0x67) ^ 0x03))
12779 /* Load halfword, memory hints instruction. */
12780 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
12782 else if (!((op2
& 0x67) ^ 0x05))
12784 /* Load word instruction. */
12785 return thumb2_record_ld_word (thumb2_insn_r
);
12787 else if (!((op2
& 0x70) ^ 0x20))
12789 /* Data-processing (register) instruction. */
12790 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12792 else if (!((op2
& 0x78) ^ 0x30))
12794 /* Multiply, multiply accumulate, abs diff instruction. */
12795 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12797 else if (!((op2
& 0x78) ^ 0x38))
12799 /* Long multiply, long multiply accumulate, and divide. */
12800 return thumb2_record_lmul_lmla_div (thumb2_insn_r
);
12802 else if (op2
& 0x40)
12804 /* Co-processor instructions. */
12805 return thumb2_record_coproc_insn (thumb2_insn_r
);
12812 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12813 and positive val on fauilure. */
12816 extract_arm_insn (insn_decode_record
*insn_record
, uint32_t insn_size
)
12818 gdb_byte buf
[insn_size
];
12820 memset (&buf
[0], 0, insn_size
);
12822 if (target_read_memory (insn_record
->this_addr
, &buf
[0], insn_size
))
12824 insn_record
->arm_insn
= (uint32_t) extract_unsigned_integer (&buf
[0],
12826 gdbarch_byte_order_for_code (insn_record
->gdbarch
));
12830 typedef int (*sti_arm_hdl_fp_t
) (insn_decode_record
*);
12832 /* Decode arm/thumb insn depending on condition cods and opcodes; and
12836 decode_insn (insn_decode_record
*arm_record
, record_type_t record_type
,
12837 uint32_t insn_size
)
12840 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm
12842 static const sti_arm_hdl_fp_t arm_handle_insn
[8] =
12844 arm_record_data_proc_misc_ld_str
, /* 000. */
12845 arm_record_data_proc_imm
, /* 001. */
12846 arm_record_ld_st_imm_offset
, /* 010. */
12847 arm_record_ld_st_reg_offset
, /* 011. */
12848 arm_record_ld_st_multiple
, /* 100. */
12849 arm_record_b_bl
, /* 101. */
12850 arm_record_asimd_vfp_coproc
, /* 110. */
12851 arm_record_coproc_data_proc
/* 111. */
12854 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb
12856 static const sti_arm_hdl_fp_t thumb_handle_insn
[8] =
12858 thumb_record_shift_add_sub
, /* 000. */
12859 thumb_record_add_sub_cmp_mov
, /* 001. */
12860 thumb_record_ld_st_reg_offset
, /* 010. */
12861 thumb_record_ld_st_imm_offset
, /* 011. */
12862 thumb_record_ld_st_stack
, /* 100. */
12863 thumb_record_misc
, /* 101. */
12864 thumb_record_ldm_stm_swi
, /* 110. */
12865 thumb_record_branch
/* 111. */
12868 uint32_t ret
= 0; /* return value: negative:failure 0:success. */
12869 uint32_t insn_id
= 0;
12871 if (extract_arm_insn (arm_record
, insn_size
))
12875 printf_unfiltered (_("Process record: error reading memory at "
12876 "addr %s len = %d.\n"),
12877 paddress (arm_record
->gdbarch
,
12878 arm_record
->this_addr
), insn_size
);
12882 else if (ARM_RECORD
== record_type
)
12884 arm_record
->cond
= bits (arm_record
->arm_insn
, 28, 31);
12885 insn_id
= bits (arm_record
->arm_insn
, 25, 27);
12887 if (arm_record
->cond
== 0xf)
12888 ret
= arm_record_extension_space (arm_record
);
12891 /* If this insn has fallen into extension space
12892 then we need not decode it anymore. */
12893 ret
= arm_handle_insn
[insn_id
] (arm_record
);
12895 if (ret
!= ARM_RECORD_SUCCESS
)
12897 arm_record_unsupported_insn (arm_record
);
12901 else if (THUMB_RECORD
== record_type
)
12903 /* As thumb does not have condition codes, we set negative. */
12904 arm_record
->cond
= -1;
12905 insn_id
= bits (arm_record
->arm_insn
, 13, 15);
12906 ret
= thumb_handle_insn
[insn_id
] (arm_record
);
12907 if (ret
!= ARM_RECORD_SUCCESS
)
12909 arm_record_unsupported_insn (arm_record
);
12913 else if (THUMB2_RECORD
== record_type
)
12915 /* As thumb does not have condition codes, we set negative. */
12916 arm_record
->cond
= -1;
12918 /* Swap first half of 32bit thumb instruction with second half. */
12919 arm_record
->arm_insn
12920 = (arm_record
->arm_insn
>> 16) | (arm_record
->arm_insn
<< 16);
12922 ret
= thumb2_record_decode_insn_handler (arm_record
);
12924 if (ret
!= ARM_RECORD_SUCCESS
)
12926 arm_record_unsupported_insn (arm_record
);
12932 /* Throw assertion. */
12933 gdb_assert_not_reached ("not a valid instruction, could not decode");
12940 /* Cleans up local record registers and memory allocations. */
12943 deallocate_reg_mem (insn_decode_record
*record
)
12945 xfree (record
->arm_regs
);
12946 xfree (record
->arm_mems
);
12950 /* Parse the current instruction and record the values of the registers and
12951 memory that will be changed in current instruction to record_arch_list".
12952 Return -1 if something is wrong. */
12955 arm_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
12956 CORE_ADDR insn_addr
)
12959 uint32_t no_of_rec
= 0;
12960 uint32_t ret
= 0; /* return value: -1:record failure ; 0:success */
12961 ULONGEST t_bit
= 0, insn_id
= 0;
12963 ULONGEST u_regval
= 0;
12965 insn_decode_record arm_record
;
12967 memset (&arm_record
, 0, sizeof (insn_decode_record
));
12968 arm_record
.regcache
= regcache
;
12969 arm_record
.this_addr
= insn_addr
;
12970 arm_record
.gdbarch
= gdbarch
;
12973 if (record_debug
> 1)
12975 fprintf_unfiltered (gdb_stdlog
, "Process record: arm_process_record "
12977 paddress (gdbarch
, arm_record
.this_addr
));
12980 if (extract_arm_insn (&arm_record
, 2))
12984 printf_unfiltered (_("Process record: error reading memory at "
12985 "addr %s len = %d.\n"),
12986 paddress (arm_record
.gdbarch
,
12987 arm_record
.this_addr
), 2);
12992 /* Check the insn, whether it is thumb or arm one. */
12994 t_bit
= arm_psr_thumb_bit (arm_record
.gdbarch
);
12995 regcache_raw_read_unsigned (arm_record
.regcache
, ARM_PS_REGNUM
, &u_regval
);
12998 if (!(u_regval
& t_bit
))
13000 /* We are decoding arm insn. */
13001 ret
= decode_insn (&arm_record
, ARM_RECORD
, ARM_INSN_SIZE_BYTES
);
13005 insn_id
= bits (arm_record
.arm_insn
, 11, 15);
13006 /* is it thumb2 insn? */
13007 if ((0x1D == insn_id
) || (0x1E == insn_id
) || (0x1F == insn_id
))
13009 ret
= decode_insn (&arm_record
, THUMB2_RECORD
,
13010 THUMB2_INSN_SIZE_BYTES
);
13014 /* We are decoding thumb insn. */
13015 ret
= decode_insn (&arm_record
, THUMB_RECORD
, THUMB_INSN_SIZE_BYTES
);
13021 /* Record registers. */
13022 record_full_arch_list_add_reg (arm_record
.regcache
, ARM_PC_REGNUM
);
13023 if (arm_record
.arm_regs
)
13025 for (no_of_rec
= 0; no_of_rec
< arm_record
.reg_rec_count
; no_of_rec
++)
13027 if (record_full_arch_list_add_reg
13028 (arm_record
.regcache
, arm_record
.arm_regs
[no_of_rec
]))
13032 /* Record memories. */
13033 if (arm_record
.arm_mems
)
13035 for (no_of_rec
= 0; no_of_rec
< arm_record
.mem_rec_count
; no_of_rec
++)
13037 if (record_full_arch_list_add_mem
13038 ((CORE_ADDR
)arm_record
.arm_mems
[no_of_rec
].addr
,
13039 arm_record
.arm_mems
[no_of_rec
].len
))
13044 if (record_full_arch_list_add_end ())
13049 deallocate_reg_mem (&arm_record
);