1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 #include <ctype.h> /* XXX for isupper () */
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register flavors. */
35 #include "arch-utils.h"
36 #include "solib-svr4.h"
41 #include "coff/internal.h"
44 /* Each OS has a different mechanism for accessing the various
45 registers stored in the sigcontext structure.
47 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
48 function pointer) which may be used to determine the addresses
49 of the various saved registers in the sigcontext structure.
51 For the ARM target, there are three parameters to this function.
52 The first is the pc value of the frame under consideration, the
53 second the stack pointer of this frame, and the last is the
54 register number to fetch.
56 If the tm.h file does not define this macro, then it's assumed that
57 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
60 When it comes time to multi-arching this code, see the identically
61 named machinery in ia64-tdep.c for an example of how it could be
62 done. It should not be necessary to modify the code below where
63 this macro is used. */
65 #ifdef SIGCONTEXT_REGISTER_ADDRESS
66 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
67 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
70 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
71 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
74 /* Macros for setting and testing a bit in a minimal symbol that marks
75 it as Thumb function. The MSB of the minimal symbol's "info" field
76 is used for this purpose. This field is already being used to store
77 the symbol size, so the assumption is that the symbol size cannot
80 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
81 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol.
82 MSYMBOL_SIZE Returns the size of the minimal symbol,
83 i.e. the "info" field with the "special" bit
86 #define MSYMBOL_SET_SPECIAL(msym) \
87 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
90 #define MSYMBOL_IS_SPECIAL(msym) \
91 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
93 #define MSYMBOL_SIZE(msym) \
94 ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
96 /* Number of different reg name sets (options). */
97 static int num_flavor_options
;
99 /* We have more registers than the disassembler as gdb can print the value
100 of special registers as well.
101 The general register names are overwritten by whatever is being used by
102 the disassembler at the moment. We also adjust the case of cpsr and fps. */
104 /* Initial value: Register names used in ARM's ISA documentation. */
105 static char * arm_register_name_strings
[] =
106 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
107 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
108 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
109 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
110 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
111 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
112 "fps", "cpsr" }; /* 24 25 */
113 static char **arm_register_names
= arm_register_name_strings
;
115 /* Valid register name flavors. */
116 static const char **valid_flavors
;
118 /* Disassembly flavor to use. Default to "std" register names. */
119 static const char *disassembly_flavor
;
120 /* Index to that option in the opcodes table. */
121 static int current_option
;
123 /* This is used to keep the bfd arch_info in sync with the disassembly
125 static void set_disassembly_flavor_sfunc(char *, int,
126 struct cmd_list_element
*);
127 static void set_disassembly_flavor (void);
129 static void convert_from_extended (void *ptr
, void *dbl
);
131 /* Define other aspects of the stack frame. We keep the offsets of
132 all saved registers, 'cause we need 'em a lot! We also keep the
133 current size of the stack frame, and the offset of the frame
134 pointer from the stack pointer (for frameless functions, and when
135 we're still in the prologue of a function with a frame). */
137 struct frame_extra_info
144 /* Addresses for calling Thumb functions have the bit 0 set.
145 Here are some macros to test, set, or clear bit 0 of addresses. */
146 #define IS_THUMB_ADDR(addr) ((addr) & 1)
147 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
148 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
151 arm_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*thisframe
)
153 return (chain
!= 0 && (FRAME_SAVED_PC (thisframe
) >= LOWEST_PC
));
156 /* Set to true if the 32-bit mode is in use. */
160 /* Flag set by arm_fix_call_dummy that tells whether the target
161 function is a Thumb function. This flag is checked by
162 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
163 its use in valops.c) to pass the function address as an additional
166 static int target_is_thumb
;
168 /* Flag set by arm_fix_call_dummy that tells whether the calling
169 function is a Thumb function. This flag is checked by
170 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
172 static int caller_is_thumb
;
174 /* Determine if the program counter specified in MEMADDR is in a Thumb
178 arm_pc_is_thumb (CORE_ADDR memaddr
)
180 struct minimal_symbol
*sym
;
182 /* If bit 0 of the address is set, assume this is a Thumb address. */
183 if (IS_THUMB_ADDR (memaddr
))
186 /* Thumb functions have a "special" bit set in minimal symbols. */
187 sym
= lookup_minimal_symbol_by_pc (memaddr
);
190 return (MSYMBOL_IS_SPECIAL (sym
));
198 /* Determine if the program counter specified in MEMADDR is in a call
199 dummy being called from a Thumb function. */
202 arm_pc_is_thumb_dummy (CORE_ADDR memaddr
)
204 CORE_ADDR sp
= read_sp ();
206 /* FIXME: Until we switch for the new call dummy macros, this heuristic
207 is the best we can do. We are trying to determine if the pc is on
208 the stack, which (hopefully) will only happen in a call dummy.
209 We hope the current stack pointer is not so far alway from the dummy
210 frame location (true if we have not pushed large data structures or
211 gone too many levels deep) and that our 1024 is not enough to consider
212 code regions as part of the stack (true for most practical purposes). */
213 if (PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 1024))
214 return caller_is_thumb
;
219 /* Remove useless bits from addresses in a running program. */
221 arm_addr_bits_remove (CORE_ADDR val
)
223 if (arm_pc_is_thumb (val
))
224 return (val
& (arm_apcs_32
? 0xfffffffe : 0x03fffffe));
226 return (val
& (arm_apcs_32
? 0xfffffffc : 0x03fffffc));
229 /* When reading symbols, we need to zap the low bit of the address,
230 which may be set to 1 for Thumb functions. */
232 arm_smash_text_address (CORE_ADDR val
)
237 /* Immediately after a function call, return the saved pc. Can't
238 always go through the frames for this because on some machines the
239 new frame is not set up until the new function executes some
243 arm_saved_pc_after_call (struct frame_info
*frame
)
245 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM
));
248 /* Determine whether the function invocation represented by FI has a
249 frame on the stack associated with it. If it does return zero,
250 otherwise return 1. */
253 arm_frameless_function_invocation (struct frame_info
*fi
)
255 CORE_ADDR func_start
, after_prologue
;
258 /* Sometimes we have functions that do a little setup (like saving the
259 vN registers with the stmdb instruction, but DO NOT set up a frame.
260 The symbol table will report this as a prologue. However, it is
261 important not to try to parse these partial frames as frames, or we
262 will get really confused.
264 So I will demand 3 instructions between the start & end of the
265 prologue before I call it a real prologue, i.e. at least
270 func_start
= (get_pc_function_start ((fi
)->pc
) + FUNCTION_START_OFFSET
);
271 after_prologue
= SKIP_PROLOGUE (func_start
);
273 /* There are some frameless functions whose first two instructions
274 follow the standard APCS form, in which case after_prologue will
275 be func_start + 8. */
277 frameless
= (after_prologue
< func_start
+ 12);
281 /* The address of the arguments in the frame. */
283 arm_frame_args_address (struct frame_info
*fi
)
288 /* The address of the local variables in the frame. */
290 arm_frame_locals_address (struct frame_info
*fi
)
295 /* The number of arguments being passed in the frame. */
297 arm_frame_num_args (struct frame_info
*fi
)
299 /* We have no way of knowing. */
303 /* A typical Thumb prologue looks like this:
307 Sometimes the latter instruction may be replaced by:
315 or, on tpcs, like this:
322 There is always one instruction of three classes:
327 When we have found at least one of each class we are done with the prolog.
328 Note that the "sub sp, #NN" before the push does not count.
332 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
334 CORE_ADDR current_pc
;
336 bit 0 - push { rlist }
337 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
338 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
342 for (current_pc
= pc
;
343 current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40;
346 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
348 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
350 findmask
|= 1; /* push found */
352 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
355 if ((findmask
& 1) == 0) /* before push ? */
358 findmask
|= 4; /* add/sub sp found */
360 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
362 findmask
|= 2; /* setting of r7 found */
364 else if (insn
== 0x466f) /* mov r7, sp */
366 findmask
|= 2; /* setting of r7 found */
368 else if (findmask
== (4+2+1))
370 /* We have found one of each type of prologue instruction */
374 /* Something in the prolog that we don't care about or some
375 instruction from outside the prolog scheduled here for
383 /* Advance the PC across any function entry prologue instructions to
384 reach some "real" code.
386 The APCS (ARM Procedure Call Standard) defines the following
390 [stmfd sp!, {a1,a2,a3,a4}]
391 stmfd sp!, {...,fp,ip,lr,pc}
392 [stfe f7, [sp, #-12]!]
393 [stfe f6, [sp, #-12]!]
394 [stfe f5, [sp, #-12]!]
395 [stfe f4, [sp, #-12]!]
396 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
399 arm_skip_prologue (CORE_ADDR pc
)
403 CORE_ADDR func_addr
, func_end
= 0;
405 struct symtab_and_line sal
;
407 /* If we're in a dummy frame, don't even try to skip the prologue. */
408 if (USE_GENERIC_DUMMY_FRAMES
409 && PC_IN_CALL_DUMMY (pc
, 0, 0))
412 /* See what the symbol table says. */
414 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
418 /* Found a function. */
419 sym
= lookup_symbol (func_name
, NULL
, VAR_NAMESPACE
, NULL
, NULL
);
420 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
422 /* Don't use this trick for assembly source files. */
423 sal
= find_pc_line (func_addr
, 0);
424 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
429 /* Check if this is Thumb code. */
430 if (arm_pc_is_thumb (pc
))
431 return thumb_skip_prologue (pc
, func_end
);
433 /* Can't find the prologue end in the symbol table, try it the hard way
434 by disassembling the instructions. */
436 /* Like arm_scan_prologue, stop no later than pc + 64. */
437 if (func_end
== 0 || func_end
> pc
+ 64)
440 for (skip_pc
= pc
; skip_pc
< func_end
; skip_pc
+= 4)
442 inst
= read_memory_integer (skip_pc
, 4);
444 /* "mov ip, sp" is no longer a required part of the prologue. */
445 if (inst
== 0xe1a0c00d) /* mov ip, sp */
448 /* Some prologues begin with "str lr, [sp, #-4]!". */
449 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
452 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
455 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
458 /* Any insns after this point may float into the code, if it makes
459 for better instruction scheduling, so we skip them only if we
460 find them, but still consider the function to be frame-ful. */
462 /* We may have either one sfmfd instruction here, or several stfe
463 insns, depending on the version of floating point code we
465 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
468 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
471 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
474 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
477 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
478 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
479 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
482 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
483 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
484 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
487 /* Un-recognized instruction; stop scanning. */
491 return skip_pc
; /* End of prologue */
495 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
496 This function decodes a Thumb function prologue to determine:
497 1) the size of the stack frame
498 2) which registers are saved on it
499 3) the offsets of saved regs
500 4) the offset from the stack pointer to the frame pointer
501 This information is stored in the "extra" fields of the frame_info.
503 A typical Thumb function prologue would create this stack frame
504 (offsets relative to FP)
505 old SP -> 24 stack parameters
508 R7 -> 0 local variables (16 bytes)
509 SP -> -12 additional stack space (12 bytes)
510 The frame size would thus be 36 bytes, and the frame offset would be
511 12 bytes. The frame register is R7.
513 The comments for thumb_skip_prolog() describe the algorithm we use
514 to detect the end of the prolog. */
518 thumb_scan_prologue (struct frame_info
*fi
)
520 CORE_ADDR prologue_start
;
521 CORE_ADDR prologue_end
;
522 CORE_ADDR current_pc
;
523 /* Which register has been copied to register n? */
526 bit 0 - push { rlist }
527 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
528 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
533 /* Don't try to scan dummy frames. */
534 if (USE_GENERIC_DUMMY_FRAMES
536 && PC_IN_CALL_DUMMY (fi
->pc
, 0, 0))
539 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
541 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
543 if (sal
.line
== 0) /* no line info, use current PC */
544 prologue_end
= fi
->pc
;
545 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
546 prologue_end
= sal
.end
; /* (probably means no prologue) */
549 /* We're in the boondocks: allow for
550 16 pushes, an add, and "mv fp,sp". */
551 prologue_end
= prologue_start
+ 40;
553 prologue_end
= min (prologue_end
, fi
->pc
);
555 /* Initialize the saved register map. When register H is copied to
556 register L, we will put H in saved_reg[L]. */
557 for (i
= 0; i
< 16; i
++)
560 /* Search the prologue looking for instructions that set up the
561 frame pointer, adjust the stack pointer, and save registers.
562 Do this until all basic prolog instructions are found. */
564 fi
->extra_info
->framesize
= 0;
565 for (current_pc
= prologue_start
;
566 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
573 insn
= read_memory_unsigned_integer (current_pc
, 2);
575 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
578 findmask
|= 1; /* push found */
579 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
580 whether to save LR (R14). */
581 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
583 /* Calculate offsets of saved R0-R7 and LR. */
584 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
585 if (mask
& (1 << regno
))
587 fi
->extra_info
->framesize
+= 4;
588 fi
->saved_regs
[saved_reg
[regno
]] =
589 -(fi
->extra_info
->framesize
);
590 /* Reset saved register map. */
591 saved_reg
[regno
] = regno
;
594 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
597 if ((findmask
& 1) == 0) /* before push? */
600 findmask
|= 4; /* add/sub sp found */
602 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
603 if (insn
& 0x80) /* is it signed? (==subtracting) */
605 fi
->extra_info
->frameoffset
+= offset
;
608 fi
->extra_info
->framesize
-= offset
;
610 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
612 findmask
|= 2; /* setting of r7 found */
613 fi
->extra_info
->framereg
= THUMB_FP_REGNUM
;
614 /* get scaled offset */
615 fi
->extra_info
->frameoffset
= (insn
& 0xff) << 2;
617 else if (insn
== 0x466f) /* mov r7, sp */
619 findmask
|= 2; /* setting of r7 found */
620 fi
->extra_info
->framereg
= THUMB_FP_REGNUM
;
621 fi
->extra_info
->frameoffset
= 0;
622 saved_reg
[THUMB_FP_REGNUM
] = ARM_SP_REGNUM
;
624 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
626 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
627 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
628 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
631 /* Something in the prolog that we don't care about or some
632 instruction from outside the prolog scheduled here for
638 /* Check if prologue for this frame's PC has already been scanned. If
639 it has, copy the relevant information about that prologue and
640 return non-zero. Otherwise do not copy anything and return zero.
642 The information saved in the cache includes:
643 * the frame register number;
644 * the size of the stack frame;
645 * the offsets of saved regs (relative to the old SP); and
646 * the offset from the stack pointer to the frame pointer
648 The cache contains only one entry, since this is adequate for the
649 typical sequence of prologue scan requests we get. When performing
650 a backtrace, GDB will usually ask to scan the same function twice
651 in a row (once to get the frame chain, and once to fill in the
652 extra frame information). */
654 static struct frame_info prologue_cache
;
657 check_prologue_cache (struct frame_info
*fi
)
661 if (fi
->pc
== prologue_cache
.pc
)
663 fi
->extra_info
->framereg
= prologue_cache
.extra_info
->framereg
;
664 fi
->extra_info
->framesize
= prologue_cache
.extra_info
->framesize
;
665 fi
->extra_info
->frameoffset
= prologue_cache
.extra_info
->frameoffset
;
666 for (i
= 0; i
< NUM_REGS
+ NUM_PSEUDO_REGS
; i
++)
667 fi
->saved_regs
[i
] = prologue_cache
.saved_regs
[i
];
675 /* Copy the prologue information from fi to the prologue cache. */
678 save_prologue_cache (struct frame_info
*fi
)
682 prologue_cache
.pc
= fi
->pc
;
683 prologue_cache
.extra_info
->framereg
= fi
->extra_info
->framereg
;
684 prologue_cache
.extra_info
->framesize
= fi
->extra_info
->framesize
;
685 prologue_cache
.extra_info
->frameoffset
= fi
->extra_info
->frameoffset
;
687 for (i
= 0; i
< NUM_REGS
+ NUM_PSEUDO_REGS
; i
++)
688 prologue_cache
.saved_regs
[i
] = fi
->saved_regs
[i
];
692 /* This function decodes an ARM function prologue to determine:
693 1) the size of the stack frame
694 2) which registers are saved on it
695 3) the offsets of saved regs
696 4) the offset from the stack pointer to the frame pointer
697 This information is stored in the "extra" fields of the frame_info.
699 There are two basic forms for the ARM prologue. The fixed argument
700 function call will look like:
703 stmfd sp!, {fp, ip, lr, pc}
707 Which would create this stack frame (offsets relative to FP):
708 IP -> 4 (caller's stack)
709 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
710 -4 LR (return address in caller)
711 -8 IP (copy of caller's SP)
713 SP -> -28 Local variables
715 The frame size would thus be 32 bytes, and the frame offset would be
716 28 bytes. The stmfd call can also save any of the vN registers it
717 plans to use, which increases the frame size accordingly.
719 Note: The stored PC is 8 off of the STMFD instruction that stored it
720 because the ARM Store instructions always store PC + 8 when you read
723 A variable argument function call will look like:
726 stmfd sp!, {a1, a2, a3, a4}
727 stmfd sp!, {fp, ip, lr, pc}
730 Which would create this stack frame (offsets relative to FP):
731 IP -> 20 (caller's stack)
736 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
737 -4 LR (return address in caller)
738 -8 IP (copy of caller's SP)
740 SP -> -28 Local variables
742 The frame size would thus be 48 bytes, and the frame offset would be
745 There is another potential complication, which is that the optimizer
746 will try to separate the store of fp in the "stmfd" instruction from
747 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
748 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
750 Also, note, the original version of the ARM toolchain claimed that there
753 instruction at the end of the prologue. I have never seen GCC produce
754 this, and the ARM docs don't mention it. We still test for it below in
760 arm_scan_prologue (struct frame_info
*fi
)
762 int regno
, sp_offset
, fp_offset
;
763 LONGEST return_value
;
764 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
766 /* Check if this function is already in the cache of frame information. */
767 if (check_prologue_cache (fi
))
770 /* Assume there is no frame until proven otherwise. */
771 fi
->extra_info
->framereg
= ARM_SP_REGNUM
;
772 fi
->extra_info
->framesize
= 0;
773 fi
->extra_info
->frameoffset
= 0;
775 /* Check for Thumb prologue. */
776 if (arm_pc_is_thumb (fi
->pc
))
778 thumb_scan_prologue (fi
);
779 save_prologue_cache (fi
);
783 /* Find the function prologue. If we can't find the function in
784 the symbol table, peek in the stack frame to find the PC. */
785 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
787 /* One way to find the end of the prologue (which works well
788 for unoptimized code) is to do the following:
790 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
793 prologue_end = fi->pc;
794 else if (sal.end < prologue_end)
795 prologue_end = sal.end;
797 This mechanism is very accurate so long as the optimizer
798 doesn't move any instructions from the function body into the
799 prologue. If this happens, sal.end will be the last
800 instruction in the first hunk of prologue code just before
801 the first instruction that the scheduler has moved from
802 the body to the prologue.
804 In order to make sure that we scan all of the prologue
805 instructions, we use a slightly less accurate mechanism which
806 may scan more than necessary. To help compensate for this
807 lack of accuracy, the prologue scanning loop below contains
808 several clauses which'll cause the loop to terminate early if
809 an implausible prologue instruction is encountered.
815 is a suitable endpoint since it accounts for the largest
816 possible prologue plus up to five instructions inserted by
819 if (prologue_end
> prologue_start
+ 64)
821 prologue_end
= prologue_start
+ 64; /* See above. */
826 /* Get address of the stmfd in the prologue of the callee;
827 the saved PC is the address of the stmfd + 8. */
828 if (!safe_read_memory_integer (fi
->frame
, 4, &return_value
))
832 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
833 prologue_end
= prologue_start
+ 64; /* See above. */
837 /* Now search the prologue looking for instructions that set up the
838 frame pointer, adjust the stack pointer, and save registers.
840 Be careful, however, and if it doesn't look like a prologue,
841 don't try to scan it. If, for instance, a frameless function
842 begins with stmfd sp!, then we will tell ourselves there is
843 a frame, which will confuse stack traceback, as well as "finish"
844 and other operations that rely on a knowledge of the stack
847 In the APCS, the prologue should start with "mov ip, sp" so
848 if we don't see this as the first insn, we will stop.
850 [Note: This doesn't seem to be true any longer, so it's now an
851 optional part of the prologue. - Kevin Buettner, 2001-11-20]
853 [Note further: The "mov ip,sp" only seems to be missing in
854 frameless functions at optimization level "-O2" or above,
855 in which case it is often (but not always) replaced by
856 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
858 sp_offset
= fp_offset
= 0;
860 for (current_pc
= prologue_start
;
861 current_pc
< prologue_end
;
864 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
866 if (insn
== 0xe1a0c00d) /* mov ip, sp */
870 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
872 /* Function is frameless: extra_info defaults OK? */
875 else if ((insn
& 0xffff0000) == 0xe92d0000)
876 /* stmfd sp!, {..., fp, ip, lr, pc}
878 stmfd sp!, {a1, a2, a3, a4} */
880 int mask
= insn
& 0xffff;
882 /* Calculate offsets of saved registers. */
883 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
884 if (mask
& (1 << regno
))
887 fi
->saved_regs
[regno
] = sp_offset
;
890 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
891 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
892 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
894 /* No need to add this to saved_regs -- it's just an arg reg. */
897 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
898 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
899 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
901 /* No need to add this to saved_regs -- it's just an arg reg. */
904 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
906 unsigned imm
= insn
& 0xff; /* immediate value */
907 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
908 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
910 fi
->extra_info
->framereg
= ARM_FP_REGNUM
;
912 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
914 unsigned imm
= insn
& 0xff; /* immediate value */
915 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
916 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
919 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
922 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
923 fi
->saved_regs
[regno
] = sp_offset
;
925 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
928 unsigned int fp_start_reg
, fp_bound_reg
;
930 if ((insn
& 0x800) == 0x800) /* N0 is set */
932 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
939 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
945 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
946 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
947 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
950 fi
->saved_regs
[fp_start_reg
++] = sp_offset
;
953 else if ((insn
& 0xf0000000) != 0xe0000000)
954 break; /* Condition not true, exit early */
955 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
956 break; /* Don't scan past a block load */
958 /* The optimizer might shove anything into the prologue,
959 so we just skip what we don't recognize. */
963 /* The frame size is just the negative of the offset (from the
964 original SP) of the last thing thing we pushed on the stack.
965 The frame offset is [new FP] - [new SP]. */
966 fi
->extra_info
->framesize
= -sp_offset
;
967 if (fi
->extra_info
->framereg
== ARM_FP_REGNUM
)
968 fi
->extra_info
->frameoffset
= fp_offset
- sp_offset
;
970 fi
->extra_info
->frameoffset
= 0;
972 save_prologue_cache (fi
);
975 /* Find REGNUM on the stack. Otherwise, it's in an active register.
976 One thing we might want to do here is to check REGNUM against the
977 clobber mask, and somehow flag it as invalid if it isn't saved on
978 the stack somewhere. This would provide a graceful failure mode
979 when trying to get the value of caller-saves registers for an inner
983 arm_find_callers_reg (struct frame_info
*fi
, int regnum
)
985 /* NOTE: cagney/2002-05-03: This function really shouldn't be
986 needed. Instead the (still being written) register unwind
987 function could be called directly. */
988 for (; fi
; fi
= fi
->next
)
990 if (USE_GENERIC_DUMMY_FRAMES
991 && PC_IN_CALL_DUMMY (fi
->pc
, 0, 0))
993 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
995 else if (fi
->saved_regs
[regnum
] != 0)
997 /* NOTE: cagney/2002-05-03: This would normally need to
998 handle ARM_SP_REGNUM as a special case as, according to
999 the frame.h comments, saved_regs[SP_REGNUM] contains the
1000 SP value not its address. It appears that the ARM isn't
1001 doing this though. */
1002 return read_memory_integer (fi
->saved_regs
[regnum
],
1003 REGISTER_RAW_SIZE (regnum
));
1006 return read_register (regnum
);
1008 /* Function: frame_chain Given a GDB frame, determine the address of
1009 the calling function's frame. This will be used to create a new
1010 GDB frame struct, and then INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC
1011 will be called for the new frame. For ARM, we save the frame size
1012 when we initialize the frame_info. */
1015 arm_frame_chain (struct frame_info
*fi
)
1017 CORE_ADDR caller_pc
;
1018 int framereg
= fi
->extra_info
->framereg
;
1020 if (USE_GENERIC_DUMMY_FRAMES
1021 && PC_IN_CALL_DUMMY (fi
->pc
, 0, 0))
1022 /* A generic call dummy's frame is the same as caller's. */
1025 if (fi
->pc
< LOWEST_PC
)
1028 /* If the caller is the startup code, we're at the end of the chain. */
1029 caller_pc
= FRAME_SAVED_PC (fi
);
1031 /* If the caller is Thumb and the caller is ARM, or vice versa,
1032 the frame register of the caller is different from ours.
1033 So we must scan the prologue of the caller to determine its
1034 frame register number. */
1035 /* XXX Fixme, we should try to do this without creating a temporary
1037 if (arm_pc_is_thumb (caller_pc
) != arm_pc_is_thumb (fi
->pc
))
1039 struct frame_info caller_fi
;
1040 struct cleanup
*old_chain
;
1042 /* Create a temporary frame suitable for scanning the caller's
1044 memset (&caller_fi
, 0, sizeof (caller_fi
));
1045 caller_fi
.extra_info
= (struct frame_extra_info
*)
1046 xcalloc (1, sizeof (struct frame_extra_info
));
1047 old_chain
= make_cleanup (xfree
, caller_fi
.extra_info
);
1048 caller_fi
.saved_regs
= (CORE_ADDR
*)
1049 xcalloc (1, SIZEOF_FRAME_SAVED_REGS
);
1050 make_cleanup (xfree
, caller_fi
.saved_regs
);
1052 /* Now, scan the prologue and obtain the frame register. */
1053 caller_fi
.pc
= caller_pc
;
1054 arm_scan_prologue (&caller_fi
);
1055 framereg
= caller_fi
.extra_info
->framereg
;
1057 /* Deallocate the storage associated with the temporary frame
1059 do_cleanups (old_chain
);
1062 /* If the caller used a frame register, return its value.
1063 Otherwise, return the caller's stack pointer. */
1064 if (framereg
== ARM_FP_REGNUM
|| framereg
== THUMB_FP_REGNUM
)
1065 return arm_find_callers_reg (fi
, framereg
);
1067 return fi
->frame
+ fi
->extra_info
->framesize
;
1070 /* This function actually figures out the frame address for a given pc
1071 and sp. This is tricky because we sometimes don't use an explicit
1072 frame pointer, and the previous stack pointer isn't necessarily
1073 recorded on the stack. The only reliable way to get this info is
1074 to examine the prologue. FROMLEAF is a little confusing, it means
1075 this is the next frame up the chain AFTER a frameless function. If
1076 this is true, then the frame value for this frame is still in the
1080 arm_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1085 if (fi
->saved_regs
== NULL
)
1086 frame_saved_regs_zalloc (fi
);
1088 fi
->extra_info
= (struct frame_extra_info
*)
1089 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1091 fi
->extra_info
->framesize
= 0;
1092 fi
->extra_info
->frameoffset
= 0;
1093 fi
->extra_info
->framereg
= 0;
1096 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1098 memset (fi
->saved_regs
, '\000', sizeof fi
->saved_regs
);
1100 /* Compute stack pointer for this frame. We use this value for both
1101 the sigtramp and call dummy cases. */
1104 else if (USE_GENERIC_DUMMY_FRAMES
1105 && PC_IN_CALL_DUMMY (fi
->next
->pc
, 0, 0))
1106 /* For generic dummy frames, pull the value direct from the frame.
1107 Having an unwind function to do this would be nice. */
1108 sp
= generic_read_register_dummy (fi
->next
->pc
, fi
->next
->frame
,
1111 sp
= (fi
->next
->frame
- fi
->next
->extra_info
->frameoffset
1112 + fi
->next
->extra_info
->framesize
);
1114 /* Determine whether or not we're in a sigtramp frame.
1115 Unfortunately, it isn't sufficient to test
1116 fi->signal_handler_caller because this value is sometimes set
1117 after invoking INIT_EXTRA_FRAME_INFO. So we test *both*
1118 fi->signal_handler_caller and PC_IN_SIGTRAMP to determine if we
1119 need to use the sigcontext addresses for the saved registers.
1121 Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare
1122 against the name of the function, the code below will have to be
1123 changed to first fetch the name of the function and then pass
1124 this name to PC_IN_SIGTRAMP. */
1126 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1127 && (fi
->signal_handler_caller
|| PC_IN_SIGTRAMP (fi
->pc
, (char *)0)))
1129 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1130 fi
->saved_regs
[reg
] = SIGCONTEXT_REGISTER_ADDRESS (sp
, fi
->pc
, reg
);
1132 /* FIXME: What about thumb mode? */
1133 fi
->extra_info
->framereg
= ARM_SP_REGNUM
;
1135 read_memory_integer (fi
->saved_regs
[fi
->extra_info
->framereg
],
1136 REGISTER_RAW_SIZE (fi
->extra_info
->framereg
));
1137 fi
->extra_info
->framesize
= 0;
1138 fi
->extra_info
->frameoffset
= 0;
1141 else if (PC_IN_CALL_DUMMY (fi
->pc
, sp
, fi
->frame
))
1144 CORE_ADDR callers_sp
;
1146 /* Set rp point at the high end of the saved registers. */
1147 rp
= fi
->frame
- REGISTER_SIZE
;
1149 /* Fill in addresses of saved registers. */
1150 fi
->saved_regs
[ARM_PS_REGNUM
] = rp
;
1151 rp
-= REGISTER_RAW_SIZE (ARM_PS_REGNUM
);
1152 for (reg
= ARM_PC_REGNUM
; reg
>= 0; reg
--)
1154 fi
->saved_regs
[reg
] = rp
;
1155 rp
-= REGISTER_RAW_SIZE (reg
);
1158 callers_sp
= read_memory_integer (fi
->saved_regs
[ARM_SP_REGNUM
],
1159 REGISTER_RAW_SIZE (ARM_SP_REGNUM
));
1160 fi
->extra_info
->framereg
= ARM_FP_REGNUM
;
1161 fi
->extra_info
->framesize
= callers_sp
- sp
;
1162 fi
->extra_info
->frameoffset
= fi
->frame
- sp
;
1166 arm_scan_prologue (fi
);
1169 /* This is the innermost frame? */
1170 fi
->frame
= read_register (fi
->extra_info
->framereg
);
1171 else if (USE_GENERIC_DUMMY_FRAMES
1172 && PC_IN_CALL_DUMMY (fi
->next
->pc
, 0, 0))
1173 /* Next inner most frame is a dummy, just grab its frame.
1174 Dummy frames always have the same FP as their caller. */
1175 fi
->frame
= fi
->next
->frame
;
1176 else if (fi
->extra_info
->framereg
== ARM_FP_REGNUM
1177 || fi
->extra_info
->framereg
== THUMB_FP_REGNUM
)
1179 /* not the innermost frame */
1180 /* If we have an FP, the callee saved it. */
1181 if (fi
->next
->saved_regs
[fi
->extra_info
->framereg
] != 0)
1183 read_memory_integer (fi
->next
1184 ->saved_regs
[fi
->extra_info
->framereg
], 4);
1186 /* If we were called by a frameless fn. then our frame is
1187 still in the frame pointer register on the board... */
1188 fi
->frame
= read_fp ();
1191 /* Calculate actual addresses of saved registers using offsets
1192 determined by arm_scan_prologue. */
1193 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1194 if (fi
->saved_regs
[reg
] != 0)
1195 fi
->saved_regs
[reg
] += (fi
->frame
+ fi
->extra_info
->framesize
1196 - fi
->extra_info
->frameoffset
);
1201 /* Find the caller of this frame. We do this by seeing if ARM_LR_REGNUM
1202 is saved in the stack anywhere, otherwise we get it from the
1205 The old definition of this function was a macro:
1206 #define FRAME_SAVED_PC(FRAME) \
1207 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1210 arm_frame_saved_pc (struct frame_info
*fi
)
1212 /* If a dummy frame, pull the PC out of the frame's register buffer. */
1213 if (USE_GENERIC_DUMMY_FRAMES
1214 && PC_IN_CALL_DUMMY (fi
->pc
, 0, 0))
1215 return generic_read_register_dummy (fi
->pc
, fi
->frame
, ARM_PC_REGNUM
);
1217 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
- fi
->extra_info
->frameoffset
,
1220 return read_memory_integer (fi
->saved_regs
[ARM_PC_REGNUM
],
1221 REGISTER_RAW_SIZE (ARM_PC_REGNUM
));
1225 CORE_ADDR pc
= arm_find_callers_reg (fi
, ARM_LR_REGNUM
);
1226 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1230 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1231 Examine the Program Status Register to decide which state we're in. */
1236 if (read_register (ARM_PS_REGNUM
) & 0x20) /* Bit 5 is Thumb state bit */
1237 return read_register (THUMB_FP_REGNUM
); /* R7 if Thumb */
1239 return read_register (ARM_FP_REGNUM
); /* R11 if ARM */
1242 /* Store into a struct frame_saved_regs the addresses of the saved
1243 registers of frame described by FRAME_INFO. This includes special
1244 registers such as PC and FP saved in special ways in the stack
1245 frame. SP is even more special: the address we return for it IS
1246 the sp for the next frame. */
1249 arm_frame_init_saved_regs (struct frame_info
*fip
)
1252 if (fip
->saved_regs
)
1255 arm_init_extra_frame_info (0, fip
);
1258 /* Set the return address for a generic dummy frame. ARM uses the
1262 arm_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
1264 write_register (ARM_LR_REGNUM
, CALL_DUMMY_ADDRESS ());
1268 /* Push an empty stack frame, to record the current PC, etc. */
1271 arm_push_dummy_frame (void)
1273 CORE_ADDR old_sp
= read_register (ARM_SP_REGNUM
);
1274 CORE_ADDR sp
= old_sp
;
1275 CORE_ADDR fp
, prologue_start
;
1278 /* Push the two dummy prologue instructions in reverse order,
1279 so that they'll be in the correct low-to-high order in memory. */
1280 /* sub fp, ip, #4 */
1281 sp
= push_word (sp
, 0xe24cb004);
1282 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1283 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
1285 /* Push a pointer to the dummy prologue + 12, because when stm
1286 instruction stores the PC, it stores the address of the stm
1287 instruction itself plus 12. */
1288 fp
= sp
= push_word (sp
, prologue_start
+ 12);
1290 /* Push the processor status. */
1291 sp
= push_word (sp
, read_register (ARM_PS_REGNUM
));
1293 /* Push all 16 registers starting with r15. */
1294 for (regnum
= ARM_PC_REGNUM
; regnum
>= 0; regnum
--)
1295 sp
= push_word (sp
, read_register (regnum
));
1297 /* Update fp (for both Thumb and ARM) and sp. */
1298 write_register (ARM_FP_REGNUM
, fp
);
1299 write_register (THUMB_FP_REGNUM
, fp
);
1300 write_register (ARM_SP_REGNUM
, sp
);
1303 /* CALL_DUMMY_WORDS:
1304 This sequence of words is the instructions
1310 Note this is 12 bytes. */
1312 static LONGEST arm_call_dummy_words
[] =
1314 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
1317 /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy
1318 breakpoint to the proper address in the call dummy, so that
1319 `finish' after a stop in a call dummy works.
1321 FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an
1322 optimal solution, but the call to arm_fix_call_dummy is immediately
1323 followed by a call to run_stack_dummy, which is the only function
1324 where call_dummy_breakpoint_offset is actually used. */
1328 arm_set_call_dummy_breakpoint_offset (void)
1330 if (caller_is_thumb
)
1331 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch
, 4);
1333 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch
, 8);
1336 /* Fix up the call dummy, based on whether the processor is currently
1337 in Thumb or ARM mode, and whether the target function is Thumb or
1338 ARM. There are three different situations requiring three
1341 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1342 been copied into the dummy parameter to this function.
1343 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1344 "mov pc,r4" instruction patched to be a "bx r4" instead.
1345 * Thumb calling anything: uses the Thumb dummy defined below, which
1346 works for calling both ARM and Thumb functions.
1348 All three call dummies expect to receive the target function
1349 address in R4, with the low bit set if it's a Thumb function. */
1352 arm_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
1353 struct value
**args
, struct type
*type
, int gcc_p
)
1355 static short thumb_dummy
[4] =
1357 0xf000, 0xf801, /* bl label */
1358 0xdf18, /* swi 24 */
1359 0x4720, /* label: bx r4 */
1361 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
1363 /* Set flag indicating whether the current PC is in a Thumb function. */
1364 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
1365 arm_set_call_dummy_breakpoint_offset ();
1367 /* If the target function is Thumb, set the low bit of the function
1368 address. And if the CPU is currently in ARM mode, patch the
1369 second instruction of call dummy to use a BX instruction to
1370 switch to Thumb mode. */
1371 target_is_thumb
= arm_pc_is_thumb (fun
);
1372 if (target_is_thumb
)
1375 if (!caller_is_thumb
)
1376 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
1379 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1380 instead of the ARM one that's already been copied. This will
1381 work for both Thumb and ARM target functions. */
1382 if (caller_is_thumb
)
1386 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
1388 for (i
= 0; i
< len
; i
++)
1390 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1391 p
+= sizeof (thumb_dummy
[0]);
1395 /* Put the target address in r4; the call dummy will copy this to
1397 write_register (4, fun
);
1402 This function does not support passing parameters using the FPA
1403 variant of the APCS. It passes any floating point arguments in the
1404 general registers and/or on the stack. */
1407 arm_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
1408 int struct_return
, CORE_ADDR struct_addr
)
1411 int argnum
, argreg
, nstack_size
;
1413 /* Walk through the list of args and determine how large a temporary
1414 stack is required. Need to take care here as structs may be
1415 passed on the stack, and we have to to push them. */
1416 nstack_size
= -4 * REGISTER_SIZE
; /* Some arguments go into A1-A4. */
1417 if (struct_return
) /* The struct address goes in A1. */
1418 nstack_size
+= REGISTER_SIZE
;
1420 /* Walk through the arguments and add their size to nstack_size. */
1421 for (argnum
= 0; argnum
< nargs
; argnum
++)
1424 struct type
*arg_type
;
1426 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1427 len
= TYPE_LENGTH (arg_type
);
1432 /* Allocate room on the stack, and initialize our stack frame
1435 if (nstack_size
> 0)
1441 /* Initialize the integer argument register pointer. */
1442 argreg
= ARM_A1_REGNUM
;
1444 /* The struct_return pointer occupies the first parameter passing
1447 write_register (argreg
++, struct_addr
);
1449 /* Process arguments from left to right. Store as many as allowed
1450 in the parameter passing registers (A1-A4), and save the rest on
1451 the temporary stack. */
1452 for (argnum
= 0; argnum
< nargs
; argnum
++)
1457 enum type_code typecode
;
1458 struct type
*arg_type
, *target_type
;
1460 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1461 target_type
= TYPE_TARGET_TYPE (arg_type
);
1462 len
= TYPE_LENGTH (arg_type
);
1463 typecode
= TYPE_CODE (arg_type
);
1464 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
1467 /* I don't know why this code was disable. The only logical use
1468 for a function pointer is to call that function, so setting
1469 the mode bit is perfectly fine. FN */
1470 /* If the argument is a pointer to a function, and it is a Thumb
1471 function, set the low bit of the pointer. */
1472 if (TYPE_CODE_PTR
== typecode
1473 && NULL
!= target_type
1474 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1476 CORE_ADDR regval
= extract_address (val
, len
);
1477 if (arm_pc_is_thumb (regval
))
1478 store_address (val
, len
, MAKE_THUMB_ADDR (regval
));
1481 /* Copy the argument to general registers or the stack in
1482 register-sized pieces. Large arguments are split between
1483 registers and stack. */
1486 int partial_len
= len
< REGISTER_SIZE
? len
: REGISTER_SIZE
;
1488 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1490 /* It's an argument being passed in a general register. */
1491 regval
= extract_address (val
, partial_len
);
1492 write_register (argreg
++, regval
);
1496 /* Push the arguments onto the stack. */
1497 write_memory ((CORE_ADDR
) fp
, val
, REGISTER_SIZE
);
1498 fp
+= REGISTER_SIZE
;
1506 /* Return adjusted stack pointer. */
1510 /* Pop the current frame. So long as the frame info has been
1511 initialized properly (see arm_init_extra_frame_info), this code
1512 works for dummy frames as well as regular frames. I.e, there's no
1513 need to have a special case for dummy frames. */
1515 arm_pop_frame (void)
1518 struct frame_info
*frame
= get_current_frame ();
1519 CORE_ADDR old_SP
= (frame
->frame
- frame
->extra_info
->frameoffset
1520 + frame
->extra_info
->framesize
);
1522 if (USE_GENERIC_DUMMY_FRAMES
1523 && PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
1525 generic_pop_dummy_frame ();
1526 flush_cached_frames ();
1530 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1531 if (frame
->saved_regs
[regnum
] != 0)
1532 write_register (regnum
,
1533 read_memory_integer (frame
->saved_regs
[regnum
],
1534 REGISTER_RAW_SIZE (regnum
)));
1536 write_register (ARM_PC_REGNUM
, FRAME_SAVED_PC (frame
));
1537 write_register (ARM_SP_REGNUM
, old_SP
);
1539 flush_cached_frames ();
1543 print_fpu_flags (int flags
)
1545 if (flags
& (1 << 0))
1546 fputs ("IVO ", stdout
);
1547 if (flags
& (1 << 1))
1548 fputs ("DVZ ", stdout
);
1549 if (flags
& (1 << 2))
1550 fputs ("OFL ", stdout
);
1551 if (flags
& (1 << 3))
1552 fputs ("UFL ", stdout
);
1553 if (flags
& (1 << 4))
1554 fputs ("INX ", stdout
);
1558 /* Print interesting information about the floating point processor
1559 (if present) or emulator. */
1561 arm_print_float_info (void)
1563 register unsigned long status
= read_register (ARM_FPS_REGNUM
);
1566 type
= (status
>> 24) & 127;
1567 printf ("%s FPU type %d\n",
1568 (status
& (1 << 31)) ? "Hardware" : "Software",
1570 fputs ("mask: ", stdout
);
1571 print_fpu_flags (status
>> 16);
1572 fputs ("flags: ", stdout
);
1573 print_fpu_flags (status
);
1576 /* Return the GDB type object for the "standard" data type of data in
1579 static struct type
*
1580 arm_register_type (int regnum
)
1582 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1584 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1585 return builtin_type_arm_ext_big
;
1587 return builtin_type_arm_ext_littlebyte_bigword
;
1590 return builtin_type_int32
;
1593 /* Index within `registers' of the first byte of the space for
1597 arm_register_byte (int regnum
)
1599 if (regnum
< ARM_F0_REGNUM
)
1600 return regnum
* INT_REGISTER_RAW_SIZE
;
1601 else if (regnum
< ARM_PS_REGNUM
)
1602 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1603 + (regnum
- ARM_F0_REGNUM
) * FP_REGISTER_RAW_SIZE
);
1605 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1606 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
1607 + (regnum
- ARM_FPS_REGNUM
) * STATUS_REGISTER_SIZE
);
1610 /* Number of bytes of storage in the actual machine representation for
1611 register N. All registers are 4 bytes, except fp0 - fp7, which are
1612 12 bytes in length. */
1615 arm_register_raw_size (int regnum
)
1617 if (regnum
< ARM_F0_REGNUM
)
1618 return INT_REGISTER_RAW_SIZE
;
1619 else if (regnum
< ARM_FPS_REGNUM
)
1620 return FP_REGISTER_RAW_SIZE
;
1622 return STATUS_REGISTER_SIZE
;
1625 /* Number of bytes of storage in a program's representation
1628 arm_register_virtual_size (int regnum
)
1630 if (regnum
< ARM_F0_REGNUM
)
1631 return INT_REGISTER_VIRTUAL_SIZE
;
1632 else if (regnum
< ARM_FPS_REGNUM
)
1633 return FP_REGISTER_VIRTUAL_SIZE
;
1635 return STATUS_REGISTER_SIZE
;
1639 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1640 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1641 It is thought that this is is the floating-point register format on
1642 little-endian systems. */
1645 convert_from_extended (void *ptr
, void *dbl
)
1648 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1649 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1651 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1653 floatformat_from_doublest (TARGET_DOUBLE_FORMAT
, &d
, dbl
);
1657 convert_to_extended (void *dbl
, void *ptr
)
1660 floatformat_to_doublest (TARGET_DOUBLE_FORMAT
, ptr
, &d
);
1661 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1662 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1664 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1669 condition_true (unsigned long cond
, unsigned long status_reg
)
1671 if (cond
== INST_AL
|| cond
== INST_NV
)
1677 return ((status_reg
& FLAG_Z
) != 0);
1679 return ((status_reg
& FLAG_Z
) == 0);
1681 return ((status_reg
& FLAG_C
) != 0);
1683 return ((status_reg
& FLAG_C
) == 0);
1685 return ((status_reg
& FLAG_N
) != 0);
1687 return ((status_reg
& FLAG_N
) == 0);
1689 return ((status_reg
& FLAG_V
) != 0);
1691 return ((status_reg
& FLAG_V
) == 0);
1693 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1695 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1697 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1699 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1701 return (((status_reg
& FLAG_Z
) == 0) &&
1702 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1704 return (((status_reg
& FLAG_Z
) != 0) ||
1705 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1710 /* Support routines for single stepping. Calculate the next PC value. */
1711 #define submask(x) ((1L << ((x) + 1)) - 1)
1712 #define bit(obj,st) (((obj) >> (st)) & 1)
1713 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1714 #define sbits(obj,st,fn) \
1715 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1716 #define BranchDest(addr,instr) \
1717 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1720 static unsigned long
1721 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1722 unsigned long status_reg
)
1724 unsigned long res
, shift
;
1725 int rm
= bits (inst
, 0, 3);
1726 unsigned long shifttype
= bits (inst
, 5, 6);
1730 int rs
= bits (inst
, 8, 11);
1731 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1734 shift
= bits (inst
, 7, 11);
1737 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1738 + (bit (inst
, 4) ? 12 : 8))
1739 : read_register (rm
));
1744 res
= shift
>= 32 ? 0 : res
<< shift
;
1748 res
= shift
>= 32 ? 0 : res
>> shift
;
1754 res
= ((res
& 0x80000000L
)
1755 ? ~((~res
) >> shift
) : res
>> shift
);
1758 case 3: /* ROR/RRX */
1761 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1763 res
= (res
>> shift
) | (res
<< (32 - shift
));
1767 return res
& 0xffffffff;
1770 /* Return number of 1-bits in VAL. */
1773 bitcount (unsigned long val
)
1776 for (nbits
= 0; val
!= 0; nbits
++)
1777 val
&= val
- 1; /* delete rightmost 1-bit in val */
1782 thumb_get_next_pc (CORE_ADDR pc
)
1784 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1785 unsigned short inst1
= read_memory_integer (pc
, 2);
1786 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1787 unsigned long offset
;
1789 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1793 /* Fetch the saved PC from the stack. It's stored above
1794 all of the other registers. */
1795 offset
= bitcount (bits (inst1
, 0, 7)) * REGISTER_SIZE
;
1796 sp
= read_register (ARM_SP_REGNUM
);
1797 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1798 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1800 error ("Infinite loop detected");
1802 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1804 unsigned long status
= read_register (ARM_PS_REGNUM
);
1805 unsigned long cond
= bits (inst1
, 8, 11);
1806 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1807 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1809 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1811 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1813 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1815 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1816 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1817 nextpc
= pc_val
+ offset
;
1824 arm_get_next_pc (CORE_ADDR pc
)
1826 unsigned long pc_val
;
1827 unsigned long this_instr
;
1828 unsigned long status
;
1831 if (arm_pc_is_thumb (pc
))
1832 return thumb_get_next_pc (pc
);
1834 pc_val
= (unsigned long) pc
;
1835 this_instr
= read_memory_integer (pc
, 4);
1836 status
= read_register (ARM_PS_REGNUM
);
1837 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1839 if (condition_true (bits (this_instr
, 28, 31), status
))
1841 switch (bits (this_instr
, 24, 27))
1844 case 0x1: /* data processing */
1848 unsigned long operand1
, operand2
, result
= 0;
1852 if (bits (this_instr
, 12, 15) != 15)
1855 if (bits (this_instr
, 22, 25) == 0
1856 && bits (this_instr
, 4, 7) == 9) /* multiply */
1857 error ("Illegal update to pc in instruction");
1859 /* Multiply into PC */
1860 c
= (status
& FLAG_C
) ? 1 : 0;
1861 rn
= bits (this_instr
, 16, 19);
1862 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1864 if (bit (this_instr
, 25))
1866 unsigned long immval
= bits (this_instr
, 0, 7);
1867 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1868 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1871 else /* operand 2 is a shifted register */
1872 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1874 switch (bits (this_instr
, 21, 24))
1877 result
= operand1
& operand2
;
1881 result
= operand1
^ operand2
;
1885 result
= operand1
- operand2
;
1889 result
= operand2
- operand1
;
1893 result
= operand1
+ operand2
;
1897 result
= operand1
+ operand2
+ c
;
1901 result
= operand1
- operand2
+ c
;
1905 result
= operand2
- operand1
+ c
;
1911 case 0xb: /* tst, teq, cmp, cmn */
1912 result
= (unsigned long) nextpc
;
1916 result
= operand1
| operand2
;
1920 /* Always step into a function. */
1925 result
= operand1
& ~operand2
;
1932 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1935 error ("Infinite loop detected");
1940 case 0x5: /* data transfer */
1943 if (bit (this_instr
, 20))
1946 if (bits (this_instr
, 12, 15) == 15)
1952 if (bit (this_instr
, 22))
1953 error ("Illegal update to pc in instruction");
1955 /* byte write to PC */
1956 rn
= bits (this_instr
, 16, 19);
1957 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1958 if (bit (this_instr
, 24))
1961 int c
= (status
& FLAG_C
) ? 1 : 0;
1962 unsigned long offset
=
1963 (bit (this_instr
, 25)
1964 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1965 : bits (this_instr
, 0, 11));
1967 if (bit (this_instr
, 23))
1972 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1975 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1978 error ("Infinite loop detected");
1984 case 0x9: /* block transfer */
1985 if (bit (this_instr
, 20))
1988 if (bit (this_instr
, 15))
1993 if (bit (this_instr
, 23))
1996 unsigned long reglist
= bits (this_instr
, 0, 14);
1997 offset
= bitcount (reglist
) * 4;
1998 if (bit (this_instr
, 24)) /* pre */
2001 else if (bit (this_instr
, 24))
2005 unsigned long rn_val
=
2006 read_register (bits (this_instr
, 16, 19));
2008 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
2012 nextpc
= ADDR_BITS_REMOVE (nextpc
);
2014 error ("Infinite loop detected");
2019 case 0xb: /* branch & link */
2020 case 0xa: /* branch */
2022 nextpc
= BranchDest (pc
, this_instr
);
2024 nextpc
= ADDR_BITS_REMOVE (nextpc
);
2026 error ("Infinite loop detected");
2032 case 0xe: /* coproc ops */
2037 fprintf_filtered (gdb_stderr
, "Bad bit-field extraction\n");
2045 /* single_step() is called just before we want to resume the inferior,
2046 if we want to single-step it but there is no hardware or kernel
2047 single-step support. We find the target of the coming instruction
2050 single_step() is also called just after the inferior stops. If we
2051 had set up a simulated single-step, we undo our damage. */
2054 arm_software_single_step (enum target_signal sig
, int insert_bpt
)
2056 static int next_pc
; /* State between setting and unsetting. */
2057 static char break_mem
[BREAKPOINT_MAX
]; /* Temporary storage for mem@bpt */
2061 next_pc
= arm_get_next_pc (read_register (ARM_PC_REGNUM
));
2062 target_insert_breakpoint (next_pc
, break_mem
);
2065 target_remove_breakpoint (next_pc
, break_mem
);
2068 #include "bfd-in2.h"
2069 #include "libcoff.h"
2072 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
2074 if (arm_pc_is_thumb (memaddr
))
2076 static asymbol
*asym
;
2077 static combined_entry_type ce
;
2078 static struct coff_symbol_struct csym
;
2079 static struct _bfd fake_bfd
;
2080 static bfd_target fake_target
;
2082 if (csym
.native
== NULL
)
2084 /* Create a fake symbol vector containing a Thumb symbol.
2085 This is solely so that the code in print_insn_little_arm()
2086 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2087 the presence of a Thumb symbol and switch to decoding
2088 Thumb instructions. */
2090 fake_target
.flavour
= bfd_target_coff_flavour
;
2091 fake_bfd
.xvec
= &fake_target
;
2092 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
2094 csym
.symbol
.the_bfd
= &fake_bfd
;
2095 csym
.symbol
.name
= "fake";
2096 asym
= (asymbol
*) & csym
;
2099 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
2100 info
->symbols
= &asym
;
2103 info
->symbols
= NULL
;
2105 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2106 return print_insn_big_arm (memaddr
, info
);
2108 return print_insn_little_arm (memaddr
, info
);
2111 /* The following define instruction sequences that will cause ARM
2112 cpu's to take an undefined instruction trap. These are used to
2113 signal a breakpoint to GDB.
2115 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2116 modes. A different instruction is required for each mode. The ARM
2117 cpu's can also be big or little endian. Thus four different
2118 instructions are needed to support all cases.
2120 Note: ARMv4 defines several new instructions that will take the
2121 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2122 not in fact add the new instructions. The new undefined
2123 instructions in ARMv4 are all instructions that had no defined
2124 behaviour in earlier chips. There is no guarantee that they will
2125 raise an exception, but may be treated as NOP's. In practice, it
2126 may only safe to rely on instructions matching:
2128 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2129 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2130 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2132 Even this may only true if the condition predicate is true. The
2133 following use a condition predicate of ALWAYS so it is always TRUE.
2135 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2136 and NetBSD all use a software interrupt rather than an undefined
2137 instruction to force a trap. This can be handled by by the
2138 abi-specific code during establishment of the gdbarch vector. */
2141 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
2142 override these definitions. */
2143 #ifndef ARM_LE_BREAKPOINT
2144 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2146 #ifndef ARM_BE_BREAKPOINT
2147 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2149 #ifndef THUMB_LE_BREAKPOINT
2150 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
2152 #ifndef THUMB_BE_BREAKPOINT
2153 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
2156 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
2157 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
2158 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2159 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2161 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2162 the program counter value to determine whether a 16-bit or 32-bit
2163 breakpoint should be used. It returns a pointer to a string of
2164 bytes that encode a breakpoint instruction, stores the length of
2165 the string to *lenptr, and adjusts the program counter (if
2166 necessary) to point to the actual memory location where the
2167 breakpoint should be inserted. */
2169 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
2170 breakpoints and storing their handles instread of what was in
2171 memory. It is nice that this is the same size as a handle -
2172 otherwise remote-rdp will have to change. */
2174 static const unsigned char *
2175 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
2177 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2179 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
2181 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2182 *lenptr
= tdep
->thumb_breakpoint_size
;
2183 return tdep
->thumb_breakpoint
;
2187 *lenptr
= tdep
->arm_breakpoint_size
;
2188 return tdep
->arm_breakpoint
;
2192 /* Extract from an array REGBUF containing the (raw) register state a
2193 function return value of type TYPE, and copy that, in virtual
2194 format, into VALBUF. */
2197 arm_extract_return_value (struct type
*type
,
2198 char regbuf
[REGISTER_BYTES
],
2201 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2203 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2205 switch (tdep
->fp_model
)
2208 convert_from_extended (®buf
[REGISTER_BYTE (ARM_F0_REGNUM
)],
2212 case ARM_FLOAT_SOFT
:
2213 case ARM_FLOAT_SOFT_VFP
:
2214 memcpy (valbuf
, ®buf
[REGISTER_BYTE (ARM_A1_REGNUM
)],
2215 TYPE_LENGTH (type
));
2220 (__FILE__
, __LINE__
,
2221 "arm_extract_return_value: Floating point model not supported");
2226 memcpy (valbuf
, ®buf
[REGISTER_BYTE (ARM_A1_REGNUM
)],
2227 TYPE_LENGTH (type
));
2230 /* Extract from an array REGBUF containing the (raw) register state
2231 the address in which a function should return its structure value. */
2234 arm_extract_struct_value_address (char *regbuf
)
2236 return extract_address (regbuf
, REGISTER_RAW_SIZE(ARM_A1_REGNUM
));
2239 /* Will a function return an aggregate type in memory or in a
2240 register? Return 0 if an aggregate type can be returned in a
2241 register, 1 if it must be returned in memory. */
2244 arm_use_struct_convention (int gcc_p
, struct type
*type
)
2247 register enum type_code code
;
2249 /* In the ARM ABI, "integer" like aggregate types are returned in
2250 registers. For an aggregate type to be integer like, its size
2251 must be less than or equal to REGISTER_SIZE and the offset of
2252 each addressable subfield must be zero. Note that bit fields are
2253 not addressable, and all addressable subfields of unions always
2254 start at offset zero.
2256 This function is based on the behaviour of GCC 2.95.1.
2257 See: gcc/arm.c: arm_return_in_memory() for details.
2259 Note: All versions of GCC before GCC 2.95.2 do not set up the
2260 parameters correctly for a function returning the following
2261 structure: struct { float f;}; This should be returned in memory,
2262 not a register. Richard Earnshaw sent me a patch, but I do not
2263 know of any way to detect if a function like the above has been
2264 compiled with the correct calling convention. */
2266 /* All aggregate types that won't fit in a register must be returned
2268 if (TYPE_LENGTH (type
) > REGISTER_SIZE
)
2273 /* The only aggregate types that can be returned in a register are
2274 structs and unions. Arrays must be returned in memory. */
2275 code
= TYPE_CODE (type
);
2276 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2281 /* Assume all other aggregate types can be returned in a register.
2282 Run a check for structures, unions and arrays. */
2285 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2288 /* Need to check if this struct/union is "integer" like. For
2289 this to be true, its size must be less than or equal to
2290 REGISTER_SIZE and the offset of each addressable subfield
2291 must be zero. Note that bit fields are not addressable, and
2292 unions always start at offset zero. If any of the subfields
2293 is a floating point type, the struct/union cannot be an
2296 /* For each field in the object, check:
2297 1) Is it FP? --> yes, nRc = 1;
2298 2) Is it addressable (bitpos != 0) and
2299 not packed (bitsize == 0)?
2303 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2305 enum type_code field_type_code
;
2306 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
2308 /* Is it a floating point type field? */
2309 if (field_type_code
== TYPE_CODE_FLT
)
2315 /* If bitpos != 0, then we have to care about it. */
2316 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2318 /* Bitfields are not addressable. If the field bitsize is
2319 zero, then the field is not packed. Hence it cannot be
2320 a bitfield or any other packed type. */
2321 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2333 /* Write into appropriate registers a function return value of type
2334 TYPE, given in virtual format. */
2337 arm_store_return_value (struct type
*type
, char *valbuf
)
2339 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2341 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2342 char buf
[ARM_MAX_REGISTER_RAW_SIZE
];
2344 switch (tdep
->fp_model
)
2348 convert_to_extended (valbuf
, buf
);
2349 write_register_bytes (REGISTER_BYTE (ARM_F0_REGNUM
), buf
,
2350 FP_REGISTER_RAW_SIZE
);
2353 case ARM_FLOAT_SOFT
:
2354 case ARM_FLOAT_SOFT_VFP
:
2355 write_register_bytes (ARM_A1_REGNUM
, valbuf
, TYPE_LENGTH (type
));
2360 (__FILE__
, __LINE__
,
2361 "arm_store_return_value: Floating point model not supported");
2366 write_register_bytes (ARM_A1_REGNUM
, valbuf
, TYPE_LENGTH (type
));
2369 /* Store the address of the place in which to copy the structure the
2370 subroutine will return. This is called from call_function. */
2373 arm_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
2375 write_register (ARM_A1_REGNUM
, addr
);
2379 arm_get_longjmp_target (CORE_ADDR
*pc
)
2382 char buf
[INT_REGISTER_RAW_SIZE
];
2383 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2385 jb_addr
= read_register (ARM_A1_REGNUM
);
2387 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2388 INT_REGISTER_RAW_SIZE
))
2391 *pc
= extract_address (buf
, INT_REGISTER_RAW_SIZE
);
2395 /* Return non-zero if the PC is inside a thumb call thunk. */
2398 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2400 CORE_ADDR start_addr
;
2402 /* Find the starting address of the function containing the PC. If
2403 the caller didn't give us a name, look it up at the same time. */
2404 if (0 == find_pc_partial_function (pc
, name
? NULL
: &name
,
2408 return strncmp (name
, "_call_via_r", 11) == 0;
2411 /* If PC is in a Thumb call or return stub, return the address of the
2412 target PC, which is in a register. The thunk functions are called
2413 _called_via_xx, where x is the register name. The possible names
2414 are r0-r9, sl, fp, ip, sp, and lr. */
2417 arm_skip_stub (CORE_ADDR pc
)
2420 CORE_ADDR start_addr
;
2422 /* Find the starting address and name of the function containing the PC. */
2423 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2426 /* Call thunks always start with "_call_via_". */
2427 if (strncmp (name
, "_call_via_", 10) == 0)
2429 /* Use the name suffix to determine which register contains the
2431 static char *table
[15] =
2432 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2433 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2437 for (regno
= 0; regno
<= 14; regno
++)
2438 if (strcmp (&name
[10], table
[regno
]) == 0)
2439 return read_register (regno
);
2442 return 0; /* not a stub */
2445 /* If the user changes the register disassembly flavor used for info
2446 register and other commands, we have to also switch the flavor used
2447 in opcodes for disassembly output. This function is run in the set
2448 disassembly_flavor command, and does that. */
2451 set_disassembly_flavor_sfunc (char *args
, int from_tty
,
2452 struct cmd_list_element
*c
)
2454 set_disassembly_flavor ();
2457 /* Return the ARM register name corresponding to register I. */
2459 arm_register_name (int i
)
2461 return arm_register_names
[i
];
2465 set_disassembly_flavor (void)
2467 const char *setname
, *setdesc
, **regnames
;
2470 /* Find the flavor that the user wants in the opcodes table. */
2472 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2473 while ((disassembly_flavor
!= setname
)
2474 && (current
< num_flavor_options
))
2475 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2476 current_option
= current
;
2478 /* Fill our copy. */
2479 for (j
= 0; j
< numregs
; j
++)
2480 arm_register_names
[j
] = (char *) regnames
[j
];
2483 if (isupper (*regnames
[ARM_PC_REGNUM
]))
2485 arm_register_names
[ARM_FPS_REGNUM
] = "FPS";
2486 arm_register_names
[ARM_PS_REGNUM
] = "CPSR";
2490 arm_register_names
[ARM_FPS_REGNUM
] = "fps";
2491 arm_register_names
[ARM_PS_REGNUM
] = "cpsr";
2494 /* Synchronize the disassembler. */
2495 set_arm_regname_option (current
);
2498 /* arm_othernames implements the "othernames" command. This is kind
2499 of hacky, and I prefer the set-show disassembly-flavor which is
2500 also used for the x86 gdb. I will keep this around, however, in
2501 case anyone is actually using it. */
2504 arm_othernames (char *names
, int n
)
2506 /* Circle through the various flavors. */
2507 current_option
= (current_option
+ 1) % num_flavor_options
;
2509 disassembly_flavor
= valid_flavors
[current_option
];
2510 set_disassembly_flavor ();
2513 /* Fetch, and possibly build, an appropriate link_map_offsets structure
2514 for ARM linux targets using the struct offsets defined in <link.h>.
2515 Note, however, that link.h is not actually referred to in this file.
2516 Instead, the relevant structs offsets were obtained from examining
2517 link.h. (We can't refer to link.h from this file because the host
2518 system won't necessarily have it, or if it does, the structs which
2519 it defines will refer to the host system, not the target). */
2521 struct link_map_offsets
*
2522 arm_linux_svr4_fetch_link_map_offsets (void)
2524 static struct link_map_offsets lmo
;
2525 static struct link_map_offsets
*lmp
= 0;
2531 lmo
.r_debug_size
= 8; /* Actual size is 20, but this is all we
2534 lmo
.r_map_offset
= 4;
2537 lmo
.link_map_size
= 20; /* Actual size is 552, but this is all we
2540 lmo
.l_addr_offset
= 0;
2541 lmo
.l_addr_size
= 4;
2543 lmo
.l_name_offset
= 4;
2544 lmo
.l_name_size
= 4;
2546 lmo
.l_next_offset
= 12;
2547 lmo
.l_next_size
= 4;
2549 lmo
.l_prev_offset
= 16;
2550 lmo
.l_prev_size
= 4;
2556 /* Test whether the coff symbol specific value corresponds to a Thumb
2560 coff_sym_is_thumb (int val
)
2562 return (val
== C_THUMBEXT
||
2563 val
== C_THUMBSTAT
||
2564 val
== C_THUMBEXTFUNC
||
2565 val
== C_THUMBSTATFUNC
||
2566 val
== C_THUMBLABEL
);
2569 /* arm_coff_make_msymbol_special()
2570 arm_elf_make_msymbol_special()
2572 These functions test whether the COFF or ELF symbol corresponds to
2573 an address in thumb code, and set a "special" bit in a minimal
2574 symbol to indicate that it does. */
2577 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2579 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2581 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2583 MSYMBOL_SET_SPECIAL (msym
);
2587 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2589 if (coff_sym_is_thumb (val
))
2590 MSYMBOL_SET_SPECIAL (msym
);
2594 static enum gdb_osabi
2595 arm_elf_osabi_sniffer (bfd
*abfd
)
2597 unsigned int elfosabi
, eflags
;
2598 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2600 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2605 /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the
2606 file are conforming to the base specification for that machine
2607 (there are no OS-specific extensions). In order to determine the
2608 real OS in use we must look for OS notes that have been added. */
2609 bfd_map_over_sections (abfd
,
2610 generic_elf_osabi_sniff_abi_tag_sections
,
2612 if (osabi
== GDB_OSABI_UNKNOWN
)
2614 /* Existing ARM tools don't set this field, so look at the EI_FLAGS
2615 field for more information. */
2616 eflags
= EF_ARM_EABI_VERSION(elf_elfheader(abfd
)->e_flags
);
2619 case EF_ARM_EABI_VER1
:
2620 osabi
= GDB_OSABI_ARM_EABI_V1
;
2623 case EF_ARM_EABI_VER2
:
2624 osabi
= GDB_OSABI_ARM_EABI_V2
;
2627 case EF_ARM_EABI_UNKNOWN
:
2628 /* Assume GNU tools. */
2629 osabi
= GDB_OSABI_ARM_APCS
;
2633 internal_error (__FILE__
, __LINE__
,
2634 "arm_elf_osabi_sniffer: Unknown ARM EABI "
2635 "version 0x%x", eflags
);
2641 /* GNU tools use this value. Check note sections in this case,
2643 bfd_map_over_sections (abfd
,
2644 generic_elf_osabi_sniff_abi_tag_sections
,
2646 if (osabi
== GDB_OSABI_UNKNOWN
)
2648 /* Assume APCS ABI. */
2649 osabi
= GDB_OSABI_ARM_APCS
;
2653 case ELFOSABI_FREEBSD
:
2654 osabi
= GDB_OSABI_FREEBSD_ELF
;
2657 case ELFOSABI_NETBSD
:
2658 osabi
= GDB_OSABI_NETBSD_ELF
;
2661 case ELFOSABI_LINUX
:
2662 osabi
= GDB_OSABI_LINUX
;
2670 /* Initialize the current architecture based on INFO. If possible,
2671 re-use an architecture from ARCHES, which is a list of
2672 architectures already created during this debugging session.
2674 Called e.g. at program startup, when reading a core file, and when
2675 reading a binary file. */
2677 static struct gdbarch
*
2678 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2680 struct gdbarch_tdep
*tdep
;
2681 struct gdbarch
*gdbarch
;
2682 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2684 /* Try to deterimine the ABI of the object we are loading. */
2686 if (info
.abfd
!= NULL
)
2688 osabi
= gdbarch_lookup_osabi (info
.abfd
);
2689 if (osabi
== GDB_OSABI_UNKNOWN
)
2691 switch (bfd_get_flavour (info
.abfd
))
2693 case bfd_target_aout_flavour
:
2694 /* Assume it's an old APCS-style ABI. */
2695 osabi
= GDB_OSABI_ARM_APCS
;
2698 case bfd_target_coff_flavour
:
2699 /* Assume it's an old APCS-style ABI. */
2701 osabi
= GDB_OSABI_ARM_APCS
;
2705 /* Leave it as "unknown". */
2710 /* Find a candidate among extant architectures. */
2711 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2713 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
2715 /* Make sure the ABI selection matches. */
2716 tdep
= gdbarch_tdep (arches
->gdbarch
);
2717 if (tdep
&& tdep
->osabi
== osabi
)
2718 return arches
->gdbarch
;
2721 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
2722 gdbarch
= gdbarch_alloc (&info
, tdep
);
2724 tdep
->osabi
= osabi
;
2726 /* This is the way it has always defaulted. */
2727 tdep
->fp_model
= ARM_FLOAT_FPA
;
2730 switch (info
.byte_order
)
2732 case BFD_ENDIAN_BIG
:
2733 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
2734 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
2735 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
2736 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
2740 case BFD_ENDIAN_LITTLE
:
2741 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
2742 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
2743 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
2744 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
2749 internal_error (__FILE__
, __LINE__
,
2750 "arm_gdbarch_init: bad byte order for float format");
2753 /* On ARM targets char defaults to unsigned. */
2754 set_gdbarch_char_signed (gdbarch
, 0);
2756 /* This should be low enough for everything. */
2757 tdep
->lowest_pc
= 0x20;
2758 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
2760 #if OLD_STYLE_ARM_DUMMY_FRAMES
2761 /* NOTE: cagney/2002-05-07: Enable the below to restore the old ARM
2762 specific (non-generic) dummy frame code. Might be useful if
2763 there appears to be a problem with the generic dummy frame
2764 mechanism that replaced it. */
2765 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
2767 /* Call dummy code. */
2768 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
2769 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
2770 /* We have to give this a value now, even though we will re-set it
2771 during each call to arm_fix_call_dummy. */
2772 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 8);
2773 set_gdbarch_call_dummy_p (gdbarch
, 1);
2774 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
2776 set_gdbarch_call_dummy_words (gdbarch
, arm_call_dummy_words
);
2777 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (arm_call_dummy_words
));
2778 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
2779 set_gdbarch_call_dummy_length (gdbarch
, 0);
2781 set_gdbarch_fix_call_dummy (gdbarch
, arm_fix_call_dummy
);
2783 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_on_stack
);
2785 set_gdbarch_use_generic_dummy_frames (gdbarch
, 1);
2786 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
2788 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
2789 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
2791 set_gdbarch_call_dummy_p (gdbarch
, 1);
2792 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
2794 set_gdbarch_call_dummy_words (gdbarch
, arm_call_dummy_words
);
2795 set_gdbarch_sizeof_call_dummy_words (gdbarch
, 0);
2796 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
2797 set_gdbarch_call_dummy_length (gdbarch
, 0);
2799 set_gdbarch_fix_call_dummy (gdbarch
, generic_fix_call_dummy
);
2800 set_gdbarch_pc_in_call_dummy (gdbarch
, generic_pc_in_call_dummy
);
2802 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
2803 set_gdbarch_push_return_address (gdbarch
, arm_push_return_address
);
2806 set_gdbarch_get_saved_register (gdbarch
, generic_get_saved_register
);
2807 set_gdbarch_push_arguments (gdbarch
, arm_push_arguments
);
2808 set_gdbarch_coerce_float_to_double (gdbarch
,
2809 standard_coerce_float_to_double
);
2811 /* Frame handling. */
2812 set_gdbarch_frame_chain_valid (gdbarch
, arm_frame_chain_valid
);
2813 set_gdbarch_init_extra_frame_info (gdbarch
, arm_init_extra_frame_info
);
2814 set_gdbarch_read_fp (gdbarch
, arm_read_fp
);
2815 set_gdbarch_frame_chain (gdbarch
, arm_frame_chain
);
2816 set_gdbarch_frameless_function_invocation
2817 (gdbarch
, arm_frameless_function_invocation
);
2818 set_gdbarch_frame_saved_pc (gdbarch
, arm_frame_saved_pc
);
2819 set_gdbarch_frame_args_address (gdbarch
, arm_frame_args_address
);
2820 set_gdbarch_frame_locals_address (gdbarch
, arm_frame_locals_address
);
2821 set_gdbarch_frame_num_args (gdbarch
, arm_frame_num_args
);
2822 set_gdbarch_frame_args_skip (gdbarch
, 0);
2823 set_gdbarch_frame_init_saved_regs (gdbarch
, arm_frame_init_saved_regs
);
2824 #if OLD_STYLE_ARM_DUMMY_FRAMES
2825 /* NOTE: cagney/2002-05-07: Enable the below to restore the old ARM
2826 specific (non-generic) dummy frame code. Might be useful if
2827 there appears to be a problem with the generic dummy frame
2828 mechanism that replaced it. */
2829 set_gdbarch_push_dummy_frame (gdbarch
, arm_push_dummy_frame
);
2831 set_gdbarch_push_dummy_frame (gdbarch
, generic_push_dummy_frame
);
2833 set_gdbarch_pop_frame (gdbarch
, arm_pop_frame
);
2835 /* Address manipulation. */
2836 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
2837 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
2839 /* Offset from address of function to start of its code. */
2840 set_gdbarch_function_start_offset (gdbarch
, 0);
2842 /* Advance PC across function entry code. */
2843 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
2845 /* Get the PC when a frame might not be available. */
2846 set_gdbarch_saved_pc_after_call (gdbarch
, arm_saved_pc_after_call
);
2848 /* The stack grows downward. */
2849 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2851 /* Breakpoint manipulation. */
2852 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
2853 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2855 /* Information about registers, etc. */
2856 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
2857 set_gdbarch_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
2858 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
2859 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
2860 set_gdbarch_register_byte (gdbarch
, arm_register_byte
);
2861 set_gdbarch_register_bytes (gdbarch
,
2862 (NUM_GREGS
* INT_REGISTER_RAW_SIZE
2863 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
2864 + NUM_SREGS
* STATUS_REGISTER_SIZE
));
2865 set_gdbarch_num_regs (gdbarch
, NUM_GREGS
+ NUM_FREGS
+ NUM_SREGS
);
2866 set_gdbarch_register_raw_size (gdbarch
, arm_register_raw_size
);
2867 set_gdbarch_register_virtual_size (gdbarch
, arm_register_virtual_size
);
2868 set_gdbarch_max_register_raw_size (gdbarch
, FP_REGISTER_RAW_SIZE
);
2869 set_gdbarch_max_register_virtual_size (gdbarch
, FP_REGISTER_VIRTUAL_SIZE
);
2870 set_gdbarch_register_virtual_type (gdbarch
, arm_register_type
);
2872 /* Integer registers are 4 bytes. */
2873 set_gdbarch_register_size (gdbarch
, 4);
2874 set_gdbarch_register_name (gdbarch
, arm_register_name
);
2876 /* Returning results. */
2877 set_gdbarch_extract_return_value (gdbarch
, arm_extract_return_value
);
2878 set_gdbarch_store_return_value (gdbarch
, arm_store_return_value
);
2879 set_gdbarch_store_struct_return (gdbarch
, arm_store_struct_return
);
2880 set_gdbarch_use_struct_convention (gdbarch
, arm_use_struct_convention
);
2881 set_gdbarch_extract_struct_value_address (gdbarch
,
2882 arm_extract_struct_value_address
);
2884 /* Single stepping. */
2885 /* XXX For an RDI target we should ask the target if it can single-step. */
2886 set_gdbarch_software_single_step (gdbarch
, arm_software_single_step
);
2888 /* Minsymbol frobbing. */
2889 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
2890 set_gdbarch_coff_make_msymbol_special (gdbarch
,
2891 arm_coff_make_msymbol_special
);
2893 /* Hook in the ABI-specific overrides, if they have been registered. */
2894 gdbarch_init_osabi (info
, gdbarch
, osabi
);
2896 /* Now we have tuned the configuration, set a few final things,
2897 based on what the OS ABI has told us. */
2899 if (tdep
->jb_pc
>= 0)
2900 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
2902 /* Floating point sizes and format. */
2903 switch (info
.byte_order
)
2905 case BFD_ENDIAN_BIG
:
2906 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
2907 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_big
);
2908 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
2912 case BFD_ENDIAN_LITTLE
:
2913 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
2914 if (tdep
->fp_model
== ARM_FLOAT_VFP
2915 || tdep
->fp_model
== ARM_FLOAT_SOFT_VFP
)
2917 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_little
);
2918 set_gdbarch_long_double_format (gdbarch
,
2919 &floatformat_ieee_double_little
);
2923 set_gdbarch_double_format
2924 (gdbarch
, &floatformat_ieee_double_littlebyte_bigword
);
2925 set_gdbarch_long_double_format
2926 (gdbarch
, &floatformat_ieee_double_littlebyte_bigword
);
2931 internal_error (__FILE__
, __LINE__
,
2932 "arm_gdbarch_init: bad byte order for float format");
2935 /* We can't use SIZEOF_FRAME_SAVED_REGS here, since that still
2936 references the old architecture vector, not the one we are
2938 if (prologue_cache
.saved_regs
!= NULL
)
2939 xfree (prologue_cache
.saved_regs
);
2941 /* We can't use NUM_REGS nor NUM_PSEUDO_REGS here, since that still
2942 references the old architecture vector, not the one we are
2944 prologue_cache
.saved_regs
= (CORE_ADDR
*)
2945 xcalloc (1, (sizeof (CORE_ADDR
)
2946 * (gdbarch_num_regs (gdbarch
)
2947 + gdbarch_num_pseudo_regs (gdbarch
))));
2953 arm_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
2955 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2960 fprintf_unfiltered (file
, "arm_dump_tdep: OS ABI = %s\n",
2961 gdbarch_osabi_name (tdep
->osabi
));
2963 fprintf_unfiltered (file
, "arm_dump_tdep: Lowest pc = 0x%lx",
2964 (unsigned long) tdep
->lowest_pc
);
2968 arm_init_abi_eabi_v1 (struct gdbarch_info info
,
2969 struct gdbarch
*gdbarch
)
2975 arm_init_abi_eabi_v2 (struct gdbarch_info info
,
2976 struct gdbarch
*gdbarch
)
2982 arm_init_abi_apcs (struct gdbarch_info info
,
2983 struct gdbarch
*gdbarch
)
2989 _initialize_arm_tdep (void)
2991 struct ui_file
*stb
;
2993 struct cmd_list_element
*new_cmd
;
2994 const char *setname
;
2995 const char *setdesc
;
2996 const char **regnames
;
2998 static char *helptext
;
3001 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
3003 /* Register an ELF OS ABI sniffer for ARM binaries. */
3004 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
3005 bfd_target_elf_flavour
,
3006 arm_elf_osabi_sniffer
);
3008 /* Register some ABI variants for embedded systems. */
3009 gdbarch_register_osabi (bfd_arch_arm
, GDB_OSABI_ARM_EABI_V1
,
3010 arm_init_abi_eabi_v1
);
3011 gdbarch_register_osabi (bfd_arch_arm
, GDB_OSABI_ARM_EABI_V2
,
3012 arm_init_abi_eabi_v2
);
3013 gdbarch_register_osabi (bfd_arch_arm
, GDB_OSABI_ARM_APCS
,
3016 tm_print_insn
= gdb_print_insn_arm
;
3018 /* Get the number of possible sets of register names defined in opcodes. */
3019 num_flavor_options
= get_arm_regname_num_options ();
3021 /* Sync the opcode insn printer with our register viewer. */
3022 parse_arm_disassembler_option ("reg-names-std");
3024 /* Begin creating the help text. */
3025 stb
= mem_fileopen ();
3026 fprintf_unfiltered (stb
, "Set the disassembly flavor.\n\
3027 The valid values are:\n");
3029 /* Initialize the array that will be passed to add_set_enum_cmd(). */
3030 valid_flavors
= xmalloc ((num_flavor_options
+ 1) * sizeof (char *));
3031 for (i
= 0; i
< num_flavor_options
; i
++)
3033 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
3034 valid_flavors
[i
] = setname
;
3035 fprintf_unfiltered (stb
, "%s - %s\n", setname
,
3037 /* Copy the default names (if found) and synchronize disassembler. */
3038 if (!strcmp (setname
, "std"))
3040 disassembly_flavor
= setname
;
3042 for (j
= 0; j
< numregs
; j
++)
3043 arm_register_names
[j
] = (char *) regnames
[j
];
3044 set_arm_regname_option (i
);
3047 /* Mark the end of valid options. */
3048 valid_flavors
[num_flavor_options
] = NULL
;
3050 /* Finish the creation of the help text. */
3051 fprintf_unfiltered (stb
, "The default is \"std\".");
3052 helptext
= ui_file_xstrdup (stb
, &length
);
3053 ui_file_delete (stb
);
3055 /* Add the disassembly-flavor command. */
3056 new_cmd
= add_set_enum_cmd ("disassembly-flavor", no_class
,
3058 &disassembly_flavor
,
3061 set_cmd_sfunc (new_cmd
, set_disassembly_flavor_sfunc
);
3062 add_show_from_set (new_cmd
, &showlist
);
3064 /* ??? Maybe this should be a boolean. */
3065 add_show_from_set (add_set_cmd ("apcs32", no_class
,
3066 var_zinteger
, (char *) &arm_apcs_32
,
3067 "Set usage of ARM 32-bit mode.\n", &setlist
),
3070 /* Add the deprecated "othernames" command. */
3072 add_com ("othernames", class_obscure
, arm_othernames
,
3073 "Switch to the next set of register names.");
3075 /* Fill in the prologue_cache fields. */
3076 prologue_cache
.saved_regs
= NULL
;
3077 prologue_cache
.extra_info
= (struct frame_extra_info
*)
3078 xcalloc (1, sizeof (struct frame_extra_info
));