1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 #include <ctype.h> /* XXX for isupper () */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
41 #include "gdb/sim-arm.h"
44 #include "coff/internal.h"
47 #include "gdb_assert.h"
51 /* Each OS has a different mechanism for accessing the various
52 registers stored in the sigcontext structure.
54 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
55 function pointer) which may be used to determine the addresses
56 of the various saved registers in the sigcontext structure.
58 For the ARM target, there are three parameters to this function.
59 The first is the pc value of the frame under consideration, the
60 second the stack pointer of this frame, and the last is the
61 register number to fetch.
63 If the tm.h file does not define this macro, then it's assumed that
64 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
67 When it comes time to multi-arching this code, see the identically
68 named machinery in ia64-tdep.c for an example of how it could be
69 done. It should not be necessary to modify the code below where
70 this macro is used. */
72 #ifdef SIGCONTEXT_REGISTER_ADDRESS
73 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
74 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
77 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
78 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
81 /* Macros for setting and testing a bit in a minimal symbol that marks
82 it as Thumb function. The MSB of the minimal symbol's "info" field
83 is used for this purpose.
85 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
86 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
88 #define MSYMBOL_SET_SPECIAL(msym) \
89 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
92 #define MSYMBOL_IS_SPECIAL(msym) \
93 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
95 /* The list of available "set arm ..." and "show arm ..." commands. */
96 static struct cmd_list_element
*setarmcmdlist
= NULL
;
97 static struct cmd_list_element
*showarmcmdlist
= NULL
;
99 /* The type of floating-point to use. Keep this in sync with enum
100 arm_float_model, and the help string in _initialize_arm_tdep. */
101 static const char *fp_model_strings
[] =
110 /* A variable that can be configured by the user. */
111 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
112 static const char *current_fp_model
= "auto";
114 /* Number of different reg name sets (options). */
115 static int num_disassembly_options
;
117 /* We have more registers than the disassembler as gdb can print the value
118 of special registers as well.
119 The general register names are overwritten by whatever is being used by
120 the disassembler at the moment. We also adjust the case of cpsr and fps. */
122 /* Initial value: Register names used in ARM's ISA documentation. */
123 static char * arm_register_name_strings
[] =
124 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
125 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
126 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
127 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
128 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
129 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
130 "fps", "cpsr" }; /* 24 25 */
131 static char **arm_register_names
= arm_register_name_strings
;
133 /* Valid register name styles. */
134 static const char **valid_disassembly_styles
;
136 /* Disassembly style to use. Default to "std" register names. */
137 static const char *disassembly_style
;
138 /* Index to that option in the opcodes table. */
139 static int current_option
;
141 /* This is used to keep the bfd arch_info in sync with the disassembly
143 static void set_disassembly_style_sfunc(char *, int,
144 struct cmd_list_element
*);
145 static void set_disassembly_style (void);
147 static void convert_from_extended (const struct floatformat
*, const void *,
149 static void convert_to_extended (const struct floatformat
*, void *,
152 struct arm_prologue_cache
154 /* The stack pointer at the time this frame was created; i.e. the
155 caller's stack pointer when this function was called. It is used
156 to identify this frame. */
159 /* The frame base for this frame is just prev_sp + frame offset -
160 frame size. FRAMESIZE is the size of this stack frame, and
161 FRAMEOFFSET if the initial offset from the stack pointer (this
162 frame's stack pointer, not PREV_SP) to the frame base. */
167 /* The register used to hold the frame pointer for this frame. */
170 /* Saved register offsets. */
171 struct trad_frame_saved_reg
*saved_regs
;
174 /* Addresses for calling Thumb functions have the bit 0 set.
175 Here are some macros to test, set, or clear bit 0 of addresses. */
176 #define IS_THUMB_ADDR(addr) ((addr) & 1)
177 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
178 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
180 /* Set to true if the 32-bit mode is in use. */
184 /* Flag set by arm_fix_call_dummy that tells whether the target
185 function is a Thumb function. This flag is checked by
186 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
187 its use in valops.c) to pass the function address as an additional
190 static int target_is_thumb
;
192 /* Flag set by arm_fix_call_dummy that tells whether the calling
193 function is a Thumb function. This flag is checked by
196 static int caller_is_thumb
;
198 /* Determine if the program counter specified in MEMADDR is in a Thumb
202 arm_pc_is_thumb (CORE_ADDR memaddr
)
204 struct minimal_symbol
*sym
;
206 /* If bit 0 of the address is set, assume this is a Thumb address. */
207 if (IS_THUMB_ADDR (memaddr
))
210 /* Thumb functions have a "special" bit set in minimal symbols. */
211 sym
= lookup_minimal_symbol_by_pc (memaddr
);
214 return (MSYMBOL_IS_SPECIAL (sym
));
222 /* Determine if the program counter specified in MEMADDR is in a call
223 dummy being called from a Thumb function. */
226 arm_pc_is_thumb_dummy (CORE_ADDR memaddr
)
228 CORE_ADDR sp
= read_sp ();
230 /* FIXME: Until we switch for the new call dummy macros, this heuristic
231 is the best we can do. We are trying to determine if the pc is on
232 the stack, which (hopefully) will only happen in a call dummy.
233 We hope the current stack pointer is not so far alway from the dummy
234 frame location (true if we have not pushed large data structures or
235 gone too many levels deep) and that our 1024 is not enough to consider
236 code regions as part of the stack (true for most practical purposes). */
237 if (deprecated_pc_in_call_dummy (memaddr
))
238 return caller_is_thumb
;
243 /* Remove useless bits from addresses in a running program. */
245 arm_addr_bits_remove (CORE_ADDR val
)
248 return (val
& (arm_pc_is_thumb (val
) ? 0xfffffffe : 0xfffffffc));
250 return (val
& 0x03fffffc);
253 /* When reading symbols, we need to zap the low bit of the address,
254 which may be set to 1 for Thumb functions. */
256 arm_smash_text_address (CORE_ADDR val
)
261 /* Immediately after a function call, return the saved pc. Can't
262 always go through the frames for this because on some machines the
263 new frame is not set up until the new function executes some
267 arm_saved_pc_after_call (struct frame_info
*frame
)
269 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM
));
272 /* A typical Thumb prologue looks like this:
276 Sometimes the latter instruction may be replaced by:
284 or, on tpcs, like this:
291 There is always one instruction of three classes:
296 When we have found at least one of each class we are done with the prolog.
297 Note that the "sub sp, #NN" before the push does not count.
301 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
303 CORE_ADDR current_pc
;
305 bit 0 - push { rlist }
306 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
307 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
311 for (current_pc
= pc
;
312 current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40;
315 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
317 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
319 findmask
|= 1; /* push found */
321 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
324 if ((findmask
& 1) == 0) /* before push ? */
327 findmask
|= 4; /* add/sub sp found */
329 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
331 findmask
|= 2; /* setting of r7 found */
333 else if (insn
== 0x466f) /* mov r7, sp */
335 findmask
|= 2; /* setting of r7 found */
337 else if (findmask
== (4+2+1))
339 /* We have found one of each type of prologue instruction */
343 /* Something in the prolog that we don't care about or some
344 instruction from outside the prolog scheduled here for
352 /* Advance the PC across any function entry prologue instructions to
353 reach some "real" code.
355 The APCS (ARM Procedure Call Standard) defines the following
359 [stmfd sp!, {a1,a2,a3,a4}]
360 stmfd sp!, {...,fp,ip,lr,pc}
361 [stfe f7, [sp, #-12]!]
362 [stfe f6, [sp, #-12]!]
363 [stfe f5, [sp, #-12]!]
364 [stfe f4, [sp, #-12]!]
365 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
368 arm_skip_prologue (CORE_ADDR pc
)
372 CORE_ADDR func_addr
, func_end
= 0;
374 struct symtab_and_line sal
;
376 /* If we're in a dummy frame, don't even try to skip the prologue. */
377 if (deprecated_pc_in_call_dummy (pc
))
380 /* See what the symbol table says. */
382 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
386 /* Found a function. */
387 sym
= lookup_symbol (func_name
, NULL
, VAR_DOMAIN
, NULL
, NULL
);
388 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
390 /* Don't use this trick for assembly source files. */
391 sal
= find_pc_line (func_addr
, 0);
392 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
397 /* Check if this is Thumb code. */
398 if (arm_pc_is_thumb (pc
))
399 return thumb_skip_prologue (pc
, func_end
);
401 /* Can't find the prologue end in the symbol table, try it the hard way
402 by disassembling the instructions. */
404 /* Like arm_scan_prologue, stop no later than pc + 64. */
405 if (func_end
== 0 || func_end
> pc
+ 64)
408 for (skip_pc
= pc
; skip_pc
< func_end
; skip_pc
+= 4)
410 inst
= read_memory_integer (skip_pc
, 4);
412 /* "mov ip, sp" is no longer a required part of the prologue. */
413 if (inst
== 0xe1a0c00d) /* mov ip, sp */
416 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
419 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
422 /* Some prologues begin with "str lr, [sp, #-4]!". */
423 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
426 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
429 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
432 /* Any insns after this point may float into the code, if it makes
433 for better instruction scheduling, so we skip them only if we
434 find them, but still consider the function to be frame-ful. */
436 /* We may have either one sfmfd instruction here, or several stfe
437 insns, depending on the version of floating point code we
439 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
442 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
445 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
448 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
451 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
452 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
453 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
456 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
457 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
458 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
461 /* Un-recognized instruction; stop scanning. */
465 return skip_pc
; /* End of prologue */
469 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
470 This function decodes a Thumb function prologue to determine:
471 1) the size of the stack frame
472 2) which registers are saved on it
473 3) the offsets of saved regs
474 4) the offset from the stack pointer to the frame pointer
476 A typical Thumb function prologue would create this stack frame
477 (offsets relative to FP)
478 old SP -> 24 stack parameters
481 R7 -> 0 local variables (16 bytes)
482 SP -> -12 additional stack space (12 bytes)
483 The frame size would thus be 36 bytes, and the frame offset would be
484 12 bytes. The frame register is R7.
486 The comments for thumb_skip_prolog() describe the algorithm we use
487 to detect the end of the prolog. */
491 thumb_scan_prologue (CORE_ADDR prev_pc
, struct arm_prologue_cache
*cache
)
493 CORE_ADDR prologue_start
;
494 CORE_ADDR prologue_end
;
495 CORE_ADDR current_pc
;
496 /* Which register has been copied to register n? */
499 bit 0 - push { rlist }
500 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
501 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
506 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
508 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
510 if (sal
.line
== 0) /* no line info, use current PC */
511 prologue_end
= prev_pc
;
512 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
513 prologue_end
= sal
.end
; /* (probably means no prologue) */
516 /* We're in the boondocks: allow for
517 16 pushes, an add, and "mv fp,sp". */
518 prologue_end
= prologue_start
+ 40;
520 prologue_end
= min (prologue_end
, prev_pc
);
522 /* Initialize the saved register map. When register H is copied to
523 register L, we will put H in saved_reg[L]. */
524 for (i
= 0; i
< 16; i
++)
527 /* Search the prologue looking for instructions that set up the
528 frame pointer, adjust the stack pointer, and save registers.
529 Do this until all basic prolog instructions are found. */
531 cache
->framesize
= 0;
532 for (current_pc
= prologue_start
;
533 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
540 insn
= read_memory_unsigned_integer (current_pc
, 2);
542 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
545 findmask
|= 1; /* push found */
546 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
547 whether to save LR (R14). */
548 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
550 /* Calculate offsets of saved R0-R7 and LR. */
551 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
552 if (mask
& (1 << regno
))
554 cache
->framesize
+= 4;
555 cache
->saved_regs
[saved_reg
[regno
]].addr
= -cache
->framesize
;
556 /* Reset saved register map. */
557 saved_reg
[regno
] = regno
;
560 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
563 if ((findmask
& 1) == 0) /* before push? */
566 findmask
|= 4; /* add/sub sp found */
568 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
569 if (insn
& 0x80) /* is it signed? (==subtracting) */
571 cache
->frameoffset
+= offset
;
574 cache
->framesize
-= offset
;
576 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
578 findmask
|= 2; /* setting of r7 found */
579 cache
->framereg
= THUMB_FP_REGNUM
;
580 /* get scaled offset */
581 cache
->frameoffset
= (insn
& 0xff) << 2;
583 else if (insn
== 0x466f) /* mov r7, sp */
585 findmask
|= 2; /* setting of r7 found */
586 cache
->framereg
= THUMB_FP_REGNUM
;
587 cache
->frameoffset
= 0;
588 saved_reg
[THUMB_FP_REGNUM
] = ARM_SP_REGNUM
;
590 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
592 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
593 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
594 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
597 /* Something in the prolog that we don't care about or some
598 instruction from outside the prolog scheduled here for
604 /* This function decodes an ARM function prologue to determine:
605 1) the size of the stack frame
606 2) which registers are saved on it
607 3) the offsets of saved regs
608 4) the offset from the stack pointer to the frame pointer
609 This information is stored in the "extra" fields of the frame_info.
611 There are two basic forms for the ARM prologue. The fixed argument
612 function call will look like:
615 stmfd sp!, {fp, ip, lr, pc}
619 Which would create this stack frame (offsets relative to FP):
620 IP -> 4 (caller's stack)
621 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
622 -4 LR (return address in caller)
623 -8 IP (copy of caller's SP)
625 SP -> -28 Local variables
627 The frame size would thus be 32 bytes, and the frame offset would be
628 28 bytes. The stmfd call can also save any of the vN registers it
629 plans to use, which increases the frame size accordingly.
631 Note: The stored PC is 8 off of the STMFD instruction that stored it
632 because the ARM Store instructions always store PC + 8 when you read
635 A variable argument function call will look like:
638 stmfd sp!, {a1, a2, a3, a4}
639 stmfd sp!, {fp, ip, lr, pc}
642 Which would create this stack frame (offsets relative to FP):
643 IP -> 20 (caller's stack)
648 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
649 -4 LR (return address in caller)
650 -8 IP (copy of caller's SP)
652 SP -> -28 Local variables
654 The frame size would thus be 48 bytes, and the frame offset would be
657 There is another potential complication, which is that the optimizer
658 will try to separate the store of fp in the "stmfd" instruction from
659 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
660 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
662 Also, note, the original version of the ARM toolchain claimed that there
665 instruction at the end of the prologue. I have never seen GCC produce
666 this, and the ARM docs don't mention it. We still test for it below in
672 arm_scan_prologue (struct frame_info
*next_frame
, struct arm_prologue_cache
*cache
)
674 int regno
, sp_offset
, fp_offset
, ip_offset
;
675 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
676 CORE_ADDR prev_pc
= frame_pc_unwind (next_frame
);
678 /* Assume there is no frame until proven otherwise. */
679 cache
->framereg
= ARM_SP_REGNUM
;
680 cache
->framesize
= 0;
681 cache
->frameoffset
= 0;
683 /* Check for Thumb prologue. */
684 if (arm_pc_is_thumb (prev_pc
))
686 thumb_scan_prologue (prev_pc
, cache
);
690 /* Find the function prologue. If we can't find the function in
691 the symbol table, peek in the stack frame to find the PC. */
692 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
694 /* One way to find the end of the prologue (which works well
695 for unoptimized code) is to do the following:
697 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
700 prologue_end = prev_pc;
701 else if (sal.end < prologue_end)
702 prologue_end = sal.end;
704 This mechanism is very accurate so long as the optimizer
705 doesn't move any instructions from the function body into the
706 prologue. If this happens, sal.end will be the last
707 instruction in the first hunk of prologue code just before
708 the first instruction that the scheduler has moved from
709 the body to the prologue.
711 In order to make sure that we scan all of the prologue
712 instructions, we use a slightly less accurate mechanism which
713 may scan more than necessary. To help compensate for this
714 lack of accuracy, the prologue scanning loop below contains
715 several clauses which'll cause the loop to terminate early if
716 an implausible prologue instruction is encountered.
722 is a suitable endpoint since it accounts for the largest
723 possible prologue plus up to five instructions inserted by
726 if (prologue_end
> prologue_start
+ 64)
728 prologue_end
= prologue_start
+ 64; /* See above. */
733 /* We have no symbol information. Our only option is to assume this
734 function has a standard stack frame and the normal frame register.
735 Then, we can find the value of our frame pointer on entrance to
736 the callee (or at the present moment if this is the innermost frame).
737 The value stored there should be the address of the stmfd + 8. */
739 LONGEST return_value
;
741 frame_loc
= frame_unwind_register_unsigned (next_frame
, ARM_FP_REGNUM
);
742 if (!safe_read_memory_integer (frame_loc
, 4, &return_value
))
746 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
747 prologue_end
= prologue_start
+ 64; /* See above. */
751 if (prev_pc
< prologue_end
)
752 prologue_end
= prev_pc
;
754 /* Now search the prologue looking for instructions that set up the
755 frame pointer, adjust the stack pointer, and save registers.
757 Be careful, however, and if it doesn't look like a prologue,
758 don't try to scan it. If, for instance, a frameless function
759 begins with stmfd sp!, then we will tell ourselves there is
760 a frame, which will confuse stack traceback, as well as "finish"
761 and other operations that rely on a knowledge of the stack
764 In the APCS, the prologue should start with "mov ip, sp" so
765 if we don't see this as the first insn, we will stop.
767 [Note: This doesn't seem to be true any longer, so it's now an
768 optional part of the prologue. - Kevin Buettner, 2001-11-20]
770 [Note further: The "mov ip,sp" only seems to be missing in
771 frameless functions at optimization level "-O2" or above,
772 in which case it is often (but not always) replaced by
773 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
775 sp_offset
= fp_offset
= ip_offset
= 0;
777 for (current_pc
= prologue_start
;
778 current_pc
< prologue_end
;
781 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
783 if (insn
== 0xe1a0c00d) /* mov ip, sp */
788 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
790 unsigned imm
= insn
& 0xff; /* immediate value */
791 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
792 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
796 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
798 unsigned imm
= insn
& 0xff; /* immediate value */
799 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
800 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
804 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
807 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= sp_offset
;
810 else if ((insn
& 0xffff0000) == 0xe92d0000)
811 /* stmfd sp!, {..., fp, ip, lr, pc}
813 stmfd sp!, {a1, a2, a3, a4} */
815 int mask
= insn
& 0xffff;
817 /* Calculate offsets of saved registers. */
818 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
819 if (mask
& (1 << regno
))
822 cache
->saved_regs
[regno
].addr
= sp_offset
;
825 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
826 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
827 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
829 /* No need to add this to saved_regs -- it's just an arg reg. */
832 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
833 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
834 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
836 /* No need to add this to saved_regs -- it's just an arg reg. */
839 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
841 unsigned imm
= insn
& 0xff; /* immediate value */
842 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
843 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
844 fp_offset
= -imm
+ ip_offset
;
845 cache
->framereg
= ARM_FP_REGNUM
;
847 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
849 unsigned imm
= insn
& 0xff; /* immediate value */
850 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
851 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
854 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
857 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
858 cache
->saved_regs
[regno
].addr
= sp_offset
;
860 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
863 unsigned int fp_start_reg
, fp_bound_reg
;
865 if ((insn
& 0x800) == 0x800) /* N0 is set */
867 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
874 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
880 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
881 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
882 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
885 cache
->saved_regs
[fp_start_reg
++].addr
= sp_offset
;
888 else if ((insn
& 0xf0000000) != 0xe0000000)
889 break; /* Condition not true, exit early */
890 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
891 break; /* Don't scan past a block load */
893 /* The optimizer might shove anything into the prologue,
894 so we just skip what we don't recognize. */
898 /* The frame size is just the negative of the offset (from the
899 original SP) of the last thing thing we pushed on the stack.
900 The frame offset is [new FP] - [new SP]. */
901 cache
->framesize
= -sp_offset
;
902 if (cache
->framereg
== ARM_FP_REGNUM
)
903 cache
->frameoffset
= fp_offset
- sp_offset
;
905 cache
->frameoffset
= 0;
908 static struct arm_prologue_cache
*
909 arm_make_prologue_cache (struct frame_info
*next_frame
)
912 struct arm_prologue_cache
*cache
;
913 CORE_ADDR unwound_fp
;
915 cache
= frame_obstack_zalloc (sizeof (struct arm_prologue_cache
));
916 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
918 arm_scan_prologue (next_frame
, cache
);
920 unwound_fp
= frame_unwind_register_unsigned (next_frame
, cache
->framereg
);
924 cache
->prev_sp
= unwound_fp
+ cache
->framesize
- cache
->frameoffset
;
926 /* Calculate actual addresses of saved registers using offsets
927 determined by arm_scan_prologue. */
928 for (reg
= 0; reg
< NUM_REGS
; reg
++)
929 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
930 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
935 /* Our frame ID for a normal frame is the current function's starting PC
936 and the caller's SP when we were called. */
939 arm_prologue_this_id (struct frame_info
*next_frame
,
941 struct frame_id
*this_id
)
943 struct arm_prologue_cache
*cache
;
947 if (*this_cache
== NULL
)
948 *this_cache
= arm_make_prologue_cache (next_frame
);
951 func
= frame_func_unwind (next_frame
);
953 /* This is meant to halt the backtrace at "_start". Make sure we
954 don't halt it at a generic dummy frame. */
955 if (func
<= LOWEST_PC
)
958 /* If we've hit a wall, stop. */
959 if (cache
->prev_sp
== 0)
962 id
= frame_id_build (cache
->prev_sp
, func
);
967 arm_prologue_prev_register (struct frame_info
*next_frame
,
971 enum lval_type
*lvalp
,
976 struct arm_prologue_cache
*cache
;
978 if (*this_cache
== NULL
)
979 *this_cache
= arm_make_prologue_cache (next_frame
);
982 /* If we are asked to unwind the PC, then we need to return the LR
983 instead. The saved value of PC points into this frame's
984 prologue, not the next frame's resume location. */
985 if (prev_regnum
== ARM_PC_REGNUM
)
986 prev_regnum
= ARM_LR_REGNUM
;
988 /* SP is generally not saved to the stack, but this frame is
989 identified by NEXT_FRAME's stack pointer at the time of the call.
990 The value was already reconstructed into PREV_SP. */
991 if (prev_regnum
== ARM_SP_REGNUM
)
995 store_unsigned_integer (valuep
, 4, cache
->prev_sp
);
999 trad_frame_get_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
1000 optimized
, lvalp
, addrp
, realnump
, valuep
);
1003 struct frame_unwind arm_prologue_unwind
= {
1005 arm_prologue_this_id
,
1006 arm_prologue_prev_register
1009 static const struct frame_unwind
*
1010 arm_prologue_unwind_sniffer (struct frame_info
*next_frame
)
1012 return &arm_prologue_unwind
;
1016 arm_normal_frame_base (struct frame_info
*next_frame
, void **this_cache
)
1018 struct arm_prologue_cache
*cache
;
1020 if (*this_cache
== NULL
)
1021 *this_cache
= arm_make_prologue_cache (next_frame
);
1022 cache
= *this_cache
;
1024 return cache
->prev_sp
+ cache
->frameoffset
- cache
->framesize
;
1027 struct frame_base arm_normal_base
= {
1028 &arm_prologue_unwind
,
1029 arm_normal_frame_base
,
1030 arm_normal_frame_base
,
1031 arm_normal_frame_base
1034 static struct arm_prologue_cache
*
1035 arm_make_sigtramp_cache (struct frame_info
*next_frame
)
1037 struct arm_prologue_cache
*cache
;
1040 cache
= frame_obstack_zalloc (sizeof (struct arm_prologue_cache
));
1042 cache
->prev_sp
= frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
);
1044 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1046 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1047 cache
->saved_regs
[reg
].addr
1048 = SIGCONTEXT_REGISTER_ADDRESS (cache
->prev_sp
,
1049 frame_pc_unwind (next_frame
), reg
);
1051 /* FIXME: What about thumb mode? */
1052 cache
->framereg
= ARM_SP_REGNUM
;
1054 = read_memory_integer (cache
->saved_regs
[cache
->framereg
].addr
,
1055 register_size (current_gdbarch
, cache
->framereg
));
1061 arm_sigtramp_this_id (struct frame_info
*next_frame
,
1063 struct frame_id
*this_id
)
1065 struct arm_prologue_cache
*cache
;
1067 if (*this_cache
== NULL
)
1068 *this_cache
= arm_make_sigtramp_cache (next_frame
);
1069 cache
= *this_cache
;
1071 /* FIXME drow/2003-07-07: This isn't right if we single-step within
1072 the sigtramp frame; the PC should be the beginning of the trampoline. */
1073 *this_id
= frame_id_build (cache
->prev_sp
, frame_pc_unwind (next_frame
));
1077 arm_sigtramp_prev_register (struct frame_info
*next_frame
,
1081 enum lval_type
*lvalp
,
1086 struct arm_prologue_cache
*cache
;
1088 if (*this_cache
== NULL
)
1089 *this_cache
= arm_make_sigtramp_cache (next_frame
);
1090 cache
= *this_cache
;
1092 trad_frame_get_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
1093 optimized
, lvalp
, addrp
, realnump
, valuep
);
1096 struct frame_unwind arm_sigtramp_unwind
= {
1098 arm_sigtramp_this_id
,
1099 arm_sigtramp_prev_register
1102 static const struct frame_unwind
*
1103 arm_sigtramp_unwind_sniffer (struct frame_info
*next_frame
)
1105 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1106 && legacy_pc_in_sigtramp (frame_pc_unwind (next_frame
), (char *) 0))
1107 return &arm_sigtramp_unwind
;
1112 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1113 dummy frame. The frame ID's base needs to match the TOS value
1114 saved by save_dummy_frame_tos() and returned from
1115 arm_push_dummy_call, and the PC needs to match the dummy frame's
1118 static struct frame_id
1119 arm_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1121 return frame_id_build (frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
),
1122 frame_pc_unwind (next_frame
));
1125 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1126 be used to construct the previous frame's ID, after looking up the
1127 containing function). */
1130 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1133 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1134 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1138 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1140 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1143 /* When arguments must be pushed onto the stack, they go on in reverse
1144 order. The code below implements a FILO (stack) to do this. */
1149 struct stack_item
*prev
;
1153 static struct stack_item
*
1154 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1156 struct stack_item
*si
;
1157 si
= xmalloc (sizeof (struct stack_item
));
1158 si
->data
= xmalloc (len
);
1161 memcpy (si
->data
, contents
, len
);
1165 static struct stack_item
*
1166 pop_stack_item (struct stack_item
*si
)
1168 struct stack_item
*dead
= si
;
1175 /* We currently only support passing parameters in integer registers. This
1176 conforms with GCC's default model. Several other variants exist and
1177 we should probably support some of them based on the selected ABI. */
1180 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1181 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1182 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1183 CORE_ADDR struct_addr
)
1188 struct stack_item
*si
= NULL
;
1190 /* Set the return address. For the ARM, the return breakpoint is
1191 always at BP_ADDR. */
1192 /* XXX Fix for Thumb. */
1193 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1195 /* Walk through the list of args and determine how large a temporary
1196 stack is required. Need to take care here as structs may be
1197 passed on the stack, and we have to to push them. */
1200 argreg
= ARM_A1_REGNUM
;
1203 /* Some platforms require a double-word aligned stack. Make sure sp
1204 is correctly aligned before we start. We always do this even if
1205 it isn't really needed -- it can never hurt things. */
1206 sp
&= ~(CORE_ADDR
)(2 * DEPRECATED_REGISTER_SIZE
- 1);
1208 /* The struct_return pointer occupies the first parameter
1209 passing register. */
1213 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = 0x%s\n",
1214 REGISTER_NAME (argreg
), paddr (struct_addr
));
1215 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1219 for (argnum
= 0; argnum
< nargs
; argnum
++)
1222 struct type
*arg_type
;
1223 struct type
*target_type
;
1224 enum type_code typecode
;
1227 arg_type
= check_typedef (value_type (args
[argnum
]));
1228 len
= TYPE_LENGTH (arg_type
);
1229 target_type
= TYPE_TARGET_TYPE (arg_type
);
1230 typecode
= TYPE_CODE (arg_type
);
1231 val
= VALUE_CONTENTS (args
[argnum
]);
1233 /* If the argument is a pointer to a function, and it is a
1234 Thumb function, create a LOCAL copy of the value and set
1235 the THUMB bit in it. */
1236 if (TYPE_CODE_PTR
== typecode
1237 && target_type
!= NULL
1238 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1240 CORE_ADDR regval
= extract_unsigned_integer (val
, len
);
1241 if (arm_pc_is_thumb (regval
))
1244 store_unsigned_integer (val
, len
, MAKE_THUMB_ADDR (regval
));
1248 /* Copy the argument to general registers or the stack in
1249 register-sized pieces. Large arguments are split between
1250 registers and stack. */
1253 int partial_len
= len
< DEPRECATED_REGISTER_SIZE
? len
: DEPRECATED_REGISTER_SIZE
;
1255 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1257 /* The argument is being passed in a general purpose
1259 CORE_ADDR regval
= extract_unsigned_integer (val
, partial_len
);
1261 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1262 argnum
, REGISTER_NAME (argreg
),
1263 phex (regval
, DEPRECATED_REGISTER_SIZE
));
1264 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1269 /* Push the arguments onto the stack. */
1271 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1273 si
= push_stack_item (si
, val
, DEPRECATED_REGISTER_SIZE
);
1274 nstack
+= DEPRECATED_REGISTER_SIZE
;
1281 /* If we have an odd number of words to push, then decrement the stack
1282 by one word now, so first stack argument will be dword aligned. */
1289 write_memory (sp
, si
->data
, si
->len
);
1290 si
= pop_stack_item (si
);
1293 /* Finally, update teh SP register. */
1294 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1300 print_fpu_flags (int flags
)
1302 if (flags
& (1 << 0))
1303 fputs ("IVO ", stdout
);
1304 if (flags
& (1 << 1))
1305 fputs ("DVZ ", stdout
);
1306 if (flags
& (1 << 2))
1307 fputs ("OFL ", stdout
);
1308 if (flags
& (1 << 3))
1309 fputs ("UFL ", stdout
);
1310 if (flags
& (1 << 4))
1311 fputs ("INX ", stdout
);
1315 /* Print interesting information about the floating point processor
1316 (if present) or emulator. */
1318 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1319 struct frame_info
*frame
, const char *args
)
1321 unsigned long status
= read_register (ARM_FPS_REGNUM
);
1324 type
= (status
>> 24) & 127;
1325 if (status
& (1 << 31))
1326 printf (_("Hardware FPU type %d\n"), type
);
1328 printf (_("Software FPU type %d\n"), type
);
1329 /* i18n: [floating point unit] mask */
1330 fputs (_("mask: "), stdout
);
1331 print_fpu_flags (status
>> 16);
1332 /* i18n: [floating point unit] flags */
1333 fputs (_("flags: "), stdout
);
1334 print_fpu_flags (status
);
1337 /* Return the GDB type object for the "standard" data type of data in
1340 static struct type
*
1341 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
1343 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1345 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1346 return builtin_type_arm_ext_big
;
1348 return builtin_type_arm_ext_littlebyte_bigword
;
1351 return builtin_type_int32
;
1354 /* Index within `registers' of the first byte of the space for
1358 arm_register_byte (int regnum
)
1360 if (regnum
< ARM_F0_REGNUM
)
1361 return regnum
* INT_REGISTER_SIZE
;
1362 else if (regnum
< ARM_PS_REGNUM
)
1363 return (NUM_GREGS
* INT_REGISTER_SIZE
1364 + (regnum
- ARM_F0_REGNUM
) * FP_REGISTER_SIZE
);
1366 return (NUM_GREGS
* INT_REGISTER_SIZE
1367 + NUM_FREGS
* FP_REGISTER_SIZE
1368 + (regnum
- ARM_FPS_REGNUM
) * STATUS_REGISTER_SIZE
);
1371 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1373 arm_register_sim_regno (int regnum
)
1376 gdb_assert (reg
>= 0 && reg
< NUM_REGS
);
1378 if (reg
< NUM_GREGS
)
1379 return SIM_ARM_R0_REGNUM
+ reg
;
1382 if (reg
< NUM_FREGS
)
1383 return SIM_ARM_FP0_REGNUM
+ reg
;
1386 if (reg
< NUM_SREGS
)
1387 return SIM_ARM_FPS_REGNUM
+ reg
;
1390 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
1393 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1394 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1395 It is thought that this is is the floating-point register format on
1396 little-endian systems. */
1399 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
1403 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1404 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1406 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1408 floatformat_from_doublest (fmt
, &d
, dbl
);
1412 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
)
1415 floatformat_to_doublest (fmt
, ptr
, &d
);
1416 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1417 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1419 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1424 condition_true (unsigned long cond
, unsigned long status_reg
)
1426 if (cond
== INST_AL
|| cond
== INST_NV
)
1432 return ((status_reg
& FLAG_Z
) != 0);
1434 return ((status_reg
& FLAG_Z
) == 0);
1436 return ((status_reg
& FLAG_C
) != 0);
1438 return ((status_reg
& FLAG_C
) == 0);
1440 return ((status_reg
& FLAG_N
) != 0);
1442 return ((status_reg
& FLAG_N
) == 0);
1444 return ((status_reg
& FLAG_V
) != 0);
1446 return ((status_reg
& FLAG_V
) == 0);
1448 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1450 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1452 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1454 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1456 return (((status_reg
& FLAG_Z
) == 0) &&
1457 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1459 return (((status_reg
& FLAG_Z
) != 0) ||
1460 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1465 /* Support routines for single stepping. Calculate the next PC value. */
1466 #define submask(x) ((1L << ((x) + 1)) - 1)
1467 #define bit(obj,st) (((obj) >> (st)) & 1)
1468 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1469 #define sbits(obj,st,fn) \
1470 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1471 #define BranchDest(addr,instr) \
1472 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1475 static unsigned long
1476 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1477 unsigned long status_reg
)
1479 unsigned long res
, shift
;
1480 int rm
= bits (inst
, 0, 3);
1481 unsigned long shifttype
= bits (inst
, 5, 6);
1485 int rs
= bits (inst
, 8, 11);
1486 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1489 shift
= bits (inst
, 7, 11);
1492 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1493 + (bit (inst
, 4) ? 12 : 8))
1494 : read_register (rm
));
1499 res
= shift
>= 32 ? 0 : res
<< shift
;
1503 res
= shift
>= 32 ? 0 : res
>> shift
;
1509 res
= ((res
& 0x80000000L
)
1510 ? ~((~res
) >> shift
) : res
>> shift
);
1513 case 3: /* ROR/RRX */
1516 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1518 res
= (res
>> shift
) | (res
<< (32 - shift
));
1522 return res
& 0xffffffff;
1525 /* Return number of 1-bits in VAL. */
1528 bitcount (unsigned long val
)
1531 for (nbits
= 0; val
!= 0; nbits
++)
1532 val
&= val
- 1; /* delete rightmost 1-bit in val */
1537 thumb_get_next_pc (CORE_ADDR pc
)
1539 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1540 unsigned short inst1
= read_memory_integer (pc
, 2);
1541 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1542 unsigned long offset
;
1544 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1548 /* Fetch the saved PC from the stack. It's stored above
1549 all of the other registers. */
1550 offset
= bitcount (bits (inst1
, 0, 7)) * DEPRECATED_REGISTER_SIZE
;
1551 sp
= read_register (ARM_SP_REGNUM
);
1552 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1553 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1555 error (_("Infinite loop detected"));
1557 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1559 unsigned long status
= read_register (ARM_PS_REGNUM
);
1560 unsigned long cond
= bits (inst1
, 8, 11);
1561 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1562 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1564 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1566 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1568 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link, and blx */
1570 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1571 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1572 nextpc
= pc_val
+ offset
;
1573 /* For BLX make sure to clear the low bits. */
1574 if (bits (inst2
, 11, 12) == 1)
1575 nextpc
= nextpc
& 0xfffffffc;
1577 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
1579 if (bits (inst1
, 3, 6) == 0x0f)
1582 nextpc
= read_register (bits (inst1
, 3, 6));
1584 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1586 error (_("Infinite loop detected"));
1593 arm_get_next_pc (CORE_ADDR pc
)
1595 unsigned long pc_val
;
1596 unsigned long this_instr
;
1597 unsigned long status
;
1600 if (arm_pc_is_thumb (pc
))
1601 return thumb_get_next_pc (pc
);
1603 pc_val
= (unsigned long) pc
;
1604 this_instr
= read_memory_integer (pc
, 4);
1605 status
= read_register (ARM_PS_REGNUM
);
1606 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1608 if (condition_true (bits (this_instr
, 28, 31), status
))
1610 switch (bits (this_instr
, 24, 27))
1613 case 0x1: /* data processing */
1617 unsigned long operand1
, operand2
, result
= 0;
1621 if (bits (this_instr
, 12, 15) != 15)
1624 if (bits (this_instr
, 22, 25) == 0
1625 && bits (this_instr
, 4, 7) == 9) /* multiply */
1626 error (_("Invalid update to pc in instruction"));
1628 /* BX <reg>, BLX <reg> */
1629 if (bits (this_instr
, 4, 28) == 0x12fff1
1630 || bits (this_instr
, 4, 28) == 0x12fff3)
1632 rn
= bits (this_instr
, 0, 3);
1633 result
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1634 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1637 error (_("Infinite loop detected"));
1642 /* Multiply into PC */
1643 c
= (status
& FLAG_C
) ? 1 : 0;
1644 rn
= bits (this_instr
, 16, 19);
1645 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1647 if (bit (this_instr
, 25))
1649 unsigned long immval
= bits (this_instr
, 0, 7);
1650 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1651 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1654 else /* operand 2 is a shifted register */
1655 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1657 switch (bits (this_instr
, 21, 24))
1660 result
= operand1
& operand2
;
1664 result
= operand1
^ operand2
;
1668 result
= operand1
- operand2
;
1672 result
= operand2
- operand1
;
1676 result
= operand1
+ operand2
;
1680 result
= operand1
+ operand2
+ c
;
1684 result
= operand1
- operand2
+ c
;
1688 result
= operand2
- operand1
+ c
;
1694 case 0xb: /* tst, teq, cmp, cmn */
1695 result
= (unsigned long) nextpc
;
1699 result
= operand1
| operand2
;
1703 /* Always step into a function. */
1708 result
= operand1
& ~operand2
;
1715 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1718 error (_("Infinite loop detected"));
1723 case 0x5: /* data transfer */
1726 if (bit (this_instr
, 20))
1729 if (bits (this_instr
, 12, 15) == 15)
1735 if (bit (this_instr
, 22))
1736 error (_("Invalid update to pc in instruction"));
1738 /* byte write to PC */
1739 rn
= bits (this_instr
, 16, 19);
1740 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1741 if (bit (this_instr
, 24))
1744 int c
= (status
& FLAG_C
) ? 1 : 0;
1745 unsigned long offset
=
1746 (bit (this_instr
, 25)
1747 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1748 : bits (this_instr
, 0, 11));
1750 if (bit (this_instr
, 23))
1755 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1758 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1761 error (_("Infinite loop detected"));
1767 case 0x9: /* block transfer */
1768 if (bit (this_instr
, 20))
1771 if (bit (this_instr
, 15))
1776 if (bit (this_instr
, 23))
1779 unsigned long reglist
= bits (this_instr
, 0, 14);
1780 offset
= bitcount (reglist
) * 4;
1781 if (bit (this_instr
, 24)) /* pre */
1784 else if (bit (this_instr
, 24))
1788 unsigned long rn_val
=
1789 read_register (bits (this_instr
, 16, 19));
1791 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1795 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1797 error (_("Infinite loop detected"));
1802 case 0xb: /* branch & link */
1803 case 0xa: /* branch */
1805 nextpc
= BranchDest (pc
, this_instr
);
1808 if (bits (this_instr
, 28, 31) == INST_NV
)
1809 nextpc
|= bit (this_instr
, 24) << 1;
1811 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1813 error (_("Infinite loop detected"));
1819 case 0xe: /* coproc ops */
1824 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
1832 /* single_step() is called just before we want to resume the inferior,
1833 if we want to single-step it but there is no hardware or kernel
1834 single-step support. We find the target of the coming instruction
1837 single_step() is also called just after the inferior stops. If we
1838 had set up a simulated single-step, we undo our damage. */
1841 arm_software_single_step (enum target_signal sig
, int insert_bpt
)
1843 static int next_pc
; /* State between setting and unsetting. */
1844 static char break_mem
[BREAKPOINT_MAX
]; /* Temporary storage for mem@bpt */
1848 next_pc
= arm_get_next_pc (read_register (ARM_PC_REGNUM
));
1849 target_insert_breakpoint (next_pc
, break_mem
);
1852 target_remove_breakpoint (next_pc
, break_mem
);
1855 #include "bfd-in2.h"
1856 #include "libcoff.h"
1859 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
1861 if (arm_pc_is_thumb (memaddr
))
1863 static asymbol
*asym
;
1864 static combined_entry_type ce
;
1865 static struct coff_symbol_struct csym
;
1866 static struct bfd fake_bfd
;
1867 static bfd_target fake_target
;
1869 if (csym
.native
== NULL
)
1871 /* Create a fake symbol vector containing a Thumb symbol.
1872 This is solely so that the code in print_insn_little_arm()
1873 and print_insn_big_arm() in opcodes/arm-dis.c will detect
1874 the presence of a Thumb symbol and switch to decoding
1875 Thumb instructions. */
1877 fake_target
.flavour
= bfd_target_coff_flavour
;
1878 fake_bfd
.xvec
= &fake_target
;
1879 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
1881 csym
.symbol
.the_bfd
= &fake_bfd
;
1882 csym
.symbol
.name
= "fake";
1883 asym
= (asymbol
*) & csym
;
1886 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
1887 info
->symbols
= &asym
;
1890 info
->symbols
= NULL
;
1892 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1893 return print_insn_big_arm (memaddr
, info
);
1895 return print_insn_little_arm (memaddr
, info
);
1898 /* The following define instruction sequences that will cause ARM
1899 cpu's to take an undefined instruction trap. These are used to
1900 signal a breakpoint to GDB.
1902 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
1903 modes. A different instruction is required for each mode. The ARM
1904 cpu's can also be big or little endian. Thus four different
1905 instructions are needed to support all cases.
1907 Note: ARMv4 defines several new instructions that will take the
1908 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
1909 not in fact add the new instructions. The new undefined
1910 instructions in ARMv4 are all instructions that had no defined
1911 behaviour in earlier chips. There is no guarantee that they will
1912 raise an exception, but may be treated as NOP's. In practice, it
1913 may only safe to rely on instructions matching:
1915 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1916 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1917 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
1919 Even this may only true if the condition predicate is true. The
1920 following use a condition predicate of ALWAYS so it is always TRUE.
1922 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
1923 and NetBSD all use a software interrupt rather than an undefined
1924 instruction to force a trap. This can be handled by by the
1925 abi-specific code during establishment of the gdbarch vector. */
1928 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
1929 override these definitions. */
1930 #ifndef ARM_LE_BREAKPOINT
1931 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
1933 #ifndef ARM_BE_BREAKPOINT
1934 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
1936 #ifndef THUMB_LE_BREAKPOINT
1937 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
1939 #ifndef THUMB_BE_BREAKPOINT
1940 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
1943 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
1944 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
1945 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
1946 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
1948 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
1949 the program counter value to determine whether a 16-bit or 32-bit
1950 breakpoint should be used. It returns a pointer to a string of
1951 bytes that encode a breakpoint instruction, stores the length of
1952 the string to *lenptr, and adjusts the program counter (if
1953 necessary) to point to the actual memory location where the
1954 breakpoint should be inserted. */
1956 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
1957 breakpoints and storing their handles instread of what was in
1958 memory. It is nice that this is the same size as a handle -
1959 otherwise remote-rdp will have to change. */
1961 static const unsigned char *
1962 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1964 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1966 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
1968 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1969 *lenptr
= tdep
->thumb_breakpoint_size
;
1970 return tdep
->thumb_breakpoint
;
1974 *lenptr
= tdep
->arm_breakpoint_size
;
1975 return tdep
->arm_breakpoint
;
1979 /* Extract from an array REGBUF containing the (raw) register state a
1980 function return value of type TYPE, and copy that, in virtual
1981 format, into VALBUF. */
1984 arm_extract_return_value (struct type
*type
,
1985 struct regcache
*regs
,
1988 bfd_byte
*valbuf
= dst
;
1990 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
1992 switch (arm_get_fp_model (current_gdbarch
))
1996 /* The value is in register F0 in internal format. We need to
1997 extract the raw value and then convert it to the desired
1999 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
2001 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
2002 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
2007 case ARM_FLOAT_SOFT_FPA
:
2008 case ARM_FLOAT_SOFT_VFP
:
2009 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
2010 if (TYPE_LENGTH (type
) > 4)
2011 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
2012 valbuf
+ INT_REGISTER_SIZE
);
2017 (__FILE__
, __LINE__
,
2018 _("arm_extract_return_value: Floating point model not supported"));
2022 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2023 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2024 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2025 || TYPE_CODE (type
) == TYPE_CODE_PTR
2026 || TYPE_CODE (type
) == TYPE_CODE_REF
2027 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2029 /* If the the type is a plain integer, then the access is
2030 straight-forward. Otherwise we have to play around a bit more. */
2031 int len
= TYPE_LENGTH (type
);
2032 int regno
= ARM_A1_REGNUM
;
2037 /* By using store_unsigned_integer we avoid having to do
2038 anything special for small big-endian values. */
2039 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2040 store_unsigned_integer (valbuf
,
2041 (len
> INT_REGISTER_SIZE
2042 ? INT_REGISTER_SIZE
: len
),
2044 len
-= INT_REGISTER_SIZE
;
2045 valbuf
+= INT_REGISTER_SIZE
;
2050 /* For a structure or union the behaviour is as if the value had
2051 been stored to word-aligned memory and then loaded into
2052 registers with 32-bit load instruction(s). */
2053 int len
= TYPE_LENGTH (type
);
2054 int regno
= ARM_A1_REGNUM
;
2055 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2059 regcache_cooked_read (regs
, regno
++, tmpbuf
);
2060 memcpy (valbuf
, tmpbuf
,
2061 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2062 len
-= INT_REGISTER_SIZE
;
2063 valbuf
+= INT_REGISTER_SIZE
;
2068 /* Extract from an array REGBUF containing the (raw) register state
2069 the address in which a function should return its structure value. */
2072 arm_extract_struct_value_address (struct regcache
*regcache
)
2076 regcache_cooked_read_unsigned (regcache
, ARM_A1_REGNUM
, &ret
);
2080 /* Will a function return an aggregate type in memory or in a
2081 register? Return 0 if an aggregate type can be returned in a
2082 register, 1 if it must be returned in memory. */
2085 arm_use_struct_convention (int gcc_p
, struct type
*type
)
2088 enum type_code code
;
2090 CHECK_TYPEDEF (type
);
2092 /* In the ARM ABI, "integer" like aggregate types are returned in
2093 registers. For an aggregate type to be integer like, its size
2094 must be less than or equal to DEPRECATED_REGISTER_SIZE and the
2095 offset of each addressable subfield must be zero. Note that bit
2096 fields are not addressable, and all addressable subfields of
2097 unions always start at offset zero.
2099 This function is based on the behaviour of GCC 2.95.1.
2100 See: gcc/arm.c: arm_return_in_memory() for details.
2102 Note: All versions of GCC before GCC 2.95.2 do not set up the
2103 parameters correctly for a function returning the following
2104 structure: struct { float f;}; This should be returned in memory,
2105 not a register. Richard Earnshaw sent me a patch, but I do not
2106 know of any way to detect if a function like the above has been
2107 compiled with the correct calling convention. */
2109 /* All aggregate types that won't fit in a register must be returned
2111 if (TYPE_LENGTH (type
) > DEPRECATED_REGISTER_SIZE
)
2116 /* The only aggregate types that can be returned in a register are
2117 structs and unions. Arrays must be returned in memory. */
2118 code
= TYPE_CODE (type
);
2119 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2124 /* Assume all other aggregate types can be returned in a register.
2125 Run a check for structures, unions and arrays. */
2128 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2131 /* Need to check if this struct/union is "integer" like. For
2132 this to be true, its size must be less than or equal to
2133 DEPRECATED_REGISTER_SIZE and the offset of each addressable
2134 subfield must be zero. Note that bit fields are not
2135 addressable, and unions always start at offset zero. If any
2136 of the subfields is a floating point type, the struct/union
2137 cannot be an integer type. */
2139 /* For each field in the object, check:
2140 1) Is it FP? --> yes, nRc = 1;
2141 2) Is it addressable (bitpos != 0) and
2142 not packed (bitsize == 0)?
2146 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2148 enum type_code field_type_code
;
2149 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, i
)));
2151 /* Is it a floating point type field? */
2152 if (field_type_code
== TYPE_CODE_FLT
)
2158 /* If bitpos != 0, then we have to care about it. */
2159 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2161 /* Bitfields are not addressable. If the field bitsize is
2162 zero, then the field is not packed. Hence it cannot be
2163 a bitfield or any other packed type. */
2164 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2176 /* Write into appropriate registers a function return value of type
2177 TYPE, given in virtual format. */
2180 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
2183 const bfd_byte
*valbuf
= src
;
2185 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2187 char buf
[MAX_REGISTER_SIZE
];
2189 switch (arm_get_fp_model (current_gdbarch
))
2193 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
);
2194 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
2197 case ARM_FLOAT_SOFT_FPA
:
2198 case ARM_FLOAT_SOFT_VFP
:
2199 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
2200 if (TYPE_LENGTH (type
) > 4)
2201 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
2202 valbuf
+ INT_REGISTER_SIZE
);
2207 (__FILE__
, __LINE__
,
2208 _("arm_store_return_value: Floating point model not supported"));
2212 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2213 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2214 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2215 || TYPE_CODE (type
) == TYPE_CODE_PTR
2216 || TYPE_CODE (type
) == TYPE_CODE_REF
2217 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2219 if (TYPE_LENGTH (type
) <= 4)
2221 /* Values of one word or less are zero/sign-extended and
2223 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2224 LONGEST val
= unpack_long (type
, valbuf
);
2226 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, val
);
2227 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
2231 /* Integral values greater than one word are stored in consecutive
2232 registers starting with r0. This will always be a multiple of
2233 the regiser size. */
2234 int len
= TYPE_LENGTH (type
);
2235 int regno
= ARM_A1_REGNUM
;
2239 regcache_cooked_write (regs
, regno
++, valbuf
);
2240 len
-= INT_REGISTER_SIZE
;
2241 valbuf
+= INT_REGISTER_SIZE
;
2247 /* For a structure or union the behaviour is as if the value had
2248 been stored to word-aligned memory and then loaded into
2249 registers with 32-bit load instruction(s). */
2250 int len
= TYPE_LENGTH (type
);
2251 int regno
= ARM_A1_REGNUM
;
2252 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2256 memcpy (tmpbuf
, valbuf
,
2257 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2258 regcache_cooked_write (regs
, regno
++, tmpbuf
);
2259 len
-= INT_REGISTER_SIZE
;
2260 valbuf
+= INT_REGISTER_SIZE
;
2266 arm_get_longjmp_target (CORE_ADDR
*pc
)
2269 char buf
[INT_REGISTER_SIZE
];
2270 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2272 jb_addr
= read_register (ARM_A1_REGNUM
);
2274 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2278 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
);
2282 /* Return non-zero if the PC is inside a thumb call thunk. */
2285 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2287 CORE_ADDR start_addr
;
2289 /* Find the starting address of the function containing the PC. If
2290 the caller didn't give us a name, look it up at the same time. */
2291 if (0 == find_pc_partial_function (pc
, name
? NULL
: &name
,
2295 return strncmp (name
, "_call_via_r", 11) == 0;
2298 /* If PC is in a Thumb call or return stub, return the address of the
2299 target PC, which is in a register. The thunk functions are called
2300 _called_via_xx, where x is the register name. The possible names
2301 are r0-r9, sl, fp, ip, sp, and lr. */
2304 arm_skip_stub (CORE_ADDR pc
)
2307 CORE_ADDR start_addr
;
2309 /* Find the starting address and name of the function containing the PC. */
2310 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2313 /* Call thunks always start with "_call_via_". */
2314 if (strncmp (name
, "_call_via_", 10) == 0)
2316 /* Use the name suffix to determine which register contains the
2318 static char *table
[15] =
2319 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2320 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2324 for (regno
= 0; regno
<= 14; regno
++)
2325 if (strcmp (&name
[10], table
[regno
]) == 0)
2326 return read_register (regno
);
2329 return 0; /* not a stub */
2333 set_arm_command (char *args
, int from_tty
)
2335 printf_unfiltered (_("\
2336 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2337 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
2341 show_arm_command (char *args
, int from_tty
)
2343 cmd_show_list (showarmcmdlist
, from_tty
, "");
2346 enum arm_float_model
2347 arm_get_fp_model (struct gdbarch
*gdbarch
)
2349 if (arm_fp_model
== ARM_FLOAT_AUTO
)
2350 return gdbarch_tdep (gdbarch
)->fp_model
;
2352 return arm_fp_model
;
2356 arm_set_fp (struct gdbarch
*gdbarch
)
2358 enum arm_float_model fp_model
= arm_get_fp_model (gdbarch
);
2360 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
2361 && (fp_model
== ARM_FLOAT_SOFT_FPA
|| fp_model
== ARM_FLOAT_FPA
))
2363 set_gdbarch_double_format (gdbarch
,
2364 &floatformat_ieee_double_littlebyte_bigword
);
2365 set_gdbarch_long_double_format
2366 (gdbarch
, &floatformat_ieee_double_littlebyte_bigword
);
2370 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_little
);
2371 set_gdbarch_long_double_format (gdbarch
,
2372 &floatformat_ieee_double_little
);
2377 set_fp_model_sfunc (char *args
, int from_tty
,
2378 struct cmd_list_element
*c
)
2380 enum arm_float_model fp_model
;
2382 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
2383 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
2385 arm_fp_model
= fp_model
;
2389 if (fp_model
== ARM_FLOAT_LAST
)
2390 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
2393 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2394 arm_set_fp (current_gdbarch
);
2398 show_fp_model (char *args
, int from_tty
,
2399 struct cmd_list_element
*c
)
2401 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2403 if (arm_fp_model
== ARM_FLOAT_AUTO
2404 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2405 /* i18n: "the default [floating point model] for the current ABI..." */
2406 printf_filtered (_(" - the default for the current ABI is \"%s\".\n"),
2407 fp_model_strings
[tdep
->fp_model
]);
2410 /* If the user changes the register disassembly style used for info
2411 register and other commands, we have to also switch the style used
2412 in opcodes for disassembly output. This function is run in the "set
2413 arm disassembly" command, and does that. */
2416 set_disassembly_style_sfunc (char *args
, int from_tty
,
2417 struct cmd_list_element
*c
)
2419 set_disassembly_style ();
2422 /* Return the ARM register name corresponding to register I. */
2424 arm_register_name (int i
)
2426 return arm_register_names
[i
];
2430 set_disassembly_style (void)
2432 const char *setname
, *setdesc
, **regnames
;
2435 /* Find the style that the user wants in the opcodes table. */
2437 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2438 while ((disassembly_style
!= setname
)
2439 && (current
< num_disassembly_options
))
2440 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2441 current_option
= current
;
2443 /* Fill our copy. */
2444 for (j
= 0; j
< numregs
; j
++)
2445 arm_register_names
[j
] = (char *) regnames
[j
];
2448 if (isupper (*regnames
[ARM_PC_REGNUM
]))
2450 arm_register_names
[ARM_FPS_REGNUM
] = "FPS";
2451 arm_register_names
[ARM_PS_REGNUM
] = "CPSR";
2455 arm_register_names
[ARM_FPS_REGNUM
] = "fps";
2456 arm_register_names
[ARM_PS_REGNUM
] = "cpsr";
2459 /* Synchronize the disassembler. */
2460 set_arm_regname_option (current
);
2463 /* arm_othernames implements the "othernames" command. This is deprecated
2464 by the "set arm disassembly" command. */
2467 arm_othernames (char *names
, int n
)
2469 /* Circle through the various flavors. */
2470 current_option
= (current_option
+ 1) % num_disassembly_options
;
2472 disassembly_style
= valid_disassembly_styles
[current_option
];
2473 set_disassembly_style ();
2476 /* Test whether the coff symbol specific value corresponds to a Thumb
2480 coff_sym_is_thumb (int val
)
2482 return (val
== C_THUMBEXT
||
2483 val
== C_THUMBSTAT
||
2484 val
== C_THUMBEXTFUNC
||
2485 val
== C_THUMBSTATFUNC
||
2486 val
== C_THUMBLABEL
);
2489 /* arm_coff_make_msymbol_special()
2490 arm_elf_make_msymbol_special()
2492 These functions test whether the COFF or ELF symbol corresponds to
2493 an address in thumb code, and set a "special" bit in a minimal
2494 symbol to indicate that it does. */
2497 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2499 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2501 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2503 MSYMBOL_SET_SPECIAL (msym
);
2507 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2509 if (coff_sym_is_thumb (val
))
2510 MSYMBOL_SET_SPECIAL (msym
);
2514 arm_write_pc (CORE_ADDR pc
, ptid_t ptid
)
2516 write_register_pid (ARM_PC_REGNUM
, pc
, ptid
);
2518 /* If necessary, set the T bit. */
2521 CORE_ADDR val
= read_register_pid (ARM_PS_REGNUM
, ptid
);
2522 if (arm_pc_is_thumb (pc
))
2523 write_register_pid (ARM_PS_REGNUM
, val
| 0x20, ptid
);
2525 write_register_pid (ARM_PS_REGNUM
, val
& ~(CORE_ADDR
) 0x20, ptid
);
2529 static enum gdb_osabi
2530 arm_elf_osabi_sniffer (bfd
*abfd
)
2532 unsigned int elfosabi
, eflags
;
2533 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2535 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2540 /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the
2541 file are conforming to the base specification for that machine
2542 (there are no OS-specific extensions). In order to determine the
2543 real OS in use we must look for OS notes that have been added. */
2544 bfd_map_over_sections (abfd
,
2545 generic_elf_osabi_sniff_abi_tag_sections
,
2547 if (osabi
== GDB_OSABI_UNKNOWN
)
2549 /* Existing ARM tools don't set this field, so look at the EI_FLAGS
2550 field for more information. */
2551 eflags
= EF_ARM_EABI_VERSION(elf_elfheader(abfd
)->e_flags
);
2554 case EF_ARM_EABI_VER1
:
2555 osabi
= GDB_OSABI_ARM_EABI_V1
;
2558 case EF_ARM_EABI_VER2
:
2559 osabi
= GDB_OSABI_ARM_EABI_V2
;
2562 case EF_ARM_EABI_UNKNOWN
:
2563 /* Assume GNU tools. */
2564 osabi
= GDB_OSABI_ARM_APCS
;
2568 internal_error (__FILE__
, __LINE__
,
2570 arm_elf_osabi_sniffer: Unknown ARM EABI version 0x%x"),
2577 /* GNU tools use this value. Check note sections in this case,
2579 bfd_map_over_sections (abfd
,
2580 generic_elf_osabi_sniff_abi_tag_sections
,
2582 if (osabi
== GDB_OSABI_UNKNOWN
)
2584 /* Assume APCS ABI. */
2585 osabi
= GDB_OSABI_ARM_APCS
;
2589 case ELFOSABI_FREEBSD
:
2590 osabi
= GDB_OSABI_FREEBSD_ELF
;
2593 case ELFOSABI_NETBSD
:
2594 osabi
= GDB_OSABI_NETBSD_ELF
;
2597 case ELFOSABI_LINUX
:
2598 osabi
= GDB_OSABI_LINUX
;
2606 /* Initialize the current architecture based on INFO. If possible,
2607 re-use an architecture from ARCHES, which is a list of
2608 architectures already created during this debugging session.
2610 Called e.g. at program startup, when reading a core file, and when
2611 reading a binary file. */
2613 static struct gdbarch
*
2614 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2616 struct gdbarch_tdep
*tdep
;
2617 struct gdbarch
*gdbarch
;
2619 /* Try to deterimine the ABI of the object we are loading. */
2621 if (info
.abfd
!= NULL
&& info
.osabi
== GDB_OSABI_UNKNOWN
)
2623 switch (bfd_get_flavour (info
.abfd
))
2625 case bfd_target_aout_flavour
:
2626 /* Assume it's an old APCS-style ABI. */
2627 info
.osabi
= GDB_OSABI_ARM_APCS
;
2630 case bfd_target_coff_flavour
:
2631 /* Assume it's an old APCS-style ABI. */
2633 info
.osabi
= GDB_OSABI_ARM_APCS
;
2637 /* Leave it as "unknown". */
2642 /* If there is already a candidate, use it. */
2643 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2645 return arches
->gdbarch
;
2647 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
2648 gdbarch
= gdbarch_alloc (&info
, tdep
);
2650 /* We used to default to FPA for generic ARM, but almost nobody uses that
2651 now, and we now provide a way for the user to force the model. So
2652 default to the most useful variant. */
2653 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
2656 switch (info
.byte_order
)
2658 case BFD_ENDIAN_BIG
:
2659 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
2660 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
2661 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
2662 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
2666 case BFD_ENDIAN_LITTLE
:
2667 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
2668 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
2669 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
2670 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
2675 internal_error (__FILE__
, __LINE__
,
2676 _("arm_gdbarch_init: bad byte order for float format"));
2679 /* On ARM targets char defaults to unsigned. */
2680 set_gdbarch_char_signed (gdbarch
, 0);
2682 /* This should be low enough for everything. */
2683 tdep
->lowest_pc
= 0x20;
2684 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
2686 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
2688 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
2690 /* Frame handling. */
2691 set_gdbarch_unwind_dummy_id (gdbarch
, arm_unwind_dummy_id
);
2692 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
2693 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
2695 frame_base_set_default (gdbarch
, &arm_normal_base
);
2697 /* Address manipulation. */
2698 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
2699 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
2701 /* Advance PC across function entry code. */
2702 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
2704 /* Get the PC when a frame might not be available. */
2705 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
, arm_saved_pc_after_call
);
2707 /* The stack grows downward. */
2708 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2710 /* Breakpoint manipulation. */
2711 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
2713 /* Information about registers, etc. */
2714 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
2715 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
2716 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
2717 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
2718 set_gdbarch_deprecated_register_byte (gdbarch
, arm_register_byte
);
2719 set_gdbarch_num_regs (gdbarch
, NUM_GREGS
+ NUM_FREGS
+ NUM_SREGS
);
2720 set_gdbarch_register_type (gdbarch
, arm_register_type
);
2722 /* Internal <-> external register number maps. */
2723 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
2725 /* Integer registers are 4 bytes. */
2726 set_gdbarch_deprecated_register_size (gdbarch
, 4);
2727 set_gdbarch_register_name (gdbarch
, arm_register_name
);
2729 /* Returning results. */
2730 set_gdbarch_extract_return_value (gdbarch
, arm_extract_return_value
);
2731 set_gdbarch_store_return_value (gdbarch
, arm_store_return_value
);
2732 set_gdbarch_deprecated_use_struct_convention (gdbarch
, arm_use_struct_convention
);
2733 set_gdbarch_deprecated_extract_struct_value_address (gdbarch
, arm_extract_struct_value_address
);
2735 /* Single stepping. */
2736 /* XXX For an RDI target we should ask the target if it can single-step. */
2737 set_gdbarch_software_single_step (gdbarch
, arm_software_single_step
);
2740 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
2742 /* Minsymbol frobbing. */
2743 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
2744 set_gdbarch_coff_make_msymbol_special (gdbarch
,
2745 arm_coff_make_msymbol_special
);
2747 /* Hook in the ABI-specific overrides, if they have been registered. */
2748 gdbarch_init_osabi (info
, gdbarch
);
2750 /* Add some default predicates. */
2751 frame_unwind_append_sniffer (gdbarch
, arm_sigtramp_unwind_sniffer
);
2752 frame_unwind_append_sniffer (gdbarch
, arm_prologue_unwind_sniffer
);
2754 /* Now we have tuned the configuration, set a few final things,
2755 based on what the OS ABI has told us. */
2757 if (tdep
->jb_pc
>= 0)
2758 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
2760 /* Floating point sizes and format. */
2761 switch (info
.byte_order
)
2763 case BFD_ENDIAN_BIG
:
2764 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
2765 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_big
);
2766 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
2770 case BFD_ENDIAN_LITTLE
:
2771 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
2772 arm_set_fp (gdbarch
);
2776 internal_error (__FILE__
, __LINE__
,
2777 _("arm_gdbarch_init: bad byte order for float format"));
2784 arm_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
2786 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2791 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
2792 (unsigned long) tdep
->lowest_pc
);
2796 arm_init_abi_eabi_v1 (struct gdbarch_info info
,
2797 struct gdbarch
*gdbarch
)
2803 arm_init_abi_eabi_v2 (struct gdbarch_info info
,
2804 struct gdbarch
*gdbarch
)
2810 arm_init_abi_apcs (struct gdbarch_info info
,
2811 struct gdbarch
*gdbarch
)
2816 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
2819 _initialize_arm_tdep (void)
2821 struct ui_file
*stb
;
2823 struct cmd_list_element
*new_set
, *new_show
;
2824 const char *setname
;
2825 const char *setdesc
;
2826 const char **regnames
;
2828 static char *helptext
;
2829 char regdesc
[1024], *rdptr
= regdesc
;
2830 size_t rest
= sizeof (regdesc
);
2832 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
2834 /* Register an ELF OS ABI sniffer for ARM binaries. */
2835 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
2836 bfd_target_elf_flavour
,
2837 arm_elf_osabi_sniffer
);
2839 /* Register some ABI variants for embedded systems. */
2840 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_EABI_V1
,
2841 arm_init_abi_eabi_v1
);
2842 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_EABI_V2
,
2843 arm_init_abi_eabi_v2
);
2844 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_APCS
,
2847 /* Get the number of possible sets of register names defined in opcodes. */
2848 num_disassembly_options
= get_arm_regname_num_options ();
2850 /* Add root prefix command for all "set arm"/"show arm" commands. */
2851 add_prefix_cmd ("arm", no_class
, set_arm_command
,
2852 _("Various ARM-specific commands."),
2853 &setarmcmdlist
, "set arm ", 0, &setlist
);
2855 add_prefix_cmd ("arm", no_class
, show_arm_command
,
2856 _("Various ARM-specific commands."),
2857 &showarmcmdlist
, "show arm ", 0, &showlist
);
2859 /* Sync the opcode insn printer with our register viewer. */
2860 parse_arm_disassembler_option ("reg-names-std");
2862 /* Initialize the array that will be passed to add_set_enum_cmd(). */
2863 valid_disassembly_styles
2864 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
2865 for (i
= 0; i
< num_disassembly_options
; i
++)
2867 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
2868 valid_disassembly_styles
[i
] = setname
;
2869 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
2872 /* Copy the default names (if found) and synchronize disassembler. */
2873 if (!strcmp (setname
, "std"))
2875 disassembly_style
= setname
;
2877 for (j
= 0; j
< numregs
; j
++)
2878 arm_register_names
[j
] = (char *) regnames
[j
];
2879 set_arm_regname_option (i
);
2882 /* Mark the end of valid options. */
2883 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
2885 /* Create the help text. */
2886 stb
= mem_fileopen ();
2887 fprintf_unfiltered (stb
, "%s%s%s",
2888 _("The valid values are:\n"),
2890 _("The default is \"std\"."));
2891 helptext
= ui_file_xstrdup (stb
, &length
);
2892 ui_file_delete (stb
);
2894 /* Add the deprecated disassembly-flavor command. */
2895 add_setshow_enum_cmd("disassembly-flavor", no_class
,
2896 valid_disassembly_styles
,
2898 _("Set the disassembly style."),
2899 _("Show the disassembly style."),
2901 _("The disassembly style is \"%s\"."),
2902 set_disassembly_style_sfunc
, NULL
,
2903 &setlist
, &showlist
, &new_set
, &new_show
);
2904 deprecate_cmd (new_set
, "set arm disassembly");
2905 deprecate_cmd (new_show
, "show arm disassembly");
2907 /* And now add the new interface. */
2908 add_setshow_enum_cmd("disassembler", no_class
,
2909 valid_disassembly_styles
, &disassembly_style
,
2910 _("Set the disassembly style."),
2911 _("Show the disassembly style."),
2913 _("The disassembly style is \"%s\"."),
2914 set_disassembly_style_sfunc
, NULL
,
2915 &setarmcmdlist
, &showarmcmdlist
, NULL
, NULL
);
2917 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
2918 _("Set usage of ARM 32-bit mode."),
2919 _("Show usage of ARM 32-bit mode."),
2920 _("When off, a 26-bit PC will be used."),
2921 _("Usage of ARM 32-bit mode is %s."),
2923 &setarmcmdlist
, &showarmcmdlist
);
2925 /* Add a command to allow the user to force the FPU model. */
2926 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
2927 _("Set the floating point type."),
2928 _("Show the floating point type."),
2929 _("auto - Determine the FP typefrom the OS-ABI.\n\
2930 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
2931 fpa - FPA co-processor (GCC compiled).\n\
2932 softvfp - Software FP with pure-endian doubles.\n\
2933 vfp - VFP co-processor."),
2934 _("The floating point type is \"%s\"."),
2935 set_fp_model_sfunc
, show_fp_model
,
2936 &setarmcmdlist
, &showarmcmdlist
, NULL
, NULL
);
2938 /* Add the deprecated "othernames" command. */
2939 deprecate_cmd (add_com ("othernames", class_obscure
, arm_othernames
,
2940 _("Switch to the next set of register names.")),
2941 "set arm disassembly");
2943 /* Debugging flag. */
2944 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
2945 _("Set ARM debugging."),
2946 _("Show ARM debugging."),
2947 _("When on, arm-specific debugging is enabled."),
2948 _("ARM debugging is %s."),
2950 &setdebuglist
, &showdebuglist
);