1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 #include <ctype.h> /* XXX for isupper () */
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register styles. */
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
42 #include "gdb/sim-arm.h"
45 #include "coff/internal.h"
48 #include "gdb_assert.h"
52 /* Each OS has a different mechanism for accessing the various
53 registers stored in the sigcontext structure.
55 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
56 function pointer) which may be used to determine the addresses
57 of the various saved registers in the sigcontext structure.
59 For the ARM target, there are three parameters to this function.
60 The first is the pc value of the frame under consideration, the
61 second the stack pointer of this frame, and the last is the
62 register number to fetch.
64 If the tm.h file does not define this macro, then it's assumed that
65 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
68 When it comes time to multi-arching this code, see the identically
69 named machinery in ia64-tdep.c for an example of how it could be
70 done. It should not be necessary to modify the code below where
71 this macro is used. */
73 #ifdef SIGCONTEXT_REGISTER_ADDRESS
74 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
75 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
78 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
79 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
82 /* Macros for setting and testing a bit in a minimal symbol that marks
83 it as Thumb function. The MSB of the minimal symbol's "info" field
84 is used for this purpose. This field is already being used to store
85 the symbol size, so the assumption is that the symbol size cannot
88 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
89 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol.
90 MSYMBOL_SIZE Returns the size of the minimal symbol,
91 i.e. the "info" field with the "special" bit
94 #define MSYMBOL_SET_SPECIAL(msym) \
95 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
98 #define MSYMBOL_IS_SPECIAL(msym) \
99 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
101 #define MSYMBOL_SIZE(msym) \
102 ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
104 /* The list of available "set arm ..." and "show arm ..." commands. */
105 static struct cmd_list_element
*setarmcmdlist
= NULL
;
106 static struct cmd_list_element
*showarmcmdlist
= NULL
;
108 /* The type of floating-point to use. Keep this in sync with enum
109 arm_float_model, and the help string in _initialize_arm_tdep. */
110 static const char *fp_model_strings
[] =
119 /* A variable that can be configured by the user. */
120 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
121 static const char *current_fp_model
= "auto";
123 /* Number of different reg name sets (options). */
124 static int num_disassembly_options
;
126 /* We have more registers than the disassembler as gdb can print the value
127 of special registers as well.
128 The general register names are overwritten by whatever is being used by
129 the disassembler at the moment. We also adjust the case of cpsr and fps. */
131 /* Initial value: Register names used in ARM's ISA documentation. */
132 static char * arm_register_name_strings
[] =
133 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
134 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
135 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
136 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
137 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
138 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
139 "fps", "cpsr" }; /* 24 25 */
140 static char **arm_register_names
= arm_register_name_strings
;
142 /* Valid register name styles. */
143 static const char **valid_disassembly_styles
;
145 /* Disassembly style to use. Default to "std" register names. */
146 static const char *disassembly_style
;
147 /* Index to that option in the opcodes table. */
148 static int current_option
;
150 /* This is used to keep the bfd arch_info in sync with the disassembly
152 static void set_disassembly_style_sfunc(char *, int,
153 struct cmd_list_element
*);
154 static void set_disassembly_style (void);
156 static void convert_from_extended (const struct floatformat
*, const void *,
158 static void convert_to_extended (const struct floatformat
*, void *,
161 struct arm_prologue_cache
163 /* The stack pointer at the time this frame was created; i.e. the
164 caller's stack pointer when this function was called. It is used
165 to identify this frame. */
168 /* The frame base for this frame is just prev_sp + frame offset -
169 frame size. FRAMESIZE is the size of this stack frame, and
170 FRAMEOFFSET if the initial offset from the stack pointer (this
171 frame's stack pointer, not PREV_SP) to the frame base. */
176 /* The register used to hold the frame pointer for this frame. */
179 /* Saved register offsets. */
180 struct trad_frame_saved_reg
*saved_regs
;
183 /* Addresses for calling Thumb functions have the bit 0 set.
184 Here are some macros to test, set, or clear bit 0 of addresses. */
185 #define IS_THUMB_ADDR(addr) ((addr) & 1)
186 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
187 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
189 /* Set to true if the 32-bit mode is in use. */
193 /* Flag set by arm_fix_call_dummy that tells whether the target
194 function is a Thumb function. This flag is checked by
195 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
196 its use in valops.c) to pass the function address as an additional
199 static int target_is_thumb
;
201 /* Flag set by arm_fix_call_dummy that tells whether the calling
202 function is a Thumb function. This flag is checked by
203 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
205 static int caller_is_thumb
;
207 /* Determine if the program counter specified in MEMADDR is in a Thumb
211 arm_pc_is_thumb (CORE_ADDR memaddr
)
213 struct minimal_symbol
*sym
;
215 /* If bit 0 of the address is set, assume this is a Thumb address. */
216 if (IS_THUMB_ADDR (memaddr
))
219 /* Thumb functions have a "special" bit set in minimal symbols. */
220 sym
= lookup_minimal_symbol_by_pc (memaddr
);
223 return (MSYMBOL_IS_SPECIAL (sym
));
231 /* Determine if the program counter specified in MEMADDR is in a call
232 dummy being called from a Thumb function. */
235 arm_pc_is_thumb_dummy (CORE_ADDR memaddr
)
237 CORE_ADDR sp
= read_sp ();
239 /* FIXME: Until we switch for the new call dummy macros, this heuristic
240 is the best we can do. We are trying to determine if the pc is on
241 the stack, which (hopefully) will only happen in a call dummy.
242 We hope the current stack pointer is not so far alway from the dummy
243 frame location (true if we have not pushed large data structures or
244 gone too many levels deep) and that our 1024 is not enough to consider
245 code regions as part of the stack (true for most practical purposes). */
246 if (DEPRECATED_PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 1024))
247 return caller_is_thumb
;
252 /* Remove useless bits from addresses in a running program. */
254 arm_addr_bits_remove (CORE_ADDR val
)
257 return (val
& (arm_pc_is_thumb (val
) ? 0xfffffffe : 0xfffffffc));
259 return (val
& 0x03fffffc);
262 /* When reading symbols, we need to zap the low bit of the address,
263 which may be set to 1 for Thumb functions. */
265 arm_smash_text_address (CORE_ADDR val
)
270 /* Immediately after a function call, return the saved pc. Can't
271 always go through the frames for this because on some machines the
272 new frame is not set up until the new function executes some
276 arm_saved_pc_after_call (struct frame_info
*frame
)
278 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM
));
281 /* Determine whether the function invocation represented by FI has a
282 frame on the stack associated with it. If it does return zero,
283 otherwise return 1. */
286 arm_frameless_function_invocation (struct frame_info
*fi
)
288 CORE_ADDR func_start
, after_prologue
;
291 /* Sometimes we have functions that do a little setup (like saving the
292 vN registers with the stmdb instruction, but DO NOT set up a frame.
293 The symbol table will report this as a prologue. However, it is
294 important not to try to parse these partial frames as frames, or we
295 will get really confused.
297 So I will demand 3 instructions between the start & end of the
298 prologue before I call it a real prologue, i.e. at least
303 func_start
= (get_frame_func (fi
) + FUNCTION_START_OFFSET
);
304 after_prologue
= SKIP_PROLOGUE (func_start
);
306 /* There are some frameless functions whose first two instructions
307 follow the standard APCS form, in which case after_prologue will
308 be func_start + 8. */
310 frameless
= (after_prologue
< func_start
+ 12);
314 /* A typical Thumb prologue looks like this:
318 Sometimes the latter instruction may be replaced by:
326 or, on tpcs, like this:
333 There is always one instruction of three classes:
338 When we have found at least one of each class we are done with the prolog.
339 Note that the "sub sp, #NN" before the push does not count.
343 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
345 CORE_ADDR current_pc
;
347 bit 0 - push { rlist }
348 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
349 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
353 for (current_pc
= pc
;
354 current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40;
357 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
359 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
361 findmask
|= 1; /* push found */
363 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
366 if ((findmask
& 1) == 0) /* before push ? */
369 findmask
|= 4; /* add/sub sp found */
371 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
373 findmask
|= 2; /* setting of r7 found */
375 else if (insn
== 0x466f) /* mov r7, sp */
377 findmask
|= 2; /* setting of r7 found */
379 else if (findmask
== (4+2+1))
381 /* We have found one of each type of prologue instruction */
385 /* Something in the prolog that we don't care about or some
386 instruction from outside the prolog scheduled here for
394 /* Advance the PC across any function entry prologue instructions to
395 reach some "real" code.
397 The APCS (ARM Procedure Call Standard) defines the following
401 [stmfd sp!, {a1,a2,a3,a4}]
402 stmfd sp!, {...,fp,ip,lr,pc}
403 [stfe f7, [sp, #-12]!]
404 [stfe f6, [sp, #-12]!]
405 [stfe f5, [sp, #-12]!]
406 [stfe f4, [sp, #-12]!]
407 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
410 arm_skip_prologue (CORE_ADDR pc
)
414 CORE_ADDR func_addr
, func_end
= 0;
416 struct symtab_and_line sal
;
418 /* If we're in a dummy frame, don't even try to skip the prologue. */
419 if (DEPRECATED_PC_IN_CALL_DUMMY (pc
, 0, 0))
422 /* See what the symbol table says. */
424 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
428 /* Found a function. */
429 sym
= lookup_symbol (func_name
, NULL
, VAR_DOMAIN
, NULL
, NULL
);
430 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
432 /* Don't use this trick for assembly source files. */
433 sal
= find_pc_line (func_addr
, 0);
434 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
439 /* Check if this is Thumb code. */
440 if (arm_pc_is_thumb (pc
))
441 return thumb_skip_prologue (pc
, func_end
);
443 /* Can't find the prologue end in the symbol table, try it the hard way
444 by disassembling the instructions. */
446 /* Like arm_scan_prologue, stop no later than pc + 64. */
447 if (func_end
== 0 || func_end
> pc
+ 64)
450 for (skip_pc
= pc
; skip_pc
< func_end
; skip_pc
+= 4)
452 inst
= read_memory_integer (skip_pc
, 4);
454 /* "mov ip, sp" is no longer a required part of the prologue. */
455 if (inst
== 0xe1a0c00d) /* mov ip, sp */
458 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
461 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
464 /* Some prologues begin with "str lr, [sp, #-4]!". */
465 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
468 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
471 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
474 /* Any insns after this point may float into the code, if it makes
475 for better instruction scheduling, so we skip them only if we
476 find them, but still consider the function to be frame-ful. */
478 /* We may have either one sfmfd instruction here, or several stfe
479 insns, depending on the version of floating point code we
481 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
484 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
487 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
490 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
493 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
494 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
495 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
498 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
499 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
500 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
503 /* Un-recognized instruction; stop scanning. */
507 return skip_pc
; /* End of prologue */
511 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
512 This function decodes a Thumb function prologue to determine:
513 1) the size of the stack frame
514 2) which registers are saved on it
515 3) the offsets of saved regs
516 4) the offset from the stack pointer to the frame pointer
518 A typical Thumb function prologue would create this stack frame
519 (offsets relative to FP)
520 old SP -> 24 stack parameters
523 R7 -> 0 local variables (16 bytes)
524 SP -> -12 additional stack space (12 bytes)
525 The frame size would thus be 36 bytes, and the frame offset would be
526 12 bytes. The frame register is R7.
528 The comments for thumb_skip_prolog() describe the algorithm we use
529 to detect the end of the prolog. */
533 thumb_scan_prologue (CORE_ADDR prev_pc
, struct arm_prologue_cache
*cache
)
535 CORE_ADDR prologue_start
;
536 CORE_ADDR prologue_end
;
537 CORE_ADDR current_pc
;
538 /* Which register has been copied to register n? */
541 bit 0 - push { rlist }
542 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
543 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
548 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
550 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
552 if (sal
.line
== 0) /* no line info, use current PC */
553 prologue_end
= prev_pc
;
554 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
555 prologue_end
= sal
.end
; /* (probably means no prologue) */
558 /* We're in the boondocks: allow for
559 16 pushes, an add, and "mv fp,sp". */
560 prologue_end
= prologue_start
+ 40;
562 prologue_end
= min (prologue_end
, prev_pc
);
564 /* Initialize the saved register map. When register H is copied to
565 register L, we will put H in saved_reg[L]. */
566 for (i
= 0; i
< 16; i
++)
569 /* Search the prologue looking for instructions that set up the
570 frame pointer, adjust the stack pointer, and save registers.
571 Do this until all basic prolog instructions are found. */
573 cache
->framesize
= 0;
574 for (current_pc
= prologue_start
;
575 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
582 insn
= read_memory_unsigned_integer (current_pc
, 2);
584 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
587 findmask
|= 1; /* push found */
588 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
589 whether to save LR (R14). */
590 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
592 /* Calculate offsets of saved R0-R7 and LR. */
593 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
594 if (mask
& (1 << regno
))
596 cache
->framesize
+= 4;
597 cache
->saved_regs
[saved_reg
[regno
]].addr
= -cache
->framesize
;
598 /* Reset saved register map. */
599 saved_reg
[regno
] = regno
;
602 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
605 if ((findmask
& 1) == 0) /* before push? */
608 findmask
|= 4; /* add/sub sp found */
610 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
611 if (insn
& 0x80) /* is it signed? (==subtracting) */
613 cache
->frameoffset
+= offset
;
616 cache
->framesize
-= offset
;
618 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
620 findmask
|= 2; /* setting of r7 found */
621 cache
->framereg
= THUMB_FP_REGNUM
;
622 /* get scaled offset */
623 cache
->frameoffset
= (insn
& 0xff) << 2;
625 else if (insn
== 0x466f) /* mov r7, sp */
627 findmask
|= 2; /* setting of r7 found */
628 cache
->framereg
= THUMB_FP_REGNUM
;
629 cache
->frameoffset
= 0;
630 saved_reg
[THUMB_FP_REGNUM
] = ARM_SP_REGNUM
;
632 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
634 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
635 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
636 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
639 /* Something in the prolog that we don't care about or some
640 instruction from outside the prolog scheduled here for
646 /* This function decodes an ARM function prologue to determine:
647 1) the size of the stack frame
648 2) which registers are saved on it
649 3) the offsets of saved regs
650 4) the offset from the stack pointer to the frame pointer
651 This information is stored in the "extra" fields of the frame_info.
653 There are two basic forms for the ARM prologue. The fixed argument
654 function call will look like:
657 stmfd sp!, {fp, ip, lr, pc}
661 Which would create this stack frame (offsets relative to FP):
662 IP -> 4 (caller's stack)
663 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
664 -4 LR (return address in caller)
665 -8 IP (copy of caller's SP)
667 SP -> -28 Local variables
669 The frame size would thus be 32 bytes, and the frame offset would be
670 28 bytes. The stmfd call can also save any of the vN registers it
671 plans to use, which increases the frame size accordingly.
673 Note: The stored PC is 8 off of the STMFD instruction that stored it
674 because the ARM Store instructions always store PC + 8 when you read
677 A variable argument function call will look like:
680 stmfd sp!, {a1, a2, a3, a4}
681 stmfd sp!, {fp, ip, lr, pc}
684 Which would create this stack frame (offsets relative to FP):
685 IP -> 20 (caller's stack)
690 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
691 -4 LR (return address in caller)
692 -8 IP (copy of caller's SP)
694 SP -> -28 Local variables
696 The frame size would thus be 48 bytes, and the frame offset would be
699 There is another potential complication, which is that the optimizer
700 will try to separate the store of fp in the "stmfd" instruction from
701 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
702 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
704 Also, note, the original version of the ARM toolchain claimed that there
707 instruction at the end of the prologue. I have never seen GCC produce
708 this, and the ARM docs don't mention it. We still test for it below in
714 arm_scan_prologue (struct frame_info
*next_frame
, struct arm_prologue_cache
*cache
)
716 int regno
, sp_offset
, fp_offset
, ip_offset
;
717 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
718 CORE_ADDR prev_pc
= frame_pc_unwind (next_frame
);
720 /* Assume there is no frame until proven otherwise. */
721 cache
->framereg
= ARM_SP_REGNUM
;
722 cache
->framesize
= 0;
723 cache
->frameoffset
= 0;
725 /* Check for Thumb prologue. */
726 if (arm_pc_is_thumb (prev_pc
))
728 thumb_scan_prologue (prev_pc
, cache
);
732 /* Find the function prologue. If we can't find the function in
733 the symbol table, peek in the stack frame to find the PC. */
734 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
736 /* One way to find the end of the prologue (which works well
737 for unoptimized code) is to do the following:
739 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
742 prologue_end = prev_pc;
743 else if (sal.end < prologue_end)
744 prologue_end = sal.end;
746 This mechanism is very accurate so long as the optimizer
747 doesn't move any instructions from the function body into the
748 prologue. If this happens, sal.end will be the last
749 instruction in the first hunk of prologue code just before
750 the first instruction that the scheduler has moved from
751 the body to the prologue.
753 In order to make sure that we scan all of the prologue
754 instructions, we use a slightly less accurate mechanism which
755 may scan more than necessary. To help compensate for this
756 lack of accuracy, the prologue scanning loop below contains
757 several clauses which'll cause the loop to terminate early if
758 an implausible prologue instruction is encountered.
764 is a suitable endpoint since it accounts for the largest
765 possible prologue plus up to five instructions inserted by
768 if (prologue_end
> prologue_start
+ 64)
770 prologue_end
= prologue_start
+ 64; /* See above. */
775 /* We have no symbol information. Our only option is to assume this
776 function has a standard stack frame and the normal frame register.
777 Then, we can find the value of our frame pointer on entrance to
778 the callee (or at the present moment if this is the innermost frame).
779 The value stored there should be the address of the stmfd + 8. */
781 LONGEST return_value
;
783 frame_loc
= frame_unwind_register_unsigned (next_frame
, ARM_FP_REGNUM
);
784 if (!safe_read_memory_integer (frame_loc
, 4, &return_value
))
788 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
789 prologue_end
= prologue_start
+ 64; /* See above. */
793 if (prev_pc
< prologue_end
)
794 prologue_end
= prev_pc
;
796 /* Now search the prologue looking for instructions that set up the
797 frame pointer, adjust the stack pointer, and save registers.
799 Be careful, however, and if it doesn't look like a prologue,
800 don't try to scan it. If, for instance, a frameless function
801 begins with stmfd sp!, then we will tell ourselves there is
802 a frame, which will confuse stack traceback, as well as "finish"
803 and other operations that rely on a knowledge of the stack
806 In the APCS, the prologue should start with "mov ip, sp" so
807 if we don't see this as the first insn, we will stop.
809 [Note: This doesn't seem to be true any longer, so it's now an
810 optional part of the prologue. - Kevin Buettner, 2001-11-20]
812 [Note further: The "mov ip,sp" only seems to be missing in
813 frameless functions at optimization level "-O2" or above,
814 in which case it is often (but not always) replaced by
815 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
817 sp_offset
= fp_offset
= ip_offset
= 0;
819 for (current_pc
= prologue_start
;
820 current_pc
< prologue_end
;
823 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
825 if (insn
== 0xe1a0c00d) /* mov ip, sp */
830 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
832 unsigned imm
= insn
& 0xff; /* immediate value */
833 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
834 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
838 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
840 unsigned imm
= insn
& 0xff; /* immediate value */
841 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
842 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
846 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
849 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= sp_offset
;
852 else if ((insn
& 0xffff0000) == 0xe92d0000)
853 /* stmfd sp!, {..., fp, ip, lr, pc}
855 stmfd sp!, {a1, a2, a3, a4} */
857 int mask
= insn
& 0xffff;
859 /* Calculate offsets of saved registers. */
860 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
861 if (mask
& (1 << regno
))
864 cache
->saved_regs
[regno
].addr
= sp_offset
;
867 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
868 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
869 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
871 /* No need to add this to saved_regs -- it's just an arg reg. */
874 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
875 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
876 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
878 /* No need to add this to saved_regs -- it's just an arg reg. */
881 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
883 unsigned imm
= insn
& 0xff; /* immediate value */
884 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
885 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
886 fp_offset
= -imm
+ ip_offset
;
887 cache
->framereg
= ARM_FP_REGNUM
;
889 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
891 unsigned imm
= insn
& 0xff; /* immediate value */
892 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
893 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
896 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
899 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
900 cache
->saved_regs
[regno
].addr
= sp_offset
;
902 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
905 unsigned int fp_start_reg
, fp_bound_reg
;
907 if ((insn
& 0x800) == 0x800) /* N0 is set */
909 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
916 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
922 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
923 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
924 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
927 cache
->saved_regs
[fp_start_reg
++].addr
= sp_offset
;
930 else if ((insn
& 0xf0000000) != 0xe0000000)
931 break; /* Condition not true, exit early */
932 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
933 break; /* Don't scan past a block load */
935 /* The optimizer might shove anything into the prologue,
936 so we just skip what we don't recognize. */
940 /* The frame size is just the negative of the offset (from the
941 original SP) of the last thing thing we pushed on the stack.
942 The frame offset is [new FP] - [new SP]. */
943 cache
->framesize
= -sp_offset
;
944 if (cache
->framereg
== ARM_FP_REGNUM
)
945 cache
->frameoffset
= fp_offset
- sp_offset
;
947 cache
->frameoffset
= 0;
950 static struct arm_prologue_cache
*
951 arm_make_prologue_cache (struct frame_info
*next_frame
)
954 struct arm_prologue_cache
*cache
;
955 CORE_ADDR unwound_fp
;
957 cache
= frame_obstack_zalloc (sizeof (struct arm_prologue_cache
));
958 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
960 arm_scan_prologue (next_frame
, cache
);
962 unwound_fp
= frame_unwind_register_unsigned (next_frame
, cache
->framereg
);
966 cache
->prev_sp
= unwound_fp
+ cache
->framesize
- cache
->frameoffset
;
968 /* Calculate actual addresses of saved registers using offsets
969 determined by arm_scan_prologue. */
970 for (reg
= 0; reg
< NUM_REGS
; reg
++)
971 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
972 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
977 /* Our frame ID for a normal frame is the current function's starting PC
978 and the caller's SP when we were called. */
981 arm_prologue_this_id (struct frame_info
*next_frame
,
983 struct frame_id
*this_id
)
985 struct arm_prologue_cache
*cache
;
989 if (*this_cache
== NULL
)
990 *this_cache
= arm_make_prologue_cache (next_frame
);
993 func
= frame_func_unwind (next_frame
);
995 /* This is meant to halt the backtrace at "_start". Make sure we
996 don't halt it at a generic dummy frame. */
997 if (func
<= LOWEST_PC
|| deprecated_inside_entry_file (func
))
1000 /* If we've hit a wall, stop. */
1001 if (cache
->prev_sp
== 0)
1004 id
= frame_id_build (cache
->prev_sp
, func
);
1006 /* Check that we're not going round in circles with the same frame
1007 ID (but avoid applying the test to sentinel frames which do go
1008 round in circles). */
1009 if (frame_relative_level (next_frame
) >= 0
1010 && get_frame_type (next_frame
) == NORMAL_FRAME
1011 && frame_id_eq (get_frame_id (next_frame
), id
))
1018 arm_prologue_prev_register (struct frame_info
*next_frame
,
1022 enum lval_type
*lvalp
,
1027 struct arm_prologue_cache
*cache
;
1029 if (*this_cache
== NULL
)
1030 *this_cache
= arm_make_prologue_cache (next_frame
);
1031 cache
= *this_cache
;
1033 /* If we are asked to unwind the PC, then we need to return the LR
1034 instead. The saved value of PC points into this frame's
1035 prologue, not the next frame's resume location. */
1036 if (prev_regnum
== ARM_PC_REGNUM
)
1037 prev_regnum
= ARM_LR_REGNUM
;
1039 /* SP is generally not saved to the stack, but this frame is
1040 identified by NEXT_FRAME's stack pointer at the time of the call.
1041 The value was already reconstructed into PREV_SP. */
1042 if (prev_regnum
== ARM_SP_REGNUM
)
1046 store_unsigned_integer (valuep
, 4, cache
->prev_sp
);
1050 trad_frame_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
1051 optimized
, lvalp
, addrp
, realnump
, valuep
);
1054 struct frame_unwind arm_prologue_unwind
= {
1056 arm_prologue_this_id
,
1057 arm_prologue_prev_register
1060 static const struct frame_unwind
*
1061 arm_prologue_unwind_sniffer (struct frame_info
*next_frame
)
1063 return &arm_prologue_unwind
;
1067 arm_normal_frame_base (struct frame_info
*next_frame
, void **this_cache
)
1069 struct arm_prologue_cache
*cache
;
1071 if (*this_cache
== NULL
)
1072 *this_cache
= arm_make_prologue_cache (next_frame
);
1073 cache
= *this_cache
;
1075 return cache
->prev_sp
+ cache
->frameoffset
- cache
->framesize
;
1078 struct frame_base arm_normal_base
= {
1079 &arm_prologue_unwind
,
1080 arm_normal_frame_base
,
1081 arm_normal_frame_base
,
1082 arm_normal_frame_base
1085 static struct arm_prologue_cache
*
1086 arm_make_sigtramp_cache (struct frame_info
*next_frame
)
1088 struct arm_prologue_cache
*cache
;
1091 cache
= frame_obstack_zalloc (sizeof (struct arm_prologue_cache
));
1093 cache
->prev_sp
= frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
);
1095 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1097 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1098 cache
->saved_regs
[reg
].addr
1099 = SIGCONTEXT_REGISTER_ADDRESS (cache
->prev_sp
,
1100 frame_pc_unwind (next_frame
), reg
);
1102 /* FIXME: What about thumb mode? */
1103 cache
->framereg
= ARM_SP_REGNUM
;
1105 = read_memory_integer (cache
->saved_regs
[cache
->framereg
].addr
,
1106 REGISTER_RAW_SIZE (cache
->framereg
));
1112 arm_sigtramp_this_id (struct frame_info
*next_frame
,
1114 struct frame_id
*this_id
)
1116 struct arm_prologue_cache
*cache
;
1118 if (*this_cache
== NULL
)
1119 *this_cache
= arm_make_sigtramp_cache (next_frame
);
1120 cache
= *this_cache
;
1122 /* FIXME drow/2003-07-07: This isn't right if we single-step within
1123 the sigtramp frame; the PC should be the beginning of the trampoline. */
1124 *this_id
= frame_id_build (cache
->prev_sp
, frame_pc_unwind (next_frame
));
1128 arm_sigtramp_prev_register (struct frame_info
*next_frame
,
1132 enum lval_type
*lvalp
,
1137 struct arm_prologue_cache
*cache
;
1139 if (*this_cache
== NULL
)
1140 *this_cache
= arm_make_sigtramp_cache (next_frame
);
1141 cache
= *this_cache
;
1143 trad_frame_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
1144 optimized
, lvalp
, addrp
, realnump
, valuep
);
1147 struct frame_unwind arm_sigtramp_unwind
= {
1149 arm_sigtramp_this_id
,
1150 arm_sigtramp_prev_register
1153 static const struct frame_unwind
*
1154 arm_sigtramp_unwind_sniffer (struct frame_info
*next_frame
)
1156 /* Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare
1157 against the name of the function, the code below will have to be
1158 changed to first fetch the name of the function and then pass
1159 this name to PC_IN_SIGTRAMP. */
1161 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1162 && PC_IN_SIGTRAMP (frame_pc_unwind (next_frame
), (char *) 0))
1163 return &arm_sigtramp_unwind
;
1168 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1169 dummy frame. The frame ID's base needs to match the TOS value
1170 saved by save_dummy_frame_tos() and returned from
1171 arm_push_dummy_call, and the PC needs to match the dummy frame's
1174 static struct frame_id
1175 arm_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1177 return frame_id_build (frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
),
1178 frame_pc_unwind (next_frame
));
1181 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1182 be used to construct the previous frame's ID, after looking up the
1183 containing function). */
1186 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1189 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1190 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1194 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1196 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1199 /* Set the return address for a generic dummy frame. ARM uses the
1203 arm_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
1205 write_register (ARM_LR_REGNUM
, entry_point_address ());
1209 /* Push an empty stack frame, to record the current PC, etc. */
1212 arm_push_dummy_frame (void)
1214 CORE_ADDR old_sp
= read_register (ARM_SP_REGNUM
);
1215 CORE_ADDR sp
= old_sp
;
1216 CORE_ADDR fp
, prologue_start
;
1219 /* Push the two dummy prologue instructions in reverse order,
1220 so that they'll be in the correct low-to-high order in memory. */
1221 /* sub fp, ip, #4 */
1222 sp
= push_word (sp
, 0xe24cb004);
1223 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1224 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
1226 /* Push a pointer to the dummy prologue + 12, because when stm
1227 instruction stores the PC, it stores the address of the stm
1228 instruction itself plus 12. */
1229 fp
= sp
= push_word (sp
, prologue_start
+ 12);
1231 /* Push the processor status. */
1232 sp
= push_word (sp
, read_register (ARM_PS_REGNUM
));
1234 /* Push all 16 registers starting with r15. */
1235 for (regnum
= ARM_PC_REGNUM
; regnum
>= 0; regnum
--)
1236 sp
= push_word (sp
, read_register (regnum
));
1238 /* Update fp (for both Thumb and ARM) and sp. */
1239 write_register (ARM_FP_REGNUM
, fp
);
1240 write_register (THUMB_FP_REGNUM
, fp
);
1241 write_register (ARM_SP_REGNUM
, sp
);
1244 /* DEPRECATED_CALL_DUMMY_WORDS:
1245 This sequence of words is the instructions
1251 Note this is 12 bytes. */
1253 static LONGEST arm_call_dummy_words
[] =
1255 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
1258 /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy
1259 breakpoint to the proper address in the call dummy, so that
1260 `finish' after a stop in a call dummy works.
1262 FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an
1263 optimal solution, but the call to arm_fix_call_dummy is immediately
1264 followed by a call to call_function_by_hand, which is the only
1265 function where call_dummy_breakpoint_offset is actually used. */
1269 arm_set_call_dummy_breakpoint_offset (void)
1271 if (caller_is_thumb
)
1272 set_gdbarch_deprecated_call_dummy_breakpoint_offset (current_gdbarch
, 4);
1274 set_gdbarch_deprecated_call_dummy_breakpoint_offset (current_gdbarch
, 8);
1277 /* Fix up the call dummy, based on whether the processor is currently
1278 in Thumb or ARM mode, and whether the target function is Thumb or
1279 ARM. There are three different situations requiring three
1282 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1283 been copied into the dummy parameter to this function.
1284 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1285 "mov pc,r4" instruction patched to be a "bx r4" instead.
1286 * Thumb calling anything: uses the Thumb dummy defined below, which
1287 works for calling both ARM and Thumb functions.
1289 All three call dummies expect to receive the target function
1290 address in R4, with the low bit set if it's a Thumb function. */
1293 arm_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
1294 struct value
**args
, struct type
*type
, int gcc_p
)
1296 static short thumb_dummy
[4] =
1298 0xf000, 0xf801, /* bl label */
1299 0xdf18, /* swi 24 */
1300 0x4720, /* label: bx r4 */
1302 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
1304 /* Set flag indicating whether the current PC is in a Thumb function. */
1305 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
1306 arm_set_call_dummy_breakpoint_offset ();
1308 /* If the target function is Thumb, set the low bit of the function
1309 address. And if the CPU is currently in ARM mode, patch the
1310 second instruction of call dummy to use a BX instruction to
1311 switch to Thumb mode. */
1312 target_is_thumb
= arm_pc_is_thumb (fun
);
1313 if (target_is_thumb
)
1316 if (!caller_is_thumb
)
1317 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
1320 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1321 instead of the ARM one that's already been copied. This will
1322 work for both Thumb and ARM target functions. */
1323 if (caller_is_thumb
)
1327 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
1329 for (i
= 0; i
< len
; i
++)
1331 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1332 p
+= sizeof (thumb_dummy
[0]);
1336 /* Put the target address in r4; the call dummy will copy this to
1338 write_register (4, fun
);
1341 /* When arguments must be pushed onto the stack, they go on in reverse
1342 order. The code below implements a FILO (stack) to do this. */
1347 struct stack_item
*prev
;
1351 static struct stack_item
*
1352 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1354 struct stack_item
*si
;
1355 si
= xmalloc (sizeof (struct stack_item
));
1356 si
->data
= xmalloc (len
);
1359 memcpy (si
->data
, contents
, len
);
1363 static struct stack_item
*
1364 pop_stack_item (struct stack_item
*si
)
1366 struct stack_item
*dead
= si
;
1373 /* We currently only support passing parameters in integer registers. This
1374 conforms with GCC's default model. Several other variants exist and
1375 we should probably support some of them based on the selected ABI. */
1378 arm_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
1379 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1380 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1381 CORE_ADDR struct_addr
)
1386 struct stack_item
*si
= NULL
;
1388 /* Set the return address. For the ARM, the return breakpoint is
1389 always at BP_ADDR. */
1390 /* XXX Fix for Thumb. */
1391 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1393 /* Walk through the list of args and determine how large a temporary
1394 stack is required. Need to take care here as structs may be
1395 passed on the stack, and we have to to push them. */
1398 argreg
= ARM_A1_REGNUM
;
1401 /* Some platforms require a double-word aligned stack. Make sure sp
1402 is correctly aligned before we start. We always do this even if
1403 it isn't really needed -- it can never hurt things. */
1404 sp
&= ~(CORE_ADDR
)(2 * DEPRECATED_REGISTER_SIZE
- 1);
1406 /* The struct_return pointer occupies the first parameter
1407 passing register. */
1411 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = 0x%s\n",
1412 REGISTER_NAME (argreg
), paddr (struct_addr
));
1413 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1417 for (argnum
= 0; argnum
< nargs
; argnum
++)
1420 struct type
*arg_type
;
1421 struct type
*target_type
;
1422 enum type_code typecode
;
1425 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1426 len
= TYPE_LENGTH (arg_type
);
1427 target_type
= TYPE_TARGET_TYPE (arg_type
);
1428 typecode
= TYPE_CODE (arg_type
);
1429 val
= VALUE_CONTENTS (args
[argnum
]);
1431 /* If the argument is a pointer to a function, and it is a
1432 Thumb function, create a LOCAL copy of the value and set
1433 the THUMB bit in it. */
1434 if (TYPE_CODE_PTR
== typecode
1435 && target_type
!= NULL
1436 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1438 CORE_ADDR regval
= extract_unsigned_integer (val
, len
);
1439 if (arm_pc_is_thumb (regval
))
1442 store_unsigned_integer (val
, len
, MAKE_THUMB_ADDR (regval
));
1446 /* Copy the argument to general registers or the stack in
1447 register-sized pieces. Large arguments are split between
1448 registers and stack. */
1451 int partial_len
= len
< DEPRECATED_REGISTER_SIZE
? len
: DEPRECATED_REGISTER_SIZE
;
1453 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1455 /* The argument is being passed in a general purpose
1457 CORE_ADDR regval
= extract_unsigned_integer (val
, partial_len
);
1459 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1460 argnum
, REGISTER_NAME (argreg
),
1461 phex (regval
, DEPRECATED_REGISTER_SIZE
));
1462 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1467 /* Push the arguments onto the stack. */
1469 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1471 si
= push_stack_item (si
, val
, DEPRECATED_REGISTER_SIZE
);
1472 nstack
+= DEPRECATED_REGISTER_SIZE
;
1479 /* If we have an odd number of words to push, then decrement the stack
1480 by one word now, so first stack argument will be dword aligned. */
1487 write_memory (sp
, si
->data
, si
->len
);
1488 si
= pop_stack_item (si
);
1491 /* Finally, update teh SP register. */
1492 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1498 print_fpu_flags (int flags
)
1500 if (flags
& (1 << 0))
1501 fputs ("IVO ", stdout
);
1502 if (flags
& (1 << 1))
1503 fputs ("DVZ ", stdout
);
1504 if (flags
& (1 << 2))
1505 fputs ("OFL ", stdout
);
1506 if (flags
& (1 << 3))
1507 fputs ("UFL ", stdout
);
1508 if (flags
& (1 << 4))
1509 fputs ("INX ", stdout
);
1513 /* Print interesting information about the floating point processor
1514 (if present) or emulator. */
1516 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1517 struct frame_info
*frame
, const char *args
)
1519 unsigned long status
= read_register (ARM_FPS_REGNUM
);
1522 type
= (status
>> 24) & 127;
1523 printf ("%s FPU type %d\n",
1524 (status
& (1 << 31)) ? "Hardware" : "Software",
1526 fputs ("mask: ", stdout
);
1527 print_fpu_flags (status
>> 16);
1528 fputs ("flags: ", stdout
);
1529 print_fpu_flags (status
);
1532 /* Return the GDB type object for the "standard" data type of data in
1535 static struct type
*
1536 arm_register_type (int regnum
)
1538 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1540 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1541 return builtin_type_arm_ext_big
;
1543 return builtin_type_arm_ext_littlebyte_bigword
;
1546 return builtin_type_int32
;
1549 /* Index within `registers' of the first byte of the space for
1553 arm_register_byte (int regnum
)
1555 if (regnum
< ARM_F0_REGNUM
)
1556 return regnum
* INT_REGISTER_RAW_SIZE
;
1557 else if (regnum
< ARM_PS_REGNUM
)
1558 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1559 + (regnum
- ARM_F0_REGNUM
) * FP_REGISTER_RAW_SIZE
);
1561 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1562 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
1563 + (regnum
- ARM_FPS_REGNUM
) * STATUS_REGISTER_SIZE
);
1566 /* Number of bytes of storage in the actual machine representation for
1567 register N. All registers are 4 bytes, except fp0 - fp7, which are
1568 12 bytes in length. */
1571 arm_register_raw_size (int regnum
)
1573 if (regnum
< ARM_F0_REGNUM
)
1574 return INT_REGISTER_RAW_SIZE
;
1575 else if (regnum
< ARM_FPS_REGNUM
)
1576 return FP_REGISTER_RAW_SIZE
;
1578 return STATUS_REGISTER_SIZE
;
1581 /* Number of bytes of storage in a program's representation
1584 arm_register_virtual_size (int regnum
)
1586 if (regnum
< ARM_F0_REGNUM
)
1587 return INT_REGISTER_VIRTUAL_SIZE
;
1588 else if (regnum
< ARM_FPS_REGNUM
)
1589 return FP_REGISTER_VIRTUAL_SIZE
;
1591 return STATUS_REGISTER_SIZE
;
1594 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1596 arm_register_sim_regno (int regnum
)
1599 gdb_assert (reg
>= 0 && reg
< NUM_REGS
);
1601 if (reg
< NUM_GREGS
)
1602 return SIM_ARM_R0_REGNUM
+ reg
;
1605 if (reg
< NUM_FREGS
)
1606 return SIM_ARM_FP0_REGNUM
+ reg
;
1609 if (reg
< NUM_SREGS
)
1610 return SIM_ARM_FPS_REGNUM
+ reg
;
1613 internal_error (__FILE__
, __LINE__
, "Bad REGNUM %d", regnum
);
1616 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1617 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1618 It is thought that this is is the floating-point register format on
1619 little-endian systems. */
1622 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
1626 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1627 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1629 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1631 floatformat_from_doublest (fmt
, &d
, dbl
);
1635 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
)
1638 floatformat_to_doublest (fmt
, ptr
, &d
);
1639 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1640 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1642 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1647 condition_true (unsigned long cond
, unsigned long status_reg
)
1649 if (cond
== INST_AL
|| cond
== INST_NV
)
1655 return ((status_reg
& FLAG_Z
) != 0);
1657 return ((status_reg
& FLAG_Z
) == 0);
1659 return ((status_reg
& FLAG_C
) != 0);
1661 return ((status_reg
& FLAG_C
) == 0);
1663 return ((status_reg
& FLAG_N
) != 0);
1665 return ((status_reg
& FLAG_N
) == 0);
1667 return ((status_reg
& FLAG_V
) != 0);
1669 return ((status_reg
& FLAG_V
) == 0);
1671 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1673 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1675 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1677 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1679 return (((status_reg
& FLAG_Z
) == 0) &&
1680 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1682 return (((status_reg
& FLAG_Z
) != 0) ||
1683 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1688 /* Support routines for single stepping. Calculate the next PC value. */
1689 #define submask(x) ((1L << ((x) + 1)) - 1)
1690 #define bit(obj,st) (((obj) >> (st)) & 1)
1691 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1692 #define sbits(obj,st,fn) \
1693 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1694 #define BranchDest(addr,instr) \
1695 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1698 static unsigned long
1699 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1700 unsigned long status_reg
)
1702 unsigned long res
, shift
;
1703 int rm
= bits (inst
, 0, 3);
1704 unsigned long shifttype
= bits (inst
, 5, 6);
1708 int rs
= bits (inst
, 8, 11);
1709 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1712 shift
= bits (inst
, 7, 11);
1715 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1716 + (bit (inst
, 4) ? 12 : 8))
1717 : read_register (rm
));
1722 res
= shift
>= 32 ? 0 : res
<< shift
;
1726 res
= shift
>= 32 ? 0 : res
>> shift
;
1732 res
= ((res
& 0x80000000L
)
1733 ? ~((~res
) >> shift
) : res
>> shift
);
1736 case 3: /* ROR/RRX */
1739 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1741 res
= (res
>> shift
) | (res
<< (32 - shift
));
1745 return res
& 0xffffffff;
1748 /* Return number of 1-bits in VAL. */
1751 bitcount (unsigned long val
)
1754 for (nbits
= 0; val
!= 0; nbits
++)
1755 val
&= val
- 1; /* delete rightmost 1-bit in val */
1760 thumb_get_next_pc (CORE_ADDR pc
)
1762 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1763 unsigned short inst1
= read_memory_integer (pc
, 2);
1764 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1765 unsigned long offset
;
1767 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1771 /* Fetch the saved PC from the stack. It's stored above
1772 all of the other registers. */
1773 offset
= bitcount (bits (inst1
, 0, 7)) * DEPRECATED_REGISTER_SIZE
;
1774 sp
= read_register (ARM_SP_REGNUM
);
1775 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1776 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1778 error ("Infinite loop detected");
1780 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1782 unsigned long status
= read_register (ARM_PS_REGNUM
);
1783 unsigned long cond
= bits (inst1
, 8, 11);
1784 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1785 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1787 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1789 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1791 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1793 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1794 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1795 nextpc
= pc_val
+ offset
;
1802 arm_get_next_pc (CORE_ADDR pc
)
1804 unsigned long pc_val
;
1805 unsigned long this_instr
;
1806 unsigned long status
;
1809 if (arm_pc_is_thumb (pc
))
1810 return thumb_get_next_pc (pc
);
1812 pc_val
= (unsigned long) pc
;
1813 this_instr
= read_memory_integer (pc
, 4);
1814 status
= read_register (ARM_PS_REGNUM
);
1815 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1817 if (condition_true (bits (this_instr
, 28, 31), status
))
1819 switch (bits (this_instr
, 24, 27))
1822 case 0x1: /* data processing */
1826 unsigned long operand1
, operand2
, result
= 0;
1830 if (bits (this_instr
, 12, 15) != 15)
1833 if (bits (this_instr
, 22, 25) == 0
1834 && bits (this_instr
, 4, 7) == 9) /* multiply */
1835 error ("Illegal update to pc in instruction");
1837 /* Multiply into PC */
1838 c
= (status
& FLAG_C
) ? 1 : 0;
1839 rn
= bits (this_instr
, 16, 19);
1840 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1842 if (bit (this_instr
, 25))
1844 unsigned long immval
= bits (this_instr
, 0, 7);
1845 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1846 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1849 else /* operand 2 is a shifted register */
1850 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1852 switch (bits (this_instr
, 21, 24))
1855 result
= operand1
& operand2
;
1859 result
= operand1
^ operand2
;
1863 result
= operand1
- operand2
;
1867 result
= operand2
- operand1
;
1871 result
= operand1
+ operand2
;
1875 result
= operand1
+ operand2
+ c
;
1879 result
= operand1
- operand2
+ c
;
1883 result
= operand2
- operand1
+ c
;
1889 case 0xb: /* tst, teq, cmp, cmn */
1890 result
= (unsigned long) nextpc
;
1894 result
= operand1
| operand2
;
1898 /* Always step into a function. */
1903 result
= operand1
& ~operand2
;
1910 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1913 error ("Infinite loop detected");
1918 case 0x5: /* data transfer */
1921 if (bit (this_instr
, 20))
1924 if (bits (this_instr
, 12, 15) == 15)
1930 if (bit (this_instr
, 22))
1931 error ("Illegal update to pc in instruction");
1933 /* byte write to PC */
1934 rn
= bits (this_instr
, 16, 19);
1935 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1936 if (bit (this_instr
, 24))
1939 int c
= (status
& FLAG_C
) ? 1 : 0;
1940 unsigned long offset
=
1941 (bit (this_instr
, 25)
1942 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1943 : bits (this_instr
, 0, 11));
1945 if (bit (this_instr
, 23))
1950 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1953 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1956 error ("Infinite loop detected");
1962 case 0x9: /* block transfer */
1963 if (bit (this_instr
, 20))
1966 if (bit (this_instr
, 15))
1971 if (bit (this_instr
, 23))
1974 unsigned long reglist
= bits (this_instr
, 0, 14);
1975 offset
= bitcount (reglist
) * 4;
1976 if (bit (this_instr
, 24)) /* pre */
1979 else if (bit (this_instr
, 24))
1983 unsigned long rn_val
=
1984 read_register (bits (this_instr
, 16, 19));
1986 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1990 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1992 error ("Infinite loop detected");
1997 case 0xb: /* branch & link */
1998 case 0xa: /* branch */
2000 nextpc
= BranchDest (pc
, this_instr
);
2002 nextpc
= ADDR_BITS_REMOVE (nextpc
);
2004 error ("Infinite loop detected");
2010 case 0xe: /* coproc ops */
2015 fprintf_filtered (gdb_stderr
, "Bad bit-field extraction\n");
2023 /* single_step() is called just before we want to resume the inferior,
2024 if we want to single-step it but there is no hardware or kernel
2025 single-step support. We find the target of the coming instruction
2028 single_step() is also called just after the inferior stops. If we
2029 had set up a simulated single-step, we undo our damage. */
2032 arm_software_single_step (enum target_signal sig
, int insert_bpt
)
2034 static int next_pc
; /* State between setting and unsetting. */
2035 static char break_mem
[BREAKPOINT_MAX
]; /* Temporary storage for mem@bpt */
2039 next_pc
= arm_get_next_pc (read_register (ARM_PC_REGNUM
));
2040 target_insert_breakpoint (next_pc
, break_mem
);
2043 target_remove_breakpoint (next_pc
, break_mem
);
2046 #include "bfd-in2.h"
2047 #include "libcoff.h"
2050 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
2052 if (arm_pc_is_thumb (memaddr
))
2054 static asymbol
*asym
;
2055 static combined_entry_type ce
;
2056 static struct coff_symbol_struct csym
;
2057 static struct bfd fake_bfd
;
2058 static bfd_target fake_target
;
2060 if (csym
.native
== NULL
)
2062 /* Create a fake symbol vector containing a Thumb symbol.
2063 This is solely so that the code in print_insn_little_arm()
2064 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2065 the presence of a Thumb symbol and switch to decoding
2066 Thumb instructions. */
2068 fake_target
.flavour
= bfd_target_coff_flavour
;
2069 fake_bfd
.xvec
= &fake_target
;
2070 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
2072 csym
.symbol
.the_bfd
= &fake_bfd
;
2073 csym
.symbol
.name
= "fake";
2074 asym
= (asymbol
*) & csym
;
2077 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
2078 info
->symbols
= &asym
;
2081 info
->symbols
= NULL
;
2083 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2084 return print_insn_big_arm (memaddr
, info
);
2086 return print_insn_little_arm (memaddr
, info
);
2089 /* The following define instruction sequences that will cause ARM
2090 cpu's to take an undefined instruction trap. These are used to
2091 signal a breakpoint to GDB.
2093 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2094 modes. A different instruction is required for each mode. The ARM
2095 cpu's can also be big or little endian. Thus four different
2096 instructions are needed to support all cases.
2098 Note: ARMv4 defines several new instructions that will take the
2099 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2100 not in fact add the new instructions. The new undefined
2101 instructions in ARMv4 are all instructions that had no defined
2102 behaviour in earlier chips. There is no guarantee that they will
2103 raise an exception, but may be treated as NOP's. In practice, it
2104 may only safe to rely on instructions matching:
2106 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2107 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2108 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2110 Even this may only true if the condition predicate is true. The
2111 following use a condition predicate of ALWAYS so it is always TRUE.
2113 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2114 and NetBSD all use a software interrupt rather than an undefined
2115 instruction to force a trap. This can be handled by by the
2116 abi-specific code during establishment of the gdbarch vector. */
2119 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
2120 override these definitions. */
2121 #ifndef ARM_LE_BREAKPOINT
2122 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2124 #ifndef ARM_BE_BREAKPOINT
2125 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2127 #ifndef THUMB_LE_BREAKPOINT
2128 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
2130 #ifndef THUMB_BE_BREAKPOINT
2131 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
2134 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
2135 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
2136 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2137 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2139 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2140 the program counter value to determine whether a 16-bit or 32-bit
2141 breakpoint should be used. It returns a pointer to a string of
2142 bytes that encode a breakpoint instruction, stores the length of
2143 the string to *lenptr, and adjusts the program counter (if
2144 necessary) to point to the actual memory location where the
2145 breakpoint should be inserted. */
2147 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
2148 breakpoints and storing their handles instread of what was in
2149 memory. It is nice that this is the same size as a handle -
2150 otherwise remote-rdp will have to change. */
2152 static const unsigned char *
2153 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
2155 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2157 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
2159 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2160 *lenptr
= tdep
->thumb_breakpoint_size
;
2161 return tdep
->thumb_breakpoint
;
2165 *lenptr
= tdep
->arm_breakpoint_size
;
2166 return tdep
->arm_breakpoint
;
2170 /* Extract from an array REGBUF containing the (raw) register state a
2171 function return value of type TYPE, and copy that, in virtual
2172 format, into VALBUF. */
2175 arm_extract_return_value (struct type
*type
,
2176 struct regcache
*regs
,
2179 bfd_byte
*valbuf
= dst
;
2181 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2183 switch (arm_get_fp_model (current_gdbarch
))
2187 /* The value is in register F0 in internal format. We need to
2188 extract the raw value and then convert it to the desired
2190 bfd_byte tmpbuf
[FP_REGISTER_RAW_SIZE
];
2192 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
2193 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
2198 case ARM_FLOAT_SOFT_FPA
:
2199 case ARM_FLOAT_SOFT_VFP
:
2200 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
2201 if (TYPE_LENGTH (type
) > 4)
2202 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
2203 valbuf
+ INT_REGISTER_RAW_SIZE
);
2208 (__FILE__
, __LINE__
,
2209 "arm_extract_return_value: Floating point model not supported");
2213 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2214 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2215 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2216 || TYPE_CODE (type
) == TYPE_CODE_PTR
2217 || TYPE_CODE (type
) == TYPE_CODE_REF
2218 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2220 /* If the the type is a plain integer, then the access is
2221 straight-forward. Otherwise we have to play around a bit more. */
2222 int len
= TYPE_LENGTH (type
);
2223 int regno
= ARM_A1_REGNUM
;
2228 /* By using store_unsigned_integer we avoid having to do
2229 anything special for small big-endian values. */
2230 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2231 store_unsigned_integer (valbuf
,
2232 (len
> INT_REGISTER_RAW_SIZE
2233 ? INT_REGISTER_RAW_SIZE
: len
),
2235 len
-= INT_REGISTER_RAW_SIZE
;
2236 valbuf
+= INT_REGISTER_RAW_SIZE
;
2241 /* For a structure or union the behaviour is as if the value had
2242 been stored to word-aligned memory and then loaded into
2243 registers with 32-bit load instruction(s). */
2244 int len
= TYPE_LENGTH (type
);
2245 int regno
= ARM_A1_REGNUM
;
2246 bfd_byte tmpbuf
[INT_REGISTER_RAW_SIZE
];
2250 regcache_cooked_read (regs
, regno
++, tmpbuf
);
2251 memcpy (valbuf
, tmpbuf
,
2252 len
> INT_REGISTER_RAW_SIZE
? INT_REGISTER_RAW_SIZE
: len
);
2253 len
-= INT_REGISTER_RAW_SIZE
;
2254 valbuf
+= INT_REGISTER_RAW_SIZE
;
2259 /* Extract from an array REGBUF containing the (raw) register state
2260 the address in which a function should return its structure value. */
2263 arm_extract_struct_value_address (struct regcache
*regcache
)
2267 regcache_cooked_read_unsigned (regcache
, ARM_A1_REGNUM
, &ret
);
2271 /* Will a function return an aggregate type in memory or in a
2272 register? Return 0 if an aggregate type can be returned in a
2273 register, 1 if it must be returned in memory. */
2276 arm_use_struct_convention (int gcc_p
, struct type
*type
)
2279 enum type_code code
;
2281 /* In the ARM ABI, "integer" like aggregate types are returned in
2282 registers. For an aggregate type to be integer like, its size
2283 must be less than or equal to DEPRECATED_REGISTER_SIZE and the
2284 offset of each addressable subfield must be zero. Note that bit
2285 fields are not addressable, and all addressable subfields of
2286 unions always start at offset zero.
2288 This function is based on the behaviour of GCC 2.95.1.
2289 See: gcc/arm.c: arm_return_in_memory() for details.
2291 Note: All versions of GCC before GCC 2.95.2 do not set up the
2292 parameters correctly for a function returning the following
2293 structure: struct { float f;}; This should be returned in memory,
2294 not a register. Richard Earnshaw sent me a patch, but I do not
2295 know of any way to detect if a function like the above has been
2296 compiled with the correct calling convention. */
2298 /* All aggregate types that won't fit in a register must be returned
2300 if (TYPE_LENGTH (type
) > DEPRECATED_REGISTER_SIZE
)
2305 /* The only aggregate types that can be returned in a register are
2306 structs and unions. Arrays must be returned in memory. */
2307 code
= TYPE_CODE (type
);
2308 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2313 /* Assume all other aggregate types can be returned in a register.
2314 Run a check for structures, unions and arrays. */
2317 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2320 /* Need to check if this struct/union is "integer" like. For
2321 this to be true, its size must be less than or equal to
2322 DEPRECATED_REGISTER_SIZE and the offset of each addressable
2323 subfield must be zero. Note that bit fields are not
2324 addressable, and unions always start at offset zero. If any
2325 of the subfields is a floating point type, the struct/union
2326 cannot be an integer type. */
2328 /* For each field in the object, check:
2329 1) Is it FP? --> yes, nRc = 1;
2330 2) Is it addressable (bitpos != 0) and
2331 not packed (bitsize == 0)?
2335 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2337 enum type_code field_type_code
;
2338 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
2340 /* Is it a floating point type field? */
2341 if (field_type_code
== TYPE_CODE_FLT
)
2347 /* If bitpos != 0, then we have to care about it. */
2348 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2350 /* Bitfields are not addressable. If the field bitsize is
2351 zero, then the field is not packed. Hence it cannot be
2352 a bitfield or any other packed type. */
2353 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2365 /* Write into appropriate registers a function return value of type
2366 TYPE, given in virtual format. */
2369 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
2372 const bfd_byte
*valbuf
= src
;
2374 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2376 char buf
[ARM_MAX_REGISTER_RAW_SIZE
];
2378 switch (arm_get_fp_model (current_gdbarch
))
2382 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
);
2383 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
2386 case ARM_FLOAT_SOFT_FPA
:
2387 case ARM_FLOAT_SOFT_VFP
:
2388 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
2389 if (TYPE_LENGTH (type
) > 4)
2390 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
2391 valbuf
+ INT_REGISTER_RAW_SIZE
);
2396 (__FILE__
, __LINE__
,
2397 "arm_store_return_value: Floating point model not supported");
2401 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2402 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2403 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2404 || TYPE_CODE (type
) == TYPE_CODE_PTR
2405 || TYPE_CODE (type
) == TYPE_CODE_REF
2406 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2408 if (TYPE_LENGTH (type
) <= 4)
2410 /* Values of one word or less are zero/sign-extended and
2412 bfd_byte tmpbuf
[INT_REGISTER_RAW_SIZE
];
2413 LONGEST val
= unpack_long (type
, valbuf
);
2415 store_signed_integer (tmpbuf
, INT_REGISTER_RAW_SIZE
, val
);
2416 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
2420 /* Integral values greater than one word are stored in consecutive
2421 registers starting with r0. This will always be a multiple of
2422 the regiser size. */
2423 int len
= TYPE_LENGTH (type
);
2424 int regno
= ARM_A1_REGNUM
;
2428 regcache_cooked_write (regs
, regno
++, valbuf
);
2429 len
-= INT_REGISTER_RAW_SIZE
;
2430 valbuf
+= INT_REGISTER_RAW_SIZE
;
2436 /* For a structure or union the behaviour is as if the value had
2437 been stored to word-aligned memory and then loaded into
2438 registers with 32-bit load instruction(s). */
2439 int len
= TYPE_LENGTH (type
);
2440 int regno
= ARM_A1_REGNUM
;
2441 bfd_byte tmpbuf
[INT_REGISTER_RAW_SIZE
];
2445 memcpy (tmpbuf
, valbuf
,
2446 len
> INT_REGISTER_RAW_SIZE
? INT_REGISTER_RAW_SIZE
: len
);
2447 regcache_cooked_write (regs
, regno
++, tmpbuf
);
2448 len
-= INT_REGISTER_RAW_SIZE
;
2449 valbuf
+= INT_REGISTER_RAW_SIZE
;
2455 arm_get_longjmp_target (CORE_ADDR
*pc
)
2458 char buf
[INT_REGISTER_RAW_SIZE
];
2459 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2461 jb_addr
= read_register (ARM_A1_REGNUM
);
2463 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2464 INT_REGISTER_RAW_SIZE
))
2467 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_RAW_SIZE
);
2471 /* Return non-zero if the PC is inside a thumb call thunk. */
2474 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2476 CORE_ADDR start_addr
;
2478 /* Find the starting address of the function containing the PC. If
2479 the caller didn't give us a name, look it up at the same time. */
2480 if (0 == find_pc_partial_function (pc
, name
? NULL
: &name
,
2484 return strncmp (name
, "_call_via_r", 11) == 0;
2487 /* If PC is in a Thumb call or return stub, return the address of the
2488 target PC, which is in a register. The thunk functions are called
2489 _called_via_xx, where x is the register name. The possible names
2490 are r0-r9, sl, fp, ip, sp, and lr. */
2493 arm_skip_stub (CORE_ADDR pc
)
2496 CORE_ADDR start_addr
;
2498 /* Find the starting address and name of the function containing the PC. */
2499 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2502 /* Call thunks always start with "_call_via_". */
2503 if (strncmp (name
, "_call_via_", 10) == 0)
2505 /* Use the name suffix to determine which register contains the
2507 static char *table
[15] =
2508 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2509 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2513 for (regno
= 0; regno
<= 14; regno
++)
2514 if (strcmp (&name
[10], table
[regno
]) == 0)
2515 return read_register (regno
);
2518 return 0; /* not a stub */
2522 set_arm_command (char *args
, int from_tty
)
2524 printf_unfiltered ("\"set arm\" must be followed by an apporpriate subcommand.\n");
2525 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
2529 show_arm_command (char *args
, int from_tty
)
2531 cmd_show_list (showarmcmdlist
, from_tty
, "");
2534 enum arm_float_model
2535 arm_get_fp_model (struct gdbarch
*gdbarch
)
2537 if (arm_fp_model
== ARM_FLOAT_AUTO
)
2538 return gdbarch_tdep (gdbarch
)->fp_model
;
2540 return arm_fp_model
;
2544 arm_set_fp (struct gdbarch
*gdbarch
)
2546 enum arm_float_model fp_model
= arm_get_fp_model (gdbarch
);
2548 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
2549 && (fp_model
== ARM_FLOAT_SOFT_FPA
|| fp_model
== ARM_FLOAT_FPA
))
2551 set_gdbarch_double_format (gdbarch
,
2552 &floatformat_ieee_double_littlebyte_bigword
);
2553 set_gdbarch_long_double_format
2554 (gdbarch
, &floatformat_ieee_double_littlebyte_bigword
);
2558 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_little
);
2559 set_gdbarch_long_double_format (gdbarch
,
2560 &floatformat_ieee_double_little
);
2565 set_fp_model_sfunc (char *args
, int from_tty
,
2566 struct cmd_list_element
*c
)
2568 enum arm_float_model fp_model
;
2570 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
2571 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
2573 arm_fp_model
= fp_model
;
2577 if (fp_model
== ARM_FLOAT_LAST
)
2578 internal_error (__FILE__
, __LINE__
, "Invalid fp model accepted: %s.",
2581 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2582 arm_set_fp (current_gdbarch
);
2586 show_fp_model (char *args
, int from_tty
,
2587 struct cmd_list_element
*c
)
2589 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2591 if (arm_fp_model
== ARM_FLOAT_AUTO
2592 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2593 printf_filtered (" - the default for the current ABI is \"%s\".\n",
2594 fp_model_strings
[tdep
->fp_model
]);
2597 /* If the user changes the register disassembly style used for info
2598 register and other commands, we have to also switch the style used
2599 in opcodes for disassembly output. This function is run in the "set
2600 arm disassembly" command, and does that. */
2603 set_disassembly_style_sfunc (char *args
, int from_tty
,
2604 struct cmd_list_element
*c
)
2606 set_disassembly_style ();
2609 /* Return the ARM register name corresponding to register I. */
2611 arm_register_name (int i
)
2613 return arm_register_names
[i
];
2617 set_disassembly_style (void)
2619 const char *setname
, *setdesc
, **regnames
;
2622 /* Find the style that the user wants in the opcodes table. */
2624 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2625 while ((disassembly_style
!= setname
)
2626 && (current
< num_disassembly_options
))
2627 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2628 current_option
= current
;
2630 /* Fill our copy. */
2631 for (j
= 0; j
< numregs
; j
++)
2632 arm_register_names
[j
] = (char *) regnames
[j
];
2635 if (isupper (*regnames
[ARM_PC_REGNUM
]))
2637 arm_register_names
[ARM_FPS_REGNUM
] = "FPS";
2638 arm_register_names
[ARM_PS_REGNUM
] = "CPSR";
2642 arm_register_names
[ARM_FPS_REGNUM
] = "fps";
2643 arm_register_names
[ARM_PS_REGNUM
] = "cpsr";
2646 /* Synchronize the disassembler. */
2647 set_arm_regname_option (current
);
2650 /* arm_othernames implements the "othernames" command. This is deprecated
2651 by the "set arm disassembly" command. */
2654 arm_othernames (char *names
, int n
)
2656 /* Circle through the various flavors. */
2657 current_option
= (current_option
+ 1) % num_disassembly_options
;
2659 disassembly_style
= valid_disassembly_styles
[current_option
];
2660 set_disassembly_style ();
2663 /* Test whether the coff symbol specific value corresponds to a Thumb
2667 coff_sym_is_thumb (int val
)
2669 return (val
== C_THUMBEXT
||
2670 val
== C_THUMBSTAT
||
2671 val
== C_THUMBEXTFUNC
||
2672 val
== C_THUMBSTATFUNC
||
2673 val
== C_THUMBLABEL
);
2676 /* arm_coff_make_msymbol_special()
2677 arm_elf_make_msymbol_special()
2679 These functions test whether the COFF or ELF symbol corresponds to
2680 an address in thumb code, and set a "special" bit in a minimal
2681 symbol to indicate that it does. */
2684 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2686 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2688 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2690 MSYMBOL_SET_SPECIAL (msym
);
2694 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2696 if (coff_sym_is_thumb (val
))
2697 MSYMBOL_SET_SPECIAL (msym
);
2701 static enum gdb_osabi
2702 arm_elf_osabi_sniffer (bfd
*abfd
)
2704 unsigned int elfosabi
, eflags
;
2705 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2707 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2712 /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the
2713 file are conforming to the base specification for that machine
2714 (there are no OS-specific extensions). In order to determine the
2715 real OS in use we must look for OS notes that have been added. */
2716 bfd_map_over_sections (abfd
,
2717 generic_elf_osabi_sniff_abi_tag_sections
,
2719 if (osabi
== GDB_OSABI_UNKNOWN
)
2721 /* Existing ARM tools don't set this field, so look at the EI_FLAGS
2722 field for more information. */
2723 eflags
= EF_ARM_EABI_VERSION(elf_elfheader(abfd
)->e_flags
);
2726 case EF_ARM_EABI_VER1
:
2727 osabi
= GDB_OSABI_ARM_EABI_V1
;
2730 case EF_ARM_EABI_VER2
:
2731 osabi
= GDB_OSABI_ARM_EABI_V2
;
2734 case EF_ARM_EABI_UNKNOWN
:
2735 /* Assume GNU tools. */
2736 osabi
= GDB_OSABI_ARM_APCS
;
2740 internal_error (__FILE__
, __LINE__
,
2741 "arm_elf_osabi_sniffer: Unknown ARM EABI "
2742 "version 0x%x", eflags
);
2748 /* GNU tools use this value. Check note sections in this case,
2750 bfd_map_over_sections (abfd
,
2751 generic_elf_osabi_sniff_abi_tag_sections
,
2753 if (osabi
== GDB_OSABI_UNKNOWN
)
2755 /* Assume APCS ABI. */
2756 osabi
= GDB_OSABI_ARM_APCS
;
2760 case ELFOSABI_FREEBSD
:
2761 osabi
= GDB_OSABI_FREEBSD_ELF
;
2764 case ELFOSABI_NETBSD
:
2765 osabi
= GDB_OSABI_NETBSD_ELF
;
2768 case ELFOSABI_LINUX
:
2769 osabi
= GDB_OSABI_LINUX
;
2777 /* Initialize the current architecture based on INFO. If possible,
2778 re-use an architecture from ARCHES, which is a list of
2779 architectures already created during this debugging session.
2781 Called e.g. at program startup, when reading a core file, and when
2782 reading a binary file. */
2784 static struct gdbarch
*
2785 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2787 struct gdbarch_tdep
*tdep
;
2788 struct gdbarch
*gdbarch
;
2790 /* Try to deterimine the ABI of the object we are loading. */
2792 if (info
.abfd
!= NULL
&& info
.osabi
== GDB_OSABI_UNKNOWN
)
2794 switch (bfd_get_flavour (info
.abfd
))
2796 case bfd_target_aout_flavour
:
2797 /* Assume it's an old APCS-style ABI. */
2798 info
.osabi
= GDB_OSABI_ARM_APCS
;
2801 case bfd_target_coff_flavour
:
2802 /* Assume it's an old APCS-style ABI. */
2804 info
.osabi
= GDB_OSABI_ARM_APCS
;
2808 /* Leave it as "unknown". */
2813 /* If there is already a candidate, use it. */
2814 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2816 return arches
->gdbarch
;
2818 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
2819 gdbarch
= gdbarch_alloc (&info
, tdep
);
2821 /* We used to default to FPA for generic ARM, but almost nobody uses that
2822 now, and we now provide a way for the user to force the model. So
2823 default to the most useful variant. */
2824 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
2827 switch (info
.byte_order
)
2829 case BFD_ENDIAN_BIG
:
2830 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
2831 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
2832 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
2833 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
2837 case BFD_ENDIAN_LITTLE
:
2838 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
2839 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
2840 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
2841 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
2846 internal_error (__FILE__
, __LINE__
,
2847 "arm_gdbarch_init: bad byte order for float format");
2850 /* On ARM targets char defaults to unsigned. */
2851 set_gdbarch_char_signed (gdbarch
, 0);
2853 /* This should be low enough for everything. */
2854 tdep
->lowest_pc
= 0x20;
2855 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
2857 set_gdbarch_deprecated_call_dummy_words (gdbarch
, arm_call_dummy_words
);
2858 set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch
, 0);
2860 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
2862 /* Frame handling. */
2863 set_gdbarch_unwind_dummy_id (gdbarch
, arm_unwind_dummy_id
);
2864 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
2865 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
2867 set_gdbarch_frameless_function_invocation
2868 (gdbarch
, arm_frameless_function_invocation
);
2869 set_gdbarch_frame_args_skip (gdbarch
, 0);
2871 frame_base_set_default (gdbarch
, &arm_normal_base
);
2873 /* Address manipulation. */
2874 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
2875 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
2877 /* Offset from address of function to start of its code. */
2878 set_gdbarch_function_start_offset (gdbarch
, 0);
2880 /* Advance PC across function entry code. */
2881 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
2883 /* Get the PC when a frame might not be available. */
2884 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
, arm_saved_pc_after_call
);
2886 /* The stack grows downward. */
2887 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2889 /* Breakpoint manipulation. */
2890 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
2891 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2893 /* Information about registers, etc. */
2894 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
2895 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
2896 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
2897 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
2898 set_gdbarch_deprecated_register_byte (gdbarch
, arm_register_byte
);
2899 set_gdbarch_deprecated_register_bytes (gdbarch
,
2900 (NUM_GREGS
* INT_REGISTER_RAW_SIZE
2901 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
2902 + NUM_SREGS
* STATUS_REGISTER_SIZE
));
2903 set_gdbarch_num_regs (gdbarch
, NUM_GREGS
+ NUM_FREGS
+ NUM_SREGS
);
2904 set_gdbarch_deprecated_register_raw_size (gdbarch
, arm_register_raw_size
);
2905 set_gdbarch_deprecated_register_virtual_size (gdbarch
, arm_register_virtual_size
);
2906 set_gdbarch_deprecated_max_register_raw_size (gdbarch
, FP_REGISTER_RAW_SIZE
);
2907 set_gdbarch_deprecated_max_register_virtual_size (gdbarch
, FP_REGISTER_VIRTUAL_SIZE
);
2908 set_gdbarch_deprecated_register_virtual_type (gdbarch
, arm_register_type
);
2910 /* Internal <-> external register number maps. */
2911 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
2913 /* Integer registers are 4 bytes. */
2914 set_gdbarch_deprecated_register_size (gdbarch
, 4);
2915 set_gdbarch_register_name (gdbarch
, arm_register_name
);
2917 /* Returning results. */
2918 set_gdbarch_extract_return_value (gdbarch
, arm_extract_return_value
);
2919 set_gdbarch_store_return_value (gdbarch
, arm_store_return_value
);
2920 set_gdbarch_use_struct_convention (gdbarch
, arm_use_struct_convention
);
2921 set_gdbarch_extract_struct_value_address (gdbarch
,
2922 arm_extract_struct_value_address
);
2924 /* Single stepping. */
2925 /* XXX For an RDI target we should ask the target if it can single-step. */
2926 set_gdbarch_software_single_step (gdbarch
, arm_software_single_step
);
2929 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
2931 /* Minsymbol frobbing. */
2932 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
2933 set_gdbarch_coff_make_msymbol_special (gdbarch
,
2934 arm_coff_make_msymbol_special
);
2936 /* Hook in the ABI-specific overrides, if they have been registered. */
2937 gdbarch_init_osabi (info
, gdbarch
);
2939 /* Add some default predicates. */
2940 frame_unwind_append_sniffer (gdbarch
, arm_sigtramp_unwind_sniffer
);
2941 frame_unwind_append_sniffer (gdbarch
, arm_prologue_unwind_sniffer
);
2943 /* Now we have tuned the configuration, set a few final things,
2944 based on what the OS ABI has told us. */
2946 if (tdep
->jb_pc
>= 0)
2947 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
2949 /* Floating point sizes and format. */
2950 switch (info
.byte_order
)
2952 case BFD_ENDIAN_BIG
:
2953 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
2954 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_big
);
2955 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
2959 case BFD_ENDIAN_LITTLE
:
2960 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
2961 arm_set_fp (gdbarch
);
2965 internal_error (__FILE__
, __LINE__
,
2966 "arm_gdbarch_init: bad byte order for float format");
2973 arm_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
2975 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2980 fprintf_unfiltered (file
, "arm_dump_tdep: Lowest pc = 0x%lx",
2981 (unsigned long) tdep
->lowest_pc
);
2985 arm_init_abi_eabi_v1 (struct gdbarch_info info
,
2986 struct gdbarch
*gdbarch
)
2992 arm_init_abi_eabi_v2 (struct gdbarch_info info
,
2993 struct gdbarch
*gdbarch
)
2999 arm_init_abi_apcs (struct gdbarch_info info
,
3000 struct gdbarch
*gdbarch
)
3005 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
3008 _initialize_arm_tdep (void)
3010 struct ui_file
*stb
;
3012 struct cmd_list_element
*new_set
, *new_show
;
3013 const char *setname
;
3014 const char *setdesc
;
3015 const char **regnames
;
3017 static char *helptext
;
3019 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
3021 /* Register an ELF OS ABI sniffer for ARM binaries. */
3022 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
3023 bfd_target_elf_flavour
,
3024 arm_elf_osabi_sniffer
);
3026 /* Register some ABI variants for embedded systems. */
3027 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_EABI_V1
,
3028 arm_init_abi_eabi_v1
);
3029 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_EABI_V2
,
3030 arm_init_abi_eabi_v2
);
3031 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_APCS
,
3034 /* Get the number of possible sets of register names defined in opcodes. */
3035 num_disassembly_options
= get_arm_regname_num_options ();
3037 /* Add root prefix command for all "set arm"/"show arm" commands. */
3038 add_prefix_cmd ("arm", no_class
, set_arm_command
,
3039 "Various ARM-specific commands.",
3040 &setarmcmdlist
, "set arm ", 0, &setlist
);
3042 add_prefix_cmd ("arm", no_class
, show_arm_command
,
3043 "Various ARM-specific commands.",
3044 &showarmcmdlist
, "show arm ", 0, &showlist
);
3046 /* Sync the opcode insn printer with our register viewer. */
3047 parse_arm_disassembler_option ("reg-names-std");
3049 /* Begin creating the help text. */
3050 stb
= mem_fileopen ();
3051 fprintf_unfiltered (stb
, "Set the disassembly style.\n"
3052 "The valid values are:\n");
3054 /* Initialize the array that will be passed to add_set_enum_cmd(). */
3055 valid_disassembly_styles
3056 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
3057 for (i
= 0; i
< num_disassembly_options
; i
++)
3059 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
3060 valid_disassembly_styles
[i
] = setname
;
3061 fprintf_unfiltered (stb
, "%s - %s\n", setname
,
3063 /* Copy the default names (if found) and synchronize disassembler. */
3064 if (!strcmp (setname
, "std"))
3066 disassembly_style
= setname
;
3068 for (j
= 0; j
< numregs
; j
++)
3069 arm_register_names
[j
] = (char *) regnames
[j
];
3070 set_arm_regname_option (i
);
3073 /* Mark the end of valid options. */
3074 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
3076 /* Finish the creation of the help text. */
3077 fprintf_unfiltered (stb
, "The default is \"std\".");
3078 helptext
= ui_file_xstrdup (stb
, &length
);
3079 ui_file_delete (stb
);
3081 /* Add the deprecated disassembly-flavor command. */
3082 new_set
= add_set_enum_cmd ("disassembly-flavor", no_class
,
3083 valid_disassembly_styles
,
3087 set_cmd_sfunc (new_set
, set_disassembly_style_sfunc
);
3088 deprecate_cmd (new_set
, "set arm disassembly");
3089 deprecate_cmd (add_show_from_set (new_set
, &showlist
),
3090 "show arm disassembly");
3092 /* And now add the new interface. */
3093 new_set
= add_set_enum_cmd ("disassembler", no_class
,
3094 valid_disassembly_styles
, &disassembly_style
,
3095 helptext
, &setarmcmdlist
);
3097 set_cmd_sfunc (new_set
, set_disassembly_style_sfunc
);
3098 add_show_from_set (new_set
, &showarmcmdlist
);
3100 add_setshow_cmd_full ("apcs32", no_class
,
3101 var_boolean
, (char *) &arm_apcs_32
,
3102 "Set usage of ARM 32-bit mode.",
3103 "Show usage of ARM 32-bit mode.",
3105 &setlist
, &showlist
, &new_set
, &new_show
);
3106 deprecate_cmd (new_set
, "set arm apcs32");
3107 deprecate_cmd (new_show
, "show arm apcs32");
3109 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
3110 "Set usage of ARM 32-bit mode. "
3111 "When off, a 26-bit PC will be used.",
3112 "Show usage of ARM 32-bit mode. "
3113 "When off, a 26-bit PC will be used.",
3115 &setarmcmdlist
, &showarmcmdlist
);
3117 /* Add a command to allow the user to force the FPU model. */
3118 new_set
= add_set_enum_cmd
3119 ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
3120 "Set the floating point type.\n"
3121 "auto - Determine the FP typefrom the OS-ABI.\n"
3122 "softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n"
3123 "fpa - FPA co-processor (GCC compiled).\n"
3124 "softvfp - Software FP with pure-endian doubles.\n"
3125 "vfp - VFP co-processor.",
3127 set_cmd_sfunc (new_set
, set_fp_model_sfunc
);
3128 set_cmd_sfunc (add_show_from_set (new_set
, &showarmcmdlist
), show_fp_model
);
3130 /* Add the deprecated "othernames" command. */
3131 deprecate_cmd (add_com ("othernames", class_obscure
, arm_othernames
,
3132 "Switch to the next set of register names."),
3133 "set arm disassembly");
3135 /* Debugging flag. */
3136 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
3137 "Set ARM debugging. "
3138 "When on, arm-specific debugging is enabled.",
3139 "Show ARM debugging. "
3140 "When on, arm-specific debugging is enabled.",
3142 &setdebuglist
, &showdebuglist
);