1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-1989, 1991-1993, 1995-1996, 1998-2012 Free
4 Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include <ctype.h> /* XXX for isupper (). */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
32 #include "reggroups.h"
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
41 #include "dwarf2-frame.h"
43 #include "prologue-value.h"
45 #include "target-descriptions.h"
46 #include "user-regs.h"
50 #include "gdb/sim-arm.h"
53 #include "coff/internal.h"
56 #include "gdb_assert.h"
61 #include "features/arm-with-m.c"
62 #include "features/arm-with-m-fpa-layout.c"
63 #include "features/arm-with-m-vfp-d16.c"
64 #include "features/arm-with-iwmmxt.c"
65 #include "features/arm-with-vfpv2.c"
66 #include "features/arm-with-vfpv3.c"
67 #include "features/arm-with-neon.c"
71 /* Macros for setting and testing a bit in a minimal symbol that marks
72 it as Thumb function. The MSB of the minimal symbol's "info" field
73 is used for this purpose.
75 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
76 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
78 #define MSYMBOL_SET_SPECIAL(msym) \
79 MSYMBOL_TARGET_FLAG_1 (msym) = 1
81 #define MSYMBOL_IS_SPECIAL(msym) \
82 MSYMBOL_TARGET_FLAG_1 (msym)
84 /* Per-objfile data used for mapping symbols. */
85 static const struct objfile_data
*arm_objfile_data_key
;
87 struct arm_mapping_symbol
92 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
93 DEF_VEC_O(arm_mapping_symbol_s
);
95 struct arm_per_objfile
97 VEC(arm_mapping_symbol_s
) **section_maps
;
100 /* The list of available "set arm ..." and "show arm ..." commands. */
101 static struct cmd_list_element
*setarmcmdlist
= NULL
;
102 static struct cmd_list_element
*showarmcmdlist
= NULL
;
104 /* The type of floating-point to use. Keep this in sync with enum
105 arm_float_model, and the help string in _initialize_arm_tdep. */
106 static const char *const fp_model_strings
[] =
116 /* A variable that can be configured by the user. */
117 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
118 static const char *current_fp_model
= "auto";
120 /* The ABI to use. Keep this in sync with arm_abi_kind. */
121 static const char *const arm_abi_strings
[] =
129 /* A variable that can be configured by the user. */
130 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
131 static const char *arm_abi_string
= "auto";
133 /* The execution mode to assume. */
134 static const char *const arm_mode_strings
[] =
142 static const char *arm_fallback_mode_string
= "auto";
143 static const char *arm_force_mode_string
= "auto";
145 /* Internal override of the execution mode. -1 means no override,
146 0 means override to ARM mode, 1 means override to Thumb mode.
147 The effect is the same as if arm_force_mode has been set by the
148 user (except the internal override has precedence over a user's
149 arm_force_mode override). */
150 static int arm_override_mode
= -1;
152 /* Number of different reg name sets (options). */
153 static int num_disassembly_options
;
155 /* The standard register names, and all the valid aliases for them. Note
156 that `fp', `sp' and `pc' are not added in this alias list, because they
157 have been added as builtin user registers in
158 std-regs.c:_initialize_frame_reg. */
163 } arm_register_aliases
[] = {
164 /* Basic register numbers. */
181 /* Synonyms (argument and variable registers). */
194 /* Other platform-specific names for r9. */
200 /* Names used by GCC (not listed in the ARM EABI). */
202 /* A special name from the older ATPCS. */
206 static const char *const arm_register_names
[] =
207 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
208 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
209 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
210 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
211 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
212 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
213 "fps", "cpsr" }; /* 24 25 */
215 /* Valid register name styles. */
216 static const char **valid_disassembly_styles
;
218 /* Disassembly style to use. Default to "std" register names. */
219 static const char *disassembly_style
;
221 /* This is used to keep the bfd arch_info in sync with the disassembly
223 static void set_disassembly_style_sfunc(char *, int,
224 struct cmd_list_element
*);
225 static void set_disassembly_style (void);
227 static void convert_from_extended (const struct floatformat
*, const void *,
229 static void convert_to_extended (const struct floatformat
*, void *,
232 static enum register_status
arm_neon_quad_read (struct gdbarch
*gdbarch
,
233 struct regcache
*regcache
,
234 int regnum
, gdb_byte
*buf
);
235 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
236 struct regcache
*regcache
,
237 int regnum
, const gdb_byte
*buf
);
239 static int thumb_insn_size (unsigned short inst1
);
241 struct arm_prologue_cache
243 /* The stack pointer at the time this frame was created; i.e. the
244 caller's stack pointer when this function was called. It is used
245 to identify this frame. */
248 /* The frame base for this frame is just prev_sp - frame size.
249 FRAMESIZE is the distance from the frame pointer to the
250 initial stack pointer. */
254 /* The register used to hold the frame pointer for this frame. */
257 /* Saved register offsets. */
258 struct trad_frame_saved_reg
*saved_regs
;
261 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
262 CORE_ADDR prologue_start
,
263 CORE_ADDR prologue_end
,
264 struct arm_prologue_cache
*cache
);
266 /* Architecture version for displaced stepping. This effects the behaviour of
267 certain instructions, and really should not be hard-wired. */
269 #define DISPLACED_STEPPING_ARCH_VERSION 5
271 /* Addresses for calling Thumb functions have the bit 0 set.
272 Here are some macros to test, set, or clear bit 0 of addresses. */
273 #define IS_THUMB_ADDR(addr) ((addr) & 1)
274 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
275 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
277 /* Set to true if the 32-bit mode is in use. */
281 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
284 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
286 if (gdbarch_tdep (gdbarch
)->is_m
)
292 /* Determine if FRAME is executing in Thumb mode. */
295 arm_frame_is_thumb (struct frame_info
*frame
)
298 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
300 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
301 directly (from a signal frame or dummy frame) or by interpreting
302 the saved LR (from a prologue or DWARF frame). So consult it and
303 trust the unwinders. */
304 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
306 return (cpsr
& t_bit
) != 0;
309 /* Callback for VEC_lower_bound. */
312 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
313 const struct arm_mapping_symbol
*rhs
)
315 return lhs
->value
< rhs
->value
;
318 /* Search for the mapping symbol covering MEMADDR. If one is found,
319 return its type. Otherwise, return 0. If START is non-NULL,
320 set *START to the location of the mapping symbol. */
323 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
325 struct obj_section
*sec
;
327 /* If there are mapping symbols, consult them. */
328 sec
= find_pc_section (memaddr
);
331 struct arm_per_objfile
*data
;
332 VEC(arm_mapping_symbol_s
) *map
;
333 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
337 data
= objfile_data (sec
->objfile
, arm_objfile_data_key
);
340 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
341 if (!VEC_empty (arm_mapping_symbol_s
, map
))
343 struct arm_mapping_symbol
*map_sym
;
345 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
346 arm_compare_mapping_symbols
);
348 /* VEC_lower_bound finds the earliest ordered insertion
349 point. If the following symbol starts at this exact
350 address, we use that; otherwise, the preceding
351 mapping symbol covers this address. */
352 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
354 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
355 if (map_sym
->value
== map_key
.value
)
358 *start
= map_sym
->value
+ obj_section_addr (sec
);
359 return map_sym
->type
;
365 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
367 *start
= map_sym
->value
+ obj_section_addr (sec
);
368 return map_sym
->type
;
377 /* Determine if the program counter specified in MEMADDR is in a Thumb
378 function. This function should be called for addresses unrelated to
379 any executing frame; otherwise, prefer arm_frame_is_thumb. */
382 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
384 struct minimal_symbol
*sym
;
386 struct displaced_step_closure
* dsc
387 = get_displaced_step_closure_by_addr(memaddr
);
389 /* If checking the mode of displaced instruction in copy area, the mode
390 should be determined by instruction on the original address. */
394 fprintf_unfiltered (gdb_stdlog
,
395 "displaced: check mode of %.8lx instead of %.8lx\n",
396 (unsigned long) dsc
->insn_addr
,
397 (unsigned long) memaddr
);
398 memaddr
= dsc
->insn_addr
;
401 /* If bit 0 of the address is set, assume this is a Thumb address. */
402 if (IS_THUMB_ADDR (memaddr
))
405 /* Respect internal mode override if active. */
406 if (arm_override_mode
!= -1)
407 return arm_override_mode
;
409 /* If the user wants to override the symbol table, let him. */
410 if (strcmp (arm_force_mode_string
, "arm") == 0)
412 if (strcmp (arm_force_mode_string
, "thumb") == 0)
415 /* ARM v6-M and v7-M are always in Thumb mode. */
416 if (gdbarch_tdep (gdbarch
)->is_m
)
419 /* If there are mapping symbols, consult them. */
420 type
= arm_find_mapping_symbol (memaddr
, NULL
);
424 /* Thumb functions have a "special" bit set in minimal symbols. */
425 sym
= lookup_minimal_symbol_by_pc (memaddr
);
427 return (MSYMBOL_IS_SPECIAL (sym
));
429 /* If the user wants to override the fallback mode, let them. */
430 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
432 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
435 /* If we couldn't find any symbol, but we're talking to a running
436 target, then trust the current value of $cpsr. This lets
437 "display/i $pc" always show the correct mode (though if there is
438 a symbol table we will not reach here, so it still may not be
439 displayed in the mode it will be executed). */
440 if (target_has_registers
)
441 return arm_frame_is_thumb (get_current_frame ());
443 /* Otherwise we're out of luck; we assume ARM. */
447 /* Remove useless bits from addresses in a running program. */
449 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
452 return UNMAKE_THUMB_ADDR (val
);
454 return (val
& 0x03fffffc);
457 /* When reading symbols, we need to zap the low bit of the address,
458 which may be set to 1 for Thumb functions. */
460 arm_smash_text_address (struct gdbarch
*gdbarch
, CORE_ADDR val
)
465 /* Return 1 if PC is the start of a compiler helper function which
466 can be safely ignored during prologue skipping. IS_THUMB is true
467 if the function is known to be a Thumb function due to the way it
470 skip_prologue_function (struct gdbarch
*gdbarch
, CORE_ADDR pc
, int is_thumb
)
472 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
473 struct minimal_symbol
*msym
;
475 msym
= lookup_minimal_symbol_by_pc (pc
);
477 && SYMBOL_VALUE_ADDRESS (msym
) == pc
478 && SYMBOL_LINKAGE_NAME (msym
) != NULL
)
480 const char *name
= SYMBOL_LINKAGE_NAME (msym
);
482 /* The GNU linker's Thumb call stub to foo is named
484 if (strstr (name
, "_from_thumb") != NULL
)
487 /* On soft-float targets, __truncdfsf2 is called to convert promoted
488 arguments to their argument types in non-prototyped
490 if (strncmp (name
, "__truncdfsf2", strlen ("__truncdfsf2")) == 0)
492 if (strncmp (name
, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
495 /* Internal functions related to thread-local storage. */
496 if (strncmp (name
, "__tls_get_addr", strlen ("__tls_get_addr")) == 0)
498 if (strncmp (name
, "__aeabi_read_tp", strlen ("__aeabi_read_tp")) == 0)
503 /* If we run against a stripped glibc, we may be unable to identify
504 special functions by name. Check for one important case,
505 __aeabi_read_tp, by comparing the *code* against the default
506 implementation (this is hand-written ARM assembler in glibc). */
509 && read_memory_unsigned_integer (pc
, 4, byte_order_for_code
)
510 == 0xe3e00a0f /* mov r0, #0xffff0fff */
511 && read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
)
512 == 0xe240f01f) /* sub pc, r0, #31 */
519 /* Support routines for instruction parsing. */
520 #define submask(x) ((1L << ((x) + 1)) - 1)
521 #define bit(obj,st) (((obj) >> (st)) & 1)
522 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
523 #define sbits(obj,st,fn) \
524 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
525 #define BranchDest(addr,instr) \
526 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
528 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
529 the first 16-bit of instruction, and INSN2 is the second 16-bit of
531 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
532 ((bits ((insn1), 0, 3) << 12) \
533 | (bits ((insn1), 10, 10) << 11) \
534 | (bits ((insn2), 12, 14) << 8) \
535 | bits ((insn2), 0, 7))
537 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
538 the 32-bit instruction. */
539 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
540 ((bits ((insn), 16, 19) << 12) \
541 | bits ((insn), 0, 11))
543 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
546 thumb_expand_immediate (unsigned int imm
)
548 unsigned int count
= imm
>> 7;
556 return (imm
& 0xff) | ((imm
& 0xff) << 16);
558 return ((imm
& 0xff) << 8) | ((imm
& 0xff) << 24);
560 return (imm
& 0xff) | ((imm
& 0xff) << 8)
561 | ((imm
& 0xff) << 16) | ((imm
& 0xff) << 24);
564 return (0x80 | (imm
& 0x7f)) << (32 - count
);
567 /* Return 1 if the 16-bit Thumb instruction INST might change
568 control flow, 0 otherwise. */
571 thumb_instruction_changes_pc (unsigned short inst
)
573 if ((inst
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
576 if ((inst
& 0xf000) == 0xd000) /* conditional branch */
579 if ((inst
& 0xf800) == 0xe000) /* unconditional branch */
582 if ((inst
& 0xff00) == 0x4700) /* bx REG, blx REG */
585 if ((inst
& 0xff87) == 0x4687) /* mov pc, REG */
588 if ((inst
& 0xf500) == 0xb100) /* CBNZ or CBZ. */
594 /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
595 might change control flow, 0 otherwise. */
598 thumb2_instruction_changes_pc (unsigned short inst1
, unsigned short inst2
)
600 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
602 /* Branches and miscellaneous control instructions. */
604 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
609 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
611 /* SUBS PC, LR, #imm8. */
614 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
616 /* Conditional branch. */
623 if ((inst1
& 0xfe50) == 0xe810)
625 /* Load multiple or RFE. */
627 if (bit (inst1
, 7) && !bit (inst1
, 8))
633 else if (!bit (inst1
, 7) && bit (inst1
, 8))
639 else if (bit (inst1
, 7) && bit (inst1
, 8))
644 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
653 if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
655 /* MOV PC or MOVS PC. */
659 if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
662 if (bits (inst1
, 0, 3) == 15)
668 if ((inst2
& 0x0fc0) == 0x0000)
674 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
680 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
689 /* Analyze a Thumb prologue, looking for a recognizable stack frame
690 and frame pointer. Scan until we encounter a store that could
691 clobber the stack frame unexpectedly, or an unknown instruction.
692 Return the last address which is definitely safe to skip for an
693 initial breakpoint. */
696 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
697 CORE_ADDR start
, CORE_ADDR limit
,
698 struct arm_prologue_cache
*cache
)
700 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
701 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
704 struct pv_area
*stack
;
705 struct cleanup
*back_to
;
707 CORE_ADDR unrecognized_pc
= 0;
709 for (i
= 0; i
< 16; i
++)
710 regs
[i
] = pv_register (i
, 0);
711 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
712 back_to
= make_cleanup_free_pv_area (stack
);
714 while (start
< limit
)
718 insn
= read_memory_unsigned_integer (start
, 2, byte_order_for_code
);
720 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
725 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
728 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
729 whether to save LR (R14). */
730 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
732 /* Calculate offsets of saved R0-R7 and LR. */
733 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
734 if (mask
& (1 << regno
))
736 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
738 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
741 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
744 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
745 if (insn
& 0x80) /* Check for SUB. */
746 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
749 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
752 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
753 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
755 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
756 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
757 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
759 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
760 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
761 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
763 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
764 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
765 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
766 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
767 regs
[bits (insn
, 6, 8)]);
768 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
769 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
771 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
772 int rm
= bits (insn
, 3, 6);
773 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
775 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
777 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
778 int src_reg
= (insn
& 0x78) >> 3;
779 regs
[dst_reg
] = regs
[src_reg
];
781 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
783 /* Handle stores to the stack. Normally pushes are used,
784 but with GCC -mtpcs-frame, there may be other stores
785 in the prologue to create the frame. */
786 int regno
= (insn
>> 8) & 0x7;
789 offset
= (insn
& 0xff) << 2;
790 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
792 if (pv_area_store_would_trash (stack
, addr
))
795 pv_area_store (stack
, addr
, 4, regs
[regno
]);
797 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
799 int rd
= bits (insn
, 0, 2);
800 int rn
= bits (insn
, 3, 5);
803 offset
= bits (insn
, 6, 10) << 2;
804 addr
= pv_add_constant (regs
[rn
], offset
);
806 if (pv_area_store_would_trash (stack
, addr
))
809 pv_area_store (stack
, addr
, 4, regs
[rd
]);
811 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
812 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
813 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
814 /* Ignore stores of argument registers to the stack. */
816 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
817 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
818 /* Ignore block loads from the stack, potentially copying
819 parameters from memory. */
821 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
822 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
823 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
824 /* Similarly ignore single loads from the stack. */
826 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
827 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
828 /* Skip register copies, i.e. saves to another register
829 instead of the stack. */
831 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
832 /* Recognize constant loads; even with small stacks these are necessary
834 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
835 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
837 /* Constant pool loads, for the same reason. */
838 unsigned int constant
;
841 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
842 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
843 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
845 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instructions. */
847 unsigned short inst2
;
849 inst2
= read_memory_unsigned_integer (start
+ 2, 2,
850 byte_order_for_code
);
852 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
854 /* BL, BLX. Allow some special function calls when
855 skipping the prologue; GCC generates these before
856 storing arguments to the stack. */
858 int j1
, j2
, imm1
, imm2
;
860 imm1
= sbits (insn
, 0, 10);
861 imm2
= bits (inst2
, 0, 10);
862 j1
= bit (inst2
, 13);
863 j2
= bit (inst2
, 11);
865 offset
= ((imm1
<< 12) + (imm2
<< 1));
866 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
868 nextpc
= start
+ 4 + offset
;
869 /* For BLX make sure to clear the low bits. */
870 if (bit (inst2
, 12) == 0)
871 nextpc
= nextpc
& 0xfffffffc;
873 if (!skip_prologue_function (gdbarch
, nextpc
,
874 bit (inst2
, 12) != 0))
878 else if ((insn
& 0xffd0) == 0xe900 /* stmdb Rn{!},
880 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
882 pv_t addr
= regs
[bits (insn
, 0, 3)];
885 if (pv_area_store_would_trash (stack
, addr
))
888 /* Calculate offsets of saved registers. */
889 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
890 if (inst2
& (1 << regno
))
892 addr
= pv_add_constant (addr
, -4);
893 pv_area_store (stack
, addr
, 4, regs
[regno
]);
897 regs
[bits (insn
, 0, 3)] = addr
;
900 else if ((insn
& 0xff50) == 0xe940 /* strd Rt, Rt2,
902 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
904 int regno1
= bits (inst2
, 12, 15);
905 int regno2
= bits (inst2
, 8, 11);
906 pv_t addr
= regs
[bits (insn
, 0, 3)];
908 offset
= inst2
& 0xff;
910 addr
= pv_add_constant (addr
, offset
);
912 addr
= pv_add_constant (addr
, -offset
);
914 if (pv_area_store_would_trash (stack
, addr
))
917 pv_area_store (stack
, addr
, 4, regs
[regno1
]);
918 pv_area_store (stack
, pv_add_constant (addr
, 4),
922 regs
[bits (insn
, 0, 3)] = addr
;
925 else if ((insn
& 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
926 && (inst2
& 0x0c00) == 0x0c00
927 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
929 int regno
= bits (inst2
, 12, 15);
930 pv_t addr
= regs
[bits (insn
, 0, 3)];
932 offset
= inst2
& 0xff;
934 addr
= pv_add_constant (addr
, offset
);
936 addr
= pv_add_constant (addr
, -offset
);
938 if (pv_area_store_would_trash (stack
, addr
))
941 pv_area_store (stack
, addr
, 4, regs
[regno
]);
944 regs
[bits (insn
, 0, 3)] = addr
;
947 else if ((insn
& 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
948 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
950 int regno
= bits (inst2
, 12, 15);
953 offset
= inst2
& 0xfff;
954 addr
= pv_add_constant (regs
[bits (insn
, 0, 3)], offset
);
956 if (pv_area_store_would_trash (stack
, addr
))
959 pv_area_store (stack
, addr
, 4, regs
[regno
]);
962 else if ((insn
& 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
963 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
964 /* Ignore stores of argument registers to the stack. */
967 else if ((insn
& 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
968 && (inst2
& 0x0d00) == 0x0c00
969 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
970 /* Ignore stores of argument registers to the stack. */
973 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!],
975 && (inst2
& 0x8000) == 0x0000
976 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
977 /* Ignore block loads from the stack, potentially copying
978 parameters from memory. */
981 else if ((insn
& 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
983 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
984 /* Similarly ignore dual loads from the stack. */
987 else if ((insn
& 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
988 && (inst2
& 0x0d00) == 0x0c00
989 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
990 /* Similarly ignore single loads from the stack. */
993 else if ((insn
& 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
994 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
995 /* Similarly ignore single loads from the stack. */
998 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
999 && (inst2
& 0x8000) == 0x0000)
1001 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1002 | (bits (inst2
, 12, 14) << 8)
1003 | bits (inst2
, 0, 7));
1005 regs
[bits (inst2
, 8, 11)]
1006 = pv_add_constant (regs
[bits (insn
, 0, 3)],
1007 thumb_expand_immediate (imm
));
1010 else if ((insn
& 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
1011 && (inst2
& 0x8000) == 0x0000)
1013 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1014 | (bits (inst2
, 12, 14) << 8)
1015 | bits (inst2
, 0, 7));
1017 regs
[bits (inst2
, 8, 11)]
1018 = pv_add_constant (regs
[bits (insn
, 0, 3)], imm
);
1021 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
1022 && (inst2
& 0x8000) == 0x0000)
1024 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1025 | (bits (inst2
, 12, 14) << 8)
1026 | bits (inst2
, 0, 7));
1028 regs
[bits (inst2
, 8, 11)]
1029 = pv_add_constant (regs
[bits (insn
, 0, 3)],
1030 - (CORE_ADDR
) thumb_expand_immediate (imm
));
1033 else if ((insn
& 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
1034 && (inst2
& 0x8000) == 0x0000)
1036 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1037 | (bits (inst2
, 12, 14) << 8)
1038 | bits (inst2
, 0, 7));
1040 regs
[bits (inst2
, 8, 11)]
1041 = pv_add_constant (regs
[bits (insn
, 0, 3)], - (CORE_ADDR
) imm
);
1044 else if ((insn
& 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1046 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1047 | (bits (inst2
, 12, 14) << 8)
1048 | bits (inst2
, 0, 7));
1050 regs
[bits (inst2
, 8, 11)]
1051 = pv_constant (thumb_expand_immediate (imm
));
1054 else if ((insn
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1057 = EXTRACT_MOVW_MOVT_IMM_T (insn
, inst2
);
1059 regs
[bits (inst2
, 8, 11)] = pv_constant (imm
);
1062 else if (insn
== 0xea5f /* mov.w Rd,Rm */
1063 && (inst2
& 0xf0f0) == 0)
1065 int dst_reg
= (inst2
& 0x0f00) >> 8;
1066 int src_reg
= inst2
& 0xf;
1067 regs
[dst_reg
] = regs
[src_reg
];
1070 else if ((insn
& 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1072 /* Constant pool loads. */
1073 unsigned int constant
;
1076 offset
= bits (insn
, 0, 11);
1078 loc
= start
+ 4 + offset
;
1080 loc
= start
+ 4 - offset
;
1082 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1083 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1086 else if ((insn
& 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1088 /* Constant pool loads. */
1089 unsigned int constant
;
1092 offset
= bits (insn
, 0, 7) << 2;
1094 loc
= start
+ 4 + offset
;
1096 loc
= start
+ 4 - offset
;
1098 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1099 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1101 constant
= read_memory_unsigned_integer (loc
+ 4, 4, byte_order
);
1102 regs
[bits (inst2
, 8, 11)] = pv_constant (constant
);
1105 else if (thumb2_instruction_changes_pc (insn
, inst2
))
1107 /* Don't scan past anything that might change control flow. */
1112 /* The optimizer might shove anything into the prologue,
1113 so we just skip what we don't recognize. */
1114 unrecognized_pc
= start
;
1119 else if (thumb_instruction_changes_pc (insn
))
1121 /* Don't scan past anything that might change control flow. */
1126 /* The optimizer might shove anything into the prologue,
1127 so we just skip what we don't recognize. */
1128 unrecognized_pc
= start
;
1135 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1136 paddress (gdbarch
, start
));
1138 if (unrecognized_pc
== 0)
1139 unrecognized_pc
= start
;
1143 do_cleanups (back_to
);
1144 return unrecognized_pc
;
1147 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1149 /* Frame pointer is fp. Frame size is constant. */
1150 cache
->framereg
= ARM_FP_REGNUM
;
1151 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1153 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
1155 /* Frame pointer is r7. Frame size is constant. */
1156 cache
->framereg
= THUMB_FP_REGNUM
;
1157 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
1161 /* Try the stack pointer... this is a bit desperate. */
1162 cache
->framereg
= ARM_SP_REGNUM
;
1163 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1166 for (i
= 0; i
< 16; i
++)
1167 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
1168 cache
->saved_regs
[i
].addr
= offset
;
1170 do_cleanups (back_to
);
1171 return unrecognized_pc
;
1175 /* Try to analyze the instructions starting from PC, which load symbol
1176 __stack_chk_guard. Return the address of instruction after loading this
1177 symbol, set the dest register number to *BASEREG, and set the size of
1178 instructions for loading symbol in OFFSET. Return 0 if instructions are
1182 arm_analyze_load_stack_chk_guard(CORE_ADDR pc
, struct gdbarch
*gdbarch
,
1183 unsigned int *destreg
, int *offset
)
1185 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1186 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1187 unsigned int low
, high
, address
;
1192 unsigned short insn1
1193 = read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
1195 if ((insn1
& 0xf800) == 0x4800) /* ldr Rd, #immed */
1197 *destreg
= bits (insn1
, 8, 10);
1199 address
= bits (insn1
, 0, 7);
1201 else if ((insn1
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1203 unsigned short insn2
1204 = read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1206 low
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1209 = read_memory_unsigned_integer (pc
+ 4, 2, byte_order_for_code
);
1211 = read_memory_unsigned_integer (pc
+ 6, 2, byte_order_for_code
);
1213 /* movt Rd, #const */
1214 if ((insn1
& 0xfbc0) == 0xf2c0)
1216 high
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1217 *destreg
= bits (insn2
, 8, 11);
1219 address
= (high
<< 16 | low
);
1226 = read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
1228 if ((insn
& 0x0e5f0000) == 0x041f0000) /* ldr Rd, #immed */
1230 address
= bits (insn
, 0, 11);
1231 *destreg
= bits (insn
, 12, 15);
1234 else if ((insn
& 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1236 low
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1239 = read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
);
1241 if ((insn
& 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1243 high
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1244 *destreg
= bits (insn
, 12, 15);
1246 address
= (high
<< 16 | low
);
1254 /* Try to skip a sequence of instructions used for stack protector. If PC
1255 points to the first instruction of this sequence, return the address of
1256 first instruction after this sequence, otherwise, return original PC.
1258 On arm, this sequence of instructions is composed of mainly three steps,
1259 Step 1: load symbol __stack_chk_guard,
1260 Step 2: load from address of __stack_chk_guard,
1261 Step 3: store it to somewhere else.
1263 Usually, instructions on step 2 and step 3 are the same on various ARM
1264 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1265 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1266 instructions in step 1 vary from different ARM architectures. On ARMv7,
1269 movw Rn, #:lower16:__stack_chk_guard
1270 movt Rn, #:upper16:__stack_chk_guard
1277 .word __stack_chk_guard
1279 Since ldr/str is a very popular instruction, we can't use them as
1280 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1281 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1282 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1285 arm_skip_stack_protector(CORE_ADDR pc
, struct gdbarch
*gdbarch
)
1287 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1288 unsigned int basereg
;
1289 struct minimal_symbol
*stack_chk_guard
;
1291 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1294 /* Try to parse the instructions in Step 1. */
1295 addr
= arm_analyze_load_stack_chk_guard (pc
, gdbarch
,
1300 stack_chk_guard
= lookup_minimal_symbol_by_pc (addr
);
1301 /* If name of symbol doesn't start with '__stack_chk_guard', this
1302 instruction sequence is not for stack protector. If symbol is
1303 removed, we conservatively think this sequence is for stack protector. */
1305 && strncmp (SYMBOL_LINKAGE_NAME (stack_chk_guard
), "__stack_chk_guard",
1306 strlen ("__stack_chk_guard")) != 0)
1311 unsigned int destreg
;
1313 = read_memory_unsigned_integer (pc
+ offset
, 2, byte_order_for_code
);
1315 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1316 if ((insn
& 0xf800) != 0x6800)
1318 if (bits (insn
, 3, 5) != basereg
)
1320 destreg
= bits (insn
, 0, 2);
1322 insn
= read_memory_unsigned_integer (pc
+ offset
+ 2, 2,
1323 byte_order_for_code
);
1324 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1325 if ((insn
& 0xf800) != 0x6000)
1327 if (destreg
!= bits (insn
, 0, 2))
1332 unsigned int destreg
;
1334 = read_memory_unsigned_integer (pc
+ offset
, 4, byte_order_for_code
);
1336 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1337 if ((insn
& 0x0e500000) != 0x04100000)
1339 if (bits (insn
, 16, 19) != basereg
)
1341 destreg
= bits (insn
, 12, 15);
1342 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1343 insn
= read_memory_unsigned_integer (pc
+ offset
+ 4,
1344 4, byte_order_for_code
);
1345 if ((insn
& 0x0e500000) != 0x04000000)
1347 if (bits (insn
, 12, 15) != destreg
)
1350 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1353 return pc
+ offset
+ 4;
1355 return pc
+ offset
+ 8;
1358 /* Advance the PC across any function entry prologue instructions to
1359 reach some "real" code.
1361 The APCS (ARM Procedure Call Standard) defines the following
1365 [stmfd sp!, {a1,a2,a3,a4}]
1366 stmfd sp!, {...,fp,ip,lr,pc}
1367 [stfe f7, [sp, #-12]!]
1368 [stfe f6, [sp, #-12]!]
1369 [stfe f5, [sp, #-12]!]
1370 [stfe f4, [sp, #-12]!]
1371 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1374 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1376 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1379 CORE_ADDR func_addr
, limit_pc
;
1381 /* See if we can determine the end of the prologue via the symbol table.
1382 If so, then return either PC, or the PC after the prologue, whichever
1384 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1386 CORE_ADDR post_prologue_pc
1387 = skip_prologue_using_sal (gdbarch
, func_addr
);
1388 struct symtab
*s
= find_pc_symtab (func_addr
);
1390 if (post_prologue_pc
)
1392 = arm_skip_stack_protector (post_prologue_pc
, gdbarch
);
1395 /* GCC always emits a line note before the prologue and another
1396 one after, even if the two are at the same address or on the
1397 same line. Take advantage of this so that we do not need to
1398 know every instruction that might appear in the prologue. We
1399 will have producer information for most binaries; if it is
1400 missing (e.g. for -gstabs), assuming the GNU tools. */
1401 if (post_prologue_pc
1403 || s
->producer
== NULL
1404 || strncmp (s
->producer
, "GNU ", sizeof ("GNU ") - 1) == 0
1405 || strncmp (s
->producer
, "clang ", sizeof ("clang ") - 1) == 0))
1406 return post_prologue_pc
;
1408 if (post_prologue_pc
!= 0)
1410 CORE_ADDR analyzed_limit
;
1412 /* For non-GCC compilers, make sure the entire line is an
1413 acceptable prologue; GDB will round this function's
1414 return value up to the end of the following line so we
1415 can not skip just part of a line (and we do not want to).
1417 RealView does not treat the prologue specially, but does
1418 associate prologue code with the opening brace; so this
1419 lets us skip the first line if we think it is the opening
1421 if (arm_pc_is_thumb (gdbarch
, func_addr
))
1422 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
1423 post_prologue_pc
, NULL
);
1425 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
1426 post_prologue_pc
, NULL
);
1428 if (analyzed_limit
!= post_prologue_pc
)
1431 return post_prologue_pc
;
1435 /* Can't determine prologue from the symbol table, need to examine
1438 /* Find an upper limit on the function prologue using the debug
1439 information. If the debug information could not be used to provide
1440 that bound, then use an arbitrary large number as the upper bound. */
1441 /* Like arm_scan_prologue, stop no later than pc + 64. */
1442 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1444 limit_pc
= pc
+ 64; /* Magic. */
1447 /* Check if this is Thumb code. */
1448 if (arm_pc_is_thumb (gdbarch
, pc
))
1449 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1451 for (skip_pc
= pc
; skip_pc
< limit_pc
; skip_pc
+= 4)
1453 inst
= read_memory_unsigned_integer (skip_pc
, 4, byte_order_for_code
);
1455 /* "mov ip, sp" is no longer a required part of the prologue. */
1456 if (inst
== 0xe1a0c00d) /* mov ip, sp */
1459 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
1462 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
1465 /* Some prologues begin with "str lr, [sp, #-4]!". */
1466 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
1469 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
1472 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
1475 /* Any insns after this point may float into the code, if it makes
1476 for better instruction scheduling, so we skip them only if we
1477 find them, but still consider the function to be frame-ful. */
1479 /* We may have either one sfmfd instruction here, or several stfe
1480 insns, depending on the version of floating point code we
1482 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
1485 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
1488 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
1491 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
1494 if ((inst
& 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */
1495 || (inst
& 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */
1496 || (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
1499 if ((inst
& 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */
1500 || (inst
& 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */
1501 || (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
1504 /* Un-recognized instruction; stop scanning. */
1508 return skip_pc
; /* End of prologue. */
1512 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1513 This function decodes a Thumb function prologue to determine:
1514 1) the size of the stack frame
1515 2) which registers are saved on it
1516 3) the offsets of saved regs
1517 4) the offset from the stack pointer to the frame pointer
1519 A typical Thumb function prologue would create this stack frame
1520 (offsets relative to FP)
1521 old SP -> 24 stack parameters
1524 R7 -> 0 local variables (16 bytes)
1525 SP -> -12 additional stack space (12 bytes)
1526 The frame size would thus be 36 bytes, and the frame offset would be
1527 12 bytes. The frame register is R7.
1529 The comments for thumb_skip_prolog() describe the algorithm we use
1530 to detect the end of the prolog. */
1534 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
1535 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
1537 CORE_ADDR prologue_start
;
1538 CORE_ADDR prologue_end
;
1540 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1543 /* See comment in arm_scan_prologue for an explanation of
1545 if (prologue_end
> prologue_start
+ 64)
1547 prologue_end
= prologue_start
+ 64;
1551 /* We're in the boondocks: we have no idea where the start of the
1555 prologue_end
= min (prologue_end
, prev_pc
);
1557 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1560 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
1563 arm_instruction_changes_pc (uint32_t this_instr
)
1565 if (bits (this_instr
, 28, 31) == INST_NV
)
1566 /* Unconditional instructions. */
1567 switch (bits (this_instr
, 24, 27))
1571 /* Branch with Link and change to Thumb. */
1576 /* Coprocessor register transfer. */
1577 if (bits (this_instr
, 12, 15) == 15)
1578 error (_("Invalid update to pc in instruction"));
1584 switch (bits (this_instr
, 25, 27))
1587 if (bits (this_instr
, 23, 24) == 2 && bit (this_instr
, 20) == 0)
1589 /* Multiplies and extra load/stores. */
1590 if (bit (this_instr
, 4) == 1 && bit (this_instr
, 7) == 1)
1591 /* Neither multiplies nor extension load/stores are allowed
1595 /* Otherwise, miscellaneous instructions. */
1597 /* BX <reg>, BXJ <reg>, BLX <reg> */
1598 if (bits (this_instr
, 4, 27) == 0x12fff1
1599 || bits (this_instr
, 4, 27) == 0x12fff2
1600 || bits (this_instr
, 4, 27) == 0x12fff3)
1603 /* Other miscellaneous instructions are unpredictable if they
1607 /* Data processing instruction. Fall through. */
1610 if (bits (this_instr
, 12, 15) == 15)
1617 /* Media instructions and architecturally undefined instructions. */
1618 if (bits (this_instr
, 25, 27) == 3 && bit (this_instr
, 4) == 1)
1622 if (bit (this_instr
, 20) == 0)
1626 if (bits (this_instr
, 12, 15) == ARM_PC_REGNUM
)
1632 /* Load/store multiple. */
1633 if (bit (this_instr
, 20) == 1 && bit (this_instr
, 15) == 1)
1639 /* Branch and branch with link. */
1644 /* Coprocessor transfers or SWIs can not affect PC. */
1648 internal_error (__FILE__
, __LINE__
, _("bad value in switch"));
1652 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1653 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1654 fill it in. Return the first address not recognized as a prologue
1657 We recognize all the instructions typically found in ARM prologues,
1658 plus harmless instructions which can be skipped (either for analysis
1659 purposes, or a more restrictive set that can be skipped when finding
1660 the end of the prologue). */
1663 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1664 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1665 struct arm_prologue_cache
*cache
)
1667 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1668 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1670 CORE_ADDR offset
, current_pc
;
1671 pv_t regs
[ARM_FPS_REGNUM
];
1672 struct pv_area
*stack
;
1673 struct cleanup
*back_to
;
1674 int framereg
, framesize
;
1675 CORE_ADDR unrecognized_pc
= 0;
1677 /* Search the prologue looking for instructions that set up the
1678 frame pointer, adjust the stack pointer, and save registers.
1680 Be careful, however, and if it doesn't look like a prologue,
1681 don't try to scan it. If, for instance, a frameless function
1682 begins with stmfd sp!, then we will tell ourselves there is
1683 a frame, which will confuse stack traceback, as well as "finish"
1684 and other operations that rely on a knowledge of the stack
1687 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1688 regs
[regno
] = pv_register (regno
, 0);
1689 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1690 back_to
= make_cleanup_free_pv_area (stack
);
1692 for (current_pc
= prologue_start
;
1693 current_pc
< prologue_end
;
1697 = read_memory_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1699 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1701 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1704 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1705 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1707 unsigned imm
= insn
& 0xff; /* immediate value */
1708 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1709 int rd
= bits (insn
, 12, 15);
1710 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1711 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1714 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1715 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1717 unsigned imm
= insn
& 0xff; /* immediate value */
1718 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1719 int rd
= bits (insn
, 12, 15);
1720 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1721 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1724 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd,
1727 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1729 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1730 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4,
1731 regs
[bits (insn
, 12, 15)]);
1734 else if ((insn
& 0xffff0000) == 0xe92d0000)
1735 /* stmfd sp!, {..., fp, ip, lr, pc}
1737 stmfd sp!, {a1, a2, a3, a4} */
1739 int mask
= insn
& 0xffff;
1741 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1744 /* Calculate offsets of saved registers. */
1745 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1746 if (mask
& (1 << regno
))
1749 = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1750 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1753 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1754 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1755 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1757 /* No need to add this to saved_regs -- it's just an arg reg. */
1760 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1761 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1762 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1764 /* No need to add this to saved_regs -- it's just an arg reg. */
1767 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn,
1769 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1771 /* No need to add this to saved_regs -- it's just arg regs. */
1774 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1776 unsigned imm
= insn
& 0xff; /* immediate value */
1777 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1778 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1779 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1781 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1783 unsigned imm
= insn
& 0xff; /* immediate value */
1784 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1785 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1786 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1788 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?,
1790 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1792 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1795 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1796 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1797 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1799 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1801 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1803 int n_saved_fp_regs
;
1804 unsigned int fp_start_reg
, fp_bound_reg
;
1806 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1809 if ((insn
& 0x800) == 0x800) /* N0 is set */
1811 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1812 n_saved_fp_regs
= 3;
1814 n_saved_fp_regs
= 1;
1818 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1819 n_saved_fp_regs
= 2;
1821 n_saved_fp_regs
= 4;
1824 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1825 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1826 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1828 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1829 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
1830 regs
[fp_start_reg
++]);
1833 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1835 /* Allow some special function calls when skipping the
1836 prologue; GCC generates these before storing arguments to
1838 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1840 if (skip_prologue_function (gdbarch
, dest
, 0))
1845 else if ((insn
& 0xf0000000) != 0xe0000000)
1846 break; /* Condition not true, exit early. */
1847 else if (arm_instruction_changes_pc (insn
))
1848 /* Don't scan past anything that might change control flow. */
1850 else if ((insn
& 0xfe500000) == 0xe8100000 /* ldm */
1851 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1852 /* Ignore block loads from the stack, potentially copying
1853 parameters from memory. */
1855 else if ((insn
& 0xfc500000) == 0xe4100000
1856 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1857 /* Similarly ignore single loads from the stack. */
1859 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1860 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1861 register instead of the stack. */
1865 /* The optimizer might shove anything into the prologue,
1866 so we just skip what we don't recognize. */
1867 unrecognized_pc
= current_pc
;
1872 if (unrecognized_pc
== 0)
1873 unrecognized_pc
= current_pc
;
1875 /* The frame size is just the distance from the frame register
1876 to the original stack pointer. */
1877 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1879 /* Frame pointer is fp. */
1880 framereg
= ARM_FP_REGNUM
;
1881 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1885 /* Try the stack pointer... this is a bit desperate. */
1886 framereg
= ARM_SP_REGNUM
;
1887 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1892 cache
->framereg
= framereg
;
1893 cache
->framesize
= framesize
;
1895 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1896 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1897 cache
->saved_regs
[regno
].addr
= offset
;
1901 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1902 paddress (gdbarch
, unrecognized_pc
));
1904 do_cleanups (back_to
);
1905 return unrecognized_pc
;
1909 arm_scan_prologue (struct frame_info
*this_frame
,
1910 struct arm_prologue_cache
*cache
)
1912 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1913 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1915 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
1916 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1917 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1918 pv_t regs
[ARM_FPS_REGNUM
];
1919 struct pv_area
*stack
;
1920 struct cleanup
*back_to
;
1923 /* Assume there is no frame until proven otherwise. */
1924 cache
->framereg
= ARM_SP_REGNUM
;
1925 cache
->framesize
= 0;
1927 /* Check for Thumb prologue. */
1928 if (arm_frame_is_thumb (this_frame
))
1930 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1934 /* Find the function prologue. If we can't find the function in
1935 the symbol table, peek in the stack frame to find the PC. */
1936 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1939 /* One way to find the end of the prologue (which works well
1940 for unoptimized code) is to do the following:
1942 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1945 prologue_end = prev_pc;
1946 else if (sal.end < prologue_end)
1947 prologue_end = sal.end;
1949 This mechanism is very accurate so long as the optimizer
1950 doesn't move any instructions from the function body into the
1951 prologue. If this happens, sal.end will be the last
1952 instruction in the first hunk of prologue code just before
1953 the first instruction that the scheduler has moved from
1954 the body to the prologue.
1956 In order to make sure that we scan all of the prologue
1957 instructions, we use a slightly less accurate mechanism which
1958 may scan more than necessary. To help compensate for this
1959 lack of accuracy, the prologue scanning loop below contains
1960 several clauses which'll cause the loop to terminate early if
1961 an implausible prologue instruction is encountered.
1967 is a suitable endpoint since it accounts for the largest
1968 possible prologue plus up to five instructions inserted by
1971 if (prologue_end
> prologue_start
+ 64)
1973 prologue_end
= prologue_start
+ 64; /* See above. */
1978 /* We have no symbol information. Our only option is to assume this
1979 function has a standard stack frame and the normal frame register.
1980 Then, we can find the value of our frame pointer on entrance to
1981 the callee (or at the present moment if this is the innermost frame).
1982 The value stored there should be the address of the stmfd + 8. */
1983 CORE_ADDR frame_loc
;
1984 LONGEST return_value
;
1986 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
1987 if (!safe_read_memory_integer (frame_loc
, 4, byte_order
, &return_value
))
1991 prologue_start
= gdbarch_addr_bits_remove
1992 (gdbarch
, return_value
) - 8;
1993 prologue_end
= prologue_start
+ 64; /* See above. */
1997 if (prev_pc
< prologue_end
)
1998 prologue_end
= prev_pc
;
2000 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
2003 static struct arm_prologue_cache
*
2004 arm_make_prologue_cache (struct frame_info
*this_frame
)
2007 struct arm_prologue_cache
*cache
;
2008 CORE_ADDR unwound_fp
;
2010 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2011 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2013 arm_scan_prologue (this_frame
, cache
);
2015 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
2016 if (unwound_fp
== 0)
2019 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
2021 /* Calculate actual addresses of saved registers using offsets
2022 determined by arm_scan_prologue. */
2023 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
2024 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
2025 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
2030 /* Our frame ID for a normal frame is the current function's starting PC
2031 and the caller's SP when we were called. */
2034 arm_prologue_this_id (struct frame_info
*this_frame
,
2036 struct frame_id
*this_id
)
2038 struct arm_prologue_cache
*cache
;
2042 if (*this_cache
== NULL
)
2043 *this_cache
= arm_make_prologue_cache (this_frame
);
2044 cache
= *this_cache
;
2046 /* This is meant to halt the backtrace at "_start". */
2047 pc
= get_frame_pc (this_frame
);
2048 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
2051 /* If we've hit a wall, stop. */
2052 if (cache
->prev_sp
== 0)
2055 /* Use function start address as part of the frame ID. If we cannot
2056 identify the start address (due to missing symbol information),
2057 fall back to just using the current PC. */
2058 func
= get_frame_func (this_frame
);
2062 id
= frame_id_build (cache
->prev_sp
, func
);
2066 static struct value
*
2067 arm_prologue_prev_register (struct frame_info
*this_frame
,
2071 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2072 struct arm_prologue_cache
*cache
;
2074 if (*this_cache
== NULL
)
2075 *this_cache
= arm_make_prologue_cache (this_frame
);
2076 cache
= *this_cache
;
2078 /* If we are asked to unwind the PC, then we need to return the LR
2079 instead. The prologue may save PC, but it will point into this
2080 frame's prologue, not the next frame's resume location. Also
2081 strip the saved T bit. A valid LR may have the low bit set, but
2082 a valid PC never does. */
2083 if (prev_regnum
== ARM_PC_REGNUM
)
2087 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2088 return frame_unwind_got_constant (this_frame
, prev_regnum
,
2089 arm_addr_bits_remove (gdbarch
, lr
));
2092 /* SP is generally not saved to the stack, but this frame is
2093 identified by the next frame's stack pointer at the time of the call.
2094 The value was already reconstructed into PREV_SP. */
2095 if (prev_regnum
== ARM_SP_REGNUM
)
2096 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
2098 /* The CPSR may have been changed by the call instruction and by the
2099 called function. The only bit we can reconstruct is the T bit,
2100 by checking the low bit of LR as of the call. This is a reliable
2101 indicator of Thumb-ness except for some ARM v4T pre-interworking
2102 Thumb code, which could get away with a clear low bit as long as
2103 the called function did not use bx. Guess that all other
2104 bits are unchanged; the condition flags are presumably lost,
2105 but the processor status is likely valid. */
2106 if (prev_regnum
== ARM_PS_REGNUM
)
2109 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
2111 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
2112 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2113 if (IS_THUMB_ADDR (lr
))
2117 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
2120 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
2124 struct frame_unwind arm_prologue_unwind
= {
2126 default_frame_unwind_stop_reason
,
2127 arm_prologue_this_id
,
2128 arm_prologue_prev_register
,
2130 default_frame_sniffer
2133 /* Maintain a list of ARM exception table entries per objfile, similar to the
2134 list of mapping symbols. We only cache entries for standard ARM-defined
2135 personality routines; the cache will contain only the frame unwinding
2136 instructions associated with the entry (not the descriptors). */
2138 static const struct objfile_data
*arm_exidx_data_key
;
2140 struct arm_exidx_entry
2145 typedef struct arm_exidx_entry arm_exidx_entry_s
;
2146 DEF_VEC_O(arm_exidx_entry_s
);
2148 struct arm_exidx_data
2150 VEC(arm_exidx_entry_s
) **section_maps
;
2154 arm_exidx_data_free (struct objfile
*objfile
, void *arg
)
2156 struct arm_exidx_data
*data
= arg
;
2159 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
2160 VEC_free (arm_exidx_entry_s
, data
->section_maps
[i
]);
2164 arm_compare_exidx_entries (const struct arm_exidx_entry
*lhs
,
2165 const struct arm_exidx_entry
*rhs
)
2167 return lhs
->addr
< rhs
->addr
;
2170 static struct obj_section
*
2171 arm_obj_section_from_vma (struct objfile
*objfile
, bfd_vma vma
)
2173 struct obj_section
*osect
;
2175 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
2176 if (bfd_get_section_flags (objfile
->obfd
,
2177 osect
->the_bfd_section
) & SEC_ALLOC
)
2179 bfd_vma start
, size
;
2180 start
= bfd_get_section_vma (objfile
->obfd
, osect
->the_bfd_section
);
2181 size
= bfd_get_section_size (osect
->the_bfd_section
);
2183 if (start
<= vma
&& vma
< start
+ size
)
2190 /* Parse contents of exception table and exception index sections
2191 of OBJFILE, and fill in the exception table entry cache.
2193 For each entry that refers to a standard ARM-defined personality
2194 routine, extract the frame unwinding instructions (from either
2195 the index or the table section). The unwinding instructions
2197 - extracting them from the rest of the table data
2198 - converting to host endianness
2199 - appending the implicit 0xb0 ("Finish") code
2201 The extracted and normalized instructions are stored for later
2202 retrieval by the arm_find_exidx_entry routine. */
2205 arm_exidx_new_objfile (struct objfile
*objfile
)
2207 struct cleanup
*cleanups
;
2208 struct arm_exidx_data
*data
;
2209 asection
*exidx
, *extab
;
2210 bfd_vma exidx_vma
= 0, extab_vma
= 0;
2211 bfd_size_type exidx_size
= 0, extab_size
= 0;
2212 gdb_byte
*exidx_data
= NULL
, *extab_data
= NULL
;
2215 /* If we've already touched this file, do nothing. */
2216 if (!objfile
|| objfile_data (objfile
, arm_exidx_data_key
) != NULL
)
2218 cleanups
= make_cleanup (null_cleanup
, NULL
);
2220 /* Read contents of exception table and index. */
2221 exidx
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.exidx");
2224 exidx_vma
= bfd_section_vma (objfile
->obfd
, exidx
);
2225 exidx_size
= bfd_get_section_size (exidx
);
2226 exidx_data
= xmalloc (exidx_size
);
2227 make_cleanup (xfree
, exidx_data
);
2229 if (!bfd_get_section_contents (objfile
->obfd
, exidx
,
2230 exidx_data
, 0, exidx_size
))
2232 do_cleanups (cleanups
);
2237 extab
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.extab");
2240 extab_vma
= bfd_section_vma (objfile
->obfd
, extab
);
2241 extab_size
= bfd_get_section_size (extab
);
2242 extab_data
= xmalloc (extab_size
);
2243 make_cleanup (xfree
, extab_data
);
2245 if (!bfd_get_section_contents (objfile
->obfd
, extab
,
2246 extab_data
, 0, extab_size
))
2248 do_cleanups (cleanups
);
2253 /* Allocate exception table data structure. */
2254 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
, struct arm_exidx_data
);
2255 set_objfile_data (objfile
, arm_exidx_data_key
, data
);
2256 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2257 objfile
->obfd
->section_count
,
2258 VEC(arm_exidx_entry_s
) *);
2260 /* Fill in exception table. */
2261 for (i
= 0; i
< exidx_size
/ 8; i
++)
2263 struct arm_exidx_entry new_exidx_entry
;
2264 bfd_vma idx
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8);
2265 bfd_vma val
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8 + 4);
2266 bfd_vma addr
= 0, word
= 0;
2267 int n_bytes
= 0, n_words
= 0;
2268 struct obj_section
*sec
;
2269 gdb_byte
*entry
= NULL
;
2271 /* Extract address of start of function. */
2272 idx
= ((idx
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2273 idx
+= exidx_vma
+ i
* 8;
2275 /* Find section containing function and compute section offset. */
2276 sec
= arm_obj_section_from_vma (objfile
, idx
);
2279 idx
-= bfd_get_section_vma (objfile
->obfd
, sec
->the_bfd_section
);
2281 /* Determine address of exception table entry. */
2284 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2286 else if ((val
& 0xff000000) == 0x80000000)
2288 /* Exception table entry embedded in .ARM.exidx
2289 -- must be short form. */
2293 else if (!(val
& 0x80000000))
2295 /* Exception table entry in .ARM.extab. */
2296 addr
= ((val
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2297 addr
+= exidx_vma
+ i
* 8 + 4;
2299 if (addr
>= extab_vma
&& addr
+ 4 <= extab_vma
+ extab_size
)
2301 word
= bfd_h_get_32 (objfile
->obfd
,
2302 extab_data
+ addr
- extab_vma
);
2305 if ((word
& 0xff000000) == 0x80000000)
2310 else if ((word
& 0xff000000) == 0x81000000
2311 || (word
& 0xff000000) == 0x82000000)
2315 n_words
= ((word
>> 16) & 0xff);
2317 else if (!(word
& 0x80000000))
2320 struct obj_section
*pers_sec
;
2321 int gnu_personality
= 0;
2323 /* Custom personality routine. */
2324 pers
= ((word
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2325 pers
= UNMAKE_THUMB_ADDR (pers
+ addr
- 4);
2327 /* Check whether we've got one of the variants of the
2328 GNU personality routines. */
2329 pers_sec
= arm_obj_section_from_vma (objfile
, pers
);
2332 static const char *personality
[] =
2334 "__gcc_personality_v0",
2335 "__gxx_personality_v0",
2336 "__gcj_personality_v0",
2337 "__gnu_objc_personality_v0",
2341 CORE_ADDR pc
= pers
+ obj_section_offset (pers_sec
);
2344 for (k
= 0; personality
[k
]; k
++)
2345 if (lookup_minimal_symbol_by_pc_name
2346 (pc
, personality
[k
], objfile
))
2348 gnu_personality
= 1;
2353 /* If so, the next word contains a word count in the high
2354 byte, followed by the same unwind instructions as the
2355 pre-defined forms. */
2357 && addr
+ 4 <= extab_vma
+ extab_size
)
2359 word
= bfd_h_get_32 (objfile
->obfd
,
2360 extab_data
+ addr
- extab_vma
);
2363 n_words
= ((word
>> 24) & 0xff);
2369 /* Sanity check address. */
2371 if (addr
< extab_vma
|| addr
+ 4 * n_words
> extab_vma
+ extab_size
)
2372 n_words
= n_bytes
= 0;
2374 /* The unwind instructions reside in WORD (only the N_BYTES least
2375 significant bytes are valid), followed by N_WORDS words in the
2376 extab section starting at ADDR. */
2377 if (n_bytes
|| n_words
)
2379 gdb_byte
*p
= entry
= obstack_alloc (&objfile
->objfile_obstack
,
2380 n_bytes
+ n_words
* 4 + 1);
2383 *p
++ = (gdb_byte
) ((word
>> (8 * n_bytes
)) & 0xff);
2387 word
= bfd_h_get_32 (objfile
->obfd
,
2388 extab_data
+ addr
- extab_vma
);
2391 *p
++ = (gdb_byte
) ((word
>> 24) & 0xff);
2392 *p
++ = (gdb_byte
) ((word
>> 16) & 0xff);
2393 *p
++ = (gdb_byte
) ((word
>> 8) & 0xff);
2394 *p
++ = (gdb_byte
) (word
& 0xff);
2397 /* Implied "Finish" to terminate the list. */
2401 /* Push entry onto vector. They are guaranteed to always
2402 appear in order of increasing addresses. */
2403 new_exidx_entry
.addr
= idx
;
2404 new_exidx_entry
.entry
= entry
;
2405 VEC_safe_push (arm_exidx_entry_s
,
2406 data
->section_maps
[sec
->the_bfd_section
->index
],
2410 do_cleanups (cleanups
);
2413 /* Search for the exception table entry covering MEMADDR. If one is found,
2414 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2415 set *START to the start of the region covered by this entry. */
2418 arm_find_exidx_entry (CORE_ADDR memaddr
, CORE_ADDR
*start
)
2420 struct obj_section
*sec
;
2422 sec
= find_pc_section (memaddr
);
2425 struct arm_exidx_data
*data
;
2426 VEC(arm_exidx_entry_s
) *map
;
2427 struct arm_exidx_entry map_key
= { memaddr
- obj_section_addr (sec
), 0 };
2430 data
= objfile_data (sec
->objfile
, arm_exidx_data_key
);
2433 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
2434 if (!VEC_empty (arm_exidx_entry_s
, map
))
2436 struct arm_exidx_entry
*map_sym
;
2438 idx
= VEC_lower_bound (arm_exidx_entry_s
, map
, &map_key
,
2439 arm_compare_exidx_entries
);
2441 /* VEC_lower_bound finds the earliest ordered insertion
2442 point. If the following symbol starts at this exact
2443 address, we use that; otherwise, the preceding
2444 exception table entry covers this address. */
2445 if (idx
< VEC_length (arm_exidx_entry_s
, map
))
2447 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
);
2448 if (map_sym
->addr
== map_key
.addr
)
2451 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2452 return map_sym
->entry
;
2458 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
- 1);
2460 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2461 return map_sym
->entry
;
2470 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2471 instruction list from the ARM exception table entry ENTRY, allocate and
2472 return a prologue cache structure describing how to unwind this frame.
2474 Return NULL if the unwinding instruction list contains a "spare",
2475 "reserved" or "refuse to unwind" instruction as defined in section
2476 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2477 for the ARM Architecture" document. */
2479 static struct arm_prologue_cache
*
2480 arm_exidx_fill_cache (struct frame_info
*this_frame
, gdb_byte
*entry
)
2485 struct arm_prologue_cache
*cache
;
2486 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2487 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2493 /* Whenever we reload SP, we actually have to retrieve its
2494 actual value in the current frame. */
2497 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2499 int reg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2500 vsp
= get_frame_register_unsigned (this_frame
, reg
);
2504 CORE_ADDR addr
= cache
->saved_regs
[ARM_SP_REGNUM
].addr
;
2505 vsp
= get_frame_memory_unsigned (this_frame
, addr
, 4);
2511 /* Decode next unwind instruction. */
2514 if ((insn
& 0xc0) == 0)
2516 int offset
= insn
& 0x3f;
2517 vsp
+= (offset
<< 2) + 4;
2519 else if ((insn
& 0xc0) == 0x40)
2521 int offset
= insn
& 0x3f;
2522 vsp
-= (offset
<< 2) + 4;
2524 else if ((insn
& 0xf0) == 0x80)
2526 int mask
= ((insn
& 0xf) << 8) | *entry
++;
2529 /* The special case of an all-zero mask identifies
2530 "Refuse to unwind". We return NULL to fall back
2531 to the prologue analyzer. */
2535 /* Pop registers r4..r15 under mask. */
2536 for (i
= 0; i
< 12; i
++)
2537 if (mask
& (1 << i
))
2539 cache
->saved_regs
[4 + i
].addr
= vsp
;
2543 /* Special-case popping SP -- we need to reload vsp. */
2544 if (mask
& (1 << (ARM_SP_REGNUM
- 4)))
2547 else if ((insn
& 0xf0) == 0x90)
2549 int reg
= insn
& 0xf;
2551 /* Reserved cases. */
2552 if (reg
== ARM_SP_REGNUM
|| reg
== ARM_PC_REGNUM
)
2555 /* Set SP from another register and mark VSP for reload. */
2556 cache
->saved_regs
[ARM_SP_REGNUM
] = cache
->saved_regs
[reg
];
2559 else if ((insn
& 0xf0) == 0xa0)
2561 int count
= insn
& 0x7;
2562 int pop_lr
= (insn
& 0x8) != 0;
2565 /* Pop r4..r[4+count]. */
2566 for (i
= 0; i
<= count
; i
++)
2568 cache
->saved_regs
[4 + i
].addr
= vsp
;
2572 /* If indicated by flag, pop LR as well. */
2575 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= vsp
;
2579 else if (insn
== 0xb0)
2581 /* We could only have updated PC by popping into it; if so, it
2582 will show up as address. Otherwise, copy LR into PC. */
2583 if (!trad_frame_addr_p (cache
->saved_regs
, ARM_PC_REGNUM
))
2584 cache
->saved_regs
[ARM_PC_REGNUM
]
2585 = cache
->saved_regs
[ARM_LR_REGNUM
];
2590 else if (insn
== 0xb1)
2592 int mask
= *entry
++;
2595 /* All-zero mask and mask >= 16 is "spare". */
2596 if (mask
== 0 || mask
>= 16)
2599 /* Pop r0..r3 under mask. */
2600 for (i
= 0; i
< 4; i
++)
2601 if (mask
& (1 << i
))
2603 cache
->saved_regs
[i
].addr
= vsp
;
2607 else if (insn
== 0xb2)
2609 ULONGEST offset
= 0;
2614 offset
|= (*entry
& 0x7f) << shift
;
2617 while (*entry
++ & 0x80);
2619 vsp
+= 0x204 + (offset
<< 2);
2621 else if (insn
== 0xb3)
2623 int start
= *entry
>> 4;
2624 int count
= (*entry
++) & 0xf;
2627 /* Only registers D0..D15 are valid here. */
2628 if (start
+ count
>= 16)
2631 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2632 for (i
= 0; i
<= count
; i
++)
2634 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2638 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2641 else if ((insn
& 0xf8) == 0xb8)
2643 int count
= insn
& 0x7;
2646 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2647 for (i
= 0; i
<= count
; i
++)
2649 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2653 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2656 else if (insn
== 0xc6)
2658 int start
= *entry
>> 4;
2659 int count
= (*entry
++) & 0xf;
2662 /* Only registers WR0..WR15 are valid. */
2663 if (start
+ count
>= 16)
2666 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2667 for (i
= 0; i
<= count
; i
++)
2669 cache
->saved_regs
[ARM_WR0_REGNUM
+ start
+ i
].addr
= vsp
;
2673 else if (insn
== 0xc7)
2675 int mask
= *entry
++;
2678 /* All-zero mask and mask >= 16 is "spare". */
2679 if (mask
== 0 || mask
>= 16)
2682 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2683 for (i
= 0; i
< 4; i
++)
2684 if (mask
& (1 << i
))
2686 cache
->saved_regs
[ARM_WCGR0_REGNUM
+ i
].addr
= vsp
;
2690 else if ((insn
& 0xf8) == 0xc0)
2692 int count
= insn
& 0x7;
2695 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2696 for (i
= 0; i
<= count
; i
++)
2698 cache
->saved_regs
[ARM_WR0_REGNUM
+ 10 + i
].addr
= vsp
;
2702 else if (insn
== 0xc8)
2704 int start
= *entry
>> 4;
2705 int count
= (*entry
++) & 0xf;
2708 /* Only registers D0..D31 are valid. */
2709 if (start
+ count
>= 16)
2712 /* Pop VFP double-precision registers
2713 D[16+start]..D[16+start+count]. */
2714 for (i
= 0; i
<= count
; i
++)
2716 cache
->saved_regs
[ARM_D0_REGNUM
+ 16 + start
+ i
].addr
= vsp
;
2720 else if (insn
== 0xc9)
2722 int start
= *entry
>> 4;
2723 int count
= (*entry
++) & 0xf;
2726 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2727 for (i
= 0; i
<= count
; i
++)
2729 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2733 else if ((insn
& 0xf8) == 0xd0)
2735 int count
= insn
& 0x7;
2738 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2739 for (i
= 0; i
<= count
; i
++)
2741 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2747 /* Everything else is "spare". */
2752 /* If we restore SP from a register, assume this was the frame register.
2753 Otherwise just fall back to SP as frame register. */
2754 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2755 cache
->framereg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2757 cache
->framereg
= ARM_SP_REGNUM
;
2759 /* Determine offset to previous frame. */
2761 = vsp
- get_frame_register_unsigned (this_frame
, cache
->framereg
);
2763 /* We already got the previous SP. */
2764 cache
->prev_sp
= vsp
;
2769 /* Unwinding via ARM exception table entries. Note that the sniffer
2770 already computes a filled-in prologue cache, which is then used
2771 with the same arm_prologue_this_id and arm_prologue_prev_register
2772 routines also used for prologue-parsing based unwinding. */
2775 arm_exidx_unwind_sniffer (const struct frame_unwind
*self
,
2776 struct frame_info
*this_frame
,
2777 void **this_prologue_cache
)
2779 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2780 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2781 CORE_ADDR addr_in_block
, exidx_region
, func_start
;
2782 struct arm_prologue_cache
*cache
;
2785 /* See if we have an ARM exception table entry covering this address. */
2786 addr_in_block
= get_frame_address_in_block (this_frame
);
2787 entry
= arm_find_exidx_entry (addr_in_block
, &exidx_region
);
2791 /* The ARM exception table does not describe unwind information
2792 for arbitrary PC values, but is guaranteed to be correct only
2793 at call sites. We have to decide here whether we want to use
2794 ARM exception table information for this frame, or fall back
2795 to using prologue parsing. (Note that if we have DWARF CFI,
2796 this sniffer isn't even called -- CFI is always preferred.)
2798 Before we make this decision, however, we check whether we
2799 actually have *symbol* information for the current frame.
2800 If not, prologue parsing would not work anyway, so we might
2801 as well use the exception table and hope for the best. */
2802 if (find_pc_partial_function (addr_in_block
, NULL
, &func_start
, NULL
))
2806 /* If the next frame is "normal", we are at a call site in this
2807 frame, so exception information is guaranteed to be valid. */
2808 if (get_next_frame (this_frame
)
2809 && get_frame_type (get_next_frame (this_frame
)) == NORMAL_FRAME
)
2812 /* We also assume exception information is valid if we're currently
2813 blocked in a system call. The system library is supposed to
2814 ensure this, so that e.g. pthread cancellation works. */
2815 if (arm_frame_is_thumb (this_frame
))
2819 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 2, 2,
2820 byte_order_for_code
, &insn
)
2821 && (insn
& 0xff00) == 0xdf00 /* svc */)
2828 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 4, 4,
2829 byte_order_for_code
, &insn
)
2830 && (insn
& 0x0f000000) == 0x0f000000 /* svc */)
2834 /* Bail out if we don't know that exception information is valid. */
2838 /* The ARM exception index does not mark the *end* of the region
2839 covered by the entry, and some functions will not have any entry.
2840 To correctly recognize the end of the covered region, the linker
2841 should have inserted dummy records with a CANTUNWIND marker.
2843 Unfortunately, current versions of GNU ld do not reliably do
2844 this, and thus we may have found an incorrect entry above.
2845 As a (temporary) sanity check, we only use the entry if it
2846 lies *within* the bounds of the function. Note that this check
2847 might reject perfectly valid entries that just happen to cover
2848 multiple functions; therefore this check ought to be removed
2849 once the linker is fixed. */
2850 if (func_start
> exidx_region
)
2854 /* Decode the list of unwinding instructions into a prologue cache.
2855 Note that this may fail due to e.g. a "refuse to unwind" code. */
2856 cache
= arm_exidx_fill_cache (this_frame
, entry
);
2860 *this_prologue_cache
= cache
;
2864 struct frame_unwind arm_exidx_unwind
= {
2866 default_frame_unwind_stop_reason
,
2867 arm_prologue_this_id
,
2868 arm_prologue_prev_register
,
2870 arm_exidx_unwind_sniffer
2873 static struct arm_prologue_cache
*
2874 arm_make_stub_cache (struct frame_info
*this_frame
)
2876 struct arm_prologue_cache
*cache
;
2878 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2879 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2881 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2886 /* Our frame ID for a stub frame is the current SP and LR. */
2889 arm_stub_this_id (struct frame_info
*this_frame
,
2891 struct frame_id
*this_id
)
2893 struct arm_prologue_cache
*cache
;
2895 if (*this_cache
== NULL
)
2896 *this_cache
= arm_make_stub_cache (this_frame
);
2897 cache
= *this_cache
;
2899 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
2903 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
2904 struct frame_info
*this_frame
,
2905 void **this_prologue_cache
)
2907 CORE_ADDR addr_in_block
;
2910 addr_in_block
= get_frame_address_in_block (this_frame
);
2911 if (in_plt_section (addr_in_block
, NULL
)
2912 /* We also use the stub winder if the target memory is unreadable
2913 to avoid having the prologue unwinder trying to read it. */
2914 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2920 struct frame_unwind arm_stub_unwind
= {
2922 default_frame_unwind_stop_reason
,
2924 arm_prologue_prev_register
,
2926 arm_stub_unwind_sniffer
2930 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
2932 struct arm_prologue_cache
*cache
;
2934 if (*this_cache
== NULL
)
2935 *this_cache
= arm_make_prologue_cache (this_frame
);
2936 cache
= *this_cache
;
2938 return cache
->prev_sp
- cache
->framesize
;
2941 struct frame_base arm_normal_base
= {
2942 &arm_prologue_unwind
,
2943 arm_normal_frame_base
,
2944 arm_normal_frame_base
,
2945 arm_normal_frame_base
2948 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
2949 dummy frame. The frame ID's base needs to match the TOS value
2950 saved by save_dummy_frame_tos() and returned from
2951 arm_push_dummy_call, and the PC needs to match the dummy frame's
2954 static struct frame_id
2955 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2957 return frame_id_build (get_frame_register_unsigned (this_frame
,
2959 get_frame_pc (this_frame
));
2962 /* Given THIS_FRAME, find the previous frame's resume PC (which will
2963 be used to construct the previous frame's ID, after looking up the
2964 containing function). */
2967 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2970 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
2971 return arm_addr_bits_remove (gdbarch
, pc
);
2975 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2977 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2980 static struct value
*
2981 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2984 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
2986 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
2991 /* The PC is normally copied from the return column, which
2992 describes saves of LR. However, that version may have an
2993 extra bit set to indicate Thumb state. The bit is not
2995 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2996 return frame_unwind_got_constant (this_frame
, regnum
,
2997 arm_addr_bits_remove (gdbarch
, lr
));
3000 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3001 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
3002 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3003 if (IS_THUMB_ADDR (lr
))
3007 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
3010 internal_error (__FILE__
, __LINE__
,
3011 _("Unexpected register %d"), regnum
);
3016 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3017 struct dwarf2_frame_state_reg
*reg
,
3018 struct frame_info
*this_frame
)
3024 reg
->how
= DWARF2_FRAME_REG_FN
;
3025 reg
->loc
.fn
= arm_dwarf2_prev_register
;
3028 reg
->how
= DWARF2_FRAME_REG_CFA
;
3033 /* Return true if we are in the function's epilogue, i.e. after the
3034 instruction that destroyed the function's stack frame. */
3037 thumb_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3039 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3040 unsigned int insn
, insn2
;
3041 int found_return
= 0, found_stack_adjust
= 0;
3042 CORE_ADDR func_start
, func_end
;
3046 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3049 /* The epilogue is a sequence of instructions along the following lines:
3051 - add stack frame size to SP or FP
3052 - [if frame pointer used] restore SP from FP
3053 - restore registers from SP [may include PC]
3054 - a return-type instruction [if PC wasn't already restored]
3056 In a first pass, we scan forward from the current PC and verify the
3057 instructions we find as compatible with this sequence, ending in a
3060 However, this is not sufficient to distinguish indirect function calls
3061 within a function from indirect tail calls in the epilogue in some cases.
3062 Therefore, if we didn't already find any SP-changing instruction during
3063 forward scan, we add a backward scanning heuristic to ensure we actually
3064 are in the epilogue. */
3067 while (scan_pc
< func_end
&& !found_return
)
3069 if (target_read_memory (scan_pc
, buf
, 2))
3073 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3075 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3077 else if (insn
== 0x46f7) /* mov pc, lr */
3079 else if (insn
== 0x46bd) /* mov sp, r7 */
3080 found_stack_adjust
= 1;
3081 else if ((insn
& 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3082 found_stack_adjust
= 1;
3083 else if ((insn
& 0xfe00) == 0xbc00) /* pop <registers> */
3085 found_stack_adjust
= 1;
3086 if (insn
& 0x0100) /* <registers> include PC. */
3089 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instruction */
3091 if (target_read_memory (scan_pc
, buf
, 2))
3095 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3097 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3099 found_stack_adjust
= 1;
3100 if (insn2
& 0x8000) /* <registers> include PC. */
3103 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3104 && (insn2
& 0x0fff) == 0x0b04)
3106 found_stack_adjust
= 1;
3107 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
3110 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3111 && (insn2
& 0x0e00) == 0x0a00)
3112 found_stack_adjust
= 1;
3123 /* Since any instruction in the epilogue sequence, with the possible
3124 exception of return itself, updates the stack pointer, we need to
3125 scan backwards for at most one instruction. Try either a 16-bit or
3126 a 32-bit instruction. This is just a heuristic, so we do not worry
3127 too much about false positives. */
3129 if (!found_stack_adjust
)
3131 if (pc
- 4 < func_start
)
3133 if (target_read_memory (pc
- 4, buf
, 4))
3136 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3137 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
3139 if (insn2
== 0x46bd) /* mov sp, r7 */
3140 found_stack_adjust
= 1;
3141 else if ((insn2
& 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3142 found_stack_adjust
= 1;
3143 else if ((insn2
& 0xff00) == 0xbc00) /* pop <registers> without PC */
3144 found_stack_adjust
= 1;
3145 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3146 found_stack_adjust
= 1;
3147 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3148 && (insn2
& 0x0fff) == 0x0b04)
3149 found_stack_adjust
= 1;
3150 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3151 && (insn2
& 0x0e00) == 0x0a00)
3152 found_stack_adjust
= 1;
3155 return found_stack_adjust
;
3158 /* Return true if we are in the function's epilogue, i.e. after the
3159 instruction that destroyed the function's stack frame. */
3162 arm_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3164 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3166 int found_return
, found_stack_adjust
;
3167 CORE_ADDR func_start
, func_end
;
3169 if (arm_pc_is_thumb (gdbarch
, pc
))
3170 return thumb_in_function_epilogue_p (gdbarch
, pc
);
3172 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3175 /* We are in the epilogue if the previous instruction was a stack
3176 adjustment and the next instruction is a possible return (bx, mov
3177 pc, or pop). We could have to scan backwards to find the stack
3178 adjustment, or forwards to find the return, but this is a decent
3179 approximation. First scan forwards. */
3182 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3183 if (bits (insn
, 28, 31) != INST_NV
)
3185 if ((insn
& 0x0ffffff0) == 0x012fff10)
3188 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
3191 else if ((insn
& 0x0fff0000) == 0x08bd0000
3192 && (insn
& 0x0000c000) != 0)
3193 /* POP (LDMIA), including PC or LR. */
3200 /* Scan backwards. This is just a heuristic, so do not worry about
3201 false positives from mode changes. */
3203 if (pc
< func_start
+ 4)
3206 found_stack_adjust
= 0;
3207 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
3208 if (bits (insn
, 28, 31) != INST_NV
)
3210 if ((insn
& 0x0df0f000) == 0x0080d000)
3211 /* ADD SP (register or immediate). */
3212 found_stack_adjust
= 1;
3213 else if ((insn
& 0x0df0f000) == 0x0040d000)
3214 /* SUB SP (register or immediate). */
3215 found_stack_adjust
= 1;
3216 else if ((insn
& 0x0ffffff0) == 0x01a0d000)
3218 found_stack_adjust
= 1;
3219 else if ((insn
& 0x0fff0000) == 0x08bd0000)
3221 found_stack_adjust
= 1;
3222 else if ((insn
& 0x0fff0000) == 0x049d0000)
3223 /* POP of a single register. */
3224 found_stack_adjust
= 1;
3227 if (found_stack_adjust
)
3234 /* When arguments must be pushed onto the stack, they go on in reverse
3235 order. The code below implements a FILO (stack) to do this. */
3240 struct stack_item
*prev
;
3244 static struct stack_item
*
3245 push_stack_item (struct stack_item
*prev
, const void *contents
, int len
)
3247 struct stack_item
*si
;
3248 si
= xmalloc (sizeof (struct stack_item
));
3249 si
->data
= xmalloc (len
);
3252 memcpy (si
->data
, contents
, len
);
3256 static struct stack_item
*
3257 pop_stack_item (struct stack_item
*si
)
3259 struct stack_item
*dead
= si
;
3267 /* Return the alignment (in bytes) of the given type. */
3270 arm_type_align (struct type
*t
)
3276 t
= check_typedef (t
);
3277 switch (TYPE_CODE (t
))
3280 /* Should never happen. */
3281 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
3285 case TYPE_CODE_ENUM
:
3289 case TYPE_CODE_RANGE
:
3291 case TYPE_CODE_CHAR
:
3292 case TYPE_CODE_BOOL
:
3293 return TYPE_LENGTH (t
);
3295 case TYPE_CODE_ARRAY
:
3296 case TYPE_CODE_COMPLEX
:
3297 /* TODO: What about vector types? */
3298 return arm_type_align (TYPE_TARGET_TYPE (t
));
3300 case TYPE_CODE_STRUCT
:
3301 case TYPE_CODE_UNION
:
3303 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
3305 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
3313 /* Possible base types for a candidate for passing and returning in
3316 enum arm_vfp_cprc_base_type
3325 /* The length of one element of base type B. */
3328 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
3332 case VFP_CPRC_SINGLE
:
3334 case VFP_CPRC_DOUBLE
:
3336 case VFP_CPRC_VEC64
:
3338 case VFP_CPRC_VEC128
:
3341 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3346 /* The character ('s', 'd' or 'q') for the type of VFP register used
3347 for passing base type B. */
3350 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
3354 case VFP_CPRC_SINGLE
:
3356 case VFP_CPRC_DOUBLE
:
3358 case VFP_CPRC_VEC64
:
3360 case VFP_CPRC_VEC128
:
3363 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3368 /* Determine whether T may be part of a candidate for passing and
3369 returning in VFP registers, ignoring the limit on the total number
3370 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3371 classification of the first valid component found; if it is not
3372 VFP_CPRC_UNKNOWN, all components must have the same classification
3373 as *BASE_TYPE. If it is found that T contains a type not permitted
3374 for passing and returning in VFP registers, a type differently
3375 classified from *BASE_TYPE, or two types differently classified
3376 from each other, return -1, otherwise return the total number of
3377 base-type elements found (possibly 0 in an empty structure or
3378 array). Vectors and complex types are not currently supported,
3379 matching the generic AAPCS support. */
3382 arm_vfp_cprc_sub_candidate (struct type
*t
,
3383 enum arm_vfp_cprc_base_type
*base_type
)
3385 t
= check_typedef (t
);
3386 switch (TYPE_CODE (t
))
3389 switch (TYPE_LENGTH (t
))
3392 if (*base_type
== VFP_CPRC_UNKNOWN
)
3393 *base_type
= VFP_CPRC_SINGLE
;
3394 else if (*base_type
!= VFP_CPRC_SINGLE
)
3399 if (*base_type
== VFP_CPRC_UNKNOWN
)
3400 *base_type
= VFP_CPRC_DOUBLE
;
3401 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3410 case TYPE_CODE_ARRAY
:
3414 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
), base_type
);
3417 if (TYPE_LENGTH (t
) == 0)
3419 gdb_assert (count
== 0);
3422 else if (count
== 0)
3424 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3425 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
3426 return TYPE_LENGTH (t
) / unitlen
;
3430 case TYPE_CODE_STRUCT
:
3435 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3437 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3439 if (sub_count
== -1)
3443 if (TYPE_LENGTH (t
) == 0)
3445 gdb_assert (count
== 0);
3448 else if (count
== 0)
3450 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3451 if (TYPE_LENGTH (t
) != unitlen
* count
)
3456 case TYPE_CODE_UNION
:
3461 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3463 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3465 if (sub_count
== -1)
3467 count
= (count
> sub_count
? count
: sub_count
);
3469 if (TYPE_LENGTH (t
) == 0)
3471 gdb_assert (count
== 0);
3474 else if (count
== 0)
3476 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3477 if (TYPE_LENGTH (t
) != unitlen
* count
)
3489 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3490 if passed to or returned from a non-variadic function with the VFP
3491 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3492 *BASE_TYPE to the base type for T and *COUNT to the number of
3493 elements of that base type before returning. */
3496 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
3499 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
3500 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
3501 if (c
<= 0 || c
> 4)
3508 /* Return 1 if the VFP ABI should be used for passing arguments to and
3509 returning values from a function of type FUNC_TYPE, 0
3513 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
3515 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3516 /* Variadic functions always use the base ABI. Assume that functions
3517 without debug info are not variadic. */
3518 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
3520 /* The VFP ABI is only supported as a variant of AAPCS. */
3521 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
3523 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
3526 /* We currently only support passing parameters in integer registers, which
3527 conforms with GCC's default model, and VFP argument passing following
3528 the VFP variant of AAPCS. Several other variants exist and
3529 we should probably support some of them based on the selected ABI. */
3532 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3533 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3534 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3535 CORE_ADDR struct_addr
)
3537 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3541 struct stack_item
*si
= NULL
;
3544 unsigned vfp_regs_free
= (1 << 16) - 1;
3546 /* Determine the type of this function and whether the VFP ABI
3548 ftype
= check_typedef (value_type (function
));
3549 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
3550 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
3551 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
3553 /* Set the return address. For the ARM, the return breakpoint is
3554 always at BP_ADDR. */
3555 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
3557 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
3559 /* Walk through the list of args and determine how large a temporary
3560 stack is required. Need to take care here as structs may be
3561 passed on the stack, and we have to push them. */
3564 argreg
= ARM_A1_REGNUM
;
3567 /* The struct_return pointer occupies the first parameter
3568 passing register. */
3572 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
3573 gdbarch_register_name (gdbarch
, argreg
),
3574 paddress (gdbarch
, struct_addr
));
3575 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
3579 for (argnum
= 0; argnum
< nargs
; argnum
++)
3582 struct type
*arg_type
;
3583 struct type
*target_type
;
3584 enum type_code typecode
;
3585 const bfd_byte
*val
;
3587 enum arm_vfp_cprc_base_type vfp_base_type
;
3589 int may_use_core_reg
= 1;
3591 arg_type
= check_typedef (value_type (args
[argnum
]));
3592 len
= TYPE_LENGTH (arg_type
);
3593 target_type
= TYPE_TARGET_TYPE (arg_type
);
3594 typecode
= TYPE_CODE (arg_type
);
3595 val
= value_contents (args
[argnum
]);
3597 align
= arm_type_align (arg_type
);
3598 /* Round alignment up to a whole number of words. */
3599 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
3600 /* Different ABIs have different maximum alignments. */
3601 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
3603 /* The APCS ABI only requires word alignment. */
3604 align
= INT_REGISTER_SIZE
;
3608 /* The AAPCS requires at most doubleword alignment. */
3609 if (align
> INT_REGISTER_SIZE
* 2)
3610 align
= INT_REGISTER_SIZE
* 2;
3614 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
3622 /* Because this is a CPRC it cannot go in a core register or
3623 cause a core register to be skipped for alignment.
3624 Either it goes in VFP registers and the rest of this loop
3625 iteration is skipped for this argument, or it goes on the
3626 stack (and the stack alignment code is correct for this
3628 may_use_core_reg
= 0;
3630 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
3631 shift
= unit_length
/ 4;
3632 mask
= (1 << (shift
* vfp_base_count
)) - 1;
3633 for (regno
= 0; regno
< 16; regno
+= shift
)
3634 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
3643 vfp_regs_free
&= ~(mask
<< regno
);
3644 reg_scaled
= regno
/ shift
;
3645 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
3646 for (i
= 0; i
< vfp_base_count
; i
++)
3650 if (reg_char
== 'q')
3651 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
3652 val
+ i
* unit_length
);
3655 sprintf (name_buf
, "%c%d", reg_char
, reg_scaled
+ i
);
3656 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3658 regcache_cooked_write (regcache
, regnum
,
3659 val
+ i
* unit_length
);
3666 /* This CPRC could not go in VFP registers, so all VFP
3667 registers are now marked as used. */
3672 /* Push stack padding for dowubleword alignment. */
3673 if (nstack
& (align
- 1))
3675 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3676 nstack
+= INT_REGISTER_SIZE
;
3679 /* Doubleword aligned quantities must go in even register pairs. */
3680 if (may_use_core_reg
3681 && argreg
<= ARM_LAST_ARG_REGNUM
3682 && align
> INT_REGISTER_SIZE
3686 /* If the argument is a pointer to a function, and it is a
3687 Thumb function, create a LOCAL copy of the value and set
3688 the THUMB bit in it. */
3689 if (TYPE_CODE_PTR
== typecode
3690 && target_type
!= NULL
3691 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
3693 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
3694 if (arm_pc_is_thumb (gdbarch
, regval
))
3696 bfd_byte
*copy
= alloca (len
);
3697 store_unsigned_integer (copy
, len
, byte_order
,
3698 MAKE_THUMB_ADDR (regval
));
3703 /* Copy the argument to general registers or the stack in
3704 register-sized pieces. Large arguments are split between
3705 registers and stack. */
3708 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
3710 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
3712 /* The argument is being passed in a general purpose
3715 = extract_unsigned_integer (val
, partial_len
, byte_order
);
3716 if (byte_order
== BFD_ENDIAN_BIG
)
3717 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
3719 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
3721 gdbarch_register_name
3723 phex (regval
, INT_REGISTER_SIZE
));
3724 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3729 /* Push the arguments onto the stack. */
3731 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
3733 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3734 nstack
+= INT_REGISTER_SIZE
;
3741 /* If we have an odd number of words to push, then decrement the stack
3742 by one word now, so first stack argument will be dword aligned. */
3749 write_memory (sp
, si
->data
, si
->len
);
3750 si
= pop_stack_item (si
);
3753 /* Finally, update teh SP register. */
3754 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
3760 /* Always align the frame to an 8-byte boundary. This is required on
3761 some platforms and harmless on the rest. */
3764 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3766 /* Align the stack to eight bytes. */
3767 return sp
& ~ (CORE_ADDR
) 7;
3771 print_fpu_flags (int flags
)
3773 if (flags
& (1 << 0))
3774 fputs ("IVO ", stdout
);
3775 if (flags
& (1 << 1))
3776 fputs ("DVZ ", stdout
);
3777 if (flags
& (1 << 2))
3778 fputs ("OFL ", stdout
);
3779 if (flags
& (1 << 3))
3780 fputs ("UFL ", stdout
);
3781 if (flags
& (1 << 4))
3782 fputs ("INX ", stdout
);
3786 /* Print interesting information about the floating point processor
3787 (if present) or emulator. */
3789 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
3790 struct frame_info
*frame
, const char *args
)
3792 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
3795 type
= (status
>> 24) & 127;
3796 if (status
& (1 << 31))
3797 printf (_("Hardware FPU type %d\n"), type
);
3799 printf (_("Software FPU type %d\n"), type
);
3800 /* i18n: [floating point unit] mask */
3801 fputs (_("mask: "), stdout
);
3802 print_fpu_flags (status
>> 16);
3803 /* i18n: [floating point unit] flags */
3804 fputs (_("flags: "), stdout
);
3805 print_fpu_flags (status
);
3808 /* Construct the ARM extended floating point type. */
3809 static struct type
*
3810 arm_ext_type (struct gdbarch
*gdbarch
)
3812 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3814 if (!tdep
->arm_ext_type
)
3816 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
3817 floatformats_arm_ext
);
3819 return tdep
->arm_ext_type
;
3822 static struct type
*
3823 arm_neon_double_type (struct gdbarch
*gdbarch
)
3825 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3827 if (tdep
->neon_double_type
== NULL
)
3829 struct type
*t
, *elem
;
3831 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
3833 elem
= builtin_type (gdbarch
)->builtin_uint8
;
3834 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
3835 elem
= builtin_type (gdbarch
)->builtin_uint16
;
3836 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
3837 elem
= builtin_type (gdbarch
)->builtin_uint32
;
3838 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
3839 elem
= builtin_type (gdbarch
)->builtin_uint64
;
3840 append_composite_type_field (t
, "u64", elem
);
3841 elem
= builtin_type (gdbarch
)->builtin_float
;
3842 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
3843 elem
= builtin_type (gdbarch
)->builtin_double
;
3844 append_composite_type_field (t
, "f64", elem
);
3846 TYPE_VECTOR (t
) = 1;
3847 TYPE_NAME (t
) = "neon_d";
3848 tdep
->neon_double_type
= t
;
3851 return tdep
->neon_double_type
;
3854 /* FIXME: The vector types are not correctly ordered on big-endian
3855 targets. Just as s0 is the low bits of d0, d0[0] is also the low
3856 bits of d0 - regardless of what unit size is being held in d0. So
3857 the offset of the first uint8 in d0 is 7, but the offset of the
3858 first float is 4. This code works as-is for little-endian
3861 static struct type
*
3862 arm_neon_quad_type (struct gdbarch
*gdbarch
)
3864 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3866 if (tdep
->neon_quad_type
== NULL
)
3868 struct type
*t
, *elem
;
3870 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
3872 elem
= builtin_type (gdbarch
)->builtin_uint8
;
3873 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
3874 elem
= builtin_type (gdbarch
)->builtin_uint16
;
3875 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
3876 elem
= builtin_type (gdbarch
)->builtin_uint32
;
3877 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
3878 elem
= builtin_type (gdbarch
)->builtin_uint64
;
3879 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
3880 elem
= builtin_type (gdbarch
)->builtin_float
;
3881 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
3882 elem
= builtin_type (gdbarch
)->builtin_double
;
3883 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
3885 TYPE_VECTOR (t
) = 1;
3886 TYPE_NAME (t
) = "neon_q";
3887 tdep
->neon_quad_type
= t
;
3890 return tdep
->neon_quad_type
;
3893 /* Return the GDB type object for the "standard" data type of data in
3896 static struct type
*
3897 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
3899 int num_regs
= gdbarch_num_regs (gdbarch
);
3901 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
3902 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
3903 return builtin_type (gdbarch
)->builtin_float
;
3905 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
3906 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
3907 return arm_neon_quad_type (gdbarch
);
3909 /* If the target description has register information, we are only
3910 in this function so that we can override the types of
3911 double-precision registers for NEON. */
3912 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
3914 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
3916 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
3917 && TYPE_CODE (t
) == TYPE_CODE_FLT
3918 && gdbarch_tdep (gdbarch
)->have_neon
)
3919 return arm_neon_double_type (gdbarch
);
3924 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
3926 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
3927 return builtin_type (gdbarch
)->builtin_void
;
3929 return arm_ext_type (gdbarch
);
3931 else if (regnum
== ARM_SP_REGNUM
)
3932 return builtin_type (gdbarch
)->builtin_data_ptr
;
3933 else if (regnum
== ARM_PC_REGNUM
)
3934 return builtin_type (gdbarch
)->builtin_func_ptr
;
3935 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
3936 /* These registers are only supported on targets which supply
3937 an XML description. */
3938 return builtin_type (gdbarch
)->builtin_int0
;
3940 return builtin_type (gdbarch
)->builtin_uint32
;
3943 /* Map a DWARF register REGNUM onto the appropriate GDB register
3947 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
3949 /* Core integer regs. */
3950 if (reg
>= 0 && reg
<= 15)
3953 /* Legacy FPA encoding. These were once used in a way which
3954 overlapped with VFP register numbering, so their use is
3955 discouraged, but GDB doesn't support the ARM toolchain
3956 which used them for VFP. */
3957 if (reg
>= 16 && reg
<= 23)
3958 return ARM_F0_REGNUM
+ reg
- 16;
3960 /* New assignments for the FPA registers. */
3961 if (reg
>= 96 && reg
<= 103)
3962 return ARM_F0_REGNUM
+ reg
- 96;
3964 /* WMMX register assignments. */
3965 if (reg
>= 104 && reg
<= 111)
3966 return ARM_WCGR0_REGNUM
+ reg
- 104;
3968 if (reg
>= 112 && reg
<= 127)
3969 return ARM_WR0_REGNUM
+ reg
- 112;
3971 if (reg
>= 192 && reg
<= 199)
3972 return ARM_WC0_REGNUM
+ reg
- 192;
3974 /* VFP v2 registers. A double precision value is actually
3975 in d1 rather than s2, but the ABI only defines numbering
3976 for the single precision registers. This will "just work"
3977 in GDB for little endian targets (we'll read eight bytes,
3978 starting in s0 and then progressing to s1), but will be
3979 reversed on big endian targets with VFP. This won't
3980 be a problem for the new Neon quad registers; you're supposed
3981 to use DW_OP_piece for those. */
3982 if (reg
>= 64 && reg
<= 95)
3986 sprintf (name_buf
, "s%d", reg
- 64);
3987 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3991 /* VFP v3 / Neon registers. This range is also used for VFP v2
3992 registers, except that it now describes d0 instead of s0. */
3993 if (reg
>= 256 && reg
<= 287)
3997 sprintf (name_buf
, "d%d", reg
- 256);
3998 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4005 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4007 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
4010 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
4012 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
4013 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
4015 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
4016 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
4018 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
4019 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
4021 if (reg
< NUM_GREGS
)
4022 return SIM_ARM_R0_REGNUM
+ reg
;
4025 if (reg
< NUM_FREGS
)
4026 return SIM_ARM_FP0_REGNUM
+ reg
;
4029 if (reg
< NUM_SREGS
)
4030 return SIM_ARM_FPS_REGNUM
+ reg
;
4033 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
4036 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4037 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4038 It is thought that this is is the floating-point register format on
4039 little-endian systems. */
4042 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
4043 void *dbl
, int endianess
)
4047 if (endianess
== BFD_ENDIAN_BIG
)
4048 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
4050 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4052 floatformat_from_doublest (fmt
, &d
, dbl
);
4056 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
4061 floatformat_to_doublest (fmt
, ptr
, &d
);
4062 if (endianess
== BFD_ENDIAN_BIG
)
4063 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
4065 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4070 condition_true (unsigned long cond
, unsigned long status_reg
)
4072 if (cond
== INST_AL
|| cond
== INST_NV
)
4078 return ((status_reg
& FLAG_Z
) != 0);
4080 return ((status_reg
& FLAG_Z
) == 0);
4082 return ((status_reg
& FLAG_C
) != 0);
4084 return ((status_reg
& FLAG_C
) == 0);
4086 return ((status_reg
& FLAG_N
) != 0);
4088 return ((status_reg
& FLAG_N
) == 0);
4090 return ((status_reg
& FLAG_V
) != 0);
4092 return ((status_reg
& FLAG_V
) == 0);
4094 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
4096 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
4098 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
4100 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
4102 return (((status_reg
& FLAG_Z
) == 0)
4103 && (((status_reg
& FLAG_N
) == 0)
4104 == ((status_reg
& FLAG_V
) == 0)));
4106 return (((status_reg
& FLAG_Z
) != 0)
4107 || (((status_reg
& FLAG_N
) == 0)
4108 != ((status_reg
& FLAG_V
) == 0)));
4113 static unsigned long
4114 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
4115 unsigned long pc_val
, unsigned long status_reg
)
4117 unsigned long res
, shift
;
4118 int rm
= bits (inst
, 0, 3);
4119 unsigned long shifttype
= bits (inst
, 5, 6);
4123 int rs
= bits (inst
, 8, 11);
4124 shift
= (rs
== 15 ? pc_val
+ 8
4125 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
4128 shift
= bits (inst
, 7, 11);
4130 res
= (rm
== ARM_PC_REGNUM
4131 ? (pc_val
+ (bit (inst
, 4) ? 12 : 8))
4132 : get_frame_register_unsigned (frame
, rm
));
4137 res
= shift
>= 32 ? 0 : res
<< shift
;
4141 res
= shift
>= 32 ? 0 : res
>> shift
;
4147 res
= ((res
& 0x80000000L
)
4148 ? ~((~res
) >> shift
) : res
>> shift
);
4151 case 3: /* ROR/RRX */
4154 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
4156 res
= (res
>> shift
) | (res
<< (32 - shift
));
4160 return res
& 0xffffffff;
4163 /* Return number of 1-bits in VAL. */
4166 bitcount (unsigned long val
)
4169 for (nbits
= 0; val
!= 0; nbits
++)
4170 val
&= val
- 1; /* Delete rightmost 1-bit in val. */
4174 /* Return the size in bytes of the complete Thumb instruction whose
4175 first halfword is INST1. */
4178 thumb_insn_size (unsigned short inst1
)
4180 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
4187 thumb_advance_itstate (unsigned int itstate
)
4189 /* Preserve IT[7:5], the first three bits of the condition. Shift
4190 the upcoming condition flags left by one bit. */
4191 itstate
= (itstate
& 0xe0) | ((itstate
<< 1) & 0x1f);
4193 /* If we have finished the IT block, clear the state. */
4194 if ((itstate
& 0x0f) == 0)
4200 /* Find the next PC after the current instruction executes. In some
4201 cases we can not statically determine the answer (see the IT state
4202 handling in this function); in that case, a breakpoint may be
4203 inserted in addition to the returned PC, which will be used to set
4204 another breakpoint by our caller. */
4207 thumb_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
)
4209 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4210 struct address_space
*aspace
= get_frame_address_space (frame
);
4211 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4212 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4213 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
4214 unsigned short inst1
;
4215 CORE_ADDR nextpc
= pc
+ 2; /* Default is next instruction. */
4216 unsigned long offset
;
4217 ULONGEST status
, itstate
;
4219 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4220 pc_val
= MAKE_THUMB_ADDR (pc_val
);
4222 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
4224 /* Thumb-2 conditional execution support. There are eight bits in
4225 the CPSR which describe conditional execution state. Once
4226 reconstructed (they're in a funny order), the low five bits
4227 describe the low bit of the condition for each instruction and
4228 how many instructions remain. The high three bits describe the
4229 base condition. One of the low four bits will be set if an IT
4230 block is active. These bits read as zero on earlier
4232 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
4233 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
4235 /* If-Then handling. On GNU/Linux, where this routine is used, we
4236 use an undefined instruction as a breakpoint. Unlike BKPT, IT
4237 can disable execution of the undefined instruction. So we might
4238 miss the breakpoint if we set it on a skipped conditional
4239 instruction. Because conditional instructions can change the
4240 flags, affecting the execution of further instructions, we may
4241 need to set two breakpoints. */
4243 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
!= NULL
)
4245 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4247 /* An IT instruction. Because this instruction does not
4248 modify the flags, we can accurately predict the next
4249 executed instruction. */
4250 itstate
= inst1
& 0x00ff;
4251 pc
+= thumb_insn_size (inst1
);
4253 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
4255 inst1
= read_memory_unsigned_integer (pc
, 2,
4256 byte_order_for_code
);
4257 pc
+= thumb_insn_size (inst1
);
4258 itstate
= thumb_advance_itstate (itstate
);
4261 return MAKE_THUMB_ADDR (pc
);
4263 else if (itstate
!= 0)
4265 /* We are in a conditional block. Check the condition. */
4266 if (! condition_true (itstate
>> 4, status
))
4268 /* Advance to the next executed instruction. */
4269 pc
+= thumb_insn_size (inst1
);
4270 itstate
= thumb_advance_itstate (itstate
);
4272 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
4274 inst1
= read_memory_unsigned_integer (pc
, 2,
4275 byte_order_for_code
);
4276 pc
+= thumb_insn_size (inst1
);
4277 itstate
= thumb_advance_itstate (itstate
);
4280 return MAKE_THUMB_ADDR (pc
);
4282 else if ((itstate
& 0x0f) == 0x08)
4284 /* This is the last instruction of the conditional
4285 block, and it is executed. We can handle it normally
4286 because the following instruction is not conditional,
4287 and we must handle it normally because it is
4288 permitted to branch. Fall through. */
4294 /* There are conditional instructions after this one.
4295 If this instruction modifies the flags, then we can
4296 not predict what the next executed instruction will
4297 be. Fortunately, this instruction is architecturally
4298 forbidden to branch; we know it will fall through.
4299 Start by skipping past it. */
4300 pc
+= thumb_insn_size (inst1
);
4301 itstate
= thumb_advance_itstate (itstate
);
4303 /* Set a breakpoint on the following instruction. */
4304 gdb_assert ((itstate
& 0x0f) != 0);
4305 arm_insert_single_step_breakpoint (gdbarch
, aspace
,
4306 MAKE_THUMB_ADDR (pc
));
4307 cond_negated
= (itstate
>> 4) & 1;
4309 /* Skip all following instructions with the same
4310 condition. If there is a later instruction in the IT
4311 block with the opposite condition, set the other
4312 breakpoint there. If not, then set a breakpoint on
4313 the instruction after the IT block. */
4316 inst1
= read_memory_unsigned_integer (pc
, 2,
4317 byte_order_for_code
);
4318 pc
+= thumb_insn_size (inst1
);
4319 itstate
= thumb_advance_itstate (itstate
);
4321 while (itstate
!= 0 && ((itstate
>> 4) & 1) == cond_negated
);
4323 return MAKE_THUMB_ADDR (pc
);
4327 else if (itstate
& 0x0f)
4329 /* We are in a conditional block. Check the condition. */
4330 int cond
= itstate
>> 4;
4332 if (! condition_true (cond
, status
))
4333 /* Advance to the next instruction. All the 32-bit
4334 instructions share a common prefix. */
4335 return MAKE_THUMB_ADDR (pc
+ thumb_insn_size (inst1
));
4337 /* Otherwise, handle the instruction normally. */
4340 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
4344 /* Fetch the saved PC from the stack. It's stored above
4345 all of the other registers. */
4346 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
4347 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
4348 nextpc
= read_memory_unsigned_integer (sp
+ offset
, 4, byte_order
);
4350 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
4352 unsigned long cond
= bits (inst1
, 8, 11);
4353 if (cond
== 0x0f) /* 0x0f = SWI */
4355 struct gdbarch_tdep
*tdep
;
4356 tdep
= gdbarch_tdep (gdbarch
);
4358 if (tdep
->syscall_next_pc
!= NULL
)
4359 nextpc
= tdep
->syscall_next_pc (frame
);
4362 else if (cond
!= 0x0f && condition_true (cond
, status
))
4363 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
4365 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
4367 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
4369 else if (thumb_insn_size (inst1
) == 4) /* 32-bit instruction */
4371 unsigned short inst2
;
4372 inst2
= read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
4374 /* Default to the next instruction. */
4376 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4378 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
4380 /* Branches and miscellaneous control instructions. */
4382 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
4385 int j1
, j2
, imm1
, imm2
;
4387 imm1
= sbits (inst1
, 0, 10);
4388 imm2
= bits (inst2
, 0, 10);
4389 j1
= bit (inst2
, 13);
4390 j2
= bit (inst2
, 11);
4392 offset
= ((imm1
<< 12) + (imm2
<< 1));
4393 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
4395 nextpc
= pc_val
+ offset
;
4396 /* For BLX make sure to clear the low bits. */
4397 if (bit (inst2
, 12) == 0)
4398 nextpc
= nextpc
& 0xfffffffc;
4400 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
4402 /* SUBS PC, LR, #imm8. */
4403 nextpc
= get_frame_register_unsigned (frame
, ARM_LR_REGNUM
);
4404 nextpc
-= inst2
& 0x00ff;
4406 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
4408 /* Conditional branch. */
4409 if (condition_true (bits (inst1
, 6, 9), status
))
4411 int sign
, j1
, j2
, imm1
, imm2
;
4413 sign
= sbits (inst1
, 10, 10);
4414 imm1
= bits (inst1
, 0, 5);
4415 imm2
= bits (inst2
, 0, 10);
4416 j1
= bit (inst2
, 13);
4417 j2
= bit (inst2
, 11);
4419 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
4420 offset
+= (imm1
<< 12) + (imm2
<< 1);
4422 nextpc
= pc_val
+ offset
;
4426 else if ((inst1
& 0xfe50) == 0xe810)
4428 /* Load multiple or RFE. */
4429 int rn
, offset
, load_pc
= 1;
4431 rn
= bits (inst1
, 0, 3);
4432 if (bit (inst1
, 7) && !bit (inst1
, 8))
4435 if (!bit (inst2
, 15))
4437 offset
= bitcount (inst2
) * 4 - 4;
4439 else if (!bit (inst1
, 7) && bit (inst1
, 8))
4442 if (!bit (inst2
, 15))
4446 else if (bit (inst1
, 7) && bit (inst1
, 8))
4451 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
4461 CORE_ADDR addr
= get_frame_register_unsigned (frame
, rn
);
4462 nextpc
= get_frame_memory_unsigned (frame
, addr
+ offset
, 4);
4465 else if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
4467 /* MOV PC or MOVS PC. */
4468 nextpc
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4469 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4471 else if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
4475 int rn
, load_pc
= 1;
4477 rn
= bits (inst1
, 0, 3);
4478 base
= get_frame_register_unsigned (frame
, rn
);
4479 if (rn
== ARM_PC_REGNUM
)
4481 base
= (base
+ 4) & ~(CORE_ADDR
) 0x3;
4483 base
+= bits (inst2
, 0, 11);
4485 base
-= bits (inst2
, 0, 11);
4487 else if (bit (inst1
, 7))
4488 base
+= bits (inst2
, 0, 11);
4489 else if (bit (inst2
, 11))
4491 if (bit (inst2
, 10))
4494 base
+= bits (inst2
, 0, 7);
4496 base
-= bits (inst2
, 0, 7);
4499 else if ((inst2
& 0x0fc0) == 0x0000)
4501 int shift
= bits (inst2
, 4, 5), rm
= bits (inst2
, 0, 3);
4502 base
+= get_frame_register_unsigned (frame
, rm
) << shift
;
4509 nextpc
= get_frame_memory_unsigned (frame
, base
, 4);
4511 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
4514 CORE_ADDR tbl_reg
, table
, offset
, length
;
4516 tbl_reg
= bits (inst1
, 0, 3);
4517 if (tbl_reg
== 0x0f)
4518 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
4520 table
= get_frame_register_unsigned (frame
, tbl_reg
);
4522 offset
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4523 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 1);
4524 nextpc
= pc_val
+ length
;
4526 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
4529 CORE_ADDR tbl_reg
, table
, offset
, length
;
4531 tbl_reg
= bits (inst1
, 0, 3);
4532 if (tbl_reg
== 0x0f)
4533 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
4535 table
= get_frame_register_unsigned (frame
, tbl_reg
);
4537 offset
= 2 * get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4538 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 2);
4539 nextpc
= pc_val
+ length
;
4542 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
4544 if (bits (inst1
, 3, 6) == 0x0f)
4545 nextpc
= UNMAKE_THUMB_ADDR (pc_val
);
4547 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
4549 else if ((inst1
& 0xff87) == 0x4687) /* mov pc, REG */
4551 if (bits (inst1
, 3, 6) == 0x0f)
4554 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
4556 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4558 else if ((inst1
& 0xf500) == 0xb100)
4561 int imm
= (bit (inst1
, 9) << 6) + (bits (inst1
, 3, 7) << 1);
4562 ULONGEST reg
= get_frame_register_unsigned (frame
, bits (inst1
, 0, 2));
4564 if (bit (inst1
, 11) && reg
!= 0)
4565 nextpc
= pc_val
+ imm
;
4566 else if (!bit (inst1
, 11) && reg
== 0)
4567 nextpc
= pc_val
+ imm
;
4572 /* Get the raw next address. PC is the current program counter, in
4573 FRAME, which is assumed to be executing in ARM mode.
4575 The value returned has the execution state of the next instruction
4576 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
4577 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
4581 arm_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
)
4583 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4584 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4585 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4586 unsigned long pc_val
;
4587 unsigned long this_instr
;
4588 unsigned long status
;
4591 pc_val
= (unsigned long) pc
;
4592 this_instr
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
4594 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
4595 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
4597 if (bits (this_instr
, 28, 31) == INST_NV
)
4598 switch (bits (this_instr
, 24, 27))
4603 /* Branch with Link and change to Thumb. */
4604 nextpc
= BranchDest (pc
, this_instr
);
4605 nextpc
|= bit (this_instr
, 24) << 1;
4606 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4612 /* Coprocessor register transfer. */
4613 if (bits (this_instr
, 12, 15) == 15)
4614 error (_("Invalid update to pc in instruction"));
4617 else if (condition_true (bits (this_instr
, 28, 31), status
))
4619 switch (bits (this_instr
, 24, 27))
4622 case 0x1: /* data processing */
4626 unsigned long operand1
, operand2
, result
= 0;
4630 if (bits (this_instr
, 12, 15) != 15)
4633 if (bits (this_instr
, 22, 25) == 0
4634 && bits (this_instr
, 4, 7) == 9) /* multiply */
4635 error (_("Invalid update to pc in instruction"));
4637 /* BX <reg>, BLX <reg> */
4638 if (bits (this_instr
, 4, 27) == 0x12fff1
4639 || bits (this_instr
, 4, 27) == 0x12fff3)
4641 rn
= bits (this_instr
, 0, 3);
4642 nextpc
= ((rn
== ARM_PC_REGNUM
)
4644 : get_frame_register_unsigned (frame
, rn
));
4649 /* Multiply into PC. */
4650 c
= (status
& FLAG_C
) ? 1 : 0;
4651 rn
= bits (this_instr
, 16, 19);
4652 operand1
= ((rn
== ARM_PC_REGNUM
)
4654 : get_frame_register_unsigned (frame
, rn
));
4656 if (bit (this_instr
, 25))
4658 unsigned long immval
= bits (this_instr
, 0, 7);
4659 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
4660 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
4663 else /* operand 2 is a shifted register. */
4664 operand2
= shifted_reg_val (frame
, this_instr
, c
,
4667 switch (bits (this_instr
, 21, 24))
4670 result
= operand1
& operand2
;
4674 result
= operand1
^ operand2
;
4678 result
= operand1
- operand2
;
4682 result
= operand2
- operand1
;
4686 result
= operand1
+ operand2
;
4690 result
= operand1
+ operand2
+ c
;
4694 result
= operand1
- operand2
+ c
;
4698 result
= operand2
- operand1
+ c
;
4704 case 0xb: /* tst, teq, cmp, cmn */
4705 result
= (unsigned long) nextpc
;
4709 result
= operand1
| operand2
;
4713 /* Always step into a function. */
4718 result
= operand1
& ~operand2
;
4726 /* In 26-bit APCS the bottom two bits of the result are
4727 ignored, and we always end up in ARM state. */
4729 nextpc
= arm_addr_bits_remove (gdbarch
, result
);
4737 case 0x5: /* data transfer */
4740 if (bit (this_instr
, 20))
4743 if (bits (this_instr
, 12, 15) == 15)
4749 if (bit (this_instr
, 22))
4750 error (_("Invalid update to pc in instruction"));
4752 /* byte write to PC */
4753 rn
= bits (this_instr
, 16, 19);
4754 base
= ((rn
== ARM_PC_REGNUM
)
4756 : get_frame_register_unsigned (frame
, rn
));
4758 if (bit (this_instr
, 24))
4761 int c
= (status
& FLAG_C
) ? 1 : 0;
4762 unsigned long offset
=
4763 (bit (this_instr
, 25)
4764 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
4765 : bits (this_instr
, 0, 11));
4767 if (bit (this_instr
, 23))
4773 (CORE_ADDR
) read_memory_unsigned_integer ((CORE_ADDR
) base
,
4780 case 0x9: /* block transfer */
4781 if (bit (this_instr
, 20))
4784 if (bit (this_instr
, 15))
4788 unsigned long rn_val
4789 = get_frame_register_unsigned (frame
,
4790 bits (this_instr
, 16, 19));
4792 if (bit (this_instr
, 23))
4795 unsigned long reglist
= bits (this_instr
, 0, 14);
4796 offset
= bitcount (reglist
) * 4;
4797 if (bit (this_instr
, 24)) /* pre */
4800 else if (bit (this_instr
, 24))
4804 (CORE_ADDR
) read_memory_unsigned_integer ((CORE_ADDR
)
4811 case 0xb: /* branch & link */
4812 case 0xa: /* branch */
4814 nextpc
= BranchDest (pc
, this_instr
);
4820 case 0xe: /* coproc ops */
4824 struct gdbarch_tdep
*tdep
;
4825 tdep
= gdbarch_tdep (gdbarch
);
4827 if (tdep
->syscall_next_pc
!= NULL
)
4828 nextpc
= tdep
->syscall_next_pc (frame
);
4834 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
4842 /* Determine next PC after current instruction executes. Will call either
4843 arm_get_next_pc_raw or thumb_get_next_pc_raw. Error out if infinite
4844 loop is detected. */
4847 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
4851 if (arm_frame_is_thumb (frame
))
4853 nextpc
= thumb_get_next_pc_raw (frame
, pc
);
4854 if (nextpc
== MAKE_THUMB_ADDR (pc
))
4855 error (_("Infinite loop detected"));
4859 nextpc
= arm_get_next_pc_raw (frame
, pc
);
4861 error (_("Infinite loop detected"));
4867 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
4868 of the appropriate mode (as encoded in the PC value), even if this
4869 differs from what would be expected according to the symbol tables. */
4872 arm_insert_single_step_breakpoint (struct gdbarch
*gdbarch
,
4873 struct address_space
*aspace
,
4876 struct cleanup
*old_chain
4877 = make_cleanup_restore_integer (&arm_override_mode
);
4879 arm_override_mode
= IS_THUMB_ADDR (pc
);
4880 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4882 insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
4884 do_cleanups (old_chain
);
4887 /* Checks for an atomic sequence of instructions beginning with a LDREX{,B,H,D}
4888 instruction and ending with a STREX{,B,H,D} instruction. If such a sequence
4889 is found, attempt to step through it. A breakpoint is placed at the end of
4893 thumb_deal_with_atomic_sequence_raw (struct frame_info
*frame
)
4895 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4896 struct address_space
*aspace
= get_frame_address_space (frame
);
4897 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4898 CORE_ADDR pc
= get_frame_pc (frame
);
4899 CORE_ADDR breaks
[2] = {-1, -1};
4901 unsigned short insn1
, insn2
;
4904 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
4905 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
4906 ULONGEST status
, itstate
;
4908 /* We currently do not support atomic sequences within an IT block. */
4909 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
4910 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
4914 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. */
4915 insn1
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
4917 if (thumb_insn_size (insn1
) != 4)
4920 insn2
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
4922 if (!((insn1
& 0xfff0) == 0xe850
4923 || ((insn1
& 0xfff0) == 0xe8d0 && (insn2
& 0x00c0) == 0x0040)))
4926 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
4928 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
4930 insn1
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
4933 if (thumb_insn_size (insn1
) != 4)
4935 /* Assume that there is at most one conditional branch in the
4936 atomic sequence. If a conditional branch is found, put a
4937 breakpoint in its destination address. */
4938 if ((insn1
& 0xf000) == 0xd000 && bits (insn1
, 8, 11) != 0x0f)
4940 if (last_breakpoint
> 0)
4941 return 0; /* More than one conditional branch found,
4942 fallback to the standard code. */
4944 breaks
[1] = loc
+ 2 + (sbits (insn1
, 0, 7) << 1);
4948 /* We do not support atomic sequences that use any *other*
4949 instructions but conditional branches to change the PC.
4950 Fall back to standard code to avoid losing control of
4952 else if (thumb_instruction_changes_pc (insn1
))
4957 insn2
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
4960 /* Assume that there is at most one conditional branch in the
4961 atomic sequence. If a conditional branch is found, put a
4962 breakpoint in its destination address. */
4963 if ((insn1
& 0xf800) == 0xf000
4964 && (insn2
& 0xd000) == 0x8000
4965 && (insn1
& 0x0380) != 0x0380)
4967 int sign
, j1
, j2
, imm1
, imm2
;
4968 unsigned int offset
;
4970 sign
= sbits (insn1
, 10, 10);
4971 imm1
= bits (insn1
, 0, 5);
4972 imm2
= bits (insn2
, 0, 10);
4973 j1
= bit (insn2
, 13);
4974 j2
= bit (insn2
, 11);
4976 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
4977 offset
+= (imm1
<< 12) + (imm2
<< 1);
4979 if (last_breakpoint
> 0)
4980 return 0; /* More than one conditional branch found,
4981 fallback to the standard code. */
4983 breaks
[1] = loc
+ offset
;
4987 /* We do not support atomic sequences that use any *other*
4988 instructions but conditional branches to change the PC.
4989 Fall back to standard code to avoid losing control of
4991 else if (thumb2_instruction_changes_pc (insn1
, insn2
))
4994 /* If we find a strex{,b,h,d}, we're done. */
4995 if ((insn1
& 0xfff0) == 0xe840
4996 || ((insn1
& 0xfff0) == 0xe8c0 && (insn2
& 0x00c0) == 0x0040))
5001 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5002 if (insn_count
== atomic_sequence_length
)
5005 /* Insert a breakpoint right after the end of the atomic sequence. */
5008 /* Check for duplicated breakpoints. Check also for a breakpoint
5009 placed (branch instruction's destination) anywhere in sequence. */
5011 && (breaks
[1] == breaks
[0]
5012 || (breaks
[1] >= pc
&& breaks
[1] < loc
)))
5013 last_breakpoint
= 0;
5015 /* Effectively inserts the breakpoints. */
5016 for (index
= 0; index
<= last_breakpoint
; index
++)
5017 arm_insert_single_step_breakpoint (gdbarch
, aspace
,
5018 MAKE_THUMB_ADDR (breaks
[index
]));
5024 arm_deal_with_atomic_sequence_raw (struct frame_info
*frame
)
5026 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5027 struct address_space
*aspace
= get_frame_address_space (frame
);
5028 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5029 CORE_ADDR pc
= get_frame_pc (frame
);
5030 CORE_ADDR breaks
[2] = {-1, -1};
5035 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
5036 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
5038 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction.
5039 Note that we do not currently support conditionally executed atomic
5041 insn
= read_memory_unsigned_integer (loc
, 4, byte_order_for_code
);
5043 if ((insn
& 0xff9000f0) != 0xe1900090)
5046 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5048 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
5050 insn
= read_memory_unsigned_integer (loc
, 4, byte_order_for_code
);
5053 /* Assume that there is at most one conditional branch in the atomic
5054 sequence. If a conditional branch is found, put a breakpoint in
5055 its destination address. */
5056 if (bits (insn
, 24, 27) == 0xa)
5058 if (last_breakpoint
> 0)
5059 return 0; /* More than one conditional branch found, fallback
5060 to the standard single-step code. */
5062 breaks
[1] = BranchDest (loc
- 4, insn
);
5066 /* We do not support atomic sequences that use any *other* instructions
5067 but conditional branches to change the PC. Fall back to standard
5068 code to avoid losing control of execution. */
5069 else if (arm_instruction_changes_pc (insn
))
5072 /* If we find a strex{,b,h,d}, we're done. */
5073 if ((insn
& 0xff9000f0) == 0xe1800090)
5077 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5078 if (insn_count
== atomic_sequence_length
)
5081 /* Insert a breakpoint right after the end of the atomic sequence. */
5084 /* Check for duplicated breakpoints. Check also for a breakpoint
5085 placed (branch instruction's destination) anywhere in sequence. */
5087 && (breaks
[1] == breaks
[0]
5088 || (breaks
[1] >= pc
&& breaks
[1] < loc
)))
5089 last_breakpoint
= 0;
5091 /* Effectively inserts the breakpoints. */
5092 for (index
= 0; index
<= last_breakpoint
; index
++)
5093 arm_insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
5099 arm_deal_with_atomic_sequence (struct frame_info
*frame
)
5101 if (arm_frame_is_thumb (frame
))
5102 return thumb_deal_with_atomic_sequence_raw (frame
);
5104 return arm_deal_with_atomic_sequence_raw (frame
);
5107 /* single_step() is called just before we want to resume the inferior,
5108 if we want to single-step it but there is no hardware or kernel
5109 single-step support. We find the target of the coming instruction
5110 and breakpoint it. */
5113 arm_software_single_step (struct frame_info
*frame
)
5115 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5116 struct address_space
*aspace
= get_frame_address_space (frame
);
5119 if (arm_deal_with_atomic_sequence (frame
))
5122 next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
5123 arm_insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
5128 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
5129 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
5130 NULL if an error occurs. BUF is freed. */
5133 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
5134 int old_len
, int new_len
)
5137 int bytes_to_read
= new_len
- old_len
;
5139 new_buf
= xmalloc (new_len
);
5140 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
5142 if (target_read_memory (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
5150 /* An IT block is at most the 2-byte IT instruction followed by
5151 four 4-byte instructions. The furthest back we must search to
5152 find an IT block that affects the current instruction is thus
5153 2 + 3 * 4 == 14 bytes. */
5154 #define MAX_IT_BLOCK_PREFIX 14
5156 /* Use a quick scan if there are more than this many bytes of
5158 #define IT_SCAN_THRESHOLD 32
5160 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
5161 A breakpoint in an IT block may not be hit, depending on the
5164 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
5168 CORE_ADDR boundary
, func_start
;
5170 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
5171 int i
, any
, last_it
, last_it_count
;
5173 /* If we are using BKPT breakpoints, none of this is necessary. */
5174 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
5177 /* ARM mode does not have this problem. */
5178 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
5181 /* We are setting a breakpoint in Thumb code that could potentially
5182 contain an IT block. The first step is to find how much Thumb
5183 code there is; we do not need to read outside of known Thumb
5185 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
5187 /* Thumb-2 code must have mapping symbols to have a chance. */
5190 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
5192 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
5193 && func_start
> boundary
)
5194 boundary
= func_start
;
5196 /* Search for a candidate IT instruction. We have to do some fancy
5197 footwork to distinguish a real IT instruction from the second
5198 half of a 32-bit instruction, but there is no need for that if
5199 there's no candidate. */
5200 buf_len
= min (bpaddr
- boundary
, MAX_IT_BLOCK_PREFIX
);
5202 /* No room for an IT instruction. */
5205 buf
= xmalloc (buf_len
);
5206 if (target_read_memory (bpaddr
- buf_len
, buf
, buf_len
) != 0)
5209 for (i
= 0; i
< buf_len
; i
+= 2)
5211 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5212 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
5224 /* OK, the code bytes before this instruction contain at least one
5225 halfword which resembles an IT instruction. We know that it's
5226 Thumb code, but there are still two possibilities. Either the
5227 halfword really is an IT instruction, or it is the second half of
5228 a 32-bit Thumb instruction. The only way we can tell is to
5229 scan forwards from a known instruction boundary. */
5230 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
5234 /* There's a lot of code before this instruction. Start with an
5235 optimistic search; it's easy to recognize halfwords that can
5236 not be the start of a 32-bit instruction, and use that to
5237 lock on to the instruction boundaries. */
5238 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
5241 buf_len
= IT_SCAN_THRESHOLD
;
5244 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
5246 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5247 if (thumb_insn_size (inst1
) == 2)
5254 /* At this point, if DEFINITE, BUF[I] is the first place we
5255 are sure that we know the instruction boundaries, and it is far
5256 enough from BPADDR that we could not miss an IT instruction
5257 affecting BPADDR. If ! DEFINITE, give up - start from a
5261 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
,
5265 buf_len
= bpaddr
- boundary
;
5271 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
5274 buf_len
= bpaddr
- boundary
;
5278 /* Scan forwards. Find the last IT instruction before BPADDR. */
5283 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5285 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
5290 else if (inst1
& 0x0002)
5292 else if (inst1
& 0x0004)
5297 i
+= thumb_insn_size (inst1
);
5303 /* There wasn't really an IT instruction after all. */
5306 if (last_it_count
< 1)
5307 /* It was too far away. */
5310 /* This really is a trouble spot. Move the breakpoint to the IT
5312 return bpaddr
- buf_len
+ last_it
;
5315 /* ARM displaced stepping support.
5317 Generally ARM displaced stepping works as follows:
5319 1. When an instruction is to be single-stepped, it is first decoded by
5320 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
5321 Depending on the type of instruction, it is then copied to a scratch
5322 location, possibly in a modified form. The copy_* set of functions
5323 performs such modification, as necessary. A breakpoint is placed after
5324 the modified instruction in the scratch space to return control to GDB.
5325 Note in particular that instructions which modify the PC will no longer
5326 do so after modification.
5328 2. The instruction is single-stepped, by setting the PC to the scratch
5329 location address, and resuming. Control returns to GDB when the
5332 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
5333 function used for the current instruction. This function's job is to
5334 put the CPU/memory state back to what it would have been if the
5335 instruction had been executed unmodified in its original location. */
5337 /* NOP instruction (mov r0, r0). */
5338 #define ARM_NOP 0xe1a00000
5339 #define THUMB_NOP 0x4600
5341 /* Helper for register reads for displaced stepping. In particular, this
5342 returns the PC as it would be seen by the instruction at its original
5346 displaced_read_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5350 CORE_ADDR from
= dsc
->insn_addr
;
5352 if (regno
== ARM_PC_REGNUM
)
5354 /* Compute pipeline offset:
5355 - When executing an ARM instruction, PC reads as the address of the
5356 current instruction plus 8.
5357 - When executing a Thumb instruction, PC reads as the address of the
5358 current instruction plus 4. */
5365 if (debug_displaced
)
5366 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
5367 (unsigned long) from
);
5368 return (ULONGEST
) from
;
5372 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
5373 if (debug_displaced
)
5374 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
5375 regno
, (unsigned long) ret
);
5381 displaced_in_arm_mode (struct regcache
*regs
)
5384 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
5386 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
5388 return (ps
& t_bit
) == 0;
5391 /* Write to the PC as from a branch instruction. */
5394 branch_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5398 /* Note: If bits 0/1 are set, this branch would be unpredictable for
5399 architecture versions < 6. */
5400 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
5401 val
& ~(ULONGEST
) 0x3);
5403 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
5404 val
& ~(ULONGEST
) 0x1);
5407 /* Write to the PC as from a branch-exchange instruction. */
5410 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
5413 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
5415 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
5419 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
5420 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
5422 else if ((val
& 2) == 0)
5424 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
5425 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
5429 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
5430 mode, align dest to 4 bytes). */
5431 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
5432 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
5433 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
5437 /* Write to the PC as if from a load instruction. */
5440 load_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5443 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
5444 bx_write_pc (regs
, val
);
5446 branch_write_pc (regs
, dsc
, val
);
5449 /* Write to the PC as if from an ALU instruction. */
5452 alu_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5455 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && !dsc
->is_thumb
)
5456 bx_write_pc (regs
, val
);
5458 branch_write_pc (regs
, dsc
, val
);
5461 /* Helper for writing to registers for displaced stepping. Writing to the PC
5462 has a varying effects depending on the instruction which does the write:
5463 this is controlled by the WRITE_PC argument. */
5466 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5467 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
5469 if (regno
== ARM_PC_REGNUM
)
5471 if (debug_displaced
)
5472 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
5473 (unsigned long) val
);
5476 case BRANCH_WRITE_PC
:
5477 branch_write_pc (regs
, dsc
, val
);
5481 bx_write_pc (regs
, val
);
5485 load_write_pc (regs
, dsc
, val
);
5489 alu_write_pc (regs
, dsc
, val
);
5492 case CANNOT_WRITE_PC
:
5493 warning (_("Instruction wrote to PC in an unexpected way when "
5494 "single-stepping"));
5498 internal_error (__FILE__
, __LINE__
,
5499 _("Invalid argument to displaced_write_reg"));
5502 dsc
->wrote_to_pc
= 1;
5506 if (debug_displaced
)
5507 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
5508 regno
, (unsigned long) val
);
5509 regcache_cooked_write_unsigned (regs
, regno
, val
);
5513 /* This function is used to concisely determine if an instruction INSN
5514 references PC. Register fields of interest in INSN should have the
5515 corresponding fields of BITMASK set to 0b1111. The function
5516 returns return 1 if any of these fields in INSN reference the PC
5517 (also 0b1111, r15), else it returns 0. */
5520 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
5522 uint32_t lowbit
= 1;
5524 while (bitmask
!= 0)
5528 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
5534 mask
= lowbit
* 0xf;
5536 if ((insn
& mask
) == mask
)
5545 /* The simplest copy function. Many instructions have the same effect no
5546 matter what address they are executed at: in those cases, use this. */
5549 arm_copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
5550 const char *iname
, struct displaced_step_closure
*dsc
)
5552 if (debug_displaced
)
5553 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
5554 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
5557 dsc
->modinsn
[0] = insn
;
5563 thumb_copy_unmodified_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
5564 uint16_t insn2
, const char *iname
,
5565 struct displaced_step_closure
*dsc
)
5567 if (debug_displaced
)
5568 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x %.4x, "
5569 "opcode/class '%s' unmodified\n", insn1
, insn2
,
5572 dsc
->modinsn
[0] = insn1
;
5573 dsc
->modinsn
[1] = insn2
;
5579 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
5582 thumb_copy_unmodified_16bit (struct gdbarch
*gdbarch
, unsigned int insn
,
5584 struct displaced_step_closure
*dsc
)
5586 if (debug_displaced
)
5587 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x, "
5588 "opcode/class '%s' unmodified\n", insn
,
5591 dsc
->modinsn
[0] = insn
;
5596 /* Preload instructions with immediate offset. */
5599 cleanup_preload (struct gdbarch
*gdbarch
,
5600 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5602 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5603 if (!dsc
->u
.preload
.immed
)
5604 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5608 install_preload (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5609 struct displaced_step_closure
*dsc
, unsigned int rn
)
5612 /* Preload instructions:
5614 {pli/pld} [rn, #+/-imm]
5616 {pli/pld} [r0, #+/-imm]. */
5618 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5619 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5620 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5621 dsc
->u
.preload
.immed
= 1;
5623 dsc
->cleanup
= &cleanup_preload
;
5627 arm_copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5628 struct displaced_step_closure
*dsc
)
5630 unsigned int rn
= bits (insn
, 16, 19);
5632 if (!insn_references_pc (insn
, 0x000f0000ul
))
5633 return arm_copy_unmodified (gdbarch
, insn
, "preload", dsc
);
5635 if (debug_displaced
)
5636 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
5637 (unsigned long) insn
);
5639 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
5641 install_preload (gdbarch
, regs
, dsc
, rn
);
5647 thumb2_copy_preload (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
5648 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5650 unsigned int rn
= bits (insn1
, 0, 3);
5651 unsigned int u_bit
= bit (insn1
, 7);
5652 int imm12
= bits (insn2
, 0, 11);
5655 if (rn
!= ARM_PC_REGNUM
)
5656 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "preload", dsc
);
5658 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
5659 PLD (literal) Encoding T1. */
5660 if (debug_displaced
)
5661 fprintf_unfiltered (gdb_stdlog
,
5662 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
5663 (unsigned int) dsc
->insn_addr
, u_bit
? '+' : '-',
5669 /* Rewrite instruction {pli/pld} PC imm12 into:
5670 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
5674 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
5676 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5677 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5679 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
5681 displaced_write_reg (regs
, dsc
, 0, pc_val
, CANNOT_WRITE_PC
);
5682 displaced_write_reg (regs
, dsc
, 1, imm12
, CANNOT_WRITE_PC
);
5683 dsc
->u
.preload
.immed
= 0;
5685 /* {pli/pld} [r0, r1] */
5686 dsc
->modinsn
[0] = insn1
& 0xfff0;
5687 dsc
->modinsn
[1] = 0xf001;
5690 dsc
->cleanup
= &cleanup_preload
;
5694 /* Preload instructions with register offset. */
5697 install_preload_reg(struct gdbarch
*gdbarch
, struct regcache
*regs
,
5698 struct displaced_step_closure
*dsc
, unsigned int rn
,
5701 ULONGEST rn_val
, rm_val
;
5703 /* Preload register-offset instructions:
5705 {pli/pld} [rn, rm {, shift}]
5707 {pli/pld} [r0, r1 {, shift}]. */
5709 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5710 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5711 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5712 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5713 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5714 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
5715 dsc
->u
.preload
.immed
= 0;
5717 dsc
->cleanup
= &cleanup_preload
;
5721 arm_copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5722 struct regcache
*regs
,
5723 struct displaced_step_closure
*dsc
)
5725 unsigned int rn
= bits (insn
, 16, 19);
5726 unsigned int rm
= bits (insn
, 0, 3);
5729 if (!insn_references_pc (insn
, 0x000f000ful
))
5730 return arm_copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
5732 if (debug_displaced
)
5733 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
5734 (unsigned long) insn
);
5736 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
5738 install_preload_reg (gdbarch
, regs
, dsc
, rn
, rm
);
5742 /* Copy/cleanup coprocessor load and store instructions. */
5745 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
5746 struct regcache
*regs
,
5747 struct displaced_step_closure
*dsc
)
5749 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 0);
5751 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5753 if (dsc
->u
.ldst
.writeback
)
5754 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
5758 install_copro_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5759 struct displaced_step_closure
*dsc
,
5760 int writeback
, unsigned int rn
)
5764 /* Coprocessor load/store instructions:
5766 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
5768 {stc/stc2} [r0, #+/-imm].
5770 ldc/ldc2 are handled identically. */
5772 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5773 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5774 /* PC should be 4-byte aligned. */
5775 rn_val
= rn_val
& 0xfffffffc;
5776 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5778 dsc
->u
.ldst
.writeback
= writeback
;
5779 dsc
->u
.ldst
.rn
= rn
;
5781 dsc
->cleanup
= &cleanup_copro_load_store
;
5785 arm_copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
5786 struct regcache
*regs
,
5787 struct displaced_step_closure
*dsc
)
5789 unsigned int rn
= bits (insn
, 16, 19);
5791 if (!insn_references_pc (insn
, 0x000f0000ul
))
5792 return arm_copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
5794 if (debug_displaced
)
5795 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
5796 "load/store insn %.8lx\n", (unsigned long) insn
);
5798 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
5800 install_copro_load_store (gdbarch
, regs
, dsc
, bit (insn
, 25), rn
);
5806 thumb2_copy_copro_load_store (struct gdbarch
*gdbarch
, uint16_t insn1
,
5807 uint16_t insn2
, struct regcache
*regs
,
5808 struct displaced_step_closure
*dsc
)
5810 unsigned int rn
= bits (insn1
, 0, 3);
5812 if (rn
!= ARM_PC_REGNUM
)
5813 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
5814 "copro load/store", dsc
);
5816 if (debug_displaced
)
5817 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
5818 "load/store insn %.4x%.4x\n", insn1
, insn2
);
5820 dsc
->modinsn
[0] = insn1
& 0xfff0;
5821 dsc
->modinsn
[1] = insn2
;
5824 /* This function is called for copying instruction LDC/LDC2/VLDR, which
5825 doesn't support writeback, so pass 0. */
5826 install_copro_load_store (gdbarch
, regs
, dsc
, 0, rn
);
5831 /* Clean up branch instructions (actually perform the branch, by setting
5835 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5836 struct displaced_step_closure
*dsc
)
5838 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5839 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
5840 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
5841 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
5846 if (dsc
->u
.branch
.link
)
5848 /* The value of LR should be the next insn of current one. In order
5849 not to confuse logic hanlding later insn `bx lr', if current insn mode
5850 is Thumb, the bit 0 of LR value should be set to 1. */
5851 ULONGEST next_insn_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
5854 next_insn_addr
|= 0x1;
5856 displaced_write_reg (regs
, dsc
, ARM_LR_REGNUM
, next_insn_addr
,
5860 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, dsc
->u
.branch
.dest
, write_pc
);
5863 /* Copy B/BL/BLX instructions with immediate destinations. */
5866 install_b_bl_blx (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5867 struct displaced_step_closure
*dsc
,
5868 unsigned int cond
, int exchange
, int link
, long offset
)
5870 /* Implement "BL<cond> <label>" as:
5872 Preparation: cond <- instruction condition
5873 Insn: mov r0, r0 (nop)
5874 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
5876 B<cond> similar, but don't set r14 in cleanup. */
5878 dsc
->u
.branch
.cond
= cond
;
5879 dsc
->u
.branch
.link
= link
;
5880 dsc
->u
.branch
.exchange
= exchange
;
5882 dsc
->u
.branch
.dest
= dsc
->insn_addr
;
5883 if (link
&& exchange
)
5884 /* For BLX, offset is computed from the Align (PC, 4). */
5885 dsc
->u
.branch
.dest
= dsc
->u
.branch
.dest
& 0xfffffffc;
5888 dsc
->u
.branch
.dest
+= 4 + offset
;
5890 dsc
->u
.branch
.dest
+= 8 + offset
;
5892 dsc
->cleanup
= &cleanup_branch
;
5895 arm_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
5896 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5898 unsigned int cond
= bits (insn
, 28, 31);
5899 int exchange
= (cond
== 0xf);
5900 int link
= exchange
|| bit (insn
, 24);
5903 if (debug_displaced
)
5904 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
5905 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
5906 (unsigned long) insn
);
5908 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
5909 then arrange the switch into Thumb mode. */
5910 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
5912 offset
= bits (insn
, 0, 23) << 2;
5914 if (bit (offset
, 25))
5915 offset
= offset
| ~0x3ffffff;
5917 dsc
->modinsn
[0] = ARM_NOP
;
5919 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5924 thumb2_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint16_t insn1
,
5925 uint16_t insn2
, struct regcache
*regs
,
5926 struct displaced_step_closure
*dsc
)
5928 int link
= bit (insn2
, 14);
5929 int exchange
= link
&& !bit (insn2
, 12);
5932 int j1
= bit (insn2
, 13);
5933 int j2
= bit (insn2
, 11);
5934 int s
= sbits (insn1
, 10, 10);
5935 int i1
= !(j1
^ bit (insn1
, 10));
5936 int i2
= !(j2
^ bit (insn1
, 10));
5938 if (!link
&& !exchange
) /* B */
5940 offset
= (bits (insn2
, 0, 10) << 1);
5941 if (bit (insn2
, 12)) /* Encoding T4 */
5943 offset
|= (bits (insn1
, 0, 9) << 12)
5949 else /* Encoding T3 */
5951 offset
|= (bits (insn1
, 0, 5) << 12)
5955 cond
= bits (insn1
, 6, 9);
5960 offset
= (bits (insn1
, 0, 9) << 12);
5961 offset
|= ((i2
<< 22) | (i1
<< 23) | (s
<< 24));
5962 offset
|= exchange
?
5963 (bits (insn2
, 1, 10) << 2) : (bits (insn2
, 0, 10) << 1);
5966 if (debug_displaced
)
5967 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s insn "
5968 "%.4x %.4x with offset %.8lx\n",
5969 link
? (exchange
) ? "blx" : "bl" : "b",
5970 insn1
, insn2
, offset
);
5972 dsc
->modinsn
[0] = THUMB_NOP
;
5974 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5978 /* Copy B Thumb instructions. */
5980 thumb_copy_b (struct gdbarch
*gdbarch
, unsigned short insn
,
5981 struct displaced_step_closure
*dsc
)
5983 unsigned int cond
= 0;
5985 unsigned short bit_12_15
= bits (insn
, 12, 15);
5986 CORE_ADDR from
= dsc
->insn_addr
;
5988 if (bit_12_15
== 0xd)
5990 /* offset = SignExtend (imm8:0, 32) */
5991 offset
= sbits ((insn
<< 1), 0, 8);
5992 cond
= bits (insn
, 8, 11);
5994 else if (bit_12_15
== 0xe) /* Encoding T2 */
5996 offset
= sbits ((insn
<< 1), 0, 11);
6000 if (debug_displaced
)
6001 fprintf_unfiltered (gdb_stdlog
,
6002 "displaced: copying b immediate insn %.4x "
6003 "with offset %d\n", insn
, offset
);
6005 dsc
->u
.branch
.cond
= cond
;
6006 dsc
->u
.branch
.link
= 0;
6007 dsc
->u
.branch
.exchange
= 0;
6008 dsc
->u
.branch
.dest
= from
+ 4 + offset
;
6010 dsc
->modinsn
[0] = THUMB_NOP
;
6012 dsc
->cleanup
= &cleanup_branch
;
6017 /* Copy BX/BLX with register-specified destinations. */
6020 install_bx_blx_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6021 struct displaced_step_closure
*dsc
, int link
,
6022 unsigned int cond
, unsigned int rm
)
6024 /* Implement {BX,BLX}<cond> <reg>" as:
6026 Preparation: cond <- instruction condition
6027 Insn: mov r0, r0 (nop)
6028 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
6030 Don't set r14 in cleanup for BX. */
6032 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, dsc
, rm
);
6034 dsc
->u
.branch
.cond
= cond
;
6035 dsc
->u
.branch
.link
= link
;
6037 dsc
->u
.branch
.exchange
= 1;
6039 dsc
->cleanup
= &cleanup_branch
;
6043 arm_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
6044 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6046 unsigned int cond
= bits (insn
, 28, 31);
6049 int link
= bit (insn
, 5);
6050 unsigned int rm
= bits (insn
, 0, 3);
6052 if (debug_displaced
)
6053 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx",
6054 (unsigned long) insn
);
6056 dsc
->modinsn
[0] = ARM_NOP
;
6058 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, cond
, rm
);
6063 thumb_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
6064 struct regcache
*regs
,
6065 struct displaced_step_closure
*dsc
)
6067 int link
= bit (insn
, 7);
6068 unsigned int rm
= bits (insn
, 3, 6);
6070 if (debug_displaced
)
6071 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x",
6072 (unsigned short) insn
);
6074 dsc
->modinsn
[0] = THUMB_NOP
;
6076 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, INST_AL
, rm
);
6082 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
6085 cleanup_alu_imm (struct gdbarch
*gdbarch
,
6086 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6088 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
6089 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6090 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6091 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6095 arm_copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
6096 struct displaced_step_closure
*dsc
)
6098 unsigned int rn
= bits (insn
, 16, 19);
6099 unsigned int rd
= bits (insn
, 12, 15);
6100 unsigned int op
= bits (insn
, 21, 24);
6101 int is_mov
= (op
== 0xd);
6102 ULONGEST rd_val
, rn_val
;
6104 if (!insn_references_pc (insn
, 0x000ff000ul
))
6105 return arm_copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
6107 if (debug_displaced
)
6108 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
6109 "%.8lx\n", is_mov
? "move" : "ALU",
6110 (unsigned long) insn
);
6112 /* Instruction is of form:
6114 <op><cond> rd, [rn,] #imm
6118 Preparation: tmp1, tmp2 <- r0, r1;
6120 Insn: <op><cond> r0, r1, #imm
6121 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6124 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6125 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6126 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6127 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6128 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6129 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6133 dsc
->modinsn
[0] = insn
& 0xfff00fff;
6135 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
6137 dsc
->cleanup
= &cleanup_alu_imm
;
6143 thumb2_copy_alu_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
6144 uint16_t insn2
, struct regcache
*regs
,
6145 struct displaced_step_closure
*dsc
)
6147 unsigned int op
= bits (insn1
, 5, 8);
6148 unsigned int rn
, rm
, rd
;
6149 ULONGEST rd_val
, rn_val
;
6151 rn
= bits (insn1
, 0, 3); /* Rn */
6152 rm
= bits (insn2
, 0, 3); /* Rm */
6153 rd
= bits (insn2
, 8, 11); /* Rd */
6155 /* This routine is only called for instruction MOV. */
6156 gdb_assert (op
== 0x2 && rn
== 0xf);
6158 if (rm
!= ARM_PC_REGNUM
&& rd
!= ARM_PC_REGNUM
)
6159 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ALU imm", dsc
);
6161 if (debug_displaced
)
6162 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x%.4x\n",
6163 "ALU", insn1
, insn2
);
6165 /* Instruction is of form:
6167 <op><cond> rd, [rn,] #imm
6171 Preparation: tmp1, tmp2 <- r0, r1;
6173 Insn: <op><cond> r0, r1, #imm
6174 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6177 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6178 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6179 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6180 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6181 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6182 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6185 dsc
->modinsn
[0] = insn1
;
6186 dsc
->modinsn
[1] = ((insn2
& 0xf0f0) | 0x1);
6189 dsc
->cleanup
= &cleanup_alu_imm
;
6194 /* Copy/cleanup arithmetic/logic insns with register RHS. */
6197 cleanup_alu_reg (struct gdbarch
*gdbarch
,
6198 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6203 rd_val
= displaced_read_reg (regs
, dsc
, 0);
6205 for (i
= 0; i
< 3; i
++)
6206 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
6208 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6212 install_alu_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6213 struct displaced_step_closure
*dsc
,
6214 unsigned int rd
, unsigned int rn
, unsigned int rm
)
6216 ULONGEST rd_val
, rn_val
, rm_val
;
6218 /* Instruction is of form:
6220 <op><cond> rd, [rn,] rm [, <shift>]
6224 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
6225 r0, r1, r2 <- rd, rn, rm
6226 Insn: <op><cond> r0, r1, r2 [, <shift>]
6227 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
6230 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6231 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6232 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6233 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6234 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6235 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6236 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6237 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6238 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
6241 dsc
->cleanup
= &cleanup_alu_reg
;
6245 arm_copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
6246 struct displaced_step_closure
*dsc
)
6248 unsigned int op
= bits (insn
, 21, 24);
6249 int is_mov
= (op
== 0xd);
6251 if (!insn_references_pc (insn
, 0x000ff00ful
))
6252 return arm_copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
6254 if (debug_displaced
)
6255 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
6256 is_mov
? "move" : "ALU", (unsigned long) insn
);
6259 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
6261 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
6263 install_alu_reg (gdbarch
, regs
, dsc
, bits (insn
, 12, 15), bits (insn
, 16, 19),
6269 thumb_copy_alu_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
6270 struct regcache
*regs
,
6271 struct displaced_step_closure
*dsc
)
6273 unsigned rn
, rm
, rd
;
6275 rd
= bits (insn
, 3, 6);
6276 rn
= (bit (insn
, 7) << 3) | bits (insn
, 0, 2);
6279 if (rd
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
6280 return thumb_copy_unmodified_16bit (gdbarch
, insn
, "ALU reg", dsc
);
6282 if (debug_displaced
)
6283 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x\n",
6284 "ALU", (unsigned short) insn
);
6286 dsc
->modinsn
[0] = ((insn
& 0xff00) | 0x08);
6288 install_alu_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
);
6293 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
6296 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
6297 struct regcache
*regs
,
6298 struct displaced_step_closure
*dsc
)
6300 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
6303 for (i
= 0; i
< 4; i
++)
6304 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
6306 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6310 install_alu_shifted_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6311 struct displaced_step_closure
*dsc
,
6312 unsigned int rd
, unsigned int rn
, unsigned int rm
,
6316 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
6318 /* Instruction is of form:
6320 <op><cond> rd, [rn,] rm, <shift> rs
6324 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
6325 r0, r1, r2, r3 <- rd, rn, rm, rs
6326 Insn: <op><cond> r0, r1, r2, <shift> r3
6328 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
6332 for (i
= 0; i
< 4; i
++)
6333 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6335 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6336 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6337 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6338 rs_val
= displaced_read_reg (regs
, dsc
, rs
);
6339 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6340 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6341 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
6342 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
6344 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
6348 arm_copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
6349 struct regcache
*regs
,
6350 struct displaced_step_closure
*dsc
)
6352 unsigned int op
= bits (insn
, 21, 24);
6353 int is_mov
= (op
== 0xd);
6354 unsigned int rd
, rn
, rm
, rs
;
6356 if (!insn_references_pc (insn
, 0x000fff0ful
))
6357 return arm_copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
6359 if (debug_displaced
)
6360 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
6361 "%.8lx\n", is_mov
? "move" : "ALU",
6362 (unsigned long) insn
);
6364 rn
= bits (insn
, 16, 19);
6365 rm
= bits (insn
, 0, 3);
6366 rs
= bits (insn
, 8, 11);
6367 rd
= bits (insn
, 12, 15);
6370 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
6372 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
6374 install_alu_shifted_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
, rs
);
6379 /* Clean up load instructions. */
6382 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6383 struct displaced_step_closure
*dsc
)
6385 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
6387 rt_val
= displaced_read_reg (regs
, dsc
, 0);
6388 if (dsc
->u
.ldst
.xfersize
== 8)
6389 rt_val2
= displaced_read_reg (regs
, dsc
, 1);
6390 rn_val
= displaced_read_reg (regs
, dsc
, 2);
6392 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6393 if (dsc
->u
.ldst
.xfersize
> 4)
6394 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6395 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
6396 if (!dsc
->u
.ldst
.immed
)
6397 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
6399 /* Handle register writeback. */
6400 if (dsc
->u
.ldst
.writeback
)
6401 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
6402 /* Put result in right place. */
6403 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
6404 if (dsc
->u
.ldst
.xfersize
== 8)
6405 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
6408 /* Clean up store instructions. */
6411 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6412 struct displaced_step_closure
*dsc
)
6414 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 2);
6416 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6417 if (dsc
->u
.ldst
.xfersize
> 4)
6418 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6419 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
6420 if (!dsc
->u
.ldst
.immed
)
6421 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
6422 if (!dsc
->u
.ldst
.restore_r4
)
6423 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
6426 if (dsc
->u
.ldst
.writeback
)
6427 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
6430 /* Copy "extra" load/store instructions. These are halfword/doubleword
6431 transfers, which have a different encoding to byte/word transfers. */
6434 arm_copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unpriveleged
,
6435 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6437 unsigned int op1
= bits (insn
, 20, 24);
6438 unsigned int op2
= bits (insn
, 5, 6);
6439 unsigned int rt
= bits (insn
, 12, 15);
6440 unsigned int rn
= bits (insn
, 16, 19);
6441 unsigned int rm
= bits (insn
, 0, 3);
6442 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
6443 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
6444 int immed
= (op1
& 0x4) != 0;
6446 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
6448 if (!insn_references_pc (insn
, 0x000ff00ful
))
6449 return arm_copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
6451 if (debug_displaced
)
6452 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
6453 "insn %.8lx\n", unpriveleged
? "unpriveleged " : "",
6454 (unsigned long) insn
);
6456 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
6459 internal_error (__FILE__
, __LINE__
,
6460 _("copy_extra_ld_st: instruction decode error"));
6462 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6463 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6464 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6466 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6468 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
6469 if (bytesize
[opcode
] == 8)
6470 rt_val2
= displaced_read_reg (regs
, dsc
, rt
+ 1);
6471 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6473 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6475 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
6476 if (bytesize
[opcode
] == 8)
6477 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
6478 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
6480 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
6483 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
6484 dsc
->u
.ldst
.rn
= rn
;
6485 dsc
->u
.ldst
.immed
= immed
;
6486 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
6487 dsc
->u
.ldst
.restore_r4
= 0;
6490 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
6492 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
6493 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
6495 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
6497 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
6498 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
6500 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
6505 /* Copy byte/half word/word loads and stores. */
6508 install_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6509 struct displaced_step_closure
*dsc
, int load
,
6510 int immed
, int writeback
, int size
, int usermode
,
6511 int rt
, int rm
, int rn
)
6513 ULONGEST rt_val
, rn_val
, rm_val
= 0;
6515 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6516 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6518 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6520 dsc
->tmp
[4] = displaced_read_reg (regs
, dsc
, 4);
6522 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
6523 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6525 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6527 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
6528 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
6530 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
6532 dsc
->u
.ldst
.xfersize
= size
;
6533 dsc
->u
.ldst
.rn
= rn
;
6534 dsc
->u
.ldst
.immed
= immed
;
6535 dsc
->u
.ldst
.writeback
= writeback
;
6537 /* To write PC we can do:
6539 Before this sequence of instructions:
6540 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
6541 r2 is the Rn value got from dispalced_read_reg.
6543 Insn1: push {pc} Write address of STR instruction + offset on stack
6544 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
6545 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
6546 = addr(Insn1) + offset - addr(Insn3) - 8
6548 Insn4: add r4, r4, #8 r4 = offset - 8
6549 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
6551 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
6553 Otherwise we don't know what value to write for PC, since the offset is
6554 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
6555 of this can be found in Section "Saving from r15" in
6556 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
6558 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
6563 thumb2_copy_load_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
6564 uint16_t insn2
, struct regcache
*regs
,
6565 struct displaced_step_closure
*dsc
, int size
)
6567 unsigned int u_bit
= bit (insn1
, 7);
6568 unsigned int rt
= bits (insn2
, 12, 15);
6569 int imm12
= bits (insn2
, 0, 11);
6572 if (debug_displaced
)
6573 fprintf_unfiltered (gdb_stdlog
,
6574 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
6575 (unsigned int) dsc
->insn_addr
, rt
, u_bit
? '+' : '-',
6581 /* Rewrite instruction LDR Rt imm12 into:
6583 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
6587 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
6590 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6591 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6592 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6594 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
6596 pc_val
= pc_val
& 0xfffffffc;
6598 displaced_write_reg (regs
, dsc
, 2, pc_val
, CANNOT_WRITE_PC
);
6599 displaced_write_reg (regs
, dsc
, 3, imm12
, CANNOT_WRITE_PC
);
6603 dsc
->u
.ldst
.xfersize
= size
;
6604 dsc
->u
.ldst
.immed
= 0;
6605 dsc
->u
.ldst
.writeback
= 0;
6606 dsc
->u
.ldst
.restore_r4
= 0;
6608 /* LDR R0, R2, R3 */
6609 dsc
->modinsn
[0] = 0xf852;
6610 dsc
->modinsn
[1] = 0x3;
6613 dsc
->cleanup
= &cleanup_load
;
6619 thumb2_copy_load_reg_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
6620 uint16_t insn2
, struct regcache
*regs
,
6621 struct displaced_step_closure
*dsc
,
6622 int writeback
, int immed
)
6624 unsigned int rt
= bits (insn2
, 12, 15);
6625 unsigned int rn
= bits (insn1
, 0, 3);
6626 unsigned int rm
= bits (insn2
, 0, 3); /* Only valid if !immed. */
6627 /* In LDR (register), there is also a register Rm, which is not allowed to
6628 be PC, so we don't have to check it. */
6630 if (rt
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
6631 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "load",
6634 if (debug_displaced
)
6635 fprintf_unfiltered (gdb_stdlog
,
6636 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
6637 rt
, rn
, insn1
, insn2
);
6639 install_load_store (gdbarch
, regs
, dsc
, 1, immed
, writeback
, 4,
6642 dsc
->u
.ldst
.restore_r4
= 0;
6645 /* ldr[b]<cond> rt, [rn, #imm], etc.
6647 ldr[b]<cond> r0, [r2, #imm]. */
6649 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
6650 dsc
->modinsn
[1] = insn2
& 0x0fff;
6653 /* ldr[b]<cond> rt, [rn, rm], etc.
6655 ldr[b]<cond> r0, [r2, r3]. */
6657 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
6658 dsc
->modinsn
[1] = (insn2
& 0x0ff0) | 0x3;
6668 arm_copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
6669 struct regcache
*regs
,
6670 struct displaced_step_closure
*dsc
,
6671 int load
, int size
, int usermode
)
6673 int immed
= !bit (insn
, 25);
6674 int writeback
= (bit (insn
, 24) == 0 || bit (insn
, 21) != 0);
6675 unsigned int rt
= bits (insn
, 12, 15);
6676 unsigned int rn
= bits (insn
, 16, 19);
6677 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
6679 if (!insn_references_pc (insn
, 0x000ff00ful
))
6680 return arm_copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
6682 if (debug_displaced
)
6683 fprintf_unfiltered (gdb_stdlog
,
6684 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
6685 load
? (size
== 1 ? "ldrb" : "ldr")
6686 : (size
== 1 ? "strb" : "str"), usermode
? "t" : "",
6688 (unsigned long) insn
);
6690 install_load_store (gdbarch
, regs
, dsc
, load
, immed
, writeback
, size
,
6691 usermode
, rt
, rm
, rn
);
6693 if (load
|| rt
!= ARM_PC_REGNUM
)
6695 dsc
->u
.ldst
.restore_r4
= 0;
6698 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
6700 {ldr,str}[b]<cond> r0, [r2, #imm]. */
6701 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
6703 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
6705 {ldr,str}[b]<cond> r0, [r2, r3]. */
6706 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
6710 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
6711 dsc
->u
.ldst
.restore_r4
= 1;
6712 dsc
->modinsn
[0] = 0xe92d8000; /* push {pc} */
6713 dsc
->modinsn
[1] = 0xe8bd0010; /* pop {r4} */
6714 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
6715 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
6716 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
6720 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
6722 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
6727 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
6732 /* Cleanup LDM instructions with fully-populated register list. This is an
6733 unfortunate corner case: it's impossible to implement correctly by modifying
6734 the instruction. The issue is as follows: we have an instruction,
6738 which we must rewrite to avoid loading PC. A possible solution would be to
6739 do the load in two halves, something like (with suitable cleanup
6743 ldm[id][ab] r8!, {r0-r7}
6745 ldm[id][ab] r8, {r7-r14}
6748 but at present there's no suitable place for <temp>, since the scratch space
6749 is overwritten before the cleanup routine is called. For now, we simply
6750 emulate the instruction. */
6753 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6754 struct displaced_step_closure
*dsc
)
6756 int inc
= dsc
->u
.block
.increment
;
6757 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
6758 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
6759 uint32_t regmask
= dsc
->u
.block
.regmask
;
6760 int regno
= inc
? 0 : 15;
6761 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
6762 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
6763 && (regmask
& 0x8000) != 0;
6764 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6765 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
6766 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6771 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
6772 sensible we can do here. Complain loudly. */
6773 if (exception_return
)
6774 error (_("Cannot single-step exception return"));
6776 /* We don't handle any stores here for now. */
6777 gdb_assert (dsc
->u
.block
.load
!= 0);
6779 if (debug_displaced
)
6780 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
6781 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
6782 dsc
->u
.block
.increment
? "inc" : "dec",
6783 dsc
->u
.block
.before
? "before" : "after");
6790 while (regno
<= ARM_PC_REGNUM
&& (regmask
& (1 << regno
)) == 0)
6793 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
6796 xfer_addr
+= bump_before
;
6798 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
6799 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
6801 xfer_addr
+= bump_after
;
6803 regmask
&= ~(1 << regno
);
6806 if (dsc
->u
.block
.writeback
)
6807 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
6811 /* Clean up an STM which included the PC in the register list. */
6814 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6815 struct displaced_step_closure
*dsc
)
6817 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6818 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
6819 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
6820 CORE_ADDR stm_insn_addr
;
6823 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6825 /* If condition code fails, there's nothing else to do. */
6826 if (!store_executed
)
6829 if (dsc
->u
.block
.increment
)
6831 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
6833 if (dsc
->u
.block
.before
)
6838 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
6840 if (dsc
->u
.block
.before
)
6844 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
6845 stm_insn_addr
= dsc
->scratch_base
;
6846 offset
= pc_val
- stm_insn_addr
;
6848 if (debug_displaced
)
6849 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
6850 "STM instruction\n", offset
);
6852 /* Rewrite the stored PC to the proper value for the non-displaced original
6854 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
6855 dsc
->insn_addr
+ offset
);
6858 /* Clean up an LDM which includes the PC in the register list. We clumped all
6859 the registers in the transferred list into a contiguous range r0...rX (to
6860 avoid loading PC directly and losing control of the debugged program), so we
6861 must undo that here. */
6864 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
6865 struct regcache
*regs
,
6866 struct displaced_step_closure
*dsc
)
6868 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6869 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
);
6870 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= ARM_PC_REGNUM
;
6871 unsigned int regs_loaded
= bitcount (mask
);
6872 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
6874 /* The method employed here will fail if the register list is fully populated
6875 (we need to avoid loading PC directly). */
6876 gdb_assert (num_to_shuffle
< 16);
6881 clobbered
= (1 << num_to_shuffle
) - 1;
6883 while (num_to_shuffle
> 0)
6885 if ((mask
& (1 << write_reg
)) != 0)
6887 unsigned int read_reg
= num_to_shuffle
- 1;
6889 if (read_reg
!= write_reg
)
6891 ULONGEST rval
= displaced_read_reg (regs
, dsc
, read_reg
);
6892 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
6893 if (debug_displaced
)
6894 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
6895 "loaded register r%d to r%d\n"), read_reg
,
6898 else if (debug_displaced
)
6899 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
6900 "r%d already in the right place\n"),
6903 clobbered
&= ~(1 << write_reg
);
6911 /* Restore any registers we scribbled over. */
6912 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
6914 if ((clobbered
& (1 << write_reg
)) != 0)
6916 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
6918 if (debug_displaced
)
6919 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
6920 "clobbered register r%d\n"), write_reg
);
6921 clobbered
&= ~(1 << write_reg
);
6925 /* Perform register writeback manually. */
6926 if (dsc
->u
.block
.writeback
)
6928 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
6930 if (dsc
->u
.block
.increment
)
6931 new_rn_val
+= regs_loaded
* 4;
6933 new_rn_val
-= regs_loaded
* 4;
6935 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
6940 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
6941 in user-level code (in particular exception return, ldm rn, {...pc}^). */
6944 arm_copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
,
6945 struct regcache
*regs
,
6946 struct displaced_step_closure
*dsc
)
6948 int load
= bit (insn
, 20);
6949 int user
= bit (insn
, 22);
6950 int increment
= bit (insn
, 23);
6951 int before
= bit (insn
, 24);
6952 int writeback
= bit (insn
, 21);
6953 int rn
= bits (insn
, 16, 19);
6955 /* Block transfers which don't mention PC can be run directly
6957 if (rn
!= ARM_PC_REGNUM
&& (insn
& 0x8000) == 0)
6958 return arm_copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
6960 if (rn
== ARM_PC_REGNUM
)
6962 warning (_("displaced: Unpredictable LDM or STM with "
6963 "base register r15"));
6964 return arm_copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
6967 if (debug_displaced
)
6968 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6969 "%.8lx\n", (unsigned long) insn
);
6971 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6972 dsc
->u
.block
.rn
= rn
;
6974 dsc
->u
.block
.load
= load
;
6975 dsc
->u
.block
.user
= user
;
6976 dsc
->u
.block
.increment
= increment
;
6977 dsc
->u
.block
.before
= before
;
6978 dsc
->u
.block
.writeback
= writeback
;
6979 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
6981 dsc
->u
.block
.regmask
= insn
& 0xffff;
6985 if ((insn
& 0xffff) == 0xffff)
6987 /* LDM with a fully-populated register list. This case is
6988 particularly tricky. Implement for now by fully emulating the
6989 instruction (which might not behave perfectly in all cases, but
6990 these instructions should be rare enough for that not to matter
6992 dsc
->modinsn
[0] = ARM_NOP
;
6994 dsc
->cleanup
= &cleanup_block_load_all
;
6998 /* LDM of a list of registers which includes PC. Implement by
6999 rewriting the list of registers to be transferred into a
7000 contiguous chunk r0...rX before doing the transfer, then shuffling
7001 registers into the correct places in the cleanup routine. */
7002 unsigned int regmask
= insn
& 0xffff;
7003 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
7004 unsigned int to
= 0, from
= 0, i
, new_rn
;
7006 for (i
= 0; i
< num_in_list
; i
++)
7007 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7009 /* Writeback makes things complicated. We need to avoid clobbering
7010 the base register with one of the registers in our modified
7011 register list, but just using a different register can't work in
7014 ldm r14!, {r0-r13,pc}
7016 which would need to be rewritten as:
7020 but that can't work, because there's no free register for N.
7022 Solve this by turning off the writeback bit, and emulating
7023 writeback manually in the cleanup routine. */
7028 new_regmask
= (1 << num_in_list
) - 1;
7030 if (debug_displaced
)
7031 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
7032 "{..., pc}: original reg list %.4x, modified "
7033 "list %.4x\n"), rn
, writeback
? "!" : "",
7034 (int) insn
& 0xffff, new_regmask
);
7036 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
7038 dsc
->cleanup
= &cleanup_block_load_pc
;
7043 /* STM of a list of registers which includes PC. Run the instruction
7044 as-is, but out of line: this will store the wrong value for the PC,
7045 so we must manually fix up the memory in the cleanup routine.
7046 Doing things this way has the advantage that we can auto-detect
7047 the offset of the PC write (which is architecture-dependent) in
7048 the cleanup routine. */
7049 dsc
->modinsn
[0] = insn
;
7051 dsc
->cleanup
= &cleanup_block_store_pc
;
7058 thumb2_copy_block_xfer (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
7059 struct regcache
*regs
,
7060 struct displaced_step_closure
*dsc
)
7062 int rn
= bits (insn1
, 0, 3);
7063 int load
= bit (insn1
, 4);
7064 int writeback
= bit (insn1
, 5);
7066 /* Block transfers which don't mention PC can be run directly
7068 if (rn
!= ARM_PC_REGNUM
&& (insn2
& 0x8000) == 0)
7069 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ldm/stm", dsc
);
7071 if (rn
== ARM_PC_REGNUM
)
7073 warning (_("displaced: Unpredictable LDM or STM with "
7074 "base register r15"));
7075 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7076 "unpredictable ldm/stm", dsc
);
7079 if (debug_displaced
)
7080 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
7081 "%.4x%.4x\n", insn1
, insn2
);
7083 /* Clear bit 13, since it should be always zero. */
7084 dsc
->u
.block
.regmask
= (insn2
& 0xdfff);
7085 dsc
->u
.block
.rn
= rn
;
7087 dsc
->u
.block
.load
= load
;
7088 dsc
->u
.block
.user
= 0;
7089 dsc
->u
.block
.increment
= bit (insn1
, 7);
7090 dsc
->u
.block
.before
= bit (insn1
, 8);
7091 dsc
->u
.block
.writeback
= writeback
;
7092 dsc
->u
.block
.cond
= INST_AL
;
7093 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
7097 if (dsc
->u
.block
.regmask
== 0xffff)
7099 /* This branch is impossible to happen. */
7104 unsigned int regmask
= dsc
->u
.block
.regmask
;
7105 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
7106 unsigned int to
= 0, from
= 0, i
, new_rn
;
7108 for (i
= 0; i
< num_in_list
; i
++)
7109 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7114 new_regmask
= (1 << num_in_list
) - 1;
7116 if (debug_displaced
)
7117 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
7118 "{..., pc}: original reg list %.4x, modified "
7119 "list %.4x\n"), rn
, writeback
? "!" : "",
7120 (int) dsc
->u
.block
.regmask
, new_regmask
);
7122 dsc
->modinsn
[0] = insn1
;
7123 dsc
->modinsn
[1] = (new_regmask
& 0xffff);
7126 dsc
->cleanup
= &cleanup_block_load_pc
;
7131 dsc
->modinsn
[0] = insn1
;
7132 dsc
->modinsn
[1] = insn2
;
7134 dsc
->cleanup
= &cleanup_block_store_pc
;
7139 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
7140 for Linux, where some SVC instructions must be treated specially. */
7143 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7144 struct displaced_step_closure
*dsc
)
7146 CORE_ADDR resume_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
7148 if (debug_displaced
)
7149 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
7150 "%.8lx\n", (unsigned long) resume_addr
);
7152 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
7156 /* Common copy routine for svc instruciton. */
7159 install_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7160 struct displaced_step_closure
*dsc
)
7162 /* Preparation: none.
7163 Insn: unmodified svc.
7164 Cleanup: pc <- insn_addr + insn_size. */
7166 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
7168 dsc
->wrote_to_pc
= 1;
7170 /* Allow OS-specific code to override SVC handling. */
7171 if (dsc
->u
.svc
.copy_svc_os
)
7172 return dsc
->u
.svc
.copy_svc_os (gdbarch
, regs
, dsc
);
7175 dsc
->cleanup
= &cleanup_svc
;
7181 arm_copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
,
7182 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7185 if (debug_displaced
)
7186 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
7187 (unsigned long) insn
);
7189 dsc
->modinsn
[0] = insn
;
7191 return install_svc (gdbarch
, regs
, dsc
);
7195 thumb_copy_svc (struct gdbarch
*gdbarch
, uint16_t insn
,
7196 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7199 if (debug_displaced
)
7200 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.4x\n",
7203 dsc
->modinsn
[0] = insn
;
7205 return install_svc (gdbarch
, regs
, dsc
);
7208 /* Copy undefined instructions. */
7211 arm_copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
7212 struct displaced_step_closure
*dsc
)
7214 if (debug_displaced
)
7215 fprintf_unfiltered (gdb_stdlog
,
7216 "displaced: copying undefined insn %.8lx\n",
7217 (unsigned long) insn
);
7219 dsc
->modinsn
[0] = insn
;
7225 thumb_32bit_copy_undef (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
7226 struct displaced_step_closure
*dsc
)
7229 if (debug_displaced
)
7230 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn "
7231 "%.4x %.4x\n", (unsigned short) insn1
,
7232 (unsigned short) insn2
);
7234 dsc
->modinsn
[0] = insn1
;
7235 dsc
->modinsn
[1] = insn2
;
7241 /* Copy unpredictable instructions. */
7244 arm_copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
7245 struct displaced_step_closure
*dsc
)
7247 if (debug_displaced
)
7248 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
7249 "%.8lx\n", (unsigned long) insn
);
7251 dsc
->modinsn
[0] = insn
;
7256 /* The decode_* functions are instruction decoding helpers. They mostly follow
7257 the presentation in the ARM ARM. */
7260 arm_decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
7261 struct regcache
*regs
,
7262 struct displaced_step_closure
*dsc
)
7264 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
7265 unsigned int rn
= bits (insn
, 16, 19);
7267 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
7268 return arm_copy_unmodified (gdbarch
, insn
, "cps", dsc
);
7269 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
7270 return arm_copy_unmodified (gdbarch
, insn
, "setend", dsc
);
7271 else if ((op1
& 0x60) == 0x20)
7272 return arm_copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
7273 else if ((op1
& 0x71) == 0x40)
7274 return arm_copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store",
7276 else if ((op1
& 0x77) == 0x41)
7277 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
7278 else if ((op1
& 0x77) == 0x45)
7279 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
7280 else if ((op1
& 0x77) == 0x51)
7283 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
7285 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7287 else if ((op1
& 0x77) == 0x55)
7288 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
7289 else if (op1
== 0x57)
7292 case 0x1: return arm_copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
7293 case 0x4: return arm_copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
7294 case 0x5: return arm_copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
7295 case 0x6: return arm_copy_unmodified (gdbarch
, insn
, "isb", dsc
);
7296 default: return arm_copy_unpred (gdbarch
, insn
, dsc
);
7298 else if ((op1
& 0x63) == 0x43)
7299 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7300 else if ((op2
& 0x1) == 0x0)
7301 switch (op1
& ~0x80)
7304 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
7306 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
7307 case 0x71: case 0x75:
7309 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
7310 case 0x63: case 0x67: case 0x73: case 0x77:
7311 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7313 return arm_copy_undef (gdbarch
, insn
, dsc
);
7316 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
7320 arm_decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
7321 struct regcache
*regs
,
7322 struct displaced_step_closure
*dsc
)
7324 if (bit (insn
, 27) == 0)
7325 return arm_decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
7326 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
7327 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
7330 return arm_copy_unmodified (gdbarch
, insn
, "srs", dsc
);
7333 return arm_copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
7335 case 0x4: case 0x5: case 0x6: case 0x7:
7336 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
7339 switch ((insn
& 0xe00000) >> 21)
7341 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
7343 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7346 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
7349 return arm_copy_undef (gdbarch
, insn
, dsc
);
7354 int rn_f
= (bits (insn
, 16, 19) == 0xf);
7355 switch ((insn
& 0xe00000) >> 21)
7358 /* ldc/ldc2 imm (undefined for rn == pc). */
7359 return rn_f
? arm_copy_undef (gdbarch
, insn
, dsc
)
7360 : arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7363 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
7365 case 0x4: case 0x5: case 0x6: case 0x7:
7366 /* ldc/ldc2 lit (undefined for rn != pc). */
7367 return rn_f
? arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
7368 : arm_copy_undef (gdbarch
, insn
, dsc
);
7371 return arm_copy_undef (gdbarch
, insn
, dsc
);
7376 return arm_copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
7379 if (bits (insn
, 16, 19) == 0xf)
7381 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7383 return arm_copy_undef (gdbarch
, insn
, dsc
);
7387 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
7389 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7393 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
7395 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7398 return arm_copy_undef (gdbarch
, insn
, dsc
);
7402 /* Decode miscellaneous instructions in dp/misc encoding space. */
7405 arm_decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
7406 struct regcache
*regs
,
7407 struct displaced_step_closure
*dsc
)
7409 unsigned int op2
= bits (insn
, 4, 6);
7410 unsigned int op
= bits (insn
, 21, 22);
7411 unsigned int op1
= bits (insn
, 16, 19);
7416 return arm_copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
7419 if (op
== 0x1) /* bx. */
7420 return arm_copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
7422 return arm_copy_unmodified (gdbarch
, insn
, "clz", dsc
);
7424 return arm_copy_undef (gdbarch
, insn
, dsc
);
7428 /* Not really supported. */
7429 return arm_copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
7431 return arm_copy_undef (gdbarch
, insn
, dsc
);
7435 return arm_copy_bx_blx_reg (gdbarch
, insn
,
7436 regs
, dsc
); /* blx register. */
7438 return arm_copy_undef (gdbarch
, insn
, dsc
);
7441 return arm_copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
7445 return arm_copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
7447 /* Not really supported. */
7448 return arm_copy_unmodified (gdbarch
, insn
, "smc", dsc
);
7451 return arm_copy_undef (gdbarch
, insn
, dsc
);
7456 arm_decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
,
7457 struct regcache
*regs
,
7458 struct displaced_step_closure
*dsc
)
7461 switch (bits (insn
, 20, 24))
7464 return arm_copy_unmodified (gdbarch
, insn
, "movw", dsc
);
7467 return arm_copy_unmodified (gdbarch
, insn
, "movt", dsc
);
7469 case 0x12: case 0x16:
7470 return arm_copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
7473 return arm_copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
7477 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
7479 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
7480 return arm_copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
7481 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
7482 return arm_copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
7483 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
7484 return arm_decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
7485 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
7486 return arm_copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
7487 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
7488 return arm_copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
7489 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
7490 return arm_copy_unmodified (gdbarch
, insn
, "synch", dsc
);
7491 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
7492 /* 2nd arg means "unpriveleged". */
7493 return arm_copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
7497 /* Should be unreachable. */
7502 arm_decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
7503 struct regcache
*regs
,
7504 struct displaced_step_closure
*dsc
)
7506 int a
= bit (insn
, 25), b
= bit (insn
, 4);
7507 uint32_t op1
= bits (insn
, 20, 24);
7508 int rn_f
= bits (insn
, 16, 19) == 0xf;
7510 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
7511 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
7512 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 0);
7513 else if ((!a
&& (op1
& 0x17) == 0x02)
7514 || (a
&& (op1
& 0x17) == 0x02 && !b
))
7515 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 1);
7516 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
7517 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
7518 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 0);
7519 else if ((!a
&& (op1
& 0x17) == 0x03)
7520 || (a
&& (op1
& 0x17) == 0x03 && !b
))
7521 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 1);
7522 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
7523 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
7524 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
7525 else if ((!a
&& (op1
& 0x17) == 0x06)
7526 || (a
&& (op1
& 0x17) == 0x06 && !b
))
7527 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
7528 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
7529 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
7530 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
7531 else if ((!a
&& (op1
& 0x17) == 0x07)
7532 || (a
&& (op1
& 0x17) == 0x07 && !b
))
7533 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
7535 /* Should be unreachable. */
7540 arm_decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
7541 struct displaced_step_closure
*dsc
)
7543 switch (bits (insn
, 20, 24))
7545 case 0x00: case 0x01: case 0x02: case 0x03:
7546 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
7548 case 0x04: case 0x05: case 0x06: case 0x07:
7549 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
7551 case 0x08: case 0x09: case 0x0a: case 0x0b:
7552 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
7553 return arm_copy_unmodified (gdbarch
, insn
,
7554 "decode/pack/unpack/saturate/reverse", dsc
);
7557 if (bits (insn
, 5, 7) == 0) /* op2. */
7559 if (bits (insn
, 12, 15) == 0xf)
7560 return arm_copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
7562 return arm_copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
7565 return arm_copy_undef (gdbarch
, insn
, dsc
);
7567 case 0x1a: case 0x1b:
7568 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
7569 return arm_copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
7571 return arm_copy_undef (gdbarch
, insn
, dsc
);
7573 case 0x1c: case 0x1d:
7574 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
7576 if (bits (insn
, 0, 3) == 0xf)
7577 return arm_copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
7579 return arm_copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
7582 return arm_copy_undef (gdbarch
, insn
, dsc
);
7584 case 0x1e: case 0x1f:
7585 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
7586 return arm_copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
7588 return arm_copy_undef (gdbarch
, insn
, dsc
);
7591 /* Should be unreachable. */
7596 arm_decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, int32_t insn
,
7597 struct regcache
*regs
,
7598 struct displaced_step_closure
*dsc
)
7601 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
7603 return arm_copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
7607 arm_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
7608 struct regcache
*regs
,
7609 struct displaced_step_closure
*dsc
)
7611 unsigned int opcode
= bits (insn
, 20, 24);
7615 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
7616 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
7618 case 0x08: case 0x0a: case 0x0c: case 0x0e:
7619 case 0x12: case 0x16:
7620 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
7622 case 0x09: case 0x0b: case 0x0d: case 0x0f:
7623 case 0x13: case 0x17:
7624 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
7626 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7627 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7628 /* Note: no writeback for these instructions. Bit 25 will always be
7629 zero though (via caller), so the following works OK. */
7630 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7633 /* Should be unreachable. */
7637 /* Decode shifted register instructions. */
7640 thumb2_decode_dp_shift_reg (struct gdbarch
*gdbarch
, uint16_t insn1
,
7641 uint16_t insn2
, struct regcache
*regs
,
7642 struct displaced_step_closure
*dsc
)
7644 /* PC is only allowed to be used in instruction MOV. */
7646 unsigned int op
= bits (insn1
, 5, 8);
7647 unsigned int rn
= bits (insn1
, 0, 3);
7649 if (op
== 0x2 && rn
== 0xf) /* MOV */
7650 return thumb2_copy_alu_imm (gdbarch
, insn1
, insn2
, regs
, dsc
);
7652 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7653 "dp (shift reg)", dsc
);
7657 /* Decode extension register load/store. Exactly the same as
7658 arm_decode_ext_reg_ld_st. */
7661 thumb2_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint16_t insn1
,
7662 uint16_t insn2
, struct regcache
*regs
,
7663 struct displaced_step_closure
*dsc
)
7665 unsigned int opcode
= bits (insn1
, 4, 8);
7669 case 0x04: case 0x05:
7670 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7671 "vfp/neon vmov", dsc
);
7673 case 0x08: case 0x0c: /* 01x00 */
7674 case 0x0a: case 0x0e: /* 01x10 */
7675 case 0x12: case 0x16: /* 10x10 */
7676 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7677 "vfp/neon vstm/vpush", dsc
);
7679 case 0x09: case 0x0d: /* 01x01 */
7680 case 0x0b: case 0x0f: /* 01x11 */
7681 case 0x13: case 0x17: /* 10x11 */
7682 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7683 "vfp/neon vldm/vpop", dsc
);
7685 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7686 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7688 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7689 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
, regs
, dsc
);
7692 /* Should be unreachable. */
7697 arm_decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
7698 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7700 unsigned int op1
= bits (insn
, 20, 25);
7701 int op
= bit (insn
, 4);
7702 unsigned int coproc
= bits (insn
, 8, 11);
7703 unsigned int rn
= bits (insn
, 16, 19);
7705 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
7706 return arm_decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
7707 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
7708 && (coproc
& 0xe) != 0xa)
7710 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7711 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
7712 && (coproc
& 0xe) != 0xa)
7713 /* ldc/ldc2 imm/lit. */
7714 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7715 else if ((op1
& 0x3e) == 0x00)
7716 return arm_copy_undef (gdbarch
, insn
, dsc
);
7717 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
7718 return arm_copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
7719 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
7720 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
7721 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
7722 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
7723 else if ((op1
& 0x30) == 0x20 && !op
)
7725 if ((coproc
& 0xe) == 0xa)
7726 return arm_copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
7728 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7730 else if ((op1
& 0x30) == 0x20 && op
)
7731 return arm_copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
7732 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
7733 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
7734 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
7735 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
7736 else if ((op1
& 0x30) == 0x30)
7737 return arm_copy_svc (gdbarch
, insn
, regs
, dsc
);
7739 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
7743 thumb2_decode_svc_copro (struct gdbarch
*gdbarch
, uint16_t insn1
,
7744 uint16_t insn2
, struct regcache
*regs
,
7745 struct displaced_step_closure
*dsc
)
7747 unsigned int coproc
= bits (insn2
, 8, 11);
7748 unsigned int op1
= bits (insn1
, 4, 9);
7749 unsigned int bit_5_8
= bits (insn1
, 5, 8);
7750 unsigned int bit_9
= bit (insn1
, 9);
7751 unsigned int bit_4
= bit (insn1
, 4);
7752 unsigned int rn
= bits (insn1
, 0, 3);
7757 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7758 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
7760 else if (bit_5_8
== 0) /* UNDEFINED. */
7761 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
7764 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
7765 if ((coproc
& 0xe) == 0xa)
7766 return thumb2_decode_ext_reg_ld_st (gdbarch
, insn1
, insn2
, regs
,
7768 else /* coproc is not 101x. */
7770 if (bit_4
== 0) /* STC/STC2. */
7771 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7773 else /* LDC/LDC2 {literal, immeidate}. */
7774 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
,
7780 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "coproc", dsc
);
7786 install_pc_relative (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7787 struct displaced_step_closure
*dsc
, int rd
)
7793 Preparation: Rd <- PC
7799 int val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
7800 displaced_write_reg (regs
, dsc
, rd
, val
, CANNOT_WRITE_PC
);
7804 thumb_copy_pc_relative_16bit (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7805 struct displaced_step_closure
*dsc
,
7806 int rd
, unsigned int imm
)
7809 /* Encoding T2: ADDS Rd, #imm */
7810 dsc
->modinsn
[0] = (0x3000 | (rd
<< 8) | imm
);
7812 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
7818 thumb_decode_pc_relative_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
7819 struct regcache
*regs
,
7820 struct displaced_step_closure
*dsc
)
7822 unsigned int rd
= bits (insn
, 8, 10);
7823 unsigned int imm8
= bits (insn
, 0, 7);
7825 if (debug_displaced
)
7826 fprintf_unfiltered (gdb_stdlog
,
7827 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
7830 return thumb_copy_pc_relative_16bit (gdbarch
, regs
, dsc
, rd
, imm8
);
7834 thumb_copy_pc_relative_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
7835 uint16_t insn2
, struct regcache
*regs
,
7836 struct displaced_step_closure
*dsc
)
7838 unsigned int rd
= bits (insn2
, 8, 11);
7839 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
7840 extract raw immediate encoding rather than computing immediate. When
7841 generating ADD or SUB instruction, we can simply perform OR operation to
7842 set immediate into ADD. */
7843 unsigned int imm_3_8
= insn2
& 0x70ff;
7844 unsigned int imm_i
= insn1
& 0x0400; /* Clear all bits except bit 10. */
7846 if (debug_displaced
)
7847 fprintf_unfiltered (gdb_stdlog
,
7848 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
7849 rd
, imm_i
, imm_3_8
, insn1
, insn2
);
7851 if (bit (insn1
, 7)) /* Encoding T2 */
7853 /* Encoding T3: SUB Rd, Rd, #imm */
7854 dsc
->modinsn
[0] = (0xf1a0 | rd
| imm_i
);
7855 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7857 else /* Encoding T3 */
7859 /* Encoding T3: ADD Rd, Rd, #imm */
7860 dsc
->modinsn
[0] = (0xf100 | rd
| imm_i
);
7861 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7865 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
7871 thumb_copy_16bit_ldr_literal (struct gdbarch
*gdbarch
, unsigned short insn1
,
7872 struct regcache
*regs
,
7873 struct displaced_step_closure
*dsc
)
7875 unsigned int rt
= bits (insn1
, 8, 10);
7877 int imm8
= (bits (insn1
, 0, 7) << 2);
7878 CORE_ADDR from
= dsc
->insn_addr
;
7884 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
7886 Insn: LDR R0, [R2, R3];
7887 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
7889 if (debug_displaced
)
7890 fprintf_unfiltered (gdb_stdlog
,
7891 "displaced: copying thumb ldr r%d [pc #%d]\n"
7894 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
7895 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
7896 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
7897 pc
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
7898 /* The assembler calculates the required value of the offset from the
7899 Align(PC,4) value of this instruction to the label. */
7900 pc
= pc
& 0xfffffffc;
7902 displaced_write_reg (regs
, dsc
, 2, pc
, CANNOT_WRITE_PC
);
7903 displaced_write_reg (regs
, dsc
, 3, imm8
, CANNOT_WRITE_PC
);
7906 dsc
->u
.ldst
.xfersize
= 4;
7908 dsc
->u
.ldst
.immed
= 0;
7909 dsc
->u
.ldst
.writeback
= 0;
7910 dsc
->u
.ldst
.restore_r4
= 0;
7912 dsc
->modinsn
[0] = 0x58d0; /* ldr r0, [r2, r3]*/
7914 dsc
->cleanup
= &cleanup_load
;
7919 /* Copy Thumb cbnz/cbz insruction. */
7922 thumb_copy_cbnz_cbz (struct gdbarch
*gdbarch
, uint16_t insn1
,
7923 struct regcache
*regs
,
7924 struct displaced_step_closure
*dsc
)
7926 int non_zero
= bit (insn1
, 11);
7927 unsigned int imm5
= (bit (insn1
, 9) << 6) | (bits (insn1
, 3, 7) << 1);
7928 CORE_ADDR from
= dsc
->insn_addr
;
7929 int rn
= bits (insn1
, 0, 2);
7930 int rn_val
= displaced_read_reg (regs
, dsc
, rn
);
7932 dsc
->u
.branch
.cond
= (rn_val
&& non_zero
) || (!rn_val
&& !non_zero
);
7933 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
7934 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
7935 condition is false, let it be, cleanup_branch will do nothing. */
7936 if (dsc
->u
.branch
.cond
)
7938 dsc
->u
.branch
.cond
= INST_AL
;
7939 dsc
->u
.branch
.dest
= from
+ 4 + imm5
;
7942 dsc
->u
.branch
.dest
= from
+ 2;
7944 dsc
->u
.branch
.link
= 0;
7945 dsc
->u
.branch
.exchange
= 0;
7947 if (debug_displaced
)
7948 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s [r%d = 0x%x]"
7949 " insn %.4x to %.8lx\n", non_zero
? "cbnz" : "cbz",
7950 rn
, rn_val
, insn1
, dsc
->u
.branch
.dest
);
7952 dsc
->modinsn
[0] = THUMB_NOP
;
7954 dsc
->cleanup
= &cleanup_branch
;
7958 /* Copy Table Branch Byte/Halfword */
7960 thumb2_copy_table_branch (struct gdbarch
*gdbarch
, uint16_t insn1
,
7961 uint16_t insn2
, struct regcache
*regs
,
7962 struct displaced_step_closure
*dsc
)
7964 ULONGEST rn_val
, rm_val
;
7965 int is_tbh
= bit (insn2
, 4);
7966 CORE_ADDR halfwords
= 0;
7967 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7969 rn_val
= displaced_read_reg (regs
, dsc
, bits (insn1
, 0, 3));
7970 rm_val
= displaced_read_reg (regs
, dsc
, bits (insn2
, 0, 3));
7976 target_read_memory (rn_val
+ 2 * rm_val
, buf
, 2);
7977 halfwords
= extract_unsigned_integer (buf
, 2, byte_order
);
7983 target_read_memory (rn_val
+ rm_val
, buf
, 1);
7984 halfwords
= extract_unsigned_integer (buf
, 1, byte_order
);
7987 if (debug_displaced
)
7988 fprintf_unfiltered (gdb_stdlog
, "displaced: %s base 0x%x offset 0x%x"
7989 " offset 0x%x\n", is_tbh
? "tbh" : "tbb",
7990 (unsigned int) rn_val
, (unsigned int) rm_val
,
7991 (unsigned int) halfwords
);
7993 dsc
->u
.branch
.cond
= INST_AL
;
7994 dsc
->u
.branch
.link
= 0;
7995 dsc
->u
.branch
.exchange
= 0;
7996 dsc
->u
.branch
.dest
= dsc
->insn_addr
+ 4 + 2 * halfwords
;
7998 dsc
->cleanup
= &cleanup_branch
;
8004 cleanup_pop_pc_16bit_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
8005 struct displaced_step_closure
*dsc
)
8008 int val
= displaced_read_reg (regs
, dsc
, 7);
8009 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, val
, BX_WRITE_PC
);
8012 val
= displaced_read_reg (regs
, dsc
, 8);
8013 displaced_write_reg (regs
, dsc
, 7, val
, CANNOT_WRITE_PC
);
8016 displaced_write_reg (regs
, dsc
, 8, dsc
->tmp
[0], CANNOT_WRITE_PC
);
8021 thumb_copy_pop_pc_16bit (struct gdbarch
*gdbarch
, unsigned short insn1
,
8022 struct regcache
*regs
,
8023 struct displaced_step_closure
*dsc
)
8025 dsc
->u
.block
.regmask
= insn1
& 0x00ff;
8027 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
8030 (1) register list is full, that is, r0-r7 are used.
8031 Prepare: tmp[0] <- r8
8033 POP {r0, r1, ...., r6, r7}; remove PC from reglist
8034 MOV r8, r7; Move value of r7 to r8;
8035 POP {r7}; Store PC value into r7.
8037 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
8039 (2) register list is not full, supposing there are N registers in
8040 register list (except PC, 0 <= N <= 7).
8041 Prepare: for each i, 0 - N, tmp[i] <- ri.
8043 POP {r0, r1, ...., rN};
8045 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
8046 from tmp[] properly.
8048 if (debug_displaced
)
8049 fprintf_unfiltered (gdb_stdlog
,
8050 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
8051 dsc
->u
.block
.regmask
, insn1
);
8053 if (dsc
->u
.block
.regmask
== 0xff)
8055 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 8);
8057 dsc
->modinsn
[0] = (insn1
& 0xfeff); /* POP {r0,r1,...,r6, r7} */
8058 dsc
->modinsn
[1] = 0x46b8; /* MOV r8, r7 */
8059 dsc
->modinsn
[2] = 0xbc80; /* POP {r7} */
8062 dsc
->cleanup
= &cleanup_pop_pc_16bit_all
;
8066 unsigned int num_in_list
= bitcount (dsc
->u
.block
.regmask
);
8067 unsigned int new_regmask
, bit
= 1;
8068 unsigned int to
= 0, from
= 0, i
, new_rn
;
8070 for (i
= 0; i
< num_in_list
+ 1; i
++)
8071 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
8073 new_regmask
= (1 << (num_in_list
+ 1)) - 1;
8075 if (debug_displaced
)
8076 fprintf_unfiltered (gdb_stdlog
, _("displaced: POP "
8077 "{..., pc}: original reg list %.4x,"
8078 " modified list %.4x\n"),
8079 (int) dsc
->u
.block
.regmask
, new_regmask
);
8081 dsc
->u
.block
.regmask
|= 0x8000;
8082 dsc
->u
.block
.writeback
= 0;
8083 dsc
->u
.block
.cond
= INST_AL
;
8085 dsc
->modinsn
[0] = (insn1
& ~0x1ff) | (new_regmask
& 0xff);
8087 dsc
->cleanup
= &cleanup_block_load_pc
;
8094 thumb_process_displaced_16bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
8095 struct regcache
*regs
,
8096 struct displaced_step_closure
*dsc
)
8098 unsigned short op_bit_12_15
= bits (insn1
, 12, 15);
8099 unsigned short op_bit_10_11
= bits (insn1
, 10, 11);
8102 /* 16-bit thumb instructions. */
8103 switch (op_bit_12_15
)
8105 /* Shift (imme), add, subtract, move and compare. */
8106 case 0: case 1: case 2: case 3:
8107 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
8108 "shift/add/sub/mov/cmp",
8112 switch (op_bit_10_11
)
8114 case 0: /* Data-processing */
8115 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
8119 case 1: /* Special data instructions and branch and exchange. */
8121 unsigned short op
= bits (insn1
, 7, 9);
8122 if (op
== 6 || op
== 7) /* BX or BLX */
8123 err
= thumb_copy_bx_blx_reg (gdbarch
, insn1
, regs
, dsc
);
8124 else if (bits (insn1
, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
8125 err
= thumb_copy_alu_reg (gdbarch
, insn1
, regs
, dsc
);
8127 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "special data",
8131 default: /* LDR (literal) */
8132 err
= thumb_copy_16bit_ldr_literal (gdbarch
, insn1
, regs
, dsc
);
8135 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
8136 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldr/str", dsc
);
8139 if (op_bit_10_11
< 2) /* Generate PC-relative address */
8140 err
= thumb_decode_pc_relative_16bit (gdbarch
, insn1
, regs
, dsc
);
8141 else /* Generate SP-relative address */
8142 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "sp-relative", dsc
);
8144 case 11: /* Misc 16-bit instructions */
8146 switch (bits (insn1
, 8, 11))
8148 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
8149 err
= thumb_copy_cbnz_cbz (gdbarch
, insn1
, regs
, dsc
);
8151 case 12: case 13: /* POP */
8152 if (bit (insn1
, 8)) /* PC is in register list. */
8153 err
= thumb_copy_pop_pc_16bit (gdbarch
, insn1
, regs
, dsc
);
8155 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "pop", dsc
);
8157 case 15: /* If-Then, and hints */
8158 if (bits (insn1
, 0, 3))
8159 /* If-Then makes up to four following instructions conditional.
8160 IT instruction itself is not conditional, so handle it as a
8161 common unmodified instruction. */
8162 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "If-Then",
8165 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "hints", dsc
);
8168 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "misc", dsc
);
8173 if (op_bit_10_11
< 2) /* Store multiple registers */
8174 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "stm", dsc
);
8175 else /* Load multiple registers */
8176 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldm", dsc
);
8178 case 13: /* Conditional branch and supervisor call */
8179 if (bits (insn1
, 9, 11) != 7) /* conditional branch */
8180 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
8182 err
= thumb_copy_svc (gdbarch
, insn1
, regs
, dsc
);
8184 case 14: /* Unconditional branch */
8185 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
8192 internal_error (__FILE__
, __LINE__
,
8193 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
8197 decode_thumb_32bit_ld_mem_hints (struct gdbarch
*gdbarch
,
8198 uint16_t insn1
, uint16_t insn2
,
8199 struct regcache
*regs
,
8200 struct displaced_step_closure
*dsc
)
8202 int rt
= bits (insn2
, 12, 15);
8203 int rn
= bits (insn1
, 0, 3);
8204 int op1
= bits (insn1
, 7, 8);
8207 switch (bits (insn1
, 5, 6))
8209 case 0: /* Load byte and memory hints */
8210 if (rt
== 0xf) /* PLD/PLI */
8213 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
8214 return thumb2_copy_preload (gdbarch
, insn1
, insn2
, regs
, dsc
);
8216 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8221 if (rn
== 0xf) /* LDRB/LDRSB (literal) */
8222 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
8225 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8226 "ldrb{reg, immediate}/ldrbt",
8231 case 1: /* Load halfword and memory hints. */
8232 if (rt
== 0xf) /* PLD{W} and Unalloc memory hint. */
8233 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8234 "pld/unalloc memhint", dsc
);
8238 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
8241 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8245 case 2: /* Load word */
8247 int insn2_bit_8_11
= bits (insn2
, 8, 11);
8250 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
, 4);
8251 else if (op1
== 0x1) /* Encoding T3 */
8252 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
, dsc
,
8254 else /* op1 == 0x0 */
8256 if (insn2_bit_8_11
== 0xc || (insn2_bit_8_11
& 0x9) == 0x9)
8257 /* LDR (immediate) */
8258 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
8259 dsc
, bit (insn2
, 8), 1);
8260 else if (insn2_bit_8_11
== 0xe) /* LDRT */
8261 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8264 /* LDR (register) */
8265 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
8271 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
8278 thumb_process_displaced_32bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
8279 uint16_t insn2
, struct regcache
*regs
,
8280 struct displaced_step_closure
*dsc
)
8283 unsigned short op
= bit (insn2
, 15);
8284 unsigned int op1
= bits (insn1
, 11, 12);
8290 switch (bits (insn1
, 9, 10))
8295 /* Load/store {dual, execlusive}, table branch. */
8296 if (bits (insn1
, 7, 8) == 1 && bits (insn1
, 4, 5) == 1
8297 && bits (insn2
, 5, 7) == 0)
8298 err
= thumb2_copy_table_branch (gdbarch
, insn1
, insn2
, regs
,
8301 /* PC is not allowed to use in load/store {dual, exclusive}
8303 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8304 "load/store dual/ex", dsc
);
8306 else /* load/store multiple */
8308 switch (bits (insn1
, 7, 8))
8310 case 0: case 3: /* SRS, RFE */
8311 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8314 case 1: case 2: /* LDM/STM/PUSH/POP */
8315 err
= thumb2_copy_block_xfer (gdbarch
, insn1
, insn2
, regs
, dsc
);
8322 /* Data-processing (shift register). */
8323 err
= thumb2_decode_dp_shift_reg (gdbarch
, insn1
, insn2
, regs
,
8326 default: /* Coprocessor instructions. */
8327 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
8332 case 2: /* op1 = 2 */
8333 if (op
) /* Branch and misc control. */
8335 if (bit (insn2
, 14) /* BLX/BL */
8336 || bit (insn2
, 12) /* Unconditional branch */
8337 || (bits (insn1
, 7, 9) != 0x7)) /* Conditional branch */
8338 err
= thumb2_copy_b_bl_blx (gdbarch
, insn1
, insn2
, regs
, dsc
);
8340 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8345 if (bit (insn1
, 9)) /* Data processing (plain binary imm). */
8347 int op
= bits (insn1
, 4, 8);
8348 int rn
= bits (insn1
, 0, 3);
8349 if ((op
== 0 || op
== 0xa) && rn
== 0xf)
8350 err
= thumb_copy_pc_relative_32bit (gdbarch
, insn1
, insn2
,
8353 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8356 else /* Data processing (modified immeidate) */
8357 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8361 case 3: /* op1 = 3 */
8362 switch (bits (insn1
, 9, 10))
8366 err
= decode_thumb_32bit_ld_mem_hints (gdbarch
, insn1
, insn2
,
8368 else /* NEON Load/Store and Store single data item */
8369 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8370 "neon elt/struct load/store",
8373 case 1: /* op1 = 3, bits (9, 10) == 1 */
8374 switch (bits (insn1
, 7, 8))
8376 case 0: case 1: /* Data processing (register) */
8377 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8380 case 2: /* Multiply and absolute difference */
8381 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8382 "mul/mua/diff", dsc
);
8384 case 3: /* Long multiply and divide */
8385 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8390 default: /* Coprocessor instructions */
8391 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
8400 internal_error (__FILE__
, __LINE__
,
8401 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
8406 thumb_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8407 CORE_ADDR to
, struct regcache
*regs
,
8408 struct displaced_step_closure
*dsc
)
8410 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8412 = read_memory_unsigned_integer (from
, 2, byte_order_for_code
);
8414 if (debug_displaced
)
8415 fprintf_unfiltered (gdb_stdlog
, "displaced: process thumb insn %.4x "
8416 "at %.8lx\n", insn1
, (unsigned long) from
);
8419 dsc
->insn_size
= thumb_insn_size (insn1
);
8420 if (thumb_insn_size (insn1
) == 4)
8423 = read_memory_unsigned_integer (from
+ 2, 2, byte_order_for_code
);
8424 thumb_process_displaced_32bit_insn (gdbarch
, insn1
, insn2
, regs
, dsc
);
8427 thumb_process_displaced_16bit_insn (gdbarch
, insn1
, regs
, dsc
);
8431 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8432 CORE_ADDR to
, struct regcache
*regs
,
8433 struct displaced_step_closure
*dsc
)
8436 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8439 /* Most displaced instructions use a 1-instruction scratch space, so set this
8440 here and override below if/when necessary. */
8442 dsc
->insn_addr
= from
;
8443 dsc
->scratch_base
= to
;
8444 dsc
->cleanup
= NULL
;
8445 dsc
->wrote_to_pc
= 0;
8447 if (!displaced_in_arm_mode (regs
))
8448 return thumb_process_displaced_insn (gdbarch
, from
, to
, regs
, dsc
);
8452 insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
8453 if (debug_displaced
)
8454 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
8455 "at %.8lx\n", (unsigned long) insn
,
8456 (unsigned long) from
);
8458 if ((insn
& 0xf0000000) == 0xf0000000)
8459 err
= arm_decode_unconditional (gdbarch
, insn
, regs
, dsc
);
8460 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
8462 case 0x0: case 0x1: case 0x2: case 0x3:
8463 err
= arm_decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
8466 case 0x4: case 0x5: case 0x6:
8467 err
= arm_decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
8471 err
= arm_decode_media (gdbarch
, insn
, dsc
);
8474 case 0x8: case 0x9: case 0xa: case 0xb:
8475 err
= arm_decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
8478 case 0xc: case 0xd: case 0xe: case 0xf:
8479 err
= arm_decode_svc_copro (gdbarch
, insn
, to
, regs
, dsc
);
8484 internal_error (__FILE__
, __LINE__
,
8485 _("arm_process_displaced_insn: Instruction decode error"));
8488 /* Actually set up the scratch space for a displaced instruction. */
8491 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8492 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
8494 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8495 unsigned int i
, len
, offset
;
8496 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8497 int size
= dsc
->is_thumb
? 2 : 4;
8498 const unsigned char *bkp_insn
;
8501 /* Poke modified instruction(s). */
8502 for (i
= 0; i
< dsc
->numinsns
; i
++)
8504 if (debug_displaced
)
8506 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn ");
8508 fprintf_unfiltered (gdb_stdlog
, "%.8lx",
8511 fprintf_unfiltered (gdb_stdlog
, "%.4x",
8512 (unsigned short)dsc
->modinsn
[i
]);
8514 fprintf_unfiltered (gdb_stdlog
, " at %.8lx\n",
8515 (unsigned long) to
+ offset
);
8518 write_memory_unsigned_integer (to
+ offset
, size
,
8519 byte_order_for_code
,
8524 /* Choose the correct breakpoint instruction. */
8527 bkp_insn
= tdep
->thumb_breakpoint
;
8528 len
= tdep
->thumb_breakpoint_size
;
8532 bkp_insn
= tdep
->arm_breakpoint
;
8533 len
= tdep
->arm_breakpoint_size
;
8536 /* Put breakpoint afterwards. */
8537 write_memory (to
+ offset
, bkp_insn
, len
);
8539 if (debug_displaced
)
8540 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
8541 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
8544 /* Entry point for copying an instruction into scratch space for displaced
8547 struct displaced_step_closure
*
8548 arm_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
8549 CORE_ADDR from
, CORE_ADDR to
,
8550 struct regcache
*regs
)
8552 struct displaced_step_closure
*dsc
8553 = xmalloc (sizeof (struct displaced_step_closure
));
8554 arm_process_displaced_insn (gdbarch
, from
, to
, regs
, dsc
);
8555 arm_displaced_init_closure (gdbarch
, from
, to
, dsc
);
8560 /* Entry point for cleaning things up after a displaced instruction has been
8564 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
8565 struct displaced_step_closure
*dsc
,
8566 CORE_ADDR from
, CORE_ADDR to
,
8567 struct regcache
*regs
)
8570 dsc
->cleanup (gdbarch
, regs
, dsc
);
8572 if (!dsc
->wrote_to_pc
)
8573 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
8574 dsc
->insn_addr
+ dsc
->insn_size
);
8578 #include "bfd-in2.h"
8579 #include "libcoff.h"
8582 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
8584 struct gdbarch
*gdbarch
= info
->application_data
;
8586 if (arm_pc_is_thumb (gdbarch
, memaddr
))
8588 static asymbol
*asym
;
8589 static combined_entry_type ce
;
8590 static struct coff_symbol_struct csym
;
8591 static struct bfd fake_bfd
;
8592 static bfd_target fake_target
;
8594 if (csym
.native
== NULL
)
8596 /* Create a fake symbol vector containing a Thumb symbol.
8597 This is solely so that the code in print_insn_little_arm()
8598 and print_insn_big_arm() in opcodes/arm-dis.c will detect
8599 the presence of a Thumb symbol and switch to decoding
8600 Thumb instructions. */
8602 fake_target
.flavour
= bfd_target_coff_flavour
;
8603 fake_bfd
.xvec
= &fake_target
;
8604 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
8606 csym
.symbol
.the_bfd
= &fake_bfd
;
8607 csym
.symbol
.name
= "fake";
8608 asym
= (asymbol
*) & csym
;
8611 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
8612 info
->symbols
= &asym
;
8615 info
->symbols
= NULL
;
8617 if (info
->endian
== BFD_ENDIAN_BIG
)
8618 return print_insn_big_arm (memaddr
, info
);
8620 return print_insn_little_arm (memaddr
, info
);
8623 /* The following define instruction sequences that will cause ARM
8624 cpu's to take an undefined instruction trap. These are used to
8625 signal a breakpoint to GDB.
8627 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
8628 modes. A different instruction is required for each mode. The ARM
8629 cpu's can also be big or little endian. Thus four different
8630 instructions are needed to support all cases.
8632 Note: ARMv4 defines several new instructions that will take the
8633 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
8634 not in fact add the new instructions. The new undefined
8635 instructions in ARMv4 are all instructions that had no defined
8636 behaviour in earlier chips. There is no guarantee that they will
8637 raise an exception, but may be treated as NOP's. In practice, it
8638 may only safe to rely on instructions matching:
8640 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
8641 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
8642 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
8644 Even this may only true if the condition predicate is true. The
8645 following use a condition predicate of ALWAYS so it is always TRUE.
8647 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
8648 and NetBSD all use a software interrupt rather than an undefined
8649 instruction to force a trap. This can be handled by by the
8650 abi-specific code during establishment of the gdbarch vector. */
8652 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
8653 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
8654 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
8655 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
8657 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
8658 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
8659 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
8660 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
8662 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
8663 the program counter value to determine whether a 16-bit or 32-bit
8664 breakpoint should be used. It returns a pointer to a string of
8665 bytes that encode a breakpoint instruction, stores the length of
8666 the string to *lenptr, and adjusts the program counter (if
8667 necessary) to point to the actual memory location where the
8668 breakpoint should be inserted. */
8670 static const unsigned char *
8671 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
8673 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8674 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8676 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
8678 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
8680 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
8681 check whether we are replacing a 32-bit instruction. */
8682 if (tdep
->thumb2_breakpoint
!= NULL
)
8685 if (target_read_memory (*pcptr
, buf
, 2) == 0)
8687 unsigned short inst1
;
8688 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
8689 if (thumb_insn_size (inst1
) == 4)
8691 *lenptr
= tdep
->thumb2_breakpoint_size
;
8692 return tdep
->thumb2_breakpoint
;
8697 *lenptr
= tdep
->thumb_breakpoint_size
;
8698 return tdep
->thumb_breakpoint
;
8702 *lenptr
= tdep
->arm_breakpoint_size
;
8703 return tdep
->arm_breakpoint
;
8708 arm_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
8711 arm_breakpoint_from_pc (gdbarch
, pcptr
, kindptr
);
8713 if (arm_pc_is_thumb (gdbarch
, *pcptr
) && *kindptr
== 4)
8714 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
8715 that this is not confused with a 32-bit ARM breakpoint. */
8719 /* Extract from an array REGBUF containing the (raw) register state a
8720 function return value of type TYPE, and copy that, in virtual
8721 format, into VALBUF. */
8724 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
8727 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
8728 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8730 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
8732 switch (gdbarch_tdep (gdbarch
)->fp_model
)
8736 /* The value is in register F0 in internal format. We need to
8737 extract the raw value and then convert it to the desired
8739 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
8741 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
8742 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
8743 valbuf
, gdbarch_byte_order (gdbarch
));
8747 case ARM_FLOAT_SOFT_FPA
:
8748 case ARM_FLOAT_SOFT_VFP
:
8749 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8750 not using the VFP ABI code. */
8752 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
8753 if (TYPE_LENGTH (type
) > 4)
8754 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
8755 valbuf
+ INT_REGISTER_SIZE
);
8759 internal_error (__FILE__
, __LINE__
,
8760 _("arm_extract_return_value: "
8761 "Floating point model not supported"));
8765 else if (TYPE_CODE (type
) == TYPE_CODE_INT
8766 || TYPE_CODE (type
) == TYPE_CODE_CHAR
8767 || TYPE_CODE (type
) == TYPE_CODE_BOOL
8768 || TYPE_CODE (type
) == TYPE_CODE_PTR
8769 || TYPE_CODE (type
) == TYPE_CODE_REF
8770 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
8772 /* If the type is a plain integer, then the access is
8773 straight-forward. Otherwise we have to play around a bit
8775 int len
= TYPE_LENGTH (type
);
8776 int regno
= ARM_A1_REGNUM
;
8781 /* By using store_unsigned_integer we avoid having to do
8782 anything special for small big-endian values. */
8783 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
8784 store_unsigned_integer (valbuf
,
8785 (len
> INT_REGISTER_SIZE
8786 ? INT_REGISTER_SIZE
: len
),
8788 len
-= INT_REGISTER_SIZE
;
8789 valbuf
+= INT_REGISTER_SIZE
;
8794 /* For a structure or union the behaviour is as if the value had
8795 been stored to word-aligned memory and then loaded into
8796 registers with 32-bit load instruction(s). */
8797 int len
= TYPE_LENGTH (type
);
8798 int regno
= ARM_A1_REGNUM
;
8799 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8803 regcache_cooked_read (regs
, regno
++, tmpbuf
);
8804 memcpy (valbuf
, tmpbuf
,
8805 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
8806 len
-= INT_REGISTER_SIZE
;
8807 valbuf
+= INT_REGISTER_SIZE
;
8813 /* Will a function return an aggregate type in memory or in a
8814 register? Return 0 if an aggregate type can be returned in a
8815 register, 1 if it must be returned in memory. */
8818 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
8821 enum type_code code
;
8823 CHECK_TYPEDEF (type
);
8825 /* In the ARM ABI, "integer" like aggregate types are returned in
8826 registers. For an aggregate type to be integer like, its size
8827 must be less than or equal to INT_REGISTER_SIZE and the
8828 offset of each addressable subfield must be zero. Note that bit
8829 fields are not addressable, and all addressable subfields of
8830 unions always start at offset zero.
8832 This function is based on the behaviour of GCC 2.95.1.
8833 See: gcc/arm.c: arm_return_in_memory() for details.
8835 Note: All versions of GCC before GCC 2.95.2 do not set up the
8836 parameters correctly for a function returning the following
8837 structure: struct { float f;}; This should be returned in memory,
8838 not a register. Richard Earnshaw sent me a patch, but I do not
8839 know of any way to detect if a function like the above has been
8840 compiled with the correct calling convention. */
8842 /* All aggregate types that won't fit in a register must be returned
8844 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
8849 /* The AAPCS says all aggregates not larger than a word are returned
8851 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
8854 /* The only aggregate types that can be returned in a register are
8855 structs and unions. Arrays must be returned in memory. */
8856 code
= TYPE_CODE (type
);
8857 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
8862 /* Assume all other aggregate types can be returned in a register.
8863 Run a check for structures, unions and arrays. */
8866 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
8869 /* Need to check if this struct/union is "integer" like. For
8870 this to be true, its size must be less than or equal to
8871 INT_REGISTER_SIZE and the offset of each addressable
8872 subfield must be zero. Note that bit fields are not
8873 addressable, and unions always start at offset zero. If any
8874 of the subfields is a floating point type, the struct/union
8875 cannot be an integer type. */
8877 /* For each field in the object, check:
8878 1) Is it FP? --> yes, nRc = 1;
8879 2) Is it addressable (bitpos != 0) and
8880 not packed (bitsize == 0)?
8884 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
8886 enum type_code field_type_code
;
8887 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
,
8890 /* Is it a floating point type field? */
8891 if (field_type_code
== TYPE_CODE_FLT
)
8897 /* If bitpos != 0, then we have to care about it. */
8898 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
8900 /* Bitfields are not addressable. If the field bitsize is
8901 zero, then the field is not packed. Hence it cannot be
8902 a bitfield or any other packed type. */
8903 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
8915 /* Write into appropriate registers a function return value of type
8916 TYPE, given in virtual format. */
8919 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
8920 const gdb_byte
*valbuf
)
8922 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
8923 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8925 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
8927 char buf
[MAX_REGISTER_SIZE
];
8929 switch (gdbarch_tdep (gdbarch
)->fp_model
)
8933 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
8934 gdbarch_byte_order (gdbarch
));
8935 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
8938 case ARM_FLOAT_SOFT_FPA
:
8939 case ARM_FLOAT_SOFT_VFP
:
8940 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8941 not using the VFP ABI code. */
8943 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
8944 if (TYPE_LENGTH (type
) > 4)
8945 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
8946 valbuf
+ INT_REGISTER_SIZE
);
8950 internal_error (__FILE__
, __LINE__
,
8951 _("arm_store_return_value: Floating "
8952 "point model not supported"));
8956 else if (TYPE_CODE (type
) == TYPE_CODE_INT
8957 || TYPE_CODE (type
) == TYPE_CODE_CHAR
8958 || TYPE_CODE (type
) == TYPE_CODE_BOOL
8959 || TYPE_CODE (type
) == TYPE_CODE_PTR
8960 || TYPE_CODE (type
) == TYPE_CODE_REF
8961 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
8963 if (TYPE_LENGTH (type
) <= 4)
8965 /* Values of one word or less are zero/sign-extended and
8967 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8968 LONGEST val
= unpack_long (type
, valbuf
);
8970 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
8971 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
8975 /* Integral values greater than one word are stored in consecutive
8976 registers starting with r0. This will always be a multiple of
8977 the regiser size. */
8978 int len
= TYPE_LENGTH (type
);
8979 int regno
= ARM_A1_REGNUM
;
8983 regcache_cooked_write (regs
, regno
++, valbuf
);
8984 len
-= INT_REGISTER_SIZE
;
8985 valbuf
+= INT_REGISTER_SIZE
;
8991 /* For a structure or union the behaviour is as if the value had
8992 been stored to word-aligned memory and then loaded into
8993 registers with 32-bit load instruction(s). */
8994 int len
= TYPE_LENGTH (type
);
8995 int regno
= ARM_A1_REGNUM
;
8996 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
9000 memcpy (tmpbuf
, valbuf
,
9001 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
9002 regcache_cooked_write (regs
, regno
++, tmpbuf
);
9003 len
-= INT_REGISTER_SIZE
;
9004 valbuf
+= INT_REGISTER_SIZE
;
9010 /* Handle function return values. */
9012 static enum return_value_convention
9013 arm_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
9014 struct type
*valtype
, struct regcache
*regcache
,
9015 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
9017 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9018 struct type
*func_type
= function
? value_type (function
) : NULL
;
9019 enum arm_vfp_cprc_base_type vfp_base_type
;
9022 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
9023 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
9025 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
9026 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
9028 for (i
= 0; i
< vfp_base_count
; i
++)
9030 if (reg_char
== 'q')
9033 arm_neon_quad_write (gdbarch
, regcache
, i
,
9034 writebuf
+ i
* unit_length
);
9037 arm_neon_quad_read (gdbarch
, regcache
, i
,
9038 readbuf
+ i
* unit_length
);
9045 sprintf (name_buf
, "%c%d", reg_char
, i
);
9046 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9049 regcache_cooked_write (regcache
, regnum
,
9050 writebuf
+ i
* unit_length
);
9052 regcache_cooked_read (regcache
, regnum
,
9053 readbuf
+ i
* unit_length
);
9056 return RETURN_VALUE_REGISTER_CONVENTION
;
9059 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
9060 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
9061 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
9063 if (tdep
->struct_return
== pcc_struct_return
9064 || arm_return_in_memory (gdbarch
, valtype
))
9065 return RETURN_VALUE_STRUCT_CONVENTION
;
9068 /* AAPCS returns complex types longer than a register in memory. */
9069 if (tdep
->arm_abi
!= ARM_ABI_APCS
9070 && TYPE_CODE (valtype
) == TYPE_CODE_COMPLEX
9071 && TYPE_LENGTH (valtype
) > INT_REGISTER_SIZE
)
9072 return RETURN_VALUE_STRUCT_CONVENTION
;
9075 arm_store_return_value (valtype
, regcache
, writebuf
);
9078 arm_extract_return_value (valtype
, regcache
, readbuf
);
9080 return RETURN_VALUE_REGISTER_CONVENTION
;
9085 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
9087 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
9088 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9089 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
9091 char buf
[INT_REGISTER_SIZE
];
9093 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
9095 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
9099 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
9103 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
9104 return the target PC. Otherwise return 0. */
9107 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
9111 CORE_ADDR start_addr
;
9113 /* Find the starting address and name of the function containing the PC. */
9114 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
9117 /* If PC is in a Thumb call or return stub, return the address of the
9118 target PC, which is in a register. The thunk functions are called
9119 _call_via_xx, where x is the register name. The possible names
9120 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
9121 functions, named __ARM_call_via_r[0-7]. */
9122 if (strncmp (name
, "_call_via_", 10) == 0
9123 || strncmp (name
, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0)
9125 /* Use the name suffix to determine which register contains the
9127 static char *table
[15] =
9128 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
9129 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
9132 int offset
= strlen (name
) - 2;
9134 for (regno
= 0; regno
<= 14; regno
++)
9135 if (strcmp (&name
[offset
], table
[regno
]) == 0)
9136 return get_frame_register_unsigned (frame
, regno
);
9139 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
9140 non-interworking calls to foo. We could decode the stubs
9141 to find the target but it's easier to use the symbol table. */
9142 namelen
= strlen (name
);
9143 if (name
[0] == '_' && name
[1] == '_'
9144 && ((namelen
> 2 + strlen ("_from_thumb")
9145 && strncmp (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb",
9146 strlen ("_from_thumb")) == 0)
9147 || (namelen
> 2 + strlen ("_from_arm")
9148 && strncmp (name
+ namelen
- strlen ("_from_arm"), "_from_arm",
9149 strlen ("_from_arm")) == 0)))
9152 int target_len
= namelen
- 2;
9153 struct minimal_symbol
*minsym
;
9154 struct objfile
*objfile
;
9155 struct obj_section
*sec
;
9157 if (name
[namelen
- 1] == 'b')
9158 target_len
-= strlen ("_from_thumb");
9160 target_len
-= strlen ("_from_arm");
9162 target_name
= alloca (target_len
+ 1);
9163 memcpy (target_name
, name
+ 2, target_len
);
9164 target_name
[target_len
] = '\0';
9166 sec
= find_pc_section (pc
);
9167 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
9168 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
9170 return SYMBOL_VALUE_ADDRESS (minsym
);
9175 return 0; /* not a stub */
9179 set_arm_command (char *args
, int from_tty
)
9181 printf_unfiltered (_("\
9182 \"set arm\" must be followed by an apporpriate subcommand.\n"));
9183 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
9187 show_arm_command (char *args
, int from_tty
)
9189 cmd_show_list (showarmcmdlist
, from_tty
, "");
9193 arm_update_current_architecture (void)
9195 struct gdbarch_info info
;
9197 /* If the current architecture is not ARM, we have nothing to do. */
9198 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_arm
)
9201 /* Update the architecture. */
9202 gdbarch_info_init (&info
);
9204 if (!gdbarch_update_p (info
))
9205 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
9209 set_fp_model_sfunc (char *args
, int from_tty
,
9210 struct cmd_list_element
*c
)
9212 enum arm_float_model fp_model
;
9214 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
9215 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
9217 arm_fp_model
= fp_model
;
9221 if (fp_model
== ARM_FLOAT_LAST
)
9222 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
9225 arm_update_current_architecture ();
9229 show_fp_model (struct ui_file
*file
, int from_tty
,
9230 struct cmd_list_element
*c
, const char *value
)
9232 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
9234 if (arm_fp_model
== ARM_FLOAT_AUTO
9235 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
9236 fprintf_filtered (file
, _("\
9237 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
9238 fp_model_strings
[tdep
->fp_model
]);
9240 fprintf_filtered (file
, _("\
9241 The current ARM floating point model is \"%s\".\n"),
9242 fp_model_strings
[arm_fp_model
]);
9246 arm_set_abi (char *args
, int from_tty
,
9247 struct cmd_list_element
*c
)
9249 enum arm_abi_kind arm_abi
;
9251 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
9252 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
9254 arm_abi_global
= arm_abi
;
9258 if (arm_abi
== ARM_ABI_LAST
)
9259 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
9262 arm_update_current_architecture ();
9266 arm_show_abi (struct ui_file
*file
, int from_tty
,
9267 struct cmd_list_element
*c
, const char *value
)
9269 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
9271 if (arm_abi_global
== ARM_ABI_AUTO
9272 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
9273 fprintf_filtered (file
, _("\
9274 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
9275 arm_abi_strings
[tdep
->arm_abi
]);
9277 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
9282 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
9283 struct cmd_list_element
*c
, const char *value
)
9285 fprintf_filtered (file
,
9286 _("The current execution mode assumed "
9287 "(when symbols are unavailable) is \"%s\".\n"),
9288 arm_fallback_mode_string
);
9292 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
9293 struct cmd_list_element
*c
, const char *value
)
9295 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
9297 fprintf_filtered (file
,
9298 _("The current execution mode assumed "
9299 "(even when symbols are available) is \"%s\".\n"),
9300 arm_force_mode_string
);
9303 /* If the user changes the register disassembly style used for info
9304 register and other commands, we have to also switch the style used
9305 in opcodes for disassembly output. This function is run in the "set
9306 arm disassembly" command, and does that. */
9309 set_disassembly_style_sfunc (char *args
, int from_tty
,
9310 struct cmd_list_element
*c
)
9312 set_disassembly_style ();
9315 /* Return the ARM register name corresponding to register I. */
9317 arm_register_name (struct gdbarch
*gdbarch
, int i
)
9319 const int num_regs
= gdbarch_num_regs (gdbarch
);
9321 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
9322 && i
>= num_regs
&& i
< num_regs
+ 32)
9324 static const char *const vfp_pseudo_names
[] = {
9325 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
9326 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
9327 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
9328 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
9331 return vfp_pseudo_names
[i
- num_regs
];
9334 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
9335 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
9337 static const char *const neon_pseudo_names
[] = {
9338 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
9339 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
9342 return neon_pseudo_names
[i
- num_regs
- 32];
9345 if (i
>= ARRAY_SIZE (arm_register_names
))
9346 /* These registers are only supported on targets which supply
9347 an XML description. */
9350 return arm_register_names
[i
];
9354 set_disassembly_style (void)
9358 /* Find the style that the user wants. */
9359 for (current
= 0; current
< num_disassembly_options
; current
++)
9360 if (disassembly_style
== valid_disassembly_styles
[current
])
9362 gdb_assert (current
< num_disassembly_options
);
9364 /* Synchronize the disassembler. */
9365 set_arm_regname_option (current
);
9368 /* Test whether the coff symbol specific value corresponds to a Thumb
9372 coff_sym_is_thumb (int val
)
9374 return (val
== C_THUMBEXT
9375 || val
== C_THUMBSTAT
9376 || val
== C_THUMBEXTFUNC
9377 || val
== C_THUMBSTATFUNC
9378 || val
== C_THUMBLABEL
);
9381 /* arm_coff_make_msymbol_special()
9382 arm_elf_make_msymbol_special()
9384 These functions test whether the COFF or ELF symbol corresponds to
9385 an address in thumb code, and set a "special" bit in a minimal
9386 symbol to indicate that it does. */
9389 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
9391 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type
*)sym
)->internal_elf_sym
)
9392 == ST_BRANCH_TO_THUMB
)
9393 MSYMBOL_SET_SPECIAL (msym
);
9397 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
9399 if (coff_sym_is_thumb (val
))
9400 MSYMBOL_SET_SPECIAL (msym
);
9404 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
9406 struct arm_per_objfile
*data
= arg
;
9409 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
9410 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
9414 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
9417 const char *name
= bfd_asymbol_name (sym
);
9418 struct arm_per_objfile
*data
;
9419 VEC(arm_mapping_symbol_s
) **map_p
;
9420 struct arm_mapping_symbol new_map_sym
;
9422 gdb_assert (name
[0] == '$');
9423 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
9426 data
= objfile_data (objfile
, arm_objfile_data_key
);
9429 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
9430 struct arm_per_objfile
);
9431 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
9432 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
9433 objfile
->obfd
->section_count
,
9434 VEC(arm_mapping_symbol_s
) *);
9436 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
9438 new_map_sym
.value
= sym
->value
;
9439 new_map_sym
.type
= name
[1];
9441 /* Assume that most mapping symbols appear in order of increasing
9442 value. If they were randomly distributed, it would be faster to
9443 always push here and then sort at first use. */
9444 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
9446 struct arm_mapping_symbol
*prev_map_sym
;
9448 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
9449 if (prev_map_sym
->value
>= sym
->value
)
9452 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
9453 arm_compare_mapping_symbols
);
9454 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
9459 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
9463 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
9465 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
9466 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
9468 /* If necessary, set the T bit. */
9471 ULONGEST val
, t_bit
;
9472 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
9473 t_bit
= arm_psr_thumb_bit (gdbarch
);
9474 if (arm_pc_is_thumb (gdbarch
, pc
))
9475 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
9478 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
9483 /* Read the contents of a NEON quad register, by reading from two
9484 double registers. This is used to implement the quad pseudo
9485 registers, and for argument passing in case the quad registers are
9486 missing; vectors are passed in quad registers when using the VFP
9487 ABI, even if a NEON unit is not present. REGNUM is the index of
9488 the quad register, in [0, 15]. */
9490 static enum register_status
9491 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9492 int regnum
, gdb_byte
*buf
)
9495 gdb_byte reg_buf
[8];
9496 int offset
, double_regnum
;
9497 enum register_status status
;
9499 sprintf (name_buf
, "d%d", regnum
<< 1);
9500 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9503 /* d0 is always the least significant half of q0. */
9504 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9509 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9510 if (status
!= REG_VALID
)
9512 memcpy (buf
+ offset
, reg_buf
, 8);
9514 offset
= 8 - offset
;
9515 status
= regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
9516 if (status
!= REG_VALID
)
9518 memcpy (buf
+ offset
, reg_buf
, 8);
9523 static enum register_status
9524 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9525 int regnum
, gdb_byte
*buf
)
9527 const int num_regs
= gdbarch_num_regs (gdbarch
);
9529 gdb_byte reg_buf
[8];
9530 int offset
, double_regnum
;
9532 gdb_assert (regnum
>= num_regs
);
9535 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
9536 /* Quad-precision register. */
9537 return arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
9540 enum register_status status
;
9542 /* Single-precision register. */
9543 gdb_assert (regnum
< 32);
9545 /* s0 is always the least significant half of d0. */
9546 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9547 offset
= (regnum
& 1) ? 0 : 4;
9549 offset
= (regnum
& 1) ? 4 : 0;
9551 sprintf (name_buf
, "d%d", regnum
>> 1);
9552 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9555 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9556 if (status
== REG_VALID
)
9557 memcpy (buf
, reg_buf
+ offset
, 4);
9562 /* Store the contents of BUF to a NEON quad register, by writing to
9563 two double registers. This is used to implement the quad pseudo
9564 registers, and for argument passing in case the quad registers are
9565 missing; vectors are passed in quad registers when using the VFP
9566 ABI, even if a NEON unit is not present. REGNUM is the index
9567 of the quad register, in [0, 15]. */
9570 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9571 int regnum
, const gdb_byte
*buf
)
9574 int offset
, double_regnum
;
9576 sprintf (name_buf
, "d%d", regnum
<< 1);
9577 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9580 /* d0 is always the least significant half of q0. */
9581 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9586 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
9587 offset
= 8 - offset
;
9588 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
9592 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9593 int regnum
, const gdb_byte
*buf
)
9595 const int num_regs
= gdbarch_num_regs (gdbarch
);
9597 gdb_byte reg_buf
[8];
9598 int offset
, double_regnum
;
9600 gdb_assert (regnum
>= num_regs
);
9603 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
9604 /* Quad-precision register. */
9605 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
9608 /* Single-precision register. */
9609 gdb_assert (regnum
< 32);
9611 /* s0 is always the least significant half of d0. */
9612 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9613 offset
= (regnum
& 1) ? 0 : 4;
9615 offset
= (regnum
& 1) ? 4 : 0;
9617 sprintf (name_buf
, "d%d", regnum
>> 1);
9618 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9621 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9622 memcpy (reg_buf
+ offset
, buf
, 4);
9623 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
9627 static struct value
*
9628 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
9630 const int *reg_p
= baton
;
9631 return value_of_register (*reg_p
, frame
);
9634 static enum gdb_osabi
9635 arm_elf_osabi_sniffer (bfd
*abfd
)
9637 unsigned int elfosabi
;
9638 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
9640 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
9642 if (elfosabi
== ELFOSABI_ARM
)
9643 /* GNU tools use this value. Check note sections in this case,
9645 bfd_map_over_sections (abfd
,
9646 generic_elf_osabi_sniff_abi_tag_sections
,
9649 /* Anything else will be handled by the generic ELF sniffer. */
9654 arm_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
9655 struct reggroup
*group
)
9657 /* FPS register's type is INT, but belongs to float_reggroup. Beside
9658 this, FPS register belongs to save_regroup, restore_reggroup, and
9659 all_reggroup, of course. */
9660 if (regnum
== ARM_FPS_REGNUM
)
9661 return (group
== float_reggroup
9662 || group
== save_reggroup
9663 || group
== restore_reggroup
9664 || group
== all_reggroup
);
9666 return default_register_reggroup_p (gdbarch
, regnum
, group
);
9670 /* For backward-compatibility we allow two 'g' packet lengths with
9671 the remote protocol depending on whether FPA registers are
9672 supplied. M-profile targets do not have FPA registers, but some
9673 stubs already exist in the wild which use a 'g' packet which
9674 supplies them albeit with dummy values. The packet format which
9675 includes FPA registers should be considered deprecated for
9676 M-profile targets. */
9679 arm_register_g_packet_guesses (struct gdbarch
*gdbarch
)
9681 if (gdbarch_tdep (gdbarch
)->is_m
)
9683 /* If we know from the executable this is an M-profile target,
9684 cater for remote targets whose register set layout is the
9685 same as the FPA layout. */
9686 register_remote_g_packet_guess (gdbarch
,
9687 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
9688 (16 * INT_REGISTER_SIZE
)
9689 + (8 * FP_REGISTER_SIZE
)
9690 + (2 * INT_REGISTER_SIZE
),
9691 tdesc_arm_with_m_fpa_layout
);
9693 /* The regular M-profile layout. */
9694 register_remote_g_packet_guess (gdbarch
,
9695 /* r0-r12,sp,lr,pc; xpsr */
9696 (16 * INT_REGISTER_SIZE
)
9697 + INT_REGISTER_SIZE
,
9700 /* M-profile plus M4F VFP. */
9701 register_remote_g_packet_guess (gdbarch
,
9702 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
9703 (16 * INT_REGISTER_SIZE
)
9704 + (16 * VFP_REGISTER_SIZE
)
9705 + (2 * INT_REGISTER_SIZE
),
9706 tdesc_arm_with_m_vfp_d16
);
9709 /* Otherwise we don't have a useful guess. */
9713 /* Initialize the current architecture based on INFO. If possible,
9714 re-use an architecture from ARCHES, which is a list of
9715 architectures already created during this debugging session.
9717 Called e.g. at program startup, when reading a core file, and when
9718 reading a binary file. */
9720 static struct gdbarch
*
9721 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
9723 struct gdbarch_tdep
*tdep
;
9724 struct gdbarch
*gdbarch
;
9725 struct gdbarch_list
*best_arch
;
9726 enum arm_abi_kind arm_abi
= arm_abi_global
;
9727 enum arm_float_model fp_model
= arm_fp_model
;
9728 struct tdesc_arch_data
*tdesc_data
= NULL
;
9730 int have_vfp_registers
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
9732 int have_fpa_registers
= 1;
9733 const struct target_desc
*tdesc
= info
.target_desc
;
9735 /* If we have an object to base this architecture on, try to determine
9738 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
9740 int ei_osabi
, e_flags
;
9742 switch (bfd_get_flavour (info
.abfd
))
9744 case bfd_target_aout_flavour
:
9745 /* Assume it's an old APCS-style ABI. */
9746 arm_abi
= ARM_ABI_APCS
;
9749 case bfd_target_coff_flavour
:
9750 /* Assume it's an old APCS-style ABI. */
9752 arm_abi
= ARM_ABI_APCS
;
9755 case bfd_target_elf_flavour
:
9756 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
9757 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9759 if (ei_osabi
== ELFOSABI_ARM
)
9761 /* GNU tools used to use this value, but do not for EABI
9762 objects. There's nowhere to tag an EABI version
9763 anyway, so assume APCS. */
9764 arm_abi
= ARM_ABI_APCS
;
9766 else if (ei_osabi
== ELFOSABI_NONE
)
9768 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
9769 int attr_arch
, attr_profile
;
9773 case EF_ARM_EABI_UNKNOWN
:
9774 /* Assume GNU tools. */
9775 arm_abi
= ARM_ABI_APCS
;
9778 case EF_ARM_EABI_VER4
:
9779 case EF_ARM_EABI_VER5
:
9780 arm_abi
= ARM_ABI_AAPCS
;
9781 /* EABI binaries default to VFP float ordering.
9782 They may also contain build attributes that can
9783 be used to identify if the VFP argument-passing
9785 if (fp_model
== ARM_FLOAT_AUTO
)
9788 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
9793 /* "The user intended FP parameter/result
9794 passing to conform to AAPCS, base
9796 fp_model
= ARM_FLOAT_SOFT_VFP
;
9799 /* "The user intended FP parameter/result
9800 passing to conform to AAPCS, VFP
9802 fp_model
= ARM_FLOAT_VFP
;
9805 /* "The user intended FP parameter/result
9806 passing to conform to tool chain-specific
9807 conventions" - we don't know any such
9808 conventions, so leave it as "auto". */
9811 /* Attribute value not mentioned in the
9812 October 2008 ABI, so leave it as
9817 fp_model
= ARM_FLOAT_SOFT_VFP
;
9823 /* Leave it as "auto". */
9824 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
9829 /* Detect M-profile programs. This only works if the
9830 executable file includes build attributes; GCC does
9831 copy them to the executable, but e.g. RealView does
9833 attr_arch
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
9835 attr_profile
= bfd_elf_get_obj_attr_int (info
.abfd
,
9837 Tag_CPU_arch_profile
);
9838 /* GCC specifies the profile for v6-M; RealView only
9839 specifies the profile for architectures starting with
9840 V7 (as opposed to architectures with a tag
9841 numerically greater than TAG_CPU_ARCH_V7). */
9842 if (!tdesc_has_registers (tdesc
)
9843 && (attr_arch
== TAG_CPU_ARCH_V6_M
9844 || attr_arch
== TAG_CPU_ARCH_V6S_M
9845 || attr_profile
== 'M'))
9850 if (fp_model
== ARM_FLOAT_AUTO
)
9852 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9854 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
9857 /* Leave it as "auto". Strictly speaking this case
9858 means FPA, but almost nobody uses that now, and
9859 many toolchains fail to set the appropriate bits
9860 for the floating-point model they use. */
9862 case EF_ARM_SOFT_FLOAT
:
9863 fp_model
= ARM_FLOAT_SOFT_FPA
;
9865 case EF_ARM_VFP_FLOAT
:
9866 fp_model
= ARM_FLOAT_VFP
;
9868 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
9869 fp_model
= ARM_FLOAT_SOFT_VFP
;
9874 if (e_flags
& EF_ARM_BE8
)
9875 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
9880 /* Leave it as "auto". */
9885 /* Check any target description for validity. */
9886 if (tdesc_has_registers (tdesc
))
9888 /* For most registers we require GDB's default names; but also allow
9889 the numeric names for sp / lr / pc, as a convenience. */
9890 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
9891 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
9892 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
9894 const struct tdesc_feature
*feature
;
9897 feature
= tdesc_find_feature (tdesc
,
9898 "org.gnu.gdb.arm.core");
9899 if (feature
== NULL
)
9901 feature
= tdesc_find_feature (tdesc
,
9902 "org.gnu.gdb.arm.m-profile");
9903 if (feature
== NULL
)
9909 tdesc_data
= tdesc_data_alloc ();
9912 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
9913 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9914 arm_register_names
[i
]);
9915 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9918 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9921 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9925 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9926 ARM_PS_REGNUM
, "xpsr");
9928 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9929 ARM_PS_REGNUM
, "cpsr");
9933 tdesc_data_cleanup (tdesc_data
);
9937 feature
= tdesc_find_feature (tdesc
,
9938 "org.gnu.gdb.arm.fpa");
9939 if (feature
!= NULL
)
9942 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
9943 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9944 arm_register_names
[i
]);
9947 tdesc_data_cleanup (tdesc_data
);
9952 have_fpa_registers
= 0;
9954 feature
= tdesc_find_feature (tdesc
,
9955 "org.gnu.gdb.xscale.iwmmxt");
9956 if (feature
!= NULL
)
9958 static const char *const iwmmxt_names
[] = {
9959 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
9960 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
9961 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
9962 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
9966 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
9968 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9969 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9971 /* Check for the control registers, but do not fail if they
9973 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
9974 tdesc_numbered_register (feature
, tdesc_data
, i
,
9975 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9977 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
9979 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9980 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9984 tdesc_data_cleanup (tdesc_data
);
9989 /* If we have a VFP unit, check whether the single precision registers
9990 are present. If not, then we will synthesize them as pseudo
9992 feature
= tdesc_find_feature (tdesc
,
9993 "org.gnu.gdb.arm.vfp");
9994 if (feature
!= NULL
)
9996 static const char *const vfp_double_names
[] = {
9997 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
9998 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
9999 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
10000 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
10003 /* Require the double precision registers. There must be either
10006 for (i
= 0; i
< 32; i
++)
10008 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10010 vfp_double_names
[i
]);
10014 if (!valid_p
&& i
== 16)
10017 /* Also require FPSCR. */
10018 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10019 ARM_FPSCR_REGNUM
, "fpscr");
10022 tdesc_data_cleanup (tdesc_data
);
10026 if (tdesc_unnumbered_register (feature
, "s0") == 0)
10027 have_vfp_pseudos
= 1;
10029 have_vfp_registers
= 1;
10031 /* If we have VFP, also check for NEON. The architecture allows
10032 NEON without VFP (integer vector operations only), but GDB
10033 does not support that. */
10034 feature
= tdesc_find_feature (tdesc
,
10035 "org.gnu.gdb.arm.neon");
10036 if (feature
!= NULL
)
10038 /* NEON requires 32 double-precision registers. */
10041 tdesc_data_cleanup (tdesc_data
);
10045 /* If there are quad registers defined by the stub, use
10046 their type; otherwise (normally) provide them with
10047 the default type. */
10048 if (tdesc_unnumbered_register (feature
, "q0") == 0)
10049 have_neon_pseudos
= 1;
10056 /* If there is already a candidate, use it. */
10057 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
10059 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
10061 if (arm_abi
!= ARM_ABI_AUTO
10062 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
10065 if (fp_model
!= ARM_FLOAT_AUTO
10066 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
10069 /* There are various other properties in tdep that we do not
10070 need to check here: those derived from a target description,
10071 since gdbarches with a different target description are
10072 automatically disqualified. */
10074 /* Do check is_m, though, since it might come from the binary. */
10075 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
10078 /* Found a match. */
10082 if (best_arch
!= NULL
)
10084 if (tdesc_data
!= NULL
)
10085 tdesc_data_cleanup (tdesc_data
);
10086 return best_arch
->gdbarch
;
10089 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
10090 gdbarch
= gdbarch_alloc (&info
, tdep
);
10092 /* Record additional information about the architecture we are defining.
10093 These are gdbarch discriminators, like the OSABI. */
10094 tdep
->arm_abi
= arm_abi
;
10095 tdep
->fp_model
= fp_model
;
10097 tdep
->have_fpa_registers
= have_fpa_registers
;
10098 tdep
->have_vfp_registers
= have_vfp_registers
;
10099 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
10100 tdep
->have_neon_pseudos
= have_neon_pseudos
;
10101 tdep
->have_neon
= have_neon
;
10103 arm_register_g_packet_guesses (gdbarch
);
10106 switch (info
.byte_order_for_code
)
10108 case BFD_ENDIAN_BIG
:
10109 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
10110 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
10111 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
10112 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
10116 case BFD_ENDIAN_LITTLE
:
10117 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
10118 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
10119 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
10120 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
10125 internal_error (__FILE__
, __LINE__
,
10126 _("arm_gdbarch_init: bad byte order for float format"));
10129 /* On ARM targets char defaults to unsigned. */
10130 set_gdbarch_char_signed (gdbarch
, 0);
10132 /* Note: for displaced stepping, this includes the breakpoint, and one word
10133 of additional scratch space. This setting isn't used for anything beside
10134 displaced stepping at present. */
10135 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
10137 /* This should be low enough for everything. */
10138 tdep
->lowest_pc
= 0x20;
10139 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
10141 /* The default, for both APCS and AAPCS, is to return small
10142 structures in registers. */
10143 tdep
->struct_return
= reg_struct_return
;
10145 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
10146 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
10148 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
10150 /* Frame handling. */
10151 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
10152 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
10153 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
10155 frame_base_set_default (gdbarch
, &arm_normal_base
);
10157 /* Address manipulation. */
10158 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
10159 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
10161 /* Advance PC across function entry code. */
10162 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
10164 /* Detect whether PC is in function epilogue. */
10165 set_gdbarch_in_function_epilogue_p (gdbarch
, arm_in_function_epilogue_p
);
10167 /* Skip trampolines. */
10168 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
10170 /* The stack grows downward. */
10171 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
10173 /* Breakpoint manipulation. */
10174 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
10175 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
10176 arm_remote_breakpoint_from_pc
);
10178 /* Information about registers, etc. */
10179 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
10180 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
10181 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
10182 set_gdbarch_register_type (gdbarch
, arm_register_type
);
10183 set_gdbarch_register_reggroup_p (gdbarch
, arm_register_reggroup_p
);
10185 /* This "info float" is FPA-specific. Use the generic version if we
10186 do not have FPA. */
10187 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
10188 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
10190 /* Internal <-> external register number maps. */
10191 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
10192 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
10194 set_gdbarch_register_name (gdbarch
, arm_register_name
);
10196 /* Returning results. */
10197 set_gdbarch_return_value (gdbarch
, arm_return_value
);
10200 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
10202 /* Minsymbol frobbing. */
10203 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
10204 set_gdbarch_coff_make_msymbol_special (gdbarch
,
10205 arm_coff_make_msymbol_special
);
10206 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
10208 /* Thumb-2 IT block support. */
10209 set_gdbarch_adjust_breakpoint_address (gdbarch
,
10210 arm_adjust_breakpoint_address
);
10212 /* Virtual tables. */
10213 set_gdbarch_vbit_in_delta (gdbarch
, 1);
10215 /* Hook in the ABI-specific overrides, if they have been registered. */
10216 gdbarch_init_osabi (info
, gdbarch
);
10218 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
10220 /* Add some default predicates. */
10221 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
10222 dwarf2_append_unwinders (gdbarch
);
10223 frame_unwind_append_unwinder (gdbarch
, &arm_exidx_unwind
);
10224 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
10226 /* Now we have tuned the configuration, set a few final things,
10227 based on what the OS ABI has told us. */
10229 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
10230 binaries are always marked. */
10231 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
10232 tdep
->arm_abi
= ARM_ABI_APCS
;
10234 /* Watchpoints are not steppable. */
10235 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
10237 /* We used to default to FPA for generic ARM, but almost nobody
10238 uses that now, and we now provide a way for the user to force
10239 the model. So default to the most useful variant. */
10240 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
10241 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
10243 if (tdep
->jb_pc
>= 0)
10244 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
10246 /* Floating point sizes and format. */
10247 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
10248 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
10250 set_gdbarch_double_format
10251 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
10252 set_gdbarch_long_double_format
10253 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
10257 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
10258 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
10261 if (have_vfp_pseudos
)
10263 /* NOTE: These are the only pseudo registers used by
10264 the ARM target at the moment. If more are added, a
10265 little more care in numbering will be needed. */
10267 int num_pseudos
= 32;
10268 if (have_neon_pseudos
)
10270 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
10271 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
10272 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
10277 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
10279 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
10281 /* Override tdesc_register_type to adjust the types of VFP
10282 registers for NEON. */
10283 set_gdbarch_register_type (gdbarch
, arm_register_type
);
10286 /* Add standard register aliases. We add aliases even for those
10287 nanes which are used by the current architecture - it's simpler,
10288 and does no harm, since nothing ever lists user registers. */
10289 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
10290 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
10291 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
10297 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
10299 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
10304 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
10305 (unsigned long) tdep
->lowest_pc
);
10308 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
10311 _initialize_arm_tdep (void)
10313 struct ui_file
*stb
;
10315 struct cmd_list_element
*new_set
, *new_show
;
10316 const char *setname
;
10317 const char *setdesc
;
10318 const char *const *regnames
;
10320 static char *helptext
;
10321 char regdesc
[1024], *rdptr
= regdesc
;
10322 size_t rest
= sizeof (regdesc
);
10324 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
10326 arm_objfile_data_key
10327 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
10329 /* Add ourselves to objfile event chain. */
10330 observer_attach_new_objfile (arm_exidx_new_objfile
);
10332 = register_objfile_data_with_cleanup (NULL
, arm_exidx_data_free
);
10334 /* Register an ELF OS ABI sniffer for ARM binaries. */
10335 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
10336 bfd_target_elf_flavour
,
10337 arm_elf_osabi_sniffer
);
10339 /* Initialize the standard target descriptions. */
10340 initialize_tdesc_arm_with_m ();
10341 initialize_tdesc_arm_with_m_fpa_layout ();
10342 initialize_tdesc_arm_with_m_vfp_d16 ();
10343 initialize_tdesc_arm_with_iwmmxt ();
10344 initialize_tdesc_arm_with_vfpv2 ();
10345 initialize_tdesc_arm_with_vfpv3 ();
10346 initialize_tdesc_arm_with_neon ();
10348 /* Get the number of possible sets of register names defined in opcodes. */
10349 num_disassembly_options
= get_arm_regname_num_options ();
10351 /* Add root prefix command for all "set arm"/"show arm" commands. */
10352 add_prefix_cmd ("arm", no_class
, set_arm_command
,
10353 _("Various ARM-specific commands."),
10354 &setarmcmdlist
, "set arm ", 0, &setlist
);
10356 add_prefix_cmd ("arm", no_class
, show_arm_command
,
10357 _("Various ARM-specific commands."),
10358 &showarmcmdlist
, "show arm ", 0, &showlist
);
10360 /* Sync the opcode insn printer with our register viewer. */
10361 parse_arm_disassembler_option ("reg-names-std");
10363 /* Initialize the array that will be passed to
10364 add_setshow_enum_cmd(). */
10365 valid_disassembly_styles
10366 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
10367 for (i
= 0; i
< num_disassembly_options
; i
++)
10369 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
10370 valid_disassembly_styles
[i
] = setname
;
10371 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
10374 /* When we find the default names, tell the disassembler to use
10376 if (!strcmp (setname
, "std"))
10378 disassembly_style
= setname
;
10379 set_arm_regname_option (i
);
10382 /* Mark the end of valid options. */
10383 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
10385 /* Create the help text. */
10386 stb
= mem_fileopen ();
10387 fprintf_unfiltered (stb
, "%s%s%s",
10388 _("The valid values are:\n"),
10390 _("The default is \"std\"."));
10391 helptext
= ui_file_xstrdup (stb
, NULL
);
10392 ui_file_delete (stb
);
10394 add_setshow_enum_cmd("disassembler", no_class
,
10395 valid_disassembly_styles
, &disassembly_style
,
10396 _("Set the disassembly style."),
10397 _("Show the disassembly style."),
10399 set_disassembly_style_sfunc
,
10400 NULL
, /* FIXME: i18n: The disassembly style is
10402 &setarmcmdlist
, &showarmcmdlist
);
10404 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
10405 _("Set usage of ARM 32-bit mode."),
10406 _("Show usage of ARM 32-bit mode."),
10407 _("When off, a 26-bit PC will be used."),
10409 NULL
, /* FIXME: i18n: Usage of ARM 32-bit
10411 &setarmcmdlist
, &showarmcmdlist
);
10413 /* Add a command to allow the user to force the FPU model. */
10414 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
10415 _("Set the floating point type."),
10416 _("Show the floating point type."),
10417 _("auto - Determine the FP typefrom the OS-ABI.\n\
10418 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
10419 fpa - FPA co-processor (GCC compiled).\n\
10420 softvfp - Software FP with pure-endian doubles.\n\
10421 vfp - VFP co-processor."),
10422 set_fp_model_sfunc
, show_fp_model
,
10423 &setarmcmdlist
, &showarmcmdlist
);
10425 /* Add a command to allow the user to force the ABI. */
10426 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
10428 _("Show the ABI."),
10429 NULL
, arm_set_abi
, arm_show_abi
,
10430 &setarmcmdlist
, &showarmcmdlist
);
10432 /* Add two commands to allow the user to force the assumed
10434 add_setshow_enum_cmd ("fallback-mode", class_support
,
10435 arm_mode_strings
, &arm_fallback_mode_string
,
10436 _("Set the mode assumed when symbols are unavailable."),
10437 _("Show the mode assumed when symbols are unavailable."),
10438 NULL
, NULL
, arm_show_fallback_mode
,
10439 &setarmcmdlist
, &showarmcmdlist
);
10440 add_setshow_enum_cmd ("force-mode", class_support
,
10441 arm_mode_strings
, &arm_force_mode_string
,
10442 _("Set the mode assumed even when symbols are available."),
10443 _("Show the mode assumed even when symbols are available."),
10444 NULL
, NULL
, arm_show_force_mode
,
10445 &setarmcmdlist
, &showarmcmdlist
);
10447 /* Debugging flag. */
10448 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
10449 _("Set ARM debugging."),
10450 _("Show ARM debugging."),
10451 _("When on, arm-specific debugging is enabled."),
10453 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
10454 &setdebuglist
, &showdebuglist
);
10457 /* ARM-reversible process record data structures. */
10459 #define ARM_INSN_SIZE_BYTES 4
10460 #define THUMB_INSN_SIZE_BYTES 2
10461 #define THUMB2_INSN_SIZE_BYTES 4
10464 #define INSN_S_L_BIT_NUM 20
10466 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
10469 unsigned int reg_len = LENGTH; \
10472 REGS = XNEWVEC (uint32_t, reg_len); \
10473 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
10478 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
10481 unsigned int mem_len = LENGTH; \
10484 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
10485 memcpy(&MEMS->len, &RECORD_BUF[0], \
10486 sizeof(struct arm_mem_r) * LENGTH); \
10491 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
10492 #define INSN_RECORDED(ARM_RECORD) \
10493 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
10495 /* ARM memory record structure. */
10498 uint32_t len
; /* Record length. */
10499 CORE_ADDR addr
; /* Memory address. */
10502 /* ARM instruction record contains opcode of current insn
10503 and execution state (before entry to decode_insn()),
10504 contains list of to-be-modified registers and
10505 memory blocks (on return from decode_insn()). */
10507 typedef struct insn_decode_record_t
10509 struct gdbarch
*gdbarch
;
10510 struct regcache
*regcache
;
10511 CORE_ADDR this_addr
; /* Address of the insn being decoded. */
10512 uint32_t arm_insn
; /* Should accommodate thumb. */
10513 uint32_t cond
; /* Condition code. */
10514 uint32_t opcode
; /* Insn opcode. */
10515 uint32_t decode
; /* Insn decode bits. */
10516 uint32_t mem_rec_count
; /* No of mem records. */
10517 uint32_t reg_rec_count
; /* No of reg records. */
10518 uint32_t *arm_regs
; /* Registers to be saved for this record. */
10519 struct arm_mem_r
*arm_mems
; /* Memory to be saved for this record. */
10520 } insn_decode_record
;
10523 /* Checks ARM SBZ and SBO mandatory fields. */
10526 sbo_sbz (uint32_t insn
, uint32_t bit_num
, uint32_t len
, uint32_t sbo
)
10528 uint32_t ones
= bits (insn
, bit_num
- 1, (bit_num
-1) + (len
- 1));
10551 } arm_record_strx_t
;
10562 arm_record_strx (insn_decode_record
*arm_insn_r
, uint32_t *record_buf
,
10563 uint32_t *record_buf_mem
, arm_record_strx_t str_type
)
10566 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10567 ULONGEST u_regval
[2]= {0};
10569 uint32_t reg_src1
= 0, reg_src2
= 0;
10570 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
10571 uint32_t opcode1
= 0;
10573 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10574 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10575 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
10578 if (14 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10580 /* 1) Handle misc store, immediate offset. */
10581 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
10582 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
10583 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10584 regcache_raw_read_unsigned (reg_cache
, reg_src1
,
10586 if (ARM_PC_REGNUM
== reg_src1
)
10588 /* If R15 was used as Rn, hence current PC+8. */
10589 u_regval
[0] = u_regval
[0] + 8;
10591 offset_8
= (immed_high
<< 4) | immed_low
;
10592 /* Calculate target store address. */
10593 if (14 == arm_insn_r
->opcode
)
10595 tgt_mem_addr
= u_regval
[0] + offset_8
;
10599 tgt_mem_addr
= u_regval
[0] - offset_8
;
10601 if (ARM_RECORD_STRH
== str_type
)
10603 record_buf_mem
[0] = 2;
10604 record_buf_mem
[1] = tgt_mem_addr
;
10605 arm_insn_r
->mem_rec_count
= 1;
10607 else if (ARM_RECORD_STRD
== str_type
)
10609 record_buf_mem
[0] = 4;
10610 record_buf_mem
[1] = tgt_mem_addr
;
10611 record_buf_mem
[2] = 4;
10612 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10613 arm_insn_r
->mem_rec_count
= 2;
10616 else if (12 == arm_insn_r
->opcode
|| 8 == arm_insn_r
->opcode
)
10618 /* 2) Store, register offset. */
10620 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10622 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10623 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10624 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10625 if (15 == reg_src2
)
10627 /* If R15 was used as Rn, hence current PC+8. */
10628 u_regval
[0] = u_regval
[0] + 8;
10630 /* Calculate target store address, Rn +/- Rm, register offset. */
10631 if (12 == arm_insn_r
->opcode
)
10633 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10637 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10639 if (ARM_RECORD_STRH
== str_type
)
10641 record_buf_mem
[0] = 2;
10642 record_buf_mem
[1] = tgt_mem_addr
;
10643 arm_insn_r
->mem_rec_count
= 1;
10645 else if (ARM_RECORD_STRD
== str_type
)
10647 record_buf_mem
[0] = 4;
10648 record_buf_mem
[1] = tgt_mem_addr
;
10649 record_buf_mem
[2] = 4;
10650 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10651 arm_insn_r
->mem_rec_count
= 2;
10654 else if (11 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10655 || 2 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
10657 /* 3) Store, immediate pre-indexed. */
10658 /* 5) Store, immediate post-indexed. */
10659 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
10660 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
10661 offset_8
= (immed_high
<< 4) | immed_low
;
10662 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10663 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10664 /* Calculate target store address, Rn +/- Rm, register offset. */
10665 if (15 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
10667 tgt_mem_addr
= u_regval
[0] + offset_8
;
10671 tgt_mem_addr
= u_regval
[0] - offset_8
;
10673 if (ARM_RECORD_STRH
== str_type
)
10675 record_buf_mem
[0] = 2;
10676 record_buf_mem
[1] = tgt_mem_addr
;
10677 arm_insn_r
->mem_rec_count
= 1;
10679 else if (ARM_RECORD_STRD
== str_type
)
10681 record_buf_mem
[0] = 4;
10682 record_buf_mem
[1] = tgt_mem_addr
;
10683 record_buf_mem
[2] = 4;
10684 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10685 arm_insn_r
->mem_rec_count
= 2;
10687 /* Record Rn also as it changes. */
10688 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
10689 arm_insn_r
->reg_rec_count
= 1;
10691 else if (9 == arm_insn_r
->opcode
|| 13 == arm_insn_r
->opcode
10692 || 0 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
10694 /* 4) Store, register pre-indexed. */
10695 /* 6) Store, register post -indexed. */
10696 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10697 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10698 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10699 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10700 /* Calculate target store address, Rn +/- Rm, register offset. */
10701 if (13 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
10703 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10707 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10709 if (ARM_RECORD_STRH
== str_type
)
10711 record_buf_mem
[0] = 2;
10712 record_buf_mem
[1] = tgt_mem_addr
;
10713 arm_insn_r
->mem_rec_count
= 1;
10715 else if (ARM_RECORD_STRD
== str_type
)
10717 record_buf_mem
[0] = 4;
10718 record_buf_mem
[1] = tgt_mem_addr
;
10719 record_buf_mem
[2] = 4;
10720 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10721 arm_insn_r
->mem_rec_count
= 2;
10723 /* Record Rn also as it changes. */
10724 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
10725 arm_insn_r
->reg_rec_count
= 1;
10730 /* Handling ARM extension space insns. */
10733 arm_record_extension_space (insn_decode_record
*arm_insn_r
)
10735 uint32_t ret
= 0; /* Return value: -1:record failure ; 0:success */
10736 uint32_t opcode1
= 0, opcode2
= 0, insn_op1
= 0;
10737 uint32_t record_buf
[8], record_buf_mem
[8];
10738 uint32_t reg_src1
= 0;
10739 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
10740 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10741 ULONGEST u_regval
= 0;
10743 gdb_assert (!INSN_RECORDED(arm_insn_r
));
10744 /* Handle unconditional insn extension space. */
10746 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 27);
10747 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10748 if (arm_insn_r
->cond
)
10750 /* PLD has no affect on architectural state, it just affects
10752 if (5 == ((opcode1
& 0xE0) >> 5))
10755 record_buf
[0] = ARM_PS_REGNUM
;
10756 record_buf
[1] = ARM_LR_REGNUM
;
10757 arm_insn_r
->reg_rec_count
= 2;
10759 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10763 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10764 if (3 == opcode1
&& bit (arm_insn_r
->arm_insn
, 4))
10767 /* Undefined instruction on ARM V5; need to handle if later
10768 versions define it. */
10771 opcode1
= bits (arm_insn_r
->arm_insn
, 24, 27);
10772 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10773 insn_op1
= bits (arm_insn_r
->arm_insn
, 20, 23);
10775 /* Handle arithmetic insn extension space. */
10776 if (!opcode1
&& 9 == opcode2
&& 1 != arm_insn_r
->cond
10777 && !INSN_RECORDED(arm_insn_r
))
10779 /* Handle MLA(S) and MUL(S). */
10780 if (0 <= insn_op1
&& 3 >= insn_op1
)
10782 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10783 record_buf
[1] = ARM_PS_REGNUM
;
10784 arm_insn_r
->reg_rec_count
= 2;
10786 else if (4 <= insn_op1
&& 15 >= insn_op1
)
10788 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
10789 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10790 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10791 record_buf
[2] = ARM_PS_REGNUM
;
10792 arm_insn_r
->reg_rec_count
= 3;
10796 opcode1
= bits (arm_insn_r
->arm_insn
, 26, 27);
10797 opcode2
= bits (arm_insn_r
->arm_insn
, 23, 24);
10798 insn_op1
= bits (arm_insn_r
->arm_insn
, 21, 22);
10800 /* Handle control insn extension space. */
10802 if (!opcode1
&& 2 == opcode2
&& !bit (arm_insn_r
->arm_insn
, 20)
10803 && 1 != arm_insn_r
->cond
&& !INSN_RECORDED(arm_insn_r
))
10805 if (!bit (arm_insn_r
->arm_insn
,25))
10807 if (!bits (arm_insn_r
->arm_insn
, 4, 7))
10809 if ((0 == insn_op1
) || (2 == insn_op1
))
10812 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10813 arm_insn_r
->reg_rec_count
= 1;
10815 else if (1 == insn_op1
)
10817 /* CSPR is going to be changed. */
10818 record_buf
[0] = ARM_PS_REGNUM
;
10819 arm_insn_r
->reg_rec_count
= 1;
10821 else if (3 == insn_op1
)
10823 /* SPSR is going to be changed. */
10824 /* We need to get SPSR value, which is yet to be done. */
10825 printf_unfiltered (_("Process record does not support "
10826 "instruction 0x%0x at address %s.\n"),
10827 arm_insn_r
->arm_insn
,
10828 paddress (arm_insn_r
->gdbarch
,
10829 arm_insn_r
->this_addr
));
10833 else if (1 == bits (arm_insn_r
->arm_insn
, 4, 7))
10838 record_buf
[0] = ARM_PS_REGNUM
;
10839 arm_insn_r
->reg_rec_count
= 1;
10841 else if (3 == insn_op1
)
10844 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10845 arm_insn_r
->reg_rec_count
= 1;
10848 else if (3 == bits (arm_insn_r
->arm_insn
, 4, 7))
10851 record_buf
[0] = ARM_PS_REGNUM
;
10852 record_buf
[1] = ARM_LR_REGNUM
;
10853 arm_insn_r
->reg_rec_count
= 2;
10855 else if (5 == bits (arm_insn_r
->arm_insn
, 4, 7))
10857 /* QADD, QSUB, QDADD, QDSUB */
10858 record_buf
[0] = ARM_PS_REGNUM
;
10859 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10860 arm_insn_r
->reg_rec_count
= 2;
10862 else if (7 == bits (arm_insn_r
->arm_insn
, 4, 7))
10865 record_buf
[0] = ARM_PS_REGNUM
;
10866 record_buf
[1] = ARM_LR_REGNUM
;
10867 arm_insn_r
->reg_rec_count
= 2;
10869 /* Save SPSR also;how? */
10870 printf_unfiltered (_("Process record does not support "
10871 "instruction 0x%0x at address %s.\n"),
10872 arm_insn_r
->arm_insn
,
10873 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
10876 else if(8 == bits (arm_insn_r
->arm_insn
, 4, 7)
10877 || 10 == bits (arm_insn_r
->arm_insn
, 4, 7)
10878 || 12 == bits (arm_insn_r
->arm_insn
, 4, 7)
10879 || 14 == bits (arm_insn_r
->arm_insn
, 4, 7)
10882 if (0 == insn_op1
|| 1 == insn_op1
)
10884 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
10885 /* We dont do optimization for SMULW<y> where we
10887 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10888 record_buf
[1] = ARM_PS_REGNUM
;
10889 arm_insn_r
->reg_rec_count
= 2;
10891 else if (2 == insn_op1
)
10894 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10895 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
10896 arm_insn_r
->reg_rec_count
= 2;
10898 else if (3 == insn_op1
)
10901 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10902 arm_insn_r
->reg_rec_count
= 1;
10908 /* MSR : immediate form. */
10911 /* CSPR is going to be changed. */
10912 record_buf
[0] = ARM_PS_REGNUM
;
10913 arm_insn_r
->reg_rec_count
= 1;
10915 else if (3 == insn_op1
)
10917 /* SPSR is going to be changed. */
10918 /* we need to get SPSR value, which is yet to be done */
10919 printf_unfiltered (_("Process record does not support "
10920 "instruction 0x%0x at address %s.\n"),
10921 arm_insn_r
->arm_insn
,
10922 paddress (arm_insn_r
->gdbarch
,
10923 arm_insn_r
->this_addr
));
10929 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10930 opcode2
= bits (arm_insn_r
->arm_insn
, 20, 24);
10931 insn_op1
= bits (arm_insn_r
->arm_insn
, 5, 6);
10933 /* Handle load/store insn extension space. */
10935 if (!opcode1
&& bit (arm_insn_r
->arm_insn
, 7)
10936 && bit (arm_insn_r
->arm_insn
, 4) && 1 != arm_insn_r
->cond
10937 && !INSN_RECORDED(arm_insn_r
))
10942 /* These insn, changes register and memory as well. */
10943 /* SWP or SWPB insn. */
10944 /* Get memory address given by Rn. */
10945 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10946 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
10947 /* SWP insn ?, swaps word. */
10948 if (8 == arm_insn_r
->opcode
)
10950 record_buf_mem
[0] = 4;
10954 /* SWPB insn, swaps only byte. */
10955 record_buf_mem
[0] = 1;
10957 record_buf_mem
[1] = u_regval
;
10958 arm_insn_r
->mem_rec_count
= 1;
10959 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10960 arm_insn_r
->reg_rec_count
= 1;
10962 else if (1 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10965 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10968 else if (2 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10971 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10972 record_buf
[1] = record_buf
[0] + 1;
10973 arm_insn_r
->reg_rec_count
= 2;
10975 else if (3 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10978 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10981 else if (bit (arm_insn_r
->arm_insn
, 20) && insn_op1
<= 3)
10983 /* LDRH, LDRSB, LDRSH. */
10984 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10985 arm_insn_r
->reg_rec_count
= 1;
10990 opcode1
= bits (arm_insn_r
->arm_insn
, 23, 27);
10991 if (24 == opcode1
&& bit (arm_insn_r
->arm_insn
, 21)
10992 && !INSN_RECORDED(arm_insn_r
))
10995 /* Handle coprocessor insn extension space. */
10998 /* To be done for ARMv5 and later; as of now we return -1. */
11000 printf_unfiltered (_("Process record does not support instruction x%0x "
11001 "at address %s.\n"),arm_insn_r
->arm_insn
,
11002 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11005 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11006 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11011 /* Handling opcode 000 insns. */
11014 arm_record_data_proc_misc_ld_str (insn_decode_record
*arm_insn_r
)
11016 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11017 uint32_t record_buf
[8], record_buf_mem
[8];
11018 ULONGEST u_regval
[2] = {0};
11020 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
11021 uint32_t immed_high
= 0, immed_low
= 0, offset_8
= 0, tgt_mem_addr
= 0;
11022 uint32_t opcode1
= 0;
11024 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11025 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11026 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
11028 /* Data processing insn /multiply insn. */
11029 if (9 == arm_insn_r
->decode
11030 && ((4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
11031 || (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)))
11033 /* Handle multiply instructions. */
11034 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
11035 if (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)
11037 /* Handle MLA and MUL. */
11038 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
11039 record_buf
[1] = ARM_PS_REGNUM
;
11040 arm_insn_r
->reg_rec_count
= 2;
11042 else if (4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
11044 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
11045 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
11046 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
11047 record_buf
[2] = ARM_PS_REGNUM
;
11048 arm_insn_r
->reg_rec_count
= 3;
11051 else if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
11052 && (11 == arm_insn_r
->decode
|| 13 == arm_insn_r
->decode
))
11054 /* Handle misc load insns, as 20th bit (L = 1). */
11055 /* LDR insn has a capability to do branching, if
11056 MOV LR, PC is precceded by LDR insn having Rn as R15
11057 in that case, it emulates branch and link insn, and hence we
11058 need to save CSPR and PC as well. I am not sure this is right
11059 place; as opcode = 010 LDR insn make this happen, if R15 was
11061 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11062 if (15 != reg_dest
)
11064 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11065 arm_insn_r
->reg_rec_count
= 1;
11069 record_buf
[0] = reg_dest
;
11070 record_buf
[1] = ARM_PS_REGNUM
;
11071 arm_insn_r
->reg_rec_count
= 2;
11074 else if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
11075 && sbo_sbz (arm_insn_r
->arm_insn
, 5, 12, 0)
11076 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
11077 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21))
11079 /* Handle MSR insn. */
11080 if (9 == arm_insn_r
->opcode
)
11082 /* CSPR is going to be changed. */
11083 record_buf
[0] = ARM_PS_REGNUM
;
11084 arm_insn_r
->reg_rec_count
= 1;
11088 /* SPSR is going to be changed. */
11089 /* How to read SPSR value? */
11090 printf_unfiltered (_("Process record does not support instruction "
11091 "0x%0x at address %s.\n"),
11092 arm_insn_r
->arm_insn
,
11093 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11097 else if (9 == arm_insn_r
->decode
11098 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
11099 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11101 /* Handling SWP, SWPB. */
11102 /* These insn, changes register and memory as well. */
11103 /* SWP or SWPB insn. */
11105 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11106 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11107 /* SWP insn ?, swaps word. */
11108 if (8 == arm_insn_r
->opcode
)
11110 record_buf_mem
[0] = 4;
11114 /* SWPB insn, swaps only byte. */
11115 record_buf_mem
[0] = 1;
11117 record_buf_mem
[1] = u_regval
[0];
11118 arm_insn_r
->mem_rec_count
= 1;
11119 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11120 arm_insn_r
->reg_rec_count
= 1;
11122 else if (3 == arm_insn_r
->decode
&& 0x12 == opcode1
11123 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
11125 /* Handle BLX, branch and link/exchange. */
11126 if (9 == arm_insn_r
->opcode
)
11128 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
11129 and R14 stores the return address. */
11130 record_buf
[0] = ARM_PS_REGNUM
;
11131 record_buf
[1] = ARM_LR_REGNUM
;
11132 arm_insn_r
->reg_rec_count
= 2;
11135 else if (7 == arm_insn_r
->decode
&& 0x12 == opcode1
)
11137 /* Handle enhanced software breakpoint insn, BKPT. */
11138 /* CPSR is changed to be executed in ARM state, disabling normal
11139 interrupts, entering abort mode. */
11140 /* According to high vector configuration PC is set. */
11141 /* user hit breakpoint and type reverse, in
11142 that case, we need to go back with previous CPSR and
11143 Program Counter. */
11144 record_buf
[0] = ARM_PS_REGNUM
;
11145 record_buf
[1] = ARM_LR_REGNUM
;
11146 arm_insn_r
->reg_rec_count
= 2;
11148 /* Save SPSR also; how? */
11149 printf_unfiltered (_("Process record does not support instruction "
11150 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11151 paddress (arm_insn_r
->gdbarch
,
11152 arm_insn_r
->this_addr
));
11155 else if (11 == arm_insn_r
->decode
11156 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11158 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
11160 /* Handle str(x) insn */
11161 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11164 else if (1 == arm_insn_r
->decode
&& 0x12 == opcode1
11165 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
11167 /* Handle BX, branch and link/exchange. */
11168 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
11169 record_buf
[0] = ARM_PS_REGNUM
;
11170 arm_insn_r
->reg_rec_count
= 1;
11172 else if (1 == arm_insn_r
->decode
&& 0x16 == opcode1
11173 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 4, 1)
11174 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1))
11176 /* Count leading zeros: CLZ. */
11177 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11178 arm_insn_r
->reg_rec_count
= 1;
11180 else if (!bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
11181 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
11182 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1)
11183 && sbo_sbz (arm_insn_r
->arm_insn
, 1, 12, 0)
11186 /* Handle MRS insn. */
11187 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11188 arm_insn_r
->reg_rec_count
= 1;
11190 else if (arm_insn_r
->opcode
<= 15)
11192 /* Normal data processing insns. */
11193 /* Out of 11 shifter operands mode, all the insn modifies destination
11194 register, which is specified by 13-16 decode. */
11195 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11196 record_buf
[1] = ARM_PS_REGNUM
;
11197 arm_insn_r
->reg_rec_count
= 2;
11204 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11205 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11209 /* Handling opcode 001 insns. */
11212 arm_record_data_proc_imm (insn_decode_record
*arm_insn_r
)
11214 uint32_t record_buf
[8], record_buf_mem
[8];
11216 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11217 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11219 if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
11220 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21)
11221 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
11224 /* Handle MSR insn. */
11225 if (9 == arm_insn_r
->opcode
)
11227 /* CSPR is going to be changed. */
11228 record_buf
[0] = ARM_PS_REGNUM
;
11229 arm_insn_r
->reg_rec_count
= 1;
11233 /* SPSR is going to be changed. */
11236 else if (arm_insn_r
->opcode
<= 15)
11238 /* Normal data processing insns. */
11239 /* Out of 11 shifter operands mode, all the insn modifies destination
11240 register, which is specified by 13-16 decode. */
11241 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11242 record_buf
[1] = ARM_PS_REGNUM
;
11243 arm_insn_r
->reg_rec_count
= 2;
11250 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11251 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11255 /* Handling opcode 010 insns. */
11258 arm_record_ld_st_imm_offset (insn_decode_record
*arm_insn_r
)
11260 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11262 uint32_t reg_src1
= 0 , reg_dest
= 0;
11263 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
11264 uint32_t record_buf
[8], record_buf_mem
[8];
11266 ULONGEST u_regval
= 0;
11268 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11269 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11271 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11273 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11274 /* LDR insn has a capability to do branching, if
11275 MOV LR, PC is precedded by LDR insn having Rn as R15
11276 in that case, it emulates branch and link insn, and hence we
11277 need to save CSPR and PC as well. */
11278 if (ARM_PC_REGNUM
!= reg_dest
)
11280 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11281 arm_insn_r
->reg_rec_count
= 1;
11285 record_buf
[0] = reg_dest
;
11286 record_buf
[1] = ARM_PS_REGNUM
;
11287 arm_insn_r
->reg_rec_count
= 2;
11292 /* Store, immediate offset, immediate pre-indexed,
11293 immediate post-indexed. */
11294 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11295 offset_12
= bits (arm_insn_r
->arm_insn
, 0, 11);
11296 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11298 if (bit (arm_insn_r
->arm_insn
, 23))
11300 tgt_mem_addr
= u_regval
+ offset_12
;
11304 tgt_mem_addr
= u_regval
- offset_12
;
11307 switch (arm_insn_r
->opcode
)
11321 record_buf_mem
[0] = 4;
11336 record_buf_mem
[0] = 1;
11340 gdb_assert_not_reached ("no decoding pattern found");
11343 record_buf_mem
[1] = tgt_mem_addr
;
11344 arm_insn_r
->mem_rec_count
= 1;
11346 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
11347 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
11348 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
11349 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
11350 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
11351 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
11354 /* We are handling pre-indexed mode; post-indexed mode;
11355 where Rn is going to be changed. */
11356 record_buf
[0] = reg_src1
;
11357 arm_insn_r
->reg_rec_count
= 1;
11361 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11362 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11366 /* Handling opcode 011 insns. */
11369 arm_record_ld_st_reg_offset (insn_decode_record
*arm_insn_r
)
11371 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11373 uint32_t shift_imm
= 0;
11374 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
11375 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
11376 uint32_t record_buf
[8], record_buf_mem
[8];
11379 ULONGEST u_regval
[2];
11381 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11382 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11384 /* Handle enhanced store insns and LDRD DSP insn,
11385 order begins according to addressing modes for store insns
11389 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11391 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11392 /* LDR insn has a capability to do branching, if
11393 MOV LR, PC is precedded by LDR insn having Rn as R15
11394 in that case, it emulates branch and link insn, and hence we
11395 need to save CSPR and PC as well. */
11396 if (15 != reg_dest
)
11398 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11399 arm_insn_r
->reg_rec_count
= 1;
11403 record_buf
[0] = reg_dest
;
11404 record_buf
[1] = ARM_PS_REGNUM
;
11405 arm_insn_r
->reg_rec_count
= 2;
11410 if (! bits (arm_insn_r
->arm_insn
, 4, 11))
11412 /* Store insn, register offset and register pre-indexed,
11413 register post-indexed. */
11415 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
11417 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11418 regcache_raw_read_unsigned (reg_cache
, reg_src1
11420 regcache_raw_read_unsigned (reg_cache
, reg_src2
11422 if (15 == reg_src2
)
11424 /* If R15 was used as Rn, hence current PC+8. */
11425 /* Pre-indexed mode doesnt reach here ; illegal insn. */
11426 u_regval
[0] = u_regval
[0] + 8;
11428 /* Calculate target store address, Rn +/- Rm, register offset. */
11430 if (bit (arm_insn_r
->arm_insn
, 23))
11432 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
11436 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
11439 switch (arm_insn_r
->opcode
)
11453 record_buf_mem
[0] = 4;
11468 record_buf_mem
[0] = 1;
11472 gdb_assert_not_reached ("no decoding pattern found");
11475 record_buf_mem
[1] = tgt_mem_addr
;
11476 arm_insn_r
->mem_rec_count
= 1;
11478 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
11479 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
11480 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
11481 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
11482 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
11483 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
11486 /* Rn is going to be changed in pre-indexed mode and
11487 post-indexed mode as well. */
11488 record_buf
[0] = reg_src2
;
11489 arm_insn_r
->reg_rec_count
= 1;
11494 /* Store insn, scaled register offset; scaled pre-indexed. */
11495 offset_12
= bits (arm_insn_r
->arm_insn
, 5, 6);
11497 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
11499 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11500 /* Get shift_imm. */
11501 shift_imm
= bits (arm_insn_r
->arm_insn
, 7, 11);
11502 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11503 regcache_raw_read_signed (reg_cache
, reg_src1
, &s_word
);
11504 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11505 /* Offset_12 used as shift. */
11509 /* Offset_12 used as index. */
11510 offset_12
= u_regval
[0] << shift_imm
;
11514 offset_12
= (!shift_imm
)?0:u_regval
[0] >> shift_imm
;
11520 if (bit (u_regval
[0], 31))
11522 offset_12
= 0xFFFFFFFF;
11531 /* This is arithmetic shift. */
11532 offset_12
= s_word
>> shift_imm
;
11539 regcache_raw_read_unsigned (reg_cache
, ARM_PS_REGNUM
,
11541 /* Get C flag value and shift it by 31. */
11542 offset_12
= (((bit (u_regval
[1], 29)) << 31) \
11543 | (u_regval
[0]) >> 1);
11547 offset_12
= (u_regval
[0] >> shift_imm
) \
11549 (sizeof(uint32_t) - shift_imm
));
11554 gdb_assert_not_reached ("no decoding pattern found");
11558 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11560 if (bit (arm_insn_r
->arm_insn
, 23))
11562 tgt_mem_addr
= u_regval
[1] + offset_12
;
11566 tgt_mem_addr
= u_regval
[1] - offset_12
;
11569 switch (arm_insn_r
->opcode
)
11583 record_buf_mem
[0] = 4;
11598 record_buf_mem
[0] = 1;
11602 gdb_assert_not_reached ("no decoding pattern found");
11605 record_buf_mem
[1] = tgt_mem_addr
;
11606 arm_insn_r
->mem_rec_count
= 1;
11608 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
11609 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
11610 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
11611 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
11612 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
11613 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
11616 /* Rn is going to be changed in register scaled pre-indexed
11617 mode,and scaled post indexed mode. */
11618 record_buf
[0] = reg_src2
;
11619 arm_insn_r
->reg_rec_count
= 1;
11624 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11625 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11629 /* Handling opcode 100 insns. */
11632 arm_record_ld_st_multiple (insn_decode_record
*arm_insn_r
)
11634 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11636 uint32_t register_list
[16] = {0}, register_count
= 0, register_bits
= 0;
11637 uint32_t reg_src1
= 0, addr_mode
= 0, no_of_regs
= 0;
11638 uint32_t start_address
= 0, index
= 0;
11639 uint32_t record_buf
[24], record_buf_mem
[48];
11641 ULONGEST u_regval
[2] = {0};
11643 /* This mode is exclusively for load and store multiple. */
11644 /* Handle incremenrt after/before and decrment after.before mode;
11645 Rn is changing depending on W bit, but as of now we store Rn too
11646 without optimization. */
11648 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11650 /* LDM (1,2,3) where LDM (3) changes CPSR too. */
11652 if (bit (arm_insn_r
->arm_insn
, 20) && !bit (arm_insn_r
->arm_insn
, 22))
11654 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
11659 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 14);
11663 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11664 while (register_bits
)
11666 if (register_bits
& 0x00000001)
11667 register_list
[register_count
++] = 1;
11668 register_bits
= register_bits
>> 1;
11671 /* Extra space for Base Register and CPSR; wihtout optimization. */
11672 record_buf
[register_count
] = reg_src1
;
11673 record_buf
[register_count
+ 1] = ARM_PS_REGNUM
;
11674 arm_insn_r
->reg_rec_count
= register_count
+ 2;
11676 for (register_count
= 0; register_count
< no_of_regs
; register_count
++)
11678 if (register_list
[register_count
])
11680 /* Register_count gives total no of registers
11681 and dually working as reg number. */
11682 record_buf
[index
] = register_count
;
11690 /* It handles both STM(1) and STM(2). */
11691 addr_mode
= bits (arm_insn_r
->arm_insn
, 23, 24);
11693 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
11695 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11696 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11697 while (register_bits
)
11699 if (register_bits
& 0x00000001)
11701 register_bits
= register_bits
>> 1;
11706 /* Decrement after. */
11708 start_address
= (u_regval
[0]) - (register_count
* 4) + 4;
11709 arm_insn_r
->mem_rec_count
= register_count
;
11710 while (register_count
)
11712 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11713 record_buf_mem
[(register_count
* 2) - 2] = 4;
11714 start_address
= start_address
+ 4;
11719 /* Increment after. */
11721 start_address
= u_regval
[0];
11722 arm_insn_r
->mem_rec_count
= register_count
;
11723 while (register_count
)
11725 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11726 record_buf_mem
[(register_count
* 2) - 2] = 4;
11727 start_address
= start_address
+ 4;
11732 /* Decrement before. */
11735 start_address
= (u_regval
[0]) - (register_count
* 4);
11736 arm_insn_r
->mem_rec_count
= register_count
;
11737 while (register_count
)
11739 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11740 record_buf_mem
[(register_count
* 2) - 2] = 4;
11741 start_address
= start_address
+ 4;
11746 /* Increment before. */
11748 start_address
= u_regval
[0] + 4;
11749 arm_insn_r
->mem_rec_count
= register_count
;
11750 while (register_count
)
11752 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11753 record_buf_mem
[(register_count
* 2) - 2] = 4;
11754 start_address
= start_address
+ 4;
11760 gdb_assert_not_reached ("no decoding pattern found");
11764 /* Base register also changes; based on condition and W bit. */
11765 /* We save it anyway without optimization. */
11766 record_buf
[0] = reg_src1
;
11767 arm_insn_r
->reg_rec_count
= 1;
11770 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11771 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11775 /* Handling opcode 101 insns. */
11778 arm_record_b_bl (insn_decode_record
*arm_insn_r
)
11780 uint32_t record_buf
[8];
11782 /* Handle B, BL, BLX(1) insns. */
11783 /* B simply branches so we do nothing here. */
11784 /* Note: BLX(1) doesnt fall here but instead it falls into
11785 extension space. */
11786 if (bit (arm_insn_r
->arm_insn
, 24))
11788 record_buf
[0] = ARM_LR_REGNUM
;
11789 arm_insn_r
->reg_rec_count
= 1;
11792 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11797 /* Handling opcode 110 insns. */
11800 arm_record_coproc (insn_decode_record
*arm_insn_r
)
11802 printf_unfiltered (_("Process record does not support instruction "
11803 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11804 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11809 /* Handling opcode 111 insns. */
11812 arm_record_coproc_data_proc (insn_decode_record
*arm_insn_r
)
11814 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arm_insn_r
->gdbarch
);
11815 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11816 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
11818 /* Handle SWI insn; system call would be handled over here. */
11820 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 24, 27);
11821 if (15 == arm_insn_r
->opcode
)
11823 /* Handle arm syscall insn. */
11824 if (tdep
->arm_swi_record
!= NULL
)
11826 ret
= tdep
->arm_swi_record(reg_cache
);
11830 printf_unfiltered (_("no syscall record support\n"));
11835 printf_unfiltered (_("Process record does not support instruction "
11836 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11837 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11841 /* Handling opcode 000 insns. */
11844 thumb_record_shift_add_sub (insn_decode_record
*thumb_insn_r
)
11846 uint32_t record_buf
[8];
11847 uint32_t reg_src1
= 0;
11849 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11851 record_buf
[0] = ARM_PS_REGNUM
;
11852 record_buf
[1] = reg_src1
;
11853 thumb_insn_r
->reg_rec_count
= 2;
11855 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11861 /* Handling opcode 001 insns. */
11864 thumb_record_add_sub_cmp_mov (insn_decode_record
*thumb_insn_r
)
11866 uint32_t record_buf
[8];
11867 uint32_t reg_src1
= 0;
11869 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11871 record_buf
[0] = ARM_PS_REGNUM
;
11872 record_buf
[1] = reg_src1
;
11873 thumb_insn_r
->reg_rec_count
= 2;
11875 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11880 /* Handling opcode 010 insns. */
11883 thumb_record_ld_st_reg_offset (insn_decode_record
*thumb_insn_r
)
11885 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11886 uint32_t record_buf
[8], record_buf_mem
[8];
11888 uint32_t reg_src1
= 0, reg_src2
= 0;
11889 uint32_t opcode1
= 0, opcode2
= 0, opcode3
= 0;
11891 ULONGEST u_regval
[2] = {0};
11893 opcode1
= bits (thumb_insn_r
->arm_insn
, 10, 12);
11895 if (bit (thumb_insn_r
->arm_insn
, 12))
11897 /* Handle load/store register offset. */
11898 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 10);
11899 if (opcode2
>= 12 && opcode2
<= 15)
11901 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
11902 reg_src1
= bits (thumb_insn_r
->arm_insn
,0, 2);
11903 record_buf
[0] = reg_src1
;
11904 thumb_insn_r
->reg_rec_count
= 1;
11906 else if (opcode2
>= 8 && opcode2
<= 10)
11908 /* STR(2), STRB(2), STRH(2) . */
11909 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11910 reg_src2
= bits (thumb_insn_r
->arm_insn
, 6, 8);
11911 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11912 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11914 record_buf_mem
[0] = 4; /* STR (2). */
11915 else if (10 == opcode2
)
11916 record_buf_mem
[0] = 1; /* STRB (2). */
11917 else if (9 == opcode2
)
11918 record_buf_mem
[0] = 2; /* STRH (2). */
11919 record_buf_mem
[1] = u_regval
[0] + u_regval
[1];
11920 thumb_insn_r
->mem_rec_count
= 1;
11923 else if (bit (thumb_insn_r
->arm_insn
, 11))
11925 /* Handle load from literal pool. */
11927 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11928 record_buf
[0] = reg_src1
;
11929 thumb_insn_r
->reg_rec_count
= 1;
11933 opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 9);
11934 opcode3
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11935 if ((3 == opcode2
) && (!opcode3
))
11937 /* Branch with exchange. */
11938 record_buf
[0] = ARM_PS_REGNUM
;
11939 thumb_insn_r
->reg_rec_count
= 1;
11943 /* Format 8; special data processing insns. */
11944 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11945 record_buf
[0] = ARM_PS_REGNUM
;
11946 record_buf
[1] = reg_src1
;
11947 thumb_insn_r
->reg_rec_count
= 2;
11952 /* Format 5; data processing insns. */
11953 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11954 if (bit (thumb_insn_r
->arm_insn
, 7))
11956 reg_src1
= reg_src1
+ 8;
11958 record_buf
[0] = ARM_PS_REGNUM
;
11959 record_buf
[1] = reg_src1
;
11960 thumb_insn_r
->reg_rec_count
= 2;
11963 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11964 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11970 /* Handling opcode 001 insns. */
11973 thumb_record_ld_st_imm_offset (insn_decode_record
*thumb_insn_r
)
11975 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11976 uint32_t record_buf
[8], record_buf_mem
[8];
11978 uint32_t reg_src1
= 0;
11979 uint32_t opcode
= 0, immed_5
= 0;
11981 ULONGEST u_regval
= 0;
11983 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11988 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11989 record_buf
[0] = reg_src1
;
11990 thumb_insn_r
->reg_rec_count
= 1;
11995 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11996 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11997 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11998 record_buf_mem
[0] = 4;
11999 record_buf_mem
[1] = u_regval
+ (immed_5
* 4);
12000 thumb_insn_r
->mem_rec_count
= 1;
12003 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12004 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12010 /* Handling opcode 100 insns. */
12013 thumb_record_ld_st_stack (insn_decode_record
*thumb_insn_r
)
12015 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12016 uint32_t record_buf
[8], record_buf_mem
[8];
12018 uint32_t reg_src1
= 0;
12019 uint32_t opcode
= 0, immed_8
= 0, immed_5
= 0;
12021 ULONGEST u_regval
= 0;
12023 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12028 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12029 record_buf
[0] = reg_src1
;
12030 thumb_insn_r
->reg_rec_count
= 1;
12032 else if (1 == opcode
)
12035 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12036 record_buf
[0] = reg_src1
;
12037 thumb_insn_r
->reg_rec_count
= 1;
12039 else if (2 == opcode
)
12042 immed_8
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12043 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
12044 record_buf_mem
[0] = 4;
12045 record_buf_mem
[1] = u_regval
+ (immed_8
* 4);
12046 thumb_insn_r
->mem_rec_count
= 1;
12048 else if (0 == opcode
)
12051 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
12052 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12053 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12054 record_buf_mem
[0] = 2;
12055 record_buf_mem
[1] = u_regval
+ (immed_5
* 2);
12056 thumb_insn_r
->mem_rec_count
= 1;
12059 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12060 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12066 /* Handling opcode 101 insns. */
12069 thumb_record_misc (insn_decode_record
*thumb_insn_r
)
12071 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12073 uint32_t opcode
= 0, opcode1
= 0, opcode2
= 0;
12074 uint32_t register_bits
= 0, register_count
= 0;
12075 uint32_t register_list
[8] = {0}, index
= 0, start_address
= 0;
12076 uint32_t record_buf
[24], record_buf_mem
[48];
12079 ULONGEST u_regval
= 0;
12081 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12082 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12083 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 12);
12088 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12089 while (register_bits
)
12091 if (register_bits
& 0x00000001)
12092 register_list
[register_count
++] = 1;
12093 register_bits
= register_bits
>> 1;
12095 record_buf
[register_count
] = ARM_PS_REGNUM
;
12096 record_buf
[register_count
+ 1] = ARM_SP_REGNUM
;
12097 thumb_insn_r
->reg_rec_count
= register_count
+ 2;
12098 for (register_count
= 0; register_count
< 8; register_count
++)
12100 if (register_list
[register_count
])
12102 record_buf
[index
] = register_count
;
12107 else if (10 == opcode2
)
12110 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12111 regcache_raw_read_unsigned (reg_cache
, ARM_PC_REGNUM
, &u_regval
);
12112 while (register_bits
)
12114 if (register_bits
& 0x00000001)
12116 register_bits
= register_bits
>> 1;
12118 start_address
= u_regval
- \
12119 (4 * (bit (thumb_insn_r
->arm_insn
, 8) + register_count
));
12120 thumb_insn_r
->mem_rec_count
= register_count
;
12121 while (register_count
)
12123 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12124 record_buf_mem
[(register_count
* 2) - 2] = 4;
12125 start_address
= start_address
+ 4;
12128 record_buf
[0] = ARM_SP_REGNUM
;
12129 thumb_insn_r
->reg_rec_count
= 1;
12131 else if (0x1E == opcode1
)
12134 /* Handle enhanced software breakpoint insn, BKPT. */
12135 /* CPSR is changed to be executed in ARM state, disabling normal
12136 interrupts, entering abort mode. */
12137 /* According to high vector configuration PC is set. */
12138 /* User hits breakpoint and type reverse, in that case, we need to go back with
12139 previous CPSR and Program Counter. */
12140 record_buf
[0] = ARM_PS_REGNUM
;
12141 record_buf
[1] = ARM_LR_REGNUM
;
12142 thumb_insn_r
->reg_rec_count
= 2;
12143 /* We need to save SPSR value, which is not yet done. */
12144 printf_unfiltered (_("Process record does not support instruction "
12145 "0x%0x at address %s.\n"),
12146 thumb_insn_r
->arm_insn
,
12147 paddress (thumb_insn_r
->gdbarch
,
12148 thumb_insn_r
->this_addr
));
12151 else if ((0 == opcode
) || (1 == opcode
))
12153 /* ADD(5), ADD(6). */
12154 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12155 record_buf
[0] = reg_src1
;
12156 thumb_insn_r
->reg_rec_count
= 1;
12158 else if (2 == opcode
)
12160 /* ADD(7), SUB(4). */
12161 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12162 record_buf
[0] = ARM_SP_REGNUM
;
12163 thumb_insn_r
->reg_rec_count
= 1;
12166 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12167 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12173 /* Handling opcode 110 insns. */
12176 thumb_record_ldm_stm_swi (insn_decode_record
*thumb_insn_r
)
12178 struct gdbarch_tdep
*tdep
= gdbarch_tdep (thumb_insn_r
->gdbarch
);
12179 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12181 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
12182 uint32_t reg_src1
= 0;
12183 uint32_t opcode1
= 0, opcode2
= 0, register_bits
= 0, register_count
= 0;
12184 uint32_t register_list
[8] = {0}, index
= 0, start_address
= 0;
12185 uint32_t record_buf
[24], record_buf_mem
[48];
12187 ULONGEST u_regval
= 0;
12189 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12190 opcode2
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12196 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12198 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12199 while (register_bits
)
12201 if (register_bits
& 0x00000001)
12202 register_list
[register_count
++] = 1;
12203 register_bits
= register_bits
>> 1;
12205 record_buf
[register_count
] = reg_src1
;
12206 thumb_insn_r
->reg_rec_count
= register_count
+ 1;
12207 for (register_count
= 0; register_count
< 8; register_count
++)
12209 if (register_list
[register_count
])
12211 record_buf
[index
] = register_count
;
12216 else if (0 == opcode2
)
12218 /* It handles both STMIA. */
12219 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12221 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12222 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12223 while (register_bits
)
12225 if (register_bits
& 0x00000001)
12227 register_bits
= register_bits
>> 1;
12229 start_address
= u_regval
;
12230 thumb_insn_r
->mem_rec_count
= register_count
;
12231 while (register_count
)
12233 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12234 record_buf_mem
[(register_count
* 2) - 2] = 4;
12235 start_address
= start_address
+ 4;
12239 else if (0x1F == opcode1
)
12241 /* Handle arm syscall insn. */
12242 if (tdep
->arm_swi_record
!= NULL
)
12244 ret
= tdep
->arm_swi_record(reg_cache
);
12248 printf_unfiltered (_("no syscall record support\n"));
12253 /* B (1), conditional branch is automatically taken care in process_record,
12254 as PC is saved there. */
12256 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12257 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12263 /* Handling opcode 111 insns. */
12266 thumb_record_branch (insn_decode_record
*thumb_insn_r
)
12268 uint32_t record_buf
[8];
12269 uint32_t bits_h
= 0;
12271 bits_h
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12273 if (2 == bits_h
|| 3 == bits_h
)
12276 record_buf
[0] = ARM_LR_REGNUM
;
12277 thumb_insn_r
->reg_rec_count
= 1;
12279 else if (1 == bits_h
)
12282 record_buf
[0] = ARM_PS_REGNUM
;
12283 record_buf
[1] = ARM_LR_REGNUM
;
12284 thumb_insn_r
->reg_rec_count
= 2;
12287 /* B(2) is automatically taken care in process_record, as PC is
12290 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12296 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12297 and positive val on fauilure. */
12300 extract_arm_insn (insn_decode_record
*insn_record
, uint32_t insn_size
)
12302 gdb_byte buf
[insn_size
];
12304 memset (&buf
[0], 0, insn_size
);
12306 if (target_read_memory (insn_record
->this_addr
, &buf
[0], insn_size
))
12308 insn_record
->arm_insn
= (uint32_t) extract_unsigned_integer (&buf
[0],
12310 gdbarch_byte_order (insn_record
->gdbarch
));
12314 typedef int (*sti_arm_hdl_fp_t
) (insn_decode_record
*);
12316 /* Decode arm/thumb insn depending on condition cods and opcodes; and
12320 decode_insn (insn_decode_record
*arm_record
, record_type_t record_type
,
12321 uint32_t insn_size
)
12324 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */
12325 static const sti_arm_hdl_fp_t
const arm_handle_insn
[8] =
12327 arm_record_data_proc_misc_ld_str
, /* 000. */
12328 arm_record_data_proc_imm
, /* 001. */
12329 arm_record_ld_st_imm_offset
, /* 010. */
12330 arm_record_ld_st_reg_offset
, /* 011. */
12331 arm_record_ld_st_multiple
, /* 100. */
12332 arm_record_b_bl
, /* 101. */
12333 arm_record_coproc
, /* 110. */
12334 arm_record_coproc_data_proc
/* 111. */
12337 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */
12338 static const sti_arm_hdl_fp_t
const thumb_handle_insn
[8] =
12340 thumb_record_shift_add_sub
, /* 000. */
12341 thumb_record_add_sub_cmp_mov
, /* 001. */
12342 thumb_record_ld_st_reg_offset
, /* 010. */
12343 thumb_record_ld_st_imm_offset
, /* 011. */
12344 thumb_record_ld_st_stack
, /* 100. */
12345 thumb_record_misc
, /* 101. */
12346 thumb_record_ldm_stm_swi
, /* 110. */
12347 thumb_record_branch
/* 111. */
12350 uint32_t ret
= 0; /* return value: negative:failure 0:success. */
12351 uint32_t insn_id
= 0;
12353 if (extract_arm_insn (arm_record
, insn_size
))
12357 printf_unfiltered (_("Process record: error reading memory at "
12358 "addr %s len = %d.\n"),
12359 paddress (arm_record
->gdbarch
, arm_record
->this_addr
), insn_size
);
12363 else if (ARM_RECORD
== record_type
)
12365 arm_record
->cond
= bits (arm_record
->arm_insn
, 28, 31);
12366 insn_id
= bits (arm_record
->arm_insn
, 25, 27);
12367 ret
= arm_record_extension_space (arm_record
);
12368 /* If this insn has fallen into extension space
12369 then we need not decode it anymore. */
12370 if (ret
!= -1 && !INSN_RECORDED(arm_record
))
12372 ret
= arm_handle_insn
[insn_id
] (arm_record
);
12375 else if (THUMB_RECORD
== record_type
)
12377 /* As thumb does not have condition codes, we set negative. */
12378 arm_record
->cond
= -1;
12379 insn_id
= bits (arm_record
->arm_insn
, 13, 15);
12380 ret
= thumb_handle_insn
[insn_id
] (arm_record
);
12382 else if (THUMB2_RECORD
== record_type
)
12384 printf_unfiltered (_("Process record doesnt support thumb32 instruction "
12385 "0x%0x at address %s.\n"),arm_record
->arm_insn
,
12386 paddress (arm_record
->gdbarch
,
12387 arm_record
->this_addr
));
12392 /* Throw assertion. */
12393 gdb_assert_not_reached ("not a valid instruction, could not decode");
12400 /* Cleans up local record registers and memory allocations. */
12403 deallocate_reg_mem (insn_decode_record
*record
)
12405 xfree (record
->arm_regs
);
12406 xfree (record
->arm_mems
);
12410 /* Parse the current instruction and record the values of the registers and
12411 memory that will be changed in current instruction to record_arch_list".
12412 Return -1 if something is wrong. */
12415 arm_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
12416 CORE_ADDR insn_addr
)
12419 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
12420 uint32_t no_of_rec
= 0;
12421 uint32_t ret
= 0; /* return value: -1:record failure ; 0:success */
12422 ULONGEST t_bit
= 0, insn_id
= 0;
12424 ULONGEST u_regval
= 0;
12426 insn_decode_record arm_record
;
12428 memset (&arm_record
, 0, sizeof (insn_decode_record
));
12429 arm_record
.regcache
= regcache
;
12430 arm_record
.this_addr
= insn_addr
;
12431 arm_record
.gdbarch
= gdbarch
;
12434 if (record_debug
> 1)
12436 fprintf_unfiltered (gdb_stdlog
, "Process record: arm_process_record "
12438 paddress (gdbarch
, arm_record
.this_addr
));
12441 if (extract_arm_insn (&arm_record
, 2))
12445 printf_unfiltered (_("Process record: error reading memory at "
12446 "addr %s len = %d.\n"),
12447 paddress (arm_record
.gdbarch
,
12448 arm_record
.this_addr
), 2);
12453 /* Check the insn, whether it is thumb or arm one. */
12455 t_bit
= arm_psr_thumb_bit (arm_record
.gdbarch
);
12456 regcache_raw_read_unsigned (arm_record
.regcache
, ARM_PS_REGNUM
, &u_regval
);
12459 if (!(u_regval
& t_bit
))
12461 /* We are decoding arm insn. */
12462 ret
= decode_insn (&arm_record
, ARM_RECORD
, ARM_INSN_SIZE_BYTES
);
12466 insn_id
= bits (arm_record
.arm_insn
, 11, 15);
12467 /* is it thumb2 insn? */
12468 if ((0x1D == insn_id
) || (0x1E == insn_id
) || (0x1F == insn_id
))
12470 ret
= decode_insn (&arm_record
, THUMB2_RECORD
,
12471 THUMB2_INSN_SIZE_BYTES
);
12475 /* We are decoding thumb insn. */
12476 ret
= decode_insn (&arm_record
, THUMB_RECORD
, THUMB_INSN_SIZE_BYTES
);
12482 /* Record registers. */
12483 record_arch_list_add_reg (arm_record
.regcache
, ARM_PC_REGNUM
);
12484 if (arm_record
.arm_regs
)
12486 for (no_of_rec
= 0; no_of_rec
< arm_record
.reg_rec_count
; no_of_rec
++)
12488 if (record_arch_list_add_reg (arm_record
.regcache
,
12489 arm_record
.arm_regs
[no_of_rec
]))
12493 /* Record memories. */
12494 if (arm_record
.arm_mems
)
12496 for (no_of_rec
= 0; no_of_rec
< arm_record
.mem_rec_count
; no_of_rec
++)
12498 if (record_arch_list_add_mem
12499 ((CORE_ADDR
)arm_record
.arm_mems
[no_of_rec
].addr
,
12500 arm_record
.arm_mems
[no_of_rec
].len
))
12505 if (record_arch_list_add_end ())
12510 deallocate_reg_mem (&arm_record
);