1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "coff/internal.h" /* Internal format of COFF symbols in BFD */
30 #include "dis-asm.h" /* For register flavors. */
31 #include <ctype.h> /* for isupper () */
35 /* Each OS has a different mechanism for accessing the various
36 registers stored in the sigcontext structure.
38 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
39 function pointer) which may be used to determine the addresses
40 of the various saved registers in the sigcontext structure.
42 For the ARM target, there are three parameters to this function.
43 The first is the pc value of the frame under consideration, the
44 second the stack pointer of this frame, and the last is the
45 register number to fetch.
47 If the tm.h file does not define this macro, then it's assumed that
48 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
51 When it comes time to multi-arching this code, see the identically
52 named machinery in ia64-tdep.c for an example of how it could be
53 done. It should not be necessary to modify the code below where
54 this macro is used. */
56 #ifdef SIGCONTEXT_REGISTER_ADDRESS
57 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
58 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
61 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
62 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
65 extern void _initialize_arm_tdep (void);
67 /* Number of different reg name sets (options). */
68 static int num_flavor_options
;
70 /* We have more registers than the disassembler as gdb can print the value
71 of special registers as well.
72 The general register names are overwritten by whatever is being used by
73 the disassembler at the moment. We also adjust the case of cpsr and fps. */
75 /* Initial value: Register names used in ARM's ISA documentation. */
76 static char * arm_register_name_strings
[] =
77 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
78 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
79 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
80 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
81 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
82 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
83 "fps", "cpsr" }; /* 24 25 */
84 char **arm_register_names
= arm_register_name_strings
;
86 /* Valid register name flavors. */
87 static const char **valid_flavors
;
89 /* Disassembly flavor to use. Default to "std" register names. */
90 static const char *disassembly_flavor
;
91 static int current_option
; /* Index to that option in the opcodes table. */
93 /* This is used to keep the bfd arch_info in sync with the disassembly
95 static void set_disassembly_flavor_sfunc(char *, int,
96 struct cmd_list_element
*);
97 static void set_disassembly_flavor (void);
99 static void convert_from_extended (void *ptr
, void *dbl
);
101 /* Define other aspects of the stack frame. We keep the offsets of
102 all saved registers, 'cause we need 'em a lot! We also keep the
103 current size of the stack frame, and the offset of the frame
104 pointer from the stack pointer (for frameless functions, and when
105 we're still in the prologue of a function with a frame) */
107 struct frame_extra_info
109 struct frame_saved_regs fsr
;
115 /* Addresses for calling Thumb functions have the bit 0 set.
116 Here are some macros to test, set, or clear bit 0 of addresses. */
117 #define IS_THUMB_ADDR(addr) ((addr) & 1)
118 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
119 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
121 /* Will a function return an aggregate type in memory or in a
122 register? Return 0 if an aggregate type can be returned in a
123 register, 1 if it must be returned in memory. */
126 arm_use_struct_convention (int gcc_p
, struct type
*type
)
129 register enum type_code code
;
131 /* In the ARM ABI, "integer" like aggregate types are returned in
132 registers. For an aggregate type to be integer like, its size
133 must be less than or equal to REGISTER_SIZE and the offset of
134 each addressable subfield must be zero. Note that bit fields are
135 not addressable, and all addressable subfields of unions always
136 start at offset zero.
138 This function is based on the behaviour of GCC 2.95.1.
139 See: gcc/arm.c: arm_return_in_memory() for details.
141 Note: All versions of GCC before GCC 2.95.2 do not set up the
142 parameters correctly for a function returning the following
143 structure: struct { float f;}; This should be returned in memory,
144 not a register. Richard Earnshaw sent me a patch, but I do not
145 know of any way to detect if a function like the above has been
146 compiled with the correct calling convention. */
148 /* All aggregate types that won't fit in a register must be returned
150 if (TYPE_LENGTH (type
) > REGISTER_SIZE
)
155 /* The only aggregate types that can be returned in a register are
156 structs and unions. Arrays must be returned in memory. */
157 code
= TYPE_CODE (type
);
158 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
163 /* Assume all other aggregate types can be returned in a register.
164 Run a check for structures, unions and arrays. */
167 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
170 /* Need to check if this struct/union is "integer" like. For
171 this to be true, its size must be less than or equal to
172 REGISTER_SIZE and the offset of each addressable subfield
173 must be zero. Note that bit fields are not addressable, and
174 unions always start at offset zero. If any of the subfields
175 is a floating point type, the struct/union cannot be an
178 /* For each field in the object, check:
179 1) Is it FP? --> yes, nRc = 1;
180 2) Is it addressable (bitpos != 0) and
181 not packed (bitsize == 0)?
185 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
187 enum type_code field_type_code
;
188 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
190 /* Is it a floating point type field? */
191 if (field_type_code
== TYPE_CODE_FLT
)
197 /* If bitpos != 0, then we have to care about it. */
198 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
200 /* Bitfields are not addressable. If the field bitsize is
201 zero, then the field is not packed. Hence it cannot be
202 a bitfield or any other packed type. */
203 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
216 arm_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*thisframe
)
218 return (chain
!= 0 && (FRAME_SAVED_PC (thisframe
) >= LOWEST_PC
));
221 /* Set to true if the 32-bit mode is in use. */
225 /* Flag set by arm_fix_call_dummy that tells whether the target
226 function is a Thumb function. This flag is checked by
227 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
228 its use in valops.c) to pass the function address as an additional
231 static int target_is_thumb
;
233 /* Flag set by arm_fix_call_dummy that tells whether the calling
234 function is a Thumb function. This flag is checked by
235 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
237 static int caller_is_thumb
;
239 /* Determine if the program counter specified in MEMADDR is in a Thumb
243 arm_pc_is_thumb (CORE_ADDR memaddr
)
245 struct minimal_symbol
*sym
;
247 /* If bit 0 of the address is set, assume this is a Thumb address. */
248 if (IS_THUMB_ADDR (memaddr
))
251 /* Thumb functions have a "special" bit set in minimal symbols. */
252 sym
= lookup_minimal_symbol_by_pc (memaddr
);
255 return (MSYMBOL_IS_SPECIAL (sym
));
263 /* Determine if the program counter specified in MEMADDR is in a call
264 dummy being called from a Thumb function. */
267 arm_pc_is_thumb_dummy (CORE_ADDR memaddr
)
269 CORE_ADDR sp
= read_sp ();
271 /* FIXME: Until we switch for the new call dummy macros, this heuristic
272 is the best we can do. We are trying to determine if the pc is on
273 the stack, which (hopefully) will only happen in a call dummy.
274 We hope the current stack pointer is not so far alway from the dummy
275 frame location (true if we have not pushed large data structures or
276 gone too many levels deep) and that our 1024 is not enough to consider
277 code regions as part of the stack (true for most practical purposes) */
278 if (PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 1024))
279 return caller_is_thumb
;
285 arm_addr_bits_remove (CORE_ADDR val
)
287 if (arm_pc_is_thumb (val
))
288 return (val
& (arm_apcs_32
? 0xfffffffe : 0x03fffffe));
290 return (val
& (arm_apcs_32
? 0xfffffffc : 0x03fffffc));
294 arm_saved_pc_after_call (struct frame_info
*frame
)
296 return ADDR_BITS_REMOVE (read_register (LR_REGNUM
));
300 arm_frameless_function_invocation (struct frame_info
*fi
)
302 CORE_ADDR func_start
, after_prologue
;
305 func_start
= (get_pc_function_start ((fi
)->pc
) + FUNCTION_START_OFFSET
);
306 after_prologue
= SKIP_PROLOGUE (func_start
);
308 /* There are some frameless functions whose first two instructions
309 follow the standard APCS form, in which case after_prologue will
310 be func_start + 8. */
312 frameless
= (after_prologue
< func_start
+ 12);
316 /* A typical Thumb prologue looks like this:
320 Sometimes the latter instruction may be replaced by:
328 or, on tpcs, like this:
335 There is always one instruction of three classes:
340 When we have found at least one of each class we are done with the prolog.
341 Note that the "sub sp, #NN" before the push does not count.
345 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
347 CORE_ADDR current_pc
;
348 int findmask
= 0; /* findmask:
349 bit 0 - push { rlist }
350 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
351 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
354 for (current_pc
= pc
; current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40; current_pc
+= 2)
356 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
358 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
360 findmask
|= 1; /* push found */
362 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
364 if ((findmask
& 1) == 0) /* before push ? */
367 findmask
|= 4; /* add/sub sp found */
369 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
371 findmask
|= 2; /* setting of r7 found */
373 else if (insn
== 0x466f) /* mov r7, sp */
375 findmask
|= 2; /* setting of r7 found */
378 continue; /* something in the prolog that we don't care about or some
379 instruction from outside the prolog scheduled here for optimization */
385 /* The APCS (ARM Procedure Call Standard) defines the following
389 [stmfd sp!, {a1,a2,a3,a4}]
390 stmfd sp!, {...,fp,ip,lr,pc}
391 [stfe f7, [sp, #-12]!]
392 [stfe f6, [sp, #-12]!]
393 [stfe f5, [sp, #-12]!]
394 [stfe f4, [sp, #-12]!]
395 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
398 arm_skip_prologue (CORE_ADDR pc
)
402 CORE_ADDR func_addr
, func_end
;
403 struct symtab_and_line sal
;
405 /* See what the symbol table says. */
407 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
409 sal
= find_pc_line (func_addr
, 0);
410 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
414 /* Check if this is Thumb code. */
415 if (arm_pc_is_thumb (pc
))
416 return thumb_skip_prologue (pc
, func_end
);
418 /* Can't find the prologue end in the symbol table, try it the hard way
419 by disassembling the instructions. */
421 inst
= read_memory_integer (skip_pc
, 4);
422 if (inst
!= 0xe1a0c00d) /* mov ip, sp */
426 inst
= read_memory_integer (skip_pc
, 4);
427 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
430 inst
= read_memory_integer (skip_pc
, 4);
433 if ((inst
& 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */
437 inst
= read_memory_integer (skip_pc
, 4);
439 /* Any insns after this point may float into the code, if it makes
440 for better instruction scheduling, so we skip them only if we
441 find them, but still consdier the function to be frame-ful. */
443 /* We may have either one sfmfd instruction here, or several stfe
444 insns, depending on the version of floating point code we
446 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
449 inst
= read_memory_integer (skip_pc
, 4);
453 while ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
456 inst
= read_memory_integer (skip_pc
, 4);
460 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
466 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
467 This function decodes a Thumb function prologue to determine:
468 1) the size of the stack frame
469 2) which registers are saved on it
470 3) the offsets of saved regs
471 4) the offset from the stack pointer to the frame pointer
472 This information is stored in the "extra" fields of the frame_info.
474 A typical Thumb function prologue would create this stack frame
475 (offsets relative to FP)
476 old SP -> 24 stack parameters
479 R7 -> 0 local variables (16 bytes)
480 SP -> -12 additional stack space (12 bytes)
481 The frame size would thus be 36 bytes, and the frame offset would be
482 12 bytes. The frame register is R7.
484 The comments for thumb_skip_prolog() describe the algorithm we use to detect
485 the end of the prolog */
489 thumb_scan_prologue (struct frame_info
*fi
)
491 CORE_ADDR prologue_start
;
492 CORE_ADDR prologue_end
;
493 CORE_ADDR current_pc
;
494 int saved_reg
[16]; /* which register has been copied to register n? */
495 int findmask
= 0; /* findmask:
496 bit 0 - push { rlist }
497 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
498 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
502 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
504 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
506 if (sal
.line
== 0) /* no line info, use current PC */
507 prologue_end
= fi
->pc
;
508 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
509 prologue_end
= sal
.end
; /* (probably means no prologue) */
512 prologue_end
= prologue_start
+ 40; /* We're in the boondocks: allow for */
513 /* 16 pushes, an add, and "mv fp,sp" */
515 prologue_end
= min (prologue_end
, fi
->pc
);
517 /* Initialize the saved register map. When register H is copied to
518 register L, we will put H in saved_reg[L]. */
519 for (i
= 0; i
< 16; i
++)
522 /* Search the prologue looking for instructions that set up the
523 frame pointer, adjust the stack pointer, and save registers.
524 Do this until all basic prolog instructions are found. */
527 for (current_pc
= prologue_start
;
528 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
535 insn
= read_memory_unsigned_integer (current_pc
, 2);
537 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
540 findmask
|= 1; /* push found */
541 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
542 whether to save LR (R14). */
543 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
545 /* Calculate offsets of saved R0-R7 and LR. */
546 for (regno
= LR_REGNUM
; regno
>= 0; regno
--)
547 if (mask
& (1 << regno
))
550 fi
->fsr
.regs
[saved_reg
[regno
]] = -(fi
->framesize
);
551 saved_reg
[regno
] = regno
; /* reset saved register map */
554 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
556 if ((findmask
& 1) == 0) /* before push ? */
559 findmask
|= 4; /* add/sub sp found */
561 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
562 if (insn
& 0x80) /* is it signed? (==subtracting) */
564 fi
->frameoffset
+= offset
;
567 fi
->framesize
-= offset
;
569 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
571 findmask
|= 2; /* setting of r7 found */
572 fi
->framereg
= THUMB_FP_REGNUM
;
573 fi
->frameoffset
= (insn
& 0xff) << 2; /* get scaled offset */
575 else if (insn
== 0x466f) /* mov r7, sp */
577 findmask
|= 2; /* setting of r7 found */
578 fi
->framereg
= THUMB_FP_REGNUM
;
580 saved_reg
[THUMB_FP_REGNUM
] = SP_REGNUM
;
582 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
584 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
585 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
586 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
589 continue; /* something in the prolog that we don't care about or some
590 instruction from outside the prolog scheduled here for optimization */
594 /* Check if prologue for this frame's PC has already been scanned. If
595 it has, copy the relevant information about that prologue and
596 return non-zero. Otherwise do not copy anything and return zero.
598 The information saved in the cache includes:
599 * the frame register number;
600 * the size of the stack frame;
601 * the offsets of saved regs (relative to the old SP); and
602 * the offset from the stack pointer to the frame pointer
604 The cache contains only one entry, since this is adequate for the
605 typical sequence of prologue scan requests we get. When performing
606 a backtrace, GDB will usually ask to scan the same function twice
607 in a row (once to get the frame chain, and once to fill in the
608 extra frame information). */
610 static struct frame_info prologue_cache
;
613 check_prologue_cache (struct frame_info
*fi
)
617 if (fi
->pc
== prologue_cache
.pc
)
619 fi
->framereg
= prologue_cache
.framereg
;
620 fi
->framesize
= prologue_cache
.framesize
;
621 fi
->frameoffset
= prologue_cache
.frameoffset
;
622 for (i
= 0; i
< NUM_REGS
; i
++)
623 fi
->fsr
.regs
[i
] = prologue_cache
.fsr
.regs
[i
];
631 /* Copy the prologue information from fi to the prologue cache. */
634 save_prologue_cache (struct frame_info
*fi
)
638 prologue_cache
.pc
= fi
->pc
;
639 prologue_cache
.framereg
= fi
->framereg
;
640 prologue_cache
.framesize
= fi
->framesize
;
641 prologue_cache
.frameoffset
= fi
->frameoffset
;
643 for (i
= 0; i
< NUM_REGS
; i
++)
644 prologue_cache
.fsr
.regs
[i
] = fi
->fsr
.regs
[i
];
648 /* This function decodes an ARM function prologue to determine:
649 1) the size of the stack frame
650 2) which registers are saved on it
651 3) the offsets of saved regs
652 4) the offset from the stack pointer to the frame pointer
653 This information is stored in the "extra" fields of the frame_info.
655 There are two basic forms for the ARM prologue. The fixed argument
656 function call will look like:
659 stmfd sp!, {fp, ip, lr, pc}
663 Which would create this stack frame (offsets relative to FP):
664 IP -> 4 (caller's stack)
665 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
666 -4 LR (return address in caller)
667 -8 IP (copy of caller's SP)
669 SP -> -28 Local variables
671 The frame size would thus be 32 bytes, and the frame offset would be
672 28 bytes. The stmfd call can also save any of the vN registers it
673 plans to use, which increases the frame size accordingly.
675 Note: The stored PC is 8 off of the STMFD instruction that stored it
676 because the ARM Store instructions always store PC + 8 when you read
679 A variable argument function call will look like:
682 stmfd sp!, {a1, a2, a3, a4}
683 stmfd sp!, {fp, ip, lr, pc}
686 Which would create this stack frame (offsets relative to FP):
687 IP -> 20 (caller's stack)
692 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
693 -4 LR (return address in caller)
694 -8 IP (copy of caller's SP)
696 SP -> -28 Local variables
698 The frame size would thus be 48 bytes, and the frame offset would be
701 There is another potential complication, which is that the optimizer
702 will try to separate the store of fp in the "stmfd" instruction from
703 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
704 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
706 Also, note, the original version of the ARM toolchain claimed that there
709 instruction at the end of the prologue. I have never seen GCC produce
710 this, and the ARM docs don't mention it. We still test for it below in
716 arm_scan_prologue (struct frame_info
*fi
)
718 int regno
, sp_offset
, fp_offset
;
719 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
721 /* Check if this function is already in the cache of frame information. */
722 if (check_prologue_cache (fi
))
725 /* Assume there is no frame until proven otherwise. */
726 fi
->framereg
= SP_REGNUM
;
730 /* Check for Thumb prologue. */
731 if (arm_pc_is_thumb (fi
->pc
))
733 thumb_scan_prologue (fi
);
734 save_prologue_cache (fi
);
738 /* Find the function prologue. If we can't find the function in
739 the symbol table, peek in the stack frame to find the PC. */
740 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
742 /* One way to find the end of the prologue (which works well
743 for unoptimized code) is to do the following:
745 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
748 prologue_end = fi->pc;
749 else if (sal.end < prologue_end)
750 prologue_end = sal.end;
752 This mechanism is very accurate so long as the optimizer
753 doesn't move any instructions from the function body into the
754 prologue. If this happens, sal.end will be the last
755 instruction in the first hunk of prologue code just before
756 the first instruction that the scheduler has moved from
757 the body to the prologue.
759 In order to make sure that we scan all of the prologue
760 instructions, we use a slightly less accurate mechanism which
761 may scan more than necessary. To help compensate for this
762 lack of accuracy, the prologue scanning loop below contains
763 several clauses which'll cause the loop to terminate early if
764 an implausible prologue instruction is encountered.
770 is a suitable endpoint since it accounts for the largest
771 possible prologue plus up to five instructions inserted by
774 if (prologue_end
> prologue_start
+ 64)
776 prologue_end
= prologue_start
+ 64; /* See above. */
781 /* Get address of the stmfd in the prologue of the callee; the saved
782 PC is the address of the stmfd + 8. */
783 prologue_start
= ADDR_BITS_REMOVE (read_memory_integer (fi
->frame
, 4))
785 prologue_end
= prologue_start
+ 64; /* See above. */
788 /* Now search the prologue looking for instructions that set up the
789 frame pointer, adjust the stack pointer, and save registers.
791 Be careful, however, and if it doesn't look like a prologue,
792 don't try to scan it. If, for instance, a frameless function
793 begins with stmfd sp!, then we will tell ourselves there is
794 a frame, which will confuse stack traceback, as well ad"finish"
795 and other operations that rely on a knowledge of the stack
798 In the APCS, the prologue should start with "mov ip, sp" so
799 if we don't see this as the first insn, we will stop. */
801 sp_offset
= fp_offset
= 0;
803 if (read_memory_unsigned_integer (prologue_start
, 4)
804 == 0xe1a0c00d) /* mov ip, sp */
806 for (current_pc
= prologue_start
+ 4; current_pc
< prologue_end
;
809 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
811 if ((insn
& 0xffff0000) == 0xe92d0000)
812 /* stmfd sp!, {..., fp, ip, lr, pc}
814 stmfd sp!, {a1, a2, a3, a4} */
816 int mask
= insn
& 0xffff;
818 /* Calculate offsets of saved registers. */
819 for (regno
= PC_REGNUM
; regno
>= 0; regno
--)
820 if (mask
& (1 << regno
))
823 fi
->fsr
.regs
[regno
] = sp_offset
;
826 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
828 unsigned imm
= insn
& 0xff; /* immediate value */
829 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
830 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
832 fi
->framereg
= FP_REGNUM
;
834 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
836 unsigned imm
= insn
& 0xff; /* immediate value */
837 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
838 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
841 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
844 regno
= F0_REGNUM
+ ((insn
>> 12) & 0x07);
845 fi
->fsr
.regs
[regno
] = sp_offset
;
847 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
850 unsigned int fp_start_reg
, fp_bound_reg
;
852 if ((insn
& 0x800) == 0x800) /* N0 is set */
854 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
861 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
867 fp_start_reg
= F0_REGNUM
+ ((insn
>> 12) & 0x7);
868 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
869 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
872 fi
->fsr
.regs
[fp_start_reg
++] = sp_offset
;
875 else if ((insn
& 0xf0000000) != 0xe0000000)
876 break; /* Condition not true, exit early */
877 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
878 break; /* Don't scan past a block load */
880 /* The optimizer might shove anything into the prologue,
881 so we just skip what we don't recognize. */
886 /* The frame size is just the negative of the offset (from the original SP)
887 of the last thing thing we pushed on the stack. The frame offset is
888 [new FP] - [new SP]. */
889 fi
->framesize
= -sp_offset
;
890 fi
->frameoffset
= fp_offset
- sp_offset
;
892 save_prologue_cache (fi
);
895 /* Find REGNUM on the stack. Otherwise, it's in an active register.
896 One thing we might want to do here is to check REGNUM against the
897 clobber mask, and somehow flag it as invalid if it isn't saved on
898 the stack somewhere. This would provide a graceful failure mode
899 when trying to get the value of caller-saves registers for an inner
903 arm_find_callers_reg (struct frame_info
*fi
, int regnum
)
905 for (; fi
; fi
= fi
->next
)
907 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
908 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
909 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
912 if (fi
->fsr
.regs
[regnum
] != 0)
913 return read_memory_integer (fi
->fsr
.regs
[regnum
],
914 REGISTER_RAW_SIZE (regnum
));
915 return read_register (regnum
);
918 /* Function: frame_chain
919 Given a GDB frame, determine the address of the calling function's frame.
920 This will be used to create a new GDB frame struct, and then
921 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
922 For ARM, we save the frame size when we initialize the frame_info.
924 The original definition of this function was a macro in tm-arm.h:
925 { In the case of the ARM, the frame's nominal address is the FP value,
926 and 12 bytes before comes the saved previous FP value as a 4-byte word. }
928 #define FRAME_CHAIN(thisframe) \
929 ((thisframe)->pc >= LOWEST_PC ? \
930 read_memory_integer ((thisframe)->frame - 12, 4) :\
936 arm_frame_chain (struct frame_info
*fi
)
938 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
939 CORE_ADDR fn_start
, callers_pc
, fp
;
941 /* is this a dummy frame? */
942 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
943 return fi
->frame
; /* dummy frame same as caller's frame */
945 /* is caller-of-this a dummy frame? */
946 callers_pc
= FRAME_SAVED_PC (fi
); /* find out who called us: */
947 fp
= arm_find_callers_reg (fi
, FP_REGNUM
);
948 if (PC_IN_CALL_DUMMY (callers_pc
, fp
, fp
))
949 return fp
; /* dummy frame's frame may bear no relation to ours */
951 if (find_pc_partial_function (fi
->pc
, 0, &fn_start
, 0))
952 if (fn_start
== entry_point_address ())
953 return 0; /* in _start fn, don't chain further */
955 CORE_ADDR caller_pc
, fn_start
;
956 struct frame_info caller_fi
;
957 int framereg
= fi
->framereg
;
959 if (fi
->pc
< LOWEST_PC
)
962 /* If the caller is the startup code, we're at the end of the chain. */
963 caller_pc
= FRAME_SAVED_PC (fi
);
964 if (find_pc_partial_function (caller_pc
, 0, &fn_start
, 0))
965 if (fn_start
== entry_point_address ())
968 /* If the caller is Thumb and the caller is ARM, or vice versa,
969 the frame register of the caller is different from ours.
970 So we must scan the prologue of the caller to determine its
971 frame register number. */
972 if (arm_pc_is_thumb (caller_pc
) != arm_pc_is_thumb (fi
->pc
))
974 memset (&caller_fi
, 0, sizeof (caller_fi
));
975 caller_fi
.pc
= caller_pc
;
976 arm_scan_prologue (&caller_fi
);
977 framereg
= caller_fi
.framereg
;
980 /* If the caller used a frame register, return its value.
981 Otherwise, return the caller's stack pointer. */
982 if (framereg
== FP_REGNUM
|| framereg
== THUMB_FP_REGNUM
)
983 return arm_find_callers_reg (fi
, framereg
);
985 return fi
->frame
+ fi
->framesize
;
988 /* This function actually figures out the frame address for a given pc
989 and sp. This is tricky because we sometimes don't use an explicit
990 frame pointer, and the previous stack pointer isn't necessarily
991 recorded on the stack. The only reliable way to get this info is
992 to examine the prologue. FROMLEAF is a little confusing, it means
993 this is the next frame up the chain AFTER a frameless function. If
994 this is true, then the frame value for this frame is still in the
998 arm_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1003 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1005 memset (fi
->fsr
.regs
, '\000', sizeof fi
->fsr
.regs
);
1007 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1008 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1010 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1011 by assuming it's always FP. */
1012 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
, SP_REGNUM
);
1014 fi
->frameoffset
= 0;
1020 /* Determine whether or not we're in a sigtramp frame.
1021 Unfortunately, it isn't sufficient to test
1022 fi->signal_handler_caller because this value is sometimes set
1023 after invoking INIT_EXTRA_FRAME_INFO. So we test *both*
1024 fi->signal_handler_caller and IN_SIGTRAMP to determine if we need
1025 to use the sigcontext addresses for the saved registers.
1027 Note: If an ARM IN_SIGTRAMP method ever needs to compare against
1028 the name of the function, the code below will have to be changed
1029 to first fetch the name of the function and then pass this name
1032 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1033 && (fi
->signal_handler_caller
|| IN_SIGTRAMP (fi
->pc
, 0)))
1040 sp
= fi
->next
->frame
- fi
->next
->frameoffset
+ fi
->next
->framesize
;
1042 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1043 fi
->fsr
.regs
[reg
] = SIGCONTEXT_REGISTER_ADDRESS (sp
, fi
->pc
, reg
);
1045 /* FIXME: What about thumb mode? */
1046 fi
->framereg
= SP_REGNUM
;
1047 fi
->frame
= read_memory_integer (fi
->fsr
.regs
[fi
->framereg
], 4);
1049 fi
->frameoffset
= 0;
1054 arm_scan_prologue (fi
);
1057 /* this is the innermost frame? */
1058 fi
->frame
= read_register (fi
->framereg
);
1059 else if (fi
->framereg
== FP_REGNUM
|| fi
->framereg
== THUMB_FP_REGNUM
)
1061 /* not the innermost frame */
1062 /* If we have an FP, the callee saved it. */
1063 if (fi
->next
->fsr
.regs
[fi
->framereg
] != 0)
1065 read_memory_integer (fi
->next
->fsr
.regs
[fi
->framereg
], 4);
1067 /* If we were called by a frameless fn. then our frame is
1068 still in the frame pointer register on the board... */
1069 fi
->frame
= read_fp ();
1072 /* Calculate actual addresses of saved registers using offsets
1073 determined by arm_scan_prologue. */
1074 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1075 if (fi
->fsr
.regs
[reg
] != 0)
1076 fi
->fsr
.regs
[reg
] += fi
->frame
+ fi
->framesize
- fi
->frameoffset
;
1081 /* Find the caller of this frame. We do this by seeing if LR_REGNUM
1082 is saved in the stack anywhere, otherwise we get it from the
1085 The old definition of this function was a macro:
1086 #define FRAME_SAVED_PC(FRAME) \
1087 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1090 arm_frame_saved_pc (struct frame_info
*fi
)
1092 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1093 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1094 return generic_read_register_dummy (fi
->pc
, fi
->frame
, PC_REGNUM
);
1098 CORE_ADDR pc
= arm_find_callers_reg (fi
, LR_REGNUM
);
1099 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1103 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1104 Examine the Program Status Register to decide which state we're in. */
1107 arm_target_read_fp (void)
1109 if (read_register (PS_REGNUM
) & 0x20) /* Bit 5 is Thumb state bit */
1110 return read_register (THUMB_FP_REGNUM
); /* R7 if Thumb */
1112 return read_register (FP_REGNUM
); /* R11 if ARM */
1115 /* Calculate the frame offsets of the saved registers (ARM version). */
1118 arm_frame_find_saved_regs (struct frame_info
*fi
,
1119 struct frame_saved_regs
*regaddr
)
1121 memcpy (regaddr
, &fi
->fsr
, sizeof (struct frame_saved_regs
));
1125 arm_push_dummy_frame (void)
1127 CORE_ADDR old_sp
= read_register (SP_REGNUM
);
1128 CORE_ADDR sp
= old_sp
;
1129 CORE_ADDR fp
, prologue_start
;
1132 /* Push the two dummy prologue instructions in reverse order,
1133 so that they'll be in the correct low-to-high order in memory. */
1134 /* sub fp, ip, #4 */
1135 sp
= push_word (sp
, 0xe24cb004);
1136 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1137 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
1139 /* Push a pointer to the dummy prologue + 12, because when stm
1140 instruction stores the PC, it stores the address of the stm
1141 instruction itself plus 12. */
1142 fp
= sp
= push_word (sp
, prologue_start
+ 12);
1143 sp
= push_word (sp
, read_register (PC_REGNUM
)); /* FIXME: was PS_REGNUM */
1144 sp
= push_word (sp
, old_sp
);
1145 sp
= push_word (sp
, read_register (FP_REGNUM
));
1147 for (regnum
= 10; regnum
>= 0; regnum
--)
1148 sp
= push_word (sp
, read_register (regnum
));
1150 write_register (FP_REGNUM
, fp
);
1151 write_register (THUMB_FP_REGNUM
, fp
);
1152 write_register (SP_REGNUM
, sp
);
1155 /* Fix up the call dummy, based on whether the processor is currently
1156 in Thumb or ARM mode, and whether the target function is Thumb or
1157 ARM. There are three different situations requiring three
1160 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1161 been copied into the dummy parameter to this function.
1162 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1163 "mov pc,r4" instruction patched to be a "bx r4" instead.
1164 * Thumb calling anything: uses the Thumb dummy defined below, which
1165 works for calling both ARM and Thumb functions.
1167 All three call dummies expect to receive the target function
1168 address in R4, with the low bit set if it's a Thumb function. */
1171 arm_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
1172 struct value
**args
, struct type
*type
, int gcc_p
)
1174 static short thumb_dummy
[4] =
1176 0xf000, 0xf801, /* bl label */
1177 0xdf18, /* swi 24 */
1178 0x4720, /* label: bx r4 */
1180 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
1182 /* Set flag indicating whether the current PC is in a Thumb function. */
1183 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
1185 /* If the target function is Thumb, set the low bit of the function
1186 address. And if the CPU is currently in ARM mode, patch the
1187 second instruction of call dummy to use a BX instruction to
1188 switch to Thumb mode. */
1189 target_is_thumb
= arm_pc_is_thumb (fun
);
1190 if (target_is_thumb
)
1193 if (!caller_is_thumb
)
1194 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
1197 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1198 instead of the ARM one that's already been copied. This will
1199 work for both Thumb and ARM target functions. */
1200 if (caller_is_thumb
)
1204 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
1206 for (i
= 0; i
< len
; i
++)
1208 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1209 p
+= sizeof (thumb_dummy
[0]);
1213 /* Put the target address in r4; the call dummy will copy this to
1215 write_register (4, fun
);
1218 /* Return the offset in the call dummy of the instruction that needs
1219 to have a breakpoint placed on it. This is the offset of the 'swi
1220 24' instruction, which is no longer actually used, but simply acts
1221 as a place-holder now.
1223 This implements the CALL_DUMMY_BREAK_OFFSET macro. */
1226 arm_call_dummy_breakpoint_offset (void)
1228 if (caller_is_thumb
)
1236 This function does not support passing parameters using the FPA
1237 variant of the APCS. It passes any floating point arguments in the
1238 general registers and/or on the stack. */
1241 arm_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
1242 int struct_return
, CORE_ADDR struct_addr
)
1245 int argnum
, argreg
, nstack_size
;
1247 /* Walk through the list of args and determine how large a temporary
1248 stack is required. Need to take care here as structs may be
1249 passed on the stack, and we have to to push them. */
1250 nstack_size
= -4 * REGISTER_SIZE
; /* Some arguments go into A1-A4. */
1251 if (struct_return
) /* The struct address goes in A1. */
1252 nstack_size
+= REGISTER_SIZE
;
1254 /* Walk through the arguments and add their size to nstack_size. */
1255 for (argnum
= 0; argnum
< nargs
; argnum
++)
1258 struct type
*arg_type
;
1260 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1261 len
= TYPE_LENGTH (arg_type
);
1263 /* ANSI C code passes float arguments as integers, K&R code
1264 passes float arguments as doubles. Correct for this here. */
1265 if (TYPE_CODE_FLT
== TYPE_CODE (arg_type
) && REGISTER_SIZE
== len
)
1266 nstack_size
+= FP_REGISTER_VIRTUAL_SIZE
;
1271 /* Allocate room on the stack, and initialize our stack frame
1274 if (nstack_size
> 0)
1280 /* Initialize the integer argument register pointer. */
1283 /* The struct_return pointer occupies the first parameter passing
1286 write_register (argreg
++, struct_addr
);
1288 /* Process arguments from left to right. Store as many as allowed
1289 in the parameter passing registers (A1-A4), and save the rest on
1290 the temporary stack. */
1291 for (argnum
= 0; argnum
< nargs
; argnum
++)
1296 enum type_code typecode
;
1297 struct type
*arg_type
, *target_type
;
1299 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1300 target_type
= TYPE_TARGET_TYPE (arg_type
);
1301 len
= TYPE_LENGTH (arg_type
);
1302 typecode
= TYPE_CODE (arg_type
);
1303 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
1305 /* ANSI C code passes float arguments as integers, K&R code
1306 passes float arguments as doubles. The .stabs record for
1307 for ANSI prototype floating point arguments records the
1308 type as FP_INTEGER, while a K&R style (no prototype)
1309 .stabs records the type as FP_FLOAT. In this latter case
1310 the compiler converts the float arguments to double before
1311 calling the function. */
1312 if (TYPE_CODE_FLT
== typecode
&& REGISTER_SIZE
== len
)
1315 dblval
= extract_floating (val
, len
);
1316 len
= TARGET_DOUBLE_BIT
/ TARGET_CHAR_BIT
;
1318 store_floating (val
, len
, dblval
);
1321 /* I don't know why this code was disable. The only logical use
1322 for a function pointer is to call that function, so setting
1323 the mode bit is perfectly fine. FN */
1324 /* If the argument is a pointer to a function, and it is a Thumb
1325 function, set the low bit of the pointer. */
1326 if (TYPE_CODE_PTR
== typecode
1327 && NULL
!= target_type
1328 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1330 CORE_ADDR regval
= extract_address (val
, len
);
1331 if (arm_pc_is_thumb (regval
))
1332 store_address (val
, len
, MAKE_THUMB_ADDR (regval
));
1335 /* Copy the argument to general registers or the stack in
1336 register-sized pieces. Large arguments are split between
1337 registers and stack. */
1340 int partial_len
= len
< REGISTER_SIZE
? len
: REGISTER_SIZE
;
1342 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1344 /* It's an argument being passed in a general register. */
1345 regval
= extract_address (val
, partial_len
);
1346 write_register (argreg
++, regval
);
1350 /* Push the arguments onto the stack. */
1351 write_memory ((CORE_ADDR
) fp
, val
, REGISTER_SIZE
);
1352 fp
+= REGISTER_SIZE
;
1360 /* Return adjusted stack pointer. */
1365 arm_pop_frame (void)
1368 struct frame_info
*frame
= get_current_frame ();
1370 if (!PC_IN_CALL_DUMMY(frame
->pc
, frame
->frame
, read_fp()))
1374 old_SP
= read_register (frame
->framereg
);
1375 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1376 if (frame
->fsr
.regs
[regnum
] != 0)
1377 write_register (regnum
,
1378 read_memory_integer (frame
->fsr
.regs
[regnum
], 4));
1380 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
1381 write_register (SP_REGNUM
, old_SP
);
1387 sp
= read_register (FP_REGNUM
);
1388 sp
-= sizeof(CORE_ADDR
); /* we don't care about this first word */
1390 write_register (PC_REGNUM
, read_memory_integer (sp
, 4));
1391 sp
-= sizeof(CORE_ADDR
);
1392 write_register (SP_REGNUM
, read_memory_integer (sp
, 4));
1393 sp
-= sizeof(CORE_ADDR
);
1394 write_register (FP_REGNUM
, read_memory_integer (sp
, 4));
1395 sp
-= sizeof(CORE_ADDR
);
1397 for (regnum
= 10; regnum
>= 0; regnum
--)
1399 write_register (regnum
, read_memory_integer (sp
, 4));
1400 sp
-= sizeof(CORE_ADDR
);
1404 flush_cached_frames ();
1408 print_fpu_flags (int flags
)
1410 if (flags
& (1 << 0))
1411 fputs ("IVO ", stdout
);
1412 if (flags
& (1 << 1))
1413 fputs ("DVZ ", stdout
);
1414 if (flags
& (1 << 2))
1415 fputs ("OFL ", stdout
);
1416 if (flags
& (1 << 3))
1417 fputs ("UFL ", stdout
);
1418 if (flags
& (1 << 4))
1419 fputs ("INX ", stdout
);
1424 arm_float_info (void)
1426 register unsigned long status
= read_register (FPS_REGNUM
);
1429 type
= (status
>> 24) & 127;
1430 printf ("%s FPU type %d\n",
1431 (status
& (1 << 31)) ? "Hardware" : "Software",
1433 fputs ("mask: ", stdout
);
1434 print_fpu_flags (status
>> 16);
1435 fputs ("flags: ", stdout
);
1436 print_fpu_flags (status
);
1439 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1440 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1441 It is thought that this is is the floating-point register format on
1442 little-endian systems. */
1445 convert_from_extended (void *ptr
, void *dbl
)
1448 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1449 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1451 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1453 floatformat_from_doublest (TARGET_DOUBLE_FORMAT
, &d
, dbl
);
1457 convert_to_extended (void *dbl
, void *ptr
)
1460 floatformat_to_doublest (TARGET_DOUBLE_FORMAT
, ptr
, &d
);
1461 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1462 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1464 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1468 /* Nonzero if register N requires conversion from raw format to
1472 arm_register_convertible (unsigned int regnum
)
1474 return ((regnum
- F0_REGNUM
) < 8);
1477 /* Convert data from raw format for register REGNUM in buffer FROM to
1478 virtual format with type TYPE in buffer TO. */
1481 arm_register_convert_to_virtual (unsigned int regnum
, struct type
*type
,
1482 void *from
, void *to
)
1486 convert_from_extended (from
, &val
);
1487 store_floating (to
, TYPE_LENGTH (type
), val
);
1490 /* Convert data from virtual format with type TYPE in buffer FROM to
1491 raw format for register REGNUM in buffer TO. */
1494 arm_register_convert_to_raw (unsigned int regnum
, struct type
*type
,
1495 void *from
, void *to
)
1497 double val
= extract_floating (from
, TYPE_LENGTH (type
));
1499 convert_to_extended (&val
, to
);
1503 condition_true (unsigned long cond
, unsigned long status_reg
)
1505 if (cond
== INST_AL
|| cond
== INST_NV
)
1511 return ((status_reg
& FLAG_Z
) != 0);
1513 return ((status_reg
& FLAG_Z
) == 0);
1515 return ((status_reg
& FLAG_C
) != 0);
1517 return ((status_reg
& FLAG_C
) == 0);
1519 return ((status_reg
& FLAG_N
) != 0);
1521 return ((status_reg
& FLAG_N
) == 0);
1523 return ((status_reg
& FLAG_V
) != 0);
1525 return ((status_reg
& FLAG_V
) == 0);
1527 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1529 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1531 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1533 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1535 return (((status_reg
& FLAG_Z
) == 0) &&
1536 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1538 return (((status_reg
& FLAG_Z
) != 0) ||
1539 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1544 #define submask(x) ((1L << ((x) + 1)) - 1)
1545 #define bit(obj,st) (((obj) >> (st)) & 1)
1546 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1547 #define sbits(obj,st,fn) \
1548 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1549 #define BranchDest(addr,instr) \
1550 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1553 static unsigned long
1554 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1555 unsigned long status_reg
)
1557 unsigned long res
, shift
;
1558 int rm
= bits (inst
, 0, 3);
1559 unsigned long shifttype
= bits (inst
, 5, 6);
1563 int rs
= bits (inst
, 8, 11);
1564 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1567 shift
= bits (inst
, 7, 11);
1570 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1571 + (bit (inst
, 4) ? 12 : 8))
1572 : read_register (rm
));
1577 res
= shift
>= 32 ? 0 : res
<< shift
;
1581 res
= shift
>= 32 ? 0 : res
>> shift
;
1587 res
= ((res
& 0x80000000L
)
1588 ? ~((~res
) >> shift
) : res
>> shift
);
1591 case 3: /* ROR/RRX */
1594 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1596 res
= (res
>> shift
) | (res
<< (32 - shift
));
1600 return res
& 0xffffffff;
1603 /* Return number of 1-bits in VAL. */
1606 bitcount (unsigned long val
)
1609 for (nbits
= 0; val
!= 0; nbits
++)
1610 val
&= val
- 1; /* delete rightmost 1-bit in val */
1615 thumb_get_next_pc (CORE_ADDR pc
)
1617 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1618 unsigned short inst1
= read_memory_integer (pc
, 2);
1619 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1620 unsigned long offset
;
1622 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1626 /* Fetch the saved PC from the stack. It's stored above
1627 all of the other registers. */
1628 offset
= bitcount (bits (inst1
, 0, 7)) * REGISTER_SIZE
;
1629 sp
= read_register (SP_REGNUM
);
1630 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1631 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1633 error ("Infinite loop detected");
1635 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1637 unsigned long status
= read_register (PS_REGNUM
);
1638 unsigned long cond
= bits (inst1
, 8, 11);
1639 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1640 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1642 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1644 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1646 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1648 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1649 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1650 nextpc
= pc_val
+ offset
;
1657 arm_get_next_pc (CORE_ADDR pc
)
1659 unsigned long pc_val
;
1660 unsigned long this_instr
;
1661 unsigned long status
;
1664 if (arm_pc_is_thumb (pc
))
1665 return thumb_get_next_pc (pc
);
1667 pc_val
= (unsigned long) pc
;
1668 this_instr
= read_memory_integer (pc
, 4);
1669 status
= read_register (PS_REGNUM
);
1670 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1672 if (condition_true (bits (this_instr
, 28, 31), status
))
1674 switch (bits (this_instr
, 24, 27))
1677 case 0x1: /* data processing */
1681 unsigned long operand1
, operand2
, result
= 0;
1685 if (bits (this_instr
, 12, 15) != 15)
1688 if (bits (this_instr
, 22, 25) == 0
1689 && bits (this_instr
, 4, 7) == 9) /* multiply */
1690 error ("Illegal update to pc in instruction");
1692 /* Multiply into PC */
1693 c
= (status
& FLAG_C
) ? 1 : 0;
1694 rn
= bits (this_instr
, 16, 19);
1695 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1697 if (bit (this_instr
, 25))
1699 unsigned long immval
= bits (this_instr
, 0, 7);
1700 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1701 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1704 else /* operand 2 is a shifted register */
1705 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1707 switch (bits (this_instr
, 21, 24))
1710 result
= operand1
& operand2
;
1714 result
= operand1
^ operand2
;
1718 result
= operand1
- operand2
;
1722 result
= operand2
- operand1
;
1726 result
= operand1
+ operand2
;
1730 result
= operand1
+ operand2
+ c
;
1734 result
= operand1
- operand2
+ c
;
1738 result
= operand2
- operand1
+ c
;
1744 case 0xb: /* tst, teq, cmp, cmn */
1745 result
= (unsigned long) nextpc
;
1749 result
= operand1
| operand2
;
1753 /* Always step into a function. */
1758 result
= operand1
& ~operand2
;
1765 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1768 error ("Infinite loop detected");
1773 case 0x5: /* data transfer */
1776 if (bit (this_instr
, 20))
1779 if (bits (this_instr
, 12, 15) == 15)
1785 if (bit (this_instr
, 22))
1786 error ("Illegal update to pc in instruction");
1788 /* byte write to PC */
1789 rn
= bits (this_instr
, 16, 19);
1790 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1791 if (bit (this_instr
, 24))
1794 int c
= (status
& FLAG_C
) ? 1 : 0;
1795 unsigned long offset
=
1796 (bit (this_instr
, 25)
1797 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1798 : bits (this_instr
, 0, 11));
1800 if (bit (this_instr
, 23))
1805 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1808 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1811 error ("Infinite loop detected");
1817 case 0x9: /* block transfer */
1818 if (bit (this_instr
, 20))
1821 if (bit (this_instr
, 15))
1826 if (bit (this_instr
, 23))
1829 unsigned long reglist
= bits (this_instr
, 0, 14);
1830 offset
= bitcount (reglist
) * 4;
1831 if (bit (this_instr
, 24)) /* pre */
1834 else if (bit (this_instr
, 24))
1838 unsigned long rn_val
=
1839 read_register (bits (this_instr
, 16, 19));
1841 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1845 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1847 error ("Infinite loop detected");
1852 case 0xb: /* branch & link */
1853 case 0xa: /* branch */
1855 nextpc
= BranchDest (pc
, this_instr
);
1857 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1859 error ("Infinite loop detected");
1865 case 0xe: /* coproc ops */
1870 fprintf (stderr
, "Bad bit-field extraction\n");
1878 #include "bfd-in2.h"
1879 #include "libcoff.h"
1882 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
1884 if (arm_pc_is_thumb (memaddr
))
1886 static asymbol
*asym
;
1887 static combined_entry_type ce
;
1888 static struct coff_symbol_struct csym
;
1889 static struct _bfd fake_bfd
;
1890 static bfd_target fake_target
;
1892 if (csym
.native
== NULL
)
1894 /* Create a fake symbol vector containing a Thumb symbol. This is
1895 solely so that the code in print_insn_little_arm() and
1896 print_insn_big_arm() in opcodes/arm-dis.c will detect the presence
1897 of a Thumb symbol and switch to decoding Thumb instructions. */
1899 fake_target
.flavour
= bfd_target_coff_flavour
;
1900 fake_bfd
.xvec
= &fake_target
;
1901 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
1903 csym
.symbol
.the_bfd
= &fake_bfd
;
1904 csym
.symbol
.name
= "fake";
1905 asym
= (asymbol
*) & csym
;
1908 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
1909 info
->symbols
= &asym
;
1912 info
->symbols
= NULL
;
1914 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1915 return print_insn_big_arm (memaddr
, info
);
1917 return print_insn_little_arm (memaddr
, info
);
1920 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the
1921 program counter value to determine whether a 16-bit or 32-bit
1922 breakpoint should be used. It returns a pointer to a string of
1923 bytes that encode a breakpoint instruction, stores the length of
1924 the string to *lenptr, and adjusts the program counter (if
1925 necessary) to point to the actual memory location where the
1926 breakpoint should be inserted. */
1929 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1931 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
1933 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1935 static char thumb_breakpoint
[] = THUMB_BE_BREAKPOINT
;
1936 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1937 *lenptr
= sizeof (thumb_breakpoint
);
1938 return thumb_breakpoint
;
1942 static char thumb_breakpoint
[] = THUMB_LE_BREAKPOINT
;
1943 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1944 *lenptr
= sizeof (thumb_breakpoint
);
1945 return thumb_breakpoint
;
1950 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1952 static char arm_breakpoint
[] = ARM_BE_BREAKPOINT
;
1953 *lenptr
= sizeof (arm_breakpoint
);
1954 return arm_breakpoint
;
1958 static char arm_breakpoint
[] = ARM_LE_BREAKPOINT
;
1959 *lenptr
= sizeof (arm_breakpoint
);
1960 return arm_breakpoint
;
1965 /* Extract from an array REGBUF containing the (raw) register state a
1966 function return value of type TYPE, and copy that, in virtual
1967 format, into VALBUF. */
1970 arm_extract_return_value (struct type
*type
,
1971 char regbuf
[REGISTER_BYTES
],
1974 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
1975 convert_from_extended (®buf
[REGISTER_BYTE (F0_REGNUM
)], valbuf
);
1977 memcpy (valbuf
, ®buf
[REGISTER_BYTE (A1_REGNUM
)], TYPE_LENGTH (type
));
1980 /* Return non-zero if the PC is inside a thumb call thunk. */
1983 arm_in_call_stub (CORE_ADDR pc
, char *name
)
1985 CORE_ADDR start_addr
;
1987 /* Find the starting address of the function containing the PC. If
1988 the caller didn't give us a name, look it up at the same time. */
1989 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
1992 return strncmp (name
, "_call_via_r", 11) == 0;
1995 /* If PC is in a Thumb call or return stub, return the address of the
1996 target PC, which is in a register. The thunk functions are called
1997 _called_via_xx, where x is the register name. The possible names
1998 are r0-r9, sl, fp, ip, sp, and lr. */
2001 arm_skip_stub (CORE_ADDR pc
)
2004 CORE_ADDR start_addr
;
2006 /* Find the starting address and name of the function containing the PC. */
2007 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2010 /* Call thunks always start with "_call_via_". */
2011 if (strncmp (name
, "_call_via_", 10) == 0)
2013 /* Use the name suffix to determine which register contains the
2015 static char *table
[15] =
2016 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2017 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2021 for (regno
= 0; regno
<= 14; regno
++)
2022 if (strcmp (&name
[10], table
[regno
]) == 0)
2023 return read_register (regno
);
2026 return 0; /* not a stub */
2029 /* If the user changes the register disassembly flavor used for info register
2030 and other commands, we have to also switch the flavor used in opcodes
2031 for disassembly output.
2032 This function is run in the set disassembly_flavor command, and does that. */
2035 set_disassembly_flavor_sfunc (char *args
, int from_tty
,
2036 struct cmd_list_element
*c
)
2038 set_disassembly_flavor ();
2042 set_disassembly_flavor (void)
2044 const char *setname
, *setdesc
, **regnames
;
2047 /* Find the flavor that the user wants in the opcodes table. */
2049 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2050 while ((disassembly_flavor
!= setname
)
2051 && (current
< num_flavor_options
))
2052 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2053 current_option
= current
;
2055 /* Fill our copy. */
2056 for (j
= 0; j
< numregs
; j
++)
2057 arm_register_names
[j
] = (char *) regnames
[j
];
2060 if (isupper (*regnames
[PC_REGNUM
]))
2062 arm_register_names
[FPS_REGNUM
] = "FPS";
2063 arm_register_names
[PS_REGNUM
] = "CPSR";
2067 arm_register_names
[FPS_REGNUM
] = "fps";
2068 arm_register_names
[PS_REGNUM
] = "cpsr";
2071 /* Synchronize the disassembler. */
2072 set_arm_regname_option (current
);
2075 /* arm_othernames implements the "othernames" command. This is kind
2076 of hacky, and I prefer the set-show disassembly-flavor which is
2077 also used for the x86 gdb. I will keep this around, however, in
2078 case anyone is actually using it. */
2081 arm_othernames (char *names
, int n
)
2083 /* Circle through the various flavors. */
2084 current_option
= (current_option
+ 1) % num_flavor_options
;
2086 disassembly_flavor
= valid_flavors
[current_option
];
2087 set_disassembly_flavor ();
2091 _initialize_arm_tdep (void)
2093 struct ui_file
*stb
;
2095 struct cmd_list_element
*new_cmd
;
2096 const char *setname
;
2097 const char *setdesc
;
2098 const char **regnames
;
2100 static char *helptext
;
2102 tm_print_insn
= gdb_print_insn_arm
;
2104 /* Get the number of possible sets of register names defined in opcodes. */
2105 num_flavor_options
= get_arm_regname_num_options ();
2107 /* Sync the opcode insn printer with our register viewer: */
2108 parse_arm_disassembler_option ("reg-names-std");
2110 /* Begin creating the help text. */
2111 stb
= mem_fileopen ();
2112 fprintf_unfiltered (stb
, "Set the disassembly flavor.\n\
2113 The valid values are:\n");
2115 /* Initialize the array that will be passed to add_set_enum_cmd(). */
2116 valid_flavors
= xmalloc ((num_flavor_options
+ 1) * sizeof (char *));
2117 for (i
= 0; i
< num_flavor_options
; i
++)
2119 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
2120 valid_flavors
[i
] = setname
;
2121 fprintf_unfiltered (stb
, "%s - %s\n", setname
,
2123 /* Copy the default names (if found) and synchronize disassembler. */
2124 if (!strcmp (setname
, "std"))
2126 disassembly_flavor
= setname
;
2128 for (j
= 0; j
< numregs
; j
++)
2129 arm_register_names
[j
] = (char *) regnames
[j
];
2130 set_arm_regname_option (i
);
2133 /* Mark the end of valid options. */
2134 valid_flavors
[num_flavor_options
] = NULL
;
2136 /* Finish the creation of the help text. */
2137 fprintf_unfiltered (stb
, "The default is \"std\".");
2138 helptext
= ui_file_xstrdup (stb
, &length
);
2139 ui_file_delete (stb
);
2141 /* Add the disassembly-flavor command */
2142 new_cmd
= add_set_enum_cmd ("disassembly-flavor", no_class
,
2144 &disassembly_flavor
,
2147 new_cmd
->function
.sfunc
= set_disassembly_flavor_sfunc
;
2148 add_show_from_set (new_cmd
, &showlist
);
2150 /* ??? Maybe this should be a boolean. */
2151 add_show_from_set (add_set_cmd ("apcs32", no_class
,
2152 var_zinteger
, (char *) &arm_apcs_32
,
2153 "Set usage of ARM 32-bit mode.\n", &setlist
),
2156 /* Add the deprecated "othernames" command */
2158 add_com ("othernames", class_obscure
, arm_othernames
,
2159 "Switch to the next set of register names.");
2162 /* Test whether the coff symbol specific value corresponds to a Thumb
2166 coff_sym_is_thumb (int val
)
2168 return (val
== C_THUMBEXT
||
2169 val
== C_THUMBSTAT
||
2170 val
== C_THUMBEXTFUNC
||
2171 val
== C_THUMBSTATFUNC
||
2172 val
== C_THUMBLABEL
);