1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
23 #include <ctype.h> /* XXX for isupper () */
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register styles. */
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
41 #include "dwarf2-frame.h"
43 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
48 #include "gdb/sim-arm.h"
51 #include "coff/internal.h"
54 #include "gdb_assert.h"
58 /* Macros for setting and testing a bit in a minimal symbol that marks
59 it as Thumb function. The MSB of the minimal symbol's "info" field
60 is used for this purpose.
62 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
63 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
65 #define MSYMBOL_SET_SPECIAL(msym) \
66 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
69 #define MSYMBOL_IS_SPECIAL(msym) \
70 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
72 /* The list of available "set arm ..." and "show arm ..." commands. */
73 static struct cmd_list_element
*setarmcmdlist
= NULL
;
74 static struct cmd_list_element
*showarmcmdlist
= NULL
;
76 /* The type of floating-point to use. Keep this in sync with enum
77 arm_float_model, and the help string in _initialize_arm_tdep. */
78 static const char *fp_model_strings
[] =
88 /* A variable that can be configured by the user. */
89 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
90 static const char *current_fp_model
= "auto";
92 /* The ABI to use. Keep this in sync with arm_abi_kind. */
93 static const char *arm_abi_strings
[] =
101 /* A variable that can be configured by the user. */
102 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
103 static const char *arm_abi_string
= "auto";
105 /* Number of different reg name sets (options). */
106 static int num_disassembly_options
;
108 /* The standard register names, and all the valid aliases for them. */
113 } arm_register_aliases
[] = {
114 /* Basic register numbers. */
131 /* Synonyms (argument and variable registers). */
144 /* Other platform-specific names for r9. */
152 /* Names used by GCC (not listed in the ARM EABI). */
155 /* A special name from the older ATPCS. */
159 static const char *const arm_register_names
[] =
160 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
161 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
162 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
163 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
164 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
165 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
166 "fps", "cpsr" }; /* 24 25 */
168 /* Valid register name styles. */
169 static const char **valid_disassembly_styles
;
171 /* Disassembly style to use. Default to "std" register names. */
172 static const char *disassembly_style
;
174 /* This is used to keep the bfd arch_info in sync with the disassembly
176 static void set_disassembly_style_sfunc(char *, int,
177 struct cmd_list_element
*);
178 static void set_disassembly_style (void);
180 static void convert_from_extended (const struct floatformat
*, const void *,
182 static void convert_to_extended (const struct floatformat
*, void *,
185 struct arm_prologue_cache
187 /* The stack pointer at the time this frame was created; i.e. the
188 caller's stack pointer when this function was called. It is used
189 to identify this frame. */
192 /* The frame base for this frame is just prev_sp + frame offset -
193 frame size. FRAMESIZE is the size of this stack frame, and
194 FRAMEOFFSET if the initial offset from the stack pointer (this
195 frame's stack pointer, not PREV_SP) to the frame base. */
200 /* The register used to hold the frame pointer for this frame. */
203 /* Saved register offsets. */
204 struct trad_frame_saved_reg
*saved_regs
;
207 /* Addresses for calling Thumb functions have the bit 0 set.
208 Here are some macros to test, set, or clear bit 0 of addresses. */
209 #define IS_THUMB_ADDR(addr) ((addr) & 1)
210 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
211 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
213 /* Set to true if the 32-bit mode is in use. */
217 /* Determine if the program counter specified in MEMADDR is in a Thumb
221 arm_pc_is_thumb (CORE_ADDR memaddr
)
223 struct minimal_symbol
*sym
;
225 /* If bit 0 of the address is set, assume this is a Thumb address. */
226 if (IS_THUMB_ADDR (memaddr
))
229 /* Thumb functions have a "special" bit set in minimal symbols. */
230 sym
= lookup_minimal_symbol_by_pc (memaddr
);
233 return (MSYMBOL_IS_SPECIAL (sym
));
241 /* Remove useless bits from addresses in a running program. */
243 arm_addr_bits_remove (CORE_ADDR val
)
246 return (val
& (arm_pc_is_thumb (val
) ? 0xfffffffe : 0xfffffffc));
248 return (val
& 0x03fffffc);
251 /* When reading symbols, we need to zap the low bit of the address,
252 which may be set to 1 for Thumb functions. */
254 arm_smash_text_address (CORE_ADDR val
)
259 /* Analyze a Thumb prologue, looking for a recognizable stack frame
260 and frame pointer. Scan until we encounter a store that could
261 clobber the stack frame unexpectedly, or an unknown instruction. */
264 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
265 CORE_ADDR start
, CORE_ADDR limit
,
266 struct arm_prologue_cache
*cache
)
270 struct pv_area
*stack
;
271 struct cleanup
*back_to
;
274 for (i
= 0; i
< 16; i
++)
275 regs
[i
] = pv_register (i
, 0);
276 stack
= make_pv_area (ARM_SP_REGNUM
);
277 back_to
= make_cleanup_free_pv_area (stack
);
279 /* The call instruction saved PC in LR, and the current PC is not
280 interesting. Due to this file's conventions, we want the value
281 of LR at this function's entry, not at the call site, so we do
282 not record the save of the PC - when the ARM prologue analyzer
283 has also been converted to the pv mechanism, we could record the
284 save here and remove the hack in prev_register. */
285 regs
[ARM_PC_REGNUM
] = pv_unknown ();
287 while (start
< limit
)
291 insn
= read_memory_unsigned_integer (start
, 2);
293 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
299 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
300 whether to save LR (R14). */
301 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
303 /* Calculate offsets of saved R0-R7 and LR. */
304 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
305 if (mask
& (1 << regno
))
307 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
313 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
315 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
321 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
324 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
325 if (insn
& 0x80) /* Check for SUB. */
326 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
329 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
332 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
333 regs
[THUMB_FP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
335 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
337 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
338 int src_reg
= (insn
& 0x78) >> 3;
339 regs
[dst_reg
] = regs
[src_reg
];
341 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
343 /* Handle stores to the stack. Normally pushes are used,
344 but with GCC -mtpcs-frame, there may be other stores
345 in the prologue to create the frame. */
346 int regno
= (insn
>> 8) & 0x7;
349 offset
= (insn
& 0xff) << 2;
350 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
352 if (pv_area_store_would_trash (stack
, addr
))
355 pv_area_store (stack
, addr
, 4, regs
[regno
]);
359 /* We don't know what this instruction is. We're finished
360 scanning. NOTE: Recognizing more safe-to-ignore
361 instructions here will improve support for optimized
371 do_cleanups (back_to
);
375 /* frameoffset is unused for this unwinder. */
376 cache
->frameoffset
= 0;
378 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
380 /* Frame pointer is fp. Frame size is constant. */
381 cache
->framereg
= ARM_FP_REGNUM
;
382 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
384 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
386 /* Frame pointer is r7. Frame size is constant. */
387 cache
->framereg
= THUMB_FP_REGNUM
;
388 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
390 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
392 /* Try the stack pointer... this is a bit desperate. */
393 cache
->framereg
= ARM_SP_REGNUM
;
394 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
398 /* We're just out of luck. We don't know where the frame is. */
399 cache
->framereg
= -1;
400 cache
->framesize
= 0;
403 for (i
= 0; i
< 16; i
++)
404 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
405 cache
->saved_regs
[i
].addr
= offset
;
407 do_cleanups (back_to
);
411 /* Advance the PC across any function entry prologue instructions to
412 reach some "real" code.
414 The APCS (ARM Procedure Call Standard) defines the following
418 [stmfd sp!, {a1,a2,a3,a4}]
419 stmfd sp!, {...,fp,ip,lr,pc}
420 [stfe f7, [sp, #-12]!]
421 [stfe f6, [sp, #-12]!]
422 [stfe f5, [sp, #-12]!]
423 [stfe f4, [sp, #-12]!]
424 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
427 arm_skip_prologue (CORE_ADDR pc
)
431 CORE_ADDR func_addr
, func_end
= 0;
433 struct symtab_and_line sal
;
435 /* If we're in a dummy frame, don't even try to skip the prologue. */
436 if (deprecated_pc_in_call_dummy (pc
))
439 /* See what the symbol table says. */
441 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
445 /* Found a function. */
446 sym
= lookup_symbol (func_name
, NULL
, VAR_DOMAIN
, NULL
, NULL
);
447 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
449 /* Don't use this trick for assembly source files. */
450 sal
= find_pc_line (func_addr
, 0);
451 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
456 /* Can't find the prologue end in the symbol table, try it the hard way
457 by disassembling the instructions. */
459 /* Like arm_scan_prologue, stop no later than pc + 64. */
460 if (func_end
== 0 || func_end
> pc
+ 64)
463 /* Check if this is Thumb code. */
464 if (arm_pc_is_thumb (pc
))
465 return thumb_analyze_prologue (current_gdbarch
, pc
, func_end
, NULL
);
467 for (skip_pc
= pc
; skip_pc
< func_end
; skip_pc
+= 4)
469 inst
= read_memory_unsigned_integer (skip_pc
, 4);
471 /* "mov ip, sp" is no longer a required part of the prologue. */
472 if (inst
== 0xe1a0c00d) /* mov ip, sp */
475 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
478 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
481 /* Some prologues begin with "str lr, [sp, #-4]!". */
482 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
485 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
488 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
491 /* Any insns after this point may float into the code, if it makes
492 for better instruction scheduling, so we skip them only if we
493 find them, but still consider the function to be frame-ful. */
495 /* We may have either one sfmfd instruction here, or several stfe
496 insns, depending on the version of floating point code we
498 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
501 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
504 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
507 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
510 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
511 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
512 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
515 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
516 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
517 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
520 /* Un-recognized instruction; stop scanning. */
524 return skip_pc
; /* End of prologue */
528 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
529 This function decodes a Thumb function prologue to determine:
530 1) the size of the stack frame
531 2) which registers are saved on it
532 3) the offsets of saved regs
533 4) the offset from the stack pointer to the frame pointer
535 A typical Thumb function prologue would create this stack frame
536 (offsets relative to FP)
537 old SP -> 24 stack parameters
540 R7 -> 0 local variables (16 bytes)
541 SP -> -12 additional stack space (12 bytes)
542 The frame size would thus be 36 bytes, and the frame offset would be
543 12 bytes. The frame register is R7.
545 The comments for thumb_skip_prolog() describe the algorithm we use
546 to detect the end of the prolog. */
550 thumb_scan_prologue (CORE_ADDR prev_pc
, struct arm_prologue_cache
*cache
)
552 CORE_ADDR prologue_start
;
553 CORE_ADDR prologue_end
;
554 CORE_ADDR current_pc
;
555 /* Which register has been copied to register n? */
558 bit 0 - push { rlist }
559 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
560 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
565 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
567 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
569 if (sal
.line
== 0) /* no line info, use current PC */
570 prologue_end
= prev_pc
;
571 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
572 prologue_end
= sal
.end
; /* (probably means no prologue) */
575 /* We're in the boondocks: we have no idea where the start of the
579 prologue_end
= min (prologue_end
, prev_pc
);
581 thumb_analyze_prologue (current_gdbarch
, prologue_start
, prologue_end
,
585 /* This function decodes an ARM function prologue to determine:
586 1) the size of the stack frame
587 2) which registers are saved on it
588 3) the offsets of saved regs
589 4) the offset from the stack pointer to the frame pointer
590 This information is stored in the "extra" fields of the frame_info.
592 There are two basic forms for the ARM prologue. The fixed argument
593 function call will look like:
596 stmfd sp!, {fp, ip, lr, pc}
600 Which would create this stack frame (offsets relative to FP):
601 IP -> 4 (caller's stack)
602 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
603 -4 LR (return address in caller)
604 -8 IP (copy of caller's SP)
606 SP -> -28 Local variables
608 The frame size would thus be 32 bytes, and the frame offset would be
609 28 bytes. The stmfd call can also save any of the vN registers it
610 plans to use, which increases the frame size accordingly.
612 Note: The stored PC is 8 off of the STMFD instruction that stored it
613 because the ARM Store instructions always store PC + 8 when you read
616 A variable argument function call will look like:
619 stmfd sp!, {a1, a2, a3, a4}
620 stmfd sp!, {fp, ip, lr, pc}
623 Which would create this stack frame (offsets relative to FP):
624 IP -> 20 (caller's stack)
629 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
630 -4 LR (return address in caller)
631 -8 IP (copy of caller's SP)
633 SP -> -28 Local variables
635 The frame size would thus be 48 bytes, and the frame offset would be
638 There is another potential complication, which is that the optimizer
639 will try to separate the store of fp in the "stmfd" instruction from
640 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
641 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
643 Also, note, the original version of the ARM toolchain claimed that there
646 instruction at the end of the prologue. I have never seen GCC produce
647 this, and the ARM docs don't mention it. We still test for it below in
653 arm_scan_prologue (struct frame_info
*next_frame
, struct arm_prologue_cache
*cache
)
655 int regno
, sp_offset
, fp_offset
, ip_offset
;
656 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
657 CORE_ADDR prev_pc
= frame_pc_unwind (next_frame
);
659 /* Assume there is no frame until proven otherwise. */
660 cache
->framereg
= ARM_SP_REGNUM
;
661 cache
->framesize
= 0;
662 cache
->frameoffset
= 0;
664 /* Check for Thumb prologue. */
665 if (arm_pc_is_thumb (prev_pc
))
667 thumb_scan_prologue (prev_pc
, cache
);
671 /* Find the function prologue. If we can't find the function in
672 the symbol table, peek in the stack frame to find the PC. */
673 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
675 /* One way to find the end of the prologue (which works well
676 for unoptimized code) is to do the following:
678 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
681 prologue_end = prev_pc;
682 else if (sal.end < prologue_end)
683 prologue_end = sal.end;
685 This mechanism is very accurate so long as the optimizer
686 doesn't move any instructions from the function body into the
687 prologue. If this happens, sal.end will be the last
688 instruction in the first hunk of prologue code just before
689 the first instruction that the scheduler has moved from
690 the body to the prologue.
692 In order to make sure that we scan all of the prologue
693 instructions, we use a slightly less accurate mechanism which
694 may scan more than necessary. To help compensate for this
695 lack of accuracy, the prologue scanning loop below contains
696 several clauses which'll cause the loop to terminate early if
697 an implausible prologue instruction is encountered.
703 is a suitable endpoint since it accounts for the largest
704 possible prologue plus up to five instructions inserted by
707 if (prologue_end
> prologue_start
+ 64)
709 prologue_end
= prologue_start
+ 64; /* See above. */
714 /* We have no symbol information. Our only option is to assume this
715 function has a standard stack frame and the normal frame register.
716 Then, we can find the value of our frame pointer on entrance to
717 the callee (or at the present moment if this is the innermost frame).
718 The value stored there should be the address of the stmfd + 8. */
720 LONGEST return_value
;
722 frame_loc
= frame_unwind_register_unsigned (next_frame
, ARM_FP_REGNUM
);
723 if (!safe_read_memory_integer (frame_loc
, 4, &return_value
))
727 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
728 prologue_end
= prologue_start
+ 64; /* See above. */
732 if (prev_pc
< prologue_end
)
733 prologue_end
= prev_pc
;
735 /* Now search the prologue looking for instructions that set up the
736 frame pointer, adjust the stack pointer, and save registers.
738 Be careful, however, and if it doesn't look like a prologue,
739 don't try to scan it. If, for instance, a frameless function
740 begins with stmfd sp!, then we will tell ourselves there is
741 a frame, which will confuse stack traceback, as well as "finish"
742 and other operations that rely on a knowledge of the stack
745 In the APCS, the prologue should start with "mov ip, sp" so
746 if we don't see this as the first insn, we will stop.
748 [Note: This doesn't seem to be true any longer, so it's now an
749 optional part of the prologue. - Kevin Buettner, 2001-11-20]
751 [Note further: The "mov ip,sp" only seems to be missing in
752 frameless functions at optimization level "-O2" or above,
753 in which case it is often (but not always) replaced by
754 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
756 sp_offset
= fp_offset
= ip_offset
= 0;
758 for (current_pc
= prologue_start
;
759 current_pc
< prologue_end
;
762 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
764 if (insn
== 0xe1a0c00d) /* mov ip, sp */
769 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
771 unsigned imm
= insn
& 0xff; /* immediate value */
772 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
773 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
777 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
779 unsigned imm
= insn
& 0xff; /* immediate value */
780 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
781 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
785 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
788 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= sp_offset
;
791 else if ((insn
& 0xffff0000) == 0xe92d0000)
792 /* stmfd sp!, {..., fp, ip, lr, pc}
794 stmfd sp!, {a1, a2, a3, a4} */
796 int mask
= insn
& 0xffff;
798 /* Calculate offsets of saved registers. */
799 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
800 if (mask
& (1 << regno
))
803 cache
->saved_regs
[regno
].addr
= sp_offset
;
806 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
807 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
808 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
810 /* No need to add this to saved_regs -- it's just an arg reg. */
813 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
814 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
815 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
817 /* No need to add this to saved_regs -- it's just an arg reg. */
820 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
822 unsigned imm
= insn
& 0xff; /* immediate value */
823 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
824 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
825 fp_offset
= -imm
+ ip_offset
;
826 cache
->framereg
= ARM_FP_REGNUM
;
828 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
830 unsigned imm
= insn
& 0xff; /* immediate value */
831 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
832 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
835 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
836 && gdbarch_tdep (current_gdbarch
)->have_fpa_registers
)
839 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
840 cache
->saved_regs
[regno
].addr
= sp_offset
;
842 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
843 && gdbarch_tdep (current_gdbarch
)->have_fpa_registers
)
846 unsigned int fp_start_reg
, fp_bound_reg
;
848 if ((insn
& 0x800) == 0x800) /* N0 is set */
850 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
857 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
863 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
864 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
865 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
868 cache
->saved_regs
[fp_start_reg
++].addr
= sp_offset
;
871 else if ((insn
& 0xf0000000) != 0xe0000000)
872 break; /* Condition not true, exit early */
873 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
874 break; /* Don't scan past a block load */
876 /* The optimizer might shove anything into the prologue,
877 so we just skip what we don't recognize. */
881 /* The frame size is just the negative of the offset (from the
882 original SP) of the last thing thing we pushed on the stack.
883 The frame offset is [new FP] - [new SP]. */
884 cache
->framesize
= -sp_offset
;
885 if (cache
->framereg
== ARM_FP_REGNUM
)
886 cache
->frameoffset
= fp_offset
- sp_offset
;
888 cache
->frameoffset
= 0;
891 static struct arm_prologue_cache
*
892 arm_make_prologue_cache (struct frame_info
*next_frame
)
895 struct arm_prologue_cache
*cache
;
896 CORE_ADDR unwound_fp
;
898 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
899 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
901 arm_scan_prologue (next_frame
, cache
);
903 unwound_fp
= frame_unwind_register_unsigned (next_frame
, cache
->framereg
);
907 cache
->prev_sp
= unwound_fp
+ cache
->framesize
- cache
->frameoffset
;
909 /* Calculate actual addresses of saved registers using offsets
910 determined by arm_scan_prologue. */
911 for (reg
= 0; reg
< NUM_REGS
; reg
++)
912 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
913 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
918 /* Our frame ID for a normal frame is the current function's starting PC
919 and the caller's SP when we were called. */
922 arm_prologue_this_id (struct frame_info
*next_frame
,
924 struct frame_id
*this_id
)
926 struct arm_prologue_cache
*cache
;
930 if (*this_cache
== NULL
)
931 *this_cache
= arm_make_prologue_cache (next_frame
);
934 func
= frame_func_unwind (next_frame
, NORMAL_FRAME
);
936 /* This is meant to halt the backtrace at "_start". Make sure we
937 don't halt it at a generic dummy frame. */
938 if (func
<= LOWEST_PC
)
941 /* If we've hit a wall, stop. */
942 if (cache
->prev_sp
== 0)
945 id
= frame_id_build (cache
->prev_sp
, func
);
950 arm_prologue_prev_register (struct frame_info
*next_frame
,
954 enum lval_type
*lvalp
,
959 struct arm_prologue_cache
*cache
;
961 if (*this_cache
== NULL
)
962 *this_cache
= arm_make_prologue_cache (next_frame
);
965 /* If we are asked to unwind the PC, then we need to return the LR
966 instead. The saved value of PC points into this frame's
967 prologue, not the next frame's resume location. */
968 if (prev_regnum
== ARM_PC_REGNUM
)
969 prev_regnum
= ARM_LR_REGNUM
;
971 /* SP is generally not saved to the stack, but this frame is
972 identified by NEXT_FRAME's stack pointer at the time of the call.
973 The value was already reconstructed into PREV_SP. */
974 if (prev_regnum
== ARM_SP_REGNUM
)
978 store_unsigned_integer (valuep
, 4, cache
->prev_sp
);
982 trad_frame_get_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
983 optimized
, lvalp
, addrp
, realnump
, valuep
);
986 struct frame_unwind arm_prologue_unwind
= {
988 arm_prologue_this_id
,
989 arm_prologue_prev_register
992 static const struct frame_unwind
*
993 arm_prologue_unwind_sniffer (struct frame_info
*next_frame
)
995 return &arm_prologue_unwind
;
998 static struct arm_prologue_cache
*
999 arm_make_stub_cache (struct frame_info
*next_frame
)
1002 struct arm_prologue_cache
*cache
;
1003 CORE_ADDR unwound_fp
;
1005 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1006 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1008 cache
->prev_sp
= frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
);
1013 /* Our frame ID for a stub frame is the current SP and LR. */
1016 arm_stub_this_id (struct frame_info
*next_frame
,
1018 struct frame_id
*this_id
)
1020 struct arm_prologue_cache
*cache
;
1022 if (*this_cache
== NULL
)
1023 *this_cache
= arm_make_stub_cache (next_frame
);
1024 cache
= *this_cache
;
1026 *this_id
= frame_id_build (cache
->prev_sp
,
1027 frame_pc_unwind (next_frame
));
1030 struct frame_unwind arm_stub_unwind
= {
1033 arm_prologue_prev_register
1036 static const struct frame_unwind
*
1037 arm_stub_unwind_sniffer (struct frame_info
*next_frame
)
1039 CORE_ADDR addr_in_block
;
1042 addr_in_block
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1043 if (in_plt_section (addr_in_block
, NULL
)
1044 || target_read_memory (frame_pc_unwind (next_frame
), dummy
, 4) != 0)
1045 return &arm_stub_unwind
;
1051 arm_normal_frame_base (struct frame_info
*next_frame
, void **this_cache
)
1053 struct arm_prologue_cache
*cache
;
1055 if (*this_cache
== NULL
)
1056 *this_cache
= arm_make_prologue_cache (next_frame
);
1057 cache
= *this_cache
;
1059 return cache
->prev_sp
+ cache
->frameoffset
- cache
->framesize
;
1062 struct frame_base arm_normal_base
= {
1063 &arm_prologue_unwind
,
1064 arm_normal_frame_base
,
1065 arm_normal_frame_base
,
1066 arm_normal_frame_base
1069 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1070 dummy frame. The frame ID's base needs to match the TOS value
1071 saved by save_dummy_frame_tos() and returned from
1072 arm_push_dummy_call, and the PC needs to match the dummy frame's
1075 static struct frame_id
1076 arm_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1078 return frame_id_build (frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
),
1079 frame_pc_unwind (next_frame
));
1082 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1083 be used to construct the previous frame's ID, after looking up the
1084 containing function). */
1087 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1090 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1091 return arm_addr_bits_remove (pc
);
1095 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1097 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1100 /* When arguments must be pushed onto the stack, they go on in reverse
1101 order. The code below implements a FILO (stack) to do this. */
1106 struct stack_item
*prev
;
1110 static struct stack_item
*
1111 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1113 struct stack_item
*si
;
1114 si
= xmalloc (sizeof (struct stack_item
));
1115 si
->data
= xmalloc (len
);
1118 memcpy (si
->data
, contents
, len
);
1122 static struct stack_item
*
1123 pop_stack_item (struct stack_item
*si
)
1125 struct stack_item
*dead
= si
;
1133 /* Return the alignment (in bytes) of the given type. */
1136 arm_type_align (struct type
*t
)
1142 t
= check_typedef (t
);
1143 switch (TYPE_CODE (t
))
1146 /* Should never happen. */
1147 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1151 case TYPE_CODE_ENUM
:
1155 case TYPE_CODE_RANGE
:
1156 case TYPE_CODE_BITSTRING
:
1158 case TYPE_CODE_CHAR
:
1159 case TYPE_CODE_BOOL
:
1160 return TYPE_LENGTH (t
);
1162 case TYPE_CODE_ARRAY
:
1163 case TYPE_CODE_COMPLEX
:
1164 /* TODO: What about vector types? */
1165 return arm_type_align (TYPE_TARGET_TYPE (t
));
1167 case TYPE_CODE_STRUCT
:
1168 case TYPE_CODE_UNION
:
1170 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1172 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
1180 /* We currently only support passing parameters in integer registers. This
1181 conforms with GCC's default model. Several other variants exist and
1182 we should probably support some of them based on the selected ABI. */
1185 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1186 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1187 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1188 CORE_ADDR struct_addr
)
1193 struct stack_item
*si
= NULL
;
1195 /* Set the return address. For the ARM, the return breakpoint is
1196 always at BP_ADDR. */
1197 /* XXX Fix for Thumb. */
1198 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1200 /* Walk through the list of args and determine how large a temporary
1201 stack is required. Need to take care here as structs may be
1202 passed on the stack, and we have to to push them. */
1205 argreg
= ARM_A1_REGNUM
;
1208 /* The struct_return pointer occupies the first parameter
1209 passing register. */
1213 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = 0x%s\n",
1214 REGISTER_NAME (argreg
), paddr (struct_addr
));
1215 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1219 for (argnum
= 0; argnum
< nargs
; argnum
++)
1222 struct type
*arg_type
;
1223 struct type
*target_type
;
1224 enum type_code typecode
;
1228 arg_type
= check_typedef (value_type (args
[argnum
]));
1229 len
= TYPE_LENGTH (arg_type
);
1230 target_type
= TYPE_TARGET_TYPE (arg_type
);
1231 typecode
= TYPE_CODE (arg_type
);
1232 val
= value_contents_writeable (args
[argnum
]);
1234 align
= arm_type_align (arg_type
);
1235 /* Round alignment up to a whole number of words. */
1236 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
1237 /* Different ABIs have different maximum alignments. */
1238 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
1240 /* The APCS ABI only requires word alignment. */
1241 align
= INT_REGISTER_SIZE
;
1245 /* The AAPCS requires at most doubleword alignment. */
1246 if (align
> INT_REGISTER_SIZE
* 2)
1247 align
= INT_REGISTER_SIZE
* 2;
1250 /* Push stack padding for dowubleword alignment. */
1251 if (nstack
& (align
- 1))
1253 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1254 nstack
+= INT_REGISTER_SIZE
;
1257 /* Doubleword aligned quantities must go in even register pairs. */
1258 if (argreg
<= ARM_LAST_ARG_REGNUM
1259 && align
> INT_REGISTER_SIZE
1263 /* If the argument is a pointer to a function, and it is a
1264 Thumb function, create a LOCAL copy of the value and set
1265 the THUMB bit in it. */
1266 if (TYPE_CODE_PTR
== typecode
1267 && target_type
!= NULL
1268 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1270 CORE_ADDR regval
= extract_unsigned_integer (val
, len
);
1271 if (arm_pc_is_thumb (regval
))
1274 store_unsigned_integer (val
, len
, MAKE_THUMB_ADDR (regval
));
1278 /* Copy the argument to general registers or the stack in
1279 register-sized pieces. Large arguments are split between
1280 registers and stack. */
1283 int partial_len
= len
< DEPRECATED_REGISTER_SIZE
? len
: DEPRECATED_REGISTER_SIZE
;
1285 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1287 /* The argument is being passed in a general purpose
1289 CORE_ADDR regval
= extract_unsigned_integer (val
, partial_len
);
1291 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1292 argnum
, REGISTER_NAME (argreg
),
1293 phex (regval
, DEPRECATED_REGISTER_SIZE
));
1294 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1299 /* Push the arguments onto the stack. */
1301 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1303 si
= push_stack_item (si
, val
, DEPRECATED_REGISTER_SIZE
);
1304 nstack
+= DEPRECATED_REGISTER_SIZE
;
1311 /* If we have an odd number of words to push, then decrement the stack
1312 by one word now, so first stack argument will be dword aligned. */
1319 write_memory (sp
, si
->data
, si
->len
);
1320 si
= pop_stack_item (si
);
1323 /* Finally, update teh SP register. */
1324 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1330 /* Always align the frame to an 8-byte boundary. This is required on
1331 some platforms and harmless on the rest. */
1334 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1336 /* Align the stack to eight bytes. */
1337 return sp
& ~ (CORE_ADDR
) 7;
1341 print_fpu_flags (int flags
)
1343 if (flags
& (1 << 0))
1344 fputs ("IVO ", stdout
);
1345 if (flags
& (1 << 1))
1346 fputs ("DVZ ", stdout
);
1347 if (flags
& (1 << 2))
1348 fputs ("OFL ", stdout
);
1349 if (flags
& (1 << 3))
1350 fputs ("UFL ", stdout
);
1351 if (flags
& (1 << 4))
1352 fputs ("INX ", stdout
);
1356 /* Print interesting information about the floating point processor
1357 (if present) or emulator. */
1359 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1360 struct frame_info
*frame
, const char *args
)
1362 unsigned long status
= read_register (ARM_FPS_REGNUM
);
1365 type
= (status
>> 24) & 127;
1366 if (status
& (1 << 31))
1367 printf (_("Hardware FPU type %d\n"), type
);
1369 printf (_("Software FPU type %d\n"), type
);
1370 /* i18n: [floating point unit] mask */
1371 fputs (_("mask: "), stdout
);
1372 print_fpu_flags (status
>> 16);
1373 /* i18n: [floating point unit] flags */
1374 fputs (_("flags: "), stdout
);
1375 print_fpu_flags (status
);
1378 /* Return the GDB type object for the "standard" data type of data in
1381 static struct type
*
1382 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
1384 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1385 return builtin_type_arm_ext
;
1386 else if (regnum
== ARM_SP_REGNUM
)
1387 return builtin_type_void_data_ptr
;
1388 else if (regnum
== ARM_PC_REGNUM
)
1389 return builtin_type_void_func_ptr
;
1390 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
1391 /* These registers are only supported on targets which supply
1392 an XML description. */
1393 return builtin_type_int0
;
1395 return builtin_type_uint32
;
1398 /* Map a DWARF register REGNUM onto the appropriate GDB register
1402 arm_dwarf_reg_to_regnum (int reg
)
1404 /* Core integer regs. */
1405 if (reg
>= 0 && reg
<= 15)
1408 /* Legacy FPA encoding. These were once used in a way which
1409 overlapped with VFP register numbering, so their use is
1410 discouraged, but GDB doesn't support the ARM toolchain
1411 which used them for VFP. */
1412 if (reg
>= 16 && reg
<= 23)
1413 return ARM_F0_REGNUM
+ reg
- 16;
1415 /* New assignments for the FPA registers. */
1416 if (reg
>= 96 && reg
<= 103)
1417 return ARM_F0_REGNUM
+ reg
- 96;
1419 /* WMMX register assignments. */
1420 if (reg
>= 104 && reg
<= 111)
1421 return ARM_WCGR0_REGNUM
+ reg
- 104;
1423 if (reg
>= 112 && reg
<= 127)
1424 return ARM_WR0_REGNUM
+ reg
- 112;
1426 if (reg
>= 192 && reg
<= 199)
1427 return ARM_WC0_REGNUM
+ reg
- 192;
1432 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1434 arm_register_sim_regno (int regnum
)
1437 gdb_assert (reg
>= 0 && reg
< NUM_REGS
);
1439 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
1440 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
1442 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
1443 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
1445 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
1446 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
1448 if (reg
< NUM_GREGS
)
1449 return SIM_ARM_R0_REGNUM
+ reg
;
1452 if (reg
< NUM_FREGS
)
1453 return SIM_ARM_FP0_REGNUM
+ reg
;
1456 if (reg
< NUM_SREGS
)
1457 return SIM_ARM_FPS_REGNUM
+ reg
;
1460 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
1463 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1464 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1465 It is thought that this is is the floating-point register format on
1466 little-endian systems. */
1469 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
1473 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1474 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1476 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1478 floatformat_from_doublest (fmt
, &d
, dbl
);
1482 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
)
1485 floatformat_to_doublest (fmt
, ptr
, &d
);
1486 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1487 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1489 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1494 condition_true (unsigned long cond
, unsigned long status_reg
)
1496 if (cond
== INST_AL
|| cond
== INST_NV
)
1502 return ((status_reg
& FLAG_Z
) != 0);
1504 return ((status_reg
& FLAG_Z
) == 0);
1506 return ((status_reg
& FLAG_C
) != 0);
1508 return ((status_reg
& FLAG_C
) == 0);
1510 return ((status_reg
& FLAG_N
) != 0);
1512 return ((status_reg
& FLAG_N
) == 0);
1514 return ((status_reg
& FLAG_V
) != 0);
1516 return ((status_reg
& FLAG_V
) == 0);
1518 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1520 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1522 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1524 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1526 return (((status_reg
& FLAG_Z
) == 0) &&
1527 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1529 return (((status_reg
& FLAG_Z
) != 0) ||
1530 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1535 /* Support routines for single stepping. Calculate the next PC value. */
1536 #define submask(x) ((1L << ((x) + 1)) - 1)
1537 #define bit(obj,st) (((obj) >> (st)) & 1)
1538 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1539 #define sbits(obj,st,fn) \
1540 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1541 #define BranchDest(addr,instr) \
1542 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1545 static unsigned long
1546 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1547 unsigned long status_reg
)
1549 unsigned long res
, shift
;
1550 int rm
= bits (inst
, 0, 3);
1551 unsigned long shifttype
= bits (inst
, 5, 6);
1555 int rs
= bits (inst
, 8, 11);
1556 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1559 shift
= bits (inst
, 7, 11);
1562 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1563 + (bit (inst
, 4) ? 12 : 8))
1564 : read_register (rm
));
1569 res
= shift
>= 32 ? 0 : res
<< shift
;
1573 res
= shift
>= 32 ? 0 : res
>> shift
;
1579 res
= ((res
& 0x80000000L
)
1580 ? ~((~res
) >> shift
) : res
>> shift
);
1583 case 3: /* ROR/RRX */
1586 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1588 res
= (res
>> shift
) | (res
<< (32 - shift
));
1592 return res
& 0xffffffff;
1595 /* Return number of 1-bits in VAL. */
1598 bitcount (unsigned long val
)
1601 for (nbits
= 0; val
!= 0; nbits
++)
1602 val
&= val
- 1; /* delete rightmost 1-bit in val */
1607 thumb_get_next_pc (CORE_ADDR pc
)
1609 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1610 unsigned short inst1
= read_memory_unsigned_integer (pc
, 2);
1611 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1612 unsigned long offset
;
1614 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1618 /* Fetch the saved PC from the stack. It's stored above
1619 all of the other registers. */
1620 offset
= bitcount (bits (inst1
, 0, 7)) * DEPRECATED_REGISTER_SIZE
;
1621 sp
= read_register (ARM_SP_REGNUM
);
1622 nextpc
= (CORE_ADDR
) read_memory_unsigned_integer (sp
+ offset
, 4);
1623 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1625 error (_("Infinite loop detected"));
1627 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1629 unsigned long status
= read_register (ARM_PS_REGNUM
);
1630 unsigned long cond
= bits (inst1
, 8, 11);
1631 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1632 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1634 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1636 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1638 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link, and blx */
1640 unsigned short inst2
= read_memory_unsigned_integer (pc
+ 2, 2);
1641 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1642 nextpc
= pc_val
+ offset
;
1643 /* For BLX make sure to clear the low bits. */
1644 if (bits (inst2
, 11, 12) == 1)
1645 nextpc
= nextpc
& 0xfffffffc;
1647 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
1649 if (bits (inst1
, 3, 6) == 0x0f)
1652 nextpc
= read_register (bits (inst1
, 3, 6));
1654 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1656 error (_("Infinite loop detected"));
1663 arm_get_next_pc (CORE_ADDR pc
)
1665 unsigned long pc_val
;
1666 unsigned long this_instr
;
1667 unsigned long status
;
1670 if (arm_pc_is_thumb (pc
))
1671 return thumb_get_next_pc (pc
);
1673 pc_val
= (unsigned long) pc
;
1674 this_instr
= read_memory_unsigned_integer (pc
, 4);
1675 status
= read_register (ARM_PS_REGNUM
);
1676 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1678 if (condition_true (bits (this_instr
, 28, 31), status
))
1680 switch (bits (this_instr
, 24, 27))
1683 case 0x1: /* data processing */
1687 unsigned long operand1
, operand2
, result
= 0;
1691 if (bits (this_instr
, 12, 15) != 15)
1694 if (bits (this_instr
, 22, 25) == 0
1695 && bits (this_instr
, 4, 7) == 9) /* multiply */
1696 error (_("Invalid update to pc in instruction"));
1698 /* BX <reg>, BLX <reg> */
1699 if (bits (this_instr
, 4, 27) == 0x12fff1
1700 || bits (this_instr
, 4, 27) == 0x12fff3)
1702 rn
= bits (this_instr
, 0, 3);
1703 result
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1704 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1707 error (_("Infinite loop detected"));
1712 /* Multiply into PC */
1713 c
= (status
& FLAG_C
) ? 1 : 0;
1714 rn
= bits (this_instr
, 16, 19);
1715 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1717 if (bit (this_instr
, 25))
1719 unsigned long immval
= bits (this_instr
, 0, 7);
1720 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1721 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1724 else /* operand 2 is a shifted register */
1725 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1727 switch (bits (this_instr
, 21, 24))
1730 result
= operand1
& operand2
;
1734 result
= operand1
^ operand2
;
1738 result
= operand1
- operand2
;
1742 result
= operand2
- operand1
;
1746 result
= operand1
+ operand2
;
1750 result
= operand1
+ operand2
+ c
;
1754 result
= operand1
- operand2
+ c
;
1758 result
= operand2
- operand1
+ c
;
1764 case 0xb: /* tst, teq, cmp, cmn */
1765 result
= (unsigned long) nextpc
;
1769 result
= operand1
| operand2
;
1773 /* Always step into a function. */
1778 result
= operand1
& ~operand2
;
1785 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1788 error (_("Infinite loop detected"));
1793 case 0x5: /* data transfer */
1796 if (bit (this_instr
, 20))
1799 if (bits (this_instr
, 12, 15) == 15)
1805 if (bit (this_instr
, 22))
1806 error (_("Invalid update to pc in instruction"));
1808 /* byte write to PC */
1809 rn
= bits (this_instr
, 16, 19);
1810 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1811 if (bit (this_instr
, 24))
1814 int c
= (status
& FLAG_C
) ? 1 : 0;
1815 unsigned long offset
=
1816 (bit (this_instr
, 25)
1817 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1818 : bits (this_instr
, 0, 11));
1820 if (bit (this_instr
, 23))
1825 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1828 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1831 error (_("Infinite loop detected"));
1837 case 0x9: /* block transfer */
1838 if (bit (this_instr
, 20))
1841 if (bit (this_instr
, 15))
1846 if (bit (this_instr
, 23))
1849 unsigned long reglist
= bits (this_instr
, 0, 14);
1850 offset
= bitcount (reglist
) * 4;
1851 if (bit (this_instr
, 24)) /* pre */
1854 else if (bit (this_instr
, 24))
1858 unsigned long rn_val
=
1859 read_register (bits (this_instr
, 16, 19));
1861 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1865 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1867 error (_("Infinite loop detected"));
1872 case 0xb: /* branch & link */
1873 case 0xa: /* branch */
1875 nextpc
= BranchDest (pc
, this_instr
);
1878 if (bits (this_instr
, 28, 31) == INST_NV
)
1879 nextpc
|= bit (this_instr
, 24) << 1;
1881 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1883 error (_("Infinite loop detected"));
1889 case 0xe: /* coproc ops */
1894 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
1902 /* single_step() is called just before we want to resume the inferior,
1903 if we want to single-step it but there is no hardware or kernel
1904 single-step support. We find the target of the coming instruction
1905 and breakpoint it. */
1908 arm_software_single_step (struct regcache
*regcache
)
1910 /* NOTE: This may insert the wrong breakpoint instruction when
1911 single-stepping over a mode-changing instruction, if the
1912 CPSR heuristics are used. */
1914 CORE_ADDR next_pc
= arm_get_next_pc (read_register (ARM_PC_REGNUM
));
1915 insert_single_step_breakpoint (next_pc
);
1920 #include "bfd-in2.h"
1921 #include "libcoff.h"
1924 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
1926 if (arm_pc_is_thumb (memaddr
))
1928 static asymbol
*asym
;
1929 static combined_entry_type ce
;
1930 static struct coff_symbol_struct csym
;
1931 static struct bfd fake_bfd
;
1932 static bfd_target fake_target
;
1934 if (csym
.native
== NULL
)
1936 /* Create a fake symbol vector containing a Thumb symbol.
1937 This is solely so that the code in print_insn_little_arm()
1938 and print_insn_big_arm() in opcodes/arm-dis.c will detect
1939 the presence of a Thumb symbol and switch to decoding
1940 Thumb instructions. */
1942 fake_target
.flavour
= bfd_target_coff_flavour
;
1943 fake_bfd
.xvec
= &fake_target
;
1944 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
1946 csym
.symbol
.the_bfd
= &fake_bfd
;
1947 csym
.symbol
.name
= "fake";
1948 asym
= (asymbol
*) & csym
;
1951 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
1952 info
->symbols
= &asym
;
1955 info
->symbols
= NULL
;
1957 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1958 return print_insn_big_arm (memaddr
, info
);
1960 return print_insn_little_arm (memaddr
, info
);
1963 /* The following define instruction sequences that will cause ARM
1964 cpu's to take an undefined instruction trap. These are used to
1965 signal a breakpoint to GDB.
1967 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
1968 modes. A different instruction is required for each mode. The ARM
1969 cpu's can also be big or little endian. Thus four different
1970 instructions are needed to support all cases.
1972 Note: ARMv4 defines several new instructions that will take the
1973 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
1974 not in fact add the new instructions. The new undefined
1975 instructions in ARMv4 are all instructions that had no defined
1976 behaviour in earlier chips. There is no guarantee that they will
1977 raise an exception, but may be treated as NOP's. In practice, it
1978 may only safe to rely on instructions matching:
1980 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1981 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1982 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
1984 Even this may only true if the condition predicate is true. The
1985 following use a condition predicate of ALWAYS so it is always TRUE.
1987 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
1988 and NetBSD all use a software interrupt rather than an undefined
1989 instruction to force a trap. This can be handled by by the
1990 abi-specific code during establishment of the gdbarch vector. */
1992 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
1993 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
1994 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
1995 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
1997 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
1998 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
1999 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2000 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2002 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2003 the program counter value to determine whether a 16-bit or 32-bit
2004 breakpoint should be used. It returns a pointer to a string of
2005 bytes that encode a breakpoint instruction, stores the length of
2006 the string to *lenptr, and adjusts the program counter (if
2007 necessary) to point to the actual memory location where the
2008 breakpoint should be inserted. */
2010 static const unsigned char *
2011 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
2013 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2015 if (arm_pc_is_thumb (*pcptr
))
2017 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2018 *lenptr
= tdep
->thumb_breakpoint_size
;
2019 return tdep
->thumb_breakpoint
;
2023 *lenptr
= tdep
->arm_breakpoint_size
;
2024 return tdep
->arm_breakpoint
;
2028 /* Extract from an array REGBUF containing the (raw) register state a
2029 function return value of type TYPE, and copy that, in virtual
2030 format, into VALBUF. */
2033 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
2036 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2038 switch (gdbarch_tdep (current_gdbarch
)->fp_model
)
2042 /* The value is in register F0 in internal format. We need to
2043 extract the raw value and then convert it to the desired
2045 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
2047 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
2048 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
2053 case ARM_FLOAT_SOFT_FPA
:
2054 case ARM_FLOAT_SOFT_VFP
:
2055 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
2056 if (TYPE_LENGTH (type
) > 4)
2057 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
2058 valbuf
+ INT_REGISTER_SIZE
);
2063 (__FILE__
, __LINE__
,
2064 _("arm_extract_return_value: Floating point model not supported"));
2068 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2069 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2070 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2071 || TYPE_CODE (type
) == TYPE_CODE_PTR
2072 || TYPE_CODE (type
) == TYPE_CODE_REF
2073 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2075 /* If the the type is a plain integer, then the access is
2076 straight-forward. Otherwise we have to play around a bit more. */
2077 int len
= TYPE_LENGTH (type
);
2078 int regno
= ARM_A1_REGNUM
;
2083 /* By using store_unsigned_integer we avoid having to do
2084 anything special for small big-endian values. */
2085 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2086 store_unsigned_integer (valbuf
,
2087 (len
> INT_REGISTER_SIZE
2088 ? INT_REGISTER_SIZE
: len
),
2090 len
-= INT_REGISTER_SIZE
;
2091 valbuf
+= INT_REGISTER_SIZE
;
2096 /* For a structure or union the behaviour is as if the value had
2097 been stored to word-aligned memory and then loaded into
2098 registers with 32-bit load instruction(s). */
2099 int len
= TYPE_LENGTH (type
);
2100 int regno
= ARM_A1_REGNUM
;
2101 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2105 regcache_cooked_read (regs
, regno
++, tmpbuf
);
2106 memcpy (valbuf
, tmpbuf
,
2107 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2108 len
-= INT_REGISTER_SIZE
;
2109 valbuf
+= INT_REGISTER_SIZE
;
2115 /* Will a function return an aggregate type in memory or in a
2116 register? Return 0 if an aggregate type can be returned in a
2117 register, 1 if it must be returned in memory. */
2120 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2123 enum type_code code
;
2125 CHECK_TYPEDEF (type
);
2127 /* In the ARM ABI, "integer" like aggregate types are returned in
2128 registers. For an aggregate type to be integer like, its size
2129 must be less than or equal to DEPRECATED_REGISTER_SIZE and the
2130 offset of each addressable subfield must be zero. Note that bit
2131 fields are not addressable, and all addressable subfields of
2132 unions always start at offset zero.
2134 This function is based on the behaviour of GCC 2.95.1.
2135 See: gcc/arm.c: arm_return_in_memory() for details.
2137 Note: All versions of GCC before GCC 2.95.2 do not set up the
2138 parameters correctly for a function returning the following
2139 structure: struct { float f;}; This should be returned in memory,
2140 not a register. Richard Earnshaw sent me a patch, but I do not
2141 know of any way to detect if a function like the above has been
2142 compiled with the correct calling convention. */
2144 /* All aggregate types that won't fit in a register must be returned
2146 if (TYPE_LENGTH (type
) > DEPRECATED_REGISTER_SIZE
)
2151 /* The AAPCS says all aggregates not larger than a word are returned
2153 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
2156 /* The only aggregate types that can be returned in a register are
2157 structs and unions. Arrays must be returned in memory. */
2158 code
= TYPE_CODE (type
);
2159 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2164 /* Assume all other aggregate types can be returned in a register.
2165 Run a check for structures, unions and arrays. */
2168 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2171 /* Need to check if this struct/union is "integer" like. For
2172 this to be true, its size must be less than or equal to
2173 DEPRECATED_REGISTER_SIZE and the offset of each addressable
2174 subfield must be zero. Note that bit fields are not
2175 addressable, and unions always start at offset zero. If any
2176 of the subfields is a floating point type, the struct/union
2177 cannot be an integer type. */
2179 /* For each field in the object, check:
2180 1) Is it FP? --> yes, nRc = 1;
2181 2) Is it addressable (bitpos != 0) and
2182 not packed (bitsize == 0)?
2186 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2188 enum type_code field_type_code
;
2189 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, i
)));
2191 /* Is it a floating point type field? */
2192 if (field_type_code
== TYPE_CODE_FLT
)
2198 /* If bitpos != 0, then we have to care about it. */
2199 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2201 /* Bitfields are not addressable. If the field bitsize is
2202 zero, then the field is not packed. Hence it cannot be
2203 a bitfield or any other packed type. */
2204 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2216 /* Write into appropriate registers a function return value of type
2217 TYPE, given in virtual format. */
2220 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
2221 const gdb_byte
*valbuf
)
2223 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2225 char buf
[MAX_REGISTER_SIZE
];
2227 switch (gdbarch_tdep (current_gdbarch
)->fp_model
)
2231 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
);
2232 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
2235 case ARM_FLOAT_SOFT_FPA
:
2236 case ARM_FLOAT_SOFT_VFP
:
2237 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
2238 if (TYPE_LENGTH (type
) > 4)
2239 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
2240 valbuf
+ INT_REGISTER_SIZE
);
2245 (__FILE__
, __LINE__
,
2246 _("arm_store_return_value: Floating point model not supported"));
2250 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2251 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2252 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2253 || TYPE_CODE (type
) == TYPE_CODE_PTR
2254 || TYPE_CODE (type
) == TYPE_CODE_REF
2255 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2257 if (TYPE_LENGTH (type
) <= 4)
2259 /* Values of one word or less are zero/sign-extended and
2261 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2262 LONGEST val
= unpack_long (type
, valbuf
);
2264 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, val
);
2265 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
2269 /* Integral values greater than one word are stored in consecutive
2270 registers starting with r0. This will always be a multiple of
2271 the regiser size. */
2272 int len
= TYPE_LENGTH (type
);
2273 int regno
= ARM_A1_REGNUM
;
2277 regcache_cooked_write (regs
, regno
++, valbuf
);
2278 len
-= INT_REGISTER_SIZE
;
2279 valbuf
+= INT_REGISTER_SIZE
;
2285 /* For a structure or union the behaviour is as if the value had
2286 been stored to word-aligned memory and then loaded into
2287 registers with 32-bit load instruction(s). */
2288 int len
= TYPE_LENGTH (type
);
2289 int regno
= ARM_A1_REGNUM
;
2290 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2294 memcpy (tmpbuf
, valbuf
,
2295 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2296 regcache_cooked_write (regs
, regno
++, tmpbuf
);
2297 len
-= INT_REGISTER_SIZE
;
2298 valbuf
+= INT_REGISTER_SIZE
;
2304 /* Handle function return values. */
2306 static enum return_value_convention
2307 arm_return_value (struct gdbarch
*gdbarch
, struct type
*valtype
,
2308 struct regcache
*regcache
, gdb_byte
*readbuf
,
2309 const gdb_byte
*writebuf
)
2311 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2313 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2314 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2315 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2317 if (tdep
->struct_return
== pcc_struct_return
2318 || arm_return_in_memory (gdbarch
, valtype
))
2319 return RETURN_VALUE_STRUCT_CONVENTION
;
2323 arm_store_return_value (valtype
, regcache
, writebuf
);
2326 arm_extract_return_value (valtype
, regcache
, readbuf
);
2328 return RETURN_VALUE_REGISTER_CONVENTION
;
2333 arm_get_longjmp_target (CORE_ADDR
*pc
)
2336 char buf
[INT_REGISTER_SIZE
];
2337 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2339 jb_addr
= read_register (ARM_A1_REGNUM
);
2341 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2345 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
);
2349 /* Return non-zero if the PC is inside a thumb call thunk. */
2352 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2354 CORE_ADDR start_addr
;
2356 /* Find the starting address of the function containing the PC. If
2357 the caller didn't give us a name, look it up at the same time. */
2358 if (0 == find_pc_partial_function (pc
, name
? NULL
: &name
,
2362 return strncmp (name
, "_call_via_r", 11) == 0;
2365 /* If PC is in a Thumb call or return stub, return the address of the
2366 target PC, which is in a register. The thunk functions are called
2367 _called_via_xx, where x is the register name. The possible names
2368 are r0-r9, sl, fp, ip, sp, and lr. */
2371 arm_skip_stub (CORE_ADDR pc
)
2374 CORE_ADDR start_addr
;
2376 /* Find the starting address and name of the function containing the PC. */
2377 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2380 /* Call thunks always start with "_call_via_". */
2381 if (strncmp (name
, "_call_via_", 10) == 0)
2383 /* Use the name suffix to determine which register contains the
2385 static char *table
[15] =
2386 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2387 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2391 for (regno
= 0; regno
<= 14; regno
++)
2392 if (strcmp (&name
[10], table
[regno
]) == 0)
2393 return read_register (regno
);
2396 return 0; /* not a stub */
2400 set_arm_command (char *args
, int from_tty
)
2402 printf_unfiltered (_("\
2403 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2404 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
2408 show_arm_command (char *args
, int from_tty
)
2410 cmd_show_list (showarmcmdlist
, from_tty
, "");
2414 arm_update_current_architecture (void)
2416 struct gdbarch_info info
;
2418 /* If the current architecture is not ARM, we have nothing to do. */
2419 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_arm
)
2422 /* Update the architecture. */
2423 gdbarch_info_init (&info
);
2425 if (!gdbarch_update_p (info
))
2426 internal_error (__FILE__
, __LINE__
, "could not update architecture");
2430 set_fp_model_sfunc (char *args
, int from_tty
,
2431 struct cmd_list_element
*c
)
2433 enum arm_float_model fp_model
;
2435 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
2436 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
2438 arm_fp_model
= fp_model
;
2442 if (fp_model
== ARM_FLOAT_LAST
)
2443 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
2446 arm_update_current_architecture ();
2450 show_fp_model (struct ui_file
*file
, int from_tty
,
2451 struct cmd_list_element
*c
, const char *value
)
2453 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2455 if (arm_fp_model
== ARM_FLOAT_AUTO
2456 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2457 fprintf_filtered (file
, _("\
2458 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2459 fp_model_strings
[tdep
->fp_model
]);
2461 fprintf_filtered (file
, _("\
2462 The current ARM floating point model is \"%s\".\n"),
2463 fp_model_strings
[arm_fp_model
]);
2467 arm_set_abi (char *args
, int from_tty
,
2468 struct cmd_list_element
*c
)
2470 enum arm_abi_kind arm_abi
;
2472 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
2473 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
2475 arm_abi_global
= arm_abi
;
2479 if (arm_abi
== ARM_ABI_LAST
)
2480 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
2483 arm_update_current_architecture ();
2487 arm_show_abi (struct ui_file
*file
, int from_tty
,
2488 struct cmd_list_element
*c
, const char *value
)
2490 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2492 if (arm_abi_global
== ARM_ABI_AUTO
2493 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2494 fprintf_filtered (file
, _("\
2495 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2496 arm_abi_strings
[tdep
->arm_abi
]);
2498 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
2502 /* If the user changes the register disassembly style used for info
2503 register and other commands, we have to also switch the style used
2504 in opcodes for disassembly output. This function is run in the "set
2505 arm disassembly" command, and does that. */
2508 set_disassembly_style_sfunc (char *args
, int from_tty
,
2509 struct cmd_list_element
*c
)
2511 set_disassembly_style ();
2514 /* Return the ARM register name corresponding to register I. */
2516 arm_register_name (int i
)
2518 if (i
>= ARRAY_SIZE (arm_register_names
))
2519 /* These registers are only supported on targets which supply
2520 an XML description. */
2523 return arm_register_names
[i
];
2527 set_disassembly_style (void)
2531 /* Find the style that the user wants. */
2532 for (current
= 0; current
< num_disassembly_options
; current
++)
2533 if (disassembly_style
== valid_disassembly_styles
[current
])
2535 gdb_assert (current
< num_disassembly_options
);
2537 /* Synchronize the disassembler. */
2538 set_arm_regname_option (current
);
2541 /* Test whether the coff symbol specific value corresponds to a Thumb
2545 coff_sym_is_thumb (int val
)
2547 return (val
== C_THUMBEXT
||
2548 val
== C_THUMBSTAT
||
2549 val
== C_THUMBEXTFUNC
||
2550 val
== C_THUMBSTATFUNC
||
2551 val
== C_THUMBLABEL
);
2554 /* arm_coff_make_msymbol_special()
2555 arm_elf_make_msymbol_special()
2557 These functions test whether the COFF or ELF symbol corresponds to
2558 an address in thumb code, and set a "special" bit in a minimal
2559 symbol to indicate that it does. */
2562 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2564 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2566 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2568 MSYMBOL_SET_SPECIAL (msym
);
2572 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2574 if (coff_sym_is_thumb (val
))
2575 MSYMBOL_SET_SPECIAL (msym
);
2579 arm_write_pc (CORE_ADDR pc
, ptid_t ptid
)
2581 write_register_pid (ARM_PC_REGNUM
, pc
, ptid
);
2583 /* If necessary, set the T bit. */
2586 CORE_ADDR val
= read_register_pid (ARM_PS_REGNUM
, ptid
);
2587 if (arm_pc_is_thumb (pc
))
2588 write_register_pid (ARM_PS_REGNUM
, val
| 0x20, ptid
);
2590 write_register_pid (ARM_PS_REGNUM
, val
& ~(CORE_ADDR
) 0x20, ptid
);
2594 static struct value
*
2595 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
2597 const int *reg_p
= baton
;
2598 return value_of_register (*reg_p
, frame
);
2601 static enum gdb_osabi
2602 arm_elf_osabi_sniffer (bfd
*abfd
)
2604 unsigned int elfosabi
;
2605 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2607 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2609 if (elfosabi
== ELFOSABI_ARM
)
2610 /* GNU tools use this value. Check note sections in this case,
2612 bfd_map_over_sections (abfd
,
2613 generic_elf_osabi_sniff_abi_tag_sections
,
2616 /* Anything else will be handled by the generic ELF sniffer. */
2621 /* Initialize the current architecture based on INFO. If possible,
2622 re-use an architecture from ARCHES, which is a list of
2623 architectures already created during this debugging session.
2625 Called e.g. at program startup, when reading a core file, and when
2626 reading a binary file. */
2628 static struct gdbarch
*
2629 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2631 struct gdbarch_tdep
*tdep
;
2632 struct gdbarch
*gdbarch
;
2633 struct gdbarch_list
*best_arch
;
2634 enum arm_abi_kind arm_abi
= arm_abi_global
;
2635 enum arm_float_model fp_model
= arm_fp_model
;
2636 struct tdesc_arch_data
*tdesc_data
= NULL
;
2638 int have_fpa_registers
= 1;
2640 /* Check any target description for validity. */
2641 if (tdesc_has_registers (info
.target_desc
))
2643 /* For most registers we require GDB's default names; but also allow
2644 the numeric names for sp / lr / pc, as a convenience. */
2645 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
2646 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
2647 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
2649 const struct tdesc_feature
*feature
;
2652 feature
= tdesc_find_feature (info
.target_desc
,
2653 "org.gnu.gdb.arm.core");
2654 if (feature
== NULL
)
2657 tdesc_data
= tdesc_data_alloc ();
2660 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
2661 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
2662 arm_register_names
[i
]);
2663 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2666 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2669 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2672 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2673 ARM_PS_REGNUM
, "cpsr");
2677 tdesc_data_cleanup (tdesc_data
);
2681 feature
= tdesc_find_feature (info
.target_desc
,
2682 "org.gnu.gdb.arm.fpa");
2683 if (feature
!= NULL
)
2686 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
2687 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
2688 arm_register_names
[i
]);
2691 tdesc_data_cleanup (tdesc_data
);
2696 have_fpa_registers
= 0;
2698 feature
= tdesc_find_feature (info
.target_desc
,
2699 "org.gnu.gdb.xscale.iwmmxt");
2700 if (feature
!= NULL
)
2702 static const char *const iwmmxt_names
[] = {
2703 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
2704 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
2705 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
2706 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
2710 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
2712 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
2713 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
2715 /* Check for the control registers, but do not fail if they
2717 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
2718 tdesc_numbered_register (feature
, tdesc_data
, i
,
2719 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
2721 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
2723 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
2724 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
2728 tdesc_data_cleanup (tdesc_data
);
2734 /* If we have an object to base this architecture on, try to determine
2737 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
2739 int ei_osabi
, e_flags
;
2741 switch (bfd_get_flavour (info
.abfd
))
2743 case bfd_target_aout_flavour
:
2744 /* Assume it's an old APCS-style ABI. */
2745 arm_abi
= ARM_ABI_APCS
;
2748 case bfd_target_coff_flavour
:
2749 /* Assume it's an old APCS-style ABI. */
2751 arm_abi
= ARM_ABI_APCS
;
2754 case bfd_target_elf_flavour
:
2755 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
2756 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2758 if (ei_osabi
== ELFOSABI_ARM
)
2760 /* GNU tools used to use this value, but do not for EABI
2761 objects. There's nowhere to tag an EABI version
2762 anyway, so assume APCS. */
2763 arm_abi
= ARM_ABI_APCS
;
2765 else if (ei_osabi
== ELFOSABI_NONE
)
2767 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
2771 case EF_ARM_EABI_UNKNOWN
:
2772 /* Assume GNU tools. */
2773 arm_abi
= ARM_ABI_APCS
;
2776 case EF_ARM_EABI_VER4
:
2777 case EF_ARM_EABI_VER5
:
2778 arm_abi
= ARM_ABI_AAPCS
;
2779 /* EABI binaries default to VFP float ordering. */
2780 if (fp_model
== ARM_FLOAT_AUTO
)
2781 fp_model
= ARM_FLOAT_SOFT_VFP
;
2785 /* Leave it as "auto". */
2786 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
2791 if (fp_model
== ARM_FLOAT_AUTO
)
2793 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2795 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
2798 /* Leave it as "auto". Strictly speaking this case
2799 means FPA, but almost nobody uses that now, and
2800 many toolchains fail to set the appropriate bits
2801 for the floating-point model they use. */
2803 case EF_ARM_SOFT_FLOAT
:
2804 fp_model
= ARM_FLOAT_SOFT_FPA
;
2806 case EF_ARM_VFP_FLOAT
:
2807 fp_model
= ARM_FLOAT_VFP
;
2809 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
2810 fp_model
= ARM_FLOAT_SOFT_VFP
;
2817 /* Leave it as "auto". */
2822 /* Now that we have inferred any architecture settings that we
2823 can, try to inherit from the last ARM ABI. */
2826 if (arm_abi
== ARM_ABI_AUTO
)
2827 arm_abi
= gdbarch_tdep (arches
->gdbarch
)->arm_abi
;
2829 if (fp_model
== ARM_FLOAT_AUTO
)
2830 fp_model
= gdbarch_tdep (arches
->gdbarch
)->fp_model
;
2834 /* There was no prior ARM architecture; fill in default values. */
2836 if (arm_abi
== ARM_ABI_AUTO
)
2837 arm_abi
= ARM_ABI_APCS
;
2839 /* We used to default to FPA for generic ARM, but almost nobody
2840 uses that now, and we now provide a way for the user to force
2841 the model. So default to the most useful variant. */
2842 if (fp_model
== ARM_FLOAT_AUTO
)
2843 fp_model
= ARM_FLOAT_SOFT_FPA
;
2846 /* If there is already a candidate, use it. */
2847 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
2849 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
2851 if (arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
2854 if (fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
2857 /* Found a match. */
2861 if (best_arch
!= NULL
)
2863 if (tdesc_data
!= NULL
)
2864 tdesc_data_cleanup (tdesc_data
);
2865 return best_arch
->gdbarch
;
2868 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
2869 gdbarch
= gdbarch_alloc (&info
, tdep
);
2871 /* Record additional information about the architecture we are defining.
2872 These are gdbarch discriminators, like the OSABI. */
2873 tdep
->arm_abi
= arm_abi
;
2874 tdep
->fp_model
= fp_model
;
2875 tdep
->have_fpa_registers
= have_fpa_registers
;
2878 switch (info
.byte_order
)
2880 case BFD_ENDIAN_BIG
:
2881 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
2882 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
2883 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
2884 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
2888 case BFD_ENDIAN_LITTLE
:
2889 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
2890 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
2891 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
2892 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
2897 internal_error (__FILE__
, __LINE__
,
2898 _("arm_gdbarch_init: bad byte order for float format"));
2901 /* On ARM targets char defaults to unsigned. */
2902 set_gdbarch_char_signed (gdbarch
, 0);
2904 /* This should be low enough for everything. */
2905 tdep
->lowest_pc
= 0x20;
2906 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
2908 /* The default, for both APCS and AAPCS, is to return small
2909 structures in registers. */
2910 tdep
->struct_return
= reg_struct_return
;
2912 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
2913 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
2915 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
2917 /* Frame handling. */
2918 set_gdbarch_unwind_dummy_id (gdbarch
, arm_unwind_dummy_id
);
2919 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
2920 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
2922 frame_base_set_default (gdbarch
, &arm_normal_base
);
2924 /* Address manipulation. */
2925 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
2926 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
2928 /* Advance PC across function entry code. */
2929 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
2931 /* Skip trampolines. */
2932 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
2934 /* The stack grows downward. */
2935 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2937 /* Breakpoint manipulation. */
2938 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
2940 /* Information about registers, etc. */
2941 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
2942 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
2943 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
2944 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
2945 set_gdbarch_register_type (gdbarch
, arm_register_type
);
2947 /* This "info float" is FPA-specific. Use the generic version if we
2949 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
2950 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
2952 /* Internal <-> external register number maps. */
2953 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
2954 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
2955 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
2957 /* Integer registers are 4 bytes. */
2958 set_gdbarch_deprecated_register_size (gdbarch
, 4);
2959 set_gdbarch_register_name (gdbarch
, arm_register_name
);
2961 /* Returning results. */
2962 set_gdbarch_return_value (gdbarch
, arm_return_value
);
2965 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
2967 /* Minsymbol frobbing. */
2968 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
2969 set_gdbarch_coff_make_msymbol_special (gdbarch
,
2970 arm_coff_make_msymbol_special
);
2972 /* Virtual tables. */
2973 set_gdbarch_vbit_in_delta (gdbarch
, 1);
2975 /* Hook in the ABI-specific overrides, if they have been registered. */
2976 gdbarch_init_osabi (info
, gdbarch
);
2978 /* Add some default predicates. */
2979 frame_unwind_append_sniffer (gdbarch
, arm_stub_unwind_sniffer
);
2980 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
2981 frame_unwind_append_sniffer (gdbarch
, arm_prologue_unwind_sniffer
);
2983 /* Now we have tuned the configuration, set a few final things,
2984 based on what the OS ABI has told us. */
2986 if (tdep
->jb_pc
>= 0)
2987 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
2989 /* Floating point sizes and format. */
2990 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
2991 if (fp_model
== ARM_FLOAT_SOFT_FPA
|| fp_model
== ARM_FLOAT_FPA
)
2993 set_gdbarch_double_format
2994 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
2995 set_gdbarch_long_double_format
2996 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
3000 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
3001 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
3005 tdesc_use_registers (gdbarch
, tdesc_data
);
3007 /* Add standard register aliases. We add aliases even for those
3008 nanes which are used by the current architecture - it's simpler,
3009 and does no harm, since nothing ever lists user registers. */
3010 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
3011 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
3012 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
3018 arm_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
3020 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3025 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
3026 (unsigned long) tdep
->lowest_pc
);
3029 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
3032 _initialize_arm_tdep (void)
3034 struct ui_file
*stb
;
3036 struct cmd_list_element
*new_set
, *new_show
;
3037 const char *setname
;
3038 const char *setdesc
;
3039 const char *const *regnames
;
3041 static char *helptext
;
3042 char regdesc
[1024], *rdptr
= regdesc
;
3043 size_t rest
= sizeof (regdesc
);
3045 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
3047 /* Register an ELF OS ABI sniffer for ARM binaries. */
3048 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
3049 bfd_target_elf_flavour
,
3050 arm_elf_osabi_sniffer
);
3052 /* Get the number of possible sets of register names defined in opcodes. */
3053 num_disassembly_options
= get_arm_regname_num_options ();
3055 /* Add root prefix command for all "set arm"/"show arm" commands. */
3056 add_prefix_cmd ("arm", no_class
, set_arm_command
,
3057 _("Various ARM-specific commands."),
3058 &setarmcmdlist
, "set arm ", 0, &setlist
);
3060 add_prefix_cmd ("arm", no_class
, show_arm_command
,
3061 _("Various ARM-specific commands."),
3062 &showarmcmdlist
, "show arm ", 0, &showlist
);
3064 /* Sync the opcode insn printer with our register viewer. */
3065 parse_arm_disassembler_option ("reg-names-std");
3067 /* Initialize the array that will be passed to
3068 add_setshow_enum_cmd(). */
3069 valid_disassembly_styles
3070 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
3071 for (i
= 0; i
< num_disassembly_options
; i
++)
3073 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
3074 valid_disassembly_styles
[i
] = setname
;
3075 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
3078 /* When we find the default names, tell the disassembler to use
3080 if (!strcmp (setname
, "std"))
3082 disassembly_style
= setname
;
3083 set_arm_regname_option (i
);
3086 /* Mark the end of valid options. */
3087 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
3089 /* Create the help text. */
3090 stb
= mem_fileopen ();
3091 fprintf_unfiltered (stb
, "%s%s%s",
3092 _("The valid values are:\n"),
3094 _("The default is \"std\"."));
3095 helptext
= ui_file_xstrdup (stb
, &length
);
3096 ui_file_delete (stb
);
3098 add_setshow_enum_cmd("disassembler", no_class
,
3099 valid_disassembly_styles
, &disassembly_style
,
3100 _("Set the disassembly style."),
3101 _("Show the disassembly style."),
3103 set_disassembly_style_sfunc
,
3104 NULL
, /* FIXME: i18n: The disassembly style is \"%s\". */
3105 &setarmcmdlist
, &showarmcmdlist
);
3107 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
3108 _("Set usage of ARM 32-bit mode."),
3109 _("Show usage of ARM 32-bit mode."),
3110 _("When off, a 26-bit PC will be used."),
3112 NULL
, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
3113 &setarmcmdlist
, &showarmcmdlist
);
3115 /* Add a command to allow the user to force the FPU model. */
3116 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
3117 _("Set the floating point type."),
3118 _("Show the floating point type."),
3119 _("auto - Determine the FP typefrom the OS-ABI.\n\
3120 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
3121 fpa - FPA co-processor (GCC compiled).\n\
3122 softvfp - Software FP with pure-endian doubles.\n\
3123 vfp - VFP co-processor."),
3124 set_fp_model_sfunc
, show_fp_model
,
3125 &setarmcmdlist
, &showarmcmdlist
);
3127 /* Add a command to allow the user to force the ABI. */
3128 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
3131 NULL
, arm_set_abi
, arm_show_abi
,
3132 &setarmcmdlist
, &showarmcmdlist
);
3134 /* Debugging flag. */
3135 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
3136 _("Set ARM debugging."),
3137 _("Show ARM debugging."),
3138 _("When on, arm-specific debugging is enabled."),
3140 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
3141 &setdebuglist
, &showdebuglist
);