1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include <ctype.h> /* XXX for isupper () */
28 #include "gdb_string.h"
29 #include "dis-asm.h" /* For register styles. */
33 #include "arch-utils.h"
35 #include "frame-unwind.h"
36 #include "frame-base.h"
37 #include "trad-frame.h"
39 #include "dwarf2-frame.h"
41 #include "prologue-value.h"
42 #include "target-descriptions.h"
43 #include "user-regs.h"
46 #include "gdb/sim-arm.h"
49 #include "coff/internal.h"
52 #include "gdb_assert.h"
56 /* Macros for setting and testing a bit in a minimal symbol that marks
57 it as Thumb function. The MSB of the minimal symbol's "info" field
58 is used for this purpose.
60 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
61 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
63 #define MSYMBOL_SET_SPECIAL(msym) \
64 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
67 #define MSYMBOL_IS_SPECIAL(msym) \
68 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
70 /* The list of available "set arm ..." and "show arm ..." commands. */
71 static struct cmd_list_element
*setarmcmdlist
= NULL
;
72 static struct cmd_list_element
*showarmcmdlist
= NULL
;
74 /* The type of floating-point to use. Keep this in sync with enum
75 arm_float_model, and the help string in _initialize_arm_tdep. */
76 static const char *fp_model_strings
[] =
86 /* A variable that can be configured by the user. */
87 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
88 static const char *current_fp_model
= "auto";
90 /* The ABI to use. Keep this in sync with arm_abi_kind. */
91 static const char *arm_abi_strings
[] =
99 /* A variable that can be configured by the user. */
100 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
101 static const char *arm_abi_string
= "auto";
103 /* Number of different reg name sets (options). */
104 static int num_disassembly_options
;
106 /* The standard register names, and all the valid aliases for them. */
111 } arm_register_aliases
[] = {
112 /* Basic register numbers. */
129 /* Synonyms (argument and variable registers). */
142 /* Other platform-specific names for r9. */
150 /* Names used by GCC (not listed in the ARM EABI). */
153 /* A special name from the older ATPCS. */
157 static const char *const arm_register_names
[] =
158 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
159 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
160 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
161 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
162 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
163 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
164 "fps", "cpsr" }; /* 24 25 */
166 /* Valid register name styles. */
167 static const char **valid_disassembly_styles
;
169 /* Disassembly style to use. Default to "std" register names. */
170 static const char *disassembly_style
;
172 /* This is used to keep the bfd arch_info in sync with the disassembly
174 static void set_disassembly_style_sfunc(char *, int,
175 struct cmd_list_element
*);
176 static void set_disassembly_style (void);
178 static void convert_from_extended (const struct floatformat
*, const void *,
180 static void convert_to_extended (const struct floatformat
*, void *,
183 struct arm_prologue_cache
185 /* The stack pointer at the time this frame was created; i.e. the
186 caller's stack pointer when this function was called. It is used
187 to identify this frame. */
190 /* The frame base for this frame is just prev_sp + frame offset -
191 frame size. FRAMESIZE is the size of this stack frame, and
192 FRAMEOFFSET if the initial offset from the stack pointer (this
193 frame's stack pointer, not PREV_SP) to the frame base. */
198 /* The register used to hold the frame pointer for this frame. */
201 /* Saved register offsets. */
202 struct trad_frame_saved_reg
*saved_regs
;
205 /* Addresses for calling Thumb functions have the bit 0 set.
206 Here are some macros to test, set, or clear bit 0 of addresses. */
207 #define IS_THUMB_ADDR(addr) ((addr) & 1)
208 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
209 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
211 /* Set to true if the 32-bit mode is in use. */
215 /* Determine if the program counter specified in MEMADDR is in a Thumb
219 arm_pc_is_thumb (CORE_ADDR memaddr
)
221 struct minimal_symbol
*sym
;
223 /* If bit 0 of the address is set, assume this is a Thumb address. */
224 if (IS_THUMB_ADDR (memaddr
))
227 /* Thumb functions have a "special" bit set in minimal symbols. */
228 sym
= lookup_minimal_symbol_by_pc (memaddr
);
231 return (MSYMBOL_IS_SPECIAL (sym
));
239 /* Remove useless bits from addresses in a running program. */
241 arm_addr_bits_remove (CORE_ADDR val
)
244 return (val
& (arm_pc_is_thumb (val
) ? 0xfffffffe : 0xfffffffc));
246 return (val
& 0x03fffffc);
249 /* When reading symbols, we need to zap the low bit of the address,
250 which may be set to 1 for Thumb functions. */
252 arm_smash_text_address (CORE_ADDR val
)
257 /* Analyze a Thumb prologue, looking for a recognizable stack frame
258 and frame pointer. Scan until we encounter a store that could
259 clobber the stack frame unexpectedly, or an unknown instruction. */
262 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
263 CORE_ADDR start
, CORE_ADDR limit
,
264 struct arm_prologue_cache
*cache
)
268 struct pv_area
*stack
;
269 struct cleanup
*back_to
;
272 for (i
= 0; i
< 16; i
++)
273 regs
[i
] = pv_register (i
, 0);
274 stack
= make_pv_area (ARM_SP_REGNUM
);
275 back_to
= make_cleanup_free_pv_area (stack
);
277 /* The call instruction saved PC in LR, and the current PC is not
278 interesting. Due to this file's conventions, we want the value
279 of LR at this function's entry, not at the call site, so we do
280 not record the save of the PC - when the ARM prologue analyzer
281 has also been converted to the pv mechanism, we could record the
282 save here and remove the hack in prev_register. */
283 regs
[ARM_PC_REGNUM
] = pv_unknown ();
285 while (start
< limit
)
289 insn
= read_memory_unsigned_integer (start
, 2);
291 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
297 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
298 whether to save LR (R14). */
299 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
301 /* Calculate offsets of saved R0-R7 and LR. */
302 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
303 if (mask
& (1 << regno
))
305 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
311 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
313 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
319 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
322 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
323 if (insn
& 0x80) /* Check for SUB. */
324 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
327 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
330 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
331 regs
[THUMB_FP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
333 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
335 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
336 int src_reg
= (insn
& 0x78) >> 3;
337 regs
[dst_reg
] = regs
[src_reg
];
339 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
341 /* Handle stores to the stack. Normally pushes are used,
342 but with GCC -mtpcs-frame, there may be other stores
343 in the prologue to create the frame. */
344 int regno
= (insn
>> 8) & 0x7;
347 offset
= (insn
& 0xff) << 2;
348 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
350 if (pv_area_store_would_trash (stack
, addr
))
353 pv_area_store (stack
, addr
, 4, regs
[regno
]);
357 /* We don't know what this instruction is. We're finished
358 scanning. NOTE: Recognizing more safe-to-ignore
359 instructions here will improve support for optimized
369 do_cleanups (back_to
);
373 /* frameoffset is unused for this unwinder. */
374 cache
->frameoffset
= 0;
376 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
378 /* Frame pointer is fp. Frame size is constant. */
379 cache
->framereg
= ARM_FP_REGNUM
;
380 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
382 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
384 /* Frame pointer is r7. Frame size is constant. */
385 cache
->framereg
= THUMB_FP_REGNUM
;
386 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
388 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
390 /* Try the stack pointer... this is a bit desperate. */
391 cache
->framereg
= ARM_SP_REGNUM
;
392 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
396 /* We're just out of luck. We don't know where the frame is. */
397 cache
->framereg
= -1;
398 cache
->framesize
= 0;
401 for (i
= 0; i
< 16; i
++)
402 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
403 cache
->saved_regs
[i
].addr
= offset
;
405 do_cleanups (back_to
);
409 /* Advance the PC across any function entry prologue instructions to
410 reach some "real" code.
412 The APCS (ARM Procedure Call Standard) defines the following
416 [stmfd sp!, {a1,a2,a3,a4}]
417 stmfd sp!, {...,fp,ip,lr,pc}
418 [stfe f7, [sp, #-12]!]
419 [stfe f6, [sp, #-12]!]
420 [stfe f5, [sp, #-12]!]
421 [stfe f4, [sp, #-12]!]
422 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
425 arm_skip_prologue (CORE_ADDR pc
)
429 CORE_ADDR func_addr
, func_end
= 0;
431 struct symtab_and_line sal
;
433 /* If we're in a dummy frame, don't even try to skip the prologue. */
434 if (deprecated_pc_in_call_dummy (pc
))
437 /* See what the symbol table says. */
439 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
443 /* Found a function. */
444 sym
= lookup_symbol (func_name
, NULL
, VAR_DOMAIN
, NULL
, NULL
);
445 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
447 /* Don't use this trick for assembly source files. */
448 sal
= find_pc_line (func_addr
, 0);
449 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
454 /* Can't find the prologue end in the symbol table, try it the hard way
455 by disassembling the instructions. */
457 /* Like arm_scan_prologue, stop no later than pc + 64. */
458 if (func_end
== 0 || func_end
> pc
+ 64)
461 /* Check if this is Thumb code. */
462 if (arm_pc_is_thumb (pc
))
463 return thumb_analyze_prologue (current_gdbarch
, pc
, func_end
, NULL
);
465 for (skip_pc
= pc
; skip_pc
< func_end
; skip_pc
+= 4)
467 inst
= read_memory_unsigned_integer (skip_pc
, 4);
469 /* "mov ip, sp" is no longer a required part of the prologue. */
470 if (inst
== 0xe1a0c00d) /* mov ip, sp */
473 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
476 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
479 /* Some prologues begin with "str lr, [sp, #-4]!". */
480 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
483 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
486 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
489 /* Any insns after this point may float into the code, if it makes
490 for better instruction scheduling, so we skip them only if we
491 find them, but still consider the function to be frame-ful. */
493 /* We may have either one sfmfd instruction here, or several stfe
494 insns, depending on the version of floating point code we
496 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
499 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
502 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
505 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
508 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
509 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
510 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
513 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
514 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
515 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
518 /* Un-recognized instruction; stop scanning. */
522 return skip_pc
; /* End of prologue */
526 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
527 This function decodes a Thumb function prologue to determine:
528 1) the size of the stack frame
529 2) which registers are saved on it
530 3) the offsets of saved regs
531 4) the offset from the stack pointer to the frame pointer
533 A typical Thumb function prologue would create this stack frame
534 (offsets relative to FP)
535 old SP -> 24 stack parameters
538 R7 -> 0 local variables (16 bytes)
539 SP -> -12 additional stack space (12 bytes)
540 The frame size would thus be 36 bytes, and the frame offset would be
541 12 bytes. The frame register is R7.
543 The comments for thumb_skip_prolog() describe the algorithm we use
544 to detect the end of the prolog. */
548 thumb_scan_prologue (CORE_ADDR prev_pc
, struct arm_prologue_cache
*cache
)
550 CORE_ADDR prologue_start
;
551 CORE_ADDR prologue_end
;
552 CORE_ADDR current_pc
;
553 /* Which register has been copied to register n? */
556 bit 0 - push { rlist }
557 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
558 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
563 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
565 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
567 if (sal
.line
== 0) /* no line info, use current PC */
568 prologue_end
= prev_pc
;
569 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
570 prologue_end
= sal
.end
; /* (probably means no prologue) */
573 /* We're in the boondocks: we have no idea where the start of the
577 prologue_end
= min (prologue_end
, prev_pc
);
579 thumb_analyze_prologue (current_gdbarch
, prologue_start
, prologue_end
,
583 /* This function decodes an ARM function prologue to determine:
584 1) the size of the stack frame
585 2) which registers are saved on it
586 3) the offsets of saved regs
587 4) the offset from the stack pointer to the frame pointer
588 This information is stored in the "extra" fields of the frame_info.
590 There are two basic forms for the ARM prologue. The fixed argument
591 function call will look like:
594 stmfd sp!, {fp, ip, lr, pc}
598 Which would create this stack frame (offsets relative to FP):
599 IP -> 4 (caller's stack)
600 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
601 -4 LR (return address in caller)
602 -8 IP (copy of caller's SP)
604 SP -> -28 Local variables
606 The frame size would thus be 32 bytes, and the frame offset would be
607 28 bytes. The stmfd call can also save any of the vN registers it
608 plans to use, which increases the frame size accordingly.
610 Note: The stored PC is 8 off of the STMFD instruction that stored it
611 because the ARM Store instructions always store PC + 8 when you read
614 A variable argument function call will look like:
617 stmfd sp!, {a1, a2, a3, a4}
618 stmfd sp!, {fp, ip, lr, pc}
621 Which would create this stack frame (offsets relative to FP):
622 IP -> 20 (caller's stack)
627 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
628 -4 LR (return address in caller)
629 -8 IP (copy of caller's SP)
631 SP -> -28 Local variables
633 The frame size would thus be 48 bytes, and the frame offset would be
636 There is another potential complication, which is that the optimizer
637 will try to separate the store of fp in the "stmfd" instruction from
638 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
639 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
641 Also, note, the original version of the ARM toolchain claimed that there
644 instruction at the end of the prologue. I have never seen GCC produce
645 this, and the ARM docs don't mention it. We still test for it below in
651 arm_scan_prologue (struct frame_info
*next_frame
, struct arm_prologue_cache
*cache
)
653 int regno
, sp_offset
, fp_offset
, ip_offset
;
654 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
655 CORE_ADDR prev_pc
= frame_pc_unwind (next_frame
);
657 /* Assume there is no frame until proven otherwise. */
658 cache
->framereg
= ARM_SP_REGNUM
;
659 cache
->framesize
= 0;
660 cache
->frameoffset
= 0;
662 /* Check for Thumb prologue. */
663 if (arm_pc_is_thumb (prev_pc
))
665 thumb_scan_prologue (prev_pc
, cache
);
669 /* Find the function prologue. If we can't find the function in
670 the symbol table, peek in the stack frame to find the PC. */
671 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
673 /* One way to find the end of the prologue (which works well
674 for unoptimized code) is to do the following:
676 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
679 prologue_end = prev_pc;
680 else if (sal.end < prologue_end)
681 prologue_end = sal.end;
683 This mechanism is very accurate so long as the optimizer
684 doesn't move any instructions from the function body into the
685 prologue. If this happens, sal.end will be the last
686 instruction in the first hunk of prologue code just before
687 the first instruction that the scheduler has moved from
688 the body to the prologue.
690 In order to make sure that we scan all of the prologue
691 instructions, we use a slightly less accurate mechanism which
692 may scan more than necessary. To help compensate for this
693 lack of accuracy, the prologue scanning loop below contains
694 several clauses which'll cause the loop to terminate early if
695 an implausible prologue instruction is encountered.
701 is a suitable endpoint since it accounts for the largest
702 possible prologue plus up to five instructions inserted by
705 if (prologue_end
> prologue_start
+ 64)
707 prologue_end
= prologue_start
+ 64; /* See above. */
712 /* We have no symbol information. Our only option is to assume this
713 function has a standard stack frame and the normal frame register.
714 Then, we can find the value of our frame pointer on entrance to
715 the callee (or at the present moment if this is the innermost frame).
716 The value stored there should be the address of the stmfd + 8. */
718 LONGEST return_value
;
720 frame_loc
= frame_unwind_register_unsigned (next_frame
, ARM_FP_REGNUM
);
721 if (!safe_read_memory_integer (frame_loc
, 4, &return_value
))
725 prologue_start
= gdbarch_addr_bits_remove
726 (current_gdbarch
, return_value
) - 8;
727 prologue_end
= prologue_start
+ 64; /* See above. */
731 if (prev_pc
< prologue_end
)
732 prologue_end
= prev_pc
;
734 /* Now search the prologue looking for instructions that set up the
735 frame pointer, adjust the stack pointer, and save registers.
737 Be careful, however, and if it doesn't look like a prologue,
738 don't try to scan it. If, for instance, a frameless function
739 begins with stmfd sp!, then we will tell ourselves there is
740 a frame, which will confuse stack traceback, as well as "finish"
741 and other operations that rely on a knowledge of the stack
744 In the APCS, the prologue should start with "mov ip, sp" so
745 if we don't see this as the first insn, we will stop.
747 [Note: This doesn't seem to be true any longer, so it's now an
748 optional part of the prologue. - Kevin Buettner, 2001-11-20]
750 [Note further: The "mov ip,sp" only seems to be missing in
751 frameless functions at optimization level "-O2" or above,
752 in which case it is often (but not always) replaced by
753 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
755 sp_offset
= fp_offset
= ip_offset
= 0;
757 for (current_pc
= prologue_start
;
758 current_pc
< prologue_end
;
761 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
763 if (insn
== 0xe1a0c00d) /* mov ip, sp */
768 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
770 unsigned imm
= insn
& 0xff; /* immediate value */
771 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
772 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
776 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
778 unsigned imm
= insn
& 0xff; /* immediate value */
779 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
780 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
784 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
787 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= sp_offset
;
790 else if ((insn
& 0xffff0000) == 0xe92d0000)
791 /* stmfd sp!, {..., fp, ip, lr, pc}
793 stmfd sp!, {a1, a2, a3, a4} */
795 int mask
= insn
& 0xffff;
797 /* Calculate offsets of saved registers. */
798 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
799 if (mask
& (1 << regno
))
802 cache
->saved_regs
[regno
].addr
= sp_offset
;
805 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
806 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
807 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
809 /* No need to add this to saved_regs -- it's just an arg reg. */
812 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
813 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
814 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
816 /* No need to add this to saved_regs -- it's just an arg reg. */
819 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
821 unsigned imm
= insn
& 0xff; /* immediate value */
822 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
823 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
824 fp_offset
= -imm
+ ip_offset
;
825 cache
->framereg
= ARM_FP_REGNUM
;
827 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
829 unsigned imm
= insn
& 0xff; /* immediate value */
830 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
831 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
834 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
835 && gdbarch_tdep (current_gdbarch
)->have_fpa_registers
)
838 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
839 cache
->saved_regs
[regno
].addr
= sp_offset
;
841 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
842 && gdbarch_tdep (current_gdbarch
)->have_fpa_registers
)
845 unsigned int fp_start_reg
, fp_bound_reg
;
847 if ((insn
& 0x800) == 0x800) /* N0 is set */
849 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
856 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
862 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
863 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
864 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
867 cache
->saved_regs
[fp_start_reg
++].addr
= sp_offset
;
870 else if ((insn
& 0xf0000000) != 0xe0000000)
871 break; /* Condition not true, exit early */
872 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
873 break; /* Don't scan past a block load */
875 /* The optimizer might shove anything into the prologue,
876 so we just skip what we don't recognize. */
880 /* The frame size is just the negative of the offset (from the
881 original SP) of the last thing thing we pushed on the stack.
882 The frame offset is [new FP] - [new SP]. */
883 cache
->framesize
= -sp_offset
;
884 if (cache
->framereg
== ARM_FP_REGNUM
)
885 cache
->frameoffset
= fp_offset
- sp_offset
;
887 cache
->frameoffset
= 0;
890 static struct arm_prologue_cache
*
891 arm_make_prologue_cache (struct frame_info
*next_frame
)
894 struct arm_prologue_cache
*cache
;
895 CORE_ADDR unwound_fp
;
897 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
898 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
900 arm_scan_prologue (next_frame
, cache
);
902 unwound_fp
= frame_unwind_register_unsigned (next_frame
, cache
->framereg
);
906 cache
->prev_sp
= unwound_fp
+ cache
->framesize
- cache
->frameoffset
;
908 /* Calculate actual addresses of saved registers using offsets
909 determined by arm_scan_prologue. */
910 for (reg
= 0; reg
< gdbarch_num_regs (current_gdbarch
); reg
++)
911 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
912 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
917 /* Our frame ID for a normal frame is the current function's starting PC
918 and the caller's SP when we were called. */
921 arm_prologue_this_id (struct frame_info
*next_frame
,
923 struct frame_id
*this_id
)
925 struct arm_prologue_cache
*cache
;
929 if (*this_cache
== NULL
)
930 *this_cache
= arm_make_prologue_cache (next_frame
);
933 func
= frame_func_unwind (next_frame
, NORMAL_FRAME
);
935 /* This is meant to halt the backtrace at "_start". Make sure we
936 don't halt it at a generic dummy frame. */
937 if (func
<= LOWEST_PC
)
940 /* If we've hit a wall, stop. */
941 if (cache
->prev_sp
== 0)
944 id
= frame_id_build (cache
->prev_sp
, func
);
949 arm_prologue_prev_register (struct frame_info
*next_frame
,
953 enum lval_type
*lvalp
,
958 struct arm_prologue_cache
*cache
;
960 if (*this_cache
== NULL
)
961 *this_cache
= arm_make_prologue_cache (next_frame
);
964 /* If we are asked to unwind the PC, then we need to return the LR
965 instead. The saved value of PC points into this frame's
966 prologue, not the next frame's resume location. */
967 if (prev_regnum
== ARM_PC_REGNUM
)
968 prev_regnum
= ARM_LR_REGNUM
;
970 /* SP is generally not saved to the stack, but this frame is
971 identified by NEXT_FRAME's stack pointer at the time of the call.
972 The value was already reconstructed into PREV_SP. */
973 if (prev_regnum
== ARM_SP_REGNUM
)
977 store_unsigned_integer (valuep
, 4, cache
->prev_sp
);
981 trad_frame_get_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
982 optimized
, lvalp
, addrp
, realnump
, valuep
);
985 struct frame_unwind arm_prologue_unwind
= {
987 arm_prologue_this_id
,
988 arm_prologue_prev_register
991 static const struct frame_unwind
*
992 arm_prologue_unwind_sniffer (struct frame_info
*next_frame
)
994 return &arm_prologue_unwind
;
997 static struct arm_prologue_cache
*
998 arm_make_stub_cache (struct frame_info
*next_frame
)
1001 struct arm_prologue_cache
*cache
;
1002 CORE_ADDR unwound_fp
;
1004 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1005 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1007 cache
->prev_sp
= frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
);
1012 /* Our frame ID for a stub frame is the current SP and LR. */
1015 arm_stub_this_id (struct frame_info
*next_frame
,
1017 struct frame_id
*this_id
)
1019 struct arm_prologue_cache
*cache
;
1021 if (*this_cache
== NULL
)
1022 *this_cache
= arm_make_stub_cache (next_frame
);
1023 cache
= *this_cache
;
1025 *this_id
= frame_id_build (cache
->prev_sp
,
1026 frame_pc_unwind (next_frame
));
1029 struct frame_unwind arm_stub_unwind
= {
1032 arm_prologue_prev_register
1035 static const struct frame_unwind
*
1036 arm_stub_unwind_sniffer (struct frame_info
*next_frame
)
1038 CORE_ADDR addr_in_block
;
1041 addr_in_block
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1042 if (in_plt_section (addr_in_block
, NULL
)
1043 || target_read_memory (frame_pc_unwind (next_frame
), dummy
, 4) != 0)
1044 return &arm_stub_unwind
;
1050 arm_normal_frame_base (struct frame_info
*next_frame
, void **this_cache
)
1052 struct arm_prologue_cache
*cache
;
1054 if (*this_cache
== NULL
)
1055 *this_cache
= arm_make_prologue_cache (next_frame
);
1056 cache
= *this_cache
;
1058 return cache
->prev_sp
+ cache
->frameoffset
- cache
->framesize
;
1061 struct frame_base arm_normal_base
= {
1062 &arm_prologue_unwind
,
1063 arm_normal_frame_base
,
1064 arm_normal_frame_base
,
1065 arm_normal_frame_base
1068 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1069 dummy frame. The frame ID's base needs to match the TOS value
1070 saved by save_dummy_frame_tos() and returned from
1071 arm_push_dummy_call, and the PC needs to match the dummy frame's
1074 static struct frame_id
1075 arm_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1077 return frame_id_build (frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
),
1078 frame_pc_unwind (next_frame
));
1081 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1082 be used to construct the previous frame's ID, after looking up the
1083 containing function). */
1086 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1089 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1090 return arm_addr_bits_remove (pc
);
1094 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1096 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1099 /* When arguments must be pushed onto the stack, they go on in reverse
1100 order. The code below implements a FILO (stack) to do this. */
1105 struct stack_item
*prev
;
1109 static struct stack_item
*
1110 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1112 struct stack_item
*si
;
1113 si
= xmalloc (sizeof (struct stack_item
));
1114 si
->data
= xmalloc (len
);
1117 memcpy (si
->data
, contents
, len
);
1121 static struct stack_item
*
1122 pop_stack_item (struct stack_item
*si
)
1124 struct stack_item
*dead
= si
;
1132 /* Return the alignment (in bytes) of the given type. */
1135 arm_type_align (struct type
*t
)
1141 t
= check_typedef (t
);
1142 switch (TYPE_CODE (t
))
1145 /* Should never happen. */
1146 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1150 case TYPE_CODE_ENUM
:
1154 case TYPE_CODE_RANGE
:
1155 case TYPE_CODE_BITSTRING
:
1157 case TYPE_CODE_CHAR
:
1158 case TYPE_CODE_BOOL
:
1159 return TYPE_LENGTH (t
);
1161 case TYPE_CODE_ARRAY
:
1162 case TYPE_CODE_COMPLEX
:
1163 /* TODO: What about vector types? */
1164 return arm_type_align (TYPE_TARGET_TYPE (t
));
1166 case TYPE_CODE_STRUCT
:
1167 case TYPE_CODE_UNION
:
1169 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1171 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
1179 /* We currently only support passing parameters in integer registers. This
1180 conforms with GCC's default model. Several other variants exist and
1181 we should probably support some of them based on the selected ABI. */
1184 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1185 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1186 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1187 CORE_ADDR struct_addr
)
1192 struct stack_item
*si
= NULL
;
1194 /* Set the return address. For the ARM, the return breakpoint is
1195 always at BP_ADDR. */
1196 /* XXX Fix for Thumb. */
1197 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1199 /* Walk through the list of args and determine how large a temporary
1200 stack is required. Need to take care here as structs may be
1201 passed on the stack, and we have to to push them. */
1204 argreg
= ARM_A1_REGNUM
;
1207 /* The struct_return pointer occupies the first parameter
1208 passing register. */
1212 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = 0x%s\n",
1213 gdbarch_register_name (current_gdbarch
, argreg
),
1214 paddr (struct_addr
));
1215 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1219 for (argnum
= 0; argnum
< nargs
; argnum
++)
1222 struct type
*arg_type
;
1223 struct type
*target_type
;
1224 enum type_code typecode
;
1228 arg_type
= check_typedef (value_type (args
[argnum
]));
1229 len
= TYPE_LENGTH (arg_type
);
1230 target_type
= TYPE_TARGET_TYPE (arg_type
);
1231 typecode
= TYPE_CODE (arg_type
);
1232 val
= value_contents_writeable (args
[argnum
]);
1234 align
= arm_type_align (arg_type
);
1235 /* Round alignment up to a whole number of words. */
1236 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
1237 /* Different ABIs have different maximum alignments. */
1238 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
1240 /* The APCS ABI only requires word alignment. */
1241 align
= INT_REGISTER_SIZE
;
1245 /* The AAPCS requires at most doubleword alignment. */
1246 if (align
> INT_REGISTER_SIZE
* 2)
1247 align
= INT_REGISTER_SIZE
* 2;
1250 /* Push stack padding for dowubleword alignment. */
1251 if (nstack
& (align
- 1))
1253 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1254 nstack
+= INT_REGISTER_SIZE
;
1257 /* Doubleword aligned quantities must go in even register pairs. */
1258 if (argreg
<= ARM_LAST_ARG_REGNUM
1259 && align
> INT_REGISTER_SIZE
1263 /* If the argument is a pointer to a function, and it is a
1264 Thumb function, create a LOCAL copy of the value and set
1265 the THUMB bit in it. */
1266 if (TYPE_CODE_PTR
== typecode
1267 && target_type
!= NULL
1268 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1270 CORE_ADDR regval
= extract_unsigned_integer (val
, len
);
1271 if (arm_pc_is_thumb (regval
))
1274 store_unsigned_integer (val
, len
, MAKE_THUMB_ADDR (regval
));
1278 /* Copy the argument to general registers or the stack in
1279 register-sized pieces. Large arguments are split between
1280 registers and stack. */
1283 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
1285 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1287 /* The argument is being passed in a general purpose
1289 CORE_ADDR regval
= extract_unsigned_integer (val
, partial_len
);
1290 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1291 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
1293 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1295 gdbarch_register_name
1296 (current_gdbarch
, argreg
),
1297 phex (regval
, INT_REGISTER_SIZE
));
1298 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1303 /* Push the arguments onto the stack. */
1305 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1307 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1308 nstack
+= INT_REGISTER_SIZE
;
1315 /* If we have an odd number of words to push, then decrement the stack
1316 by one word now, so first stack argument will be dword aligned. */
1323 write_memory (sp
, si
->data
, si
->len
);
1324 si
= pop_stack_item (si
);
1327 /* Finally, update teh SP register. */
1328 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1334 /* Always align the frame to an 8-byte boundary. This is required on
1335 some platforms and harmless on the rest. */
1338 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1340 /* Align the stack to eight bytes. */
1341 return sp
& ~ (CORE_ADDR
) 7;
1345 print_fpu_flags (int flags
)
1347 if (flags
& (1 << 0))
1348 fputs ("IVO ", stdout
);
1349 if (flags
& (1 << 1))
1350 fputs ("DVZ ", stdout
);
1351 if (flags
& (1 << 2))
1352 fputs ("OFL ", stdout
);
1353 if (flags
& (1 << 3))
1354 fputs ("UFL ", stdout
);
1355 if (flags
& (1 << 4))
1356 fputs ("INX ", stdout
);
1360 /* Print interesting information about the floating point processor
1361 (if present) or emulator. */
1363 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1364 struct frame_info
*frame
, const char *args
)
1366 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
1369 type
= (status
>> 24) & 127;
1370 if (status
& (1 << 31))
1371 printf (_("Hardware FPU type %d\n"), type
);
1373 printf (_("Software FPU type %d\n"), type
);
1374 /* i18n: [floating point unit] mask */
1375 fputs (_("mask: "), stdout
);
1376 print_fpu_flags (status
>> 16);
1377 /* i18n: [floating point unit] flags */
1378 fputs (_("flags: "), stdout
);
1379 print_fpu_flags (status
);
1382 /* Return the GDB type object for the "standard" data type of data in
1385 static struct type
*
1386 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
1388 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1389 return builtin_type_arm_ext
;
1390 else if (regnum
== ARM_SP_REGNUM
)
1391 return builtin_type_void_data_ptr
;
1392 else if (regnum
== ARM_PC_REGNUM
)
1393 return builtin_type_void_func_ptr
;
1394 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
1395 /* These registers are only supported on targets which supply
1396 an XML description. */
1397 return builtin_type_int0
;
1399 return builtin_type_uint32
;
1402 /* Map a DWARF register REGNUM onto the appropriate GDB register
1406 arm_dwarf_reg_to_regnum (int reg
)
1408 /* Core integer regs. */
1409 if (reg
>= 0 && reg
<= 15)
1412 /* Legacy FPA encoding. These were once used in a way which
1413 overlapped with VFP register numbering, so their use is
1414 discouraged, but GDB doesn't support the ARM toolchain
1415 which used them for VFP. */
1416 if (reg
>= 16 && reg
<= 23)
1417 return ARM_F0_REGNUM
+ reg
- 16;
1419 /* New assignments for the FPA registers. */
1420 if (reg
>= 96 && reg
<= 103)
1421 return ARM_F0_REGNUM
+ reg
- 96;
1423 /* WMMX register assignments. */
1424 if (reg
>= 104 && reg
<= 111)
1425 return ARM_WCGR0_REGNUM
+ reg
- 104;
1427 if (reg
>= 112 && reg
<= 127)
1428 return ARM_WR0_REGNUM
+ reg
- 112;
1430 if (reg
>= 192 && reg
<= 199)
1431 return ARM_WC0_REGNUM
+ reg
- 192;
1436 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1438 arm_register_sim_regno (int regnum
)
1441 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (current_gdbarch
));
1443 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
1444 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
1446 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
1447 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
1449 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
1450 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
1452 if (reg
< NUM_GREGS
)
1453 return SIM_ARM_R0_REGNUM
+ reg
;
1456 if (reg
< NUM_FREGS
)
1457 return SIM_ARM_FP0_REGNUM
+ reg
;
1460 if (reg
< NUM_SREGS
)
1461 return SIM_ARM_FPS_REGNUM
+ reg
;
1464 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
1467 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1468 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1469 It is thought that this is is the floating-point register format on
1470 little-endian systems. */
1473 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
1477 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1478 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1480 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1482 floatformat_from_doublest (fmt
, &d
, dbl
);
1486 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
)
1489 floatformat_to_doublest (fmt
, ptr
, &d
);
1490 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1491 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1493 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1498 condition_true (unsigned long cond
, unsigned long status_reg
)
1500 if (cond
== INST_AL
|| cond
== INST_NV
)
1506 return ((status_reg
& FLAG_Z
) != 0);
1508 return ((status_reg
& FLAG_Z
) == 0);
1510 return ((status_reg
& FLAG_C
) != 0);
1512 return ((status_reg
& FLAG_C
) == 0);
1514 return ((status_reg
& FLAG_N
) != 0);
1516 return ((status_reg
& FLAG_N
) == 0);
1518 return ((status_reg
& FLAG_V
) != 0);
1520 return ((status_reg
& FLAG_V
) == 0);
1522 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1524 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1526 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1528 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1530 return (((status_reg
& FLAG_Z
) == 0) &&
1531 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1533 return (((status_reg
& FLAG_Z
) != 0) ||
1534 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1539 /* Support routines for single stepping. Calculate the next PC value. */
1540 #define submask(x) ((1L << ((x) + 1)) - 1)
1541 #define bit(obj,st) (((obj) >> (st)) & 1)
1542 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1543 #define sbits(obj,st,fn) \
1544 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1545 #define BranchDest(addr,instr) \
1546 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1549 static unsigned long
1550 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
1551 unsigned long pc_val
, unsigned long status_reg
)
1553 unsigned long res
, shift
;
1554 int rm
= bits (inst
, 0, 3);
1555 unsigned long shifttype
= bits (inst
, 5, 6);
1559 int rs
= bits (inst
, 8, 11);
1560 shift
= (rs
== 15 ? pc_val
+ 8
1561 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
1564 shift
= bits (inst
, 7, 11);
1567 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1568 + (bit (inst
, 4) ? 12 : 8))
1569 : get_frame_register_unsigned (frame
, rm
));
1574 res
= shift
>= 32 ? 0 : res
<< shift
;
1578 res
= shift
>= 32 ? 0 : res
>> shift
;
1584 res
= ((res
& 0x80000000L
)
1585 ? ~((~res
) >> shift
) : res
>> shift
);
1588 case 3: /* ROR/RRX */
1591 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1593 res
= (res
>> shift
) | (res
<< (32 - shift
));
1597 return res
& 0xffffffff;
1600 /* Return number of 1-bits in VAL. */
1603 bitcount (unsigned long val
)
1606 for (nbits
= 0; val
!= 0; nbits
++)
1607 val
&= val
- 1; /* delete rightmost 1-bit in val */
1612 thumb_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1614 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1615 unsigned short inst1
= read_memory_unsigned_integer (pc
, 2);
1616 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1617 unsigned long offset
;
1619 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1623 /* Fetch the saved PC from the stack. It's stored above
1624 all of the other registers. */
1625 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
1626 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
1627 nextpc
= (CORE_ADDR
) read_memory_unsigned_integer (sp
+ offset
, 4);
1628 nextpc
= gdbarch_addr_bits_remove (current_gdbarch
, nextpc
);
1630 error (_("Infinite loop detected"));
1632 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1634 unsigned long status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
1635 unsigned long cond
= bits (inst1
, 8, 11);
1636 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1637 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1639 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1641 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1643 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link, and blx */
1645 unsigned short inst2
= read_memory_unsigned_integer (pc
+ 2, 2);
1646 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1647 nextpc
= pc_val
+ offset
;
1648 /* For BLX make sure to clear the low bits. */
1649 if (bits (inst2
, 11, 12) == 1)
1650 nextpc
= nextpc
& 0xfffffffc;
1652 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
1654 if (bits (inst1
, 3, 6) == 0x0f)
1657 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
1659 nextpc
= gdbarch_addr_bits_remove (current_gdbarch
, nextpc
);
1661 error (_("Infinite loop detected"));
1668 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1670 unsigned long pc_val
;
1671 unsigned long this_instr
;
1672 unsigned long status
;
1675 if (arm_pc_is_thumb (pc
))
1676 return thumb_get_next_pc (frame
, pc
);
1678 pc_val
= (unsigned long) pc
;
1679 this_instr
= read_memory_unsigned_integer (pc
, 4);
1680 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
1681 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1683 if (bits (this_instr
, 28, 31) == INST_NV
)
1684 switch (bits (this_instr
, 24, 27))
1689 /* Branch with Link and change to Thumb. */
1690 nextpc
= BranchDest (pc
, this_instr
);
1691 nextpc
|= bit (this_instr
, 24) << 1;
1693 nextpc
= gdbarch_addr_bits_remove (current_gdbarch
, nextpc
);
1695 error (_("Infinite loop detected"));
1701 /* Coprocessor register transfer. */
1702 if (bits (this_instr
, 12, 15) == 15)
1703 error (_("Invalid update to pc in instruction"));
1706 else if (condition_true (bits (this_instr
, 28, 31), status
))
1708 switch (bits (this_instr
, 24, 27))
1711 case 0x1: /* data processing */
1715 unsigned long operand1
, operand2
, result
= 0;
1719 if (bits (this_instr
, 12, 15) != 15)
1722 if (bits (this_instr
, 22, 25) == 0
1723 && bits (this_instr
, 4, 7) == 9) /* multiply */
1724 error (_("Invalid update to pc in instruction"));
1726 /* BX <reg>, BLX <reg> */
1727 if (bits (this_instr
, 4, 27) == 0x12fff1
1728 || bits (this_instr
, 4, 27) == 0x12fff3)
1730 rn
= bits (this_instr
, 0, 3);
1731 result
= (rn
== 15) ? pc_val
+ 8
1732 : get_frame_register_unsigned (frame
, rn
);
1733 nextpc
= (CORE_ADDR
) gdbarch_addr_bits_remove
1734 (current_gdbarch
, result
);
1737 error (_("Infinite loop detected"));
1742 /* Multiply into PC */
1743 c
= (status
& FLAG_C
) ? 1 : 0;
1744 rn
= bits (this_instr
, 16, 19);
1745 operand1
= (rn
== 15) ? pc_val
+ 8
1746 : get_frame_register_unsigned (frame
, rn
);
1748 if (bit (this_instr
, 25))
1750 unsigned long immval
= bits (this_instr
, 0, 7);
1751 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1752 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1755 else /* operand 2 is a shifted register */
1756 operand2
= shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
);
1758 switch (bits (this_instr
, 21, 24))
1761 result
= operand1
& operand2
;
1765 result
= operand1
^ operand2
;
1769 result
= operand1
- operand2
;
1773 result
= operand2
- operand1
;
1777 result
= operand1
+ operand2
;
1781 result
= operand1
+ operand2
+ c
;
1785 result
= operand1
- operand2
+ c
;
1789 result
= operand2
- operand1
+ c
;
1795 case 0xb: /* tst, teq, cmp, cmn */
1796 result
= (unsigned long) nextpc
;
1800 result
= operand1
| operand2
;
1804 /* Always step into a function. */
1809 result
= operand1
& ~operand2
;
1816 nextpc
= (CORE_ADDR
) gdbarch_addr_bits_remove
1817 (current_gdbarch
, result
);
1820 error (_("Infinite loop detected"));
1825 case 0x5: /* data transfer */
1828 if (bit (this_instr
, 20))
1831 if (bits (this_instr
, 12, 15) == 15)
1837 if (bit (this_instr
, 22))
1838 error (_("Invalid update to pc in instruction"));
1840 /* byte write to PC */
1841 rn
= bits (this_instr
, 16, 19);
1842 base
= (rn
== 15) ? pc_val
+ 8
1843 : get_frame_register_unsigned (frame
, rn
);
1844 if (bit (this_instr
, 24))
1847 int c
= (status
& FLAG_C
) ? 1 : 0;
1848 unsigned long offset
=
1849 (bit (this_instr
, 25)
1850 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
1851 : bits (this_instr
, 0, 11));
1853 if (bit (this_instr
, 23))
1858 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1861 nextpc
= gdbarch_addr_bits_remove (current_gdbarch
, nextpc
);
1864 error (_("Infinite loop detected"));
1870 case 0x9: /* block transfer */
1871 if (bit (this_instr
, 20))
1874 if (bit (this_instr
, 15))
1879 if (bit (this_instr
, 23))
1882 unsigned long reglist
= bits (this_instr
, 0, 14);
1883 offset
= bitcount (reglist
) * 4;
1884 if (bit (this_instr
, 24)) /* pre */
1887 else if (bit (this_instr
, 24))
1891 unsigned long rn_val
=
1892 get_frame_register_unsigned (frame
,
1893 bits (this_instr
, 16, 19));
1895 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1899 nextpc
= gdbarch_addr_bits_remove
1900 (current_gdbarch
, nextpc
);
1902 error (_("Infinite loop detected"));
1907 case 0xb: /* branch & link */
1908 case 0xa: /* branch */
1910 nextpc
= BranchDest (pc
, this_instr
);
1912 nextpc
= gdbarch_addr_bits_remove (current_gdbarch
, nextpc
);
1914 error (_("Infinite loop detected"));
1920 case 0xe: /* coproc ops */
1925 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
1933 /* single_step() is called just before we want to resume the inferior,
1934 if we want to single-step it but there is no hardware or kernel
1935 single-step support. We find the target of the coming instruction
1936 and breakpoint it. */
1939 arm_software_single_step (struct frame_info
*frame
)
1941 /* NOTE: This may insert the wrong breakpoint instruction when
1942 single-stepping over a mode-changing instruction, if the
1943 CPSR heuristics are used. */
1945 CORE_ADDR next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
1946 insert_single_step_breakpoint (next_pc
);
1951 #include "bfd-in2.h"
1952 #include "libcoff.h"
1955 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
1957 if (arm_pc_is_thumb (memaddr
))
1959 static asymbol
*asym
;
1960 static combined_entry_type ce
;
1961 static struct coff_symbol_struct csym
;
1962 static struct bfd fake_bfd
;
1963 static bfd_target fake_target
;
1965 if (csym
.native
== NULL
)
1967 /* Create a fake symbol vector containing a Thumb symbol.
1968 This is solely so that the code in print_insn_little_arm()
1969 and print_insn_big_arm() in opcodes/arm-dis.c will detect
1970 the presence of a Thumb symbol and switch to decoding
1971 Thumb instructions. */
1973 fake_target
.flavour
= bfd_target_coff_flavour
;
1974 fake_bfd
.xvec
= &fake_target
;
1975 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
1977 csym
.symbol
.the_bfd
= &fake_bfd
;
1978 csym
.symbol
.name
= "fake";
1979 asym
= (asymbol
*) & csym
;
1982 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
1983 info
->symbols
= &asym
;
1986 info
->symbols
= NULL
;
1988 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1989 return print_insn_big_arm (memaddr
, info
);
1991 return print_insn_little_arm (memaddr
, info
);
1994 /* The following define instruction sequences that will cause ARM
1995 cpu's to take an undefined instruction trap. These are used to
1996 signal a breakpoint to GDB.
1998 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
1999 modes. A different instruction is required for each mode. The ARM
2000 cpu's can also be big or little endian. Thus four different
2001 instructions are needed to support all cases.
2003 Note: ARMv4 defines several new instructions that will take the
2004 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2005 not in fact add the new instructions. The new undefined
2006 instructions in ARMv4 are all instructions that had no defined
2007 behaviour in earlier chips. There is no guarantee that they will
2008 raise an exception, but may be treated as NOP's. In practice, it
2009 may only safe to rely on instructions matching:
2011 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2012 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2013 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2015 Even this may only true if the condition predicate is true. The
2016 following use a condition predicate of ALWAYS so it is always TRUE.
2018 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2019 and NetBSD all use a software interrupt rather than an undefined
2020 instruction to force a trap. This can be handled by by the
2021 abi-specific code during establishment of the gdbarch vector. */
2023 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2024 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2025 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
2026 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
2028 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
2029 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
2030 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2031 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2033 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2034 the program counter value to determine whether a 16-bit or 32-bit
2035 breakpoint should be used. It returns a pointer to a string of
2036 bytes that encode a breakpoint instruction, stores the length of
2037 the string to *lenptr, and adjusts the program counter (if
2038 necessary) to point to the actual memory location where the
2039 breakpoint should be inserted. */
2041 static const unsigned char *
2042 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
2044 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2046 if (arm_pc_is_thumb (*pcptr
))
2048 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2049 *lenptr
= tdep
->thumb_breakpoint_size
;
2050 return tdep
->thumb_breakpoint
;
2054 *lenptr
= tdep
->arm_breakpoint_size
;
2055 return tdep
->arm_breakpoint
;
2059 /* Extract from an array REGBUF containing the (raw) register state a
2060 function return value of type TYPE, and copy that, in virtual
2061 format, into VALBUF. */
2064 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
2067 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2069 switch (gdbarch_tdep (current_gdbarch
)->fp_model
)
2073 /* The value is in register F0 in internal format. We need to
2074 extract the raw value and then convert it to the desired
2076 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
2078 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
2079 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
2084 case ARM_FLOAT_SOFT_FPA
:
2085 case ARM_FLOAT_SOFT_VFP
:
2086 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
2087 if (TYPE_LENGTH (type
) > 4)
2088 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
2089 valbuf
+ INT_REGISTER_SIZE
);
2094 (__FILE__
, __LINE__
,
2095 _("arm_extract_return_value: Floating point model not supported"));
2099 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2100 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2101 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2102 || TYPE_CODE (type
) == TYPE_CODE_PTR
2103 || TYPE_CODE (type
) == TYPE_CODE_REF
2104 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2106 /* If the the type is a plain integer, then the access is
2107 straight-forward. Otherwise we have to play around a bit more. */
2108 int len
= TYPE_LENGTH (type
);
2109 int regno
= ARM_A1_REGNUM
;
2114 /* By using store_unsigned_integer we avoid having to do
2115 anything special for small big-endian values. */
2116 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2117 store_unsigned_integer (valbuf
,
2118 (len
> INT_REGISTER_SIZE
2119 ? INT_REGISTER_SIZE
: len
),
2121 len
-= INT_REGISTER_SIZE
;
2122 valbuf
+= INT_REGISTER_SIZE
;
2127 /* For a structure or union the behaviour is as if the value had
2128 been stored to word-aligned memory and then loaded into
2129 registers with 32-bit load instruction(s). */
2130 int len
= TYPE_LENGTH (type
);
2131 int regno
= ARM_A1_REGNUM
;
2132 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2136 regcache_cooked_read (regs
, regno
++, tmpbuf
);
2137 memcpy (valbuf
, tmpbuf
,
2138 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2139 len
-= INT_REGISTER_SIZE
;
2140 valbuf
+= INT_REGISTER_SIZE
;
2146 /* Will a function return an aggregate type in memory or in a
2147 register? Return 0 if an aggregate type can be returned in a
2148 register, 1 if it must be returned in memory. */
2151 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2154 enum type_code code
;
2156 CHECK_TYPEDEF (type
);
2158 /* In the ARM ABI, "integer" like aggregate types are returned in
2159 registers. For an aggregate type to be integer like, its size
2160 must be less than or equal to INT_REGISTER_SIZE and the
2161 offset of each addressable subfield must be zero. Note that bit
2162 fields are not addressable, and all addressable subfields of
2163 unions always start at offset zero.
2165 This function is based on the behaviour of GCC 2.95.1.
2166 See: gcc/arm.c: arm_return_in_memory() for details.
2168 Note: All versions of GCC before GCC 2.95.2 do not set up the
2169 parameters correctly for a function returning the following
2170 structure: struct { float f;}; This should be returned in memory,
2171 not a register. Richard Earnshaw sent me a patch, but I do not
2172 know of any way to detect if a function like the above has been
2173 compiled with the correct calling convention. */
2175 /* All aggregate types that won't fit in a register must be returned
2177 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
2182 /* The AAPCS says all aggregates not larger than a word are returned
2184 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
2187 /* The only aggregate types that can be returned in a register are
2188 structs and unions. Arrays must be returned in memory. */
2189 code
= TYPE_CODE (type
);
2190 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2195 /* Assume all other aggregate types can be returned in a register.
2196 Run a check for structures, unions and arrays. */
2199 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2202 /* Need to check if this struct/union is "integer" like. For
2203 this to be true, its size must be less than or equal to
2204 INT_REGISTER_SIZE and the offset of each addressable
2205 subfield must be zero. Note that bit fields are not
2206 addressable, and unions always start at offset zero. If any
2207 of the subfields is a floating point type, the struct/union
2208 cannot be an integer type. */
2210 /* For each field in the object, check:
2211 1) Is it FP? --> yes, nRc = 1;
2212 2) Is it addressable (bitpos != 0) and
2213 not packed (bitsize == 0)?
2217 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2219 enum type_code field_type_code
;
2220 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, i
)));
2222 /* Is it a floating point type field? */
2223 if (field_type_code
== TYPE_CODE_FLT
)
2229 /* If bitpos != 0, then we have to care about it. */
2230 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2232 /* Bitfields are not addressable. If the field bitsize is
2233 zero, then the field is not packed. Hence it cannot be
2234 a bitfield or any other packed type. */
2235 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2247 /* Write into appropriate registers a function return value of type
2248 TYPE, given in virtual format. */
2251 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
2252 const gdb_byte
*valbuf
)
2254 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2256 char buf
[MAX_REGISTER_SIZE
];
2258 switch (gdbarch_tdep (current_gdbarch
)->fp_model
)
2262 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
);
2263 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
2266 case ARM_FLOAT_SOFT_FPA
:
2267 case ARM_FLOAT_SOFT_VFP
:
2268 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
2269 if (TYPE_LENGTH (type
) > 4)
2270 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
2271 valbuf
+ INT_REGISTER_SIZE
);
2276 (__FILE__
, __LINE__
,
2277 _("arm_store_return_value: Floating point model not supported"));
2281 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2282 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2283 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2284 || TYPE_CODE (type
) == TYPE_CODE_PTR
2285 || TYPE_CODE (type
) == TYPE_CODE_REF
2286 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2288 if (TYPE_LENGTH (type
) <= 4)
2290 /* Values of one word or less are zero/sign-extended and
2292 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2293 LONGEST val
= unpack_long (type
, valbuf
);
2295 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, val
);
2296 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
2300 /* Integral values greater than one word are stored in consecutive
2301 registers starting with r0. This will always be a multiple of
2302 the regiser size. */
2303 int len
= TYPE_LENGTH (type
);
2304 int regno
= ARM_A1_REGNUM
;
2308 regcache_cooked_write (regs
, regno
++, valbuf
);
2309 len
-= INT_REGISTER_SIZE
;
2310 valbuf
+= INT_REGISTER_SIZE
;
2316 /* For a structure or union the behaviour is as if the value had
2317 been stored to word-aligned memory and then loaded into
2318 registers with 32-bit load instruction(s). */
2319 int len
= TYPE_LENGTH (type
);
2320 int regno
= ARM_A1_REGNUM
;
2321 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2325 memcpy (tmpbuf
, valbuf
,
2326 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2327 regcache_cooked_write (regs
, regno
++, tmpbuf
);
2328 len
-= INT_REGISTER_SIZE
;
2329 valbuf
+= INT_REGISTER_SIZE
;
2335 /* Handle function return values. */
2337 static enum return_value_convention
2338 arm_return_value (struct gdbarch
*gdbarch
, struct type
*valtype
,
2339 struct regcache
*regcache
, gdb_byte
*readbuf
,
2340 const gdb_byte
*writebuf
)
2342 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2344 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2345 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2346 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2348 if (tdep
->struct_return
== pcc_struct_return
2349 || arm_return_in_memory (gdbarch
, valtype
))
2350 return RETURN_VALUE_STRUCT_CONVENTION
;
2354 arm_store_return_value (valtype
, regcache
, writebuf
);
2357 arm_extract_return_value (valtype
, regcache
, readbuf
);
2359 return RETURN_VALUE_REGISTER_CONVENTION
;
2364 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2367 char buf
[INT_REGISTER_SIZE
];
2368 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (frame
));
2370 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
2372 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2376 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
);
2380 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
2381 return the target PC. Otherwise return 0. */
2384 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
2388 CORE_ADDR start_addr
;
2390 /* Find the starting address and name of the function containing the PC. */
2391 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2394 /* If PC is in a Thumb call or return stub, return the address of the
2395 target PC, which is in a register. The thunk functions are called
2396 _call_via_xx, where x is the register name. The possible names
2397 are r0-r9, sl, fp, ip, sp, and lr. */
2398 if (strncmp (name
, "_call_via_", 10) == 0)
2400 /* Use the name suffix to determine which register contains the
2402 static char *table
[15] =
2403 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2404 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2407 int offset
= strlen (name
) - 2;
2409 for (regno
= 0; regno
<= 14; regno
++)
2410 if (strcmp (&name
[offset
], table
[regno
]) == 0)
2411 return get_frame_register_unsigned (frame
, regno
);
2414 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
2415 non-interworking calls to foo. We could decode the stubs
2416 to find the target but it's easier to use the symbol table. */
2417 namelen
= strlen (name
);
2418 if (name
[0] == '_' && name
[1] == '_'
2419 && ((namelen
> 2 + strlen ("_from_thumb")
2420 && strncmp (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb",
2421 strlen ("_from_thumb")) == 0)
2422 || (namelen
> 2 + strlen ("_from_arm")
2423 && strncmp (name
+ namelen
- strlen ("_from_arm"), "_from_arm",
2424 strlen ("_from_arm")) == 0)))
2427 int target_len
= namelen
- 2;
2428 struct minimal_symbol
*minsym
;
2429 struct objfile
*objfile
;
2430 struct obj_section
*sec
;
2432 if (name
[namelen
- 1] == 'b')
2433 target_len
-= strlen ("_from_thumb");
2435 target_len
-= strlen ("_from_arm");
2437 target_name
= alloca (target_len
+ 1);
2438 memcpy (target_name
, name
+ 2, target_len
);
2439 target_name
[target_len
] = '\0';
2441 sec
= find_pc_section (pc
);
2442 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
2443 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
2445 return SYMBOL_VALUE_ADDRESS (minsym
);
2450 return 0; /* not a stub */
2454 set_arm_command (char *args
, int from_tty
)
2456 printf_unfiltered (_("\
2457 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2458 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
2462 show_arm_command (char *args
, int from_tty
)
2464 cmd_show_list (showarmcmdlist
, from_tty
, "");
2468 arm_update_current_architecture (void)
2470 struct gdbarch_info info
;
2472 /* If the current architecture is not ARM, we have nothing to do. */
2473 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_arm
)
2476 /* Update the architecture. */
2477 gdbarch_info_init (&info
);
2479 if (!gdbarch_update_p (info
))
2480 internal_error (__FILE__
, __LINE__
, "could not update architecture");
2484 set_fp_model_sfunc (char *args
, int from_tty
,
2485 struct cmd_list_element
*c
)
2487 enum arm_float_model fp_model
;
2489 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
2490 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
2492 arm_fp_model
= fp_model
;
2496 if (fp_model
== ARM_FLOAT_LAST
)
2497 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
2500 arm_update_current_architecture ();
2504 show_fp_model (struct ui_file
*file
, int from_tty
,
2505 struct cmd_list_element
*c
, const char *value
)
2507 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2509 if (arm_fp_model
== ARM_FLOAT_AUTO
2510 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2511 fprintf_filtered (file
, _("\
2512 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2513 fp_model_strings
[tdep
->fp_model
]);
2515 fprintf_filtered (file
, _("\
2516 The current ARM floating point model is \"%s\".\n"),
2517 fp_model_strings
[arm_fp_model
]);
2521 arm_set_abi (char *args
, int from_tty
,
2522 struct cmd_list_element
*c
)
2524 enum arm_abi_kind arm_abi
;
2526 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
2527 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
2529 arm_abi_global
= arm_abi
;
2533 if (arm_abi
== ARM_ABI_LAST
)
2534 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
2537 arm_update_current_architecture ();
2541 arm_show_abi (struct ui_file
*file
, int from_tty
,
2542 struct cmd_list_element
*c
, const char *value
)
2544 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2546 if (arm_abi_global
== ARM_ABI_AUTO
2547 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2548 fprintf_filtered (file
, _("\
2549 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2550 arm_abi_strings
[tdep
->arm_abi
]);
2552 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
2556 /* If the user changes the register disassembly style used for info
2557 register and other commands, we have to also switch the style used
2558 in opcodes for disassembly output. This function is run in the "set
2559 arm disassembly" command, and does that. */
2562 set_disassembly_style_sfunc (char *args
, int from_tty
,
2563 struct cmd_list_element
*c
)
2565 set_disassembly_style ();
2568 /* Return the ARM register name corresponding to register I. */
2570 arm_register_name (int i
)
2572 if (i
>= ARRAY_SIZE (arm_register_names
))
2573 /* These registers are only supported on targets which supply
2574 an XML description. */
2577 return arm_register_names
[i
];
2581 set_disassembly_style (void)
2585 /* Find the style that the user wants. */
2586 for (current
= 0; current
< num_disassembly_options
; current
++)
2587 if (disassembly_style
== valid_disassembly_styles
[current
])
2589 gdb_assert (current
< num_disassembly_options
);
2591 /* Synchronize the disassembler. */
2592 set_arm_regname_option (current
);
2595 /* Test whether the coff symbol specific value corresponds to a Thumb
2599 coff_sym_is_thumb (int val
)
2601 return (val
== C_THUMBEXT
||
2602 val
== C_THUMBSTAT
||
2603 val
== C_THUMBEXTFUNC
||
2604 val
== C_THUMBSTATFUNC
||
2605 val
== C_THUMBLABEL
);
2608 /* arm_coff_make_msymbol_special()
2609 arm_elf_make_msymbol_special()
2611 These functions test whether the COFF or ELF symbol corresponds to
2612 an address in thumb code, and set a "special" bit in a minimal
2613 symbol to indicate that it does. */
2616 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2618 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2620 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2622 MSYMBOL_SET_SPECIAL (msym
);
2626 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2628 if (coff_sym_is_thumb (val
))
2629 MSYMBOL_SET_SPECIAL (msym
);
2633 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2635 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
2637 /* If necessary, set the T bit. */
2641 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
2642 if (arm_pc_is_thumb (pc
))
2643 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
, val
| 0x20);
2645 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
2646 val
& ~(ULONGEST
) 0x20);
2650 static struct value
*
2651 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
2653 const int *reg_p
= baton
;
2654 return value_of_register (*reg_p
, frame
);
2657 static enum gdb_osabi
2658 arm_elf_osabi_sniffer (bfd
*abfd
)
2660 unsigned int elfosabi
;
2661 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2663 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2665 if (elfosabi
== ELFOSABI_ARM
)
2666 /* GNU tools use this value. Check note sections in this case,
2668 bfd_map_over_sections (abfd
,
2669 generic_elf_osabi_sniff_abi_tag_sections
,
2672 /* Anything else will be handled by the generic ELF sniffer. */
2677 /* Initialize the current architecture based on INFO. If possible,
2678 re-use an architecture from ARCHES, which is a list of
2679 architectures already created during this debugging session.
2681 Called e.g. at program startup, when reading a core file, and when
2682 reading a binary file. */
2684 static struct gdbarch
*
2685 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2687 struct gdbarch_tdep
*tdep
;
2688 struct gdbarch
*gdbarch
;
2689 struct gdbarch_list
*best_arch
;
2690 enum arm_abi_kind arm_abi
= arm_abi_global
;
2691 enum arm_float_model fp_model
= arm_fp_model
;
2692 struct tdesc_arch_data
*tdesc_data
= NULL
;
2694 int have_fpa_registers
= 1;
2696 /* Check any target description for validity. */
2697 if (tdesc_has_registers (info
.target_desc
))
2699 /* For most registers we require GDB's default names; but also allow
2700 the numeric names for sp / lr / pc, as a convenience. */
2701 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
2702 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
2703 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
2705 const struct tdesc_feature
*feature
;
2708 feature
= tdesc_find_feature (info
.target_desc
,
2709 "org.gnu.gdb.arm.core");
2710 if (feature
== NULL
)
2713 tdesc_data
= tdesc_data_alloc ();
2716 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
2717 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
2718 arm_register_names
[i
]);
2719 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2722 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2725 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2728 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2729 ARM_PS_REGNUM
, "cpsr");
2733 tdesc_data_cleanup (tdesc_data
);
2737 feature
= tdesc_find_feature (info
.target_desc
,
2738 "org.gnu.gdb.arm.fpa");
2739 if (feature
!= NULL
)
2742 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
2743 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
2744 arm_register_names
[i
]);
2747 tdesc_data_cleanup (tdesc_data
);
2752 have_fpa_registers
= 0;
2754 feature
= tdesc_find_feature (info
.target_desc
,
2755 "org.gnu.gdb.xscale.iwmmxt");
2756 if (feature
!= NULL
)
2758 static const char *const iwmmxt_names
[] = {
2759 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
2760 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
2761 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
2762 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
2766 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
2768 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
2769 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
2771 /* Check for the control registers, but do not fail if they
2773 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
2774 tdesc_numbered_register (feature
, tdesc_data
, i
,
2775 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
2777 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
2779 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
2780 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
2784 tdesc_data_cleanup (tdesc_data
);
2790 /* If we have an object to base this architecture on, try to determine
2793 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
2795 int ei_osabi
, e_flags
;
2797 switch (bfd_get_flavour (info
.abfd
))
2799 case bfd_target_aout_flavour
:
2800 /* Assume it's an old APCS-style ABI. */
2801 arm_abi
= ARM_ABI_APCS
;
2804 case bfd_target_coff_flavour
:
2805 /* Assume it's an old APCS-style ABI. */
2807 arm_abi
= ARM_ABI_APCS
;
2810 case bfd_target_elf_flavour
:
2811 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
2812 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2814 if (ei_osabi
== ELFOSABI_ARM
)
2816 /* GNU tools used to use this value, but do not for EABI
2817 objects. There's nowhere to tag an EABI version
2818 anyway, so assume APCS. */
2819 arm_abi
= ARM_ABI_APCS
;
2821 else if (ei_osabi
== ELFOSABI_NONE
)
2823 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
2827 case EF_ARM_EABI_UNKNOWN
:
2828 /* Assume GNU tools. */
2829 arm_abi
= ARM_ABI_APCS
;
2832 case EF_ARM_EABI_VER4
:
2833 case EF_ARM_EABI_VER5
:
2834 arm_abi
= ARM_ABI_AAPCS
;
2835 /* EABI binaries default to VFP float ordering. */
2836 if (fp_model
== ARM_FLOAT_AUTO
)
2837 fp_model
= ARM_FLOAT_SOFT_VFP
;
2841 /* Leave it as "auto". */
2842 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
2847 if (fp_model
== ARM_FLOAT_AUTO
)
2849 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2851 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
2854 /* Leave it as "auto". Strictly speaking this case
2855 means FPA, but almost nobody uses that now, and
2856 many toolchains fail to set the appropriate bits
2857 for the floating-point model they use. */
2859 case EF_ARM_SOFT_FLOAT
:
2860 fp_model
= ARM_FLOAT_SOFT_FPA
;
2862 case EF_ARM_VFP_FLOAT
:
2863 fp_model
= ARM_FLOAT_VFP
;
2865 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
2866 fp_model
= ARM_FLOAT_SOFT_VFP
;
2873 /* Leave it as "auto". */
2878 /* If there is already a candidate, use it. */
2879 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
2881 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
2883 if (arm_abi
!= ARM_ABI_AUTO
2884 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
2887 if (fp_model
!= ARM_FLOAT_AUTO
2888 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
2891 /* Found a match. */
2895 if (best_arch
!= NULL
)
2897 if (tdesc_data
!= NULL
)
2898 tdesc_data_cleanup (tdesc_data
);
2899 return best_arch
->gdbarch
;
2902 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
2903 gdbarch
= gdbarch_alloc (&info
, tdep
);
2905 /* Record additional information about the architecture we are defining.
2906 These are gdbarch discriminators, like the OSABI. */
2907 tdep
->arm_abi
= arm_abi
;
2908 tdep
->fp_model
= fp_model
;
2909 tdep
->have_fpa_registers
= have_fpa_registers
;
2912 switch (info
.byte_order
)
2914 case BFD_ENDIAN_BIG
:
2915 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
2916 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
2917 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
2918 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
2922 case BFD_ENDIAN_LITTLE
:
2923 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
2924 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
2925 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
2926 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
2931 internal_error (__FILE__
, __LINE__
,
2932 _("arm_gdbarch_init: bad byte order for float format"));
2935 /* On ARM targets char defaults to unsigned. */
2936 set_gdbarch_char_signed (gdbarch
, 0);
2938 /* This should be low enough for everything. */
2939 tdep
->lowest_pc
= 0x20;
2940 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
2942 /* The default, for both APCS and AAPCS, is to return small
2943 structures in registers. */
2944 tdep
->struct_return
= reg_struct_return
;
2946 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
2947 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
2949 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
2951 /* Frame handling. */
2952 set_gdbarch_unwind_dummy_id (gdbarch
, arm_unwind_dummy_id
);
2953 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
2954 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
2956 frame_base_set_default (gdbarch
, &arm_normal_base
);
2958 /* Address manipulation. */
2959 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
2960 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
2962 /* Advance PC across function entry code. */
2963 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
2965 /* Skip trampolines. */
2966 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
2968 /* The stack grows downward. */
2969 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2971 /* Breakpoint manipulation. */
2972 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
2974 /* Information about registers, etc. */
2975 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
2976 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
2977 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
2978 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
2979 set_gdbarch_register_type (gdbarch
, arm_register_type
);
2981 /* This "info float" is FPA-specific. Use the generic version if we
2983 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
2984 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
2986 /* Internal <-> external register number maps. */
2987 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
2988 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
2989 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
2991 set_gdbarch_register_name (gdbarch
, arm_register_name
);
2993 /* Returning results. */
2994 set_gdbarch_return_value (gdbarch
, arm_return_value
);
2997 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
2999 /* Minsymbol frobbing. */
3000 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
3001 set_gdbarch_coff_make_msymbol_special (gdbarch
,
3002 arm_coff_make_msymbol_special
);
3004 /* Virtual tables. */
3005 set_gdbarch_vbit_in_delta (gdbarch
, 1);
3007 /* Hook in the ABI-specific overrides, if they have been registered. */
3008 gdbarch_init_osabi (info
, gdbarch
);
3010 /* Add some default predicates. */
3011 frame_unwind_append_sniffer (gdbarch
, arm_stub_unwind_sniffer
);
3012 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
3013 frame_unwind_append_sniffer (gdbarch
, arm_prologue_unwind_sniffer
);
3015 /* Now we have tuned the configuration, set a few final things,
3016 based on what the OS ABI has told us. */
3018 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
3019 binaries are always marked. */
3020 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
3021 tdep
->arm_abi
= ARM_ABI_APCS
;
3023 /* We used to default to FPA for generic ARM, but almost nobody
3024 uses that now, and we now provide a way for the user to force
3025 the model. So default to the most useful variant. */
3026 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
3027 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
3029 if (tdep
->jb_pc
>= 0)
3030 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
3032 /* Floating point sizes and format. */
3033 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
3034 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
3036 set_gdbarch_double_format
3037 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
3038 set_gdbarch_long_double_format
3039 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
3043 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
3044 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
3048 tdesc_use_registers (gdbarch
, tdesc_data
);
3050 /* Add standard register aliases. We add aliases even for those
3051 nanes which are used by the current architecture - it's simpler,
3052 and does no harm, since nothing ever lists user registers. */
3053 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
3054 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
3055 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
3061 arm_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
3063 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3068 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
3069 (unsigned long) tdep
->lowest_pc
);
3072 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
3075 _initialize_arm_tdep (void)
3077 struct ui_file
*stb
;
3079 struct cmd_list_element
*new_set
, *new_show
;
3080 const char *setname
;
3081 const char *setdesc
;
3082 const char *const *regnames
;
3084 static char *helptext
;
3085 char regdesc
[1024], *rdptr
= regdesc
;
3086 size_t rest
= sizeof (regdesc
);
3088 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
3090 /* Register an ELF OS ABI sniffer for ARM binaries. */
3091 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
3092 bfd_target_elf_flavour
,
3093 arm_elf_osabi_sniffer
);
3095 /* Get the number of possible sets of register names defined in opcodes. */
3096 num_disassembly_options
= get_arm_regname_num_options ();
3098 /* Add root prefix command for all "set arm"/"show arm" commands. */
3099 add_prefix_cmd ("arm", no_class
, set_arm_command
,
3100 _("Various ARM-specific commands."),
3101 &setarmcmdlist
, "set arm ", 0, &setlist
);
3103 add_prefix_cmd ("arm", no_class
, show_arm_command
,
3104 _("Various ARM-specific commands."),
3105 &showarmcmdlist
, "show arm ", 0, &showlist
);
3107 /* Sync the opcode insn printer with our register viewer. */
3108 parse_arm_disassembler_option ("reg-names-std");
3110 /* Initialize the array that will be passed to
3111 add_setshow_enum_cmd(). */
3112 valid_disassembly_styles
3113 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
3114 for (i
= 0; i
< num_disassembly_options
; i
++)
3116 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
3117 valid_disassembly_styles
[i
] = setname
;
3118 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
3121 /* When we find the default names, tell the disassembler to use
3123 if (!strcmp (setname
, "std"))
3125 disassembly_style
= setname
;
3126 set_arm_regname_option (i
);
3129 /* Mark the end of valid options. */
3130 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
3132 /* Create the help text. */
3133 stb
= mem_fileopen ();
3134 fprintf_unfiltered (stb
, "%s%s%s",
3135 _("The valid values are:\n"),
3137 _("The default is \"std\"."));
3138 helptext
= ui_file_xstrdup (stb
, &length
);
3139 ui_file_delete (stb
);
3141 add_setshow_enum_cmd("disassembler", no_class
,
3142 valid_disassembly_styles
, &disassembly_style
,
3143 _("Set the disassembly style."),
3144 _("Show the disassembly style."),
3146 set_disassembly_style_sfunc
,
3147 NULL
, /* FIXME: i18n: The disassembly style is \"%s\". */
3148 &setarmcmdlist
, &showarmcmdlist
);
3150 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
3151 _("Set usage of ARM 32-bit mode."),
3152 _("Show usage of ARM 32-bit mode."),
3153 _("When off, a 26-bit PC will be used."),
3155 NULL
, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
3156 &setarmcmdlist
, &showarmcmdlist
);
3158 /* Add a command to allow the user to force the FPU model. */
3159 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
3160 _("Set the floating point type."),
3161 _("Show the floating point type."),
3162 _("auto - Determine the FP typefrom the OS-ABI.\n\
3163 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
3164 fpa - FPA co-processor (GCC compiled).\n\
3165 softvfp - Software FP with pure-endian doubles.\n\
3166 vfp - VFP co-processor."),
3167 set_fp_model_sfunc
, show_fp_model
,
3168 &setarmcmdlist
, &showarmcmdlist
);
3170 /* Add a command to allow the user to force the ABI. */
3171 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
3174 NULL
, arm_set_abi
, arm_show_abi
,
3175 &setarmcmdlist
, &showarmcmdlist
);
3177 /* Debugging flag. */
3178 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
3179 _("Set ARM debugging."),
3180 _("Show ARM debugging."),
3181 _("When on, arm-specific debugging is enabled."),
3183 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
3184 &setdebuglist
, &showdebuglist
);