1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
31 #include "reggroups.h"
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "arch/arm-get-next-pcs.h"
51 #include "gdb/sim-arm.h"
54 #include "coff/internal.h"
60 #include "record-full.h"
62 #include "features/arm-with-m.c"
63 #include "features/arm-with-m-fpa-layout.c"
64 #include "features/arm-with-m-vfp-d16.c"
65 #include "features/arm-with-iwmmxt.c"
66 #include "features/arm-with-vfpv2.c"
67 #include "features/arm-with-vfpv3.c"
68 #include "features/arm-with-neon.c"
72 /* Macros for setting and testing a bit in a minimal symbol that marks
73 it as Thumb function. The MSB of the minimal symbol's "info" field
74 is used for this purpose.
76 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
77 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
79 #define MSYMBOL_SET_SPECIAL(msym) \
80 MSYMBOL_TARGET_FLAG_1 (msym) = 1
82 #define MSYMBOL_IS_SPECIAL(msym) \
83 MSYMBOL_TARGET_FLAG_1 (msym)
85 /* Per-objfile data used for mapping symbols. */
86 static const struct objfile_data
*arm_objfile_data_key
;
88 struct arm_mapping_symbol
93 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
94 DEF_VEC_O(arm_mapping_symbol_s
);
96 struct arm_per_objfile
98 VEC(arm_mapping_symbol_s
) **section_maps
;
101 /* The list of available "set arm ..." and "show arm ..." commands. */
102 static struct cmd_list_element
*setarmcmdlist
= NULL
;
103 static struct cmd_list_element
*showarmcmdlist
= NULL
;
105 /* The type of floating-point to use. Keep this in sync with enum
106 arm_float_model, and the help string in _initialize_arm_tdep. */
107 static const char *const fp_model_strings
[] =
117 /* A variable that can be configured by the user. */
118 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
119 static const char *current_fp_model
= "auto";
121 /* The ABI to use. Keep this in sync with arm_abi_kind. */
122 static const char *const arm_abi_strings
[] =
130 /* A variable that can be configured by the user. */
131 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
132 static const char *arm_abi_string
= "auto";
134 /* The execution mode to assume. */
135 static const char *const arm_mode_strings
[] =
143 static const char *arm_fallback_mode_string
= "auto";
144 static const char *arm_force_mode_string
= "auto";
146 /* Internal override of the execution mode. -1 means no override,
147 0 means override to ARM mode, 1 means override to Thumb mode.
148 The effect is the same as if arm_force_mode has been set by the
149 user (except the internal override has precedence over a user's
150 arm_force_mode override). */
151 static int arm_override_mode
= -1;
153 /* Number of different reg name sets (options). */
154 static int num_disassembly_options
;
156 /* The standard register names, and all the valid aliases for them. Note
157 that `fp', `sp' and `pc' are not added in this alias list, because they
158 have been added as builtin user registers in
159 std-regs.c:_initialize_frame_reg. */
164 } arm_register_aliases
[] = {
165 /* Basic register numbers. */
182 /* Synonyms (argument and variable registers). */
195 /* Other platform-specific names for r9. */
201 /* Names used by GCC (not listed in the ARM EABI). */
203 /* A special name from the older ATPCS. */
207 static const char *const arm_register_names
[] =
208 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
209 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
210 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
211 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
212 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
213 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
214 "fps", "cpsr" }; /* 24 25 */
216 /* Valid register name styles. */
217 static const char **valid_disassembly_styles
;
219 /* Disassembly style to use. Default to "std" register names. */
220 static const char *disassembly_style
;
222 /* This is used to keep the bfd arch_info in sync with the disassembly
224 static void set_disassembly_style_sfunc(char *, int,
225 struct cmd_list_element
*);
226 static void set_disassembly_style (void);
228 static void convert_from_extended (const struct floatformat
*, const void *,
230 static void convert_to_extended (const struct floatformat
*, void *,
233 static enum register_status
arm_neon_quad_read (struct gdbarch
*gdbarch
,
234 struct regcache
*regcache
,
235 int regnum
, gdb_byte
*buf
);
236 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
237 struct regcache
*regcache
,
238 int regnum
, const gdb_byte
*buf
);
241 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
);
244 /* get_next_pcs operations. */
245 static struct arm_get_next_pcs_ops arm_get_next_pcs_ops
= {
246 arm_get_next_pcs_read_memory_unsigned_integer
,
247 arm_get_next_pcs_syscall_next_pc
,
248 arm_get_next_pcs_addr_bits_remove
,
249 arm_get_next_pcs_is_thumb
,
253 struct arm_prologue_cache
255 /* The stack pointer at the time this frame was created; i.e. the
256 caller's stack pointer when this function was called. It is used
257 to identify this frame. */
260 /* The frame base for this frame is just prev_sp - frame size.
261 FRAMESIZE is the distance from the frame pointer to the
262 initial stack pointer. */
266 /* The register used to hold the frame pointer for this frame. */
269 /* Saved register offsets. */
270 struct trad_frame_saved_reg
*saved_regs
;
273 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
274 CORE_ADDR prologue_start
,
275 CORE_ADDR prologue_end
,
276 struct arm_prologue_cache
*cache
);
278 /* Architecture version for displaced stepping. This effects the behaviour of
279 certain instructions, and really should not be hard-wired. */
281 #define DISPLACED_STEPPING_ARCH_VERSION 5
283 /* Set to true if the 32-bit mode is in use. */
287 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
290 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
292 if (gdbarch_tdep (gdbarch
)->is_m
)
298 /* Determine if the processor is currently executing in Thumb mode. */
301 arm_is_thumb (struct regcache
*regcache
)
304 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regcache
));
306 cpsr
= regcache_raw_get_unsigned (regcache
, ARM_PS_REGNUM
);
308 return (cpsr
& t_bit
) != 0;
311 /* Determine if FRAME is executing in Thumb mode. */
314 arm_frame_is_thumb (struct frame_info
*frame
)
317 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
319 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
320 directly (from a signal frame or dummy frame) or by interpreting
321 the saved LR (from a prologue or DWARF frame). So consult it and
322 trust the unwinders. */
323 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
325 return (cpsr
& t_bit
) != 0;
328 /* Callback for VEC_lower_bound. */
331 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
332 const struct arm_mapping_symbol
*rhs
)
334 return lhs
->value
< rhs
->value
;
337 /* Search for the mapping symbol covering MEMADDR. If one is found,
338 return its type. Otherwise, return 0. If START is non-NULL,
339 set *START to the location of the mapping symbol. */
342 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
344 struct obj_section
*sec
;
346 /* If there are mapping symbols, consult them. */
347 sec
= find_pc_section (memaddr
);
350 struct arm_per_objfile
*data
;
351 VEC(arm_mapping_symbol_s
) *map
;
352 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
356 data
= (struct arm_per_objfile
*) objfile_data (sec
->objfile
,
357 arm_objfile_data_key
);
360 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
361 if (!VEC_empty (arm_mapping_symbol_s
, map
))
363 struct arm_mapping_symbol
*map_sym
;
365 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
366 arm_compare_mapping_symbols
);
368 /* VEC_lower_bound finds the earliest ordered insertion
369 point. If the following symbol starts at this exact
370 address, we use that; otherwise, the preceding
371 mapping symbol covers this address. */
372 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
374 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
375 if (map_sym
->value
== map_key
.value
)
378 *start
= map_sym
->value
+ obj_section_addr (sec
);
379 return map_sym
->type
;
385 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
387 *start
= map_sym
->value
+ obj_section_addr (sec
);
388 return map_sym
->type
;
397 /* Determine if the program counter specified in MEMADDR is in a Thumb
398 function. This function should be called for addresses unrelated to
399 any executing frame; otherwise, prefer arm_frame_is_thumb. */
402 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
404 struct bound_minimal_symbol sym
;
406 struct displaced_step_closure
* dsc
407 = get_displaced_step_closure_by_addr(memaddr
);
409 /* If checking the mode of displaced instruction in copy area, the mode
410 should be determined by instruction on the original address. */
414 fprintf_unfiltered (gdb_stdlog
,
415 "displaced: check mode of %.8lx instead of %.8lx\n",
416 (unsigned long) dsc
->insn_addr
,
417 (unsigned long) memaddr
);
418 memaddr
= dsc
->insn_addr
;
421 /* If bit 0 of the address is set, assume this is a Thumb address. */
422 if (IS_THUMB_ADDR (memaddr
))
425 /* Respect internal mode override if active. */
426 if (arm_override_mode
!= -1)
427 return arm_override_mode
;
429 /* If the user wants to override the symbol table, let him. */
430 if (strcmp (arm_force_mode_string
, "arm") == 0)
432 if (strcmp (arm_force_mode_string
, "thumb") == 0)
435 /* ARM v6-M and v7-M are always in Thumb mode. */
436 if (gdbarch_tdep (gdbarch
)->is_m
)
439 /* If there are mapping symbols, consult them. */
440 type
= arm_find_mapping_symbol (memaddr
, NULL
);
444 /* Thumb functions have a "special" bit set in minimal symbols. */
445 sym
= lookup_minimal_symbol_by_pc (memaddr
);
447 return (MSYMBOL_IS_SPECIAL (sym
.minsym
));
449 /* If the user wants to override the fallback mode, let them. */
450 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
452 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
455 /* If we couldn't find any symbol, but we're talking to a running
456 target, then trust the current value of $cpsr. This lets
457 "display/i $pc" always show the correct mode (though if there is
458 a symbol table we will not reach here, so it still may not be
459 displayed in the mode it will be executed). */
460 if (target_has_registers
)
461 return arm_frame_is_thumb (get_current_frame ());
463 /* Otherwise we're out of luck; we assume ARM. */
467 /* Remove useless bits from addresses in a running program. */
469 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
471 /* On M-profile devices, do not strip the low bit from EXC_RETURN
472 (the magic exception return address). */
473 if (gdbarch_tdep (gdbarch
)->is_m
474 && (val
& 0xfffffff0) == 0xfffffff0)
478 return UNMAKE_THUMB_ADDR (val
);
480 return (val
& 0x03fffffc);
483 /* Return 1 if PC is the start of a compiler helper function which
484 can be safely ignored during prologue skipping. IS_THUMB is true
485 if the function is known to be a Thumb function due to the way it
488 skip_prologue_function (struct gdbarch
*gdbarch
, CORE_ADDR pc
, int is_thumb
)
490 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
491 struct bound_minimal_symbol msym
;
493 msym
= lookup_minimal_symbol_by_pc (pc
);
494 if (msym
.minsym
!= NULL
495 && BMSYMBOL_VALUE_ADDRESS (msym
) == pc
496 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
)
498 const char *name
= MSYMBOL_LINKAGE_NAME (msym
.minsym
);
500 /* The GNU linker's Thumb call stub to foo is named
502 if (strstr (name
, "_from_thumb") != NULL
)
505 /* On soft-float targets, __truncdfsf2 is called to convert promoted
506 arguments to their argument types in non-prototyped
508 if (startswith (name
, "__truncdfsf2"))
510 if (startswith (name
, "__aeabi_d2f"))
513 /* Internal functions related to thread-local storage. */
514 if (startswith (name
, "__tls_get_addr"))
516 if (startswith (name
, "__aeabi_read_tp"))
521 /* If we run against a stripped glibc, we may be unable to identify
522 special functions by name. Check for one important case,
523 __aeabi_read_tp, by comparing the *code* against the default
524 implementation (this is hand-written ARM assembler in glibc). */
527 && read_memory_unsigned_integer (pc
, 4, byte_order_for_code
)
528 == 0xe3e00a0f /* mov r0, #0xffff0fff */
529 && read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
)
530 == 0xe240f01f) /* sub pc, r0, #31 */
537 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
538 the first 16-bit of instruction, and INSN2 is the second 16-bit of
540 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
541 ((bits ((insn1), 0, 3) << 12) \
542 | (bits ((insn1), 10, 10) << 11) \
543 | (bits ((insn2), 12, 14) << 8) \
544 | bits ((insn2), 0, 7))
546 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
547 the 32-bit instruction. */
548 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
549 ((bits ((insn), 16, 19) << 12) \
550 | bits ((insn), 0, 11))
552 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
555 thumb_expand_immediate (unsigned int imm
)
557 unsigned int count
= imm
>> 7;
565 return (imm
& 0xff) | ((imm
& 0xff) << 16);
567 return ((imm
& 0xff) << 8) | ((imm
& 0xff) << 24);
569 return (imm
& 0xff) | ((imm
& 0xff) << 8)
570 | ((imm
& 0xff) << 16) | ((imm
& 0xff) << 24);
573 return (0x80 | (imm
& 0x7f)) << (32 - count
);
576 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
577 epilogue, 0 otherwise. */
580 thumb_instruction_restores_sp (unsigned short insn
)
582 return (insn
== 0x46bd /* mov sp, r7 */
583 || (insn
& 0xff80) == 0xb000 /* add sp, imm */
584 || (insn
& 0xfe00) == 0xbc00); /* pop <registers> */
587 /* Analyze a Thumb prologue, looking for a recognizable stack frame
588 and frame pointer. Scan until we encounter a store that could
589 clobber the stack frame unexpectedly, or an unknown instruction.
590 Return the last address which is definitely safe to skip for an
591 initial breakpoint. */
594 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
595 CORE_ADDR start
, CORE_ADDR limit
,
596 struct arm_prologue_cache
*cache
)
598 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
599 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
602 struct pv_area
*stack
;
603 struct cleanup
*back_to
;
605 CORE_ADDR unrecognized_pc
= 0;
607 for (i
= 0; i
< 16; i
++)
608 regs
[i
] = pv_register (i
, 0);
609 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
610 back_to
= make_cleanup_free_pv_area (stack
);
612 while (start
< limit
)
616 insn
= read_memory_unsigned_integer (start
, 2, byte_order_for_code
);
618 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
623 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
626 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
627 whether to save LR (R14). */
628 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
630 /* Calculate offsets of saved R0-R7 and LR. */
631 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
632 if (mask
& (1 << regno
))
634 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
636 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
639 else if ((insn
& 0xff80) == 0xb080) /* sub sp, #imm */
641 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
642 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
645 else if (thumb_instruction_restores_sp (insn
))
647 /* Don't scan past the epilogue. */
650 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
651 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
653 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
654 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
655 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
657 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
658 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
659 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
661 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
662 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
663 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
664 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
665 regs
[bits (insn
, 6, 8)]);
666 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
667 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
669 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
670 int rm
= bits (insn
, 3, 6);
671 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
673 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
675 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
676 int src_reg
= (insn
& 0x78) >> 3;
677 regs
[dst_reg
] = regs
[src_reg
];
679 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
681 /* Handle stores to the stack. Normally pushes are used,
682 but with GCC -mtpcs-frame, there may be other stores
683 in the prologue to create the frame. */
684 int regno
= (insn
>> 8) & 0x7;
687 offset
= (insn
& 0xff) << 2;
688 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
690 if (pv_area_store_would_trash (stack
, addr
))
693 pv_area_store (stack
, addr
, 4, regs
[regno
]);
695 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
697 int rd
= bits (insn
, 0, 2);
698 int rn
= bits (insn
, 3, 5);
701 offset
= bits (insn
, 6, 10) << 2;
702 addr
= pv_add_constant (regs
[rn
], offset
);
704 if (pv_area_store_would_trash (stack
, addr
))
707 pv_area_store (stack
, addr
, 4, regs
[rd
]);
709 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
710 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
711 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
712 /* Ignore stores of argument registers to the stack. */
714 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
715 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
716 /* Ignore block loads from the stack, potentially copying
717 parameters from memory. */
719 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
720 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
721 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
722 /* Similarly ignore single loads from the stack. */
724 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
725 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
726 /* Skip register copies, i.e. saves to another register
727 instead of the stack. */
729 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
730 /* Recognize constant loads; even with small stacks these are necessary
732 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
733 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
735 /* Constant pool loads, for the same reason. */
736 unsigned int constant
;
739 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
740 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
741 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
743 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instructions. */
745 unsigned short inst2
;
747 inst2
= read_memory_unsigned_integer (start
+ 2, 2,
748 byte_order_for_code
);
750 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
752 /* BL, BLX. Allow some special function calls when
753 skipping the prologue; GCC generates these before
754 storing arguments to the stack. */
756 int j1
, j2
, imm1
, imm2
;
758 imm1
= sbits (insn
, 0, 10);
759 imm2
= bits (inst2
, 0, 10);
760 j1
= bit (inst2
, 13);
761 j2
= bit (inst2
, 11);
763 offset
= ((imm1
<< 12) + (imm2
<< 1));
764 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
766 nextpc
= start
+ 4 + offset
;
767 /* For BLX make sure to clear the low bits. */
768 if (bit (inst2
, 12) == 0)
769 nextpc
= nextpc
& 0xfffffffc;
771 if (!skip_prologue_function (gdbarch
, nextpc
,
772 bit (inst2
, 12) != 0))
776 else if ((insn
& 0xffd0) == 0xe900 /* stmdb Rn{!},
778 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
780 pv_t addr
= regs
[bits (insn
, 0, 3)];
783 if (pv_area_store_would_trash (stack
, addr
))
786 /* Calculate offsets of saved registers. */
787 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
788 if (inst2
& (1 << regno
))
790 addr
= pv_add_constant (addr
, -4);
791 pv_area_store (stack
, addr
, 4, regs
[regno
]);
795 regs
[bits (insn
, 0, 3)] = addr
;
798 else if ((insn
& 0xff50) == 0xe940 /* strd Rt, Rt2,
800 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
802 int regno1
= bits (inst2
, 12, 15);
803 int regno2
= bits (inst2
, 8, 11);
804 pv_t addr
= regs
[bits (insn
, 0, 3)];
806 offset
= inst2
& 0xff;
808 addr
= pv_add_constant (addr
, offset
);
810 addr
= pv_add_constant (addr
, -offset
);
812 if (pv_area_store_would_trash (stack
, addr
))
815 pv_area_store (stack
, addr
, 4, regs
[regno1
]);
816 pv_area_store (stack
, pv_add_constant (addr
, 4),
820 regs
[bits (insn
, 0, 3)] = addr
;
823 else if ((insn
& 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
824 && (inst2
& 0x0c00) == 0x0c00
825 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
827 int regno
= bits (inst2
, 12, 15);
828 pv_t addr
= regs
[bits (insn
, 0, 3)];
830 offset
= inst2
& 0xff;
832 addr
= pv_add_constant (addr
, offset
);
834 addr
= pv_add_constant (addr
, -offset
);
836 if (pv_area_store_would_trash (stack
, addr
))
839 pv_area_store (stack
, addr
, 4, regs
[regno
]);
842 regs
[bits (insn
, 0, 3)] = addr
;
845 else if ((insn
& 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
846 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
848 int regno
= bits (inst2
, 12, 15);
851 offset
= inst2
& 0xfff;
852 addr
= pv_add_constant (regs
[bits (insn
, 0, 3)], offset
);
854 if (pv_area_store_would_trash (stack
, addr
))
857 pv_area_store (stack
, addr
, 4, regs
[regno
]);
860 else if ((insn
& 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
861 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
862 /* Ignore stores of argument registers to the stack. */
865 else if ((insn
& 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
866 && (inst2
& 0x0d00) == 0x0c00
867 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
868 /* Ignore stores of argument registers to the stack. */
871 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!],
873 && (inst2
& 0x8000) == 0x0000
874 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
875 /* Ignore block loads from the stack, potentially copying
876 parameters from memory. */
879 else if ((insn
& 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
881 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
882 /* Similarly ignore dual loads from the stack. */
885 else if ((insn
& 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
886 && (inst2
& 0x0d00) == 0x0c00
887 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
888 /* Similarly ignore single loads from the stack. */
891 else if ((insn
& 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
892 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
893 /* Similarly ignore single loads from the stack. */
896 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
897 && (inst2
& 0x8000) == 0x0000)
899 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
900 | (bits (inst2
, 12, 14) << 8)
901 | bits (inst2
, 0, 7));
903 regs
[bits (inst2
, 8, 11)]
904 = pv_add_constant (regs
[bits (insn
, 0, 3)],
905 thumb_expand_immediate (imm
));
908 else if ((insn
& 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
909 && (inst2
& 0x8000) == 0x0000)
911 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
912 | (bits (inst2
, 12, 14) << 8)
913 | bits (inst2
, 0, 7));
915 regs
[bits (inst2
, 8, 11)]
916 = pv_add_constant (regs
[bits (insn
, 0, 3)], imm
);
919 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
920 && (inst2
& 0x8000) == 0x0000)
922 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
923 | (bits (inst2
, 12, 14) << 8)
924 | bits (inst2
, 0, 7));
926 regs
[bits (inst2
, 8, 11)]
927 = pv_add_constant (regs
[bits (insn
, 0, 3)],
928 - (CORE_ADDR
) thumb_expand_immediate (imm
));
931 else if ((insn
& 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
932 && (inst2
& 0x8000) == 0x0000)
934 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
935 | (bits (inst2
, 12, 14) << 8)
936 | bits (inst2
, 0, 7));
938 regs
[bits (inst2
, 8, 11)]
939 = pv_add_constant (regs
[bits (insn
, 0, 3)], - (CORE_ADDR
) imm
);
942 else if ((insn
& 0xfbff) == 0xf04f) /* mov.w Rd, #const */
944 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
945 | (bits (inst2
, 12, 14) << 8)
946 | bits (inst2
, 0, 7));
948 regs
[bits (inst2
, 8, 11)]
949 = pv_constant (thumb_expand_immediate (imm
));
952 else if ((insn
& 0xfbf0) == 0xf240) /* movw Rd, #const */
955 = EXTRACT_MOVW_MOVT_IMM_T (insn
, inst2
);
957 regs
[bits (inst2
, 8, 11)] = pv_constant (imm
);
960 else if (insn
== 0xea5f /* mov.w Rd,Rm */
961 && (inst2
& 0xf0f0) == 0)
963 int dst_reg
= (inst2
& 0x0f00) >> 8;
964 int src_reg
= inst2
& 0xf;
965 regs
[dst_reg
] = regs
[src_reg
];
968 else if ((insn
& 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
970 /* Constant pool loads. */
971 unsigned int constant
;
974 offset
= bits (inst2
, 0, 11);
976 loc
= start
+ 4 + offset
;
978 loc
= start
+ 4 - offset
;
980 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
981 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
984 else if ((insn
& 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
986 /* Constant pool loads. */
987 unsigned int constant
;
990 offset
= bits (inst2
, 0, 7) << 2;
992 loc
= start
+ 4 + offset
;
994 loc
= start
+ 4 - offset
;
996 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
997 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
999 constant
= read_memory_unsigned_integer (loc
+ 4, 4, byte_order
);
1000 regs
[bits (inst2
, 8, 11)] = pv_constant (constant
);
1003 else if (thumb2_instruction_changes_pc (insn
, inst2
))
1005 /* Don't scan past anything that might change control flow. */
1010 /* The optimizer might shove anything into the prologue,
1011 so we just skip what we don't recognize. */
1012 unrecognized_pc
= start
;
1017 else if (thumb_instruction_changes_pc (insn
))
1019 /* Don't scan past anything that might change control flow. */
1024 /* The optimizer might shove anything into the prologue,
1025 so we just skip what we don't recognize. */
1026 unrecognized_pc
= start
;
1033 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1034 paddress (gdbarch
, start
));
1036 if (unrecognized_pc
== 0)
1037 unrecognized_pc
= start
;
1041 do_cleanups (back_to
);
1042 return unrecognized_pc
;
1045 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1047 /* Frame pointer is fp. Frame size is constant. */
1048 cache
->framereg
= ARM_FP_REGNUM
;
1049 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1051 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
1053 /* Frame pointer is r7. Frame size is constant. */
1054 cache
->framereg
= THUMB_FP_REGNUM
;
1055 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
1059 /* Try the stack pointer... this is a bit desperate. */
1060 cache
->framereg
= ARM_SP_REGNUM
;
1061 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1064 for (i
= 0; i
< 16; i
++)
1065 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
1066 cache
->saved_regs
[i
].addr
= offset
;
1068 do_cleanups (back_to
);
1069 return unrecognized_pc
;
1073 /* Try to analyze the instructions starting from PC, which load symbol
1074 __stack_chk_guard. Return the address of instruction after loading this
1075 symbol, set the dest register number to *BASEREG, and set the size of
1076 instructions for loading symbol in OFFSET. Return 0 if instructions are
1080 arm_analyze_load_stack_chk_guard(CORE_ADDR pc
, struct gdbarch
*gdbarch
,
1081 unsigned int *destreg
, int *offset
)
1083 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1084 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1085 unsigned int low
, high
, address
;
1090 unsigned short insn1
1091 = read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
1093 if ((insn1
& 0xf800) == 0x4800) /* ldr Rd, #immed */
1095 *destreg
= bits (insn1
, 8, 10);
1097 address
= (pc
& 0xfffffffc) + 4 + (bits (insn1
, 0, 7) << 2);
1098 address
= read_memory_unsigned_integer (address
, 4,
1099 byte_order_for_code
);
1101 else if ((insn1
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1103 unsigned short insn2
1104 = read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1106 low
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1109 = read_memory_unsigned_integer (pc
+ 4, 2, byte_order_for_code
);
1111 = read_memory_unsigned_integer (pc
+ 6, 2, byte_order_for_code
);
1113 /* movt Rd, #const */
1114 if ((insn1
& 0xfbc0) == 0xf2c0)
1116 high
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1117 *destreg
= bits (insn2
, 8, 11);
1119 address
= (high
<< 16 | low
);
1126 = read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
1128 if ((insn
& 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1130 address
= bits (insn
, 0, 11) + pc
+ 8;
1131 address
= read_memory_unsigned_integer (address
, 4,
1132 byte_order_for_code
);
1134 *destreg
= bits (insn
, 12, 15);
1137 else if ((insn
& 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1139 low
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1142 = read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
);
1144 if ((insn
& 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1146 high
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1147 *destreg
= bits (insn
, 12, 15);
1149 address
= (high
<< 16 | low
);
1157 /* Try to skip a sequence of instructions used for stack protector. If PC
1158 points to the first instruction of this sequence, return the address of
1159 first instruction after this sequence, otherwise, return original PC.
1161 On arm, this sequence of instructions is composed of mainly three steps,
1162 Step 1: load symbol __stack_chk_guard,
1163 Step 2: load from address of __stack_chk_guard,
1164 Step 3: store it to somewhere else.
1166 Usually, instructions on step 2 and step 3 are the same on various ARM
1167 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1168 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1169 instructions in step 1 vary from different ARM architectures. On ARMv7,
1172 movw Rn, #:lower16:__stack_chk_guard
1173 movt Rn, #:upper16:__stack_chk_guard
1180 .word __stack_chk_guard
1182 Since ldr/str is a very popular instruction, we can't use them as
1183 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1184 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1185 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1188 arm_skip_stack_protector(CORE_ADDR pc
, struct gdbarch
*gdbarch
)
1190 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1191 unsigned int basereg
;
1192 struct bound_minimal_symbol stack_chk_guard
;
1194 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1197 /* Try to parse the instructions in Step 1. */
1198 addr
= arm_analyze_load_stack_chk_guard (pc
, gdbarch
,
1203 stack_chk_guard
= lookup_minimal_symbol_by_pc (addr
);
1204 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1205 Otherwise, this sequence cannot be for stack protector. */
1206 if (stack_chk_guard
.minsym
== NULL
1207 || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard
.minsym
), "__stack_chk_guard"))
1212 unsigned int destreg
;
1214 = read_memory_unsigned_integer (pc
+ offset
, 2, byte_order_for_code
);
1216 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1217 if ((insn
& 0xf800) != 0x6800)
1219 if (bits (insn
, 3, 5) != basereg
)
1221 destreg
= bits (insn
, 0, 2);
1223 insn
= read_memory_unsigned_integer (pc
+ offset
+ 2, 2,
1224 byte_order_for_code
);
1225 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1226 if ((insn
& 0xf800) != 0x6000)
1228 if (destreg
!= bits (insn
, 0, 2))
1233 unsigned int destreg
;
1235 = read_memory_unsigned_integer (pc
+ offset
, 4, byte_order_for_code
);
1237 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1238 if ((insn
& 0x0e500000) != 0x04100000)
1240 if (bits (insn
, 16, 19) != basereg
)
1242 destreg
= bits (insn
, 12, 15);
1243 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1244 insn
= read_memory_unsigned_integer (pc
+ offset
+ 4,
1245 4, byte_order_for_code
);
1246 if ((insn
& 0x0e500000) != 0x04000000)
1248 if (bits (insn
, 12, 15) != destreg
)
1251 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1254 return pc
+ offset
+ 4;
1256 return pc
+ offset
+ 8;
1259 /* Advance the PC across any function entry prologue instructions to
1260 reach some "real" code.
1262 The APCS (ARM Procedure Call Standard) defines the following
1266 [stmfd sp!, {a1,a2,a3,a4}]
1267 stmfd sp!, {...,fp,ip,lr,pc}
1268 [stfe f7, [sp, #-12]!]
1269 [stfe f6, [sp, #-12]!]
1270 [stfe f5, [sp, #-12]!]
1271 [stfe f4, [sp, #-12]!]
1272 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1275 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1277 CORE_ADDR func_addr
, limit_pc
;
1279 /* See if we can determine the end of the prologue via the symbol table.
1280 If so, then return either PC, or the PC after the prologue, whichever
1282 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1284 CORE_ADDR post_prologue_pc
1285 = skip_prologue_using_sal (gdbarch
, func_addr
);
1286 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1288 if (post_prologue_pc
)
1290 = arm_skip_stack_protector (post_prologue_pc
, gdbarch
);
1293 /* GCC always emits a line note before the prologue and another
1294 one after, even if the two are at the same address or on the
1295 same line. Take advantage of this so that we do not need to
1296 know every instruction that might appear in the prologue. We
1297 will have producer information for most binaries; if it is
1298 missing (e.g. for -gstabs), assuming the GNU tools. */
1299 if (post_prologue_pc
1301 || COMPUNIT_PRODUCER (cust
) == NULL
1302 || startswith (COMPUNIT_PRODUCER (cust
), "GNU ")
1303 || startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
1304 return post_prologue_pc
;
1306 if (post_prologue_pc
!= 0)
1308 CORE_ADDR analyzed_limit
;
1310 /* For non-GCC compilers, make sure the entire line is an
1311 acceptable prologue; GDB will round this function's
1312 return value up to the end of the following line so we
1313 can not skip just part of a line (and we do not want to).
1315 RealView does not treat the prologue specially, but does
1316 associate prologue code with the opening brace; so this
1317 lets us skip the first line if we think it is the opening
1319 if (arm_pc_is_thumb (gdbarch
, func_addr
))
1320 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
1321 post_prologue_pc
, NULL
);
1323 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
1324 post_prologue_pc
, NULL
);
1326 if (analyzed_limit
!= post_prologue_pc
)
1329 return post_prologue_pc
;
1333 /* Can't determine prologue from the symbol table, need to examine
1336 /* Find an upper limit on the function prologue using the debug
1337 information. If the debug information could not be used to provide
1338 that bound, then use an arbitrary large number as the upper bound. */
1339 /* Like arm_scan_prologue, stop no later than pc + 64. */
1340 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1342 limit_pc
= pc
+ 64; /* Magic. */
1345 /* Check if this is Thumb code. */
1346 if (arm_pc_is_thumb (gdbarch
, pc
))
1347 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1349 return arm_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1353 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1354 This function decodes a Thumb function prologue to determine:
1355 1) the size of the stack frame
1356 2) which registers are saved on it
1357 3) the offsets of saved regs
1358 4) the offset from the stack pointer to the frame pointer
1360 A typical Thumb function prologue would create this stack frame
1361 (offsets relative to FP)
1362 old SP -> 24 stack parameters
1365 R7 -> 0 local variables (16 bytes)
1366 SP -> -12 additional stack space (12 bytes)
1367 The frame size would thus be 36 bytes, and the frame offset would be
1368 12 bytes. The frame register is R7.
1370 The comments for thumb_skip_prolog() describe the algorithm we use
1371 to detect the end of the prolog. */
1375 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
1376 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
1378 CORE_ADDR prologue_start
;
1379 CORE_ADDR prologue_end
;
1381 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1384 /* See comment in arm_scan_prologue for an explanation of
1386 if (prologue_end
> prologue_start
+ 64)
1388 prologue_end
= prologue_start
+ 64;
1392 /* We're in the boondocks: we have no idea where the start of the
1396 prologue_end
= min (prologue_end
, prev_pc
);
1398 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1401 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1405 arm_instruction_restores_sp (unsigned int insn
)
1407 if (bits (insn
, 28, 31) != INST_NV
)
1409 if ((insn
& 0x0df0f000) == 0x0080d000
1410 /* ADD SP (register or immediate). */
1411 || (insn
& 0x0df0f000) == 0x0040d000
1412 /* SUB SP (register or immediate). */
1413 || (insn
& 0x0ffffff0) == 0x01a0d000
1415 || (insn
& 0x0fff0000) == 0x08bd0000
1417 || (insn
& 0x0fff0000) == 0x049d0000)
1418 /* POP of a single register. */
1425 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1426 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1427 fill it in. Return the first address not recognized as a prologue
1430 We recognize all the instructions typically found in ARM prologues,
1431 plus harmless instructions which can be skipped (either for analysis
1432 purposes, or a more restrictive set that can be skipped when finding
1433 the end of the prologue). */
1436 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1437 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1438 struct arm_prologue_cache
*cache
)
1440 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1442 CORE_ADDR offset
, current_pc
;
1443 pv_t regs
[ARM_FPS_REGNUM
];
1444 struct pv_area
*stack
;
1445 struct cleanup
*back_to
;
1446 CORE_ADDR unrecognized_pc
= 0;
1448 /* Search the prologue looking for instructions that set up the
1449 frame pointer, adjust the stack pointer, and save registers.
1451 Be careful, however, and if it doesn't look like a prologue,
1452 don't try to scan it. If, for instance, a frameless function
1453 begins with stmfd sp!, then we will tell ourselves there is
1454 a frame, which will confuse stack traceback, as well as "finish"
1455 and other operations that rely on a knowledge of the stack
1458 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1459 regs
[regno
] = pv_register (regno
, 0);
1460 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1461 back_to
= make_cleanup_free_pv_area (stack
);
1463 for (current_pc
= prologue_start
;
1464 current_pc
< prologue_end
;
1468 = read_memory_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1470 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1472 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1475 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1476 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1478 unsigned imm
= insn
& 0xff; /* immediate value */
1479 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1480 int rd
= bits (insn
, 12, 15);
1481 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1482 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1485 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1486 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1488 unsigned imm
= insn
& 0xff; /* immediate value */
1489 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1490 int rd
= bits (insn
, 12, 15);
1491 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1492 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1495 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd,
1498 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1500 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1501 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4,
1502 regs
[bits (insn
, 12, 15)]);
1505 else if ((insn
& 0xffff0000) == 0xe92d0000)
1506 /* stmfd sp!, {..., fp, ip, lr, pc}
1508 stmfd sp!, {a1, a2, a3, a4} */
1510 int mask
= insn
& 0xffff;
1512 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1515 /* Calculate offsets of saved registers. */
1516 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1517 if (mask
& (1 << regno
))
1520 = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1521 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1524 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1525 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1526 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1528 /* No need to add this to saved_regs -- it's just an arg reg. */
1531 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1532 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1533 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1535 /* No need to add this to saved_regs -- it's just an arg reg. */
1538 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn,
1540 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1542 /* No need to add this to saved_regs -- it's just arg regs. */
1545 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1547 unsigned imm
= insn
& 0xff; /* immediate value */
1548 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1549 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1550 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1552 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1554 unsigned imm
= insn
& 0xff; /* immediate value */
1555 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1556 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1557 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1559 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?,
1561 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1563 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1566 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1567 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1568 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1570 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1572 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1574 int n_saved_fp_regs
;
1575 unsigned int fp_start_reg
, fp_bound_reg
;
1577 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1580 if ((insn
& 0x800) == 0x800) /* N0 is set */
1582 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1583 n_saved_fp_regs
= 3;
1585 n_saved_fp_regs
= 1;
1589 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1590 n_saved_fp_regs
= 2;
1592 n_saved_fp_regs
= 4;
1595 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1596 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1597 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1599 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1600 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
1601 regs
[fp_start_reg
++]);
1604 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1606 /* Allow some special function calls when skipping the
1607 prologue; GCC generates these before storing arguments to
1609 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1611 if (skip_prologue_function (gdbarch
, dest
, 0))
1616 else if ((insn
& 0xf0000000) != 0xe0000000)
1617 break; /* Condition not true, exit early. */
1618 else if (arm_instruction_changes_pc (insn
))
1619 /* Don't scan past anything that might change control flow. */
1621 else if (arm_instruction_restores_sp (insn
))
1623 /* Don't scan past the epilogue. */
1626 else if ((insn
& 0xfe500000) == 0xe8100000 /* ldm */
1627 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1628 /* Ignore block loads from the stack, potentially copying
1629 parameters from memory. */
1631 else if ((insn
& 0xfc500000) == 0xe4100000
1632 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1633 /* Similarly ignore single loads from the stack. */
1635 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1636 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1637 register instead of the stack. */
1641 /* The optimizer might shove anything into the prologue, if
1642 we build up cache (cache != NULL) from scanning prologue,
1643 we just skip what we don't recognize and scan further to
1644 make cache as complete as possible. However, if we skip
1645 prologue, we'll stop immediately on unrecognized
1647 unrecognized_pc
= current_pc
;
1655 if (unrecognized_pc
== 0)
1656 unrecognized_pc
= current_pc
;
1660 int framereg
, framesize
;
1662 /* The frame size is just the distance from the frame register
1663 to the original stack pointer. */
1664 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1666 /* Frame pointer is fp. */
1667 framereg
= ARM_FP_REGNUM
;
1668 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1672 /* Try the stack pointer... this is a bit desperate. */
1673 framereg
= ARM_SP_REGNUM
;
1674 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1677 cache
->framereg
= framereg
;
1678 cache
->framesize
= framesize
;
1680 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1681 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1682 cache
->saved_regs
[regno
].addr
= offset
;
1686 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1687 paddress (gdbarch
, unrecognized_pc
));
1689 do_cleanups (back_to
);
1690 return unrecognized_pc
;
1694 arm_scan_prologue (struct frame_info
*this_frame
,
1695 struct arm_prologue_cache
*cache
)
1697 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1698 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1699 CORE_ADDR prologue_start
, prologue_end
;
1700 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1701 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1703 /* Assume there is no frame until proven otherwise. */
1704 cache
->framereg
= ARM_SP_REGNUM
;
1705 cache
->framesize
= 0;
1707 /* Check for Thumb prologue. */
1708 if (arm_frame_is_thumb (this_frame
))
1710 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1714 /* Find the function prologue. If we can't find the function in
1715 the symbol table, peek in the stack frame to find the PC. */
1716 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1719 /* One way to find the end of the prologue (which works well
1720 for unoptimized code) is to do the following:
1722 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1725 prologue_end = prev_pc;
1726 else if (sal.end < prologue_end)
1727 prologue_end = sal.end;
1729 This mechanism is very accurate so long as the optimizer
1730 doesn't move any instructions from the function body into the
1731 prologue. If this happens, sal.end will be the last
1732 instruction in the first hunk of prologue code just before
1733 the first instruction that the scheduler has moved from
1734 the body to the prologue.
1736 In order to make sure that we scan all of the prologue
1737 instructions, we use a slightly less accurate mechanism which
1738 may scan more than necessary. To help compensate for this
1739 lack of accuracy, the prologue scanning loop below contains
1740 several clauses which'll cause the loop to terminate early if
1741 an implausible prologue instruction is encountered.
1747 is a suitable endpoint since it accounts for the largest
1748 possible prologue plus up to five instructions inserted by
1751 if (prologue_end
> prologue_start
+ 64)
1753 prologue_end
= prologue_start
+ 64; /* See above. */
1758 /* We have no symbol information. Our only option is to assume this
1759 function has a standard stack frame and the normal frame register.
1760 Then, we can find the value of our frame pointer on entrance to
1761 the callee (or at the present moment if this is the innermost frame).
1762 The value stored there should be the address of the stmfd + 8. */
1763 CORE_ADDR frame_loc
;
1764 LONGEST return_value
;
1766 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
1767 if (!safe_read_memory_integer (frame_loc
, 4, byte_order
, &return_value
))
1771 prologue_start
= gdbarch_addr_bits_remove
1772 (gdbarch
, return_value
) - 8;
1773 prologue_end
= prologue_start
+ 64; /* See above. */
1777 if (prev_pc
< prologue_end
)
1778 prologue_end
= prev_pc
;
1780 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1783 static struct arm_prologue_cache
*
1784 arm_make_prologue_cache (struct frame_info
*this_frame
)
1787 struct arm_prologue_cache
*cache
;
1788 CORE_ADDR unwound_fp
;
1790 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1791 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1793 arm_scan_prologue (this_frame
, cache
);
1795 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
1796 if (unwound_fp
== 0)
1799 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
1801 /* Calculate actual addresses of saved registers using offsets
1802 determined by arm_scan_prologue. */
1803 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
1804 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
1805 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
1810 /* Implementation of the stop_reason hook for arm_prologue frames. */
1812 static enum unwind_stop_reason
1813 arm_prologue_unwind_stop_reason (struct frame_info
*this_frame
,
1816 struct arm_prologue_cache
*cache
;
1819 if (*this_cache
== NULL
)
1820 *this_cache
= arm_make_prologue_cache (this_frame
);
1821 cache
= (struct arm_prologue_cache
*) *this_cache
;
1823 /* This is meant to halt the backtrace at "_start". */
1824 pc
= get_frame_pc (this_frame
);
1825 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1826 return UNWIND_OUTERMOST
;
1828 /* If we've hit a wall, stop. */
1829 if (cache
->prev_sp
== 0)
1830 return UNWIND_OUTERMOST
;
1832 return UNWIND_NO_REASON
;
1835 /* Our frame ID for a normal frame is the current function's starting PC
1836 and the caller's SP when we were called. */
1839 arm_prologue_this_id (struct frame_info
*this_frame
,
1841 struct frame_id
*this_id
)
1843 struct arm_prologue_cache
*cache
;
1847 if (*this_cache
== NULL
)
1848 *this_cache
= arm_make_prologue_cache (this_frame
);
1849 cache
= (struct arm_prologue_cache
*) *this_cache
;
1851 /* Use function start address as part of the frame ID. If we cannot
1852 identify the start address (due to missing symbol information),
1853 fall back to just using the current PC. */
1854 pc
= get_frame_pc (this_frame
);
1855 func
= get_frame_func (this_frame
);
1859 id
= frame_id_build (cache
->prev_sp
, func
);
1863 static struct value
*
1864 arm_prologue_prev_register (struct frame_info
*this_frame
,
1868 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1869 struct arm_prologue_cache
*cache
;
1871 if (*this_cache
== NULL
)
1872 *this_cache
= arm_make_prologue_cache (this_frame
);
1873 cache
= (struct arm_prologue_cache
*) *this_cache
;
1875 /* If we are asked to unwind the PC, then we need to return the LR
1876 instead. The prologue may save PC, but it will point into this
1877 frame's prologue, not the next frame's resume location. Also
1878 strip the saved T bit. A valid LR may have the low bit set, but
1879 a valid PC never does. */
1880 if (prev_regnum
== ARM_PC_REGNUM
)
1884 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1885 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1886 arm_addr_bits_remove (gdbarch
, lr
));
1889 /* SP is generally not saved to the stack, but this frame is
1890 identified by the next frame's stack pointer at the time of the call.
1891 The value was already reconstructed into PREV_SP. */
1892 if (prev_regnum
== ARM_SP_REGNUM
)
1893 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1895 /* The CPSR may have been changed by the call instruction and by the
1896 called function. The only bit we can reconstruct is the T bit,
1897 by checking the low bit of LR as of the call. This is a reliable
1898 indicator of Thumb-ness except for some ARM v4T pre-interworking
1899 Thumb code, which could get away with a clear low bit as long as
1900 the called function did not use bx. Guess that all other
1901 bits are unchanged; the condition flags are presumably lost,
1902 but the processor status is likely valid. */
1903 if (prev_regnum
== ARM_PS_REGNUM
)
1906 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
1908 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1909 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1910 if (IS_THUMB_ADDR (lr
))
1914 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1917 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1921 struct frame_unwind arm_prologue_unwind
= {
1923 arm_prologue_unwind_stop_reason
,
1924 arm_prologue_this_id
,
1925 arm_prologue_prev_register
,
1927 default_frame_sniffer
1930 /* Maintain a list of ARM exception table entries per objfile, similar to the
1931 list of mapping symbols. We only cache entries for standard ARM-defined
1932 personality routines; the cache will contain only the frame unwinding
1933 instructions associated with the entry (not the descriptors). */
1935 static const struct objfile_data
*arm_exidx_data_key
;
1937 struct arm_exidx_entry
1942 typedef struct arm_exidx_entry arm_exidx_entry_s
;
1943 DEF_VEC_O(arm_exidx_entry_s
);
1945 struct arm_exidx_data
1947 VEC(arm_exidx_entry_s
) **section_maps
;
1951 arm_exidx_data_free (struct objfile
*objfile
, void *arg
)
1953 struct arm_exidx_data
*data
= (struct arm_exidx_data
*) arg
;
1956 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
1957 VEC_free (arm_exidx_entry_s
, data
->section_maps
[i
]);
1961 arm_compare_exidx_entries (const struct arm_exidx_entry
*lhs
,
1962 const struct arm_exidx_entry
*rhs
)
1964 return lhs
->addr
< rhs
->addr
;
1967 static struct obj_section
*
1968 arm_obj_section_from_vma (struct objfile
*objfile
, bfd_vma vma
)
1970 struct obj_section
*osect
;
1972 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
1973 if (bfd_get_section_flags (objfile
->obfd
,
1974 osect
->the_bfd_section
) & SEC_ALLOC
)
1976 bfd_vma start
, size
;
1977 start
= bfd_get_section_vma (objfile
->obfd
, osect
->the_bfd_section
);
1978 size
= bfd_get_section_size (osect
->the_bfd_section
);
1980 if (start
<= vma
&& vma
< start
+ size
)
1987 /* Parse contents of exception table and exception index sections
1988 of OBJFILE, and fill in the exception table entry cache.
1990 For each entry that refers to a standard ARM-defined personality
1991 routine, extract the frame unwinding instructions (from either
1992 the index or the table section). The unwinding instructions
1994 - extracting them from the rest of the table data
1995 - converting to host endianness
1996 - appending the implicit 0xb0 ("Finish") code
1998 The extracted and normalized instructions are stored for later
1999 retrieval by the arm_find_exidx_entry routine. */
2002 arm_exidx_new_objfile (struct objfile
*objfile
)
2004 struct cleanup
*cleanups
;
2005 struct arm_exidx_data
*data
;
2006 asection
*exidx
, *extab
;
2007 bfd_vma exidx_vma
= 0, extab_vma
= 0;
2008 bfd_size_type exidx_size
= 0, extab_size
= 0;
2009 gdb_byte
*exidx_data
= NULL
, *extab_data
= NULL
;
2012 /* If we've already touched this file, do nothing. */
2013 if (!objfile
|| objfile_data (objfile
, arm_exidx_data_key
) != NULL
)
2015 cleanups
= make_cleanup (null_cleanup
, NULL
);
2017 /* Read contents of exception table and index. */
2018 exidx
= bfd_get_section_by_name (objfile
->obfd
, ELF_STRING_ARM_unwind
);
2021 exidx_vma
= bfd_section_vma (objfile
->obfd
, exidx
);
2022 exidx_size
= bfd_get_section_size (exidx
);
2023 exidx_data
= (gdb_byte
*) xmalloc (exidx_size
);
2024 make_cleanup (xfree
, exidx_data
);
2026 if (!bfd_get_section_contents (objfile
->obfd
, exidx
,
2027 exidx_data
, 0, exidx_size
))
2029 do_cleanups (cleanups
);
2034 extab
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.extab");
2037 extab_vma
= bfd_section_vma (objfile
->obfd
, extab
);
2038 extab_size
= bfd_get_section_size (extab
);
2039 extab_data
= (gdb_byte
*) xmalloc (extab_size
);
2040 make_cleanup (xfree
, extab_data
);
2042 if (!bfd_get_section_contents (objfile
->obfd
, extab
,
2043 extab_data
, 0, extab_size
))
2045 do_cleanups (cleanups
);
2050 /* Allocate exception table data structure. */
2051 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
, struct arm_exidx_data
);
2052 set_objfile_data (objfile
, arm_exidx_data_key
, data
);
2053 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2054 objfile
->obfd
->section_count
,
2055 VEC(arm_exidx_entry_s
) *);
2057 /* Fill in exception table. */
2058 for (i
= 0; i
< exidx_size
/ 8; i
++)
2060 struct arm_exidx_entry new_exidx_entry
;
2061 bfd_vma idx
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8);
2062 bfd_vma val
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8 + 4);
2063 bfd_vma addr
= 0, word
= 0;
2064 int n_bytes
= 0, n_words
= 0;
2065 struct obj_section
*sec
;
2066 gdb_byte
*entry
= NULL
;
2068 /* Extract address of start of function. */
2069 idx
= ((idx
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2070 idx
+= exidx_vma
+ i
* 8;
2072 /* Find section containing function and compute section offset. */
2073 sec
= arm_obj_section_from_vma (objfile
, idx
);
2076 idx
-= bfd_get_section_vma (objfile
->obfd
, sec
->the_bfd_section
);
2078 /* Determine address of exception table entry. */
2081 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2083 else if ((val
& 0xff000000) == 0x80000000)
2085 /* Exception table entry embedded in .ARM.exidx
2086 -- must be short form. */
2090 else if (!(val
& 0x80000000))
2092 /* Exception table entry in .ARM.extab. */
2093 addr
= ((val
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2094 addr
+= exidx_vma
+ i
* 8 + 4;
2096 if (addr
>= extab_vma
&& addr
+ 4 <= extab_vma
+ extab_size
)
2098 word
= bfd_h_get_32 (objfile
->obfd
,
2099 extab_data
+ addr
- extab_vma
);
2102 if ((word
& 0xff000000) == 0x80000000)
2107 else if ((word
& 0xff000000) == 0x81000000
2108 || (word
& 0xff000000) == 0x82000000)
2112 n_words
= ((word
>> 16) & 0xff);
2114 else if (!(word
& 0x80000000))
2117 struct obj_section
*pers_sec
;
2118 int gnu_personality
= 0;
2120 /* Custom personality routine. */
2121 pers
= ((word
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2122 pers
= UNMAKE_THUMB_ADDR (pers
+ addr
- 4);
2124 /* Check whether we've got one of the variants of the
2125 GNU personality routines. */
2126 pers_sec
= arm_obj_section_from_vma (objfile
, pers
);
2129 static const char *personality
[] =
2131 "__gcc_personality_v0",
2132 "__gxx_personality_v0",
2133 "__gcj_personality_v0",
2134 "__gnu_objc_personality_v0",
2138 CORE_ADDR pc
= pers
+ obj_section_offset (pers_sec
);
2141 for (k
= 0; personality
[k
]; k
++)
2142 if (lookup_minimal_symbol_by_pc_name
2143 (pc
, personality
[k
], objfile
))
2145 gnu_personality
= 1;
2150 /* If so, the next word contains a word count in the high
2151 byte, followed by the same unwind instructions as the
2152 pre-defined forms. */
2154 && addr
+ 4 <= extab_vma
+ extab_size
)
2156 word
= bfd_h_get_32 (objfile
->obfd
,
2157 extab_data
+ addr
- extab_vma
);
2160 n_words
= ((word
>> 24) & 0xff);
2166 /* Sanity check address. */
2168 if (addr
< extab_vma
|| addr
+ 4 * n_words
> extab_vma
+ extab_size
)
2169 n_words
= n_bytes
= 0;
2171 /* The unwind instructions reside in WORD (only the N_BYTES least
2172 significant bytes are valid), followed by N_WORDS words in the
2173 extab section starting at ADDR. */
2174 if (n_bytes
|| n_words
)
2177 = (gdb_byte
*) obstack_alloc (&objfile
->objfile_obstack
,
2178 n_bytes
+ n_words
* 4 + 1);
2181 *p
++ = (gdb_byte
) ((word
>> (8 * n_bytes
)) & 0xff);
2185 word
= bfd_h_get_32 (objfile
->obfd
,
2186 extab_data
+ addr
- extab_vma
);
2189 *p
++ = (gdb_byte
) ((word
>> 24) & 0xff);
2190 *p
++ = (gdb_byte
) ((word
>> 16) & 0xff);
2191 *p
++ = (gdb_byte
) ((word
>> 8) & 0xff);
2192 *p
++ = (gdb_byte
) (word
& 0xff);
2195 /* Implied "Finish" to terminate the list. */
2199 /* Push entry onto vector. They are guaranteed to always
2200 appear in order of increasing addresses. */
2201 new_exidx_entry
.addr
= idx
;
2202 new_exidx_entry
.entry
= entry
;
2203 VEC_safe_push (arm_exidx_entry_s
,
2204 data
->section_maps
[sec
->the_bfd_section
->index
],
2208 do_cleanups (cleanups
);
2211 /* Search for the exception table entry covering MEMADDR. If one is found,
2212 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2213 set *START to the start of the region covered by this entry. */
2216 arm_find_exidx_entry (CORE_ADDR memaddr
, CORE_ADDR
*start
)
2218 struct obj_section
*sec
;
2220 sec
= find_pc_section (memaddr
);
2223 struct arm_exidx_data
*data
;
2224 VEC(arm_exidx_entry_s
) *map
;
2225 struct arm_exidx_entry map_key
= { memaddr
- obj_section_addr (sec
), 0 };
2228 data
= ((struct arm_exidx_data
*)
2229 objfile_data (sec
->objfile
, arm_exidx_data_key
));
2232 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
2233 if (!VEC_empty (arm_exidx_entry_s
, map
))
2235 struct arm_exidx_entry
*map_sym
;
2237 idx
= VEC_lower_bound (arm_exidx_entry_s
, map
, &map_key
,
2238 arm_compare_exidx_entries
);
2240 /* VEC_lower_bound finds the earliest ordered insertion
2241 point. If the following symbol starts at this exact
2242 address, we use that; otherwise, the preceding
2243 exception table entry covers this address. */
2244 if (idx
< VEC_length (arm_exidx_entry_s
, map
))
2246 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
);
2247 if (map_sym
->addr
== map_key
.addr
)
2250 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2251 return map_sym
->entry
;
2257 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
- 1);
2259 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2260 return map_sym
->entry
;
2269 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2270 instruction list from the ARM exception table entry ENTRY, allocate and
2271 return a prologue cache structure describing how to unwind this frame.
2273 Return NULL if the unwinding instruction list contains a "spare",
2274 "reserved" or "refuse to unwind" instruction as defined in section
2275 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2276 for the ARM Architecture" document. */
2278 static struct arm_prologue_cache
*
2279 arm_exidx_fill_cache (struct frame_info
*this_frame
, gdb_byte
*entry
)
2284 struct arm_prologue_cache
*cache
;
2285 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2286 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2292 /* Whenever we reload SP, we actually have to retrieve its
2293 actual value in the current frame. */
2296 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2298 int reg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2299 vsp
= get_frame_register_unsigned (this_frame
, reg
);
2303 CORE_ADDR addr
= cache
->saved_regs
[ARM_SP_REGNUM
].addr
;
2304 vsp
= get_frame_memory_unsigned (this_frame
, addr
, 4);
2310 /* Decode next unwind instruction. */
2313 if ((insn
& 0xc0) == 0)
2315 int offset
= insn
& 0x3f;
2316 vsp
+= (offset
<< 2) + 4;
2318 else if ((insn
& 0xc0) == 0x40)
2320 int offset
= insn
& 0x3f;
2321 vsp
-= (offset
<< 2) + 4;
2323 else if ((insn
& 0xf0) == 0x80)
2325 int mask
= ((insn
& 0xf) << 8) | *entry
++;
2328 /* The special case of an all-zero mask identifies
2329 "Refuse to unwind". We return NULL to fall back
2330 to the prologue analyzer. */
2334 /* Pop registers r4..r15 under mask. */
2335 for (i
= 0; i
< 12; i
++)
2336 if (mask
& (1 << i
))
2338 cache
->saved_regs
[4 + i
].addr
= vsp
;
2342 /* Special-case popping SP -- we need to reload vsp. */
2343 if (mask
& (1 << (ARM_SP_REGNUM
- 4)))
2346 else if ((insn
& 0xf0) == 0x90)
2348 int reg
= insn
& 0xf;
2350 /* Reserved cases. */
2351 if (reg
== ARM_SP_REGNUM
|| reg
== ARM_PC_REGNUM
)
2354 /* Set SP from another register and mark VSP for reload. */
2355 cache
->saved_regs
[ARM_SP_REGNUM
] = cache
->saved_regs
[reg
];
2358 else if ((insn
& 0xf0) == 0xa0)
2360 int count
= insn
& 0x7;
2361 int pop_lr
= (insn
& 0x8) != 0;
2364 /* Pop r4..r[4+count]. */
2365 for (i
= 0; i
<= count
; i
++)
2367 cache
->saved_regs
[4 + i
].addr
= vsp
;
2371 /* If indicated by flag, pop LR as well. */
2374 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= vsp
;
2378 else if (insn
== 0xb0)
2380 /* We could only have updated PC by popping into it; if so, it
2381 will show up as address. Otherwise, copy LR into PC. */
2382 if (!trad_frame_addr_p (cache
->saved_regs
, ARM_PC_REGNUM
))
2383 cache
->saved_regs
[ARM_PC_REGNUM
]
2384 = cache
->saved_regs
[ARM_LR_REGNUM
];
2389 else if (insn
== 0xb1)
2391 int mask
= *entry
++;
2394 /* All-zero mask and mask >= 16 is "spare". */
2395 if (mask
== 0 || mask
>= 16)
2398 /* Pop r0..r3 under mask. */
2399 for (i
= 0; i
< 4; i
++)
2400 if (mask
& (1 << i
))
2402 cache
->saved_regs
[i
].addr
= vsp
;
2406 else if (insn
== 0xb2)
2408 ULONGEST offset
= 0;
2413 offset
|= (*entry
& 0x7f) << shift
;
2416 while (*entry
++ & 0x80);
2418 vsp
+= 0x204 + (offset
<< 2);
2420 else if (insn
== 0xb3)
2422 int start
= *entry
>> 4;
2423 int count
= (*entry
++) & 0xf;
2426 /* Only registers D0..D15 are valid here. */
2427 if (start
+ count
>= 16)
2430 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2431 for (i
= 0; i
<= count
; i
++)
2433 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2437 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2440 else if ((insn
& 0xf8) == 0xb8)
2442 int count
= insn
& 0x7;
2445 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2446 for (i
= 0; i
<= count
; i
++)
2448 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2452 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2455 else if (insn
== 0xc6)
2457 int start
= *entry
>> 4;
2458 int count
= (*entry
++) & 0xf;
2461 /* Only registers WR0..WR15 are valid. */
2462 if (start
+ count
>= 16)
2465 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2466 for (i
= 0; i
<= count
; i
++)
2468 cache
->saved_regs
[ARM_WR0_REGNUM
+ start
+ i
].addr
= vsp
;
2472 else if (insn
== 0xc7)
2474 int mask
= *entry
++;
2477 /* All-zero mask and mask >= 16 is "spare". */
2478 if (mask
== 0 || mask
>= 16)
2481 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2482 for (i
= 0; i
< 4; i
++)
2483 if (mask
& (1 << i
))
2485 cache
->saved_regs
[ARM_WCGR0_REGNUM
+ i
].addr
= vsp
;
2489 else if ((insn
& 0xf8) == 0xc0)
2491 int count
= insn
& 0x7;
2494 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2495 for (i
= 0; i
<= count
; i
++)
2497 cache
->saved_regs
[ARM_WR0_REGNUM
+ 10 + i
].addr
= vsp
;
2501 else if (insn
== 0xc8)
2503 int start
= *entry
>> 4;
2504 int count
= (*entry
++) & 0xf;
2507 /* Only registers D0..D31 are valid. */
2508 if (start
+ count
>= 16)
2511 /* Pop VFP double-precision registers
2512 D[16+start]..D[16+start+count]. */
2513 for (i
= 0; i
<= count
; i
++)
2515 cache
->saved_regs
[ARM_D0_REGNUM
+ 16 + start
+ i
].addr
= vsp
;
2519 else if (insn
== 0xc9)
2521 int start
= *entry
>> 4;
2522 int count
= (*entry
++) & 0xf;
2525 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2526 for (i
= 0; i
<= count
; i
++)
2528 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2532 else if ((insn
& 0xf8) == 0xd0)
2534 int count
= insn
& 0x7;
2537 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2538 for (i
= 0; i
<= count
; i
++)
2540 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2546 /* Everything else is "spare". */
2551 /* If we restore SP from a register, assume this was the frame register.
2552 Otherwise just fall back to SP as frame register. */
2553 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2554 cache
->framereg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2556 cache
->framereg
= ARM_SP_REGNUM
;
2558 /* Determine offset to previous frame. */
2560 = vsp
- get_frame_register_unsigned (this_frame
, cache
->framereg
);
2562 /* We already got the previous SP. */
2563 cache
->prev_sp
= vsp
;
2568 /* Unwinding via ARM exception table entries. Note that the sniffer
2569 already computes a filled-in prologue cache, which is then used
2570 with the same arm_prologue_this_id and arm_prologue_prev_register
2571 routines also used for prologue-parsing based unwinding. */
2574 arm_exidx_unwind_sniffer (const struct frame_unwind
*self
,
2575 struct frame_info
*this_frame
,
2576 void **this_prologue_cache
)
2578 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2579 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2580 CORE_ADDR addr_in_block
, exidx_region
, func_start
;
2581 struct arm_prologue_cache
*cache
;
2584 /* See if we have an ARM exception table entry covering this address. */
2585 addr_in_block
= get_frame_address_in_block (this_frame
);
2586 entry
= arm_find_exidx_entry (addr_in_block
, &exidx_region
);
2590 /* The ARM exception table does not describe unwind information
2591 for arbitrary PC values, but is guaranteed to be correct only
2592 at call sites. We have to decide here whether we want to use
2593 ARM exception table information for this frame, or fall back
2594 to using prologue parsing. (Note that if we have DWARF CFI,
2595 this sniffer isn't even called -- CFI is always preferred.)
2597 Before we make this decision, however, we check whether we
2598 actually have *symbol* information for the current frame.
2599 If not, prologue parsing would not work anyway, so we might
2600 as well use the exception table and hope for the best. */
2601 if (find_pc_partial_function (addr_in_block
, NULL
, &func_start
, NULL
))
2605 /* If the next frame is "normal", we are at a call site in this
2606 frame, so exception information is guaranteed to be valid. */
2607 if (get_next_frame (this_frame
)
2608 && get_frame_type (get_next_frame (this_frame
)) == NORMAL_FRAME
)
2611 /* We also assume exception information is valid if we're currently
2612 blocked in a system call. The system library is supposed to
2613 ensure this, so that e.g. pthread cancellation works. */
2614 if (arm_frame_is_thumb (this_frame
))
2618 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 2, 2,
2619 byte_order_for_code
, &insn
)
2620 && (insn
& 0xff00) == 0xdf00 /* svc */)
2627 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 4, 4,
2628 byte_order_for_code
, &insn
)
2629 && (insn
& 0x0f000000) == 0x0f000000 /* svc */)
2633 /* Bail out if we don't know that exception information is valid. */
2637 /* The ARM exception index does not mark the *end* of the region
2638 covered by the entry, and some functions will not have any entry.
2639 To correctly recognize the end of the covered region, the linker
2640 should have inserted dummy records with a CANTUNWIND marker.
2642 Unfortunately, current versions of GNU ld do not reliably do
2643 this, and thus we may have found an incorrect entry above.
2644 As a (temporary) sanity check, we only use the entry if it
2645 lies *within* the bounds of the function. Note that this check
2646 might reject perfectly valid entries that just happen to cover
2647 multiple functions; therefore this check ought to be removed
2648 once the linker is fixed. */
2649 if (func_start
> exidx_region
)
2653 /* Decode the list of unwinding instructions into a prologue cache.
2654 Note that this may fail due to e.g. a "refuse to unwind" code. */
2655 cache
= arm_exidx_fill_cache (this_frame
, entry
);
2659 *this_prologue_cache
= cache
;
2663 struct frame_unwind arm_exidx_unwind
= {
2665 default_frame_unwind_stop_reason
,
2666 arm_prologue_this_id
,
2667 arm_prologue_prev_register
,
2669 arm_exidx_unwind_sniffer
2672 static struct arm_prologue_cache
*
2673 arm_make_epilogue_frame_cache (struct frame_info
*this_frame
)
2675 struct arm_prologue_cache
*cache
;
2679 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2680 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2682 /* Still rely on the offset calculated from prologue. */
2683 arm_scan_prologue (this_frame
, cache
);
2685 /* Since we are in epilogue, the SP has been restored. */
2686 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2688 /* Calculate actual addresses of saved registers using offsets
2689 determined by arm_scan_prologue. */
2690 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
2691 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
2692 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
2697 /* Implementation of function hook 'this_id' in
2698 'struct frame_uwnind' for epilogue unwinder. */
2701 arm_epilogue_frame_this_id (struct frame_info
*this_frame
,
2703 struct frame_id
*this_id
)
2705 struct arm_prologue_cache
*cache
;
2708 if (*this_cache
== NULL
)
2709 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2710 cache
= (struct arm_prologue_cache
*) *this_cache
;
2712 /* Use function start address as part of the frame ID. If we cannot
2713 identify the start address (due to missing symbol information),
2714 fall back to just using the current PC. */
2715 pc
= get_frame_pc (this_frame
);
2716 func
= get_frame_func (this_frame
);
2720 (*this_id
) = frame_id_build (cache
->prev_sp
, pc
);
2723 /* Implementation of function hook 'prev_register' in
2724 'struct frame_uwnind' for epilogue unwinder. */
2726 static struct value
*
2727 arm_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2728 void **this_cache
, int regnum
)
2730 struct arm_prologue_cache
*cache
;
2732 if (*this_cache
== NULL
)
2733 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2734 cache
= (struct arm_prologue_cache
*) *this_cache
;
2736 return arm_prologue_prev_register (this_frame
, this_cache
, regnum
);
2739 static int arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
,
2741 static int thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
,
2744 /* Implementation of function hook 'sniffer' in
2745 'struct frame_uwnind' for epilogue unwinder. */
2748 arm_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2749 struct frame_info
*this_frame
,
2750 void **this_prologue_cache
)
2752 if (frame_relative_level (this_frame
) == 0)
2754 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2755 CORE_ADDR pc
= get_frame_pc (this_frame
);
2757 if (arm_frame_is_thumb (this_frame
))
2758 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
2760 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
2766 /* Frame unwinder from epilogue. */
2768 static const struct frame_unwind arm_epilogue_frame_unwind
=
2771 default_frame_unwind_stop_reason
,
2772 arm_epilogue_frame_this_id
,
2773 arm_epilogue_frame_prev_register
,
2775 arm_epilogue_frame_sniffer
,
2778 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2779 trampoline, return the target PC. Otherwise return 0.
2781 void call0a (char c, short s, int i, long l) {}
2785 (*pointer_to_call0a) (c, s, i, l);
2788 Instead of calling a stub library function _call_via_xx (xx is
2789 the register name), GCC may inline the trampoline in the object
2790 file as below (register r2 has the address of call0a).
2793 .type main, %function
2802 The trampoline 'bx r2' doesn't belong to main. */
2805 arm_skip_bx_reg (struct frame_info
*frame
, CORE_ADDR pc
)
2807 /* The heuristics of recognizing such trampoline is that FRAME is
2808 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2809 if (arm_frame_is_thumb (frame
))
2813 if (target_read_memory (pc
, buf
, 2) == 0)
2815 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2816 enum bfd_endian byte_order_for_code
2817 = gdbarch_byte_order_for_code (gdbarch
);
2819 = extract_unsigned_integer (buf
, 2, byte_order_for_code
);
2821 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
2824 = get_frame_register_unsigned (frame
, bits (insn
, 3, 6));
2826 /* Clear the LSB so that gdb core sets step-resume
2827 breakpoint at the right address. */
2828 return UNMAKE_THUMB_ADDR (dest
);
2836 static struct arm_prologue_cache
*
2837 arm_make_stub_cache (struct frame_info
*this_frame
)
2839 struct arm_prologue_cache
*cache
;
2841 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2842 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2844 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2849 /* Our frame ID for a stub frame is the current SP and LR. */
2852 arm_stub_this_id (struct frame_info
*this_frame
,
2854 struct frame_id
*this_id
)
2856 struct arm_prologue_cache
*cache
;
2858 if (*this_cache
== NULL
)
2859 *this_cache
= arm_make_stub_cache (this_frame
);
2860 cache
= (struct arm_prologue_cache
*) *this_cache
;
2862 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
2866 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
2867 struct frame_info
*this_frame
,
2868 void **this_prologue_cache
)
2870 CORE_ADDR addr_in_block
;
2872 CORE_ADDR pc
, start_addr
;
2875 addr_in_block
= get_frame_address_in_block (this_frame
);
2876 pc
= get_frame_pc (this_frame
);
2877 if (in_plt_section (addr_in_block
)
2878 /* We also use the stub winder if the target memory is unreadable
2879 to avoid having the prologue unwinder trying to read it. */
2880 || target_read_memory (pc
, dummy
, 4) != 0)
2883 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0
2884 && arm_skip_bx_reg (this_frame
, pc
) != 0)
2890 struct frame_unwind arm_stub_unwind
= {
2892 default_frame_unwind_stop_reason
,
2894 arm_prologue_prev_register
,
2896 arm_stub_unwind_sniffer
2899 /* Put here the code to store, into CACHE->saved_regs, the addresses
2900 of the saved registers of frame described by THIS_FRAME. CACHE is
2903 static struct arm_prologue_cache
*
2904 arm_m_exception_cache (struct frame_info
*this_frame
)
2906 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2907 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2908 struct arm_prologue_cache
*cache
;
2909 CORE_ADDR unwound_sp
;
2912 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2913 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2915 unwound_sp
= get_frame_register_unsigned (this_frame
,
2918 /* The hardware saves eight 32-bit words, comprising xPSR,
2919 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
2920 "B1.5.6 Exception entry behavior" in
2921 "ARMv7-M Architecture Reference Manual". */
2922 cache
->saved_regs
[0].addr
= unwound_sp
;
2923 cache
->saved_regs
[1].addr
= unwound_sp
+ 4;
2924 cache
->saved_regs
[2].addr
= unwound_sp
+ 8;
2925 cache
->saved_regs
[3].addr
= unwound_sp
+ 12;
2926 cache
->saved_regs
[12].addr
= unwound_sp
+ 16;
2927 cache
->saved_regs
[14].addr
= unwound_sp
+ 20;
2928 cache
->saved_regs
[15].addr
= unwound_sp
+ 24;
2929 cache
->saved_regs
[ARM_PS_REGNUM
].addr
= unwound_sp
+ 28;
2931 /* If bit 9 of the saved xPSR is set, then there is a four-byte
2932 aligner between the top of the 32-byte stack frame and the
2933 previous context's stack pointer. */
2934 cache
->prev_sp
= unwound_sp
+ 32;
2935 if (safe_read_memory_integer (unwound_sp
+ 28, 4, byte_order
, &xpsr
)
2936 && (xpsr
& (1 << 9)) != 0)
2937 cache
->prev_sp
+= 4;
2942 /* Implementation of function hook 'this_id' in
2943 'struct frame_uwnind'. */
2946 arm_m_exception_this_id (struct frame_info
*this_frame
,
2948 struct frame_id
*this_id
)
2950 struct arm_prologue_cache
*cache
;
2952 if (*this_cache
== NULL
)
2953 *this_cache
= arm_m_exception_cache (this_frame
);
2954 cache
= (struct arm_prologue_cache
*) *this_cache
;
2956 /* Our frame ID for a stub frame is the current SP and LR. */
2957 *this_id
= frame_id_build (cache
->prev_sp
,
2958 get_frame_pc (this_frame
));
2961 /* Implementation of function hook 'prev_register' in
2962 'struct frame_uwnind'. */
2964 static struct value
*
2965 arm_m_exception_prev_register (struct frame_info
*this_frame
,
2969 struct arm_prologue_cache
*cache
;
2971 if (*this_cache
== NULL
)
2972 *this_cache
= arm_m_exception_cache (this_frame
);
2973 cache
= (struct arm_prologue_cache
*) *this_cache
;
2975 /* The value was already reconstructed into PREV_SP. */
2976 if (prev_regnum
== ARM_SP_REGNUM
)
2977 return frame_unwind_got_constant (this_frame
, prev_regnum
,
2980 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
2984 /* Implementation of function hook 'sniffer' in
2985 'struct frame_uwnind'. */
2988 arm_m_exception_unwind_sniffer (const struct frame_unwind
*self
,
2989 struct frame_info
*this_frame
,
2990 void **this_prologue_cache
)
2992 CORE_ADDR this_pc
= get_frame_pc (this_frame
);
2994 /* No need to check is_m; this sniffer is only registered for
2995 M-profile architectures. */
2997 /* Exception frames return to one of these magic PCs. Other values
2998 are not defined as of v7-M. See details in "B1.5.8 Exception
2999 return behavior" in "ARMv7-M Architecture Reference Manual". */
3000 if (this_pc
== 0xfffffff1 || this_pc
== 0xfffffff9
3001 || this_pc
== 0xfffffffd)
3007 /* Frame unwinder for M-profile exceptions. */
3009 struct frame_unwind arm_m_exception_unwind
=
3012 default_frame_unwind_stop_reason
,
3013 arm_m_exception_this_id
,
3014 arm_m_exception_prev_register
,
3016 arm_m_exception_unwind_sniffer
3020 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
3022 struct arm_prologue_cache
*cache
;
3024 if (*this_cache
== NULL
)
3025 *this_cache
= arm_make_prologue_cache (this_frame
);
3026 cache
= (struct arm_prologue_cache
*) *this_cache
;
3028 return cache
->prev_sp
- cache
->framesize
;
3031 struct frame_base arm_normal_base
= {
3032 &arm_prologue_unwind
,
3033 arm_normal_frame_base
,
3034 arm_normal_frame_base
,
3035 arm_normal_frame_base
3038 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3039 dummy frame. The frame ID's base needs to match the TOS value
3040 saved by save_dummy_frame_tos() and returned from
3041 arm_push_dummy_call, and the PC needs to match the dummy frame's
3044 static struct frame_id
3045 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3047 return frame_id_build (get_frame_register_unsigned (this_frame
,
3049 get_frame_pc (this_frame
));
3052 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3053 be used to construct the previous frame's ID, after looking up the
3054 containing function). */
3057 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3060 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
3061 return arm_addr_bits_remove (gdbarch
, pc
);
3065 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3067 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
3070 static struct value
*
3071 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
3074 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
3076 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
3081 /* The PC is normally copied from the return column, which
3082 describes saves of LR. However, that version may have an
3083 extra bit set to indicate Thumb state. The bit is not
3085 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3086 return frame_unwind_got_constant (this_frame
, regnum
,
3087 arm_addr_bits_remove (gdbarch
, lr
));
3090 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3091 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
3092 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3093 if (IS_THUMB_ADDR (lr
))
3097 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
3100 internal_error (__FILE__
, __LINE__
,
3101 _("Unexpected register %d"), regnum
);
3106 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3107 struct dwarf2_frame_state_reg
*reg
,
3108 struct frame_info
*this_frame
)
3114 reg
->how
= DWARF2_FRAME_REG_FN
;
3115 reg
->loc
.fn
= arm_dwarf2_prev_register
;
3118 reg
->how
= DWARF2_FRAME_REG_CFA
;
3123 /* Implement the stack_frame_destroyed_p gdbarch method. */
3126 thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3128 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3129 unsigned int insn
, insn2
;
3130 int found_return
= 0, found_stack_adjust
= 0;
3131 CORE_ADDR func_start
, func_end
;
3135 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3138 if (func_end
- pc
> 4 * 4)
3140 /* There shouldn't be more than four instructions in epilogue.
3141 If PC is still 16 bytes away from FUNC_END, it isn't in
3146 /* The epilogue is a sequence of instructions along the following lines:
3148 - add stack frame size to SP or FP
3149 - [if frame pointer used] restore SP from FP
3150 - restore registers from SP [may include PC]
3151 - a return-type instruction [if PC wasn't already restored]
3153 In a first pass, we scan forward from the current PC and verify the
3154 instructions we find as compatible with this sequence, ending in a
3157 However, this is not sufficient to distinguish indirect function calls
3158 within a function from indirect tail calls in the epilogue in some cases.
3159 Therefore, if we didn't already find any SP-changing instruction during
3160 forward scan, we add a backward scanning heuristic to ensure we actually
3161 are in the epilogue. */
3164 while (scan_pc
< func_end
&& !found_return
)
3166 if (target_read_memory (scan_pc
, buf
, 2))
3170 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3172 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3174 else if (insn
== 0x46f7) /* mov pc, lr */
3176 else if (thumb_instruction_restores_sp (insn
))
3178 if ((insn
& 0xff00) == 0xbd00) /* pop <registers, PC> */
3181 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instruction */
3183 if (target_read_memory (scan_pc
, buf
, 2))
3187 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3189 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3191 if (insn2
& 0x8000) /* <registers> include PC. */
3194 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3195 && (insn2
& 0x0fff) == 0x0b04)
3197 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
3200 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3201 && (insn2
& 0x0e00) == 0x0a00)
3213 /* Since any instruction in the epilogue sequence, with the possible
3214 exception of return itself, updates the stack pointer, we need to
3215 scan backwards for at most one instruction. Try either a 16-bit or
3216 a 32-bit instruction. This is just a heuristic, so we do not worry
3217 too much about false positives. */
3219 if (pc
- 4 < func_start
)
3221 if (target_read_memory (pc
- 4, buf
, 4))
3224 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3225 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
3227 if (thumb_instruction_restores_sp (insn2
))
3228 found_stack_adjust
= 1;
3229 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3230 found_stack_adjust
= 1;
3231 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3232 && (insn2
& 0x0fff) == 0x0b04)
3233 found_stack_adjust
= 1;
3234 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3235 && (insn2
& 0x0e00) == 0x0a00)
3236 found_stack_adjust
= 1;
3238 return found_stack_adjust
;
3242 arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3244 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3247 CORE_ADDR func_start
, func_end
;
3249 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3252 /* We are in the epilogue if the previous instruction was a stack
3253 adjustment and the next instruction is a possible return (bx, mov
3254 pc, or pop). We could have to scan backwards to find the stack
3255 adjustment, or forwards to find the return, but this is a decent
3256 approximation. First scan forwards. */
3259 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3260 if (bits (insn
, 28, 31) != INST_NV
)
3262 if ((insn
& 0x0ffffff0) == 0x012fff10)
3265 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
3268 else if ((insn
& 0x0fff0000) == 0x08bd0000
3269 && (insn
& 0x0000c000) != 0)
3270 /* POP (LDMIA), including PC or LR. */
3277 /* Scan backwards. This is just a heuristic, so do not worry about
3278 false positives from mode changes. */
3280 if (pc
< func_start
+ 4)
3283 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
3284 if (arm_instruction_restores_sp (insn
))
3290 /* Implement the stack_frame_destroyed_p gdbarch method. */
3293 arm_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3295 if (arm_pc_is_thumb (gdbarch
, pc
))
3296 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
3298 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
3301 /* When arguments must be pushed onto the stack, they go on in reverse
3302 order. The code below implements a FILO (stack) to do this. */
3307 struct stack_item
*prev
;
3311 static struct stack_item
*
3312 push_stack_item (struct stack_item
*prev
, const gdb_byte
*contents
, int len
)
3314 struct stack_item
*si
;
3315 si
= XNEW (struct stack_item
);
3316 si
->data
= (gdb_byte
*) xmalloc (len
);
3319 memcpy (si
->data
, contents
, len
);
3323 static struct stack_item
*
3324 pop_stack_item (struct stack_item
*si
)
3326 struct stack_item
*dead
= si
;
3334 /* Return the alignment (in bytes) of the given type. */
3337 arm_type_align (struct type
*t
)
3343 t
= check_typedef (t
);
3344 switch (TYPE_CODE (t
))
3347 /* Should never happen. */
3348 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
3352 case TYPE_CODE_ENUM
:
3356 case TYPE_CODE_RANGE
:
3358 case TYPE_CODE_CHAR
:
3359 case TYPE_CODE_BOOL
:
3360 return TYPE_LENGTH (t
);
3362 case TYPE_CODE_ARRAY
:
3363 if (TYPE_VECTOR (t
))
3365 /* Use the natural alignment for vector types (the same for
3366 scalar type), but the maximum alignment is 64-bit. */
3367 if (TYPE_LENGTH (t
) > 8)
3370 return TYPE_LENGTH (t
);
3373 return arm_type_align (TYPE_TARGET_TYPE (t
));
3374 case TYPE_CODE_COMPLEX
:
3375 return arm_type_align (TYPE_TARGET_TYPE (t
));
3377 case TYPE_CODE_STRUCT
:
3378 case TYPE_CODE_UNION
:
3380 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
3382 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
3390 /* Possible base types for a candidate for passing and returning in
3393 enum arm_vfp_cprc_base_type
3402 /* The length of one element of base type B. */
3405 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
3409 case VFP_CPRC_SINGLE
:
3411 case VFP_CPRC_DOUBLE
:
3413 case VFP_CPRC_VEC64
:
3415 case VFP_CPRC_VEC128
:
3418 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3423 /* The character ('s', 'd' or 'q') for the type of VFP register used
3424 for passing base type B. */
3427 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
3431 case VFP_CPRC_SINGLE
:
3433 case VFP_CPRC_DOUBLE
:
3435 case VFP_CPRC_VEC64
:
3437 case VFP_CPRC_VEC128
:
3440 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3445 /* Determine whether T may be part of a candidate for passing and
3446 returning in VFP registers, ignoring the limit on the total number
3447 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3448 classification of the first valid component found; if it is not
3449 VFP_CPRC_UNKNOWN, all components must have the same classification
3450 as *BASE_TYPE. If it is found that T contains a type not permitted
3451 for passing and returning in VFP registers, a type differently
3452 classified from *BASE_TYPE, or two types differently classified
3453 from each other, return -1, otherwise return the total number of
3454 base-type elements found (possibly 0 in an empty structure or
3455 array). Vector types are not currently supported, matching the
3456 generic AAPCS support. */
3459 arm_vfp_cprc_sub_candidate (struct type
*t
,
3460 enum arm_vfp_cprc_base_type
*base_type
)
3462 t
= check_typedef (t
);
3463 switch (TYPE_CODE (t
))
3466 switch (TYPE_LENGTH (t
))
3469 if (*base_type
== VFP_CPRC_UNKNOWN
)
3470 *base_type
= VFP_CPRC_SINGLE
;
3471 else if (*base_type
!= VFP_CPRC_SINGLE
)
3476 if (*base_type
== VFP_CPRC_UNKNOWN
)
3477 *base_type
= VFP_CPRC_DOUBLE
;
3478 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3487 case TYPE_CODE_COMPLEX
:
3488 /* Arguments of complex T where T is one of the types float or
3489 double get treated as if they are implemented as:
3498 switch (TYPE_LENGTH (t
))
3501 if (*base_type
== VFP_CPRC_UNKNOWN
)
3502 *base_type
= VFP_CPRC_SINGLE
;
3503 else if (*base_type
!= VFP_CPRC_SINGLE
)
3508 if (*base_type
== VFP_CPRC_UNKNOWN
)
3509 *base_type
= VFP_CPRC_DOUBLE
;
3510 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3519 case TYPE_CODE_ARRAY
:
3521 if (TYPE_VECTOR (t
))
3523 /* A 64-bit or 128-bit containerized vector type are VFP
3525 switch (TYPE_LENGTH (t
))
3528 if (*base_type
== VFP_CPRC_UNKNOWN
)
3529 *base_type
= VFP_CPRC_VEC64
;
3532 if (*base_type
== VFP_CPRC_UNKNOWN
)
3533 *base_type
= VFP_CPRC_VEC128
;
3544 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
),
3548 if (TYPE_LENGTH (t
) == 0)
3550 gdb_assert (count
== 0);
3553 else if (count
== 0)
3555 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3556 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
3557 return TYPE_LENGTH (t
) / unitlen
;
3562 case TYPE_CODE_STRUCT
:
3567 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3569 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3571 if (sub_count
== -1)
3575 if (TYPE_LENGTH (t
) == 0)
3577 gdb_assert (count
== 0);
3580 else if (count
== 0)
3582 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3583 if (TYPE_LENGTH (t
) != unitlen
* count
)
3588 case TYPE_CODE_UNION
:
3593 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3595 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3597 if (sub_count
== -1)
3599 count
= (count
> sub_count
? count
: sub_count
);
3601 if (TYPE_LENGTH (t
) == 0)
3603 gdb_assert (count
== 0);
3606 else if (count
== 0)
3608 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3609 if (TYPE_LENGTH (t
) != unitlen
* count
)
3621 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3622 if passed to or returned from a non-variadic function with the VFP
3623 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3624 *BASE_TYPE to the base type for T and *COUNT to the number of
3625 elements of that base type before returning. */
3628 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
3631 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
3632 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
3633 if (c
<= 0 || c
> 4)
3640 /* Return 1 if the VFP ABI should be used for passing arguments to and
3641 returning values from a function of type FUNC_TYPE, 0
3645 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
3647 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3648 /* Variadic functions always use the base ABI. Assume that functions
3649 without debug info are not variadic. */
3650 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
3652 /* The VFP ABI is only supported as a variant of AAPCS. */
3653 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
3655 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
3658 /* We currently only support passing parameters in integer registers, which
3659 conforms with GCC's default model, and VFP argument passing following
3660 the VFP variant of AAPCS. Several other variants exist and
3661 we should probably support some of them based on the selected ABI. */
3664 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3665 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3666 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3667 CORE_ADDR struct_addr
)
3669 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3673 struct stack_item
*si
= NULL
;
3676 unsigned vfp_regs_free
= (1 << 16) - 1;
3678 /* Determine the type of this function and whether the VFP ABI
3680 ftype
= check_typedef (value_type (function
));
3681 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
3682 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
3683 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
3685 /* Set the return address. For the ARM, the return breakpoint is
3686 always at BP_ADDR. */
3687 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
3689 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
3691 /* Walk through the list of args and determine how large a temporary
3692 stack is required. Need to take care here as structs may be
3693 passed on the stack, and we have to push them. */
3696 argreg
= ARM_A1_REGNUM
;
3699 /* The struct_return pointer occupies the first parameter
3700 passing register. */
3704 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
3705 gdbarch_register_name (gdbarch
, argreg
),
3706 paddress (gdbarch
, struct_addr
));
3707 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
3711 for (argnum
= 0; argnum
< nargs
; argnum
++)
3714 struct type
*arg_type
;
3715 struct type
*target_type
;
3716 enum type_code typecode
;
3717 const bfd_byte
*val
;
3719 enum arm_vfp_cprc_base_type vfp_base_type
;
3721 int may_use_core_reg
= 1;
3723 arg_type
= check_typedef (value_type (args
[argnum
]));
3724 len
= TYPE_LENGTH (arg_type
);
3725 target_type
= TYPE_TARGET_TYPE (arg_type
);
3726 typecode
= TYPE_CODE (arg_type
);
3727 val
= value_contents (args
[argnum
]);
3729 align
= arm_type_align (arg_type
);
3730 /* Round alignment up to a whole number of words. */
3731 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
3732 /* Different ABIs have different maximum alignments. */
3733 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
3735 /* The APCS ABI only requires word alignment. */
3736 align
= INT_REGISTER_SIZE
;
3740 /* The AAPCS requires at most doubleword alignment. */
3741 if (align
> INT_REGISTER_SIZE
* 2)
3742 align
= INT_REGISTER_SIZE
* 2;
3746 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
3754 /* Because this is a CPRC it cannot go in a core register or
3755 cause a core register to be skipped for alignment.
3756 Either it goes in VFP registers and the rest of this loop
3757 iteration is skipped for this argument, or it goes on the
3758 stack (and the stack alignment code is correct for this
3760 may_use_core_reg
= 0;
3762 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
3763 shift
= unit_length
/ 4;
3764 mask
= (1 << (shift
* vfp_base_count
)) - 1;
3765 for (regno
= 0; regno
< 16; regno
+= shift
)
3766 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
3775 vfp_regs_free
&= ~(mask
<< regno
);
3776 reg_scaled
= regno
/ shift
;
3777 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
3778 for (i
= 0; i
< vfp_base_count
; i
++)
3782 if (reg_char
== 'q')
3783 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
3784 val
+ i
* unit_length
);
3787 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d",
3788 reg_char
, reg_scaled
+ i
);
3789 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3791 regcache_cooked_write (regcache
, regnum
,
3792 val
+ i
* unit_length
);
3799 /* This CPRC could not go in VFP registers, so all VFP
3800 registers are now marked as used. */
3805 /* Push stack padding for dowubleword alignment. */
3806 if (nstack
& (align
- 1))
3808 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3809 nstack
+= INT_REGISTER_SIZE
;
3812 /* Doubleword aligned quantities must go in even register pairs. */
3813 if (may_use_core_reg
3814 && argreg
<= ARM_LAST_ARG_REGNUM
3815 && align
> INT_REGISTER_SIZE
3819 /* If the argument is a pointer to a function, and it is a
3820 Thumb function, create a LOCAL copy of the value and set
3821 the THUMB bit in it. */
3822 if (TYPE_CODE_PTR
== typecode
3823 && target_type
!= NULL
3824 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
3826 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
3827 if (arm_pc_is_thumb (gdbarch
, regval
))
3829 bfd_byte
*copy
= (bfd_byte
*) alloca (len
);
3830 store_unsigned_integer (copy
, len
, byte_order
,
3831 MAKE_THUMB_ADDR (regval
));
3836 /* Copy the argument to general registers or the stack in
3837 register-sized pieces. Large arguments are split between
3838 registers and stack. */
3841 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
3843 = extract_unsigned_integer (val
, partial_len
, byte_order
);
3845 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
3847 /* The argument is being passed in a general purpose
3849 if (byte_order
== BFD_ENDIAN_BIG
)
3850 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
3852 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
3854 gdbarch_register_name
3856 phex (regval
, INT_REGISTER_SIZE
));
3857 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3862 gdb_byte buf
[INT_REGISTER_SIZE
];
3864 memset (buf
, 0, sizeof (buf
));
3865 store_unsigned_integer (buf
, partial_len
, byte_order
, regval
);
3867 /* Push the arguments onto the stack. */
3869 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
3871 si
= push_stack_item (si
, buf
, INT_REGISTER_SIZE
);
3872 nstack
+= INT_REGISTER_SIZE
;
3879 /* If we have an odd number of words to push, then decrement the stack
3880 by one word now, so first stack argument will be dword aligned. */
3887 write_memory (sp
, si
->data
, si
->len
);
3888 si
= pop_stack_item (si
);
3891 /* Finally, update teh SP register. */
3892 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
3898 /* Always align the frame to an 8-byte boundary. This is required on
3899 some platforms and harmless on the rest. */
3902 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3904 /* Align the stack to eight bytes. */
3905 return sp
& ~ (CORE_ADDR
) 7;
3909 print_fpu_flags (struct ui_file
*file
, int flags
)
3911 if (flags
& (1 << 0))
3912 fputs_filtered ("IVO ", file
);
3913 if (flags
& (1 << 1))
3914 fputs_filtered ("DVZ ", file
);
3915 if (flags
& (1 << 2))
3916 fputs_filtered ("OFL ", file
);
3917 if (flags
& (1 << 3))
3918 fputs_filtered ("UFL ", file
);
3919 if (flags
& (1 << 4))
3920 fputs_filtered ("INX ", file
);
3921 fputc_filtered ('\n', file
);
3924 /* Print interesting information about the floating point processor
3925 (if present) or emulator. */
3927 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
3928 struct frame_info
*frame
, const char *args
)
3930 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
3933 type
= (status
>> 24) & 127;
3934 if (status
& (1 << 31))
3935 fprintf_filtered (file
, _("Hardware FPU type %d\n"), type
);
3937 fprintf_filtered (file
, _("Software FPU type %d\n"), type
);
3938 /* i18n: [floating point unit] mask */
3939 fputs_filtered (_("mask: "), file
);
3940 print_fpu_flags (file
, status
>> 16);
3941 /* i18n: [floating point unit] flags */
3942 fputs_filtered (_("flags: "), file
);
3943 print_fpu_flags (file
, status
);
3946 /* Construct the ARM extended floating point type. */
3947 static struct type
*
3948 arm_ext_type (struct gdbarch
*gdbarch
)
3950 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3952 if (!tdep
->arm_ext_type
)
3954 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
3955 floatformats_arm_ext
);
3957 return tdep
->arm_ext_type
;
3960 static struct type
*
3961 arm_neon_double_type (struct gdbarch
*gdbarch
)
3963 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3965 if (tdep
->neon_double_type
== NULL
)
3967 struct type
*t
, *elem
;
3969 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
3971 elem
= builtin_type (gdbarch
)->builtin_uint8
;
3972 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
3973 elem
= builtin_type (gdbarch
)->builtin_uint16
;
3974 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
3975 elem
= builtin_type (gdbarch
)->builtin_uint32
;
3976 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
3977 elem
= builtin_type (gdbarch
)->builtin_uint64
;
3978 append_composite_type_field (t
, "u64", elem
);
3979 elem
= builtin_type (gdbarch
)->builtin_float
;
3980 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
3981 elem
= builtin_type (gdbarch
)->builtin_double
;
3982 append_composite_type_field (t
, "f64", elem
);
3984 TYPE_VECTOR (t
) = 1;
3985 TYPE_NAME (t
) = "neon_d";
3986 tdep
->neon_double_type
= t
;
3989 return tdep
->neon_double_type
;
3992 /* FIXME: The vector types are not correctly ordered on big-endian
3993 targets. Just as s0 is the low bits of d0, d0[0] is also the low
3994 bits of d0 - regardless of what unit size is being held in d0. So
3995 the offset of the first uint8 in d0 is 7, but the offset of the
3996 first float is 4. This code works as-is for little-endian
3999 static struct type
*
4000 arm_neon_quad_type (struct gdbarch
*gdbarch
)
4002 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4004 if (tdep
->neon_quad_type
== NULL
)
4006 struct type
*t
, *elem
;
4008 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
4010 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4011 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
4012 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4013 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
4014 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4015 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
4016 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4017 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
4018 elem
= builtin_type (gdbarch
)->builtin_float
;
4019 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
4020 elem
= builtin_type (gdbarch
)->builtin_double
;
4021 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
4023 TYPE_VECTOR (t
) = 1;
4024 TYPE_NAME (t
) = "neon_q";
4025 tdep
->neon_quad_type
= t
;
4028 return tdep
->neon_quad_type
;
4031 /* Return the GDB type object for the "standard" data type of data in
4034 static struct type
*
4035 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
4037 int num_regs
= gdbarch_num_regs (gdbarch
);
4039 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
4040 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
4041 return builtin_type (gdbarch
)->builtin_float
;
4043 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
4044 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
4045 return arm_neon_quad_type (gdbarch
);
4047 /* If the target description has register information, we are only
4048 in this function so that we can override the types of
4049 double-precision registers for NEON. */
4050 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
4052 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
4054 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
4055 && TYPE_CODE (t
) == TYPE_CODE_FLT
4056 && gdbarch_tdep (gdbarch
)->have_neon
)
4057 return arm_neon_double_type (gdbarch
);
4062 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
4064 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
4065 return builtin_type (gdbarch
)->builtin_void
;
4067 return arm_ext_type (gdbarch
);
4069 else if (regnum
== ARM_SP_REGNUM
)
4070 return builtin_type (gdbarch
)->builtin_data_ptr
;
4071 else if (regnum
== ARM_PC_REGNUM
)
4072 return builtin_type (gdbarch
)->builtin_func_ptr
;
4073 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
4074 /* These registers are only supported on targets which supply
4075 an XML description. */
4076 return builtin_type (gdbarch
)->builtin_int0
;
4078 return builtin_type (gdbarch
)->builtin_uint32
;
4081 /* Map a DWARF register REGNUM onto the appropriate GDB register
4085 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
4087 /* Core integer regs. */
4088 if (reg
>= 0 && reg
<= 15)
4091 /* Legacy FPA encoding. These were once used in a way which
4092 overlapped with VFP register numbering, so their use is
4093 discouraged, but GDB doesn't support the ARM toolchain
4094 which used them for VFP. */
4095 if (reg
>= 16 && reg
<= 23)
4096 return ARM_F0_REGNUM
+ reg
- 16;
4098 /* New assignments for the FPA registers. */
4099 if (reg
>= 96 && reg
<= 103)
4100 return ARM_F0_REGNUM
+ reg
- 96;
4102 /* WMMX register assignments. */
4103 if (reg
>= 104 && reg
<= 111)
4104 return ARM_WCGR0_REGNUM
+ reg
- 104;
4106 if (reg
>= 112 && reg
<= 127)
4107 return ARM_WR0_REGNUM
+ reg
- 112;
4109 if (reg
>= 192 && reg
<= 199)
4110 return ARM_WC0_REGNUM
+ reg
- 192;
4112 /* VFP v2 registers. A double precision value is actually
4113 in d1 rather than s2, but the ABI only defines numbering
4114 for the single precision registers. This will "just work"
4115 in GDB for little endian targets (we'll read eight bytes,
4116 starting in s0 and then progressing to s1), but will be
4117 reversed on big endian targets with VFP. This won't
4118 be a problem for the new Neon quad registers; you're supposed
4119 to use DW_OP_piece for those. */
4120 if (reg
>= 64 && reg
<= 95)
4124 xsnprintf (name_buf
, sizeof (name_buf
), "s%d", reg
- 64);
4125 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4129 /* VFP v3 / Neon registers. This range is also used for VFP v2
4130 registers, except that it now describes d0 instead of s0. */
4131 if (reg
>= 256 && reg
<= 287)
4135 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", reg
- 256);
4136 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4143 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4145 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
4148 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
4150 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
4151 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
4153 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
4154 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
4156 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
4157 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
4159 if (reg
< NUM_GREGS
)
4160 return SIM_ARM_R0_REGNUM
+ reg
;
4163 if (reg
< NUM_FREGS
)
4164 return SIM_ARM_FP0_REGNUM
+ reg
;
4167 if (reg
< NUM_SREGS
)
4168 return SIM_ARM_FPS_REGNUM
+ reg
;
4171 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
4174 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4175 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4176 It is thought that this is is the floating-point register format on
4177 little-endian systems. */
4180 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
4181 void *dbl
, int endianess
)
4185 if (endianess
== BFD_ENDIAN_BIG
)
4186 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
4188 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4190 floatformat_from_doublest (fmt
, &d
, dbl
);
4194 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
4199 floatformat_to_doublest (fmt
, ptr
, &d
);
4200 if (endianess
== BFD_ENDIAN_BIG
)
4201 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
4203 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4207 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
4208 of the appropriate mode (as encoded in the PC value), even if this
4209 differs from what would be expected according to the symbol tables. */
4212 arm_insert_single_step_breakpoint (struct gdbarch
*gdbarch
,
4213 struct address_space
*aspace
,
4216 struct cleanup
*old_chain
4217 = make_cleanup_restore_integer (&arm_override_mode
);
4219 arm_override_mode
= IS_THUMB_ADDR (pc
);
4220 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4222 insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
4224 do_cleanups (old_chain
);
4227 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
4228 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
4229 NULL if an error occurs. BUF is freed. */
4232 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
4233 int old_len
, int new_len
)
4236 int bytes_to_read
= new_len
- old_len
;
4238 new_buf
= (gdb_byte
*) xmalloc (new_len
);
4239 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
4241 if (target_read_memory (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
4249 /* An IT block is at most the 2-byte IT instruction followed by
4250 four 4-byte instructions. The furthest back we must search to
4251 find an IT block that affects the current instruction is thus
4252 2 + 3 * 4 == 14 bytes. */
4253 #define MAX_IT_BLOCK_PREFIX 14
4255 /* Use a quick scan if there are more than this many bytes of
4257 #define IT_SCAN_THRESHOLD 32
4259 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
4260 A breakpoint in an IT block may not be hit, depending on the
4263 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
4267 CORE_ADDR boundary
, func_start
;
4269 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
4270 int i
, any
, last_it
, last_it_count
;
4272 /* If we are using BKPT breakpoints, none of this is necessary. */
4273 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
4276 /* ARM mode does not have this problem. */
4277 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
4280 /* We are setting a breakpoint in Thumb code that could potentially
4281 contain an IT block. The first step is to find how much Thumb
4282 code there is; we do not need to read outside of known Thumb
4284 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
4286 /* Thumb-2 code must have mapping symbols to have a chance. */
4289 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
4291 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
4292 && func_start
> boundary
)
4293 boundary
= func_start
;
4295 /* Search for a candidate IT instruction. We have to do some fancy
4296 footwork to distinguish a real IT instruction from the second
4297 half of a 32-bit instruction, but there is no need for that if
4298 there's no candidate. */
4299 buf_len
= min (bpaddr
- boundary
, MAX_IT_BLOCK_PREFIX
);
4301 /* No room for an IT instruction. */
4304 buf
= (gdb_byte
*) xmalloc (buf_len
);
4305 if (target_read_memory (bpaddr
- buf_len
, buf
, buf_len
) != 0)
4308 for (i
= 0; i
< buf_len
; i
+= 2)
4310 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4311 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4324 /* OK, the code bytes before this instruction contain at least one
4325 halfword which resembles an IT instruction. We know that it's
4326 Thumb code, but there are still two possibilities. Either the
4327 halfword really is an IT instruction, or it is the second half of
4328 a 32-bit Thumb instruction. The only way we can tell is to
4329 scan forwards from a known instruction boundary. */
4330 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
4334 /* There's a lot of code before this instruction. Start with an
4335 optimistic search; it's easy to recognize halfwords that can
4336 not be the start of a 32-bit instruction, and use that to
4337 lock on to the instruction boundaries. */
4338 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
4341 buf_len
= IT_SCAN_THRESHOLD
;
4344 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
4346 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4347 if (thumb_insn_size (inst1
) == 2)
4354 /* At this point, if DEFINITE, BUF[I] is the first place we
4355 are sure that we know the instruction boundaries, and it is far
4356 enough from BPADDR that we could not miss an IT instruction
4357 affecting BPADDR. If ! DEFINITE, give up - start from a
4361 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
,
4365 buf_len
= bpaddr
- boundary
;
4371 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
4374 buf_len
= bpaddr
- boundary
;
4378 /* Scan forwards. Find the last IT instruction before BPADDR. */
4383 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4385 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4390 else if (inst1
& 0x0002)
4392 else if (inst1
& 0x0004)
4397 i
+= thumb_insn_size (inst1
);
4403 /* There wasn't really an IT instruction after all. */
4406 if (last_it_count
< 1)
4407 /* It was too far away. */
4410 /* This really is a trouble spot. Move the breakpoint to the IT
4412 return bpaddr
- buf_len
+ last_it
;
4415 /* ARM displaced stepping support.
4417 Generally ARM displaced stepping works as follows:
4419 1. When an instruction is to be single-stepped, it is first decoded by
4420 arm_process_displaced_insn. Depending on the type of instruction, it is
4421 then copied to a scratch location, possibly in a modified form. The
4422 copy_* set of functions performs such modification, as necessary. A
4423 breakpoint is placed after the modified instruction in the scratch space
4424 to return control to GDB. Note in particular that instructions which
4425 modify the PC will no longer do so after modification.
4427 2. The instruction is single-stepped, by setting the PC to the scratch
4428 location address, and resuming. Control returns to GDB when the
4431 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
4432 function used for the current instruction. This function's job is to
4433 put the CPU/memory state back to what it would have been if the
4434 instruction had been executed unmodified in its original location. */
4436 /* NOP instruction (mov r0, r0). */
4437 #define ARM_NOP 0xe1a00000
4438 #define THUMB_NOP 0x4600
4440 /* Helper for register reads for displaced stepping. In particular, this
4441 returns the PC as it would be seen by the instruction at its original
4445 displaced_read_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4449 CORE_ADDR from
= dsc
->insn_addr
;
4451 if (regno
== ARM_PC_REGNUM
)
4453 /* Compute pipeline offset:
4454 - When executing an ARM instruction, PC reads as the address of the
4455 current instruction plus 8.
4456 - When executing a Thumb instruction, PC reads as the address of the
4457 current instruction plus 4. */
4464 if (debug_displaced
)
4465 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
4466 (unsigned long) from
);
4467 return (ULONGEST
) from
;
4471 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
4472 if (debug_displaced
)
4473 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
4474 regno
, (unsigned long) ret
);
4480 displaced_in_arm_mode (struct regcache
*regs
)
4483 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
4485 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4487 return (ps
& t_bit
) == 0;
4490 /* Write to the PC as from a branch instruction. */
4493 branch_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4497 /* Note: If bits 0/1 are set, this branch would be unpredictable for
4498 architecture versions < 6. */
4499 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4500 val
& ~(ULONGEST
) 0x3);
4502 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4503 val
& ~(ULONGEST
) 0x1);
4506 /* Write to the PC as from a branch-exchange instruction. */
4509 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
4512 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
4514 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4518 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
4519 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
4521 else if ((val
& 2) == 0)
4523 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4524 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
4528 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
4529 mode, align dest to 4 bytes). */
4530 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
4531 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4532 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
4536 /* Write to the PC as if from a load instruction. */
4539 load_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4542 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
4543 bx_write_pc (regs
, val
);
4545 branch_write_pc (regs
, dsc
, val
);
4548 /* Write to the PC as if from an ALU instruction. */
4551 alu_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4554 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && !dsc
->is_thumb
)
4555 bx_write_pc (regs
, val
);
4557 branch_write_pc (regs
, dsc
, val
);
4560 /* Helper for writing to registers for displaced stepping. Writing to the PC
4561 has a varying effects depending on the instruction which does the write:
4562 this is controlled by the WRITE_PC argument. */
4565 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4566 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
4568 if (regno
== ARM_PC_REGNUM
)
4570 if (debug_displaced
)
4571 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
4572 (unsigned long) val
);
4575 case BRANCH_WRITE_PC
:
4576 branch_write_pc (regs
, dsc
, val
);
4580 bx_write_pc (regs
, val
);
4584 load_write_pc (regs
, dsc
, val
);
4588 alu_write_pc (regs
, dsc
, val
);
4591 case CANNOT_WRITE_PC
:
4592 warning (_("Instruction wrote to PC in an unexpected way when "
4593 "single-stepping"));
4597 internal_error (__FILE__
, __LINE__
,
4598 _("Invalid argument to displaced_write_reg"));
4601 dsc
->wrote_to_pc
= 1;
4605 if (debug_displaced
)
4606 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
4607 regno
, (unsigned long) val
);
4608 regcache_cooked_write_unsigned (regs
, regno
, val
);
4612 /* This function is used to concisely determine if an instruction INSN
4613 references PC. Register fields of interest in INSN should have the
4614 corresponding fields of BITMASK set to 0b1111. The function
4615 returns return 1 if any of these fields in INSN reference the PC
4616 (also 0b1111, r15), else it returns 0. */
4619 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
4621 uint32_t lowbit
= 1;
4623 while (bitmask
!= 0)
4627 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
4633 mask
= lowbit
* 0xf;
4635 if ((insn
& mask
) == mask
)
4644 /* The simplest copy function. Many instructions have the same effect no
4645 matter what address they are executed at: in those cases, use this. */
4648 arm_copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
4649 const char *iname
, struct displaced_step_closure
*dsc
)
4651 if (debug_displaced
)
4652 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
4653 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
4656 dsc
->modinsn
[0] = insn
;
4662 thumb_copy_unmodified_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
4663 uint16_t insn2
, const char *iname
,
4664 struct displaced_step_closure
*dsc
)
4666 if (debug_displaced
)
4667 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x %.4x, "
4668 "opcode/class '%s' unmodified\n", insn1
, insn2
,
4671 dsc
->modinsn
[0] = insn1
;
4672 dsc
->modinsn
[1] = insn2
;
4678 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
4681 thumb_copy_unmodified_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
4683 struct displaced_step_closure
*dsc
)
4685 if (debug_displaced
)
4686 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x, "
4687 "opcode/class '%s' unmodified\n", insn
,
4690 dsc
->modinsn
[0] = insn
;
4695 /* Preload instructions with immediate offset. */
4698 cleanup_preload (struct gdbarch
*gdbarch
,
4699 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4701 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4702 if (!dsc
->u
.preload
.immed
)
4703 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
4707 install_preload (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4708 struct displaced_step_closure
*dsc
, unsigned int rn
)
4711 /* Preload instructions:
4713 {pli/pld} [rn, #+/-imm]
4715 {pli/pld} [r0, #+/-imm]. */
4717 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4718 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4719 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4720 dsc
->u
.preload
.immed
= 1;
4722 dsc
->cleanup
= &cleanup_preload
;
4726 arm_copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4727 struct displaced_step_closure
*dsc
)
4729 unsigned int rn
= bits (insn
, 16, 19);
4731 if (!insn_references_pc (insn
, 0x000f0000ul
))
4732 return arm_copy_unmodified (gdbarch
, insn
, "preload", dsc
);
4734 if (debug_displaced
)
4735 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4736 (unsigned long) insn
);
4738 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4740 install_preload (gdbarch
, regs
, dsc
, rn
);
4746 thumb2_copy_preload (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
4747 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4749 unsigned int rn
= bits (insn1
, 0, 3);
4750 unsigned int u_bit
= bit (insn1
, 7);
4751 int imm12
= bits (insn2
, 0, 11);
4754 if (rn
!= ARM_PC_REGNUM
)
4755 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "preload", dsc
);
4757 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
4758 PLD (literal) Encoding T1. */
4759 if (debug_displaced
)
4760 fprintf_unfiltered (gdb_stdlog
,
4761 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
4762 (unsigned int) dsc
->insn_addr
, u_bit
? '+' : '-',
4768 /* Rewrite instruction {pli/pld} PC imm12 into:
4769 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
4773 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
4775 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4776 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4778 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
4780 displaced_write_reg (regs
, dsc
, 0, pc_val
, CANNOT_WRITE_PC
);
4781 displaced_write_reg (regs
, dsc
, 1, imm12
, CANNOT_WRITE_PC
);
4782 dsc
->u
.preload
.immed
= 0;
4784 /* {pli/pld} [r0, r1] */
4785 dsc
->modinsn
[0] = insn1
& 0xfff0;
4786 dsc
->modinsn
[1] = 0xf001;
4789 dsc
->cleanup
= &cleanup_preload
;
4793 /* Preload instructions with register offset. */
4796 install_preload_reg(struct gdbarch
*gdbarch
, struct regcache
*regs
,
4797 struct displaced_step_closure
*dsc
, unsigned int rn
,
4800 ULONGEST rn_val
, rm_val
;
4802 /* Preload register-offset instructions:
4804 {pli/pld} [rn, rm {, shift}]
4806 {pli/pld} [r0, r1 {, shift}]. */
4808 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4809 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4810 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4811 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
4812 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4813 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
4814 dsc
->u
.preload
.immed
= 0;
4816 dsc
->cleanup
= &cleanup_preload
;
4820 arm_copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
4821 struct regcache
*regs
,
4822 struct displaced_step_closure
*dsc
)
4824 unsigned int rn
= bits (insn
, 16, 19);
4825 unsigned int rm
= bits (insn
, 0, 3);
4828 if (!insn_references_pc (insn
, 0x000f000ful
))
4829 return arm_copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
4831 if (debug_displaced
)
4832 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4833 (unsigned long) insn
);
4835 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
4837 install_preload_reg (gdbarch
, regs
, dsc
, rn
, rm
);
4841 /* Copy/cleanup coprocessor load and store instructions. */
4844 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
4845 struct regcache
*regs
,
4846 struct displaced_step_closure
*dsc
)
4848 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 0);
4850 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4852 if (dsc
->u
.ldst
.writeback
)
4853 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
4857 install_copro_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4858 struct displaced_step_closure
*dsc
,
4859 int writeback
, unsigned int rn
)
4863 /* Coprocessor load/store instructions:
4865 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
4867 {stc/stc2} [r0, #+/-imm].
4869 ldc/ldc2 are handled identically. */
4871 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4872 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4873 /* PC should be 4-byte aligned. */
4874 rn_val
= rn_val
& 0xfffffffc;
4875 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4877 dsc
->u
.ldst
.writeback
= writeback
;
4878 dsc
->u
.ldst
.rn
= rn
;
4880 dsc
->cleanup
= &cleanup_copro_load_store
;
4884 arm_copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
4885 struct regcache
*regs
,
4886 struct displaced_step_closure
*dsc
)
4888 unsigned int rn
= bits (insn
, 16, 19);
4890 if (!insn_references_pc (insn
, 0x000f0000ul
))
4891 return arm_copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
4893 if (debug_displaced
)
4894 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4895 "load/store insn %.8lx\n", (unsigned long) insn
);
4897 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4899 install_copro_load_store (gdbarch
, regs
, dsc
, bit (insn
, 25), rn
);
4905 thumb2_copy_copro_load_store (struct gdbarch
*gdbarch
, uint16_t insn1
,
4906 uint16_t insn2
, struct regcache
*regs
,
4907 struct displaced_step_closure
*dsc
)
4909 unsigned int rn
= bits (insn1
, 0, 3);
4911 if (rn
!= ARM_PC_REGNUM
)
4912 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
4913 "copro load/store", dsc
);
4915 if (debug_displaced
)
4916 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4917 "load/store insn %.4x%.4x\n", insn1
, insn2
);
4919 dsc
->modinsn
[0] = insn1
& 0xfff0;
4920 dsc
->modinsn
[1] = insn2
;
4923 /* This function is called for copying instruction LDC/LDC2/VLDR, which
4924 doesn't support writeback, so pass 0. */
4925 install_copro_load_store (gdbarch
, regs
, dsc
, 0, rn
);
4930 /* Clean up branch instructions (actually perform the branch, by setting
4934 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4935 struct displaced_step_closure
*dsc
)
4937 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
4938 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
4939 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
4940 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
4945 if (dsc
->u
.branch
.link
)
4947 /* The value of LR should be the next insn of current one. In order
4948 not to confuse logic hanlding later insn `bx lr', if current insn mode
4949 is Thumb, the bit 0 of LR value should be set to 1. */
4950 ULONGEST next_insn_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
4953 next_insn_addr
|= 0x1;
4955 displaced_write_reg (regs
, dsc
, ARM_LR_REGNUM
, next_insn_addr
,
4959 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, dsc
->u
.branch
.dest
, write_pc
);
4962 /* Copy B/BL/BLX instructions with immediate destinations. */
4965 install_b_bl_blx (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4966 struct displaced_step_closure
*dsc
,
4967 unsigned int cond
, int exchange
, int link
, long offset
)
4969 /* Implement "BL<cond> <label>" as:
4971 Preparation: cond <- instruction condition
4972 Insn: mov r0, r0 (nop)
4973 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
4975 B<cond> similar, but don't set r14 in cleanup. */
4977 dsc
->u
.branch
.cond
= cond
;
4978 dsc
->u
.branch
.link
= link
;
4979 dsc
->u
.branch
.exchange
= exchange
;
4981 dsc
->u
.branch
.dest
= dsc
->insn_addr
;
4982 if (link
&& exchange
)
4983 /* For BLX, offset is computed from the Align (PC, 4). */
4984 dsc
->u
.branch
.dest
= dsc
->u
.branch
.dest
& 0xfffffffc;
4987 dsc
->u
.branch
.dest
+= 4 + offset
;
4989 dsc
->u
.branch
.dest
+= 8 + offset
;
4991 dsc
->cleanup
= &cleanup_branch
;
4994 arm_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
4995 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4997 unsigned int cond
= bits (insn
, 28, 31);
4998 int exchange
= (cond
== 0xf);
4999 int link
= exchange
|| bit (insn
, 24);
5002 if (debug_displaced
)
5003 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
5004 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
5005 (unsigned long) insn
);
5007 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
5008 then arrange the switch into Thumb mode. */
5009 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
5011 offset
= bits (insn
, 0, 23) << 2;
5013 if (bit (offset
, 25))
5014 offset
= offset
| ~0x3ffffff;
5016 dsc
->modinsn
[0] = ARM_NOP
;
5018 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5023 thumb2_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint16_t insn1
,
5024 uint16_t insn2
, struct regcache
*regs
,
5025 struct displaced_step_closure
*dsc
)
5027 int link
= bit (insn2
, 14);
5028 int exchange
= link
&& !bit (insn2
, 12);
5031 int j1
= bit (insn2
, 13);
5032 int j2
= bit (insn2
, 11);
5033 int s
= sbits (insn1
, 10, 10);
5034 int i1
= !(j1
^ bit (insn1
, 10));
5035 int i2
= !(j2
^ bit (insn1
, 10));
5037 if (!link
&& !exchange
) /* B */
5039 offset
= (bits (insn2
, 0, 10) << 1);
5040 if (bit (insn2
, 12)) /* Encoding T4 */
5042 offset
|= (bits (insn1
, 0, 9) << 12)
5048 else /* Encoding T3 */
5050 offset
|= (bits (insn1
, 0, 5) << 12)
5054 cond
= bits (insn1
, 6, 9);
5059 offset
= (bits (insn1
, 0, 9) << 12);
5060 offset
|= ((i2
<< 22) | (i1
<< 23) | (s
<< 24));
5061 offset
|= exchange
?
5062 (bits (insn2
, 1, 10) << 2) : (bits (insn2
, 0, 10) << 1);
5065 if (debug_displaced
)
5066 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s insn "
5067 "%.4x %.4x with offset %.8lx\n",
5068 link
? (exchange
) ? "blx" : "bl" : "b",
5069 insn1
, insn2
, offset
);
5071 dsc
->modinsn
[0] = THUMB_NOP
;
5073 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5077 /* Copy B Thumb instructions. */
5079 thumb_copy_b (struct gdbarch
*gdbarch
, uint16_t insn
,
5080 struct displaced_step_closure
*dsc
)
5082 unsigned int cond
= 0;
5084 unsigned short bit_12_15
= bits (insn
, 12, 15);
5085 CORE_ADDR from
= dsc
->insn_addr
;
5087 if (bit_12_15
== 0xd)
5089 /* offset = SignExtend (imm8:0, 32) */
5090 offset
= sbits ((insn
<< 1), 0, 8);
5091 cond
= bits (insn
, 8, 11);
5093 else if (bit_12_15
== 0xe) /* Encoding T2 */
5095 offset
= sbits ((insn
<< 1), 0, 11);
5099 if (debug_displaced
)
5100 fprintf_unfiltered (gdb_stdlog
,
5101 "displaced: copying b immediate insn %.4x "
5102 "with offset %d\n", insn
, offset
);
5104 dsc
->u
.branch
.cond
= cond
;
5105 dsc
->u
.branch
.link
= 0;
5106 dsc
->u
.branch
.exchange
= 0;
5107 dsc
->u
.branch
.dest
= from
+ 4 + offset
;
5109 dsc
->modinsn
[0] = THUMB_NOP
;
5111 dsc
->cleanup
= &cleanup_branch
;
5116 /* Copy BX/BLX with register-specified destinations. */
5119 install_bx_blx_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5120 struct displaced_step_closure
*dsc
, int link
,
5121 unsigned int cond
, unsigned int rm
)
5123 /* Implement {BX,BLX}<cond> <reg>" as:
5125 Preparation: cond <- instruction condition
5126 Insn: mov r0, r0 (nop)
5127 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
5129 Don't set r14 in cleanup for BX. */
5131 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, dsc
, rm
);
5133 dsc
->u
.branch
.cond
= cond
;
5134 dsc
->u
.branch
.link
= link
;
5136 dsc
->u
.branch
.exchange
= 1;
5138 dsc
->cleanup
= &cleanup_branch
;
5142 arm_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5143 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5145 unsigned int cond
= bits (insn
, 28, 31);
5148 int link
= bit (insn
, 5);
5149 unsigned int rm
= bits (insn
, 0, 3);
5151 if (debug_displaced
)
5152 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx",
5153 (unsigned long) insn
);
5155 dsc
->modinsn
[0] = ARM_NOP
;
5157 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, cond
, rm
);
5162 thumb_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5163 struct regcache
*regs
,
5164 struct displaced_step_closure
*dsc
)
5166 int link
= bit (insn
, 7);
5167 unsigned int rm
= bits (insn
, 3, 6);
5169 if (debug_displaced
)
5170 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x",
5171 (unsigned short) insn
);
5173 dsc
->modinsn
[0] = THUMB_NOP
;
5175 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, INST_AL
, rm
);
5181 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
5184 cleanup_alu_imm (struct gdbarch
*gdbarch
,
5185 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5187 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5188 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5189 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5190 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5194 arm_copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5195 struct displaced_step_closure
*dsc
)
5197 unsigned int rn
= bits (insn
, 16, 19);
5198 unsigned int rd
= bits (insn
, 12, 15);
5199 unsigned int op
= bits (insn
, 21, 24);
5200 int is_mov
= (op
== 0xd);
5201 ULONGEST rd_val
, rn_val
;
5203 if (!insn_references_pc (insn
, 0x000ff000ul
))
5204 return arm_copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
5206 if (debug_displaced
)
5207 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
5208 "%.8lx\n", is_mov
? "move" : "ALU",
5209 (unsigned long) insn
);
5211 /* Instruction is of form:
5213 <op><cond> rd, [rn,] #imm
5217 Preparation: tmp1, tmp2 <- r0, r1;
5219 Insn: <op><cond> r0, r1, #imm
5220 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5223 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5224 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5225 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5226 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5227 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5228 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5232 dsc
->modinsn
[0] = insn
& 0xfff00fff;
5234 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
5236 dsc
->cleanup
= &cleanup_alu_imm
;
5242 thumb2_copy_alu_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5243 uint16_t insn2
, struct regcache
*regs
,
5244 struct displaced_step_closure
*dsc
)
5246 unsigned int op
= bits (insn1
, 5, 8);
5247 unsigned int rn
, rm
, rd
;
5248 ULONGEST rd_val
, rn_val
;
5250 rn
= bits (insn1
, 0, 3); /* Rn */
5251 rm
= bits (insn2
, 0, 3); /* Rm */
5252 rd
= bits (insn2
, 8, 11); /* Rd */
5254 /* This routine is only called for instruction MOV. */
5255 gdb_assert (op
== 0x2 && rn
== 0xf);
5257 if (rm
!= ARM_PC_REGNUM
&& rd
!= ARM_PC_REGNUM
)
5258 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ALU imm", dsc
);
5260 if (debug_displaced
)
5261 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x%.4x\n",
5262 "ALU", insn1
, insn2
);
5264 /* Instruction is of form:
5266 <op><cond> rd, [rn,] #imm
5270 Preparation: tmp1, tmp2 <- r0, r1;
5272 Insn: <op><cond> r0, r1, #imm
5273 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5276 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5277 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5278 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5279 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5280 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5281 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5284 dsc
->modinsn
[0] = insn1
;
5285 dsc
->modinsn
[1] = ((insn2
& 0xf0f0) | 0x1);
5288 dsc
->cleanup
= &cleanup_alu_imm
;
5293 /* Copy/cleanup arithmetic/logic insns with register RHS. */
5296 cleanup_alu_reg (struct gdbarch
*gdbarch
,
5297 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5302 rd_val
= displaced_read_reg (regs
, dsc
, 0);
5304 for (i
= 0; i
< 3; i
++)
5305 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5307 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5311 install_alu_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5312 struct displaced_step_closure
*dsc
,
5313 unsigned int rd
, unsigned int rn
, unsigned int rm
)
5315 ULONGEST rd_val
, rn_val
, rm_val
;
5317 /* Instruction is of form:
5319 <op><cond> rd, [rn,] rm [, <shift>]
5323 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
5324 r0, r1, r2 <- rd, rn, rm
5325 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
5326 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
5329 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5330 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5331 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5332 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5333 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5334 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5335 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5336 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5337 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5340 dsc
->cleanup
= &cleanup_alu_reg
;
5344 arm_copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5345 struct displaced_step_closure
*dsc
)
5347 unsigned int op
= bits (insn
, 21, 24);
5348 int is_mov
= (op
== 0xd);
5350 if (!insn_references_pc (insn
, 0x000ff00ful
))
5351 return arm_copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
5353 if (debug_displaced
)
5354 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
5355 is_mov
? "move" : "ALU", (unsigned long) insn
);
5358 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
5360 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
5362 install_alu_reg (gdbarch
, regs
, dsc
, bits (insn
, 12, 15), bits (insn
, 16, 19),
5368 thumb_copy_alu_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5369 struct regcache
*regs
,
5370 struct displaced_step_closure
*dsc
)
5374 rm
= bits (insn
, 3, 6);
5375 rd
= (bit (insn
, 7) << 3) | bits (insn
, 0, 2);
5377 if (rd
!= ARM_PC_REGNUM
&& rm
!= ARM_PC_REGNUM
)
5378 return thumb_copy_unmodified_16bit (gdbarch
, insn
, "ALU reg", dsc
);
5380 if (debug_displaced
)
5381 fprintf_unfiltered (gdb_stdlog
, "displaced: copying ALU reg insn %.4x\n",
5382 (unsigned short) insn
);
5384 dsc
->modinsn
[0] = ((insn
& 0xff00) | 0x10);
5386 install_alu_reg (gdbarch
, regs
, dsc
, rd
, rd
, rm
);
5391 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
5394 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
5395 struct regcache
*regs
,
5396 struct displaced_step_closure
*dsc
)
5398 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5401 for (i
= 0; i
< 4; i
++)
5402 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5404 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5408 install_alu_shifted_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5409 struct displaced_step_closure
*dsc
,
5410 unsigned int rd
, unsigned int rn
, unsigned int rm
,
5414 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
5416 /* Instruction is of form:
5418 <op><cond> rd, [rn,] rm, <shift> rs
5422 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
5423 r0, r1, r2, r3 <- rd, rn, rm, rs
5424 Insn: <op><cond> r0, r1, r2, <shift> r3
5426 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
5430 for (i
= 0; i
< 4; i
++)
5431 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
5433 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5434 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5435 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5436 rs_val
= displaced_read_reg (regs
, dsc
, rs
);
5437 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5438 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5439 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5440 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
5442 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
5446 arm_copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5447 struct regcache
*regs
,
5448 struct displaced_step_closure
*dsc
)
5450 unsigned int op
= bits (insn
, 21, 24);
5451 int is_mov
= (op
== 0xd);
5452 unsigned int rd
, rn
, rm
, rs
;
5454 if (!insn_references_pc (insn
, 0x000fff0ful
))
5455 return arm_copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
5457 if (debug_displaced
)
5458 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
5459 "%.8lx\n", is_mov
? "move" : "ALU",
5460 (unsigned long) insn
);
5462 rn
= bits (insn
, 16, 19);
5463 rm
= bits (insn
, 0, 3);
5464 rs
= bits (insn
, 8, 11);
5465 rd
= bits (insn
, 12, 15);
5468 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
5470 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
5472 install_alu_shifted_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
, rs
);
5477 /* Clean up load instructions. */
5480 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5481 struct displaced_step_closure
*dsc
)
5483 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
5485 rt_val
= displaced_read_reg (regs
, dsc
, 0);
5486 if (dsc
->u
.ldst
.xfersize
== 8)
5487 rt_val2
= displaced_read_reg (regs
, dsc
, 1);
5488 rn_val
= displaced_read_reg (regs
, dsc
, 2);
5490 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5491 if (dsc
->u
.ldst
.xfersize
> 4)
5492 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5493 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5494 if (!dsc
->u
.ldst
.immed
)
5495 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5497 /* Handle register writeback. */
5498 if (dsc
->u
.ldst
.writeback
)
5499 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5500 /* Put result in right place. */
5501 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
5502 if (dsc
->u
.ldst
.xfersize
== 8)
5503 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
5506 /* Clean up store instructions. */
5509 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5510 struct displaced_step_closure
*dsc
)
5512 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 2);
5514 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5515 if (dsc
->u
.ldst
.xfersize
> 4)
5516 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5517 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5518 if (!dsc
->u
.ldst
.immed
)
5519 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5520 if (!dsc
->u
.ldst
.restore_r4
)
5521 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
5524 if (dsc
->u
.ldst
.writeback
)
5525 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5528 /* Copy "extra" load/store instructions. These are halfword/doubleword
5529 transfers, which have a different encoding to byte/word transfers. */
5532 arm_copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unprivileged
,
5533 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5535 unsigned int op1
= bits (insn
, 20, 24);
5536 unsigned int op2
= bits (insn
, 5, 6);
5537 unsigned int rt
= bits (insn
, 12, 15);
5538 unsigned int rn
= bits (insn
, 16, 19);
5539 unsigned int rm
= bits (insn
, 0, 3);
5540 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
5541 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
5542 int immed
= (op1
& 0x4) != 0;
5544 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
5546 if (!insn_references_pc (insn
, 0x000ff00ful
))
5547 return arm_copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
5549 if (debug_displaced
)
5550 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
5551 "insn %.8lx\n", unprivileged
? "unprivileged " : "",
5552 (unsigned long) insn
);
5554 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
5557 internal_error (__FILE__
, __LINE__
,
5558 _("copy_extra_ld_st: instruction decode error"));
5560 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5561 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5562 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5564 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5566 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5567 if (bytesize
[opcode
] == 8)
5568 rt_val2
= displaced_read_reg (regs
, dsc
, rt
+ 1);
5569 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5571 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5573 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5574 if (bytesize
[opcode
] == 8)
5575 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
5576 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5578 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5581 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
5582 dsc
->u
.ldst
.rn
= rn
;
5583 dsc
->u
.ldst
.immed
= immed
;
5584 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
5585 dsc
->u
.ldst
.restore_r4
= 0;
5588 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
5590 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
5591 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5593 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
5595 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
5596 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5598 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
5603 /* Copy byte/half word/word loads and stores. */
5606 install_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5607 struct displaced_step_closure
*dsc
, int load
,
5608 int immed
, int writeback
, int size
, int usermode
,
5609 int rt
, int rm
, int rn
)
5611 ULONGEST rt_val
, rn_val
, rm_val
= 0;
5613 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5614 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5616 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5618 dsc
->tmp
[4] = displaced_read_reg (regs
, dsc
, 4);
5620 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5621 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5623 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5625 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5626 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5628 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5630 dsc
->u
.ldst
.xfersize
= size
;
5631 dsc
->u
.ldst
.rn
= rn
;
5632 dsc
->u
.ldst
.immed
= immed
;
5633 dsc
->u
.ldst
.writeback
= writeback
;
5635 /* To write PC we can do:
5637 Before this sequence of instructions:
5638 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
5639 r2 is the Rn value got from dispalced_read_reg.
5641 Insn1: push {pc} Write address of STR instruction + offset on stack
5642 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
5643 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
5644 = addr(Insn1) + offset - addr(Insn3) - 8
5646 Insn4: add r4, r4, #8 r4 = offset - 8
5647 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
5649 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
5651 Otherwise we don't know what value to write for PC, since the offset is
5652 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
5653 of this can be found in Section "Saving from r15" in
5654 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
5656 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5661 thumb2_copy_load_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
5662 uint16_t insn2
, struct regcache
*regs
,
5663 struct displaced_step_closure
*dsc
, int size
)
5665 unsigned int u_bit
= bit (insn1
, 7);
5666 unsigned int rt
= bits (insn2
, 12, 15);
5667 int imm12
= bits (insn2
, 0, 11);
5670 if (debug_displaced
)
5671 fprintf_unfiltered (gdb_stdlog
,
5672 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
5673 (unsigned int) dsc
->insn_addr
, rt
, u_bit
? '+' : '-',
5679 /* Rewrite instruction LDR Rt imm12 into:
5681 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
5685 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
5688 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5689 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5690 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5692 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
5694 pc_val
= pc_val
& 0xfffffffc;
5696 displaced_write_reg (regs
, dsc
, 2, pc_val
, CANNOT_WRITE_PC
);
5697 displaced_write_reg (regs
, dsc
, 3, imm12
, CANNOT_WRITE_PC
);
5701 dsc
->u
.ldst
.xfersize
= size
;
5702 dsc
->u
.ldst
.immed
= 0;
5703 dsc
->u
.ldst
.writeback
= 0;
5704 dsc
->u
.ldst
.restore_r4
= 0;
5706 /* LDR R0, R2, R3 */
5707 dsc
->modinsn
[0] = 0xf852;
5708 dsc
->modinsn
[1] = 0x3;
5711 dsc
->cleanup
= &cleanup_load
;
5717 thumb2_copy_load_reg_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5718 uint16_t insn2
, struct regcache
*regs
,
5719 struct displaced_step_closure
*dsc
,
5720 int writeback
, int immed
)
5722 unsigned int rt
= bits (insn2
, 12, 15);
5723 unsigned int rn
= bits (insn1
, 0, 3);
5724 unsigned int rm
= bits (insn2
, 0, 3); /* Only valid if !immed. */
5725 /* In LDR (register), there is also a register Rm, which is not allowed to
5726 be PC, so we don't have to check it. */
5728 if (rt
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
5729 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "load",
5732 if (debug_displaced
)
5733 fprintf_unfiltered (gdb_stdlog
,
5734 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
5735 rt
, rn
, insn1
, insn2
);
5737 install_load_store (gdbarch
, regs
, dsc
, 1, immed
, writeback
, 4,
5740 dsc
->u
.ldst
.restore_r4
= 0;
5743 /* ldr[b]<cond> rt, [rn, #imm], etc.
5745 ldr[b]<cond> r0, [r2, #imm]. */
5747 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5748 dsc
->modinsn
[1] = insn2
& 0x0fff;
5751 /* ldr[b]<cond> rt, [rn, rm], etc.
5753 ldr[b]<cond> r0, [r2, r3]. */
5755 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5756 dsc
->modinsn
[1] = (insn2
& 0x0ff0) | 0x3;
5766 arm_copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
5767 struct regcache
*regs
,
5768 struct displaced_step_closure
*dsc
,
5769 int load
, int size
, int usermode
)
5771 int immed
= !bit (insn
, 25);
5772 int writeback
= (bit (insn
, 24) == 0 || bit (insn
, 21) != 0);
5773 unsigned int rt
= bits (insn
, 12, 15);
5774 unsigned int rn
= bits (insn
, 16, 19);
5775 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
5777 if (!insn_references_pc (insn
, 0x000ff00ful
))
5778 return arm_copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
5780 if (debug_displaced
)
5781 fprintf_unfiltered (gdb_stdlog
,
5782 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
5783 load
? (size
== 1 ? "ldrb" : "ldr")
5784 : (size
== 1 ? "strb" : "str"), usermode
? "t" : "",
5786 (unsigned long) insn
);
5788 install_load_store (gdbarch
, regs
, dsc
, load
, immed
, writeback
, size
,
5789 usermode
, rt
, rm
, rn
);
5791 if (load
|| rt
!= ARM_PC_REGNUM
)
5793 dsc
->u
.ldst
.restore_r4
= 0;
5796 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
5798 {ldr,str}[b]<cond> r0, [r2, #imm]. */
5799 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5801 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
5803 {ldr,str}[b]<cond> r0, [r2, r3]. */
5804 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5808 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
5809 dsc
->u
.ldst
.restore_r4
= 1;
5810 dsc
->modinsn
[0] = 0xe92d8000; /* push {pc} */
5811 dsc
->modinsn
[1] = 0xe8bd0010; /* pop {r4} */
5812 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
5813 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
5814 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
5818 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
5820 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
5825 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5830 /* Cleanup LDM instructions with fully-populated register list. This is an
5831 unfortunate corner case: it's impossible to implement correctly by modifying
5832 the instruction. The issue is as follows: we have an instruction,
5836 which we must rewrite to avoid loading PC. A possible solution would be to
5837 do the load in two halves, something like (with suitable cleanup
5841 ldm[id][ab] r8!, {r0-r7}
5843 ldm[id][ab] r8, {r7-r14}
5846 but at present there's no suitable place for <temp>, since the scratch space
5847 is overwritten before the cleanup routine is called. For now, we simply
5848 emulate the instruction. */
5851 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5852 struct displaced_step_closure
*dsc
)
5854 int inc
= dsc
->u
.block
.increment
;
5855 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
5856 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
5857 uint32_t regmask
= dsc
->u
.block
.regmask
;
5858 int regno
= inc
? 0 : 15;
5859 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
5860 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
5861 && (regmask
& 0x8000) != 0;
5862 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5863 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
5864 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5869 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
5870 sensible we can do here. Complain loudly. */
5871 if (exception_return
)
5872 error (_("Cannot single-step exception return"));
5874 /* We don't handle any stores here for now. */
5875 gdb_assert (dsc
->u
.block
.load
!= 0);
5877 if (debug_displaced
)
5878 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
5879 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
5880 dsc
->u
.block
.increment
? "inc" : "dec",
5881 dsc
->u
.block
.before
? "before" : "after");
5888 while (regno
<= ARM_PC_REGNUM
&& (regmask
& (1 << regno
)) == 0)
5891 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
5894 xfer_addr
+= bump_before
;
5896 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
5897 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
5899 xfer_addr
+= bump_after
;
5901 regmask
&= ~(1 << regno
);
5904 if (dsc
->u
.block
.writeback
)
5905 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
5909 /* Clean up an STM which included the PC in the register list. */
5912 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5913 struct displaced_step_closure
*dsc
)
5915 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5916 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
5917 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
5918 CORE_ADDR stm_insn_addr
;
5921 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5923 /* If condition code fails, there's nothing else to do. */
5924 if (!store_executed
)
5927 if (dsc
->u
.block
.increment
)
5929 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
5931 if (dsc
->u
.block
.before
)
5936 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
5938 if (dsc
->u
.block
.before
)
5942 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
5943 stm_insn_addr
= dsc
->scratch_base
;
5944 offset
= pc_val
- stm_insn_addr
;
5946 if (debug_displaced
)
5947 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
5948 "STM instruction\n", offset
);
5950 /* Rewrite the stored PC to the proper value for the non-displaced original
5952 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
5953 dsc
->insn_addr
+ offset
);
5956 /* Clean up an LDM which includes the PC in the register list. We clumped all
5957 the registers in the transferred list into a contiguous range r0...rX (to
5958 avoid loading PC directly and losing control of the debugged program), so we
5959 must undo that here. */
5962 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
5963 struct regcache
*regs
,
5964 struct displaced_step_closure
*dsc
)
5966 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5967 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
);
5968 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= ARM_PC_REGNUM
;
5969 unsigned int regs_loaded
= bitcount (mask
);
5970 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
5972 /* The method employed here will fail if the register list is fully populated
5973 (we need to avoid loading PC directly). */
5974 gdb_assert (num_to_shuffle
< 16);
5979 clobbered
= (1 << num_to_shuffle
) - 1;
5981 while (num_to_shuffle
> 0)
5983 if ((mask
& (1 << write_reg
)) != 0)
5985 unsigned int read_reg
= num_to_shuffle
- 1;
5987 if (read_reg
!= write_reg
)
5989 ULONGEST rval
= displaced_read_reg (regs
, dsc
, read_reg
);
5990 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
5991 if (debug_displaced
)
5992 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
5993 "loaded register r%d to r%d\n"), read_reg
,
5996 else if (debug_displaced
)
5997 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
5998 "r%d already in the right place\n"),
6001 clobbered
&= ~(1 << write_reg
);
6009 /* Restore any registers we scribbled over. */
6010 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
6012 if ((clobbered
& (1 << write_reg
)) != 0)
6014 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
6016 if (debug_displaced
)
6017 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
6018 "clobbered register r%d\n"), write_reg
);
6019 clobbered
&= ~(1 << write_reg
);
6023 /* Perform register writeback manually. */
6024 if (dsc
->u
.block
.writeback
)
6026 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
6028 if (dsc
->u
.block
.increment
)
6029 new_rn_val
+= regs_loaded
* 4;
6031 new_rn_val
-= regs_loaded
* 4;
6033 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
6038 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
6039 in user-level code (in particular exception return, ldm rn, {...pc}^). */
6042 arm_copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
,
6043 struct regcache
*regs
,
6044 struct displaced_step_closure
*dsc
)
6046 int load
= bit (insn
, 20);
6047 int user
= bit (insn
, 22);
6048 int increment
= bit (insn
, 23);
6049 int before
= bit (insn
, 24);
6050 int writeback
= bit (insn
, 21);
6051 int rn
= bits (insn
, 16, 19);
6053 /* Block transfers which don't mention PC can be run directly
6055 if (rn
!= ARM_PC_REGNUM
&& (insn
& 0x8000) == 0)
6056 return arm_copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
6058 if (rn
== ARM_PC_REGNUM
)
6060 warning (_("displaced: Unpredictable LDM or STM with "
6061 "base register r15"));
6062 return arm_copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
6065 if (debug_displaced
)
6066 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6067 "%.8lx\n", (unsigned long) insn
);
6069 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6070 dsc
->u
.block
.rn
= rn
;
6072 dsc
->u
.block
.load
= load
;
6073 dsc
->u
.block
.user
= user
;
6074 dsc
->u
.block
.increment
= increment
;
6075 dsc
->u
.block
.before
= before
;
6076 dsc
->u
.block
.writeback
= writeback
;
6077 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
6079 dsc
->u
.block
.regmask
= insn
& 0xffff;
6083 if ((insn
& 0xffff) == 0xffff)
6085 /* LDM with a fully-populated register list. This case is
6086 particularly tricky. Implement for now by fully emulating the
6087 instruction (which might not behave perfectly in all cases, but
6088 these instructions should be rare enough for that not to matter
6090 dsc
->modinsn
[0] = ARM_NOP
;
6092 dsc
->cleanup
= &cleanup_block_load_all
;
6096 /* LDM of a list of registers which includes PC. Implement by
6097 rewriting the list of registers to be transferred into a
6098 contiguous chunk r0...rX before doing the transfer, then shuffling
6099 registers into the correct places in the cleanup routine. */
6100 unsigned int regmask
= insn
& 0xffff;
6101 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
6104 for (i
= 0; i
< num_in_list
; i
++)
6105 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6107 /* Writeback makes things complicated. We need to avoid clobbering
6108 the base register with one of the registers in our modified
6109 register list, but just using a different register can't work in
6112 ldm r14!, {r0-r13,pc}
6114 which would need to be rewritten as:
6118 but that can't work, because there's no free register for N.
6120 Solve this by turning off the writeback bit, and emulating
6121 writeback manually in the cleanup routine. */
6126 new_regmask
= (1 << num_in_list
) - 1;
6128 if (debug_displaced
)
6129 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6130 "{..., pc}: original reg list %.4x, modified "
6131 "list %.4x\n"), rn
, writeback
? "!" : "",
6132 (int) insn
& 0xffff, new_regmask
);
6134 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
6136 dsc
->cleanup
= &cleanup_block_load_pc
;
6141 /* STM of a list of registers which includes PC. Run the instruction
6142 as-is, but out of line: this will store the wrong value for the PC,
6143 so we must manually fix up the memory in the cleanup routine.
6144 Doing things this way has the advantage that we can auto-detect
6145 the offset of the PC write (which is architecture-dependent) in
6146 the cleanup routine. */
6147 dsc
->modinsn
[0] = insn
;
6149 dsc
->cleanup
= &cleanup_block_store_pc
;
6156 thumb2_copy_block_xfer (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6157 struct regcache
*regs
,
6158 struct displaced_step_closure
*dsc
)
6160 int rn
= bits (insn1
, 0, 3);
6161 int load
= bit (insn1
, 4);
6162 int writeback
= bit (insn1
, 5);
6164 /* Block transfers which don't mention PC can be run directly
6166 if (rn
!= ARM_PC_REGNUM
&& (insn2
& 0x8000) == 0)
6167 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ldm/stm", dsc
);
6169 if (rn
== ARM_PC_REGNUM
)
6171 warning (_("displaced: Unpredictable LDM or STM with "
6172 "base register r15"));
6173 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6174 "unpredictable ldm/stm", dsc
);
6177 if (debug_displaced
)
6178 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6179 "%.4x%.4x\n", insn1
, insn2
);
6181 /* Clear bit 13, since it should be always zero. */
6182 dsc
->u
.block
.regmask
= (insn2
& 0xdfff);
6183 dsc
->u
.block
.rn
= rn
;
6185 dsc
->u
.block
.load
= load
;
6186 dsc
->u
.block
.user
= 0;
6187 dsc
->u
.block
.increment
= bit (insn1
, 7);
6188 dsc
->u
.block
.before
= bit (insn1
, 8);
6189 dsc
->u
.block
.writeback
= writeback
;
6190 dsc
->u
.block
.cond
= INST_AL
;
6191 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6195 if (dsc
->u
.block
.regmask
== 0xffff)
6197 /* This branch is impossible to happen. */
6202 unsigned int regmask
= dsc
->u
.block
.regmask
;
6203 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
6206 for (i
= 0; i
< num_in_list
; i
++)
6207 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6212 new_regmask
= (1 << num_in_list
) - 1;
6214 if (debug_displaced
)
6215 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6216 "{..., pc}: original reg list %.4x, modified "
6217 "list %.4x\n"), rn
, writeback
? "!" : "",
6218 (int) dsc
->u
.block
.regmask
, new_regmask
);
6220 dsc
->modinsn
[0] = insn1
;
6221 dsc
->modinsn
[1] = (new_regmask
& 0xffff);
6224 dsc
->cleanup
= &cleanup_block_load_pc
;
6229 dsc
->modinsn
[0] = insn1
;
6230 dsc
->modinsn
[1] = insn2
;
6232 dsc
->cleanup
= &cleanup_block_store_pc
;
6237 /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs.
6238 This is used to avoid a dependency on BFD's bfd_endian enum. */
6241 arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr
, int len
,
6244 return read_memory_unsigned_integer (memaddr
, len
,
6245 (enum bfd_endian
) byte_order
);
6248 /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */
6251 arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs
*self
,
6254 return gdbarch_addr_bits_remove (get_regcache_arch (self
->regcache
), val
);
6257 /* Wrapper over syscall_next_pc for use in get_next_pcs. */
6260 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
)
6265 /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */
6268 arm_get_next_pcs_is_thumb (struct arm_get_next_pcs
*self
)
6270 return arm_is_thumb (self
->regcache
);
6273 /* single_step() is called just before we want to resume the inferior,
6274 if we want to single-step it but there is no hardware or kernel
6275 single-step support. We find the target of the coming instructions
6276 and breakpoint them. */
6279 arm_software_single_step (struct frame_info
*frame
)
6281 struct regcache
*regcache
= get_current_regcache ();
6282 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
6283 struct address_space
*aspace
= get_regcache_aspace (regcache
);
6284 struct arm_get_next_pcs next_pcs_ctx
;
6287 VEC (CORE_ADDR
) *next_pcs
= NULL
;
6288 struct cleanup
*old_chain
= make_cleanup (VEC_cleanup (CORE_ADDR
), &next_pcs
);
6290 arm_get_next_pcs_ctor (&next_pcs_ctx
,
6291 &arm_get_next_pcs_ops
,
6292 gdbarch_byte_order (gdbarch
),
6293 gdbarch_byte_order_for_code (gdbarch
),
6297 next_pcs
= arm_get_next_pcs (&next_pcs_ctx
);
6299 for (i
= 0; VEC_iterate (CORE_ADDR
, next_pcs
, i
, pc
); i
++)
6300 arm_insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
6302 do_cleanups (old_chain
);
6307 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
6308 for Linux, where some SVC instructions must be treated specially. */
6311 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6312 struct displaced_step_closure
*dsc
)
6314 CORE_ADDR resume_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
6316 if (debug_displaced
)
6317 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
6318 "%.8lx\n", (unsigned long) resume_addr
);
6320 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
6324 /* Common copy routine for svc instruciton. */
6327 install_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6328 struct displaced_step_closure
*dsc
)
6330 /* Preparation: none.
6331 Insn: unmodified svc.
6332 Cleanup: pc <- insn_addr + insn_size. */
6334 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
6336 dsc
->wrote_to_pc
= 1;
6338 /* Allow OS-specific code to override SVC handling. */
6339 if (dsc
->u
.svc
.copy_svc_os
)
6340 return dsc
->u
.svc
.copy_svc_os (gdbarch
, regs
, dsc
);
6343 dsc
->cleanup
= &cleanup_svc
;
6349 arm_copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
,
6350 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6353 if (debug_displaced
)
6354 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
6355 (unsigned long) insn
);
6357 dsc
->modinsn
[0] = insn
;
6359 return install_svc (gdbarch
, regs
, dsc
);
6363 thumb_copy_svc (struct gdbarch
*gdbarch
, uint16_t insn
,
6364 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6367 if (debug_displaced
)
6368 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.4x\n",
6371 dsc
->modinsn
[0] = insn
;
6373 return install_svc (gdbarch
, regs
, dsc
);
6376 /* Copy undefined instructions. */
6379 arm_copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
6380 struct displaced_step_closure
*dsc
)
6382 if (debug_displaced
)
6383 fprintf_unfiltered (gdb_stdlog
,
6384 "displaced: copying undefined insn %.8lx\n",
6385 (unsigned long) insn
);
6387 dsc
->modinsn
[0] = insn
;
6393 thumb_32bit_copy_undef (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6394 struct displaced_step_closure
*dsc
)
6397 if (debug_displaced
)
6398 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn "
6399 "%.4x %.4x\n", (unsigned short) insn1
,
6400 (unsigned short) insn2
);
6402 dsc
->modinsn
[0] = insn1
;
6403 dsc
->modinsn
[1] = insn2
;
6409 /* Copy unpredictable instructions. */
6412 arm_copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
6413 struct displaced_step_closure
*dsc
)
6415 if (debug_displaced
)
6416 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
6417 "%.8lx\n", (unsigned long) insn
);
6419 dsc
->modinsn
[0] = insn
;
6424 /* The decode_* functions are instruction decoding helpers. They mostly follow
6425 the presentation in the ARM ARM. */
6428 arm_decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
6429 struct regcache
*regs
,
6430 struct displaced_step_closure
*dsc
)
6432 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
6433 unsigned int rn
= bits (insn
, 16, 19);
6435 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
6436 return arm_copy_unmodified (gdbarch
, insn
, "cps", dsc
);
6437 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
6438 return arm_copy_unmodified (gdbarch
, insn
, "setend", dsc
);
6439 else if ((op1
& 0x60) == 0x20)
6440 return arm_copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
6441 else if ((op1
& 0x71) == 0x40)
6442 return arm_copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store",
6444 else if ((op1
& 0x77) == 0x41)
6445 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6446 else if ((op1
& 0x77) == 0x45)
6447 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
6448 else if ((op1
& 0x77) == 0x51)
6451 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6453 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6455 else if ((op1
& 0x77) == 0x55)
6456 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6457 else if (op1
== 0x57)
6460 case 0x1: return arm_copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
6461 case 0x4: return arm_copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
6462 case 0x5: return arm_copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
6463 case 0x6: return arm_copy_unmodified (gdbarch
, insn
, "isb", dsc
);
6464 default: return arm_copy_unpred (gdbarch
, insn
, dsc
);
6466 else if ((op1
& 0x63) == 0x43)
6467 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6468 else if ((op2
& 0x1) == 0x0)
6469 switch (op1
& ~0x80)
6472 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6474 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
6475 case 0x71: case 0x75:
6477 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
6478 case 0x63: case 0x67: case 0x73: case 0x77:
6479 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6481 return arm_copy_undef (gdbarch
, insn
, dsc
);
6484 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
6488 arm_decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
6489 struct regcache
*regs
,
6490 struct displaced_step_closure
*dsc
)
6492 if (bit (insn
, 27) == 0)
6493 return arm_decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
6494 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
6495 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
6498 return arm_copy_unmodified (gdbarch
, insn
, "srs", dsc
);
6501 return arm_copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
6503 case 0x4: case 0x5: case 0x6: case 0x7:
6504 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6507 switch ((insn
& 0xe00000) >> 21)
6509 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
6511 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6514 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6517 return arm_copy_undef (gdbarch
, insn
, dsc
);
6522 int rn_f
= (bits (insn
, 16, 19) == 0xf);
6523 switch ((insn
& 0xe00000) >> 21)
6526 /* ldc/ldc2 imm (undefined for rn == pc). */
6527 return rn_f
? arm_copy_undef (gdbarch
, insn
, dsc
)
6528 : arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6531 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6533 case 0x4: case 0x5: case 0x6: case 0x7:
6534 /* ldc/ldc2 lit (undefined for rn != pc). */
6535 return rn_f
? arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
6536 : arm_copy_undef (gdbarch
, insn
, dsc
);
6539 return arm_copy_undef (gdbarch
, insn
, dsc
);
6544 return arm_copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
6547 if (bits (insn
, 16, 19) == 0xf)
6549 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6551 return arm_copy_undef (gdbarch
, insn
, dsc
);
6555 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6557 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6561 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6563 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6566 return arm_copy_undef (gdbarch
, insn
, dsc
);
6570 /* Decode miscellaneous instructions in dp/misc encoding space. */
6573 arm_decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
6574 struct regcache
*regs
,
6575 struct displaced_step_closure
*dsc
)
6577 unsigned int op2
= bits (insn
, 4, 6);
6578 unsigned int op
= bits (insn
, 21, 22);
6583 return arm_copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
6586 if (op
== 0x1) /* bx. */
6587 return arm_copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
6589 return arm_copy_unmodified (gdbarch
, insn
, "clz", dsc
);
6591 return arm_copy_undef (gdbarch
, insn
, dsc
);
6595 /* Not really supported. */
6596 return arm_copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
6598 return arm_copy_undef (gdbarch
, insn
, dsc
);
6602 return arm_copy_bx_blx_reg (gdbarch
, insn
,
6603 regs
, dsc
); /* blx register. */
6605 return arm_copy_undef (gdbarch
, insn
, dsc
);
6608 return arm_copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
6612 return arm_copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
6614 /* Not really supported. */
6615 return arm_copy_unmodified (gdbarch
, insn
, "smc", dsc
);
6618 return arm_copy_undef (gdbarch
, insn
, dsc
);
6623 arm_decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
,
6624 struct regcache
*regs
,
6625 struct displaced_step_closure
*dsc
)
6628 switch (bits (insn
, 20, 24))
6631 return arm_copy_unmodified (gdbarch
, insn
, "movw", dsc
);
6634 return arm_copy_unmodified (gdbarch
, insn
, "movt", dsc
);
6636 case 0x12: case 0x16:
6637 return arm_copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
6640 return arm_copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
6644 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
6646 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
6647 return arm_copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
6648 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
6649 return arm_copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
6650 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
6651 return arm_decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
6652 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
6653 return arm_copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
6654 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
6655 return arm_copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
6656 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
6657 return arm_copy_unmodified (gdbarch
, insn
, "synch", dsc
);
6658 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
6659 /* 2nd arg means "unprivileged". */
6660 return arm_copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
6664 /* Should be unreachable. */
6669 arm_decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
6670 struct regcache
*regs
,
6671 struct displaced_step_closure
*dsc
)
6673 int a
= bit (insn
, 25), b
= bit (insn
, 4);
6674 uint32_t op1
= bits (insn
, 20, 24);
6676 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
6677 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
6678 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 0);
6679 else if ((!a
&& (op1
& 0x17) == 0x02)
6680 || (a
&& (op1
& 0x17) == 0x02 && !b
))
6681 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 1);
6682 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
6683 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
6684 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 0);
6685 else if ((!a
&& (op1
& 0x17) == 0x03)
6686 || (a
&& (op1
& 0x17) == 0x03 && !b
))
6687 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 1);
6688 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
6689 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
6690 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
6691 else if ((!a
&& (op1
& 0x17) == 0x06)
6692 || (a
&& (op1
& 0x17) == 0x06 && !b
))
6693 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
6694 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
6695 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
6696 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
6697 else if ((!a
&& (op1
& 0x17) == 0x07)
6698 || (a
&& (op1
& 0x17) == 0x07 && !b
))
6699 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
6701 /* Should be unreachable. */
6706 arm_decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
6707 struct displaced_step_closure
*dsc
)
6709 switch (bits (insn
, 20, 24))
6711 case 0x00: case 0x01: case 0x02: case 0x03:
6712 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
6714 case 0x04: case 0x05: case 0x06: case 0x07:
6715 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
6717 case 0x08: case 0x09: case 0x0a: case 0x0b:
6718 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
6719 return arm_copy_unmodified (gdbarch
, insn
,
6720 "decode/pack/unpack/saturate/reverse", dsc
);
6723 if (bits (insn
, 5, 7) == 0) /* op2. */
6725 if (bits (insn
, 12, 15) == 0xf)
6726 return arm_copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
6728 return arm_copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
6731 return arm_copy_undef (gdbarch
, insn
, dsc
);
6733 case 0x1a: case 0x1b:
6734 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6735 return arm_copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
6737 return arm_copy_undef (gdbarch
, insn
, dsc
);
6739 case 0x1c: case 0x1d:
6740 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
6742 if (bits (insn
, 0, 3) == 0xf)
6743 return arm_copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
6745 return arm_copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
6748 return arm_copy_undef (gdbarch
, insn
, dsc
);
6750 case 0x1e: case 0x1f:
6751 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6752 return arm_copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
6754 return arm_copy_undef (gdbarch
, insn
, dsc
);
6757 /* Should be unreachable. */
6762 arm_decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, uint32_t insn
,
6763 struct regcache
*regs
,
6764 struct displaced_step_closure
*dsc
)
6767 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6769 return arm_copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
6773 arm_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
6774 struct regcache
*regs
,
6775 struct displaced_step_closure
*dsc
)
6777 unsigned int opcode
= bits (insn
, 20, 24);
6781 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
6782 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
6784 case 0x08: case 0x0a: case 0x0c: case 0x0e:
6785 case 0x12: case 0x16:
6786 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
6788 case 0x09: case 0x0b: case 0x0d: case 0x0f:
6789 case 0x13: case 0x17:
6790 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
6792 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6793 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6794 /* Note: no writeback for these instructions. Bit 25 will always be
6795 zero though (via caller), so the following works OK. */
6796 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6799 /* Should be unreachable. */
6803 /* Decode shifted register instructions. */
6806 thumb2_decode_dp_shift_reg (struct gdbarch
*gdbarch
, uint16_t insn1
,
6807 uint16_t insn2
, struct regcache
*regs
,
6808 struct displaced_step_closure
*dsc
)
6810 /* PC is only allowed to be used in instruction MOV. */
6812 unsigned int op
= bits (insn1
, 5, 8);
6813 unsigned int rn
= bits (insn1
, 0, 3);
6815 if (op
== 0x2 && rn
== 0xf) /* MOV */
6816 return thumb2_copy_alu_imm (gdbarch
, insn1
, insn2
, regs
, dsc
);
6818 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6819 "dp (shift reg)", dsc
);
6823 /* Decode extension register load/store. Exactly the same as
6824 arm_decode_ext_reg_ld_st. */
6827 thumb2_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint16_t insn1
,
6828 uint16_t insn2
, struct regcache
*regs
,
6829 struct displaced_step_closure
*dsc
)
6831 unsigned int opcode
= bits (insn1
, 4, 8);
6835 case 0x04: case 0x05:
6836 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6837 "vfp/neon vmov", dsc
);
6839 case 0x08: case 0x0c: /* 01x00 */
6840 case 0x0a: case 0x0e: /* 01x10 */
6841 case 0x12: case 0x16: /* 10x10 */
6842 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6843 "vfp/neon vstm/vpush", dsc
);
6845 case 0x09: case 0x0d: /* 01x01 */
6846 case 0x0b: case 0x0f: /* 01x11 */
6847 case 0x13: case 0x17: /* 10x11 */
6848 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6849 "vfp/neon vldm/vpop", dsc
);
6851 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6852 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6854 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6855 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
, regs
, dsc
);
6858 /* Should be unreachable. */
6863 arm_decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
,
6864 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6866 unsigned int op1
= bits (insn
, 20, 25);
6867 int op
= bit (insn
, 4);
6868 unsigned int coproc
= bits (insn
, 8, 11);
6870 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
6871 return arm_decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
6872 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
6873 && (coproc
& 0xe) != 0xa)
6875 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6876 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
6877 && (coproc
& 0xe) != 0xa)
6878 /* ldc/ldc2 imm/lit. */
6879 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6880 else if ((op1
& 0x3e) == 0x00)
6881 return arm_copy_undef (gdbarch
, insn
, dsc
);
6882 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
6883 return arm_copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
6884 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
6885 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6886 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
6887 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6888 else if ((op1
& 0x30) == 0x20 && !op
)
6890 if ((coproc
& 0xe) == 0xa)
6891 return arm_copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
6893 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6895 else if ((op1
& 0x30) == 0x20 && op
)
6896 return arm_copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
6897 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
6898 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6899 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
6900 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6901 else if ((op1
& 0x30) == 0x30)
6902 return arm_copy_svc (gdbarch
, insn
, regs
, dsc
);
6904 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
6908 thumb2_decode_svc_copro (struct gdbarch
*gdbarch
, uint16_t insn1
,
6909 uint16_t insn2
, struct regcache
*regs
,
6910 struct displaced_step_closure
*dsc
)
6912 unsigned int coproc
= bits (insn2
, 8, 11);
6913 unsigned int bit_5_8
= bits (insn1
, 5, 8);
6914 unsigned int bit_9
= bit (insn1
, 9);
6915 unsigned int bit_4
= bit (insn1
, 4);
6920 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6921 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
6923 else if (bit_5_8
== 0) /* UNDEFINED. */
6924 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
6927 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
6928 if ((coproc
& 0xe) == 0xa)
6929 return thumb2_decode_ext_reg_ld_st (gdbarch
, insn1
, insn2
, regs
,
6931 else /* coproc is not 101x. */
6933 if (bit_4
== 0) /* STC/STC2. */
6934 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6936 else /* LDC/LDC2 {literal, immeidate}. */
6937 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
,
6943 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "coproc", dsc
);
6949 install_pc_relative (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6950 struct displaced_step_closure
*dsc
, int rd
)
6956 Preparation: Rd <- PC
6962 int val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
6963 displaced_write_reg (regs
, dsc
, rd
, val
, CANNOT_WRITE_PC
);
6967 thumb_copy_pc_relative_16bit (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6968 struct displaced_step_closure
*dsc
,
6969 int rd
, unsigned int imm
)
6972 /* Encoding T2: ADDS Rd, #imm */
6973 dsc
->modinsn
[0] = (0x3000 | (rd
<< 8) | imm
);
6975 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
6981 thumb_decode_pc_relative_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
6982 struct regcache
*regs
,
6983 struct displaced_step_closure
*dsc
)
6985 unsigned int rd
= bits (insn
, 8, 10);
6986 unsigned int imm8
= bits (insn
, 0, 7);
6988 if (debug_displaced
)
6989 fprintf_unfiltered (gdb_stdlog
,
6990 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
6993 return thumb_copy_pc_relative_16bit (gdbarch
, regs
, dsc
, rd
, imm8
);
6997 thumb_copy_pc_relative_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
6998 uint16_t insn2
, struct regcache
*regs
,
6999 struct displaced_step_closure
*dsc
)
7001 unsigned int rd
= bits (insn2
, 8, 11);
7002 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
7003 extract raw immediate encoding rather than computing immediate. When
7004 generating ADD or SUB instruction, we can simply perform OR operation to
7005 set immediate into ADD. */
7006 unsigned int imm_3_8
= insn2
& 0x70ff;
7007 unsigned int imm_i
= insn1
& 0x0400; /* Clear all bits except bit 10. */
7009 if (debug_displaced
)
7010 fprintf_unfiltered (gdb_stdlog
,
7011 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
7012 rd
, imm_i
, imm_3_8
, insn1
, insn2
);
7014 if (bit (insn1
, 7)) /* Encoding T2 */
7016 /* Encoding T3: SUB Rd, Rd, #imm */
7017 dsc
->modinsn
[0] = (0xf1a0 | rd
| imm_i
);
7018 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7020 else /* Encoding T3 */
7022 /* Encoding T3: ADD Rd, Rd, #imm */
7023 dsc
->modinsn
[0] = (0xf100 | rd
| imm_i
);
7024 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7028 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
7034 thumb_copy_16bit_ldr_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
7035 struct regcache
*regs
,
7036 struct displaced_step_closure
*dsc
)
7038 unsigned int rt
= bits (insn1
, 8, 10);
7040 int imm8
= (bits (insn1
, 0, 7) << 2);
7046 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
7048 Insn: LDR R0, [R2, R3];
7049 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
7051 if (debug_displaced
)
7052 fprintf_unfiltered (gdb_stdlog
,
7053 "displaced: copying thumb ldr r%d [pc #%d]\n"
7056 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
7057 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
7058 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
7059 pc
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
7060 /* The assembler calculates the required value of the offset from the
7061 Align(PC,4) value of this instruction to the label. */
7062 pc
= pc
& 0xfffffffc;
7064 displaced_write_reg (regs
, dsc
, 2, pc
, CANNOT_WRITE_PC
);
7065 displaced_write_reg (regs
, dsc
, 3, imm8
, CANNOT_WRITE_PC
);
7068 dsc
->u
.ldst
.xfersize
= 4;
7070 dsc
->u
.ldst
.immed
= 0;
7071 dsc
->u
.ldst
.writeback
= 0;
7072 dsc
->u
.ldst
.restore_r4
= 0;
7074 dsc
->modinsn
[0] = 0x58d0; /* ldr r0, [r2, r3]*/
7076 dsc
->cleanup
= &cleanup_load
;
7081 /* Copy Thumb cbnz/cbz insruction. */
7084 thumb_copy_cbnz_cbz (struct gdbarch
*gdbarch
, uint16_t insn1
,
7085 struct regcache
*regs
,
7086 struct displaced_step_closure
*dsc
)
7088 int non_zero
= bit (insn1
, 11);
7089 unsigned int imm5
= (bit (insn1
, 9) << 6) | (bits (insn1
, 3, 7) << 1);
7090 CORE_ADDR from
= dsc
->insn_addr
;
7091 int rn
= bits (insn1
, 0, 2);
7092 int rn_val
= displaced_read_reg (regs
, dsc
, rn
);
7094 dsc
->u
.branch
.cond
= (rn_val
&& non_zero
) || (!rn_val
&& !non_zero
);
7095 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
7096 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
7097 condition is false, let it be, cleanup_branch will do nothing. */
7098 if (dsc
->u
.branch
.cond
)
7100 dsc
->u
.branch
.cond
= INST_AL
;
7101 dsc
->u
.branch
.dest
= from
+ 4 + imm5
;
7104 dsc
->u
.branch
.dest
= from
+ 2;
7106 dsc
->u
.branch
.link
= 0;
7107 dsc
->u
.branch
.exchange
= 0;
7109 if (debug_displaced
)
7110 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s [r%d = 0x%x]"
7111 " insn %.4x to %.8lx\n", non_zero
? "cbnz" : "cbz",
7112 rn
, rn_val
, insn1
, dsc
->u
.branch
.dest
);
7114 dsc
->modinsn
[0] = THUMB_NOP
;
7116 dsc
->cleanup
= &cleanup_branch
;
7120 /* Copy Table Branch Byte/Halfword */
7122 thumb2_copy_table_branch (struct gdbarch
*gdbarch
, uint16_t insn1
,
7123 uint16_t insn2
, struct regcache
*regs
,
7124 struct displaced_step_closure
*dsc
)
7126 ULONGEST rn_val
, rm_val
;
7127 int is_tbh
= bit (insn2
, 4);
7128 CORE_ADDR halfwords
= 0;
7129 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7131 rn_val
= displaced_read_reg (regs
, dsc
, bits (insn1
, 0, 3));
7132 rm_val
= displaced_read_reg (regs
, dsc
, bits (insn2
, 0, 3));
7138 target_read_memory (rn_val
+ 2 * rm_val
, buf
, 2);
7139 halfwords
= extract_unsigned_integer (buf
, 2, byte_order
);
7145 target_read_memory (rn_val
+ rm_val
, buf
, 1);
7146 halfwords
= extract_unsigned_integer (buf
, 1, byte_order
);
7149 if (debug_displaced
)
7150 fprintf_unfiltered (gdb_stdlog
, "displaced: %s base 0x%x offset 0x%x"
7151 " offset 0x%x\n", is_tbh
? "tbh" : "tbb",
7152 (unsigned int) rn_val
, (unsigned int) rm_val
,
7153 (unsigned int) halfwords
);
7155 dsc
->u
.branch
.cond
= INST_AL
;
7156 dsc
->u
.branch
.link
= 0;
7157 dsc
->u
.branch
.exchange
= 0;
7158 dsc
->u
.branch
.dest
= dsc
->insn_addr
+ 4 + 2 * halfwords
;
7160 dsc
->cleanup
= &cleanup_branch
;
7166 cleanup_pop_pc_16bit_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7167 struct displaced_step_closure
*dsc
)
7170 int val
= displaced_read_reg (regs
, dsc
, 7);
7171 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, val
, BX_WRITE_PC
);
7174 val
= displaced_read_reg (regs
, dsc
, 8);
7175 displaced_write_reg (regs
, dsc
, 7, val
, CANNOT_WRITE_PC
);
7178 displaced_write_reg (regs
, dsc
, 8, dsc
->tmp
[0], CANNOT_WRITE_PC
);
7183 thumb_copy_pop_pc_16bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
7184 struct regcache
*regs
,
7185 struct displaced_step_closure
*dsc
)
7187 dsc
->u
.block
.regmask
= insn1
& 0x00ff;
7189 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
7192 (1) register list is full, that is, r0-r7 are used.
7193 Prepare: tmp[0] <- r8
7195 POP {r0, r1, ...., r6, r7}; remove PC from reglist
7196 MOV r8, r7; Move value of r7 to r8;
7197 POP {r7}; Store PC value into r7.
7199 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
7201 (2) register list is not full, supposing there are N registers in
7202 register list (except PC, 0 <= N <= 7).
7203 Prepare: for each i, 0 - N, tmp[i] <- ri.
7205 POP {r0, r1, ...., rN};
7207 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
7208 from tmp[] properly.
7210 if (debug_displaced
)
7211 fprintf_unfiltered (gdb_stdlog
,
7212 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
7213 dsc
->u
.block
.regmask
, insn1
);
7215 if (dsc
->u
.block
.regmask
== 0xff)
7217 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 8);
7219 dsc
->modinsn
[0] = (insn1
& 0xfeff); /* POP {r0,r1,...,r6, r7} */
7220 dsc
->modinsn
[1] = 0x46b8; /* MOV r8, r7 */
7221 dsc
->modinsn
[2] = 0xbc80; /* POP {r7} */
7224 dsc
->cleanup
= &cleanup_pop_pc_16bit_all
;
7228 unsigned int num_in_list
= bitcount (dsc
->u
.block
.regmask
);
7230 unsigned int new_regmask
;
7232 for (i
= 0; i
< num_in_list
+ 1; i
++)
7233 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7235 new_regmask
= (1 << (num_in_list
+ 1)) - 1;
7237 if (debug_displaced
)
7238 fprintf_unfiltered (gdb_stdlog
, _("displaced: POP "
7239 "{..., pc}: original reg list %.4x,"
7240 " modified list %.4x\n"),
7241 (int) dsc
->u
.block
.regmask
, new_regmask
);
7243 dsc
->u
.block
.regmask
|= 0x8000;
7244 dsc
->u
.block
.writeback
= 0;
7245 dsc
->u
.block
.cond
= INST_AL
;
7247 dsc
->modinsn
[0] = (insn1
& ~0x1ff) | (new_regmask
& 0xff);
7249 dsc
->cleanup
= &cleanup_block_load_pc
;
7256 thumb_process_displaced_16bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7257 struct regcache
*regs
,
7258 struct displaced_step_closure
*dsc
)
7260 unsigned short op_bit_12_15
= bits (insn1
, 12, 15);
7261 unsigned short op_bit_10_11
= bits (insn1
, 10, 11);
7264 /* 16-bit thumb instructions. */
7265 switch (op_bit_12_15
)
7267 /* Shift (imme), add, subtract, move and compare. */
7268 case 0: case 1: case 2: case 3:
7269 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7270 "shift/add/sub/mov/cmp",
7274 switch (op_bit_10_11
)
7276 case 0: /* Data-processing */
7277 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7281 case 1: /* Special data instructions and branch and exchange. */
7283 unsigned short op
= bits (insn1
, 7, 9);
7284 if (op
== 6 || op
== 7) /* BX or BLX */
7285 err
= thumb_copy_bx_blx_reg (gdbarch
, insn1
, regs
, dsc
);
7286 else if (bits (insn1
, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
7287 err
= thumb_copy_alu_reg (gdbarch
, insn1
, regs
, dsc
);
7289 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "special data",
7293 default: /* LDR (literal) */
7294 err
= thumb_copy_16bit_ldr_literal (gdbarch
, insn1
, regs
, dsc
);
7297 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
7298 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldr/str", dsc
);
7301 if (op_bit_10_11
< 2) /* Generate PC-relative address */
7302 err
= thumb_decode_pc_relative_16bit (gdbarch
, insn1
, regs
, dsc
);
7303 else /* Generate SP-relative address */
7304 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "sp-relative", dsc
);
7306 case 11: /* Misc 16-bit instructions */
7308 switch (bits (insn1
, 8, 11))
7310 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
7311 err
= thumb_copy_cbnz_cbz (gdbarch
, insn1
, regs
, dsc
);
7313 case 12: case 13: /* POP */
7314 if (bit (insn1
, 8)) /* PC is in register list. */
7315 err
= thumb_copy_pop_pc_16bit (gdbarch
, insn1
, regs
, dsc
);
7317 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "pop", dsc
);
7319 case 15: /* If-Then, and hints */
7320 if (bits (insn1
, 0, 3))
7321 /* If-Then makes up to four following instructions conditional.
7322 IT instruction itself is not conditional, so handle it as a
7323 common unmodified instruction. */
7324 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "If-Then",
7327 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "hints", dsc
);
7330 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "misc", dsc
);
7335 if (op_bit_10_11
< 2) /* Store multiple registers */
7336 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "stm", dsc
);
7337 else /* Load multiple registers */
7338 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldm", dsc
);
7340 case 13: /* Conditional branch and supervisor call */
7341 if (bits (insn1
, 9, 11) != 7) /* conditional branch */
7342 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7344 err
= thumb_copy_svc (gdbarch
, insn1
, regs
, dsc
);
7346 case 14: /* Unconditional branch */
7347 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7354 internal_error (__FILE__
, __LINE__
,
7355 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
7359 decode_thumb_32bit_ld_mem_hints (struct gdbarch
*gdbarch
,
7360 uint16_t insn1
, uint16_t insn2
,
7361 struct regcache
*regs
,
7362 struct displaced_step_closure
*dsc
)
7364 int rt
= bits (insn2
, 12, 15);
7365 int rn
= bits (insn1
, 0, 3);
7366 int op1
= bits (insn1
, 7, 8);
7368 switch (bits (insn1
, 5, 6))
7370 case 0: /* Load byte and memory hints */
7371 if (rt
== 0xf) /* PLD/PLI */
7374 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
7375 return thumb2_copy_preload (gdbarch
, insn1
, insn2
, regs
, dsc
);
7377 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7382 if (rn
== 0xf) /* LDRB/LDRSB (literal) */
7383 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7386 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7387 "ldrb{reg, immediate}/ldrbt",
7392 case 1: /* Load halfword and memory hints. */
7393 if (rt
== 0xf) /* PLD{W} and Unalloc memory hint. */
7394 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7395 "pld/unalloc memhint", dsc
);
7399 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7402 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7406 case 2: /* Load word */
7408 int insn2_bit_8_11
= bits (insn2
, 8, 11);
7411 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
, 4);
7412 else if (op1
== 0x1) /* Encoding T3 */
7413 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
, dsc
,
7415 else /* op1 == 0x0 */
7417 if (insn2_bit_8_11
== 0xc || (insn2_bit_8_11
& 0x9) == 0x9)
7418 /* LDR (immediate) */
7419 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7420 dsc
, bit (insn2
, 8), 1);
7421 else if (insn2_bit_8_11
== 0xe) /* LDRT */
7422 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7425 /* LDR (register) */
7426 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7432 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
7439 thumb_process_displaced_32bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7440 uint16_t insn2
, struct regcache
*regs
,
7441 struct displaced_step_closure
*dsc
)
7444 unsigned short op
= bit (insn2
, 15);
7445 unsigned int op1
= bits (insn1
, 11, 12);
7451 switch (bits (insn1
, 9, 10))
7456 /* Load/store {dual, execlusive}, table branch. */
7457 if (bits (insn1
, 7, 8) == 1 && bits (insn1
, 4, 5) == 1
7458 && bits (insn2
, 5, 7) == 0)
7459 err
= thumb2_copy_table_branch (gdbarch
, insn1
, insn2
, regs
,
7462 /* PC is not allowed to use in load/store {dual, exclusive}
7464 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7465 "load/store dual/ex", dsc
);
7467 else /* load/store multiple */
7469 switch (bits (insn1
, 7, 8))
7471 case 0: case 3: /* SRS, RFE */
7472 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7475 case 1: case 2: /* LDM/STM/PUSH/POP */
7476 err
= thumb2_copy_block_xfer (gdbarch
, insn1
, insn2
, regs
, dsc
);
7483 /* Data-processing (shift register). */
7484 err
= thumb2_decode_dp_shift_reg (gdbarch
, insn1
, insn2
, regs
,
7487 default: /* Coprocessor instructions. */
7488 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7493 case 2: /* op1 = 2 */
7494 if (op
) /* Branch and misc control. */
7496 if (bit (insn2
, 14) /* BLX/BL */
7497 || bit (insn2
, 12) /* Unconditional branch */
7498 || (bits (insn1
, 7, 9) != 0x7)) /* Conditional branch */
7499 err
= thumb2_copy_b_bl_blx (gdbarch
, insn1
, insn2
, regs
, dsc
);
7501 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7506 if (bit (insn1
, 9)) /* Data processing (plain binary imm). */
7508 int op
= bits (insn1
, 4, 8);
7509 int rn
= bits (insn1
, 0, 3);
7510 if ((op
== 0 || op
== 0xa) && rn
== 0xf)
7511 err
= thumb_copy_pc_relative_32bit (gdbarch
, insn1
, insn2
,
7514 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7517 else /* Data processing (modified immeidate) */
7518 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7522 case 3: /* op1 = 3 */
7523 switch (bits (insn1
, 9, 10))
7527 err
= decode_thumb_32bit_ld_mem_hints (gdbarch
, insn1
, insn2
,
7529 else /* NEON Load/Store and Store single data item */
7530 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7531 "neon elt/struct load/store",
7534 case 1: /* op1 = 3, bits (9, 10) == 1 */
7535 switch (bits (insn1
, 7, 8))
7537 case 0: case 1: /* Data processing (register) */
7538 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7541 case 2: /* Multiply and absolute difference */
7542 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7543 "mul/mua/diff", dsc
);
7545 case 3: /* Long multiply and divide */
7546 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7551 default: /* Coprocessor instructions */
7552 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7561 internal_error (__FILE__
, __LINE__
,
7562 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
7567 thumb_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7568 struct regcache
*regs
,
7569 struct displaced_step_closure
*dsc
)
7571 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7573 = read_memory_unsigned_integer (from
, 2, byte_order_for_code
);
7575 if (debug_displaced
)
7576 fprintf_unfiltered (gdb_stdlog
, "displaced: process thumb insn %.4x "
7577 "at %.8lx\n", insn1
, (unsigned long) from
);
7580 dsc
->insn_size
= thumb_insn_size (insn1
);
7581 if (thumb_insn_size (insn1
) == 4)
7584 = read_memory_unsigned_integer (from
+ 2, 2, byte_order_for_code
);
7585 thumb_process_displaced_32bit_insn (gdbarch
, insn1
, insn2
, regs
, dsc
);
7588 thumb_process_displaced_16bit_insn (gdbarch
, insn1
, regs
, dsc
);
7592 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7593 CORE_ADDR to
, struct regcache
*regs
,
7594 struct displaced_step_closure
*dsc
)
7597 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7600 /* Most displaced instructions use a 1-instruction scratch space, so set this
7601 here and override below if/when necessary. */
7603 dsc
->insn_addr
= from
;
7604 dsc
->scratch_base
= to
;
7605 dsc
->cleanup
= NULL
;
7606 dsc
->wrote_to_pc
= 0;
7608 if (!displaced_in_arm_mode (regs
))
7609 return thumb_process_displaced_insn (gdbarch
, from
, regs
, dsc
);
7613 insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
7614 if (debug_displaced
)
7615 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
7616 "at %.8lx\n", (unsigned long) insn
,
7617 (unsigned long) from
);
7619 if ((insn
& 0xf0000000) == 0xf0000000)
7620 err
= arm_decode_unconditional (gdbarch
, insn
, regs
, dsc
);
7621 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
7623 case 0x0: case 0x1: case 0x2: case 0x3:
7624 err
= arm_decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
7627 case 0x4: case 0x5: case 0x6:
7628 err
= arm_decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
7632 err
= arm_decode_media (gdbarch
, insn
, dsc
);
7635 case 0x8: case 0x9: case 0xa: case 0xb:
7636 err
= arm_decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
7639 case 0xc: case 0xd: case 0xe: case 0xf:
7640 err
= arm_decode_svc_copro (gdbarch
, insn
, regs
, dsc
);
7645 internal_error (__FILE__
, __LINE__
,
7646 _("arm_process_displaced_insn: Instruction decode error"));
7649 /* Actually set up the scratch space for a displaced instruction. */
7652 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7653 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
7655 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7656 unsigned int i
, len
, offset
;
7657 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7658 int size
= dsc
->is_thumb
? 2 : 4;
7659 const gdb_byte
*bkp_insn
;
7662 /* Poke modified instruction(s). */
7663 for (i
= 0; i
< dsc
->numinsns
; i
++)
7665 if (debug_displaced
)
7667 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn ");
7669 fprintf_unfiltered (gdb_stdlog
, "%.8lx",
7672 fprintf_unfiltered (gdb_stdlog
, "%.4x",
7673 (unsigned short)dsc
->modinsn
[i
]);
7675 fprintf_unfiltered (gdb_stdlog
, " at %.8lx\n",
7676 (unsigned long) to
+ offset
);
7679 write_memory_unsigned_integer (to
+ offset
, size
,
7680 byte_order_for_code
,
7685 /* Choose the correct breakpoint instruction. */
7688 bkp_insn
= tdep
->thumb_breakpoint
;
7689 len
= tdep
->thumb_breakpoint_size
;
7693 bkp_insn
= tdep
->arm_breakpoint
;
7694 len
= tdep
->arm_breakpoint_size
;
7697 /* Put breakpoint afterwards. */
7698 write_memory (to
+ offset
, bkp_insn
, len
);
7700 if (debug_displaced
)
7701 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
7702 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
7705 /* Entry point for cleaning things up after a displaced instruction has been
7709 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
7710 struct displaced_step_closure
*dsc
,
7711 CORE_ADDR from
, CORE_ADDR to
,
7712 struct regcache
*regs
)
7715 dsc
->cleanup (gdbarch
, regs
, dsc
);
7717 if (!dsc
->wrote_to_pc
)
7718 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
7719 dsc
->insn_addr
+ dsc
->insn_size
);
7723 #include "bfd-in2.h"
7724 #include "libcoff.h"
7727 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
7729 struct gdbarch
*gdbarch
= (struct gdbarch
*) info
->application_data
;
7731 if (arm_pc_is_thumb (gdbarch
, memaddr
))
7733 static asymbol
*asym
;
7734 static combined_entry_type ce
;
7735 static struct coff_symbol_struct csym
;
7736 static struct bfd fake_bfd
;
7737 static bfd_target fake_target
;
7739 if (csym
.native
== NULL
)
7741 /* Create a fake symbol vector containing a Thumb symbol.
7742 This is solely so that the code in print_insn_little_arm()
7743 and print_insn_big_arm() in opcodes/arm-dis.c will detect
7744 the presence of a Thumb symbol and switch to decoding
7745 Thumb instructions. */
7747 fake_target
.flavour
= bfd_target_coff_flavour
;
7748 fake_bfd
.xvec
= &fake_target
;
7749 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
7751 csym
.symbol
.the_bfd
= &fake_bfd
;
7752 csym
.symbol
.name
= "fake";
7753 asym
= (asymbol
*) & csym
;
7756 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
7757 info
->symbols
= &asym
;
7760 info
->symbols
= NULL
;
7762 if (info
->endian
== BFD_ENDIAN_BIG
)
7763 return print_insn_big_arm (memaddr
, info
);
7765 return print_insn_little_arm (memaddr
, info
);
7768 /* The following define instruction sequences that will cause ARM
7769 cpu's to take an undefined instruction trap. These are used to
7770 signal a breakpoint to GDB.
7772 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
7773 modes. A different instruction is required for each mode. The ARM
7774 cpu's can also be big or little endian. Thus four different
7775 instructions are needed to support all cases.
7777 Note: ARMv4 defines several new instructions that will take the
7778 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
7779 not in fact add the new instructions. The new undefined
7780 instructions in ARMv4 are all instructions that had no defined
7781 behaviour in earlier chips. There is no guarantee that they will
7782 raise an exception, but may be treated as NOP's. In practice, it
7783 may only safe to rely on instructions matching:
7785 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
7786 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
7787 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
7789 Even this may only true if the condition predicate is true. The
7790 following use a condition predicate of ALWAYS so it is always TRUE.
7792 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
7793 and NetBSD all use a software interrupt rather than an undefined
7794 instruction to force a trap. This can be handled by by the
7795 abi-specific code during establishment of the gdbarch vector. */
7797 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
7798 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
7799 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
7800 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
7802 static const gdb_byte arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
7803 static const gdb_byte arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
7804 static const gdb_byte arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
7805 static const gdb_byte arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
7807 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
7808 the program counter value to determine whether a 16-bit or 32-bit
7809 breakpoint should be used. It returns a pointer to a string of
7810 bytes that encode a breakpoint instruction, stores the length of
7811 the string to *lenptr, and adjusts the program counter (if
7812 necessary) to point to the actual memory location where the
7813 breakpoint should be inserted. */
7815 static const unsigned char *
7816 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
7818 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7819 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7821 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
7823 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
7825 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
7826 check whether we are replacing a 32-bit instruction. */
7827 if (tdep
->thumb2_breakpoint
!= NULL
)
7830 if (target_read_memory (*pcptr
, buf
, 2) == 0)
7832 unsigned short inst1
;
7833 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
7834 if (thumb_insn_size (inst1
) == 4)
7836 *lenptr
= tdep
->thumb2_breakpoint_size
;
7837 return tdep
->thumb2_breakpoint
;
7842 *lenptr
= tdep
->thumb_breakpoint_size
;
7843 return tdep
->thumb_breakpoint
;
7847 *lenptr
= tdep
->arm_breakpoint_size
;
7848 return tdep
->arm_breakpoint
;
7853 arm_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
7856 arm_breakpoint_from_pc (gdbarch
, pcptr
, kindptr
);
7858 if (arm_pc_is_thumb (gdbarch
, *pcptr
) && *kindptr
== 4)
7859 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
7860 that this is not confused with a 32-bit ARM breakpoint. */
7864 /* Extract from an array REGBUF containing the (raw) register state a
7865 function return value of type TYPE, and copy that, in virtual
7866 format, into VALBUF. */
7869 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
7872 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
7873 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7875 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
7877 switch (gdbarch_tdep (gdbarch
)->fp_model
)
7881 /* The value is in register F0 in internal format. We need to
7882 extract the raw value and then convert it to the desired
7884 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
7886 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
7887 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
7888 valbuf
, gdbarch_byte_order (gdbarch
));
7892 case ARM_FLOAT_SOFT_FPA
:
7893 case ARM_FLOAT_SOFT_VFP
:
7894 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7895 not using the VFP ABI code. */
7897 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
7898 if (TYPE_LENGTH (type
) > 4)
7899 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
7900 valbuf
+ INT_REGISTER_SIZE
);
7904 internal_error (__FILE__
, __LINE__
,
7905 _("arm_extract_return_value: "
7906 "Floating point model not supported"));
7910 else if (TYPE_CODE (type
) == TYPE_CODE_INT
7911 || TYPE_CODE (type
) == TYPE_CODE_CHAR
7912 || TYPE_CODE (type
) == TYPE_CODE_BOOL
7913 || TYPE_CODE (type
) == TYPE_CODE_PTR
7914 || TYPE_CODE (type
) == TYPE_CODE_REF
7915 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
7917 /* If the type is a plain integer, then the access is
7918 straight-forward. Otherwise we have to play around a bit
7920 int len
= TYPE_LENGTH (type
);
7921 int regno
= ARM_A1_REGNUM
;
7926 /* By using store_unsigned_integer we avoid having to do
7927 anything special for small big-endian values. */
7928 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
7929 store_unsigned_integer (valbuf
,
7930 (len
> INT_REGISTER_SIZE
7931 ? INT_REGISTER_SIZE
: len
),
7933 len
-= INT_REGISTER_SIZE
;
7934 valbuf
+= INT_REGISTER_SIZE
;
7939 /* For a structure or union the behaviour is as if the value had
7940 been stored to word-aligned memory and then loaded into
7941 registers with 32-bit load instruction(s). */
7942 int len
= TYPE_LENGTH (type
);
7943 int regno
= ARM_A1_REGNUM
;
7944 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
7948 regcache_cooked_read (regs
, regno
++, tmpbuf
);
7949 memcpy (valbuf
, tmpbuf
,
7950 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
7951 len
-= INT_REGISTER_SIZE
;
7952 valbuf
+= INT_REGISTER_SIZE
;
7958 /* Will a function return an aggregate type in memory or in a
7959 register? Return 0 if an aggregate type can be returned in a
7960 register, 1 if it must be returned in memory. */
7963 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
7965 enum type_code code
;
7967 type
= check_typedef (type
);
7969 /* Simple, non-aggregate types (ie not including vectors and
7970 complex) are always returned in a register (or registers). */
7971 code
= TYPE_CODE (type
);
7972 if (TYPE_CODE_STRUCT
!= code
&& TYPE_CODE_UNION
!= code
7973 && TYPE_CODE_ARRAY
!= code
&& TYPE_CODE_COMPLEX
!= code
)
7976 if (TYPE_CODE_ARRAY
== code
&& TYPE_VECTOR (type
))
7978 /* Vector values should be returned using ARM registers if they
7979 are not over 16 bytes. */
7980 return (TYPE_LENGTH (type
) > 16);
7983 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
7985 /* The AAPCS says all aggregates not larger than a word are returned
7987 if (TYPE_LENGTH (type
) <= INT_REGISTER_SIZE
)
7996 /* All aggregate types that won't fit in a register must be returned
7998 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
8001 /* In the ARM ABI, "integer" like aggregate types are returned in
8002 registers. For an aggregate type to be integer like, its size
8003 must be less than or equal to INT_REGISTER_SIZE and the
8004 offset of each addressable subfield must be zero. Note that bit
8005 fields are not addressable, and all addressable subfields of
8006 unions always start at offset zero.
8008 This function is based on the behaviour of GCC 2.95.1.
8009 See: gcc/arm.c: arm_return_in_memory() for details.
8011 Note: All versions of GCC before GCC 2.95.2 do not set up the
8012 parameters correctly for a function returning the following
8013 structure: struct { float f;}; This should be returned in memory,
8014 not a register. Richard Earnshaw sent me a patch, but I do not
8015 know of any way to detect if a function like the above has been
8016 compiled with the correct calling convention. */
8018 /* Assume all other aggregate types can be returned in a register.
8019 Run a check for structures, unions and arrays. */
8022 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
8025 /* Need to check if this struct/union is "integer" like. For
8026 this to be true, its size must be less than or equal to
8027 INT_REGISTER_SIZE and the offset of each addressable
8028 subfield must be zero. Note that bit fields are not
8029 addressable, and unions always start at offset zero. If any
8030 of the subfields is a floating point type, the struct/union
8031 cannot be an integer type. */
8033 /* For each field in the object, check:
8034 1) Is it FP? --> yes, nRc = 1;
8035 2) Is it addressable (bitpos != 0) and
8036 not packed (bitsize == 0)?
8040 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
8042 enum type_code field_type_code
;
8045 = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
,
8048 /* Is it a floating point type field? */
8049 if (field_type_code
== TYPE_CODE_FLT
)
8055 /* If bitpos != 0, then we have to care about it. */
8056 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
8058 /* Bitfields are not addressable. If the field bitsize is
8059 zero, then the field is not packed. Hence it cannot be
8060 a bitfield or any other packed type. */
8061 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
8074 /* Write into appropriate registers a function return value of type
8075 TYPE, given in virtual format. */
8078 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
8079 const gdb_byte
*valbuf
)
8081 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
8082 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8084 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
8086 gdb_byte buf
[MAX_REGISTER_SIZE
];
8088 switch (gdbarch_tdep (gdbarch
)->fp_model
)
8092 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
8093 gdbarch_byte_order (gdbarch
));
8094 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
8097 case ARM_FLOAT_SOFT_FPA
:
8098 case ARM_FLOAT_SOFT_VFP
:
8099 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8100 not using the VFP ABI code. */
8102 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
8103 if (TYPE_LENGTH (type
) > 4)
8104 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
8105 valbuf
+ INT_REGISTER_SIZE
);
8109 internal_error (__FILE__
, __LINE__
,
8110 _("arm_store_return_value: Floating "
8111 "point model not supported"));
8115 else if (TYPE_CODE (type
) == TYPE_CODE_INT
8116 || TYPE_CODE (type
) == TYPE_CODE_CHAR
8117 || TYPE_CODE (type
) == TYPE_CODE_BOOL
8118 || TYPE_CODE (type
) == TYPE_CODE_PTR
8119 || TYPE_CODE (type
) == TYPE_CODE_REF
8120 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
8122 if (TYPE_LENGTH (type
) <= 4)
8124 /* Values of one word or less are zero/sign-extended and
8126 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8127 LONGEST val
= unpack_long (type
, valbuf
);
8129 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
8130 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
8134 /* Integral values greater than one word are stored in consecutive
8135 registers starting with r0. This will always be a multiple of
8136 the regiser size. */
8137 int len
= TYPE_LENGTH (type
);
8138 int regno
= ARM_A1_REGNUM
;
8142 regcache_cooked_write (regs
, regno
++, valbuf
);
8143 len
-= INT_REGISTER_SIZE
;
8144 valbuf
+= INT_REGISTER_SIZE
;
8150 /* For a structure or union the behaviour is as if the value had
8151 been stored to word-aligned memory and then loaded into
8152 registers with 32-bit load instruction(s). */
8153 int len
= TYPE_LENGTH (type
);
8154 int regno
= ARM_A1_REGNUM
;
8155 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8159 memcpy (tmpbuf
, valbuf
,
8160 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
8161 regcache_cooked_write (regs
, regno
++, tmpbuf
);
8162 len
-= INT_REGISTER_SIZE
;
8163 valbuf
+= INT_REGISTER_SIZE
;
8169 /* Handle function return values. */
8171 static enum return_value_convention
8172 arm_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
8173 struct type
*valtype
, struct regcache
*regcache
,
8174 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
8176 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8177 struct type
*func_type
= function
? value_type (function
) : NULL
;
8178 enum arm_vfp_cprc_base_type vfp_base_type
;
8181 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
8182 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
8184 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
8185 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
8187 for (i
= 0; i
< vfp_base_count
; i
++)
8189 if (reg_char
== 'q')
8192 arm_neon_quad_write (gdbarch
, regcache
, i
,
8193 writebuf
+ i
* unit_length
);
8196 arm_neon_quad_read (gdbarch
, regcache
, i
,
8197 readbuf
+ i
* unit_length
);
8204 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d", reg_char
, i
);
8205 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8208 regcache_cooked_write (regcache
, regnum
,
8209 writebuf
+ i
* unit_length
);
8211 regcache_cooked_read (regcache
, regnum
,
8212 readbuf
+ i
* unit_length
);
8215 return RETURN_VALUE_REGISTER_CONVENTION
;
8218 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
8219 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
8220 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
8222 if (tdep
->struct_return
== pcc_struct_return
8223 || arm_return_in_memory (gdbarch
, valtype
))
8224 return RETURN_VALUE_STRUCT_CONVENTION
;
8226 else if (TYPE_CODE (valtype
) == TYPE_CODE_COMPLEX
)
8228 if (arm_return_in_memory (gdbarch
, valtype
))
8229 return RETURN_VALUE_STRUCT_CONVENTION
;
8233 arm_store_return_value (valtype
, regcache
, writebuf
);
8236 arm_extract_return_value (valtype
, regcache
, readbuf
);
8238 return RETURN_VALUE_REGISTER_CONVENTION
;
8243 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
8245 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
8246 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8247 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8249 gdb_byte buf
[INT_REGISTER_SIZE
];
8251 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
8253 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
8257 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
8261 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
8262 return the target PC. Otherwise return 0. */
8265 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
8269 CORE_ADDR start_addr
;
8271 /* Find the starting address and name of the function containing the PC. */
8272 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
8274 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
8276 start_addr
= arm_skip_bx_reg (frame
, pc
);
8277 if (start_addr
!= 0)
8283 /* If PC is in a Thumb call or return stub, return the address of the
8284 target PC, which is in a register. The thunk functions are called
8285 _call_via_xx, where x is the register name. The possible names
8286 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
8287 functions, named __ARM_call_via_r[0-7]. */
8288 if (startswith (name
, "_call_via_")
8289 || startswith (name
, "__ARM_call_via_"))
8291 /* Use the name suffix to determine which register contains the
8293 static char *table
[15] =
8294 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8295 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
8298 int offset
= strlen (name
) - 2;
8300 for (regno
= 0; regno
<= 14; regno
++)
8301 if (strcmp (&name
[offset
], table
[regno
]) == 0)
8302 return get_frame_register_unsigned (frame
, regno
);
8305 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
8306 non-interworking calls to foo. We could decode the stubs
8307 to find the target but it's easier to use the symbol table. */
8308 namelen
= strlen (name
);
8309 if (name
[0] == '_' && name
[1] == '_'
8310 && ((namelen
> 2 + strlen ("_from_thumb")
8311 && startswith (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb"))
8312 || (namelen
> 2 + strlen ("_from_arm")
8313 && startswith (name
+ namelen
- strlen ("_from_arm"), "_from_arm"))))
8316 int target_len
= namelen
- 2;
8317 struct bound_minimal_symbol minsym
;
8318 struct objfile
*objfile
;
8319 struct obj_section
*sec
;
8321 if (name
[namelen
- 1] == 'b')
8322 target_len
-= strlen ("_from_thumb");
8324 target_len
-= strlen ("_from_arm");
8326 target_name
= (char *) alloca (target_len
+ 1);
8327 memcpy (target_name
, name
+ 2, target_len
);
8328 target_name
[target_len
] = '\0';
8330 sec
= find_pc_section (pc
);
8331 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
8332 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
8333 if (minsym
.minsym
!= NULL
)
8334 return BMSYMBOL_VALUE_ADDRESS (minsym
);
8339 return 0; /* not a stub */
8343 set_arm_command (char *args
, int from_tty
)
8345 printf_unfiltered (_("\
8346 \"set arm\" must be followed by an apporpriate subcommand.\n"));
8347 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
8351 show_arm_command (char *args
, int from_tty
)
8353 cmd_show_list (showarmcmdlist
, from_tty
, "");
8357 arm_update_current_architecture (void)
8359 struct gdbarch_info info
;
8361 /* If the current architecture is not ARM, we have nothing to do. */
8362 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_arm
)
8365 /* Update the architecture. */
8366 gdbarch_info_init (&info
);
8368 if (!gdbarch_update_p (info
))
8369 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
8373 set_fp_model_sfunc (char *args
, int from_tty
,
8374 struct cmd_list_element
*c
)
8378 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
8379 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
8381 arm_fp_model
= (enum arm_float_model
) fp_model
;
8385 if (fp_model
== ARM_FLOAT_LAST
)
8386 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
8389 arm_update_current_architecture ();
8393 show_fp_model (struct ui_file
*file
, int from_tty
,
8394 struct cmd_list_element
*c
, const char *value
)
8396 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8398 if (arm_fp_model
== ARM_FLOAT_AUTO
8399 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8400 fprintf_filtered (file
, _("\
8401 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
8402 fp_model_strings
[tdep
->fp_model
]);
8404 fprintf_filtered (file
, _("\
8405 The current ARM floating point model is \"%s\".\n"),
8406 fp_model_strings
[arm_fp_model
]);
8410 arm_set_abi (char *args
, int from_tty
,
8411 struct cmd_list_element
*c
)
8415 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
8416 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
8418 arm_abi_global
= (enum arm_abi_kind
) arm_abi
;
8422 if (arm_abi
== ARM_ABI_LAST
)
8423 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
8426 arm_update_current_architecture ();
8430 arm_show_abi (struct ui_file
*file
, int from_tty
,
8431 struct cmd_list_element
*c
, const char *value
)
8433 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8435 if (arm_abi_global
== ARM_ABI_AUTO
8436 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8437 fprintf_filtered (file
, _("\
8438 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
8439 arm_abi_strings
[tdep
->arm_abi
]);
8441 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
8446 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
8447 struct cmd_list_element
*c
, const char *value
)
8449 fprintf_filtered (file
,
8450 _("The current execution mode assumed "
8451 "(when symbols are unavailable) is \"%s\".\n"),
8452 arm_fallback_mode_string
);
8456 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
8457 struct cmd_list_element
*c
, const char *value
)
8459 fprintf_filtered (file
,
8460 _("The current execution mode assumed "
8461 "(even when symbols are available) is \"%s\".\n"),
8462 arm_force_mode_string
);
8465 /* If the user changes the register disassembly style used for info
8466 register and other commands, we have to also switch the style used
8467 in opcodes for disassembly output. This function is run in the "set
8468 arm disassembly" command, and does that. */
8471 set_disassembly_style_sfunc (char *args
, int from_tty
,
8472 struct cmd_list_element
*c
)
8474 set_disassembly_style ();
8477 /* Return the ARM register name corresponding to register I. */
8479 arm_register_name (struct gdbarch
*gdbarch
, int i
)
8481 const int num_regs
= gdbarch_num_regs (gdbarch
);
8483 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
8484 && i
>= num_regs
&& i
< num_regs
+ 32)
8486 static const char *const vfp_pseudo_names
[] = {
8487 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
8488 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
8489 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
8490 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
8493 return vfp_pseudo_names
[i
- num_regs
];
8496 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
8497 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
8499 static const char *const neon_pseudo_names
[] = {
8500 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
8501 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
8504 return neon_pseudo_names
[i
- num_regs
- 32];
8507 if (i
>= ARRAY_SIZE (arm_register_names
))
8508 /* These registers are only supported on targets which supply
8509 an XML description. */
8512 return arm_register_names
[i
];
8516 set_disassembly_style (void)
8520 /* Find the style that the user wants. */
8521 for (current
= 0; current
< num_disassembly_options
; current
++)
8522 if (disassembly_style
== valid_disassembly_styles
[current
])
8524 gdb_assert (current
< num_disassembly_options
);
8526 /* Synchronize the disassembler. */
8527 set_arm_regname_option (current
);
8530 /* Test whether the coff symbol specific value corresponds to a Thumb
8534 coff_sym_is_thumb (int val
)
8536 return (val
== C_THUMBEXT
8537 || val
== C_THUMBSTAT
8538 || val
== C_THUMBEXTFUNC
8539 || val
== C_THUMBSTATFUNC
8540 || val
== C_THUMBLABEL
);
8543 /* arm_coff_make_msymbol_special()
8544 arm_elf_make_msymbol_special()
8546 These functions test whether the COFF or ELF symbol corresponds to
8547 an address in thumb code, and set a "special" bit in a minimal
8548 symbol to indicate that it does. */
8551 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
8553 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type
*)sym
)->internal_elf_sym
)
8554 == ST_BRANCH_TO_THUMB
)
8555 MSYMBOL_SET_SPECIAL (msym
);
8559 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
8561 if (coff_sym_is_thumb (val
))
8562 MSYMBOL_SET_SPECIAL (msym
);
8566 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
8568 struct arm_per_objfile
*data
= (struct arm_per_objfile
*) arg
;
8571 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
8572 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
8576 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
8579 const char *name
= bfd_asymbol_name (sym
);
8580 struct arm_per_objfile
*data
;
8581 VEC(arm_mapping_symbol_s
) **map_p
;
8582 struct arm_mapping_symbol new_map_sym
;
8584 gdb_assert (name
[0] == '$');
8585 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
8588 data
= (struct arm_per_objfile
*) objfile_data (objfile
,
8589 arm_objfile_data_key
);
8592 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
8593 struct arm_per_objfile
);
8594 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
8595 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
8596 objfile
->obfd
->section_count
,
8597 VEC(arm_mapping_symbol_s
) *);
8599 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
8601 new_map_sym
.value
= sym
->value
;
8602 new_map_sym
.type
= name
[1];
8604 /* Assume that most mapping symbols appear in order of increasing
8605 value. If they were randomly distributed, it would be faster to
8606 always push here and then sort at first use. */
8607 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
8609 struct arm_mapping_symbol
*prev_map_sym
;
8611 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
8612 if (prev_map_sym
->value
>= sym
->value
)
8615 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
8616 arm_compare_mapping_symbols
);
8617 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
8622 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
8626 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
8628 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
8629 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
8631 /* If necessary, set the T bit. */
8634 ULONGEST val
, t_bit
;
8635 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
8636 t_bit
= arm_psr_thumb_bit (gdbarch
);
8637 if (arm_pc_is_thumb (gdbarch
, pc
))
8638 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8641 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8646 /* Read the contents of a NEON quad register, by reading from two
8647 double registers. This is used to implement the quad pseudo
8648 registers, and for argument passing in case the quad registers are
8649 missing; vectors are passed in quad registers when using the VFP
8650 ABI, even if a NEON unit is not present. REGNUM is the index of
8651 the quad register, in [0, 15]. */
8653 static enum register_status
8654 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8655 int regnum
, gdb_byte
*buf
)
8658 gdb_byte reg_buf
[8];
8659 int offset
, double_regnum
;
8660 enum register_status status
;
8662 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8663 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8666 /* d0 is always the least significant half of q0. */
8667 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8672 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8673 if (status
!= REG_VALID
)
8675 memcpy (buf
+ offset
, reg_buf
, 8);
8677 offset
= 8 - offset
;
8678 status
= regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
8679 if (status
!= REG_VALID
)
8681 memcpy (buf
+ offset
, reg_buf
, 8);
8686 static enum register_status
8687 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8688 int regnum
, gdb_byte
*buf
)
8690 const int num_regs
= gdbarch_num_regs (gdbarch
);
8692 gdb_byte reg_buf
[8];
8693 int offset
, double_regnum
;
8695 gdb_assert (regnum
>= num_regs
);
8698 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8699 /* Quad-precision register. */
8700 return arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
8703 enum register_status status
;
8705 /* Single-precision register. */
8706 gdb_assert (regnum
< 32);
8708 /* s0 is always the least significant half of d0. */
8709 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8710 offset
= (regnum
& 1) ? 0 : 4;
8712 offset
= (regnum
& 1) ? 4 : 0;
8714 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8715 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8718 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8719 if (status
== REG_VALID
)
8720 memcpy (buf
, reg_buf
+ offset
, 4);
8725 /* Store the contents of BUF to a NEON quad register, by writing to
8726 two double registers. This is used to implement the quad pseudo
8727 registers, and for argument passing in case the quad registers are
8728 missing; vectors are passed in quad registers when using the VFP
8729 ABI, even if a NEON unit is not present. REGNUM is the index
8730 of the quad register, in [0, 15]. */
8733 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8734 int regnum
, const gdb_byte
*buf
)
8737 int offset
, double_regnum
;
8739 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8740 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8743 /* d0 is always the least significant half of q0. */
8744 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8749 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
8750 offset
= 8 - offset
;
8751 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
8755 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8756 int regnum
, const gdb_byte
*buf
)
8758 const int num_regs
= gdbarch_num_regs (gdbarch
);
8760 gdb_byte reg_buf
[8];
8761 int offset
, double_regnum
;
8763 gdb_assert (regnum
>= num_regs
);
8766 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8767 /* Quad-precision register. */
8768 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
8771 /* Single-precision register. */
8772 gdb_assert (regnum
< 32);
8774 /* s0 is always the least significant half of d0. */
8775 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8776 offset
= (regnum
& 1) ? 0 : 4;
8778 offset
= (regnum
& 1) ? 4 : 0;
8780 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8781 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8784 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8785 memcpy (reg_buf
+ offset
, buf
, 4);
8786 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
8790 static struct value
*
8791 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
8793 const int *reg_p
= (const int *) baton
;
8794 return value_of_register (*reg_p
, frame
);
8797 static enum gdb_osabi
8798 arm_elf_osabi_sniffer (bfd
*abfd
)
8800 unsigned int elfosabi
;
8801 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
8803 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
8805 if (elfosabi
== ELFOSABI_ARM
)
8806 /* GNU tools use this value. Check note sections in this case,
8808 bfd_map_over_sections (abfd
,
8809 generic_elf_osabi_sniff_abi_tag_sections
,
8812 /* Anything else will be handled by the generic ELF sniffer. */
8817 arm_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
8818 struct reggroup
*group
)
8820 /* FPS register's type is INT, but belongs to float_reggroup. Beside
8821 this, FPS register belongs to save_regroup, restore_reggroup, and
8822 all_reggroup, of course. */
8823 if (regnum
== ARM_FPS_REGNUM
)
8824 return (group
== float_reggroup
8825 || group
== save_reggroup
8826 || group
== restore_reggroup
8827 || group
== all_reggroup
);
8829 return default_register_reggroup_p (gdbarch
, regnum
, group
);
8833 /* For backward-compatibility we allow two 'g' packet lengths with
8834 the remote protocol depending on whether FPA registers are
8835 supplied. M-profile targets do not have FPA registers, but some
8836 stubs already exist in the wild which use a 'g' packet which
8837 supplies them albeit with dummy values. The packet format which
8838 includes FPA registers should be considered deprecated for
8839 M-profile targets. */
8842 arm_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8844 if (gdbarch_tdep (gdbarch
)->is_m
)
8846 /* If we know from the executable this is an M-profile target,
8847 cater for remote targets whose register set layout is the
8848 same as the FPA layout. */
8849 register_remote_g_packet_guess (gdbarch
,
8850 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
8851 (16 * INT_REGISTER_SIZE
)
8852 + (8 * FP_REGISTER_SIZE
)
8853 + (2 * INT_REGISTER_SIZE
),
8854 tdesc_arm_with_m_fpa_layout
);
8856 /* The regular M-profile layout. */
8857 register_remote_g_packet_guess (gdbarch
,
8858 /* r0-r12,sp,lr,pc; xpsr */
8859 (16 * INT_REGISTER_SIZE
)
8860 + INT_REGISTER_SIZE
,
8863 /* M-profile plus M4F VFP. */
8864 register_remote_g_packet_guess (gdbarch
,
8865 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
8866 (16 * INT_REGISTER_SIZE
)
8867 + (16 * VFP_REGISTER_SIZE
)
8868 + (2 * INT_REGISTER_SIZE
),
8869 tdesc_arm_with_m_vfp_d16
);
8872 /* Otherwise we don't have a useful guess. */
8876 /* Initialize the current architecture based on INFO. If possible,
8877 re-use an architecture from ARCHES, which is a list of
8878 architectures already created during this debugging session.
8880 Called e.g. at program startup, when reading a core file, and when
8881 reading a binary file. */
8883 static struct gdbarch
*
8884 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8886 struct gdbarch_tdep
*tdep
;
8887 struct gdbarch
*gdbarch
;
8888 struct gdbarch_list
*best_arch
;
8889 enum arm_abi_kind arm_abi
= arm_abi_global
;
8890 enum arm_float_model fp_model
= arm_fp_model
;
8891 struct tdesc_arch_data
*tdesc_data
= NULL
;
8893 int vfp_register_count
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
8894 int have_wmmx_registers
= 0;
8896 int have_fpa_registers
= 1;
8897 const struct target_desc
*tdesc
= info
.target_desc
;
8899 /* If we have an object to base this architecture on, try to determine
8902 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
8904 int ei_osabi
, e_flags
;
8906 switch (bfd_get_flavour (info
.abfd
))
8908 case bfd_target_aout_flavour
:
8909 /* Assume it's an old APCS-style ABI. */
8910 arm_abi
= ARM_ABI_APCS
;
8913 case bfd_target_coff_flavour
:
8914 /* Assume it's an old APCS-style ABI. */
8916 arm_abi
= ARM_ABI_APCS
;
8919 case bfd_target_elf_flavour
:
8920 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
8921 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8923 if (ei_osabi
== ELFOSABI_ARM
)
8925 /* GNU tools used to use this value, but do not for EABI
8926 objects. There's nowhere to tag an EABI version
8927 anyway, so assume APCS. */
8928 arm_abi
= ARM_ABI_APCS
;
8930 else if (ei_osabi
== ELFOSABI_NONE
|| ei_osabi
== ELFOSABI_GNU
)
8932 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
8933 int attr_arch
, attr_profile
;
8937 case EF_ARM_EABI_UNKNOWN
:
8938 /* Assume GNU tools. */
8939 arm_abi
= ARM_ABI_APCS
;
8942 case EF_ARM_EABI_VER4
:
8943 case EF_ARM_EABI_VER5
:
8944 arm_abi
= ARM_ABI_AAPCS
;
8945 /* EABI binaries default to VFP float ordering.
8946 They may also contain build attributes that can
8947 be used to identify if the VFP argument-passing
8949 if (fp_model
== ARM_FLOAT_AUTO
)
8952 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
8956 case AEABI_VFP_args_base
:
8957 /* "The user intended FP parameter/result
8958 passing to conform to AAPCS, base
8960 fp_model
= ARM_FLOAT_SOFT_VFP
;
8962 case AEABI_VFP_args_vfp
:
8963 /* "The user intended FP parameter/result
8964 passing to conform to AAPCS, VFP
8966 fp_model
= ARM_FLOAT_VFP
;
8968 case AEABI_VFP_args_toolchain
:
8969 /* "The user intended FP parameter/result
8970 passing to conform to tool chain-specific
8971 conventions" - we don't know any such
8972 conventions, so leave it as "auto". */
8974 case AEABI_VFP_args_compatible
:
8975 /* "Code is compatible with both the base
8976 and VFP variants; the user did not permit
8977 non-variadic functions to pass FP
8978 parameters/results" - leave it as
8982 /* Attribute value not mentioned in the
8983 November 2012 ABI, so leave it as
8988 fp_model
= ARM_FLOAT_SOFT_VFP
;
8994 /* Leave it as "auto". */
8995 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
9000 /* Detect M-profile programs. This only works if the
9001 executable file includes build attributes; GCC does
9002 copy them to the executable, but e.g. RealView does
9004 attr_arch
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
9006 attr_profile
= bfd_elf_get_obj_attr_int (info
.abfd
,
9008 Tag_CPU_arch_profile
);
9009 /* GCC specifies the profile for v6-M; RealView only
9010 specifies the profile for architectures starting with
9011 V7 (as opposed to architectures with a tag
9012 numerically greater than TAG_CPU_ARCH_V7). */
9013 if (!tdesc_has_registers (tdesc
)
9014 && (attr_arch
== TAG_CPU_ARCH_V6_M
9015 || attr_arch
== TAG_CPU_ARCH_V6S_M
9016 || attr_profile
== 'M'))
9021 if (fp_model
== ARM_FLOAT_AUTO
)
9023 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9025 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
9028 /* Leave it as "auto". Strictly speaking this case
9029 means FPA, but almost nobody uses that now, and
9030 many toolchains fail to set the appropriate bits
9031 for the floating-point model they use. */
9033 case EF_ARM_SOFT_FLOAT
:
9034 fp_model
= ARM_FLOAT_SOFT_FPA
;
9036 case EF_ARM_VFP_FLOAT
:
9037 fp_model
= ARM_FLOAT_VFP
;
9039 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
9040 fp_model
= ARM_FLOAT_SOFT_VFP
;
9045 if (e_flags
& EF_ARM_BE8
)
9046 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
9051 /* Leave it as "auto". */
9056 /* Check any target description for validity. */
9057 if (tdesc_has_registers (tdesc
))
9059 /* For most registers we require GDB's default names; but also allow
9060 the numeric names for sp / lr / pc, as a convenience. */
9061 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
9062 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
9063 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
9065 const struct tdesc_feature
*feature
;
9068 feature
= tdesc_find_feature (tdesc
,
9069 "org.gnu.gdb.arm.core");
9070 if (feature
== NULL
)
9072 feature
= tdesc_find_feature (tdesc
,
9073 "org.gnu.gdb.arm.m-profile");
9074 if (feature
== NULL
)
9080 tdesc_data
= tdesc_data_alloc ();
9083 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
9084 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9085 arm_register_names
[i
]);
9086 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9089 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9092 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9096 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9097 ARM_PS_REGNUM
, "xpsr");
9099 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9100 ARM_PS_REGNUM
, "cpsr");
9104 tdesc_data_cleanup (tdesc_data
);
9108 feature
= tdesc_find_feature (tdesc
,
9109 "org.gnu.gdb.arm.fpa");
9110 if (feature
!= NULL
)
9113 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
9114 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9115 arm_register_names
[i
]);
9118 tdesc_data_cleanup (tdesc_data
);
9123 have_fpa_registers
= 0;
9125 feature
= tdesc_find_feature (tdesc
,
9126 "org.gnu.gdb.xscale.iwmmxt");
9127 if (feature
!= NULL
)
9129 static const char *const iwmmxt_names
[] = {
9130 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
9131 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
9132 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
9133 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
9137 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
9139 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9140 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9142 /* Check for the control registers, but do not fail if they
9144 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
9145 tdesc_numbered_register (feature
, tdesc_data
, i
,
9146 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9148 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
9150 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9151 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9155 tdesc_data_cleanup (tdesc_data
);
9159 have_wmmx_registers
= 1;
9162 /* If we have a VFP unit, check whether the single precision registers
9163 are present. If not, then we will synthesize them as pseudo
9165 feature
= tdesc_find_feature (tdesc
,
9166 "org.gnu.gdb.arm.vfp");
9167 if (feature
!= NULL
)
9169 static const char *const vfp_double_names
[] = {
9170 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
9171 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
9172 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
9173 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
9176 /* Require the double precision registers. There must be either
9179 for (i
= 0; i
< 32; i
++)
9181 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9183 vfp_double_names
[i
]);
9187 if (!valid_p
&& i
== 16)
9190 /* Also require FPSCR. */
9191 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9192 ARM_FPSCR_REGNUM
, "fpscr");
9195 tdesc_data_cleanup (tdesc_data
);
9199 if (tdesc_unnumbered_register (feature
, "s0") == 0)
9200 have_vfp_pseudos
= 1;
9202 vfp_register_count
= i
;
9204 /* If we have VFP, also check for NEON. The architecture allows
9205 NEON without VFP (integer vector operations only), but GDB
9206 does not support that. */
9207 feature
= tdesc_find_feature (tdesc
,
9208 "org.gnu.gdb.arm.neon");
9209 if (feature
!= NULL
)
9211 /* NEON requires 32 double-precision registers. */
9214 tdesc_data_cleanup (tdesc_data
);
9218 /* If there are quad registers defined by the stub, use
9219 their type; otherwise (normally) provide them with
9220 the default type. */
9221 if (tdesc_unnumbered_register (feature
, "q0") == 0)
9222 have_neon_pseudos
= 1;
9229 /* If there is already a candidate, use it. */
9230 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
9232 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
9234 if (arm_abi
!= ARM_ABI_AUTO
9235 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
9238 if (fp_model
!= ARM_FLOAT_AUTO
9239 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
9242 /* There are various other properties in tdep that we do not
9243 need to check here: those derived from a target description,
9244 since gdbarches with a different target description are
9245 automatically disqualified. */
9247 /* Do check is_m, though, since it might come from the binary. */
9248 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
9251 /* Found a match. */
9255 if (best_arch
!= NULL
)
9257 if (tdesc_data
!= NULL
)
9258 tdesc_data_cleanup (tdesc_data
);
9259 return best_arch
->gdbarch
;
9262 tdep
= XCNEW (struct gdbarch_tdep
);
9263 gdbarch
= gdbarch_alloc (&info
, tdep
);
9265 /* Record additional information about the architecture we are defining.
9266 These are gdbarch discriminators, like the OSABI. */
9267 tdep
->arm_abi
= arm_abi
;
9268 tdep
->fp_model
= fp_model
;
9270 tdep
->have_fpa_registers
= have_fpa_registers
;
9271 tdep
->have_wmmx_registers
= have_wmmx_registers
;
9272 gdb_assert (vfp_register_count
== 0
9273 || vfp_register_count
== 16
9274 || vfp_register_count
== 32);
9275 tdep
->vfp_register_count
= vfp_register_count
;
9276 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
9277 tdep
->have_neon_pseudos
= have_neon_pseudos
;
9278 tdep
->have_neon
= have_neon
;
9280 arm_register_g_packet_guesses (gdbarch
);
9283 switch (info
.byte_order_for_code
)
9285 case BFD_ENDIAN_BIG
:
9286 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
9287 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
9288 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
9289 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
9293 case BFD_ENDIAN_LITTLE
:
9294 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
9295 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
9296 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
9297 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
9302 internal_error (__FILE__
, __LINE__
,
9303 _("arm_gdbarch_init: bad byte order for float format"));
9306 /* On ARM targets char defaults to unsigned. */
9307 set_gdbarch_char_signed (gdbarch
, 0);
9309 /* Note: for displaced stepping, this includes the breakpoint, and one word
9310 of additional scratch space. This setting isn't used for anything beside
9311 displaced stepping at present. */
9312 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
9314 /* This should be low enough for everything. */
9315 tdep
->lowest_pc
= 0x20;
9316 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
9318 /* The default, for both APCS and AAPCS, is to return small
9319 structures in registers. */
9320 tdep
->struct_return
= reg_struct_return
;
9322 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
9323 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
9325 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
9327 /* Frame handling. */
9328 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
9329 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
9330 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
9332 frame_base_set_default (gdbarch
, &arm_normal_base
);
9334 /* Address manipulation. */
9335 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
9337 /* Advance PC across function entry code. */
9338 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
9340 /* Detect whether PC is at a point where the stack has been destroyed. */
9341 set_gdbarch_stack_frame_destroyed_p (gdbarch
, arm_stack_frame_destroyed_p
);
9343 /* Skip trampolines. */
9344 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
9346 /* The stack grows downward. */
9347 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
9349 /* Breakpoint manipulation. */
9350 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
9351 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
9352 arm_remote_breakpoint_from_pc
);
9354 /* Information about registers, etc. */
9355 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
9356 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
9357 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
9358 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9359 set_gdbarch_register_reggroup_p (gdbarch
, arm_register_reggroup_p
);
9361 /* This "info float" is FPA-specific. Use the generic version if we
9363 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
9364 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
9366 /* Internal <-> external register number maps. */
9367 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
9368 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
9370 set_gdbarch_register_name (gdbarch
, arm_register_name
);
9372 /* Returning results. */
9373 set_gdbarch_return_value (gdbarch
, arm_return_value
);
9376 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
9378 /* Minsymbol frobbing. */
9379 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
9380 set_gdbarch_coff_make_msymbol_special (gdbarch
,
9381 arm_coff_make_msymbol_special
);
9382 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
9384 /* Thumb-2 IT block support. */
9385 set_gdbarch_adjust_breakpoint_address (gdbarch
,
9386 arm_adjust_breakpoint_address
);
9388 /* Virtual tables. */
9389 set_gdbarch_vbit_in_delta (gdbarch
, 1);
9391 /* Hook in the ABI-specific overrides, if they have been registered. */
9392 gdbarch_init_osabi (info
, gdbarch
);
9394 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
9396 /* Add some default predicates. */
9398 frame_unwind_append_unwinder (gdbarch
, &arm_m_exception_unwind
);
9399 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
9400 dwarf2_append_unwinders (gdbarch
);
9401 frame_unwind_append_unwinder (gdbarch
, &arm_exidx_unwind
);
9402 frame_unwind_append_unwinder (gdbarch
, &arm_epilogue_frame_unwind
);
9403 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
9405 /* Now we have tuned the configuration, set a few final things,
9406 based on what the OS ABI has told us. */
9408 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
9409 binaries are always marked. */
9410 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
9411 tdep
->arm_abi
= ARM_ABI_APCS
;
9413 /* Watchpoints are not steppable. */
9414 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
9416 /* We used to default to FPA for generic ARM, but almost nobody
9417 uses that now, and we now provide a way for the user to force
9418 the model. So default to the most useful variant. */
9419 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
9420 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
9422 if (tdep
->jb_pc
>= 0)
9423 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
9425 /* Floating point sizes and format. */
9426 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
9427 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
9429 set_gdbarch_double_format
9430 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9431 set_gdbarch_long_double_format
9432 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9436 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
9437 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
9440 if (have_vfp_pseudos
)
9442 /* NOTE: These are the only pseudo registers used by
9443 the ARM target at the moment. If more are added, a
9444 little more care in numbering will be needed. */
9446 int num_pseudos
= 32;
9447 if (have_neon_pseudos
)
9449 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
9450 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
9451 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
9456 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
9458 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
9460 /* Override tdesc_register_type to adjust the types of VFP
9461 registers for NEON. */
9462 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9465 /* Add standard register aliases. We add aliases even for those
9466 nanes which are used by the current architecture - it's simpler,
9467 and does no harm, since nothing ever lists user registers. */
9468 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
9469 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
9470 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
9476 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
9478 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9483 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
9484 (unsigned long) tdep
->lowest_pc
);
9487 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
9490 _initialize_arm_tdep (void)
9492 struct ui_file
*stb
;
9494 const char *setname
;
9495 const char *setdesc
;
9496 const char *const *regnames
;
9498 static char *helptext
;
9499 char regdesc
[1024], *rdptr
= regdesc
;
9500 size_t rest
= sizeof (regdesc
);
9502 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
9504 arm_objfile_data_key
9505 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
9507 /* Add ourselves to objfile event chain. */
9508 observer_attach_new_objfile (arm_exidx_new_objfile
);
9510 = register_objfile_data_with_cleanup (NULL
, arm_exidx_data_free
);
9512 /* Register an ELF OS ABI sniffer for ARM binaries. */
9513 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
9514 bfd_target_elf_flavour
,
9515 arm_elf_osabi_sniffer
);
9517 /* Initialize the standard target descriptions. */
9518 initialize_tdesc_arm_with_m ();
9519 initialize_tdesc_arm_with_m_fpa_layout ();
9520 initialize_tdesc_arm_with_m_vfp_d16 ();
9521 initialize_tdesc_arm_with_iwmmxt ();
9522 initialize_tdesc_arm_with_vfpv2 ();
9523 initialize_tdesc_arm_with_vfpv3 ();
9524 initialize_tdesc_arm_with_neon ();
9526 /* Get the number of possible sets of register names defined in opcodes. */
9527 num_disassembly_options
= get_arm_regname_num_options ();
9529 /* Add root prefix command for all "set arm"/"show arm" commands. */
9530 add_prefix_cmd ("arm", no_class
, set_arm_command
,
9531 _("Various ARM-specific commands."),
9532 &setarmcmdlist
, "set arm ", 0, &setlist
);
9534 add_prefix_cmd ("arm", no_class
, show_arm_command
,
9535 _("Various ARM-specific commands."),
9536 &showarmcmdlist
, "show arm ", 0, &showlist
);
9538 /* Sync the opcode insn printer with our register viewer. */
9539 parse_arm_disassembler_option ("reg-names-std");
9541 /* Initialize the array that will be passed to
9542 add_setshow_enum_cmd(). */
9543 valid_disassembly_styles
= XNEWVEC (const char *,
9544 num_disassembly_options
+ 1);
9545 for (i
= 0; i
< num_disassembly_options
; i
++)
9547 get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
9548 valid_disassembly_styles
[i
] = setname
;
9549 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
9552 /* When we find the default names, tell the disassembler to use
9554 if (!strcmp (setname
, "std"))
9556 disassembly_style
= setname
;
9557 set_arm_regname_option (i
);
9560 /* Mark the end of valid options. */
9561 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
9563 /* Create the help text. */
9564 stb
= mem_fileopen ();
9565 fprintf_unfiltered (stb
, "%s%s%s",
9566 _("The valid values are:\n"),
9568 _("The default is \"std\"."));
9569 helptext
= ui_file_xstrdup (stb
, NULL
);
9570 ui_file_delete (stb
);
9572 add_setshow_enum_cmd("disassembler", no_class
,
9573 valid_disassembly_styles
, &disassembly_style
,
9574 _("Set the disassembly style."),
9575 _("Show the disassembly style."),
9577 set_disassembly_style_sfunc
,
9578 NULL
, /* FIXME: i18n: The disassembly style is
9580 &setarmcmdlist
, &showarmcmdlist
);
9582 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
9583 _("Set usage of ARM 32-bit mode."),
9584 _("Show usage of ARM 32-bit mode."),
9585 _("When off, a 26-bit PC will be used."),
9587 NULL
, /* FIXME: i18n: Usage of ARM 32-bit
9589 &setarmcmdlist
, &showarmcmdlist
);
9591 /* Add a command to allow the user to force the FPU model. */
9592 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
9593 _("Set the floating point type."),
9594 _("Show the floating point type."),
9595 _("auto - Determine the FP typefrom the OS-ABI.\n\
9596 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
9597 fpa - FPA co-processor (GCC compiled).\n\
9598 softvfp - Software FP with pure-endian doubles.\n\
9599 vfp - VFP co-processor."),
9600 set_fp_model_sfunc
, show_fp_model
,
9601 &setarmcmdlist
, &showarmcmdlist
);
9603 /* Add a command to allow the user to force the ABI. */
9604 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
9607 NULL
, arm_set_abi
, arm_show_abi
,
9608 &setarmcmdlist
, &showarmcmdlist
);
9610 /* Add two commands to allow the user to force the assumed
9612 add_setshow_enum_cmd ("fallback-mode", class_support
,
9613 arm_mode_strings
, &arm_fallback_mode_string
,
9614 _("Set the mode assumed when symbols are unavailable."),
9615 _("Show the mode assumed when symbols are unavailable."),
9616 NULL
, NULL
, arm_show_fallback_mode
,
9617 &setarmcmdlist
, &showarmcmdlist
);
9618 add_setshow_enum_cmd ("force-mode", class_support
,
9619 arm_mode_strings
, &arm_force_mode_string
,
9620 _("Set the mode assumed even when symbols are available."),
9621 _("Show the mode assumed even when symbols are available."),
9622 NULL
, NULL
, arm_show_force_mode
,
9623 &setarmcmdlist
, &showarmcmdlist
);
9625 /* Debugging flag. */
9626 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
9627 _("Set ARM debugging."),
9628 _("Show ARM debugging."),
9629 _("When on, arm-specific debugging is enabled."),
9631 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
9632 &setdebuglist
, &showdebuglist
);
9635 /* ARM-reversible process record data structures. */
9637 #define ARM_INSN_SIZE_BYTES 4
9638 #define THUMB_INSN_SIZE_BYTES 2
9639 #define THUMB2_INSN_SIZE_BYTES 4
9642 /* Position of the bit within a 32-bit ARM instruction
9643 that defines whether the instruction is a load or store. */
9644 #define INSN_S_L_BIT_NUM 20
9646 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
9649 unsigned int reg_len = LENGTH; \
9652 REGS = XNEWVEC (uint32_t, reg_len); \
9653 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
9658 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
9661 unsigned int mem_len = LENGTH; \
9664 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
9665 memcpy(&MEMS->len, &RECORD_BUF[0], \
9666 sizeof(struct arm_mem_r) * LENGTH); \
9671 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
9672 #define INSN_RECORDED(ARM_RECORD) \
9673 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
9675 /* ARM memory record structure. */
9678 uint32_t len
; /* Record length. */
9679 uint32_t addr
; /* Memory address. */
9682 /* ARM instruction record contains opcode of current insn
9683 and execution state (before entry to decode_insn()),
9684 contains list of to-be-modified registers and
9685 memory blocks (on return from decode_insn()). */
9687 typedef struct insn_decode_record_t
9689 struct gdbarch
*gdbarch
;
9690 struct regcache
*regcache
;
9691 CORE_ADDR this_addr
; /* Address of the insn being decoded. */
9692 uint32_t arm_insn
; /* Should accommodate thumb. */
9693 uint32_t cond
; /* Condition code. */
9694 uint32_t opcode
; /* Insn opcode. */
9695 uint32_t decode
; /* Insn decode bits. */
9696 uint32_t mem_rec_count
; /* No of mem records. */
9697 uint32_t reg_rec_count
; /* No of reg records. */
9698 uint32_t *arm_regs
; /* Registers to be saved for this record. */
9699 struct arm_mem_r
*arm_mems
; /* Memory to be saved for this record. */
9700 } insn_decode_record
;
9703 /* Checks ARM SBZ and SBO mandatory fields. */
9706 sbo_sbz (uint32_t insn
, uint32_t bit_num
, uint32_t len
, uint32_t sbo
)
9708 uint32_t ones
= bits (insn
, bit_num
- 1, (bit_num
-1) + (len
- 1));
9727 enum arm_record_result
9729 ARM_RECORD_SUCCESS
= 0,
9730 ARM_RECORD_FAILURE
= 1
9737 } arm_record_strx_t
;
9748 arm_record_strx (insn_decode_record
*arm_insn_r
, uint32_t *record_buf
,
9749 uint32_t *record_buf_mem
, arm_record_strx_t str_type
)
9752 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
9753 ULONGEST u_regval
[2]= {0};
9755 uint32_t reg_src1
= 0, reg_src2
= 0;
9756 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
9758 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
9759 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
9761 if (14 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
9763 /* 1) Handle misc store, immediate offset. */
9764 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9765 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9766 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9767 regcache_raw_read_unsigned (reg_cache
, reg_src1
,
9769 if (ARM_PC_REGNUM
== reg_src1
)
9771 /* If R15 was used as Rn, hence current PC+8. */
9772 u_regval
[0] = u_regval
[0] + 8;
9774 offset_8
= (immed_high
<< 4) | immed_low
;
9775 /* Calculate target store address. */
9776 if (14 == arm_insn_r
->opcode
)
9778 tgt_mem_addr
= u_regval
[0] + offset_8
;
9782 tgt_mem_addr
= u_regval
[0] - offset_8
;
9784 if (ARM_RECORD_STRH
== str_type
)
9786 record_buf_mem
[0] = 2;
9787 record_buf_mem
[1] = tgt_mem_addr
;
9788 arm_insn_r
->mem_rec_count
= 1;
9790 else if (ARM_RECORD_STRD
== str_type
)
9792 record_buf_mem
[0] = 4;
9793 record_buf_mem
[1] = tgt_mem_addr
;
9794 record_buf_mem
[2] = 4;
9795 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9796 arm_insn_r
->mem_rec_count
= 2;
9799 else if (12 == arm_insn_r
->opcode
|| 8 == arm_insn_r
->opcode
)
9801 /* 2) Store, register offset. */
9803 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9805 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9806 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9807 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9810 /* If R15 was used as Rn, hence current PC+8. */
9811 u_regval
[0] = u_regval
[0] + 8;
9813 /* Calculate target store address, Rn +/- Rm, register offset. */
9814 if (12 == arm_insn_r
->opcode
)
9816 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9820 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9822 if (ARM_RECORD_STRH
== str_type
)
9824 record_buf_mem
[0] = 2;
9825 record_buf_mem
[1] = tgt_mem_addr
;
9826 arm_insn_r
->mem_rec_count
= 1;
9828 else if (ARM_RECORD_STRD
== str_type
)
9830 record_buf_mem
[0] = 4;
9831 record_buf_mem
[1] = tgt_mem_addr
;
9832 record_buf_mem
[2] = 4;
9833 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9834 arm_insn_r
->mem_rec_count
= 2;
9837 else if (11 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
9838 || 2 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9840 /* 3) Store, immediate pre-indexed. */
9841 /* 5) Store, immediate post-indexed. */
9842 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9843 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9844 offset_8
= (immed_high
<< 4) | immed_low
;
9845 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9846 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9847 /* Calculate target store address, Rn +/- Rm, register offset. */
9848 if (15 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9850 tgt_mem_addr
= u_regval
[0] + offset_8
;
9854 tgt_mem_addr
= u_regval
[0] - offset_8
;
9856 if (ARM_RECORD_STRH
== str_type
)
9858 record_buf_mem
[0] = 2;
9859 record_buf_mem
[1] = tgt_mem_addr
;
9860 arm_insn_r
->mem_rec_count
= 1;
9862 else if (ARM_RECORD_STRD
== str_type
)
9864 record_buf_mem
[0] = 4;
9865 record_buf_mem
[1] = tgt_mem_addr
;
9866 record_buf_mem
[2] = 4;
9867 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9868 arm_insn_r
->mem_rec_count
= 2;
9870 /* Record Rn also as it changes. */
9871 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
9872 arm_insn_r
->reg_rec_count
= 1;
9874 else if (9 == arm_insn_r
->opcode
|| 13 == arm_insn_r
->opcode
9875 || 0 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9877 /* 4) Store, register pre-indexed. */
9878 /* 6) Store, register post -indexed. */
9879 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9880 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9881 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9882 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9883 /* Calculate target store address, Rn +/- Rm, register offset. */
9884 if (13 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9886 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9890 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9892 if (ARM_RECORD_STRH
== str_type
)
9894 record_buf_mem
[0] = 2;
9895 record_buf_mem
[1] = tgt_mem_addr
;
9896 arm_insn_r
->mem_rec_count
= 1;
9898 else if (ARM_RECORD_STRD
== str_type
)
9900 record_buf_mem
[0] = 4;
9901 record_buf_mem
[1] = tgt_mem_addr
;
9902 record_buf_mem
[2] = 4;
9903 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9904 arm_insn_r
->mem_rec_count
= 2;
9906 /* Record Rn also as it changes. */
9907 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
9908 arm_insn_r
->reg_rec_count
= 1;
9913 /* Handling ARM extension space insns. */
9916 arm_record_extension_space (insn_decode_record
*arm_insn_r
)
9918 uint32_t ret
= 0; /* Return value: -1:record failure ; 0:success */
9919 uint32_t opcode1
= 0, opcode2
= 0, insn_op1
= 0;
9920 uint32_t record_buf
[8], record_buf_mem
[8];
9921 uint32_t reg_src1
= 0;
9922 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
9923 ULONGEST u_regval
= 0;
9925 gdb_assert (!INSN_RECORDED(arm_insn_r
));
9926 /* Handle unconditional insn extension space. */
9928 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 27);
9929 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
9930 if (arm_insn_r
->cond
)
9932 /* PLD has no affect on architectural state, it just affects
9934 if (5 == ((opcode1
& 0xE0) >> 5))
9937 record_buf
[0] = ARM_PS_REGNUM
;
9938 record_buf
[1] = ARM_LR_REGNUM
;
9939 arm_insn_r
->reg_rec_count
= 2;
9941 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
9945 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
9946 if (3 == opcode1
&& bit (arm_insn_r
->arm_insn
, 4))
9949 /* Undefined instruction on ARM V5; need to handle if later
9950 versions define it. */
9953 opcode1
= bits (arm_insn_r
->arm_insn
, 24, 27);
9954 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
9955 insn_op1
= bits (arm_insn_r
->arm_insn
, 20, 23);
9957 /* Handle arithmetic insn extension space. */
9958 if (!opcode1
&& 9 == opcode2
&& 1 != arm_insn_r
->cond
9959 && !INSN_RECORDED(arm_insn_r
))
9961 /* Handle MLA(S) and MUL(S). */
9962 if (0 <= insn_op1
&& 3 >= insn_op1
)
9964 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
9965 record_buf
[1] = ARM_PS_REGNUM
;
9966 arm_insn_r
->reg_rec_count
= 2;
9968 else if (4 <= insn_op1
&& 15 >= insn_op1
)
9970 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
9971 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
9972 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
9973 record_buf
[2] = ARM_PS_REGNUM
;
9974 arm_insn_r
->reg_rec_count
= 3;
9978 opcode1
= bits (arm_insn_r
->arm_insn
, 26, 27);
9979 opcode2
= bits (arm_insn_r
->arm_insn
, 23, 24);
9980 insn_op1
= bits (arm_insn_r
->arm_insn
, 21, 22);
9982 /* Handle control insn extension space. */
9984 if (!opcode1
&& 2 == opcode2
&& !bit (arm_insn_r
->arm_insn
, 20)
9985 && 1 != arm_insn_r
->cond
&& !INSN_RECORDED(arm_insn_r
))
9987 if (!bit (arm_insn_r
->arm_insn
,25))
9989 if (!bits (arm_insn_r
->arm_insn
, 4, 7))
9991 if ((0 == insn_op1
) || (2 == insn_op1
))
9994 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
9995 arm_insn_r
->reg_rec_count
= 1;
9997 else if (1 == insn_op1
)
9999 /* CSPR is going to be changed. */
10000 record_buf
[0] = ARM_PS_REGNUM
;
10001 arm_insn_r
->reg_rec_count
= 1;
10003 else if (3 == insn_op1
)
10005 /* SPSR is going to be changed. */
10006 /* We need to get SPSR value, which is yet to be done. */
10010 else if (1 == bits (arm_insn_r
->arm_insn
, 4, 7))
10015 record_buf
[0] = ARM_PS_REGNUM
;
10016 arm_insn_r
->reg_rec_count
= 1;
10018 else if (3 == insn_op1
)
10021 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10022 arm_insn_r
->reg_rec_count
= 1;
10025 else if (3 == bits (arm_insn_r
->arm_insn
, 4, 7))
10028 record_buf
[0] = ARM_PS_REGNUM
;
10029 record_buf
[1] = ARM_LR_REGNUM
;
10030 arm_insn_r
->reg_rec_count
= 2;
10032 else if (5 == bits (arm_insn_r
->arm_insn
, 4, 7))
10034 /* QADD, QSUB, QDADD, QDSUB */
10035 record_buf
[0] = ARM_PS_REGNUM
;
10036 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10037 arm_insn_r
->reg_rec_count
= 2;
10039 else if (7 == bits (arm_insn_r
->arm_insn
, 4, 7))
10042 record_buf
[0] = ARM_PS_REGNUM
;
10043 record_buf
[1] = ARM_LR_REGNUM
;
10044 arm_insn_r
->reg_rec_count
= 2;
10046 /* Save SPSR also;how? */
10049 else if(8 == bits (arm_insn_r
->arm_insn
, 4, 7)
10050 || 10 == bits (arm_insn_r
->arm_insn
, 4, 7)
10051 || 12 == bits (arm_insn_r
->arm_insn
, 4, 7)
10052 || 14 == bits (arm_insn_r
->arm_insn
, 4, 7)
10055 if (0 == insn_op1
|| 1 == insn_op1
)
10057 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
10058 /* We dont do optimization for SMULW<y> where we
10060 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10061 record_buf
[1] = ARM_PS_REGNUM
;
10062 arm_insn_r
->reg_rec_count
= 2;
10064 else if (2 == insn_op1
)
10067 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10068 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
10069 arm_insn_r
->reg_rec_count
= 2;
10071 else if (3 == insn_op1
)
10074 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10075 arm_insn_r
->reg_rec_count
= 1;
10081 /* MSR : immediate form. */
10084 /* CSPR is going to be changed. */
10085 record_buf
[0] = ARM_PS_REGNUM
;
10086 arm_insn_r
->reg_rec_count
= 1;
10088 else if (3 == insn_op1
)
10090 /* SPSR is going to be changed. */
10091 /* we need to get SPSR value, which is yet to be done */
10097 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10098 opcode2
= bits (arm_insn_r
->arm_insn
, 20, 24);
10099 insn_op1
= bits (arm_insn_r
->arm_insn
, 5, 6);
10101 /* Handle load/store insn extension space. */
10103 if (!opcode1
&& bit (arm_insn_r
->arm_insn
, 7)
10104 && bit (arm_insn_r
->arm_insn
, 4) && 1 != arm_insn_r
->cond
10105 && !INSN_RECORDED(arm_insn_r
))
10110 /* These insn, changes register and memory as well. */
10111 /* SWP or SWPB insn. */
10112 /* Get memory address given by Rn. */
10113 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10114 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
10115 /* SWP insn ?, swaps word. */
10116 if (8 == arm_insn_r
->opcode
)
10118 record_buf_mem
[0] = 4;
10122 /* SWPB insn, swaps only byte. */
10123 record_buf_mem
[0] = 1;
10125 record_buf_mem
[1] = u_regval
;
10126 arm_insn_r
->mem_rec_count
= 1;
10127 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10128 arm_insn_r
->reg_rec_count
= 1;
10130 else if (1 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10133 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10136 else if (2 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10139 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10140 record_buf
[1] = record_buf
[0] + 1;
10141 arm_insn_r
->reg_rec_count
= 2;
10143 else if (3 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10146 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10149 else if (bit (arm_insn_r
->arm_insn
, 20) && insn_op1
<= 3)
10151 /* LDRH, LDRSB, LDRSH. */
10152 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10153 arm_insn_r
->reg_rec_count
= 1;
10158 opcode1
= bits (arm_insn_r
->arm_insn
, 23, 27);
10159 if (24 == opcode1
&& bit (arm_insn_r
->arm_insn
, 21)
10160 && !INSN_RECORDED(arm_insn_r
))
10163 /* Handle coprocessor insn extension space. */
10166 /* To be done for ARMv5 and later; as of now we return -1. */
10170 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10171 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10176 /* Handling opcode 000 insns. */
10179 arm_record_data_proc_misc_ld_str (insn_decode_record
*arm_insn_r
)
10181 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10182 uint32_t record_buf
[8], record_buf_mem
[8];
10183 ULONGEST u_regval
[2] = {0};
10185 uint32_t reg_src1
= 0, reg_dest
= 0;
10186 uint32_t opcode1
= 0;
10188 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10189 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10190 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
10192 /* Data processing insn /multiply insn. */
10193 if (9 == arm_insn_r
->decode
10194 && ((4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
10195 || (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)))
10197 /* Handle multiply instructions. */
10198 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
10199 if (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)
10201 /* Handle MLA and MUL. */
10202 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10203 record_buf
[1] = ARM_PS_REGNUM
;
10204 arm_insn_r
->reg_rec_count
= 2;
10206 else if (4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
10208 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
10209 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10210 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10211 record_buf
[2] = ARM_PS_REGNUM
;
10212 arm_insn_r
->reg_rec_count
= 3;
10215 else if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
10216 && (11 == arm_insn_r
->decode
|| 13 == arm_insn_r
->decode
))
10218 /* Handle misc load insns, as 20th bit (L = 1). */
10219 /* LDR insn has a capability to do branching, if
10220 MOV LR, PC is precceded by LDR insn having Rn as R15
10221 in that case, it emulates branch and link insn, and hence we
10222 need to save CSPR and PC as well. I am not sure this is right
10223 place; as opcode = 010 LDR insn make this happen, if R15 was
10225 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10226 if (15 != reg_dest
)
10228 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10229 arm_insn_r
->reg_rec_count
= 1;
10233 record_buf
[0] = reg_dest
;
10234 record_buf
[1] = ARM_PS_REGNUM
;
10235 arm_insn_r
->reg_rec_count
= 2;
10238 else if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
10239 && sbo_sbz (arm_insn_r
->arm_insn
, 5, 12, 0)
10240 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
10241 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21))
10243 /* Handle MSR insn. */
10244 if (9 == arm_insn_r
->opcode
)
10246 /* CSPR is going to be changed. */
10247 record_buf
[0] = ARM_PS_REGNUM
;
10248 arm_insn_r
->reg_rec_count
= 1;
10252 /* SPSR is going to be changed. */
10253 /* How to read SPSR value? */
10257 else if (9 == arm_insn_r
->decode
10258 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10259 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10261 /* Handling SWP, SWPB. */
10262 /* These insn, changes register and memory as well. */
10263 /* SWP or SWPB insn. */
10265 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10266 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10267 /* SWP insn ?, swaps word. */
10268 if (8 == arm_insn_r
->opcode
)
10270 record_buf_mem
[0] = 4;
10274 /* SWPB insn, swaps only byte. */
10275 record_buf_mem
[0] = 1;
10277 record_buf_mem
[1] = u_regval
[0];
10278 arm_insn_r
->mem_rec_count
= 1;
10279 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10280 arm_insn_r
->reg_rec_count
= 1;
10282 else if (3 == arm_insn_r
->decode
&& 0x12 == opcode1
10283 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10285 /* Handle BLX, branch and link/exchange. */
10286 if (9 == arm_insn_r
->opcode
)
10288 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
10289 and R14 stores the return address. */
10290 record_buf
[0] = ARM_PS_REGNUM
;
10291 record_buf
[1] = ARM_LR_REGNUM
;
10292 arm_insn_r
->reg_rec_count
= 2;
10295 else if (7 == arm_insn_r
->decode
&& 0x12 == opcode1
)
10297 /* Handle enhanced software breakpoint insn, BKPT. */
10298 /* CPSR is changed to be executed in ARM state, disabling normal
10299 interrupts, entering abort mode. */
10300 /* According to high vector configuration PC is set. */
10301 /* user hit breakpoint and type reverse, in
10302 that case, we need to go back with previous CPSR and
10303 Program Counter. */
10304 record_buf
[0] = ARM_PS_REGNUM
;
10305 record_buf
[1] = ARM_LR_REGNUM
;
10306 arm_insn_r
->reg_rec_count
= 2;
10308 /* Save SPSR also; how? */
10311 else if (11 == arm_insn_r
->decode
10312 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10314 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
10316 /* Handle str(x) insn */
10317 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10320 else if (1 == arm_insn_r
->decode
&& 0x12 == opcode1
10321 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10323 /* Handle BX, branch and link/exchange. */
10324 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
10325 record_buf
[0] = ARM_PS_REGNUM
;
10326 arm_insn_r
->reg_rec_count
= 1;
10328 else if (1 == arm_insn_r
->decode
&& 0x16 == opcode1
10329 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 4, 1)
10330 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1))
10332 /* Count leading zeros: CLZ. */
10333 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10334 arm_insn_r
->reg_rec_count
= 1;
10336 else if (!bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
10337 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10338 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1)
10339 && sbo_sbz (arm_insn_r
->arm_insn
, 1, 12, 0)
10342 /* Handle MRS insn. */
10343 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10344 arm_insn_r
->reg_rec_count
= 1;
10346 else if (arm_insn_r
->opcode
<= 15)
10348 /* Normal data processing insns. */
10349 /* Out of 11 shifter operands mode, all the insn modifies destination
10350 register, which is specified by 13-16 decode. */
10351 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10352 record_buf
[1] = ARM_PS_REGNUM
;
10353 arm_insn_r
->reg_rec_count
= 2;
10360 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10361 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10365 /* Handling opcode 001 insns. */
10368 arm_record_data_proc_imm (insn_decode_record
*arm_insn_r
)
10370 uint32_t record_buf
[8], record_buf_mem
[8];
10372 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10373 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10375 if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
10376 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21)
10377 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
10380 /* Handle MSR insn. */
10381 if (9 == arm_insn_r
->opcode
)
10383 /* CSPR is going to be changed. */
10384 record_buf
[0] = ARM_PS_REGNUM
;
10385 arm_insn_r
->reg_rec_count
= 1;
10389 /* SPSR is going to be changed. */
10392 else if (arm_insn_r
->opcode
<= 15)
10394 /* Normal data processing insns. */
10395 /* Out of 11 shifter operands mode, all the insn modifies destination
10396 register, which is specified by 13-16 decode. */
10397 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10398 record_buf
[1] = ARM_PS_REGNUM
;
10399 arm_insn_r
->reg_rec_count
= 2;
10406 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10407 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10412 arm_record_media (insn_decode_record
*arm_insn_r
)
10414 uint32_t record_buf
[8];
10416 switch (bits (arm_insn_r
->arm_insn
, 22, 24))
10419 /* Parallel addition and subtraction, signed */
10421 /* Parallel addition and subtraction, unsigned */
10424 /* Packing, unpacking, saturation and reversal */
10426 int rd
= bits (arm_insn_r
->arm_insn
, 12, 15);
10428 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10434 /* Signed multiplies */
10436 int rd
= bits (arm_insn_r
->arm_insn
, 16, 19);
10437 unsigned int op1
= bits (arm_insn_r
->arm_insn
, 20, 22);
10439 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10441 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10442 else if (op1
== 0x4)
10443 record_buf
[arm_insn_r
->reg_rec_count
++]
10444 = bits (arm_insn_r
->arm_insn
, 12, 15);
10450 if (bit (arm_insn_r
->arm_insn
, 21)
10451 && bits (arm_insn_r
->arm_insn
, 5, 6) == 0x2)
10454 record_buf
[arm_insn_r
->reg_rec_count
++]
10455 = bits (arm_insn_r
->arm_insn
, 12, 15);
10457 else if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x0
10458 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x0)
10460 /* USAD8 and USADA8 */
10461 record_buf
[arm_insn_r
->reg_rec_count
++]
10462 = bits (arm_insn_r
->arm_insn
, 16, 19);
10469 if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x3
10470 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x7)
10472 /* Permanently UNDEFINED */
10477 /* BFC, BFI and UBFX */
10478 record_buf
[arm_insn_r
->reg_rec_count
++]
10479 = bits (arm_insn_r
->arm_insn
, 12, 15);
10488 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10493 /* Handle ARM mode instructions with opcode 010. */
10496 arm_record_ld_st_imm_offset (insn_decode_record
*arm_insn_r
)
10498 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10500 uint32_t reg_base
, reg_dest
;
10501 uint32_t offset_12
, tgt_mem_addr
;
10502 uint32_t record_buf
[8], record_buf_mem
[8];
10503 unsigned char wback
;
10506 /* Calculate wback. */
10507 wback
= (bit (arm_insn_r
->arm_insn
, 24) == 0)
10508 || (bit (arm_insn_r
->arm_insn
, 21) == 1);
10510 arm_insn_r
->reg_rec_count
= 0;
10511 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
10513 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10515 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
10518 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10519 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_dest
;
10521 /* The LDR instruction is capable of doing branching. If MOV LR, PC
10522 preceeds a LDR instruction having R15 as reg_base, it
10523 emulates a branch and link instruction, and hence we need to save
10524 CPSR and PC as well. */
10525 if (ARM_PC_REGNUM
== reg_dest
)
10526 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10528 /* If wback is true, also save the base register, which is going to be
10531 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10535 /* STR (immediate), STRB (immediate), STRBT and STRT. */
10537 offset_12
= bits (arm_insn_r
->arm_insn
, 0, 11);
10538 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
10540 /* Handle bit U. */
10541 if (bit (arm_insn_r
->arm_insn
, 23))
10543 /* U == 1: Add the offset. */
10544 tgt_mem_addr
= (uint32_t) u_regval
+ offset_12
;
10548 /* U == 0: subtract the offset. */
10549 tgt_mem_addr
= (uint32_t) u_regval
- offset_12
;
10552 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
10554 if (bit (arm_insn_r
->arm_insn
, 22))
10556 /* STRB and STRBT: 1 byte. */
10557 record_buf_mem
[0] = 1;
10561 /* STR and STRT: 4 bytes. */
10562 record_buf_mem
[0] = 4;
10565 /* Handle bit P. */
10566 if (bit (arm_insn_r
->arm_insn
, 24))
10567 record_buf_mem
[1] = tgt_mem_addr
;
10569 record_buf_mem
[1] = (uint32_t) u_regval
;
10571 arm_insn_r
->mem_rec_count
= 1;
10573 /* If wback is true, also save the base register, which is going to be
10576 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10579 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10580 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10584 /* Handling opcode 011 insns. */
10587 arm_record_ld_st_reg_offset (insn_decode_record
*arm_insn_r
)
10589 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10591 uint32_t shift_imm
= 0;
10592 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
10593 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
10594 uint32_t record_buf
[8], record_buf_mem
[8];
10597 ULONGEST u_regval
[2];
10599 if (bit (arm_insn_r
->arm_insn
, 4))
10600 return arm_record_media (arm_insn_r
);
10602 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10603 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10605 /* Handle enhanced store insns and LDRD DSP insn,
10606 order begins according to addressing modes for store insns
10610 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10612 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10613 /* LDR insn has a capability to do branching, if
10614 MOV LR, PC is precedded by LDR insn having Rn as R15
10615 in that case, it emulates branch and link insn, and hence we
10616 need to save CSPR and PC as well. */
10617 if (15 != reg_dest
)
10619 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10620 arm_insn_r
->reg_rec_count
= 1;
10624 record_buf
[0] = reg_dest
;
10625 record_buf
[1] = ARM_PS_REGNUM
;
10626 arm_insn_r
->reg_rec_count
= 2;
10631 if (! bits (arm_insn_r
->arm_insn
, 4, 11))
10633 /* Store insn, register offset and register pre-indexed,
10634 register post-indexed. */
10636 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10638 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10639 regcache_raw_read_unsigned (reg_cache
, reg_src1
10641 regcache_raw_read_unsigned (reg_cache
, reg_src2
10643 if (15 == reg_src2
)
10645 /* If R15 was used as Rn, hence current PC+8. */
10646 /* Pre-indexed mode doesnt reach here ; illegal insn. */
10647 u_regval
[0] = u_regval
[0] + 8;
10649 /* Calculate target store address, Rn +/- Rm, register offset. */
10651 if (bit (arm_insn_r
->arm_insn
, 23))
10653 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10657 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10660 switch (arm_insn_r
->opcode
)
10674 record_buf_mem
[0] = 4;
10689 record_buf_mem
[0] = 1;
10693 gdb_assert_not_reached ("no decoding pattern found");
10696 record_buf_mem
[1] = tgt_mem_addr
;
10697 arm_insn_r
->mem_rec_count
= 1;
10699 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10700 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10701 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10702 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10703 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10704 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10707 /* Rn is going to be changed in pre-indexed mode and
10708 post-indexed mode as well. */
10709 record_buf
[0] = reg_src2
;
10710 arm_insn_r
->reg_rec_count
= 1;
10715 /* Store insn, scaled register offset; scaled pre-indexed. */
10716 offset_12
= bits (arm_insn_r
->arm_insn
, 5, 6);
10718 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10720 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10721 /* Get shift_imm. */
10722 shift_imm
= bits (arm_insn_r
->arm_insn
, 7, 11);
10723 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10724 regcache_raw_read_signed (reg_cache
, reg_src1
, &s_word
);
10725 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10726 /* Offset_12 used as shift. */
10730 /* Offset_12 used as index. */
10731 offset_12
= u_regval
[0] << shift_imm
;
10735 offset_12
= (!shift_imm
)?0:u_regval
[0] >> shift_imm
;
10741 if (bit (u_regval
[0], 31))
10743 offset_12
= 0xFFFFFFFF;
10752 /* This is arithmetic shift. */
10753 offset_12
= s_word
>> shift_imm
;
10760 regcache_raw_read_unsigned (reg_cache
, ARM_PS_REGNUM
,
10762 /* Get C flag value and shift it by 31. */
10763 offset_12
= (((bit (u_regval
[1], 29)) << 31) \
10764 | (u_regval
[0]) >> 1);
10768 offset_12
= (u_regval
[0] >> shift_imm
) \
10770 (sizeof(uint32_t) - shift_imm
));
10775 gdb_assert_not_reached ("no decoding pattern found");
10779 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10781 if (bit (arm_insn_r
->arm_insn
, 23))
10783 tgt_mem_addr
= u_regval
[1] + offset_12
;
10787 tgt_mem_addr
= u_regval
[1] - offset_12
;
10790 switch (arm_insn_r
->opcode
)
10804 record_buf_mem
[0] = 4;
10819 record_buf_mem
[0] = 1;
10823 gdb_assert_not_reached ("no decoding pattern found");
10826 record_buf_mem
[1] = tgt_mem_addr
;
10827 arm_insn_r
->mem_rec_count
= 1;
10829 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10830 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10831 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10832 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10833 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10834 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10837 /* Rn is going to be changed in register scaled pre-indexed
10838 mode,and scaled post indexed mode. */
10839 record_buf
[0] = reg_src2
;
10840 arm_insn_r
->reg_rec_count
= 1;
10845 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10846 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10850 /* Handle ARM mode instructions with opcode 100. */
10853 arm_record_ld_st_multiple (insn_decode_record
*arm_insn_r
)
10855 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10856 uint32_t register_count
= 0, register_bits
;
10857 uint32_t reg_base
, addr_mode
;
10858 uint32_t record_buf
[24], record_buf_mem
[48];
10862 /* Fetch the list of registers. */
10863 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
10864 arm_insn_r
->reg_rec_count
= 0;
10866 /* Fetch the base register that contains the address we are loading data
10868 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
10870 /* Calculate wback. */
10871 wback
= (bit (arm_insn_r
->arm_insn
, 21) == 1);
10873 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10875 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
10877 /* Find out which registers are going to be loaded from memory. */
10878 while (register_bits
)
10880 if (register_bits
& 0x00000001)
10881 record_buf
[arm_insn_r
->reg_rec_count
++] = register_count
;
10882 register_bits
= register_bits
>> 1;
10887 /* If wback is true, also save the base register, which is going to be
10890 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10892 /* Save the CPSR register. */
10893 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10897 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
10899 addr_mode
= bits (arm_insn_r
->arm_insn
, 23, 24);
10901 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
10903 /* Find out how many registers are going to be stored to memory. */
10904 while (register_bits
)
10906 if (register_bits
& 0x00000001)
10908 register_bits
= register_bits
>> 1;
10913 /* STMDA (STMED): Decrement after. */
10915 record_buf_mem
[1] = (uint32_t) u_regval
10916 - register_count
* INT_REGISTER_SIZE
+ 4;
10918 /* STM (STMIA, STMEA): Increment after. */
10920 record_buf_mem
[1] = (uint32_t) u_regval
;
10922 /* STMDB (STMFD): Decrement before. */
10924 record_buf_mem
[1] = (uint32_t) u_regval
10925 - register_count
* INT_REGISTER_SIZE
;
10927 /* STMIB (STMFA): Increment before. */
10929 record_buf_mem
[1] = (uint32_t) u_regval
+ INT_REGISTER_SIZE
;
10932 gdb_assert_not_reached ("no decoding pattern found");
10936 record_buf_mem
[0] = register_count
* INT_REGISTER_SIZE
;
10937 arm_insn_r
->mem_rec_count
= 1;
10939 /* If wback is true, also save the base register, which is going to be
10942 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10945 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10946 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10950 /* Handling opcode 101 insns. */
10953 arm_record_b_bl (insn_decode_record
*arm_insn_r
)
10955 uint32_t record_buf
[8];
10957 /* Handle B, BL, BLX(1) insns. */
10958 /* B simply branches so we do nothing here. */
10959 /* Note: BLX(1) doesnt fall here but instead it falls into
10960 extension space. */
10961 if (bit (arm_insn_r
->arm_insn
, 24))
10963 record_buf
[0] = ARM_LR_REGNUM
;
10964 arm_insn_r
->reg_rec_count
= 1;
10967 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10973 arm_record_unsupported_insn (insn_decode_record
*arm_insn_r
)
10975 printf_unfiltered (_("Process record does not support instruction "
10976 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
10977 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
10982 /* Record handler for vector data transfer instructions. */
10985 arm_record_vdata_transfer_insn (insn_decode_record
*arm_insn_r
)
10987 uint32_t bits_a
, bit_c
, bit_l
, reg_t
, reg_v
;
10988 uint32_t record_buf
[4];
10990 const int num_regs
= gdbarch_num_regs (arm_insn_r
->gdbarch
);
10991 reg_t
= bits (arm_insn_r
->arm_insn
, 12, 15);
10992 reg_v
= bits (arm_insn_r
->arm_insn
, 21, 23);
10993 bits_a
= bits (arm_insn_r
->arm_insn
, 21, 23);
10994 bit_l
= bit (arm_insn_r
->arm_insn
, 20);
10995 bit_c
= bit (arm_insn_r
->arm_insn
, 8);
10997 /* Handle VMOV instruction. */
10998 if (bit_l
&& bit_c
)
11000 record_buf
[0] = reg_t
;
11001 arm_insn_r
->reg_rec_count
= 1;
11003 else if (bit_l
&& !bit_c
)
11005 /* Handle VMOV instruction. */
11006 if (bits_a
== 0x00)
11008 record_buf
[0] = reg_t
;
11009 arm_insn_r
->reg_rec_count
= 1;
11011 /* Handle VMRS instruction. */
11012 else if (bits_a
== 0x07)
11015 reg_t
= ARM_PS_REGNUM
;
11017 record_buf
[0] = reg_t
;
11018 arm_insn_r
->reg_rec_count
= 1;
11021 else if (!bit_l
&& !bit_c
)
11023 /* Handle VMOV instruction. */
11024 if (bits_a
== 0x00)
11026 record_buf
[0] = ARM_D0_REGNUM
+ reg_v
;
11028 arm_insn_r
->reg_rec_count
= 1;
11030 /* Handle VMSR instruction. */
11031 else if (bits_a
== 0x07)
11033 record_buf
[0] = ARM_FPSCR_REGNUM
;
11034 arm_insn_r
->reg_rec_count
= 1;
11037 else if (!bit_l
&& bit_c
)
11039 /* Handle VMOV instruction. */
11040 if (!(bits_a
& 0x04))
11042 record_buf
[0] = (reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4))
11044 arm_insn_r
->reg_rec_count
= 1;
11046 /* Handle VDUP instruction. */
11049 if (bit (arm_insn_r
->arm_insn
, 21))
11051 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11052 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11053 record_buf
[1] = reg_v
+ ARM_D0_REGNUM
+ 1;
11054 arm_insn_r
->reg_rec_count
= 2;
11058 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11059 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11060 arm_insn_r
->reg_rec_count
= 1;
11065 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11069 /* Record handler for extension register load/store instructions. */
11072 arm_record_exreg_ld_st_insn (insn_decode_record
*arm_insn_r
)
11074 uint32_t opcode
, single_reg
;
11075 uint8_t op_vldm_vstm
;
11076 uint32_t record_buf
[8], record_buf_mem
[128];
11077 ULONGEST u_regval
= 0;
11079 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11080 const int num_regs
= gdbarch_num_regs (arm_insn_r
->gdbarch
);
11082 opcode
= bits (arm_insn_r
->arm_insn
, 20, 24);
11083 single_reg
= !bit (arm_insn_r
->arm_insn
, 8);
11084 op_vldm_vstm
= opcode
& 0x1b;
11086 /* Handle VMOV instructions. */
11087 if ((opcode
& 0x1e) == 0x04)
11089 if (bit (arm_insn_r
->arm_insn
, 20)) /* to_arm_registers bit 20? */
11091 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11092 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11093 arm_insn_r
->reg_rec_count
= 2;
11097 uint8_t reg_m
= bits (arm_insn_r
->arm_insn
, 0, 3);
11098 uint8_t bit_m
= bit (arm_insn_r
->arm_insn
, 5);
11102 /* The first S register number m is REG_M:M (M is bit 5),
11103 the corresponding D register number is REG_M:M / 2, which
11105 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_D0_REGNUM
+ reg_m
;
11106 /* The second S register number is REG_M:M + 1, the
11107 corresponding D register number is (REG_M:M + 1) / 2.
11108 IOW, if bit M is 1, the first and second S registers
11109 are mapped to different D registers, otherwise, they are
11110 in the same D register. */
11113 record_buf
[arm_insn_r
->reg_rec_count
++]
11114 = ARM_D0_REGNUM
+ reg_m
+ 1;
11119 record_buf
[0] = ((bit_m
<< 4) + reg_m
+ ARM_D0_REGNUM
);
11120 arm_insn_r
->reg_rec_count
= 1;
11124 /* Handle VSTM and VPUSH instructions. */
11125 else if (op_vldm_vstm
== 0x08 || op_vldm_vstm
== 0x0a
11126 || op_vldm_vstm
== 0x12)
11128 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
11129 uint32_t memory_index
= 0;
11131 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11132 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11133 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11134 imm_off32
= imm_off8
<< 2;
11135 memory_count
= imm_off8
;
11137 if (bit (arm_insn_r
->arm_insn
, 23))
11138 start_address
= u_regval
;
11140 start_address
= u_regval
- imm_off32
;
11142 if (bit (arm_insn_r
->arm_insn
, 21))
11144 record_buf
[0] = reg_rn
;
11145 arm_insn_r
->reg_rec_count
= 1;
11148 while (memory_count
> 0)
11152 record_buf_mem
[memory_index
] = 4;
11153 record_buf_mem
[memory_index
+ 1] = start_address
;
11154 start_address
= start_address
+ 4;
11155 memory_index
= memory_index
+ 2;
11159 record_buf_mem
[memory_index
] = 4;
11160 record_buf_mem
[memory_index
+ 1] = start_address
;
11161 record_buf_mem
[memory_index
+ 2] = 4;
11162 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11163 start_address
= start_address
+ 8;
11164 memory_index
= memory_index
+ 4;
11168 arm_insn_r
->mem_rec_count
= (memory_index
>> 1);
11170 /* Handle VLDM instructions. */
11171 else if (op_vldm_vstm
== 0x09 || op_vldm_vstm
== 0x0b
11172 || op_vldm_vstm
== 0x13)
11174 uint32_t reg_count
, reg_vd
;
11175 uint32_t reg_index
= 0;
11176 uint32_t bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11178 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11179 reg_count
= bits (arm_insn_r
->arm_insn
, 0, 7);
11181 /* REG_VD is the first D register number. If the instruction
11182 loads memory to S registers (SINGLE_REG is TRUE), the register
11183 number is (REG_VD << 1 | bit D), so the corresponding D
11184 register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */
11186 reg_vd
= reg_vd
| (bit_d
<< 4);
11188 if (bit (arm_insn_r
->arm_insn
, 21) /* write back */)
11189 record_buf
[reg_index
++] = bits (arm_insn_r
->arm_insn
, 16, 19);
11191 /* If the instruction loads memory to D register, REG_COUNT should
11192 be divided by 2, according to the ARM Architecture Reference
11193 Manual. If the instruction loads memory to S register, divide by
11194 2 as well because two S registers are mapped to D register. */
11195 reg_count
= reg_count
/ 2;
11196 if (single_reg
&& bit_d
)
11198 /* Increase the register count if S register list starts from
11199 an odd number (bit d is one). */
11203 while (reg_count
> 0)
11205 record_buf
[reg_index
++] = ARM_D0_REGNUM
+ reg_vd
+ reg_count
- 1;
11208 arm_insn_r
->reg_rec_count
= reg_index
;
11210 /* VSTR Vector store register. */
11211 else if ((opcode
& 0x13) == 0x10)
11213 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
;
11214 uint32_t memory_index
= 0;
11216 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11217 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11218 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11219 imm_off32
= imm_off8
<< 2;
11221 if (bit (arm_insn_r
->arm_insn
, 23))
11222 start_address
= u_regval
+ imm_off32
;
11224 start_address
= u_regval
- imm_off32
;
11228 record_buf_mem
[memory_index
] = 4;
11229 record_buf_mem
[memory_index
+ 1] = start_address
;
11230 arm_insn_r
->mem_rec_count
= 1;
11234 record_buf_mem
[memory_index
] = 4;
11235 record_buf_mem
[memory_index
+ 1] = start_address
;
11236 record_buf_mem
[memory_index
+ 2] = 4;
11237 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11238 arm_insn_r
->mem_rec_count
= 2;
11241 /* VLDR Vector load register. */
11242 else if ((opcode
& 0x13) == 0x11)
11244 uint32_t reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11248 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
11249 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
;
11253 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
11254 /* Record register D rather than pseudo register S. */
11255 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
/ 2;
11257 arm_insn_r
->reg_rec_count
= 1;
11260 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11261 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11265 /* Record handler for arm/thumb mode VFP data processing instructions. */
11268 arm_record_vfp_data_proc_insn (insn_decode_record
*arm_insn_r
)
11270 uint32_t opc1
, opc2
, opc3
, dp_op_sz
, bit_d
, reg_vd
;
11271 uint32_t record_buf
[4];
11272 enum insn_types
{INSN_T0
, INSN_T1
, INSN_T2
, INSN_T3
, INSN_INV
};
11273 enum insn_types curr_insn_type
= INSN_INV
;
11275 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11276 opc1
= bits (arm_insn_r
->arm_insn
, 20, 23);
11277 opc2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11278 opc3
= bits (arm_insn_r
->arm_insn
, 6, 7);
11279 dp_op_sz
= bit (arm_insn_r
->arm_insn
, 8);
11280 bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11281 opc1
= opc1
& 0x04;
11283 /* Handle VMLA, VMLS. */
11286 if (bit (arm_insn_r
->arm_insn
, 10))
11288 if (bit (arm_insn_r
->arm_insn
, 6))
11289 curr_insn_type
= INSN_T0
;
11291 curr_insn_type
= INSN_T1
;
11296 curr_insn_type
= INSN_T1
;
11298 curr_insn_type
= INSN_T2
;
11301 /* Handle VNMLA, VNMLS, VNMUL. */
11302 else if (opc1
== 0x01)
11305 curr_insn_type
= INSN_T1
;
11307 curr_insn_type
= INSN_T2
;
11310 else if (opc1
== 0x02 && !(opc3
& 0x01))
11312 if (bit (arm_insn_r
->arm_insn
, 10))
11314 if (bit (arm_insn_r
->arm_insn
, 6))
11315 curr_insn_type
= INSN_T0
;
11317 curr_insn_type
= INSN_T1
;
11322 curr_insn_type
= INSN_T1
;
11324 curr_insn_type
= INSN_T2
;
11327 /* Handle VADD, VSUB. */
11328 else if (opc1
== 0x03)
11330 if (!bit (arm_insn_r
->arm_insn
, 9))
11332 if (bit (arm_insn_r
->arm_insn
, 6))
11333 curr_insn_type
= INSN_T0
;
11335 curr_insn_type
= INSN_T1
;
11340 curr_insn_type
= INSN_T1
;
11342 curr_insn_type
= INSN_T2
;
11346 else if (opc1
== 0x0b)
11349 curr_insn_type
= INSN_T1
;
11351 curr_insn_type
= INSN_T2
;
11353 /* Handle all other vfp data processing instructions. */
11354 else if (opc1
== 0x0b)
11357 if (!(opc3
& 0x01) || (opc2
== 0x00 && opc3
== 0x01))
11359 if (bit (arm_insn_r
->arm_insn
, 4))
11361 if (bit (arm_insn_r
->arm_insn
, 6))
11362 curr_insn_type
= INSN_T0
;
11364 curr_insn_type
= INSN_T1
;
11369 curr_insn_type
= INSN_T1
;
11371 curr_insn_type
= INSN_T2
;
11374 /* Handle VNEG and VABS. */
11375 else if ((opc2
== 0x01 && opc3
== 0x01)
11376 || (opc2
== 0x00 && opc3
== 0x03))
11378 if (!bit (arm_insn_r
->arm_insn
, 11))
11380 if (bit (arm_insn_r
->arm_insn
, 6))
11381 curr_insn_type
= INSN_T0
;
11383 curr_insn_type
= INSN_T1
;
11388 curr_insn_type
= INSN_T1
;
11390 curr_insn_type
= INSN_T2
;
11393 /* Handle VSQRT. */
11394 else if (opc2
== 0x01 && opc3
== 0x03)
11397 curr_insn_type
= INSN_T1
;
11399 curr_insn_type
= INSN_T2
;
11402 else if (opc2
== 0x07 && opc3
== 0x03)
11405 curr_insn_type
= INSN_T1
;
11407 curr_insn_type
= INSN_T2
;
11409 else if (opc3
& 0x01)
11412 if ((opc2
== 0x08) || (opc2
& 0x0e) == 0x0c)
11414 if (!bit (arm_insn_r
->arm_insn
, 18))
11415 curr_insn_type
= INSN_T2
;
11419 curr_insn_type
= INSN_T1
;
11421 curr_insn_type
= INSN_T2
;
11425 else if ((opc2
& 0x0e) == 0x0a || (opc2
& 0x0e) == 0x0e)
11428 curr_insn_type
= INSN_T1
;
11430 curr_insn_type
= INSN_T2
;
11432 /* Handle VCVTB, VCVTT. */
11433 else if ((opc2
& 0x0e) == 0x02)
11434 curr_insn_type
= INSN_T2
;
11435 /* Handle VCMP, VCMPE. */
11436 else if ((opc2
& 0x0e) == 0x04)
11437 curr_insn_type
= INSN_T3
;
11441 switch (curr_insn_type
)
11444 reg_vd
= reg_vd
| (bit_d
<< 4);
11445 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11446 record_buf
[1] = reg_vd
+ ARM_D0_REGNUM
+ 1;
11447 arm_insn_r
->reg_rec_count
= 2;
11451 reg_vd
= reg_vd
| (bit_d
<< 4);
11452 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11453 arm_insn_r
->reg_rec_count
= 1;
11457 reg_vd
= (reg_vd
<< 1) | bit_d
;
11458 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11459 arm_insn_r
->reg_rec_count
= 1;
11463 record_buf
[0] = ARM_FPSCR_REGNUM
;
11464 arm_insn_r
->reg_rec_count
= 1;
11468 gdb_assert_not_reached ("no decoding pattern found");
11472 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11476 /* Handling opcode 110 insns. */
11479 arm_record_asimd_vfp_coproc (insn_decode_record
*arm_insn_r
)
11481 uint32_t op1
, op1_ebit
, coproc
;
11483 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11484 op1
= bits (arm_insn_r
->arm_insn
, 20, 25);
11485 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11487 if ((coproc
& 0x0e) == 0x0a)
11489 /* Handle extension register ld/st instructions. */
11491 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11493 /* 64-bit transfers between arm core and extension registers. */
11494 if ((op1
& 0x3e) == 0x04)
11495 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11499 /* Handle coprocessor ld/st instructions. */
11504 return arm_record_unsupported_insn (arm_insn_r
);
11507 return arm_record_unsupported_insn (arm_insn_r
);
11510 /* Move to coprocessor from two arm core registers. */
11512 return arm_record_unsupported_insn (arm_insn_r
);
11514 /* Move to two arm core registers from coprocessor. */
11519 reg_t
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11520 reg_t
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11521 arm_insn_r
->reg_rec_count
= 2;
11523 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, reg_t
);
11527 return arm_record_unsupported_insn (arm_insn_r
);
11530 /* Handling opcode 111 insns. */
11533 arm_record_coproc_data_proc (insn_decode_record
*arm_insn_r
)
11535 uint32_t op
, op1_sbit
, op1_ebit
, coproc
;
11536 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arm_insn_r
->gdbarch
);
11537 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11539 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 24, 27);
11540 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11541 op1_sbit
= bit (arm_insn_r
->arm_insn
, 24);
11542 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11543 op
= bit (arm_insn_r
->arm_insn
, 4);
11545 /* Handle arm SWI/SVC system call instructions. */
11548 if (tdep
->arm_syscall_record
!= NULL
)
11550 ULONGEST svc_operand
, svc_number
;
11552 svc_operand
= (0x00ffffff & arm_insn_r
->arm_insn
);
11554 if (svc_operand
) /* OABI. */
11555 svc_number
= svc_operand
- 0x900000;
11557 regcache_raw_read_unsigned (reg_cache
, 7, &svc_number
);
11559 return tdep
->arm_syscall_record (reg_cache
, svc_number
);
11563 printf_unfiltered (_("no syscall record support\n"));
11568 if ((coproc
& 0x0e) == 0x0a)
11570 /* VFP data-processing instructions. */
11571 if (!op1_sbit
&& !op
)
11572 return arm_record_vfp_data_proc_insn (arm_insn_r
);
11574 /* Advanced SIMD, VFP instructions. */
11575 if (!op1_sbit
&& op
)
11576 return arm_record_vdata_transfer_insn (arm_insn_r
);
11580 /* Coprocessor data operations. */
11581 if (!op1_sbit
&& !op
)
11582 return arm_record_unsupported_insn (arm_insn_r
);
11584 /* Move to Coprocessor from ARM core register. */
11585 if (!op1_sbit
&& !op1_ebit
&& op
)
11586 return arm_record_unsupported_insn (arm_insn_r
);
11588 /* Move to arm core register from coprocessor. */
11589 if (!op1_sbit
&& op1_ebit
&& op
)
11591 uint32_t record_buf
[1];
11593 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11594 if (record_buf
[0] == 15)
11595 record_buf
[0] = ARM_PS_REGNUM
;
11597 arm_insn_r
->reg_rec_count
= 1;
11598 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
,
11604 return arm_record_unsupported_insn (arm_insn_r
);
11607 /* Handling opcode 000 insns. */
11610 thumb_record_shift_add_sub (insn_decode_record
*thumb_insn_r
)
11612 uint32_t record_buf
[8];
11613 uint32_t reg_src1
= 0;
11615 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11617 record_buf
[0] = ARM_PS_REGNUM
;
11618 record_buf
[1] = reg_src1
;
11619 thumb_insn_r
->reg_rec_count
= 2;
11621 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11627 /* Handling opcode 001 insns. */
11630 thumb_record_add_sub_cmp_mov (insn_decode_record
*thumb_insn_r
)
11632 uint32_t record_buf
[8];
11633 uint32_t reg_src1
= 0;
11635 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11637 record_buf
[0] = ARM_PS_REGNUM
;
11638 record_buf
[1] = reg_src1
;
11639 thumb_insn_r
->reg_rec_count
= 2;
11641 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11646 /* Handling opcode 010 insns. */
11649 thumb_record_ld_st_reg_offset (insn_decode_record
*thumb_insn_r
)
11651 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11652 uint32_t record_buf
[8], record_buf_mem
[8];
11654 uint32_t reg_src1
= 0, reg_src2
= 0;
11655 uint32_t opcode1
= 0, opcode2
= 0, opcode3
= 0;
11657 ULONGEST u_regval
[2] = {0};
11659 opcode1
= bits (thumb_insn_r
->arm_insn
, 10, 12);
11661 if (bit (thumb_insn_r
->arm_insn
, 12))
11663 /* Handle load/store register offset. */
11664 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 10);
11665 if (opcode2
>= 12 && opcode2
<= 15)
11667 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
11668 reg_src1
= bits (thumb_insn_r
->arm_insn
,0, 2);
11669 record_buf
[0] = reg_src1
;
11670 thumb_insn_r
->reg_rec_count
= 1;
11672 else if (opcode2
>= 8 && opcode2
<= 10)
11674 /* STR(2), STRB(2), STRH(2) . */
11675 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11676 reg_src2
= bits (thumb_insn_r
->arm_insn
, 6, 8);
11677 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11678 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11680 record_buf_mem
[0] = 4; /* STR (2). */
11681 else if (10 == opcode2
)
11682 record_buf_mem
[0] = 1; /* STRB (2). */
11683 else if (9 == opcode2
)
11684 record_buf_mem
[0] = 2; /* STRH (2). */
11685 record_buf_mem
[1] = u_regval
[0] + u_regval
[1];
11686 thumb_insn_r
->mem_rec_count
= 1;
11689 else if (bit (thumb_insn_r
->arm_insn
, 11))
11691 /* Handle load from literal pool. */
11693 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11694 record_buf
[0] = reg_src1
;
11695 thumb_insn_r
->reg_rec_count
= 1;
11699 opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 9);
11700 opcode3
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11701 if ((3 == opcode2
) && (!opcode3
))
11703 /* Branch with exchange. */
11704 record_buf
[0] = ARM_PS_REGNUM
;
11705 thumb_insn_r
->reg_rec_count
= 1;
11709 /* Format 8; special data processing insns. */
11710 record_buf
[0] = ARM_PS_REGNUM
;
11711 record_buf
[1] = (bit (thumb_insn_r
->arm_insn
, 7) << 3
11712 | bits (thumb_insn_r
->arm_insn
, 0, 2));
11713 thumb_insn_r
->reg_rec_count
= 2;
11718 /* Format 5; data processing insns. */
11719 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11720 if (bit (thumb_insn_r
->arm_insn
, 7))
11722 reg_src1
= reg_src1
+ 8;
11724 record_buf
[0] = ARM_PS_REGNUM
;
11725 record_buf
[1] = reg_src1
;
11726 thumb_insn_r
->reg_rec_count
= 2;
11729 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11730 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11736 /* Handling opcode 001 insns. */
11739 thumb_record_ld_st_imm_offset (insn_decode_record
*thumb_insn_r
)
11741 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11742 uint32_t record_buf
[8], record_buf_mem
[8];
11744 uint32_t reg_src1
= 0;
11745 uint32_t opcode
= 0, immed_5
= 0;
11747 ULONGEST u_regval
= 0;
11749 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11754 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11755 record_buf
[0] = reg_src1
;
11756 thumb_insn_r
->reg_rec_count
= 1;
11761 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11762 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11763 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11764 record_buf_mem
[0] = 4;
11765 record_buf_mem
[1] = u_regval
+ (immed_5
* 4);
11766 thumb_insn_r
->mem_rec_count
= 1;
11769 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11770 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11776 /* Handling opcode 100 insns. */
11779 thumb_record_ld_st_stack (insn_decode_record
*thumb_insn_r
)
11781 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11782 uint32_t record_buf
[8], record_buf_mem
[8];
11784 uint32_t reg_src1
= 0;
11785 uint32_t opcode
= 0, immed_8
= 0, immed_5
= 0;
11787 ULONGEST u_regval
= 0;
11789 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11794 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11795 record_buf
[0] = reg_src1
;
11796 thumb_insn_r
->reg_rec_count
= 1;
11798 else if (1 == opcode
)
11801 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11802 record_buf
[0] = reg_src1
;
11803 thumb_insn_r
->reg_rec_count
= 1;
11805 else if (2 == opcode
)
11808 immed_8
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11809 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
11810 record_buf_mem
[0] = 4;
11811 record_buf_mem
[1] = u_regval
+ (immed_8
* 4);
11812 thumb_insn_r
->mem_rec_count
= 1;
11814 else if (0 == opcode
)
11817 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11818 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11819 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11820 record_buf_mem
[0] = 2;
11821 record_buf_mem
[1] = u_regval
+ (immed_5
* 2);
11822 thumb_insn_r
->mem_rec_count
= 1;
11825 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11826 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11832 /* Handling opcode 101 insns. */
11835 thumb_record_misc (insn_decode_record
*thumb_insn_r
)
11837 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11839 uint32_t opcode
= 0, opcode1
= 0, opcode2
= 0;
11840 uint32_t register_bits
= 0, register_count
= 0;
11841 uint32_t index
= 0, start_address
= 0;
11842 uint32_t record_buf
[24], record_buf_mem
[48];
11845 ULONGEST u_regval
= 0;
11847 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11848 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
11849 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 12);
11854 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11855 while (register_bits
)
11857 if (register_bits
& 0x00000001)
11858 record_buf
[index
++] = register_count
;
11859 register_bits
= register_bits
>> 1;
11862 record_buf
[index
++] = ARM_PS_REGNUM
;
11863 record_buf
[index
++] = ARM_SP_REGNUM
;
11864 thumb_insn_r
->reg_rec_count
= index
;
11866 else if (10 == opcode2
)
11869 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11870 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
11871 while (register_bits
)
11873 if (register_bits
& 0x00000001)
11875 register_bits
= register_bits
>> 1;
11877 start_address
= u_regval
- \
11878 (4 * (bit (thumb_insn_r
->arm_insn
, 8) + register_count
));
11879 thumb_insn_r
->mem_rec_count
= register_count
;
11880 while (register_count
)
11882 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11883 record_buf_mem
[(register_count
* 2) - 2] = 4;
11884 start_address
= start_address
+ 4;
11887 record_buf
[0] = ARM_SP_REGNUM
;
11888 thumb_insn_r
->reg_rec_count
= 1;
11890 else if (0x1E == opcode1
)
11893 /* Handle enhanced software breakpoint insn, BKPT. */
11894 /* CPSR is changed to be executed in ARM state, disabling normal
11895 interrupts, entering abort mode. */
11896 /* According to high vector configuration PC is set. */
11897 /* User hits breakpoint and type reverse, in that case, we need to go back with
11898 previous CPSR and Program Counter. */
11899 record_buf
[0] = ARM_PS_REGNUM
;
11900 record_buf
[1] = ARM_LR_REGNUM
;
11901 thumb_insn_r
->reg_rec_count
= 2;
11902 /* We need to save SPSR value, which is not yet done. */
11903 printf_unfiltered (_("Process record does not support instruction "
11904 "0x%0x at address %s.\n"),
11905 thumb_insn_r
->arm_insn
,
11906 paddress (thumb_insn_r
->gdbarch
,
11907 thumb_insn_r
->this_addr
));
11910 else if ((0 == opcode
) || (1 == opcode
))
11912 /* ADD(5), ADD(6). */
11913 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11914 record_buf
[0] = reg_src1
;
11915 thumb_insn_r
->reg_rec_count
= 1;
11917 else if (2 == opcode
)
11919 /* ADD(7), SUB(4). */
11920 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11921 record_buf
[0] = ARM_SP_REGNUM
;
11922 thumb_insn_r
->reg_rec_count
= 1;
11925 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11926 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11932 /* Handling opcode 110 insns. */
11935 thumb_record_ldm_stm_swi (insn_decode_record
*thumb_insn_r
)
11937 struct gdbarch_tdep
*tdep
= gdbarch_tdep (thumb_insn_r
->gdbarch
);
11938 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11940 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
11941 uint32_t reg_src1
= 0;
11942 uint32_t opcode1
= 0, opcode2
= 0, register_bits
= 0, register_count
= 0;
11943 uint32_t index
= 0, start_address
= 0;
11944 uint32_t record_buf
[24], record_buf_mem
[48];
11946 ULONGEST u_regval
= 0;
11948 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
11949 opcode2
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11955 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11957 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11958 while (register_bits
)
11960 if (register_bits
& 0x00000001)
11961 record_buf
[index
++] = register_count
;
11962 register_bits
= register_bits
>> 1;
11965 record_buf
[index
++] = reg_src1
;
11966 thumb_insn_r
->reg_rec_count
= index
;
11968 else if (0 == opcode2
)
11970 /* It handles both STMIA. */
11971 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11973 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11974 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11975 while (register_bits
)
11977 if (register_bits
& 0x00000001)
11979 register_bits
= register_bits
>> 1;
11981 start_address
= u_regval
;
11982 thumb_insn_r
->mem_rec_count
= register_count
;
11983 while (register_count
)
11985 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11986 record_buf_mem
[(register_count
* 2) - 2] = 4;
11987 start_address
= start_address
+ 4;
11991 else if (0x1F == opcode1
)
11993 /* Handle arm syscall insn. */
11994 if (tdep
->arm_syscall_record
!= NULL
)
11996 regcache_raw_read_unsigned (reg_cache
, 7, &u_regval
);
11997 ret
= tdep
->arm_syscall_record (reg_cache
, u_regval
);
12001 printf_unfiltered (_("no syscall record support\n"));
12006 /* B (1), conditional branch is automatically taken care in process_record,
12007 as PC is saved there. */
12009 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12010 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12016 /* Handling opcode 111 insns. */
12019 thumb_record_branch (insn_decode_record
*thumb_insn_r
)
12021 uint32_t record_buf
[8];
12022 uint32_t bits_h
= 0;
12024 bits_h
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12026 if (2 == bits_h
|| 3 == bits_h
)
12029 record_buf
[0] = ARM_LR_REGNUM
;
12030 thumb_insn_r
->reg_rec_count
= 1;
12032 else if (1 == bits_h
)
12035 record_buf
[0] = ARM_PS_REGNUM
;
12036 record_buf
[1] = ARM_LR_REGNUM
;
12037 thumb_insn_r
->reg_rec_count
= 2;
12040 /* B(2) is automatically taken care in process_record, as PC is
12043 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12048 /* Handler for thumb2 load/store multiple instructions. */
12051 thumb2_record_ld_st_multiple (insn_decode_record
*thumb2_insn_r
)
12053 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12055 uint32_t reg_rn
, op
;
12056 uint32_t register_bits
= 0, register_count
= 0;
12057 uint32_t index
= 0, start_address
= 0;
12058 uint32_t record_buf
[24], record_buf_mem
[48];
12060 ULONGEST u_regval
= 0;
12062 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12063 op
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12065 if (0 == op
|| 3 == op
)
12067 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12069 /* Handle RFE instruction. */
12070 record_buf
[0] = ARM_PS_REGNUM
;
12071 thumb2_insn_r
->reg_rec_count
= 1;
12075 /* Handle SRS instruction after reading banked SP. */
12076 return arm_record_unsupported_insn (thumb2_insn_r
);
12079 else if (1 == op
|| 2 == op
)
12081 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12083 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
12084 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12085 while (register_bits
)
12087 if (register_bits
& 0x00000001)
12088 record_buf
[index
++] = register_count
;
12091 register_bits
= register_bits
>> 1;
12093 record_buf
[index
++] = reg_rn
;
12094 record_buf
[index
++] = ARM_PS_REGNUM
;
12095 thumb2_insn_r
->reg_rec_count
= index
;
12099 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
12100 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12101 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12102 while (register_bits
)
12104 if (register_bits
& 0x00000001)
12107 register_bits
= register_bits
>> 1;
12112 /* Start address calculation for LDMDB/LDMEA. */
12113 start_address
= u_regval
;
12117 /* Start address calculation for LDMDB/LDMEA. */
12118 start_address
= u_regval
- register_count
* 4;
12121 thumb2_insn_r
->mem_rec_count
= register_count
;
12122 while (register_count
)
12124 record_buf_mem
[register_count
* 2 - 1] = start_address
;
12125 record_buf_mem
[register_count
* 2 - 2] = 4;
12126 start_address
= start_address
+ 4;
12129 record_buf
[0] = reg_rn
;
12130 record_buf
[1] = ARM_PS_REGNUM
;
12131 thumb2_insn_r
->reg_rec_count
= 2;
12135 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12137 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12139 return ARM_RECORD_SUCCESS
;
12142 /* Handler for thumb2 load/store (dual/exclusive) and table branch
12146 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record
*thumb2_insn_r
)
12148 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12150 uint32_t reg_rd
, reg_rn
, offset_imm
;
12151 uint32_t reg_dest1
, reg_dest2
;
12152 uint32_t address
, offset_addr
;
12153 uint32_t record_buf
[8], record_buf_mem
[8];
12154 uint32_t op1
, op2
, op3
;
12156 ULONGEST u_regval
[2];
12158 op1
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12159 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 21);
12160 op3
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12162 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12164 if(!(1 == op1
&& 1 == op2
&& (0 == op3
|| 1 == op3
)))
12166 reg_dest1
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12167 record_buf
[0] = reg_dest1
;
12168 record_buf
[1] = ARM_PS_REGNUM
;
12169 thumb2_insn_r
->reg_rec_count
= 2;
12172 if (3 == op2
|| (op1
& 2) || (1 == op1
&& 1 == op2
&& 7 == op3
))
12174 reg_dest2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12175 record_buf
[2] = reg_dest2
;
12176 thumb2_insn_r
->reg_rec_count
= 3;
12181 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12182 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12184 if (0 == op1
&& 0 == op2
)
12186 /* Handle STREX. */
12187 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12188 address
= u_regval
[0] + (offset_imm
* 4);
12189 record_buf_mem
[0] = 4;
12190 record_buf_mem
[1] = address
;
12191 thumb2_insn_r
->mem_rec_count
= 1;
12192 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12193 record_buf
[0] = reg_rd
;
12194 thumb2_insn_r
->reg_rec_count
= 1;
12196 else if (1 == op1
&& 0 == op2
)
12198 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12199 record_buf
[0] = reg_rd
;
12200 thumb2_insn_r
->reg_rec_count
= 1;
12201 address
= u_regval
[0];
12202 record_buf_mem
[1] = address
;
12206 /* Handle STREXB. */
12207 record_buf_mem
[0] = 1;
12208 thumb2_insn_r
->mem_rec_count
= 1;
12212 /* Handle STREXH. */
12213 record_buf_mem
[0] = 2 ;
12214 thumb2_insn_r
->mem_rec_count
= 1;
12218 /* Handle STREXD. */
12219 address
= u_regval
[0];
12220 record_buf_mem
[0] = 4;
12221 record_buf_mem
[2] = 4;
12222 record_buf_mem
[3] = address
+ 4;
12223 thumb2_insn_r
->mem_rec_count
= 2;
12228 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12230 if (bit (thumb2_insn_r
->arm_insn
, 24))
12232 if (bit (thumb2_insn_r
->arm_insn
, 23))
12233 offset_addr
= u_regval
[0] + (offset_imm
* 4);
12235 offset_addr
= u_regval
[0] - (offset_imm
* 4);
12237 address
= offset_addr
;
12240 address
= u_regval
[0];
12242 record_buf_mem
[0] = 4;
12243 record_buf_mem
[1] = address
;
12244 record_buf_mem
[2] = 4;
12245 record_buf_mem
[3] = address
+ 4;
12246 thumb2_insn_r
->mem_rec_count
= 2;
12247 record_buf
[0] = reg_rn
;
12248 thumb2_insn_r
->reg_rec_count
= 1;
12252 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12254 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12256 return ARM_RECORD_SUCCESS
;
12259 /* Handler for thumb2 data processing (shift register and modified immediate)
12263 thumb2_record_data_proc_sreg_mimm (insn_decode_record
*thumb2_insn_r
)
12265 uint32_t reg_rd
, op
;
12266 uint32_t record_buf
[8];
12268 op
= bits (thumb2_insn_r
->arm_insn
, 21, 24);
12269 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12271 if ((0 == op
|| 4 == op
|| 8 == op
|| 13 == op
) && 15 == reg_rd
)
12273 record_buf
[0] = ARM_PS_REGNUM
;
12274 thumb2_insn_r
->reg_rec_count
= 1;
12278 record_buf
[0] = reg_rd
;
12279 record_buf
[1] = ARM_PS_REGNUM
;
12280 thumb2_insn_r
->reg_rec_count
= 2;
12283 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12285 return ARM_RECORD_SUCCESS
;
12288 /* Generic handler for thumb2 instructions which effect destination and PS
12292 thumb2_record_ps_dest_generic (insn_decode_record
*thumb2_insn_r
)
12295 uint32_t record_buf
[8];
12297 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12299 record_buf
[0] = reg_rd
;
12300 record_buf
[1] = ARM_PS_REGNUM
;
12301 thumb2_insn_r
->reg_rec_count
= 2;
12303 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12305 return ARM_RECORD_SUCCESS
;
12308 /* Handler for thumb2 branch and miscellaneous control instructions. */
12311 thumb2_record_branch_misc_cntrl (insn_decode_record
*thumb2_insn_r
)
12313 uint32_t op
, op1
, op2
;
12314 uint32_t record_buf
[8];
12316 op
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12317 op1
= bits (thumb2_insn_r
->arm_insn
, 12, 14);
12318 op2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12320 /* Handle MSR insn. */
12321 if (!(op1
& 0x2) && 0x38 == op
)
12325 /* CPSR is going to be changed. */
12326 record_buf
[0] = ARM_PS_REGNUM
;
12327 thumb2_insn_r
->reg_rec_count
= 1;
12331 arm_record_unsupported_insn(thumb2_insn_r
);
12335 else if (4 == (op1
& 0x5) || 5 == (op1
& 0x5))
12338 record_buf
[0] = ARM_PS_REGNUM
;
12339 record_buf
[1] = ARM_LR_REGNUM
;
12340 thumb2_insn_r
->reg_rec_count
= 2;
12343 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12345 return ARM_RECORD_SUCCESS
;
12348 /* Handler for thumb2 store single data item instructions. */
12351 thumb2_record_str_single_data (insn_decode_record
*thumb2_insn_r
)
12353 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12355 uint32_t reg_rn
, reg_rm
, offset_imm
, shift_imm
;
12356 uint32_t address
, offset_addr
;
12357 uint32_t record_buf
[8], record_buf_mem
[8];
12360 ULONGEST u_regval
[2];
12362 op1
= bits (thumb2_insn_r
->arm_insn
, 21, 23);
12363 op2
= bits (thumb2_insn_r
->arm_insn
, 6, 11);
12364 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12365 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12367 if (bit (thumb2_insn_r
->arm_insn
, 23))
12370 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 11);
12371 offset_addr
= u_regval
[0] + offset_imm
;
12372 address
= offset_addr
;
12377 if ((0 == op1
|| 1 == op1
|| 2 == op1
) && !(op2
& 0x20))
12379 /* Handle STRB (register). */
12380 reg_rm
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12381 regcache_raw_read_unsigned (reg_cache
, reg_rm
, &u_regval
[1]);
12382 shift_imm
= bits (thumb2_insn_r
->arm_insn
, 4, 5);
12383 offset_addr
= u_regval
[1] << shift_imm
;
12384 address
= u_regval
[0] + offset_addr
;
12388 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12389 if (bit (thumb2_insn_r
->arm_insn
, 10))
12391 if (bit (thumb2_insn_r
->arm_insn
, 9))
12392 offset_addr
= u_regval
[0] + offset_imm
;
12394 offset_addr
= u_regval
[0] - offset_imm
;
12396 address
= offset_addr
;
12399 address
= u_regval
[0];
12405 /* Store byte instructions. */
12408 record_buf_mem
[0] = 1;
12410 /* Store half word instructions. */
12413 record_buf_mem
[0] = 2;
12415 /* Store word instructions. */
12418 record_buf_mem
[0] = 4;
12422 gdb_assert_not_reached ("no decoding pattern found");
12426 record_buf_mem
[1] = address
;
12427 thumb2_insn_r
->mem_rec_count
= 1;
12428 record_buf
[0] = reg_rn
;
12429 thumb2_insn_r
->reg_rec_count
= 1;
12431 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12433 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12435 return ARM_RECORD_SUCCESS
;
12438 /* Handler for thumb2 load memory hints instructions. */
12441 thumb2_record_ld_mem_hints (insn_decode_record
*thumb2_insn_r
)
12443 uint32_t record_buf
[8];
12444 uint32_t reg_rt
, reg_rn
;
12446 reg_rt
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12447 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12449 if (ARM_PC_REGNUM
!= reg_rt
)
12451 record_buf
[0] = reg_rt
;
12452 record_buf
[1] = reg_rn
;
12453 record_buf
[2] = ARM_PS_REGNUM
;
12454 thumb2_insn_r
->reg_rec_count
= 3;
12456 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12458 return ARM_RECORD_SUCCESS
;
12461 return ARM_RECORD_FAILURE
;
12464 /* Handler for thumb2 load word instructions. */
12467 thumb2_record_ld_word (insn_decode_record
*thumb2_insn_r
)
12469 uint32_t record_buf
[8];
12471 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12472 record_buf
[1] = ARM_PS_REGNUM
;
12473 thumb2_insn_r
->reg_rec_count
= 2;
12475 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12477 return ARM_RECORD_SUCCESS
;
12480 /* Handler for thumb2 long multiply, long multiply accumulate, and
12481 divide instructions. */
12484 thumb2_record_lmul_lmla_div (insn_decode_record
*thumb2_insn_r
)
12486 uint32_t opcode1
= 0, opcode2
= 0;
12487 uint32_t record_buf
[8];
12489 opcode1
= bits (thumb2_insn_r
->arm_insn
, 20, 22);
12490 opcode2
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12492 if (0 == opcode1
|| 2 == opcode1
|| (opcode1
>= 4 && opcode1
<= 6))
12494 /* Handle SMULL, UMULL, SMULAL. */
12495 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
12496 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12497 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12498 record_buf
[2] = ARM_PS_REGNUM
;
12499 thumb2_insn_r
->reg_rec_count
= 3;
12501 else if (1 == opcode1
|| 3 == opcode2
)
12503 /* Handle SDIV and UDIV. */
12504 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12505 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12506 record_buf
[2] = ARM_PS_REGNUM
;
12507 thumb2_insn_r
->reg_rec_count
= 3;
12510 return ARM_RECORD_FAILURE
;
12512 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12514 return ARM_RECORD_SUCCESS
;
12517 /* Record handler for thumb32 coprocessor instructions. */
12520 thumb2_record_coproc_insn (insn_decode_record
*thumb2_insn_r
)
12522 if (bit (thumb2_insn_r
->arm_insn
, 25))
12523 return arm_record_coproc_data_proc (thumb2_insn_r
);
12525 return arm_record_asimd_vfp_coproc (thumb2_insn_r
);
12528 /* Record handler for advance SIMD structure load/store instructions. */
12531 thumb2_record_asimd_struct_ld_st (insn_decode_record
*thumb2_insn_r
)
12533 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12534 uint32_t l_bit
, a_bit
, b_bits
;
12535 uint32_t record_buf
[128], record_buf_mem
[128];
12536 uint32_t reg_rn
, reg_vd
, address
, f_elem
;
12537 uint32_t index_r
= 0, index_e
= 0, bf_regs
= 0, index_m
= 0, loop_t
= 0;
12540 l_bit
= bit (thumb2_insn_r
->arm_insn
, 21);
12541 a_bit
= bit (thumb2_insn_r
->arm_insn
, 23);
12542 b_bits
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12543 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12544 reg_vd
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12545 reg_vd
= (bit (thumb2_insn_r
->arm_insn
, 22) << 4) | reg_vd
;
12546 f_ebytes
= (1 << bits (thumb2_insn_r
->arm_insn
, 6, 7));
12547 f_elem
= 8 / f_ebytes
;
12551 ULONGEST u_regval
= 0;
12552 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12553 address
= u_regval
;
12558 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12560 if (b_bits
== 0x07)
12562 else if (b_bits
== 0x0a)
12564 else if (b_bits
== 0x06)
12566 else if (b_bits
== 0x02)
12571 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12573 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12575 record_buf_mem
[index_m
++] = f_ebytes
;
12576 record_buf_mem
[index_m
++] = address
;
12577 address
= address
+ f_ebytes
;
12578 thumb2_insn_r
->mem_rec_count
+= 1;
12583 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12585 if (b_bits
== 0x09 || b_bits
== 0x08)
12587 else if (b_bits
== 0x03)
12592 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12593 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12595 for (loop_t
= 0; loop_t
< 2; loop_t
++)
12597 record_buf_mem
[index_m
++] = f_ebytes
;
12598 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12599 thumb2_insn_r
->mem_rec_count
+= 1;
12601 address
= address
+ (2 * f_ebytes
);
12605 else if ((b_bits
& 0x0e) == 0x04)
12607 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12609 for (loop_t
= 0; loop_t
< 3; loop_t
++)
12611 record_buf_mem
[index_m
++] = f_ebytes
;
12612 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12613 thumb2_insn_r
->mem_rec_count
+= 1;
12615 address
= address
+ (3 * f_ebytes
);
12619 else if (!(b_bits
& 0x0e))
12621 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12623 for (loop_t
= 0; loop_t
< 4; loop_t
++)
12625 record_buf_mem
[index_m
++] = f_ebytes
;
12626 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12627 thumb2_insn_r
->mem_rec_count
+= 1;
12629 address
= address
+ (4 * f_ebytes
);
12635 uint8_t bft_size
= bits (thumb2_insn_r
->arm_insn
, 10, 11);
12637 if (bft_size
== 0x00)
12639 else if (bft_size
== 0x01)
12641 else if (bft_size
== 0x02)
12647 if (!(b_bits
& 0x0b) || b_bits
== 0x08)
12648 thumb2_insn_r
->mem_rec_count
= 1;
12650 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09)
12651 thumb2_insn_r
->mem_rec_count
= 2;
12653 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a)
12654 thumb2_insn_r
->mem_rec_count
= 3;
12656 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b)
12657 thumb2_insn_r
->mem_rec_count
= 4;
12659 for (index_m
= 0; index_m
< thumb2_insn_r
->mem_rec_count
; index_m
++)
12661 record_buf_mem
[index_m
] = f_ebytes
;
12662 record_buf_mem
[index_m
] = address
+ (index_m
* f_ebytes
);
12671 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12672 thumb2_insn_r
->reg_rec_count
= 1;
12674 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12675 thumb2_insn_r
->reg_rec_count
= 2;
12677 else if ((b_bits
& 0x0e) == 0x04)
12678 thumb2_insn_r
->reg_rec_count
= 3;
12680 else if (!(b_bits
& 0x0e))
12681 thumb2_insn_r
->reg_rec_count
= 4;
12686 if (!(b_bits
& 0x0b) || b_bits
== 0x08 || b_bits
== 0x0c)
12687 thumb2_insn_r
->reg_rec_count
= 1;
12689 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09 || b_bits
== 0x0d)
12690 thumb2_insn_r
->reg_rec_count
= 2;
12692 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a || b_bits
== 0x0e)
12693 thumb2_insn_r
->reg_rec_count
= 3;
12695 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b || b_bits
== 0x0f)
12696 thumb2_insn_r
->reg_rec_count
= 4;
12698 for (index_r
= 0; index_r
< thumb2_insn_r
->reg_rec_count
; index_r
++)
12699 record_buf
[index_r
] = reg_vd
+ ARM_D0_REGNUM
+ index_r
;
12703 if (bits (thumb2_insn_r
->arm_insn
, 0, 3) != 15)
12705 record_buf
[index_r
] = reg_rn
;
12706 thumb2_insn_r
->reg_rec_count
+= 1;
12709 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12711 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12716 /* Decodes thumb2 instruction type and invokes its record handler. */
12718 static unsigned int
12719 thumb2_record_decode_insn_handler (insn_decode_record
*thumb2_insn_r
)
12721 uint32_t op
, op1
, op2
;
12723 op
= bit (thumb2_insn_r
->arm_insn
, 15);
12724 op1
= bits (thumb2_insn_r
->arm_insn
, 27, 28);
12725 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12729 if (!(op2
& 0x64 ))
12731 /* Load/store multiple instruction. */
12732 return thumb2_record_ld_st_multiple (thumb2_insn_r
);
12734 else if (!((op2
& 0x64) ^ 0x04))
12736 /* Load/store (dual/exclusive) and table branch instruction. */
12737 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r
);
12739 else if (!((op2
& 0x20) ^ 0x20))
12741 /* Data-processing (shifted register). */
12742 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12744 else if (op2
& 0x40)
12746 /* Co-processor instructions. */
12747 return thumb2_record_coproc_insn (thumb2_insn_r
);
12750 else if (op1
== 0x02)
12754 /* Branches and miscellaneous control instructions. */
12755 return thumb2_record_branch_misc_cntrl (thumb2_insn_r
);
12757 else if (op2
& 0x20)
12759 /* Data-processing (plain binary immediate) instruction. */
12760 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12764 /* Data-processing (modified immediate). */
12765 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12768 else if (op1
== 0x03)
12770 if (!(op2
& 0x71 ))
12772 /* Store single data item. */
12773 return thumb2_record_str_single_data (thumb2_insn_r
);
12775 else if (!((op2
& 0x71) ^ 0x10))
12777 /* Advanced SIMD or structure load/store instructions. */
12778 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r
);
12780 else if (!((op2
& 0x67) ^ 0x01))
12782 /* Load byte, memory hints instruction. */
12783 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
12785 else if (!((op2
& 0x67) ^ 0x03))
12787 /* Load halfword, memory hints instruction. */
12788 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
12790 else if (!((op2
& 0x67) ^ 0x05))
12792 /* Load word instruction. */
12793 return thumb2_record_ld_word (thumb2_insn_r
);
12795 else if (!((op2
& 0x70) ^ 0x20))
12797 /* Data-processing (register) instruction. */
12798 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12800 else if (!((op2
& 0x78) ^ 0x30))
12802 /* Multiply, multiply accumulate, abs diff instruction. */
12803 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12805 else if (!((op2
& 0x78) ^ 0x38))
12807 /* Long multiply, long multiply accumulate, and divide. */
12808 return thumb2_record_lmul_lmla_div (thumb2_insn_r
);
12810 else if (op2
& 0x40)
12812 /* Co-processor instructions. */
12813 return thumb2_record_coproc_insn (thumb2_insn_r
);
12820 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12821 and positive val on fauilure. */
12824 extract_arm_insn (insn_decode_record
*insn_record
, uint32_t insn_size
)
12826 gdb_byte buf
[insn_size
];
12828 memset (&buf
[0], 0, insn_size
);
12830 if (target_read_memory (insn_record
->this_addr
, &buf
[0], insn_size
))
12832 insn_record
->arm_insn
= (uint32_t) extract_unsigned_integer (&buf
[0],
12834 gdbarch_byte_order_for_code (insn_record
->gdbarch
));
12838 typedef int (*sti_arm_hdl_fp_t
) (insn_decode_record
*);
12840 /* Decode arm/thumb insn depending on condition cods and opcodes; and
12844 decode_insn (insn_decode_record
*arm_record
, record_type_t record_type
,
12845 uint32_t insn_size
)
12848 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm
12850 static const sti_arm_hdl_fp_t arm_handle_insn
[8] =
12852 arm_record_data_proc_misc_ld_str
, /* 000. */
12853 arm_record_data_proc_imm
, /* 001. */
12854 arm_record_ld_st_imm_offset
, /* 010. */
12855 arm_record_ld_st_reg_offset
, /* 011. */
12856 arm_record_ld_st_multiple
, /* 100. */
12857 arm_record_b_bl
, /* 101. */
12858 arm_record_asimd_vfp_coproc
, /* 110. */
12859 arm_record_coproc_data_proc
/* 111. */
12862 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb
12864 static const sti_arm_hdl_fp_t thumb_handle_insn
[8] =
12866 thumb_record_shift_add_sub
, /* 000. */
12867 thumb_record_add_sub_cmp_mov
, /* 001. */
12868 thumb_record_ld_st_reg_offset
, /* 010. */
12869 thumb_record_ld_st_imm_offset
, /* 011. */
12870 thumb_record_ld_st_stack
, /* 100. */
12871 thumb_record_misc
, /* 101. */
12872 thumb_record_ldm_stm_swi
, /* 110. */
12873 thumb_record_branch
/* 111. */
12876 uint32_t ret
= 0; /* return value: negative:failure 0:success. */
12877 uint32_t insn_id
= 0;
12879 if (extract_arm_insn (arm_record
, insn_size
))
12883 printf_unfiltered (_("Process record: error reading memory at "
12884 "addr %s len = %d.\n"),
12885 paddress (arm_record
->gdbarch
,
12886 arm_record
->this_addr
), insn_size
);
12890 else if (ARM_RECORD
== record_type
)
12892 arm_record
->cond
= bits (arm_record
->arm_insn
, 28, 31);
12893 insn_id
= bits (arm_record
->arm_insn
, 25, 27);
12895 if (arm_record
->cond
== 0xf)
12896 ret
= arm_record_extension_space (arm_record
);
12899 /* If this insn has fallen into extension space
12900 then we need not decode it anymore. */
12901 ret
= arm_handle_insn
[insn_id
] (arm_record
);
12903 if (ret
!= ARM_RECORD_SUCCESS
)
12905 arm_record_unsupported_insn (arm_record
);
12909 else if (THUMB_RECORD
== record_type
)
12911 /* As thumb does not have condition codes, we set negative. */
12912 arm_record
->cond
= -1;
12913 insn_id
= bits (arm_record
->arm_insn
, 13, 15);
12914 ret
= thumb_handle_insn
[insn_id
] (arm_record
);
12915 if (ret
!= ARM_RECORD_SUCCESS
)
12917 arm_record_unsupported_insn (arm_record
);
12921 else if (THUMB2_RECORD
== record_type
)
12923 /* As thumb does not have condition codes, we set negative. */
12924 arm_record
->cond
= -1;
12926 /* Swap first half of 32bit thumb instruction with second half. */
12927 arm_record
->arm_insn
12928 = (arm_record
->arm_insn
>> 16) | (arm_record
->arm_insn
<< 16);
12930 ret
= thumb2_record_decode_insn_handler (arm_record
);
12932 if (ret
!= ARM_RECORD_SUCCESS
)
12934 arm_record_unsupported_insn (arm_record
);
12940 /* Throw assertion. */
12941 gdb_assert_not_reached ("not a valid instruction, could not decode");
12948 /* Cleans up local record registers and memory allocations. */
12951 deallocate_reg_mem (insn_decode_record
*record
)
12953 xfree (record
->arm_regs
);
12954 xfree (record
->arm_mems
);
12958 /* Parse the current instruction and record the values of the registers and
12959 memory that will be changed in current instruction to record_arch_list".
12960 Return -1 if something is wrong. */
12963 arm_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
12964 CORE_ADDR insn_addr
)
12967 uint32_t no_of_rec
= 0;
12968 uint32_t ret
= 0; /* return value: -1:record failure ; 0:success */
12969 ULONGEST t_bit
= 0, insn_id
= 0;
12971 ULONGEST u_regval
= 0;
12973 insn_decode_record arm_record
;
12975 memset (&arm_record
, 0, sizeof (insn_decode_record
));
12976 arm_record
.regcache
= regcache
;
12977 arm_record
.this_addr
= insn_addr
;
12978 arm_record
.gdbarch
= gdbarch
;
12981 if (record_debug
> 1)
12983 fprintf_unfiltered (gdb_stdlog
, "Process record: arm_process_record "
12985 paddress (gdbarch
, arm_record
.this_addr
));
12988 if (extract_arm_insn (&arm_record
, 2))
12992 printf_unfiltered (_("Process record: error reading memory at "
12993 "addr %s len = %d.\n"),
12994 paddress (arm_record
.gdbarch
,
12995 arm_record
.this_addr
), 2);
13000 /* Check the insn, whether it is thumb or arm one. */
13002 t_bit
= arm_psr_thumb_bit (arm_record
.gdbarch
);
13003 regcache_raw_read_unsigned (arm_record
.regcache
, ARM_PS_REGNUM
, &u_regval
);
13006 if (!(u_regval
& t_bit
))
13008 /* We are decoding arm insn. */
13009 ret
= decode_insn (&arm_record
, ARM_RECORD
, ARM_INSN_SIZE_BYTES
);
13013 insn_id
= bits (arm_record
.arm_insn
, 11, 15);
13014 /* is it thumb2 insn? */
13015 if ((0x1D == insn_id
) || (0x1E == insn_id
) || (0x1F == insn_id
))
13017 ret
= decode_insn (&arm_record
, THUMB2_RECORD
,
13018 THUMB2_INSN_SIZE_BYTES
);
13022 /* We are decoding thumb insn. */
13023 ret
= decode_insn (&arm_record
, THUMB_RECORD
, THUMB_INSN_SIZE_BYTES
);
13029 /* Record registers. */
13030 record_full_arch_list_add_reg (arm_record
.regcache
, ARM_PC_REGNUM
);
13031 if (arm_record
.arm_regs
)
13033 for (no_of_rec
= 0; no_of_rec
< arm_record
.reg_rec_count
; no_of_rec
++)
13035 if (record_full_arch_list_add_reg
13036 (arm_record
.regcache
, arm_record
.arm_regs
[no_of_rec
]))
13040 /* Record memories. */
13041 if (arm_record
.arm_mems
)
13043 for (no_of_rec
= 0; no_of_rec
< arm_record
.mem_rec_count
; no_of_rec
++)
13045 if (record_full_arch_list_add_mem
13046 ((CORE_ADDR
)arm_record
.arm_mems
[no_of_rec
].addr
,
13047 arm_record
.arm_mems
[no_of_rec
].len
))
13052 if (record_full_arch_list_add_end ())
13057 deallocate_reg_mem (&arm_record
);