1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 #include <ctype.h> /* XXX for isupper () */
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register styles. */
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
42 #include "gdb/sim-arm.h"
45 #include "coff/internal.h"
48 #include "gdb_assert.h"
52 /* Each OS has a different mechanism for accessing the various
53 registers stored in the sigcontext structure.
55 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
56 function pointer) which may be used to determine the addresses
57 of the various saved registers in the sigcontext structure.
59 For the ARM target, there are three parameters to this function.
60 The first is the pc value of the frame under consideration, the
61 second the stack pointer of this frame, and the last is the
62 register number to fetch.
64 If the tm.h file does not define this macro, then it's assumed that
65 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
68 When it comes time to multi-arching this code, see the identically
69 named machinery in ia64-tdep.c for an example of how it could be
70 done. It should not be necessary to modify the code below where
71 this macro is used. */
73 #ifdef SIGCONTEXT_REGISTER_ADDRESS
74 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
75 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
78 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
79 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
82 /* Macros for setting and testing a bit in a minimal symbol that marks
83 it as Thumb function. The MSB of the minimal symbol's "info" field
84 is used for this purpose. This field is already being used to store
85 the symbol size, so the assumption is that the symbol size cannot
88 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
89 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol.
90 MSYMBOL_SIZE Returns the size of the minimal symbol,
91 i.e. the "info" field with the "special" bit
94 #define MSYMBOL_SET_SPECIAL(msym) \
95 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
98 #define MSYMBOL_IS_SPECIAL(msym) \
99 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
101 #define MSYMBOL_SIZE(msym) \
102 ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
104 /* The list of available "set arm ..." and "show arm ..." commands. */
105 static struct cmd_list_element
*setarmcmdlist
= NULL
;
106 static struct cmd_list_element
*showarmcmdlist
= NULL
;
108 /* The type of floating-point to use. Keep this in sync with enum
109 arm_float_model, and the help string in _initialize_arm_tdep. */
110 static const char *fp_model_strings
[] =
119 /* A variable that can be configured by the user. */
120 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
121 static const char *current_fp_model
= "auto";
123 /* Number of different reg name sets (options). */
124 static int num_disassembly_options
;
126 /* We have more registers than the disassembler as gdb can print the value
127 of special registers as well.
128 The general register names are overwritten by whatever is being used by
129 the disassembler at the moment. We also adjust the case of cpsr and fps. */
131 /* Initial value: Register names used in ARM's ISA documentation. */
132 static char * arm_register_name_strings
[] =
133 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
134 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
135 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
136 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
137 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
138 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
139 "fps", "cpsr" }; /* 24 25 */
140 static char **arm_register_names
= arm_register_name_strings
;
142 /* Valid register name styles. */
143 static const char **valid_disassembly_styles
;
145 /* Disassembly style to use. Default to "std" register names. */
146 static const char *disassembly_style
;
147 /* Index to that option in the opcodes table. */
148 static int current_option
;
150 /* This is used to keep the bfd arch_info in sync with the disassembly
152 static void set_disassembly_style_sfunc(char *, int,
153 struct cmd_list_element
*);
154 static void set_disassembly_style (void);
156 static void convert_from_extended (const struct floatformat
*, const void *,
158 static void convert_to_extended (const struct floatformat
*, void *,
161 struct arm_prologue_cache
163 /* The stack pointer at the time this frame was created; i.e. the
164 caller's stack pointer when this function was called. It is used
165 to identify this frame. */
168 /* The frame base for this frame is just prev_sp + frame offset -
169 frame size. FRAMESIZE is the size of this stack frame, and
170 FRAMEOFFSET if the initial offset from the stack pointer (this
171 frame's stack pointer, not PREV_SP) to the frame base. */
176 /* The register used to hold the frame pointer for this frame. */
179 /* Saved register offsets. */
180 struct trad_frame_saved_reg
*saved_regs
;
183 /* Addresses for calling Thumb functions have the bit 0 set.
184 Here are some macros to test, set, or clear bit 0 of addresses. */
185 #define IS_THUMB_ADDR(addr) ((addr) & 1)
186 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
187 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
189 /* Set to true if the 32-bit mode is in use. */
193 /* Flag set by arm_fix_call_dummy that tells whether the target
194 function is a Thumb function. This flag is checked by
195 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
196 its use in valops.c) to pass the function address as an additional
199 static int target_is_thumb
;
201 /* Flag set by arm_fix_call_dummy that tells whether the calling
202 function is a Thumb function. This flag is checked by
203 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
205 static int caller_is_thumb
;
207 /* Determine if the program counter specified in MEMADDR is in a Thumb
211 arm_pc_is_thumb (CORE_ADDR memaddr
)
213 struct minimal_symbol
*sym
;
215 /* If bit 0 of the address is set, assume this is a Thumb address. */
216 if (IS_THUMB_ADDR (memaddr
))
219 /* Thumb functions have a "special" bit set in minimal symbols. */
220 sym
= lookup_minimal_symbol_by_pc (memaddr
);
223 return (MSYMBOL_IS_SPECIAL (sym
));
231 /* Determine if the program counter specified in MEMADDR is in a call
232 dummy being called from a Thumb function. */
235 arm_pc_is_thumb_dummy (CORE_ADDR memaddr
)
237 CORE_ADDR sp
= read_sp ();
239 /* FIXME: Until we switch for the new call dummy macros, this heuristic
240 is the best we can do. We are trying to determine if the pc is on
241 the stack, which (hopefully) will only happen in a call dummy.
242 We hope the current stack pointer is not so far alway from the dummy
243 frame location (true if we have not pushed large data structures or
244 gone too many levels deep) and that our 1024 is not enough to consider
245 code regions as part of the stack (true for most practical purposes). */
246 if (DEPRECATED_PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 1024))
247 return caller_is_thumb
;
252 /* Remove useless bits from addresses in a running program. */
254 arm_addr_bits_remove (CORE_ADDR val
)
257 return (val
& (arm_pc_is_thumb (val
) ? 0xfffffffe : 0xfffffffc));
259 return (val
& 0x03fffffc);
262 /* When reading symbols, we need to zap the low bit of the address,
263 which may be set to 1 for Thumb functions. */
265 arm_smash_text_address (CORE_ADDR val
)
270 /* Immediately after a function call, return the saved pc. Can't
271 always go through the frames for this because on some machines the
272 new frame is not set up until the new function executes some
276 arm_saved_pc_after_call (struct frame_info
*frame
)
278 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM
));
281 /* Determine whether the function invocation represented by FI has a
282 frame on the stack associated with it. If it does return zero,
283 otherwise return 1. */
286 arm_frameless_function_invocation (struct frame_info
*fi
)
288 CORE_ADDR func_start
, after_prologue
;
291 /* Sometimes we have functions that do a little setup (like saving the
292 vN registers with the stmdb instruction, but DO NOT set up a frame.
293 The symbol table will report this as a prologue. However, it is
294 important not to try to parse these partial frames as frames, or we
295 will get really confused.
297 So I will demand 3 instructions between the start & end of the
298 prologue before I call it a real prologue, i.e. at least
303 func_start
= (get_frame_func (fi
) + FUNCTION_START_OFFSET
);
304 after_prologue
= SKIP_PROLOGUE (func_start
);
306 /* There are some frameless functions whose first two instructions
307 follow the standard APCS form, in which case after_prologue will
308 be func_start + 8. */
310 frameless
= (after_prologue
< func_start
+ 12);
314 /* A typical Thumb prologue looks like this:
318 Sometimes the latter instruction may be replaced by:
326 or, on tpcs, like this:
333 There is always one instruction of three classes:
338 When we have found at least one of each class we are done with the prolog.
339 Note that the "sub sp, #NN" before the push does not count.
343 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
345 CORE_ADDR current_pc
;
347 bit 0 - push { rlist }
348 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
349 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
353 for (current_pc
= pc
;
354 current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40;
357 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
359 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
361 findmask
|= 1; /* push found */
363 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
366 if ((findmask
& 1) == 0) /* before push ? */
369 findmask
|= 4; /* add/sub sp found */
371 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
373 findmask
|= 2; /* setting of r7 found */
375 else if (insn
== 0x466f) /* mov r7, sp */
377 findmask
|= 2; /* setting of r7 found */
379 else if (findmask
== (4+2+1))
381 /* We have found one of each type of prologue instruction */
385 /* Something in the prolog that we don't care about or some
386 instruction from outside the prolog scheduled here for
394 /* Advance the PC across any function entry prologue instructions to
395 reach some "real" code.
397 The APCS (ARM Procedure Call Standard) defines the following
401 [stmfd sp!, {a1,a2,a3,a4}]
402 stmfd sp!, {...,fp,ip,lr,pc}
403 [stfe f7, [sp, #-12]!]
404 [stfe f6, [sp, #-12]!]
405 [stfe f5, [sp, #-12]!]
406 [stfe f4, [sp, #-12]!]
407 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
410 arm_skip_prologue (CORE_ADDR pc
)
414 CORE_ADDR func_addr
, func_end
= 0;
416 struct symtab_and_line sal
;
418 /* If we're in a dummy frame, don't even try to skip the prologue. */
419 if (DEPRECATED_PC_IN_CALL_DUMMY (pc
, 0, 0))
422 /* See what the symbol table says. */
424 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
428 /* Found a function. */
429 sym
= lookup_symbol (func_name
, NULL
, VAR_DOMAIN
, NULL
, NULL
);
430 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
432 /* Don't use this trick for assembly source files. */
433 sal
= find_pc_line (func_addr
, 0);
434 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
439 /* Check if this is Thumb code. */
440 if (arm_pc_is_thumb (pc
))
441 return thumb_skip_prologue (pc
, func_end
);
443 /* Can't find the prologue end in the symbol table, try it the hard way
444 by disassembling the instructions. */
446 /* Like arm_scan_prologue, stop no later than pc + 64. */
447 if (func_end
== 0 || func_end
> pc
+ 64)
450 for (skip_pc
= pc
; skip_pc
< func_end
; skip_pc
+= 4)
452 inst
= read_memory_integer (skip_pc
, 4);
454 /* "mov ip, sp" is no longer a required part of the prologue. */
455 if (inst
== 0xe1a0c00d) /* mov ip, sp */
458 /* Some prologues begin with "str lr, [sp, #-4]!". */
459 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
462 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
465 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
468 /* Any insns after this point may float into the code, if it makes
469 for better instruction scheduling, so we skip them only if we
470 find them, but still consider the function to be frame-ful. */
472 /* We may have either one sfmfd instruction here, or several stfe
473 insns, depending on the version of floating point code we
475 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
478 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
481 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
484 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
487 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
488 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
489 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
492 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
493 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
494 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
497 /* Un-recognized instruction; stop scanning. */
501 return skip_pc
; /* End of prologue */
505 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
506 This function decodes a Thumb function prologue to determine:
507 1) the size of the stack frame
508 2) which registers are saved on it
509 3) the offsets of saved regs
510 4) the offset from the stack pointer to the frame pointer
512 A typical Thumb function prologue would create this stack frame
513 (offsets relative to FP)
514 old SP -> 24 stack parameters
517 R7 -> 0 local variables (16 bytes)
518 SP -> -12 additional stack space (12 bytes)
519 The frame size would thus be 36 bytes, and the frame offset would be
520 12 bytes. The frame register is R7.
522 The comments for thumb_skip_prolog() describe the algorithm we use
523 to detect the end of the prolog. */
527 thumb_scan_prologue (CORE_ADDR prev_pc
, struct arm_prologue_cache
*cache
)
529 CORE_ADDR prologue_start
;
530 CORE_ADDR prologue_end
;
531 CORE_ADDR current_pc
;
532 /* Which register has been copied to register n? */
535 bit 0 - push { rlist }
536 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
537 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
542 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
544 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
546 if (sal
.line
== 0) /* no line info, use current PC */
547 prologue_end
= prev_pc
;
548 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
549 prologue_end
= sal
.end
; /* (probably means no prologue) */
552 /* We're in the boondocks: allow for
553 16 pushes, an add, and "mv fp,sp". */
554 prologue_end
= prologue_start
+ 40;
556 prologue_end
= min (prologue_end
, prev_pc
);
558 /* Initialize the saved register map. When register H is copied to
559 register L, we will put H in saved_reg[L]. */
560 for (i
= 0; i
< 16; i
++)
563 /* Search the prologue looking for instructions that set up the
564 frame pointer, adjust the stack pointer, and save registers.
565 Do this until all basic prolog instructions are found. */
567 cache
->framesize
= 0;
568 for (current_pc
= prologue_start
;
569 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
576 insn
= read_memory_unsigned_integer (current_pc
, 2);
578 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
581 findmask
|= 1; /* push found */
582 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
583 whether to save LR (R14). */
584 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
586 /* Calculate offsets of saved R0-R7 and LR. */
587 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
588 if (mask
& (1 << regno
))
590 cache
->framesize
+= 4;
591 cache
->saved_regs
[saved_reg
[regno
]].addr
= -cache
->framesize
;
592 /* Reset saved register map. */
593 saved_reg
[regno
] = regno
;
596 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
599 if ((findmask
& 1) == 0) /* before push? */
602 findmask
|= 4; /* add/sub sp found */
604 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
605 if (insn
& 0x80) /* is it signed? (==subtracting) */
607 cache
->frameoffset
+= offset
;
610 cache
->framesize
-= offset
;
612 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
614 findmask
|= 2; /* setting of r7 found */
615 cache
->framereg
= THUMB_FP_REGNUM
;
616 /* get scaled offset */
617 cache
->frameoffset
= (insn
& 0xff) << 2;
619 else if (insn
== 0x466f) /* mov r7, sp */
621 findmask
|= 2; /* setting of r7 found */
622 cache
->framereg
= THUMB_FP_REGNUM
;
623 cache
->frameoffset
= 0;
624 saved_reg
[THUMB_FP_REGNUM
] = ARM_SP_REGNUM
;
626 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
628 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
629 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
630 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
633 /* Something in the prolog that we don't care about or some
634 instruction from outside the prolog scheduled here for
640 /* This function decodes an ARM function prologue to determine:
641 1) the size of the stack frame
642 2) which registers are saved on it
643 3) the offsets of saved regs
644 4) the offset from the stack pointer to the frame pointer
645 This information is stored in the "extra" fields of the frame_info.
647 There are two basic forms for the ARM prologue. The fixed argument
648 function call will look like:
651 stmfd sp!, {fp, ip, lr, pc}
655 Which would create this stack frame (offsets relative to FP):
656 IP -> 4 (caller's stack)
657 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
658 -4 LR (return address in caller)
659 -8 IP (copy of caller's SP)
661 SP -> -28 Local variables
663 The frame size would thus be 32 bytes, and the frame offset would be
664 28 bytes. The stmfd call can also save any of the vN registers it
665 plans to use, which increases the frame size accordingly.
667 Note: The stored PC is 8 off of the STMFD instruction that stored it
668 because the ARM Store instructions always store PC + 8 when you read
671 A variable argument function call will look like:
674 stmfd sp!, {a1, a2, a3, a4}
675 stmfd sp!, {fp, ip, lr, pc}
678 Which would create this stack frame (offsets relative to FP):
679 IP -> 20 (caller's stack)
684 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
685 -4 LR (return address in caller)
686 -8 IP (copy of caller's SP)
688 SP -> -28 Local variables
690 The frame size would thus be 48 bytes, and the frame offset would be
693 There is another potential complication, which is that the optimizer
694 will try to separate the store of fp in the "stmfd" instruction from
695 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
696 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
698 Also, note, the original version of the ARM toolchain claimed that there
701 instruction at the end of the prologue. I have never seen GCC produce
702 this, and the ARM docs don't mention it. We still test for it below in
708 arm_scan_prologue (struct frame_info
*next_frame
, struct arm_prologue_cache
*cache
)
710 int regno
, sp_offset
, fp_offset
;
711 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
712 CORE_ADDR prev_pc
= frame_pc_unwind (next_frame
);
714 /* Assume there is no frame until proven otherwise. */
715 cache
->framereg
= ARM_SP_REGNUM
;
716 cache
->framesize
= 0;
717 cache
->frameoffset
= 0;
719 /* Check for Thumb prologue. */
720 if (arm_pc_is_thumb (prev_pc
))
722 thumb_scan_prologue (prev_pc
, cache
);
726 /* Find the function prologue. If we can't find the function in
727 the symbol table, peek in the stack frame to find the PC. */
728 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
730 /* One way to find the end of the prologue (which works well
731 for unoptimized code) is to do the following:
733 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
736 prologue_end = prev_pc;
737 else if (sal.end < prologue_end)
738 prologue_end = sal.end;
740 This mechanism is very accurate so long as the optimizer
741 doesn't move any instructions from the function body into the
742 prologue. If this happens, sal.end will be the last
743 instruction in the first hunk of prologue code just before
744 the first instruction that the scheduler has moved from
745 the body to the prologue.
747 In order to make sure that we scan all of the prologue
748 instructions, we use a slightly less accurate mechanism which
749 may scan more than necessary. To help compensate for this
750 lack of accuracy, the prologue scanning loop below contains
751 several clauses which'll cause the loop to terminate early if
752 an implausible prologue instruction is encountered.
758 is a suitable endpoint since it accounts for the largest
759 possible prologue plus up to five instructions inserted by
762 if (prologue_end
> prologue_start
+ 64)
764 prologue_end
= prologue_start
+ 64; /* See above. */
769 /* We have no symbol information. Our only option is to assume this
770 function has a standard stack frame and the normal frame register.
771 Then, we can find the value of our frame pointer on entrance to
772 the callee (or at the present moment if this is the innermost frame).
773 The value stored there should be the address of the stmfd + 8. */
775 LONGEST return_value
;
777 frame_loc
= frame_unwind_register_unsigned (next_frame
, ARM_FP_REGNUM
);
778 if (!safe_read_memory_integer (frame_loc
, 4, &return_value
))
782 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
783 prologue_end
= prologue_start
+ 64; /* See above. */
787 if (prev_pc
< prologue_end
)
788 prologue_end
= prev_pc
;
790 /* Now search the prologue looking for instructions that set up the
791 frame pointer, adjust the stack pointer, and save registers.
793 Be careful, however, and if it doesn't look like a prologue,
794 don't try to scan it. If, for instance, a frameless function
795 begins with stmfd sp!, then we will tell ourselves there is
796 a frame, which will confuse stack traceback, as well as "finish"
797 and other operations that rely on a knowledge of the stack
800 In the APCS, the prologue should start with "mov ip, sp" so
801 if we don't see this as the first insn, we will stop.
803 [Note: This doesn't seem to be true any longer, so it's now an
804 optional part of the prologue. - Kevin Buettner, 2001-11-20]
806 [Note further: The "mov ip,sp" only seems to be missing in
807 frameless functions at optimization level "-O2" or above,
808 in which case it is often (but not always) replaced by
809 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
811 sp_offset
= fp_offset
= 0;
813 for (current_pc
= prologue_start
;
814 current_pc
< prologue_end
;
817 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
819 if (insn
== 0xe1a0c00d) /* mov ip, sp */
823 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
825 /* Function is frameless: extra_info defaults OK? */
828 else if ((insn
& 0xffff0000) == 0xe92d0000)
829 /* stmfd sp!, {..., fp, ip, lr, pc}
831 stmfd sp!, {a1, a2, a3, a4} */
833 int mask
= insn
& 0xffff;
835 /* Calculate offsets of saved registers. */
836 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
837 if (mask
& (1 << regno
))
840 cache
->saved_regs
[regno
].addr
= sp_offset
;
843 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
844 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
845 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
847 /* No need to add this to saved_regs -- it's just an arg reg. */
850 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
851 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
852 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
854 /* No need to add this to saved_regs -- it's just an arg reg. */
857 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
859 unsigned imm
= insn
& 0xff; /* immediate value */
860 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
861 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
863 cache
->framereg
= ARM_FP_REGNUM
;
865 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
867 unsigned imm
= insn
& 0xff; /* immediate value */
868 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
869 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
872 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
875 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
876 cache
->saved_regs
[regno
].addr
= sp_offset
;
878 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
881 unsigned int fp_start_reg
, fp_bound_reg
;
883 if ((insn
& 0x800) == 0x800) /* N0 is set */
885 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
892 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
898 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
899 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
900 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
903 cache
->saved_regs
[fp_start_reg
++].addr
= sp_offset
;
906 else if ((insn
& 0xf0000000) != 0xe0000000)
907 break; /* Condition not true, exit early */
908 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
909 break; /* Don't scan past a block load */
911 /* The optimizer might shove anything into the prologue,
912 so we just skip what we don't recognize. */
916 /* The frame size is just the negative of the offset (from the
917 original SP) of the last thing thing we pushed on the stack.
918 The frame offset is [new FP] - [new SP]. */
919 cache
->framesize
= -sp_offset
;
920 if (cache
->framereg
== ARM_FP_REGNUM
)
921 cache
->frameoffset
= fp_offset
- sp_offset
;
923 cache
->frameoffset
= 0;
926 static struct arm_prologue_cache
*
927 arm_make_prologue_cache (struct frame_info
*next_frame
)
930 struct arm_prologue_cache
*cache
;
931 CORE_ADDR unwound_fp
;
933 cache
= frame_obstack_zalloc (sizeof (struct arm_prologue_cache
));
934 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
936 arm_scan_prologue (next_frame
, cache
);
938 unwound_fp
= frame_unwind_register_unsigned (next_frame
, cache
->framereg
);
942 cache
->prev_sp
= unwound_fp
+ cache
->framesize
- cache
->frameoffset
;
944 /* Calculate actual addresses of saved registers using offsets
945 determined by arm_scan_prologue. */
946 for (reg
= 0; reg
< NUM_REGS
; reg
++)
947 if (cache
->saved_regs
[reg
].addr
!= 0)
948 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
953 /* Our frame ID for a normal frame is the current function's starting PC
954 and the caller's SP when we were called. */
957 arm_prologue_this_id (struct frame_info
*next_frame
,
959 struct frame_id
*this_id
)
961 struct arm_prologue_cache
*cache
;
965 if (*this_cache
== NULL
)
966 *this_cache
= arm_make_prologue_cache (next_frame
);
969 func
= frame_func_unwind (next_frame
);
971 /* This is meant to halt the backtrace at "_start". Make sure we
972 don't halt it at a generic dummy frame. */
973 if (func
<= LOWEST_PC
|| deprecated_inside_entry_file (func
))
976 /* If we've hit a wall, stop. */
977 if (cache
->prev_sp
== 0)
980 id
= frame_id_build (cache
->prev_sp
, func
);
982 /* Check that we're not going round in circles with the same frame
983 ID (but avoid applying the test to sentinel frames which do go
984 round in circles). */
985 if (frame_relative_level (next_frame
) >= 0
986 && get_frame_type (next_frame
) == NORMAL_FRAME
987 && frame_id_eq (get_frame_id (next_frame
), id
))
994 arm_prologue_prev_register (struct frame_info
*next_frame
,
998 enum lval_type
*lvalp
,
1003 struct arm_prologue_cache
*cache
;
1005 if (*this_cache
== NULL
)
1006 *this_cache
= arm_make_prologue_cache (next_frame
);
1007 cache
= *this_cache
;
1009 /* If we are asked to unwind the PC, then we need to return the LR
1010 instead. The saved value of PC points into this frame's
1011 prologue, not the next frame's resume location. */
1012 if (prev_regnum
== ARM_PC_REGNUM
)
1013 prev_regnum
= ARM_LR_REGNUM
;
1015 /* SP is generally not saved to the stack, but this frame is
1016 identified by NEXT_FRAME's stack pointer at the time of the call.
1017 The value was already reconstructed into PREV_SP. */
1018 if (prev_regnum
== ARM_SP_REGNUM
)
1022 store_unsigned_integer (valuep
, 4, cache
->prev_sp
);
1026 trad_frame_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
1027 optimized
, lvalp
, addrp
, realnump
, valuep
);
1030 struct frame_unwind arm_prologue_unwind
= {
1032 arm_prologue_this_id
,
1033 arm_prologue_prev_register
1036 static const struct frame_unwind
*
1037 arm_prologue_unwind_sniffer (struct frame_info
*next_frame
)
1039 return &arm_prologue_unwind
;
1043 arm_normal_frame_base (struct frame_info
*next_frame
, void **this_cache
)
1045 struct arm_prologue_cache
*cache
;
1047 if (*this_cache
== NULL
)
1048 *this_cache
= arm_make_prologue_cache (next_frame
);
1049 cache
= *this_cache
;
1051 return cache
->prev_sp
+ cache
->frameoffset
- cache
->framesize
;
1054 struct frame_base arm_normal_base
= {
1055 &arm_prologue_unwind
,
1056 arm_normal_frame_base
,
1057 arm_normal_frame_base
,
1058 arm_normal_frame_base
1061 static struct arm_prologue_cache
*
1062 arm_make_sigtramp_cache (struct frame_info
*next_frame
)
1064 struct arm_prologue_cache
*cache
;
1067 cache
= frame_obstack_zalloc (sizeof (struct arm_prologue_cache
));
1069 cache
->prev_sp
= frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
);
1071 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1073 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1074 cache
->saved_regs
[reg
].addr
1075 = SIGCONTEXT_REGISTER_ADDRESS (cache
->prev_sp
,
1076 frame_pc_unwind (next_frame
), reg
);
1078 /* FIXME: What about thumb mode? */
1079 cache
->framereg
= ARM_SP_REGNUM
;
1081 = read_memory_integer (cache
->saved_regs
[cache
->framereg
].addr
,
1082 REGISTER_RAW_SIZE (cache
->framereg
));
1088 arm_sigtramp_this_id (struct frame_info
*next_frame
,
1090 struct frame_id
*this_id
)
1092 struct arm_prologue_cache
*cache
;
1094 if (*this_cache
== NULL
)
1095 *this_cache
= arm_make_sigtramp_cache (next_frame
);
1096 cache
= *this_cache
;
1098 /* FIXME drow/2003-07-07: This isn't right if we single-step within
1099 the sigtramp frame; the PC should be the beginning of the trampoline. */
1100 *this_id
= frame_id_build (cache
->prev_sp
, frame_pc_unwind (next_frame
));
1104 arm_sigtramp_prev_register (struct frame_info
*next_frame
,
1108 enum lval_type
*lvalp
,
1113 struct arm_prologue_cache
*cache
;
1115 if (*this_cache
== NULL
)
1116 *this_cache
= arm_make_sigtramp_cache (next_frame
);
1117 cache
= *this_cache
;
1119 trad_frame_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
1120 optimized
, lvalp
, addrp
, realnump
, valuep
);
1123 struct frame_unwind arm_sigtramp_unwind
= {
1125 arm_sigtramp_this_id
,
1126 arm_sigtramp_prev_register
1129 static const struct frame_unwind
*
1130 arm_sigtramp_unwind_sniffer (struct frame_info
*next_frame
)
1132 /* Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare
1133 against the name of the function, the code below will have to be
1134 changed to first fetch the name of the function and then pass
1135 this name to PC_IN_SIGTRAMP. */
1137 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1138 && PC_IN_SIGTRAMP (frame_pc_unwind (next_frame
), (char *) 0))
1139 return &arm_sigtramp_unwind
;
1144 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1145 dummy frame. The frame ID's base needs to match the TOS value
1146 saved by save_dummy_frame_tos() and returned from
1147 arm_push_dummy_call, and the PC needs to match the dummy frame's
1150 static struct frame_id
1151 arm_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1153 return frame_id_build (frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
),
1154 frame_pc_unwind (next_frame
));
1157 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1158 be used to construct the previous frame's ID, after looking up the
1159 containing function). */
1162 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1165 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1166 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1170 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1172 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1175 /* Set the return address for a generic dummy frame. ARM uses the
1179 arm_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
1181 write_register (ARM_LR_REGNUM
, entry_point_address ());
1185 /* Push an empty stack frame, to record the current PC, etc. */
1188 arm_push_dummy_frame (void)
1190 CORE_ADDR old_sp
= read_register (ARM_SP_REGNUM
);
1191 CORE_ADDR sp
= old_sp
;
1192 CORE_ADDR fp
, prologue_start
;
1195 /* Push the two dummy prologue instructions in reverse order,
1196 so that they'll be in the correct low-to-high order in memory. */
1197 /* sub fp, ip, #4 */
1198 sp
= push_word (sp
, 0xe24cb004);
1199 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1200 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
1202 /* Push a pointer to the dummy prologue + 12, because when stm
1203 instruction stores the PC, it stores the address of the stm
1204 instruction itself plus 12. */
1205 fp
= sp
= push_word (sp
, prologue_start
+ 12);
1207 /* Push the processor status. */
1208 sp
= push_word (sp
, read_register (ARM_PS_REGNUM
));
1210 /* Push all 16 registers starting with r15. */
1211 for (regnum
= ARM_PC_REGNUM
; regnum
>= 0; regnum
--)
1212 sp
= push_word (sp
, read_register (regnum
));
1214 /* Update fp (for both Thumb and ARM) and sp. */
1215 write_register (ARM_FP_REGNUM
, fp
);
1216 write_register (THUMB_FP_REGNUM
, fp
);
1217 write_register (ARM_SP_REGNUM
, sp
);
1220 /* DEPRECATED_CALL_DUMMY_WORDS:
1221 This sequence of words is the instructions
1227 Note this is 12 bytes. */
1229 static LONGEST arm_call_dummy_words
[] =
1231 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
1234 /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy
1235 breakpoint to the proper address in the call dummy, so that
1236 `finish' after a stop in a call dummy works.
1238 FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an
1239 optimal solution, but the call to arm_fix_call_dummy is immediately
1240 followed by a call to call_function_by_hand, which is the only
1241 function where call_dummy_breakpoint_offset is actually used. */
1245 arm_set_call_dummy_breakpoint_offset (void)
1247 if (caller_is_thumb
)
1248 set_gdbarch_deprecated_call_dummy_breakpoint_offset (current_gdbarch
, 4);
1250 set_gdbarch_deprecated_call_dummy_breakpoint_offset (current_gdbarch
, 8);
1253 /* Fix up the call dummy, based on whether the processor is currently
1254 in Thumb or ARM mode, and whether the target function is Thumb or
1255 ARM. There are three different situations requiring three
1258 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1259 been copied into the dummy parameter to this function.
1260 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1261 "mov pc,r4" instruction patched to be a "bx r4" instead.
1262 * Thumb calling anything: uses the Thumb dummy defined below, which
1263 works for calling both ARM and Thumb functions.
1265 All three call dummies expect to receive the target function
1266 address in R4, with the low bit set if it's a Thumb function. */
1269 arm_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
1270 struct value
**args
, struct type
*type
, int gcc_p
)
1272 static short thumb_dummy
[4] =
1274 0xf000, 0xf801, /* bl label */
1275 0xdf18, /* swi 24 */
1276 0x4720, /* label: bx r4 */
1278 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
1280 /* Set flag indicating whether the current PC is in a Thumb function. */
1281 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
1282 arm_set_call_dummy_breakpoint_offset ();
1284 /* If the target function is Thumb, set the low bit of the function
1285 address. And if the CPU is currently in ARM mode, patch the
1286 second instruction of call dummy to use a BX instruction to
1287 switch to Thumb mode. */
1288 target_is_thumb
= arm_pc_is_thumb (fun
);
1289 if (target_is_thumb
)
1292 if (!caller_is_thumb
)
1293 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
1296 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1297 instead of the ARM one that's already been copied. This will
1298 work for both Thumb and ARM target functions. */
1299 if (caller_is_thumb
)
1303 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
1305 for (i
= 0; i
< len
; i
++)
1307 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1308 p
+= sizeof (thumb_dummy
[0]);
1312 /* Put the target address in r4; the call dummy will copy this to
1314 write_register (4, fun
);
1317 /* When arguments must be pushed onto the stack, they go on in reverse
1318 order. The code below implements a FILO (stack) to do this. */
1323 struct stack_item
*prev
;
1327 static struct stack_item
*
1328 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1330 struct stack_item
*si
;
1331 si
= xmalloc (sizeof (struct stack_item
));
1332 si
->data
= xmalloc (len
);
1335 memcpy (si
->data
, contents
, len
);
1339 static struct stack_item
*
1340 pop_stack_item (struct stack_item
*si
)
1342 struct stack_item
*dead
= si
;
1349 /* We currently only support passing parameters in integer registers. This
1350 conforms with GCC's default model. Several other variants exist and
1351 we should probably support some of them based on the selected ABI. */
1354 arm_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
1355 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1356 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1357 CORE_ADDR struct_addr
)
1362 struct stack_item
*si
= NULL
;
1364 /* Set the return address. For the ARM, the return breakpoint is
1365 always at BP_ADDR. */
1366 /* XXX Fix for Thumb. */
1367 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1369 /* Walk through the list of args and determine how large a temporary
1370 stack is required. Need to take care here as structs may be
1371 passed on the stack, and we have to to push them. */
1374 argreg
= ARM_A1_REGNUM
;
1377 /* Some platforms require a double-word aligned stack. Make sure sp
1378 is correctly aligned before we start. We always do this even if
1379 it isn't really needed -- it can never hurt things. */
1380 sp
&= ~(CORE_ADDR
)(2 * DEPRECATED_REGISTER_SIZE
- 1);
1382 /* The struct_return pointer occupies the first parameter
1383 passing register. */
1387 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = 0x%s\n",
1388 REGISTER_NAME (argreg
), paddr (struct_addr
));
1389 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1393 for (argnum
= 0; argnum
< nargs
; argnum
++)
1396 struct type
*arg_type
;
1397 struct type
*target_type
;
1398 enum type_code typecode
;
1401 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1402 len
= TYPE_LENGTH (arg_type
);
1403 target_type
= TYPE_TARGET_TYPE (arg_type
);
1404 typecode
= TYPE_CODE (arg_type
);
1405 val
= VALUE_CONTENTS (args
[argnum
]);
1407 /* If the argument is a pointer to a function, and it is a
1408 Thumb function, create a LOCAL copy of the value and set
1409 the THUMB bit in it. */
1410 if (TYPE_CODE_PTR
== typecode
1411 && target_type
!= NULL
1412 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1414 CORE_ADDR regval
= extract_unsigned_integer (val
, len
);
1415 if (arm_pc_is_thumb (regval
))
1418 store_unsigned_integer (val
, len
, MAKE_THUMB_ADDR (regval
));
1422 /* Copy the argument to general registers or the stack in
1423 register-sized pieces. Large arguments are split between
1424 registers and stack. */
1427 int partial_len
= len
< DEPRECATED_REGISTER_SIZE
? len
: DEPRECATED_REGISTER_SIZE
;
1429 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1431 /* The argument is being passed in a general purpose
1433 CORE_ADDR regval
= extract_unsigned_integer (val
, partial_len
);
1435 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1436 argnum
, REGISTER_NAME (argreg
),
1437 phex (regval
, DEPRECATED_REGISTER_SIZE
));
1438 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1443 /* Push the arguments onto the stack. */
1445 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1447 si
= push_stack_item (si
, val
, DEPRECATED_REGISTER_SIZE
);
1448 nstack
+= DEPRECATED_REGISTER_SIZE
;
1455 /* If we have an odd number of words to push, then decrement the stack
1456 by one word now, so first stack argument will be dword aligned. */
1463 write_memory (sp
, si
->data
, si
->len
);
1464 si
= pop_stack_item (si
);
1467 /* Finally, update teh SP register. */
1468 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1474 print_fpu_flags (int flags
)
1476 if (flags
& (1 << 0))
1477 fputs ("IVO ", stdout
);
1478 if (flags
& (1 << 1))
1479 fputs ("DVZ ", stdout
);
1480 if (flags
& (1 << 2))
1481 fputs ("OFL ", stdout
);
1482 if (flags
& (1 << 3))
1483 fputs ("UFL ", stdout
);
1484 if (flags
& (1 << 4))
1485 fputs ("INX ", stdout
);
1489 /* Print interesting information about the floating point processor
1490 (if present) or emulator. */
1492 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1493 struct frame_info
*frame
, const char *args
)
1495 unsigned long status
= read_register (ARM_FPS_REGNUM
);
1498 type
= (status
>> 24) & 127;
1499 printf ("%s FPU type %d\n",
1500 (status
& (1 << 31)) ? "Hardware" : "Software",
1502 fputs ("mask: ", stdout
);
1503 print_fpu_flags (status
>> 16);
1504 fputs ("flags: ", stdout
);
1505 print_fpu_flags (status
);
1508 /* Return the GDB type object for the "standard" data type of data in
1511 static struct type
*
1512 arm_register_type (int regnum
)
1514 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1516 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1517 return builtin_type_arm_ext_big
;
1519 return builtin_type_arm_ext_littlebyte_bigword
;
1522 return builtin_type_int32
;
1525 /* Index within `registers' of the first byte of the space for
1529 arm_register_byte (int regnum
)
1531 if (regnum
< ARM_F0_REGNUM
)
1532 return regnum
* INT_REGISTER_RAW_SIZE
;
1533 else if (regnum
< ARM_PS_REGNUM
)
1534 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1535 + (regnum
- ARM_F0_REGNUM
) * FP_REGISTER_RAW_SIZE
);
1537 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1538 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
1539 + (regnum
- ARM_FPS_REGNUM
) * STATUS_REGISTER_SIZE
);
1542 /* Number of bytes of storage in the actual machine representation for
1543 register N. All registers are 4 bytes, except fp0 - fp7, which are
1544 12 bytes in length. */
1547 arm_register_raw_size (int regnum
)
1549 if (regnum
< ARM_F0_REGNUM
)
1550 return INT_REGISTER_RAW_SIZE
;
1551 else if (regnum
< ARM_FPS_REGNUM
)
1552 return FP_REGISTER_RAW_SIZE
;
1554 return STATUS_REGISTER_SIZE
;
1557 /* Number of bytes of storage in a program's representation
1560 arm_register_virtual_size (int regnum
)
1562 if (regnum
< ARM_F0_REGNUM
)
1563 return INT_REGISTER_VIRTUAL_SIZE
;
1564 else if (regnum
< ARM_FPS_REGNUM
)
1565 return FP_REGISTER_VIRTUAL_SIZE
;
1567 return STATUS_REGISTER_SIZE
;
1570 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1572 arm_register_sim_regno (int regnum
)
1575 gdb_assert (reg
>= 0 && reg
< NUM_REGS
);
1577 if (reg
< NUM_GREGS
)
1578 return SIM_ARM_R0_REGNUM
+ reg
;
1581 if (reg
< NUM_FREGS
)
1582 return SIM_ARM_FP0_REGNUM
+ reg
;
1585 if (reg
< NUM_SREGS
)
1586 return SIM_ARM_FPS_REGNUM
+ reg
;
1589 internal_error (__FILE__
, __LINE__
, "Bad REGNUM %d", regnum
);
1592 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1593 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1594 It is thought that this is is the floating-point register format on
1595 little-endian systems. */
1598 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
1602 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1603 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1605 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1607 floatformat_from_doublest (fmt
, &d
, dbl
);
1611 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
)
1614 floatformat_to_doublest (fmt
, ptr
, &d
);
1615 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1616 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1618 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1623 condition_true (unsigned long cond
, unsigned long status_reg
)
1625 if (cond
== INST_AL
|| cond
== INST_NV
)
1631 return ((status_reg
& FLAG_Z
) != 0);
1633 return ((status_reg
& FLAG_Z
) == 0);
1635 return ((status_reg
& FLAG_C
) != 0);
1637 return ((status_reg
& FLAG_C
) == 0);
1639 return ((status_reg
& FLAG_N
) != 0);
1641 return ((status_reg
& FLAG_N
) == 0);
1643 return ((status_reg
& FLAG_V
) != 0);
1645 return ((status_reg
& FLAG_V
) == 0);
1647 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1649 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1651 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1653 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1655 return (((status_reg
& FLAG_Z
) == 0) &&
1656 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1658 return (((status_reg
& FLAG_Z
) != 0) ||
1659 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1664 /* Support routines for single stepping. Calculate the next PC value. */
1665 #define submask(x) ((1L << ((x) + 1)) - 1)
1666 #define bit(obj,st) (((obj) >> (st)) & 1)
1667 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1668 #define sbits(obj,st,fn) \
1669 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1670 #define BranchDest(addr,instr) \
1671 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1674 static unsigned long
1675 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1676 unsigned long status_reg
)
1678 unsigned long res
, shift
;
1679 int rm
= bits (inst
, 0, 3);
1680 unsigned long shifttype
= bits (inst
, 5, 6);
1684 int rs
= bits (inst
, 8, 11);
1685 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1688 shift
= bits (inst
, 7, 11);
1691 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1692 + (bit (inst
, 4) ? 12 : 8))
1693 : read_register (rm
));
1698 res
= shift
>= 32 ? 0 : res
<< shift
;
1702 res
= shift
>= 32 ? 0 : res
>> shift
;
1708 res
= ((res
& 0x80000000L
)
1709 ? ~((~res
) >> shift
) : res
>> shift
);
1712 case 3: /* ROR/RRX */
1715 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1717 res
= (res
>> shift
) | (res
<< (32 - shift
));
1721 return res
& 0xffffffff;
1724 /* Return number of 1-bits in VAL. */
1727 bitcount (unsigned long val
)
1730 for (nbits
= 0; val
!= 0; nbits
++)
1731 val
&= val
- 1; /* delete rightmost 1-bit in val */
1736 thumb_get_next_pc (CORE_ADDR pc
)
1738 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1739 unsigned short inst1
= read_memory_integer (pc
, 2);
1740 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1741 unsigned long offset
;
1743 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1747 /* Fetch the saved PC from the stack. It's stored above
1748 all of the other registers. */
1749 offset
= bitcount (bits (inst1
, 0, 7)) * DEPRECATED_REGISTER_SIZE
;
1750 sp
= read_register (ARM_SP_REGNUM
);
1751 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1752 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1754 error ("Infinite loop detected");
1756 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1758 unsigned long status
= read_register (ARM_PS_REGNUM
);
1759 unsigned long cond
= bits (inst1
, 8, 11);
1760 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1761 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1763 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1765 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1767 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1769 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1770 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1771 nextpc
= pc_val
+ offset
;
1778 arm_get_next_pc (CORE_ADDR pc
)
1780 unsigned long pc_val
;
1781 unsigned long this_instr
;
1782 unsigned long status
;
1785 if (arm_pc_is_thumb (pc
))
1786 return thumb_get_next_pc (pc
);
1788 pc_val
= (unsigned long) pc
;
1789 this_instr
= read_memory_integer (pc
, 4);
1790 status
= read_register (ARM_PS_REGNUM
);
1791 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1793 if (condition_true (bits (this_instr
, 28, 31), status
))
1795 switch (bits (this_instr
, 24, 27))
1798 case 0x1: /* data processing */
1802 unsigned long operand1
, operand2
, result
= 0;
1806 if (bits (this_instr
, 12, 15) != 15)
1809 if (bits (this_instr
, 22, 25) == 0
1810 && bits (this_instr
, 4, 7) == 9) /* multiply */
1811 error ("Illegal update to pc in instruction");
1813 /* Multiply into PC */
1814 c
= (status
& FLAG_C
) ? 1 : 0;
1815 rn
= bits (this_instr
, 16, 19);
1816 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1818 if (bit (this_instr
, 25))
1820 unsigned long immval
= bits (this_instr
, 0, 7);
1821 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1822 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1825 else /* operand 2 is a shifted register */
1826 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1828 switch (bits (this_instr
, 21, 24))
1831 result
= operand1
& operand2
;
1835 result
= operand1
^ operand2
;
1839 result
= operand1
- operand2
;
1843 result
= operand2
- operand1
;
1847 result
= operand1
+ operand2
;
1851 result
= operand1
+ operand2
+ c
;
1855 result
= operand1
- operand2
+ c
;
1859 result
= operand2
- operand1
+ c
;
1865 case 0xb: /* tst, teq, cmp, cmn */
1866 result
= (unsigned long) nextpc
;
1870 result
= operand1
| operand2
;
1874 /* Always step into a function. */
1879 result
= operand1
& ~operand2
;
1886 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1889 error ("Infinite loop detected");
1894 case 0x5: /* data transfer */
1897 if (bit (this_instr
, 20))
1900 if (bits (this_instr
, 12, 15) == 15)
1906 if (bit (this_instr
, 22))
1907 error ("Illegal update to pc in instruction");
1909 /* byte write to PC */
1910 rn
= bits (this_instr
, 16, 19);
1911 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1912 if (bit (this_instr
, 24))
1915 int c
= (status
& FLAG_C
) ? 1 : 0;
1916 unsigned long offset
=
1917 (bit (this_instr
, 25)
1918 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1919 : bits (this_instr
, 0, 11));
1921 if (bit (this_instr
, 23))
1926 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1929 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1932 error ("Infinite loop detected");
1938 case 0x9: /* block transfer */
1939 if (bit (this_instr
, 20))
1942 if (bit (this_instr
, 15))
1947 if (bit (this_instr
, 23))
1950 unsigned long reglist
= bits (this_instr
, 0, 14);
1951 offset
= bitcount (reglist
) * 4;
1952 if (bit (this_instr
, 24)) /* pre */
1955 else if (bit (this_instr
, 24))
1959 unsigned long rn_val
=
1960 read_register (bits (this_instr
, 16, 19));
1962 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1966 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1968 error ("Infinite loop detected");
1973 case 0xb: /* branch & link */
1974 case 0xa: /* branch */
1976 nextpc
= BranchDest (pc
, this_instr
);
1978 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1980 error ("Infinite loop detected");
1986 case 0xe: /* coproc ops */
1991 fprintf_filtered (gdb_stderr
, "Bad bit-field extraction\n");
1999 /* single_step() is called just before we want to resume the inferior,
2000 if we want to single-step it but there is no hardware or kernel
2001 single-step support. We find the target of the coming instruction
2004 single_step() is also called just after the inferior stops. If we
2005 had set up a simulated single-step, we undo our damage. */
2008 arm_software_single_step (enum target_signal sig
, int insert_bpt
)
2010 static int next_pc
; /* State between setting and unsetting. */
2011 static char break_mem
[BREAKPOINT_MAX
]; /* Temporary storage for mem@bpt */
2015 next_pc
= arm_get_next_pc (read_register (ARM_PC_REGNUM
));
2016 target_insert_breakpoint (next_pc
, break_mem
);
2019 target_remove_breakpoint (next_pc
, break_mem
);
2022 #include "bfd-in2.h"
2023 #include "libcoff.h"
2026 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
2028 if (arm_pc_is_thumb (memaddr
))
2030 static asymbol
*asym
;
2031 static combined_entry_type ce
;
2032 static struct coff_symbol_struct csym
;
2033 static struct bfd fake_bfd
;
2034 static bfd_target fake_target
;
2036 if (csym
.native
== NULL
)
2038 /* Create a fake symbol vector containing a Thumb symbol.
2039 This is solely so that the code in print_insn_little_arm()
2040 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2041 the presence of a Thumb symbol and switch to decoding
2042 Thumb instructions. */
2044 fake_target
.flavour
= bfd_target_coff_flavour
;
2045 fake_bfd
.xvec
= &fake_target
;
2046 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
2048 csym
.symbol
.the_bfd
= &fake_bfd
;
2049 csym
.symbol
.name
= "fake";
2050 asym
= (asymbol
*) & csym
;
2053 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
2054 info
->symbols
= &asym
;
2057 info
->symbols
= NULL
;
2059 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2060 return print_insn_big_arm (memaddr
, info
);
2062 return print_insn_little_arm (memaddr
, info
);
2065 /* The following define instruction sequences that will cause ARM
2066 cpu's to take an undefined instruction trap. These are used to
2067 signal a breakpoint to GDB.
2069 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2070 modes. A different instruction is required for each mode. The ARM
2071 cpu's can also be big or little endian. Thus four different
2072 instructions are needed to support all cases.
2074 Note: ARMv4 defines several new instructions that will take the
2075 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2076 not in fact add the new instructions. The new undefined
2077 instructions in ARMv4 are all instructions that had no defined
2078 behaviour in earlier chips. There is no guarantee that they will
2079 raise an exception, but may be treated as NOP's. In practice, it
2080 may only safe to rely on instructions matching:
2082 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2083 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2084 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2086 Even this may only true if the condition predicate is true. The
2087 following use a condition predicate of ALWAYS so it is always TRUE.
2089 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2090 and NetBSD all use a software interrupt rather than an undefined
2091 instruction to force a trap. This can be handled by by the
2092 abi-specific code during establishment of the gdbarch vector. */
2095 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
2096 override these definitions. */
2097 #ifndef ARM_LE_BREAKPOINT
2098 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2100 #ifndef ARM_BE_BREAKPOINT
2101 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2103 #ifndef THUMB_LE_BREAKPOINT
2104 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
2106 #ifndef THUMB_BE_BREAKPOINT
2107 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
2110 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
2111 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
2112 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2113 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2115 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2116 the program counter value to determine whether a 16-bit or 32-bit
2117 breakpoint should be used. It returns a pointer to a string of
2118 bytes that encode a breakpoint instruction, stores the length of
2119 the string to *lenptr, and adjusts the program counter (if
2120 necessary) to point to the actual memory location where the
2121 breakpoint should be inserted. */
2123 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
2124 breakpoints and storing their handles instread of what was in
2125 memory. It is nice that this is the same size as a handle -
2126 otherwise remote-rdp will have to change. */
2128 static const unsigned char *
2129 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
2131 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2133 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
2135 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2136 *lenptr
= tdep
->thumb_breakpoint_size
;
2137 return tdep
->thumb_breakpoint
;
2141 *lenptr
= tdep
->arm_breakpoint_size
;
2142 return tdep
->arm_breakpoint
;
2146 /* Extract from an array REGBUF containing the (raw) register state a
2147 function return value of type TYPE, and copy that, in virtual
2148 format, into VALBUF. */
2151 arm_extract_return_value (struct type
*type
,
2152 struct regcache
*regs
,
2155 bfd_byte
*valbuf
= dst
;
2157 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2159 switch (arm_get_fp_model (current_gdbarch
))
2163 /* The value is in register F0 in internal format. We need to
2164 extract the raw value and then convert it to the desired
2166 bfd_byte tmpbuf
[FP_REGISTER_RAW_SIZE
];
2168 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
2169 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
2174 case ARM_FLOAT_SOFT_FPA
:
2175 case ARM_FLOAT_SOFT_VFP
:
2176 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
2177 if (TYPE_LENGTH (type
) > 4)
2178 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
2179 valbuf
+ INT_REGISTER_RAW_SIZE
);
2184 (__FILE__
, __LINE__
,
2185 "arm_extract_return_value: Floating point model not supported");
2189 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2190 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2191 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2192 || TYPE_CODE (type
) == TYPE_CODE_PTR
2193 || TYPE_CODE (type
) == TYPE_CODE_REF
2194 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2196 /* If the the type is a plain integer, then the access is
2197 straight-forward. Otherwise we have to play around a bit more. */
2198 int len
= TYPE_LENGTH (type
);
2199 int regno
= ARM_A1_REGNUM
;
2204 /* By using store_unsigned_integer we avoid having to do
2205 anything special for small big-endian values. */
2206 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2207 store_unsigned_integer (valbuf
,
2208 (len
> INT_REGISTER_RAW_SIZE
2209 ? INT_REGISTER_RAW_SIZE
: len
),
2211 len
-= INT_REGISTER_RAW_SIZE
;
2212 valbuf
+= INT_REGISTER_RAW_SIZE
;
2217 /* For a structure or union the behaviour is as if the value had
2218 been stored to word-aligned memory and then loaded into
2219 registers with 32-bit load instruction(s). */
2220 int len
= TYPE_LENGTH (type
);
2221 int regno
= ARM_A1_REGNUM
;
2222 bfd_byte tmpbuf
[INT_REGISTER_RAW_SIZE
];
2226 regcache_cooked_read (regs
, regno
++, tmpbuf
);
2227 memcpy (valbuf
, tmpbuf
,
2228 len
> INT_REGISTER_RAW_SIZE
? INT_REGISTER_RAW_SIZE
: len
);
2229 len
-= INT_REGISTER_RAW_SIZE
;
2230 valbuf
+= INT_REGISTER_RAW_SIZE
;
2235 /* Extract from an array REGBUF containing the (raw) register state
2236 the address in which a function should return its structure value. */
2239 arm_extract_struct_value_address (struct regcache
*regcache
)
2243 regcache_cooked_read_unsigned (regcache
, ARM_A1_REGNUM
, &ret
);
2247 /* Will a function return an aggregate type in memory or in a
2248 register? Return 0 if an aggregate type can be returned in a
2249 register, 1 if it must be returned in memory. */
2252 arm_use_struct_convention (int gcc_p
, struct type
*type
)
2255 enum type_code code
;
2257 /* In the ARM ABI, "integer" like aggregate types are returned in
2258 registers. For an aggregate type to be integer like, its size
2259 must be less than or equal to DEPRECATED_REGISTER_SIZE and the
2260 offset of each addressable subfield must be zero. Note that bit
2261 fields are not addressable, and all addressable subfields of
2262 unions always start at offset zero.
2264 This function is based on the behaviour of GCC 2.95.1.
2265 See: gcc/arm.c: arm_return_in_memory() for details.
2267 Note: All versions of GCC before GCC 2.95.2 do not set up the
2268 parameters correctly for a function returning the following
2269 structure: struct { float f;}; This should be returned in memory,
2270 not a register. Richard Earnshaw sent me a patch, but I do not
2271 know of any way to detect if a function like the above has been
2272 compiled with the correct calling convention. */
2274 /* All aggregate types that won't fit in a register must be returned
2276 if (TYPE_LENGTH (type
) > DEPRECATED_REGISTER_SIZE
)
2281 /* The only aggregate types that can be returned in a register are
2282 structs and unions. Arrays must be returned in memory. */
2283 code
= TYPE_CODE (type
);
2284 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2289 /* Assume all other aggregate types can be returned in a register.
2290 Run a check for structures, unions and arrays. */
2293 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2296 /* Need to check if this struct/union is "integer" like. For
2297 this to be true, its size must be less than or equal to
2298 DEPRECATED_REGISTER_SIZE and the offset of each addressable
2299 subfield must be zero. Note that bit fields are not
2300 addressable, and unions always start at offset zero. If any
2301 of the subfields is a floating point type, the struct/union
2302 cannot be an integer type. */
2304 /* For each field in the object, check:
2305 1) Is it FP? --> yes, nRc = 1;
2306 2) Is it addressable (bitpos != 0) and
2307 not packed (bitsize == 0)?
2311 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2313 enum type_code field_type_code
;
2314 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
2316 /* Is it a floating point type field? */
2317 if (field_type_code
== TYPE_CODE_FLT
)
2323 /* If bitpos != 0, then we have to care about it. */
2324 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2326 /* Bitfields are not addressable. If the field bitsize is
2327 zero, then the field is not packed. Hence it cannot be
2328 a bitfield or any other packed type. */
2329 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2341 /* Write into appropriate registers a function return value of type
2342 TYPE, given in virtual format. */
2345 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
2348 const bfd_byte
*valbuf
= src
;
2350 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2352 char buf
[ARM_MAX_REGISTER_RAW_SIZE
];
2354 switch (arm_get_fp_model (current_gdbarch
))
2358 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
);
2359 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
2362 case ARM_FLOAT_SOFT_FPA
:
2363 case ARM_FLOAT_SOFT_VFP
:
2364 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
2365 if (TYPE_LENGTH (type
) > 4)
2366 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
2367 valbuf
+ INT_REGISTER_RAW_SIZE
);
2372 (__FILE__
, __LINE__
,
2373 "arm_store_return_value: Floating point model not supported");
2377 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2378 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2379 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2380 || TYPE_CODE (type
) == TYPE_CODE_PTR
2381 || TYPE_CODE (type
) == TYPE_CODE_REF
2382 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2384 if (TYPE_LENGTH (type
) <= 4)
2386 /* Values of one word or less are zero/sign-extended and
2388 bfd_byte tmpbuf
[INT_REGISTER_RAW_SIZE
];
2389 LONGEST val
= unpack_long (type
, valbuf
);
2391 store_signed_integer (tmpbuf
, INT_REGISTER_RAW_SIZE
, val
);
2392 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
2396 /* Integral values greater than one word are stored in consecutive
2397 registers starting with r0. This will always be a multiple of
2398 the regiser size. */
2399 int len
= TYPE_LENGTH (type
);
2400 int regno
= ARM_A1_REGNUM
;
2404 regcache_cooked_write (regs
, regno
++, valbuf
);
2405 len
-= INT_REGISTER_RAW_SIZE
;
2406 valbuf
+= INT_REGISTER_RAW_SIZE
;
2412 /* For a structure or union the behaviour is as if the value had
2413 been stored to word-aligned memory and then loaded into
2414 registers with 32-bit load instruction(s). */
2415 int len
= TYPE_LENGTH (type
);
2416 int regno
= ARM_A1_REGNUM
;
2417 bfd_byte tmpbuf
[INT_REGISTER_RAW_SIZE
];
2421 memcpy (tmpbuf
, valbuf
,
2422 len
> INT_REGISTER_RAW_SIZE
? INT_REGISTER_RAW_SIZE
: len
);
2423 regcache_cooked_write (regs
, regno
++, tmpbuf
);
2424 len
-= INT_REGISTER_RAW_SIZE
;
2425 valbuf
+= INT_REGISTER_RAW_SIZE
;
2431 arm_get_longjmp_target (CORE_ADDR
*pc
)
2434 char buf
[INT_REGISTER_RAW_SIZE
];
2435 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2437 jb_addr
= read_register (ARM_A1_REGNUM
);
2439 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2440 INT_REGISTER_RAW_SIZE
))
2443 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_RAW_SIZE
);
2447 /* Return non-zero if the PC is inside a thumb call thunk. */
2450 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2452 CORE_ADDR start_addr
;
2454 /* Find the starting address of the function containing the PC. If
2455 the caller didn't give us a name, look it up at the same time. */
2456 if (0 == find_pc_partial_function (pc
, name
? NULL
: &name
,
2460 return strncmp (name
, "_call_via_r", 11) == 0;
2463 /* If PC is in a Thumb call or return stub, return the address of the
2464 target PC, which is in a register. The thunk functions are called
2465 _called_via_xx, where x is the register name. The possible names
2466 are r0-r9, sl, fp, ip, sp, and lr. */
2469 arm_skip_stub (CORE_ADDR pc
)
2472 CORE_ADDR start_addr
;
2474 /* Find the starting address and name of the function containing the PC. */
2475 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2478 /* Call thunks always start with "_call_via_". */
2479 if (strncmp (name
, "_call_via_", 10) == 0)
2481 /* Use the name suffix to determine which register contains the
2483 static char *table
[15] =
2484 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2485 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2489 for (regno
= 0; regno
<= 14; regno
++)
2490 if (strcmp (&name
[10], table
[regno
]) == 0)
2491 return read_register (regno
);
2494 return 0; /* not a stub */
2498 set_arm_command (char *args
, int from_tty
)
2500 printf_unfiltered ("\"set arm\" must be followed by an apporpriate subcommand.\n");
2501 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
2505 show_arm_command (char *args
, int from_tty
)
2507 cmd_show_list (showarmcmdlist
, from_tty
, "");
2510 enum arm_float_model
2511 arm_get_fp_model (struct gdbarch
*gdbarch
)
2513 if (arm_fp_model
== ARM_FLOAT_AUTO
)
2514 return gdbarch_tdep (gdbarch
)->fp_model
;
2516 return arm_fp_model
;
2520 arm_set_fp (struct gdbarch
*gdbarch
)
2522 enum arm_float_model fp_model
= arm_get_fp_model (gdbarch
);
2524 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
2525 && (fp_model
== ARM_FLOAT_SOFT_FPA
|| fp_model
== ARM_FLOAT_FPA
))
2527 set_gdbarch_double_format (gdbarch
,
2528 &floatformat_ieee_double_littlebyte_bigword
);
2529 set_gdbarch_long_double_format
2530 (gdbarch
, &floatformat_ieee_double_littlebyte_bigword
);
2534 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_little
);
2535 set_gdbarch_long_double_format (gdbarch
,
2536 &floatformat_ieee_double_little
);
2541 set_fp_model_sfunc (char *args
, int from_tty
,
2542 struct cmd_list_element
*c
)
2544 enum arm_float_model fp_model
;
2546 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
2547 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
2549 arm_fp_model
= fp_model
;
2553 if (fp_model
== ARM_FLOAT_LAST
)
2554 internal_error (__FILE__
, __LINE__
, "Invalid fp model accepted: %s.",
2557 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2558 arm_set_fp (current_gdbarch
);
2562 show_fp_model (char *args
, int from_tty
,
2563 struct cmd_list_element
*c
)
2565 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2567 if (arm_fp_model
== ARM_FLOAT_AUTO
2568 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2569 printf_filtered (" - the default for the current ABI is \"%s\".\n",
2570 fp_model_strings
[tdep
->fp_model
]);
2573 /* If the user changes the register disassembly style used for info
2574 register and other commands, we have to also switch the style used
2575 in opcodes for disassembly output. This function is run in the "set
2576 arm disassembly" command, and does that. */
2579 set_disassembly_style_sfunc (char *args
, int from_tty
,
2580 struct cmd_list_element
*c
)
2582 set_disassembly_style ();
2585 /* Return the ARM register name corresponding to register I. */
2587 arm_register_name (int i
)
2589 return arm_register_names
[i
];
2593 set_disassembly_style (void)
2595 const char *setname
, *setdesc
, **regnames
;
2598 /* Find the style that the user wants in the opcodes table. */
2600 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2601 while ((disassembly_style
!= setname
)
2602 && (current
< num_disassembly_options
))
2603 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2604 current_option
= current
;
2606 /* Fill our copy. */
2607 for (j
= 0; j
< numregs
; j
++)
2608 arm_register_names
[j
] = (char *) regnames
[j
];
2611 if (isupper (*regnames
[ARM_PC_REGNUM
]))
2613 arm_register_names
[ARM_FPS_REGNUM
] = "FPS";
2614 arm_register_names
[ARM_PS_REGNUM
] = "CPSR";
2618 arm_register_names
[ARM_FPS_REGNUM
] = "fps";
2619 arm_register_names
[ARM_PS_REGNUM
] = "cpsr";
2622 /* Synchronize the disassembler. */
2623 set_arm_regname_option (current
);
2626 /* arm_othernames implements the "othernames" command. This is deprecated
2627 by the "set arm disassembly" command. */
2630 arm_othernames (char *names
, int n
)
2632 /* Circle through the various flavors. */
2633 current_option
= (current_option
+ 1) % num_disassembly_options
;
2635 disassembly_style
= valid_disassembly_styles
[current_option
];
2636 set_disassembly_style ();
2639 /* Test whether the coff symbol specific value corresponds to a Thumb
2643 coff_sym_is_thumb (int val
)
2645 return (val
== C_THUMBEXT
||
2646 val
== C_THUMBSTAT
||
2647 val
== C_THUMBEXTFUNC
||
2648 val
== C_THUMBSTATFUNC
||
2649 val
== C_THUMBLABEL
);
2652 /* arm_coff_make_msymbol_special()
2653 arm_elf_make_msymbol_special()
2655 These functions test whether the COFF or ELF symbol corresponds to
2656 an address in thumb code, and set a "special" bit in a minimal
2657 symbol to indicate that it does. */
2660 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2662 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2664 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2666 MSYMBOL_SET_SPECIAL (msym
);
2670 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2672 if (coff_sym_is_thumb (val
))
2673 MSYMBOL_SET_SPECIAL (msym
);
2677 static enum gdb_osabi
2678 arm_elf_osabi_sniffer (bfd
*abfd
)
2680 unsigned int elfosabi
, eflags
;
2681 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2683 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2688 /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the
2689 file are conforming to the base specification for that machine
2690 (there are no OS-specific extensions). In order to determine the
2691 real OS in use we must look for OS notes that have been added. */
2692 bfd_map_over_sections (abfd
,
2693 generic_elf_osabi_sniff_abi_tag_sections
,
2695 if (osabi
== GDB_OSABI_UNKNOWN
)
2697 /* Existing ARM tools don't set this field, so look at the EI_FLAGS
2698 field for more information. */
2699 eflags
= EF_ARM_EABI_VERSION(elf_elfheader(abfd
)->e_flags
);
2702 case EF_ARM_EABI_VER1
:
2703 osabi
= GDB_OSABI_ARM_EABI_V1
;
2706 case EF_ARM_EABI_VER2
:
2707 osabi
= GDB_OSABI_ARM_EABI_V2
;
2710 case EF_ARM_EABI_UNKNOWN
:
2711 /* Assume GNU tools. */
2712 osabi
= GDB_OSABI_ARM_APCS
;
2716 internal_error (__FILE__
, __LINE__
,
2717 "arm_elf_osabi_sniffer: Unknown ARM EABI "
2718 "version 0x%x", eflags
);
2724 /* GNU tools use this value. Check note sections in this case,
2726 bfd_map_over_sections (abfd
,
2727 generic_elf_osabi_sniff_abi_tag_sections
,
2729 if (osabi
== GDB_OSABI_UNKNOWN
)
2731 /* Assume APCS ABI. */
2732 osabi
= GDB_OSABI_ARM_APCS
;
2736 case ELFOSABI_FREEBSD
:
2737 osabi
= GDB_OSABI_FREEBSD_ELF
;
2740 case ELFOSABI_NETBSD
:
2741 osabi
= GDB_OSABI_NETBSD_ELF
;
2744 case ELFOSABI_LINUX
:
2745 osabi
= GDB_OSABI_LINUX
;
2753 /* Initialize the current architecture based on INFO. If possible,
2754 re-use an architecture from ARCHES, which is a list of
2755 architectures already created during this debugging session.
2757 Called e.g. at program startup, when reading a core file, and when
2758 reading a binary file. */
2760 static struct gdbarch
*
2761 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2763 struct gdbarch_tdep
*tdep
;
2764 struct gdbarch
*gdbarch
;
2766 /* Try to deterimine the ABI of the object we are loading. */
2768 if (info
.abfd
!= NULL
&& info
.osabi
== GDB_OSABI_UNKNOWN
)
2770 switch (bfd_get_flavour (info
.abfd
))
2772 case bfd_target_aout_flavour
:
2773 /* Assume it's an old APCS-style ABI. */
2774 info
.osabi
= GDB_OSABI_ARM_APCS
;
2777 case bfd_target_coff_flavour
:
2778 /* Assume it's an old APCS-style ABI. */
2780 info
.osabi
= GDB_OSABI_ARM_APCS
;
2784 /* Leave it as "unknown". */
2789 /* If there is already a candidate, use it. */
2790 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2792 return arches
->gdbarch
;
2794 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
2795 gdbarch
= gdbarch_alloc (&info
, tdep
);
2797 /* We used to default to FPA for generic ARM, but almost nobody uses that
2798 now, and we now provide a way for the user to force the model. So
2799 default to the most useful variant. */
2800 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
2803 switch (info
.byte_order
)
2805 case BFD_ENDIAN_BIG
:
2806 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
2807 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
2808 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
2809 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
2813 case BFD_ENDIAN_LITTLE
:
2814 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
2815 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
2816 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
2817 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
2822 internal_error (__FILE__
, __LINE__
,
2823 "arm_gdbarch_init: bad byte order for float format");
2826 /* On ARM targets char defaults to unsigned. */
2827 set_gdbarch_char_signed (gdbarch
, 0);
2829 /* This should be low enough for everything. */
2830 tdep
->lowest_pc
= 0x20;
2831 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
2833 set_gdbarch_deprecated_call_dummy_words (gdbarch
, arm_call_dummy_words
);
2834 set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch
, 0);
2836 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
2838 /* Frame handling. */
2839 set_gdbarch_unwind_dummy_id (gdbarch
, arm_unwind_dummy_id
);
2840 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
2841 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
2843 set_gdbarch_frameless_function_invocation
2844 (gdbarch
, arm_frameless_function_invocation
);
2845 set_gdbarch_frame_args_skip (gdbarch
, 0);
2847 frame_base_set_default (gdbarch
, &arm_normal_base
);
2849 /* Address manipulation. */
2850 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
2851 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
2853 /* Offset from address of function to start of its code. */
2854 set_gdbarch_function_start_offset (gdbarch
, 0);
2856 /* Advance PC across function entry code. */
2857 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
2859 /* Get the PC when a frame might not be available. */
2860 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
, arm_saved_pc_after_call
);
2862 /* The stack grows downward. */
2863 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2865 /* Breakpoint manipulation. */
2866 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
2867 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2869 /* Information about registers, etc. */
2870 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
2871 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
2872 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
2873 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
2874 set_gdbarch_deprecated_register_byte (gdbarch
, arm_register_byte
);
2875 set_gdbarch_deprecated_register_bytes (gdbarch
,
2876 (NUM_GREGS
* INT_REGISTER_RAW_SIZE
2877 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
2878 + NUM_SREGS
* STATUS_REGISTER_SIZE
));
2879 set_gdbarch_num_regs (gdbarch
, NUM_GREGS
+ NUM_FREGS
+ NUM_SREGS
);
2880 set_gdbarch_deprecated_register_raw_size (gdbarch
, arm_register_raw_size
);
2881 set_gdbarch_deprecated_register_virtual_size (gdbarch
, arm_register_virtual_size
);
2882 set_gdbarch_deprecated_max_register_raw_size (gdbarch
, FP_REGISTER_RAW_SIZE
);
2883 set_gdbarch_deprecated_max_register_virtual_size (gdbarch
, FP_REGISTER_VIRTUAL_SIZE
);
2884 set_gdbarch_deprecated_register_virtual_type (gdbarch
, arm_register_type
);
2886 /* Internal <-> external register number maps. */
2887 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
2889 /* Integer registers are 4 bytes. */
2890 set_gdbarch_deprecated_register_size (gdbarch
, 4);
2891 set_gdbarch_register_name (gdbarch
, arm_register_name
);
2893 /* Returning results. */
2894 set_gdbarch_extract_return_value (gdbarch
, arm_extract_return_value
);
2895 set_gdbarch_store_return_value (gdbarch
, arm_store_return_value
);
2896 set_gdbarch_use_struct_convention (gdbarch
, arm_use_struct_convention
);
2897 set_gdbarch_extract_struct_value_address (gdbarch
,
2898 arm_extract_struct_value_address
);
2900 /* Single stepping. */
2901 /* XXX For an RDI target we should ask the target if it can single-step. */
2902 set_gdbarch_software_single_step (gdbarch
, arm_software_single_step
);
2905 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
2907 /* Minsymbol frobbing. */
2908 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
2909 set_gdbarch_coff_make_msymbol_special (gdbarch
,
2910 arm_coff_make_msymbol_special
);
2912 /* Hook in the ABI-specific overrides, if they have been registered. */
2913 gdbarch_init_osabi (info
, gdbarch
);
2915 /* Add some default predicates. */
2916 frame_unwind_append_sniffer (gdbarch
, arm_sigtramp_unwind_sniffer
);
2917 frame_unwind_append_sniffer (gdbarch
, arm_prologue_unwind_sniffer
);
2919 /* Now we have tuned the configuration, set a few final things,
2920 based on what the OS ABI has told us. */
2922 if (tdep
->jb_pc
>= 0)
2923 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
2925 /* Floating point sizes and format. */
2926 switch (info
.byte_order
)
2928 case BFD_ENDIAN_BIG
:
2929 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
2930 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_big
);
2931 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
2935 case BFD_ENDIAN_LITTLE
:
2936 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
2937 arm_set_fp (gdbarch
);
2941 internal_error (__FILE__
, __LINE__
,
2942 "arm_gdbarch_init: bad byte order for float format");
2949 arm_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
2951 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2956 fprintf_unfiltered (file
, "arm_dump_tdep: Lowest pc = 0x%lx",
2957 (unsigned long) tdep
->lowest_pc
);
2961 arm_init_abi_eabi_v1 (struct gdbarch_info info
,
2962 struct gdbarch
*gdbarch
)
2968 arm_init_abi_eabi_v2 (struct gdbarch_info info
,
2969 struct gdbarch
*gdbarch
)
2975 arm_init_abi_apcs (struct gdbarch_info info
,
2976 struct gdbarch
*gdbarch
)
2981 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
2984 _initialize_arm_tdep (void)
2986 struct ui_file
*stb
;
2988 struct cmd_list_element
*new_set
, *new_show
;
2989 const char *setname
;
2990 const char *setdesc
;
2991 const char **regnames
;
2993 static char *helptext
;
2995 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
2997 /* Register an ELF OS ABI sniffer for ARM binaries. */
2998 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
2999 bfd_target_elf_flavour
,
3000 arm_elf_osabi_sniffer
);
3002 /* Register some ABI variants for embedded systems. */
3003 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_EABI_V1
,
3004 arm_init_abi_eabi_v1
);
3005 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_EABI_V2
,
3006 arm_init_abi_eabi_v2
);
3007 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_APCS
,
3010 /* Get the number of possible sets of register names defined in opcodes. */
3011 num_disassembly_options
= get_arm_regname_num_options ();
3013 /* Add root prefix command for all "set arm"/"show arm" commands. */
3014 add_prefix_cmd ("arm", no_class
, set_arm_command
,
3015 "Various ARM-specific commands.",
3016 &setarmcmdlist
, "set arm ", 0, &setlist
);
3018 add_prefix_cmd ("arm", no_class
, show_arm_command
,
3019 "Various ARM-specific commands.",
3020 &showarmcmdlist
, "show arm ", 0, &showlist
);
3022 /* Sync the opcode insn printer with our register viewer. */
3023 parse_arm_disassembler_option ("reg-names-std");
3025 /* Begin creating the help text. */
3026 stb
= mem_fileopen ();
3027 fprintf_unfiltered (stb
, "Set the disassembly style.\n"
3028 "The valid values are:\n");
3030 /* Initialize the array that will be passed to add_set_enum_cmd(). */
3031 valid_disassembly_styles
3032 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
3033 for (i
= 0; i
< num_disassembly_options
; i
++)
3035 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
3036 valid_disassembly_styles
[i
] = setname
;
3037 fprintf_unfiltered (stb
, "%s - %s\n", setname
,
3039 /* Copy the default names (if found) and synchronize disassembler. */
3040 if (!strcmp (setname
, "std"))
3042 disassembly_style
= setname
;
3044 for (j
= 0; j
< numregs
; j
++)
3045 arm_register_names
[j
] = (char *) regnames
[j
];
3046 set_arm_regname_option (i
);
3049 /* Mark the end of valid options. */
3050 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
3052 /* Finish the creation of the help text. */
3053 fprintf_unfiltered (stb
, "The default is \"std\".");
3054 helptext
= ui_file_xstrdup (stb
, &length
);
3055 ui_file_delete (stb
);
3057 /* Add the deprecated disassembly-flavor command. */
3058 new_set
= add_set_enum_cmd ("disassembly-flavor", no_class
,
3059 valid_disassembly_styles
,
3063 set_cmd_sfunc (new_set
, set_disassembly_style_sfunc
);
3064 deprecate_cmd (new_set
, "set arm disassembly");
3065 deprecate_cmd (add_show_from_set (new_set
, &showlist
),
3066 "show arm disassembly");
3068 /* And now add the new interface. */
3069 new_set
= add_set_enum_cmd ("disassembler", no_class
,
3070 valid_disassembly_styles
, &disassembly_style
,
3071 helptext
, &setarmcmdlist
);
3073 set_cmd_sfunc (new_set
, set_disassembly_style_sfunc
);
3074 add_show_from_set (new_set
, &showarmcmdlist
);
3076 add_setshow_cmd_full ("apcs32", no_class
,
3077 var_boolean
, (char *) &arm_apcs_32
,
3078 "Set usage of ARM 32-bit mode.",
3079 "Show usage of ARM 32-bit mode.",
3081 &setlist
, &showlist
, &new_set
, &new_show
);
3082 deprecate_cmd (new_set
, "set arm apcs32");
3083 deprecate_cmd (new_show
, "show arm apcs32");
3085 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
3086 "Set usage of ARM 32-bit mode. "
3087 "When off, a 26-bit PC will be used.",
3088 "Show usage of ARM 32-bit mode. "
3089 "When off, a 26-bit PC will be used.",
3091 &setarmcmdlist
, &showarmcmdlist
);
3093 /* Add a command to allow the user to force the FPU model. */
3094 new_set
= add_set_enum_cmd
3095 ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
3096 "Set the floating point type.\n"
3097 "auto - Determine the FP typefrom the OS-ABI.\n"
3098 "softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n"
3099 "fpa - FPA co-processor (GCC compiled).\n"
3100 "softvfp - Software FP with pure-endian doubles.\n"
3101 "vfp - VFP co-processor.",
3103 set_cmd_sfunc (new_set
, set_fp_model_sfunc
);
3104 set_cmd_sfunc (add_show_from_set (new_set
, &showarmcmdlist
), show_fp_model
);
3106 /* Add the deprecated "othernames" command. */
3107 deprecate_cmd (add_com ("othernames", class_obscure
, arm_othernames
,
3108 "Switch to the next set of register names."),
3109 "set arm disassembly");
3111 /* Debugging flag. */
3112 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
3113 "Set ARM debugging. "
3114 "When on, arm-specific debugging is enabled.",
3115 "Show ARM debugging. "
3116 "When on, arm-specific debugging is enabled.",
3118 &setdebuglist
, &showdebuglist
);