1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 #include <ctype.h> /* XXX for isupper () */
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register flavors. */
35 #include "arch-utils.h"
36 #include "solib-svr4.h"
41 #include "coff/internal.h"
43 /* Each OS has a different mechanism for accessing the various
44 registers stored in the sigcontext structure.
46 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
47 function pointer) which may be used to determine the addresses
48 of the various saved registers in the sigcontext structure.
50 For the ARM target, there are three parameters to this function.
51 The first is the pc value of the frame under consideration, the
52 second the stack pointer of this frame, and the last is the
53 register number to fetch.
55 If the tm.h file does not define this macro, then it's assumed that
56 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
59 When it comes time to multi-arching this code, see the identically
60 named machinery in ia64-tdep.c for an example of how it could be
61 done. It should not be necessary to modify the code below where
62 this macro is used. */
64 #ifdef SIGCONTEXT_REGISTER_ADDRESS
65 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
66 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
69 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
70 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
73 /* Macros for setting and testing a bit in a minimal symbol that marks
74 it as Thumb function. The MSB of the minimal symbol's "info" field
75 is used for this purpose. This field is already being used to store
76 the symbol size, so the assumption is that the symbol size cannot
79 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
80 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol.
81 MSYMBOL_SIZE Returns the size of the minimal symbol,
82 i.e. the "info" field with the "special" bit
85 #define MSYMBOL_SET_SPECIAL(msym) \
86 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
89 #define MSYMBOL_IS_SPECIAL(msym) \
90 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
92 #define MSYMBOL_SIZE(msym) \
93 ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
95 /* Number of different reg name sets (options). */
96 static int num_flavor_options
;
98 /* We have more registers than the disassembler as gdb can print the value
99 of special registers as well.
100 The general register names are overwritten by whatever is being used by
101 the disassembler at the moment. We also adjust the case of cpsr and fps. */
103 /* Initial value: Register names used in ARM's ISA documentation. */
104 static char * arm_register_name_strings
[] =
105 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
106 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
107 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
108 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
109 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
110 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
111 "fps", "cpsr" }; /* 24 25 */
112 static char **arm_register_names
= arm_register_name_strings
;
114 /* Valid register name flavors. */
115 static const char **valid_flavors
;
117 /* Disassembly flavor to use. Default to "std" register names. */
118 static const char *disassembly_flavor
;
119 static int current_option
; /* Index to that option in the opcodes table. */
121 /* This is used to keep the bfd arch_info in sync with the disassembly
123 static void set_disassembly_flavor_sfunc(char *, int,
124 struct cmd_list_element
*);
125 static void set_disassembly_flavor (void);
127 static void convert_from_extended (void *ptr
, void *dbl
);
129 /* Define other aspects of the stack frame. We keep the offsets of
130 all saved registers, 'cause we need 'em a lot! We also keep the
131 current size of the stack frame, and the offset of the frame
132 pointer from the stack pointer (for frameless functions, and when
133 we're still in the prologue of a function with a frame) */
135 struct frame_extra_info
142 /* Addresses for calling Thumb functions have the bit 0 set.
143 Here are some macros to test, set, or clear bit 0 of addresses. */
144 #define IS_THUMB_ADDR(addr) ((addr) & 1)
145 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
146 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
149 arm_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*thisframe
)
151 return (chain
!= 0 && (FRAME_SAVED_PC (thisframe
) >= LOWEST_PC
));
154 /* Set to true if the 32-bit mode is in use. */
158 /* Flag set by arm_fix_call_dummy that tells whether the target
159 function is a Thumb function. This flag is checked by
160 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
161 its use in valops.c) to pass the function address as an additional
164 static int target_is_thumb
;
166 /* Flag set by arm_fix_call_dummy that tells whether the calling
167 function is a Thumb function. This flag is checked by
168 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
170 static int caller_is_thumb
;
172 /* Determine if the program counter specified in MEMADDR is in a Thumb
176 arm_pc_is_thumb (CORE_ADDR memaddr
)
178 struct minimal_symbol
*sym
;
180 /* If bit 0 of the address is set, assume this is a Thumb address. */
181 if (IS_THUMB_ADDR (memaddr
))
184 /* Thumb functions have a "special" bit set in minimal symbols. */
185 sym
= lookup_minimal_symbol_by_pc (memaddr
);
188 return (MSYMBOL_IS_SPECIAL (sym
));
196 /* Determine if the program counter specified in MEMADDR is in a call
197 dummy being called from a Thumb function. */
200 arm_pc_is_thumb_dummy (CORE_ADDR memaddr
)
202 CORE_ADDR sp
= read_sp ();
204 /* FIXME: Until we switch for the new call dummy macros, this heuristic
205 is the best we can do. We are trying to determine if the pc is on
206 the stack, which (hopefully) will only happen in a call dummy.
207 We hope the current stack pointer is not so far alway from the dummy
208 frame location (true if we have not pushed large data structures or
209 gone too many levels deep) and that our 1024 is not enough to consider
210 code regions as part of the stack (true for most practical purposes) */
211 if (PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 1024))
212 return caller_is_thumb
;
217 /* Remove useless bits from addresses in a running program. */
219 arm_addr_bits_remove (CORE_ADDR val
)
221 if (arm_pc_is_thumb (val
))
222 return (val
& (arm_apcs_32
? 0xfffffffe : 0x03fffffe));
224 return (val
& (arm_apcs_32
? 0xfffffffc : 0x03fffffc));
227 /* When reading symbols, we need to zap the low bit of the address,
228 which may be set to 1 for Thumb functions. */
230 arm_smash_text_address (CORE_ADDR val
)
235 /* Immediately after a function call, return the saved pc. Can't
236 always go through the frames for this because on some machines the
237 new frame is not set up until the new function executes some
241 arm_saved_pc_after_call (struct frame_info
*frame
)
243 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM
));
246 /* Determine whether the function invocation represented by FI has a
247 frame on the stack associated with it. If it does return zero,
248 otherwise return 1. */
251 arm_frameless_function_invocation (struct frame_info
*fi
)
253 CORE_ADDR func_start
, after_prologue
;
256 /* Sometimes we have functions that do a little setup (like saving the
257 vN registers with the stmdb instruction, but DO NOT set up a frame.
258 The symbol table will report this as a prologue. However, it is
259 important not to try to parse these partial frames as frames, or we
260 will get really confused.
262 So I will demand 3 instructions between the start & end of the
263 prologue before I call it a real prologue, i.e. at least
268 func_start
= (get_pc_function_start ((fi
)->pc
) + FUNCTION_START_OFFSET
);
269 after_prologue
= SKIP_PROLOGUE (func_start
);
271 /* There are some frameless functions whose first two instructions
272 follow the standard APCS form, in which case after_prologue will
273 be func_start + 8. */
275 frameless
= (after_prologue
< func_start
+ 12);
279 /* The address of the arguments in the frame. */
281 arm_frame_args_address (struct frame_info
*fi
)
286 /* The address of the local variables in the frame. */
288 arm_frame_locals_address (struct frame_info
*fi
)
293 /* The number of arguments being passed in the frame. */
295 arm_frame_num_args (struct frame_info
*fi
)
297 /* We have no way of knowing. */
301 /* A typical Thumb prologue looks like this:
305 Sometimes the latter instruction may be replaced by:
313 or, on tpcs, like this:
320 There is always one instruction of three classes:
325 When we have found at least one of each class we are done with the prolog.
326 Note that the "sub sp, #NN" before the push does not count.
330 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
332 CORE_ADDR current_pc
;
333 int findmask
= 0; /* findmask:
334 bit 0 - push { rlist }
335 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
336 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
339 for (current_pc
= pc
; current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40; current_pc
+= 2)
341 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
343 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
345 findmask
|= 1; /* push found */
347 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
349 if ((findmask
& 1) == 0) /* before push ? */
352 findmask
|= 4; /* add/sub sp found */
354 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
356 findmask
|= 2; /* setting of r7 found */
358 else if (insn
== 0x466f) /* mov r7, sp */
360 findmask
|= 2; /* setting of r7 found */
362 else if (findmask
== (4+2+1))
364 break; /* We have found one of each type of prologue instruction */
367 continue; /* something in the prolog that we don't care about or some
368 instruction from outside the prolog scheduled here for optimization */
374 /* Advance the PC across any function entry prologue instructions to reach
377 The APCS (ARM Procedure Call Standard) defines the following
381 [stmfd sp!, {a1,a2,a3,a4}]
382 stmfd sp!, {...,fp,ip,lr,pc}
383 [stfe f7, [sp, #-12]!]
384 [stfe f6, [sp, #-12]!]
385 [stfe f5, [sp, #-12]!]
386 [stfe f4, [sp, #-12]!]
387 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
390 arm_skip_prologue (CORE_ADDR pc
)
394 CORE_ADDR func_addr
, func_end
;
396 struct symtab_and_line sal
;
398 /* See what the symbol table says. */
400 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
404 /* Found a function. */
405 sym
= lookup_symbol (func_name
, NULL
, VAR_NAMESPACE
, NULL
, NULL
);
406 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
408 /* Don't use this trick for assembly source files. */
409 sal
= find_pc_line (func_addr
, 0);
410 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
415 /* Check if this is Thumb code. */
416 if (arm_pc_is_thumb (pc
))
417 return thumb_skip_prologue (pc
, func_end
);
419 /* Can't find the prologue end in the symbol table, try it the hard way
420 by disassembling the instructions. */
422 inst
= read_memory_integer (skip_pc
, 4);
423 if (inst
!= 0xe1a0c00d) /* mov ip, sp */
427 inst
= read_memory_integer (skip_pc
, 4);
428 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
431 inst
= read_memory_integer (skip_pc
, 4);
434 if ((inst
& 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */
438 inst
= read_memory_integer (skip_pc
, 4);
440 /* Any insns after this point may float into the code, if it makes
441 for better instruction scheduling, so we skip them only if we
442 find them, but still consdier the function to be frame-ful. */
444 /* We may have either one sfmfd instruction here, or several stfe
445 insns, depending on the version of floating point code we
447 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
450 inst
= read_memory_integer (skip_pc
, 4);
454 while ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
457 inst
= read_memory_integer (skip_pc
, 4);
461 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
467 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
468 This function decodes a Thumb function prologue to determine:
469 1) the size of the stack frame
470 2) which registers are saved on it
471 3) the offsets of saved regs
472 4) the offset from the stack pointer to the frame pointer
473 This information is stored in the "extra" fields of the frame_info.
475 A typical Thumb function prologue would create this stack frame
476 (offsets relative to FP)
477 old SP -> 24 stack parameters
480 R7 -> 0 local variables (16 bytes)
481 SP -> -12 additional stack space (12 bytes)
482 The frame size would thus be 36 bytes, and the frame offset would be
483 12 bytes. The frame register is R7.
485 The comments for thumb_skip_prolog() describe the algorithm we use to detect
486 the end of the prolog */
490 thumb_scan_prologue (struct frame_info
*fi
)
492 CORE_ADDR prologue_start
;
493 CORE_ADDR prologue_end
;
494 CORE_ADDR current_pc
;
495 int saved_reg
[16]; /* which register has been copied to register n? */
496 int findmask
= 0; /* findmask:
497 bit 0 - push { rlist }
498 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
499 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
503 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
505 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
507 if (sal
.line
== 0) /* no line info, use current PC */
508 prologue_end
= fi
->pc
;
509 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
510 prologue_end
= sal
.end
; /* (probably means no prologue) */
513 prologue_end
= prologue_start
+ 40; /* We're in the boondocks: allow for */
514 /* 16 pushes, an add, and "mv fp,sp" */
516 prologue_end
= min (prologue_end
, fi
->pc
);
518 /* Initialize the saved register map. When register H is copied to
519 register L, we will put H in saved_reg[L]. */
520 for (i
= 0; i
< 16; i
++)
523 /* Search the prologue looking for instructions that set up the
524 frame pointer, adjust the stack pointer, and save registers.
525 Do this until all basic prolog instructions are found. */
527 fi
->extra_info
->framesize
= 0;
528 for (current_pc
= prologue_start
;
529 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
536 insn
= read_memory_unsigned_integer (current_pc
, 2);
538 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
541 findmask
|= 1; /* push found */
542 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
543 whether to save LR (R14). */
544 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
546 /* Calculate offsets of saved R0-R7 and LR. */
547 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
548 if (mask
& (1 << regno
))
550 fi
->extra_info
->framesize
+= 4;
551 fi
->saved_regs
[saved_reg
[regno
]] =
552 -(fi
->extra_info
->framesize
);
553 saved_reg
[regno
] = regno
; /* reset saved register map */
556 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
558 if ((findmask
& 1) == 0) /* before push ? */
561 findmask
|= 4; /* add/sub sp found */
563 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
564 if (insn
& 0x80) /* is it signed? (==subtracting) */
566 fi
->extra_info
->frameoffset
+= offset
;
569 fi
->extra_info
->framesize
-= offset
;
571 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
573 findmask
|= 2; /* setting of r7 found */
574 fi
->extra_info
->framereg
= THUMB_FP_REGNUM
;
575 /* get scaled offset */
576 fi
->extra_info
->frameoffset
= (insn
& 0xff) << 2;
578 else if (insn
== 0x466f) /* mov r7, sp */
580 findmask
|= 2; /* setting of r7 found */
581 fi
->extra_info
->framereg
= THUMB_FP_REGNUM
;
582 fi
->extra_info
->frameoffset
= 0;
583 saved_reg
[THUMB_FP_REGNUM
] = ARM_SP_REGNUM
;
585 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
587 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
588 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
589 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
592 continue; /* something in the prolog that we don't care about or some
593 instruction from outside the prolog scheduled here for optimization */
597 /* Check if prologue for this frame's PC has already been scanned. If
598 it has, copy the relevant information about that prologue and
599 return non-zero. Otherwise do not copy anything and return zero.
601 The information saved in the cache includes:
602 * the frame register number;
603 * the size of the stack frame;
604 * the offsets of saved regs (relative to the old SP); and
605 * the offset from the stack pointer to the frame pointer
607 The cache contains only one entry, since this is adequate for the
608 typical sequence of prologue scan requests we get. When performing
609 a backtrace, GDB will usually ask to scan the same function twice
610 in a row (once to get the frame chain, and once to fill in the
611 extra frame information). */
613 static struct frame_info prologue_cache
;
616 check_prologue_cache (struct frame_info
*fi
)
620 if (fi
->pc
== prologue_cache
.pc
)
622 fi
->extra_info
->framereg
= prologue_cache
.extra_info
->framereg
;
623 fi
->extra_info
->framesize
= prologue_cache
.extra_info
->framesize
;
624 fi
->extra_info
->frameoffset
= prologue_cache
.extra_info
->frameoffset
;
625 for (i
= 0; i
< NUM_REGS
+ NUM_PSEUDO_REGS
; i
++)
626 fi
->saved_regs
[i
] = prologue_cache
.saved_regs
[i
];
634 /* Copy the prologue information from fi to the prologue cache. */
637 save_prologue_cache (struct frame_info
*fi
)
641 prologue_cache
.pc
= fi
->pc
;
642 prologue_cache
.extra_info
->framereg
= fi
->extra_info
->framereg
;
643 prologue_cache
.extra_info
->framesize
= fi
->extra_info
->framesize
;
644 prologue_cache
.extra_info
->frameoffset
= fi
->extra_info
->frameoffset
;
646 for (i
= 0; i
< NUM_REGS
+ NUM_PSEUDO_REGS
; i
++)
647 prologue_cache
.saved_regs
[i
] = fi
->saved_regs
[i
];
651 /* This function decodes an ARM function prologue to determine:
652 1) the size of the stack frame
653 2) which registers are saved on it
654 3) the offsets of saved regs
655 4) the offset from the stack pointer to the frame pointer
656 This information is stored in the "extra" fields of the frame_info.
658 There are two basic forms for the ARM prologue. The fixed argument
659 function call will look like:
662 stmfd sp!, {fp, ip, lr, pc}
666 Which would create this stack frame (offsets relative to FP):
667 IP -> 4 (caller's stack)
668 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
669 -4 LR (return address in caller)
670 -8 IP (copy of caller's SP)
672 SP -> -28 Local variables
674 The frame size would thus be 32 bytes, and the frame offset would be
675 28 bytes. The stmfd call can also save any of the vN registers it
676 plans to use, which increases the frame size accordingly.
678 Note: The stored PC is 8 off of the STMFD instruction that stored it
679 because the ARM Store instructions always store PC + 8 when you read
682 A variable argument function call will look like:
685 stmfd sp!, {a1, a2, a3, a4}
686 stmfd sp!, {fp, ip, lr, pc}
689 Which would create this stack frame (offsets relative to FP):
690 IP -> 20 (caller's stack)
695 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
696 -4 LR (return address in caller)
697 -8 IP (copy of caller's SP)
699 SP -> -28 Local variables
701 The frame size would thus be 48 bytes, and the frame offset would be
704 There is another potential complication, which is that the optimizer
705 will try to separate the store of fp in the "stmfd" instruction from
706 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
707 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
709 Also, note, the original version of the ARM toolchain claimed that there
712 instruction at the end of the prologue. I have never seen GCC produce
713 this, and the ARM docs don't mention it. We still test for it below in
719 arm_scan_prologue (struct frame_info
*fi
)
721 int regno
, sp_offset
, fp_offset
;
722 LONGEST return_value
;
723 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
725 /* Check if this function is already in the cache of frame information. */
726 if (check_prologue_cache (fi
))
729 /* Assume there is no frame until proven otherwise. */
730 fi
->extra_info
->framereg
= ARM_SP_REGNUM
;
731 fi
->extra_info
->framesize
= 0;
732 fi
->extra_info
->frameoffset
= 0;
734 /* Check for Thumb prologue. */
735 if (arm_pc_is_thumb (fi
->pc
))
737 thumb_scan_prologue (fi
);
738 save_prologue_cache (fi
);
742 /* Find the function prologue. If we can't find the function in
743 the symbol table, peek in the stack frame to find the PC. */
744 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
746 /* One way to find the end of the prologue (which works well
747 for unoptimized code) is to do the following:
749 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
752 prologue_end = fi->pc;
753 else if (sal.end < prologue_end)
754 prologue_end = sal.end;
756 This mechanism is very accurate so long as the optimizer
757 doesn't move any instructions from the function body into the
758 prologue. If this happens, sal.end will be the last
759 instruction in the first hunk of prologue code just before
760 the first instruction that the scheduler has moved from
761 the body to the prologue.
763 In order to make sure that we scan all of the prologue
764 instructions, we use a slightly less accurate mechanism which
765 may scan more than necessary. To help compensate for this
766 lack of accuracy, the prologue scanning loop below contains
767 several clauses which'll cause the loop to terminate early if
768 an implausible prologue instruction is encountered.
774 is a suitable endpoint since it accounts for the largest
775 possible prologue plus up to five instructions inserted by
778 if (prologue_end
> prologue_start
+ 64)
780 prologue_end
= prologue_start
+ 64; /* See above. */
785 /* Get address of the stmfd in the prologue of the callee; the saved
786 PC is the address of the stmfd + 8. */
787 if (!safe_read_memory_integer (fi
->frame
, 4, &return_value
))
791 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
792 prologue_end
= prologue_start
+ 64; /* See above. */
796 /* Now search the prologue looking for instructions that set up the
797 frame pointer, adjust the stack pointer, and save registers.
799 Be careful, however, and if it doesn't look like a prologue,
800 don't try to scan it. If, for instance, a frameless function
801 begins with stmfd sp!, then we will tell ourselves there is
802 a frame, which will confuse stack traceback, as well ad"finish"
803 and other operations that rely on a knowledge of the stack
806 In the APCS, the prologue should start with "mov ip, sp" so
807 if we don't see this as the first insn, we will stop. [Note:
808 This doesn't seem to be true any longer, so it's now an optional
809 part of the prologue. - Kevin Buettner, 2001-11-20] */
811 sp_offset
= fp_offset
= 0;
813 if (read_memory_unsigned_integer (prologue_start
, 4)
814 == 0xe1a0c00d) /* mov ip, sp */
815 current_pc
= prologue_start
+ 4;
817 current_pc
= prologue_start
;
819 for (; current_pc
< prologue_end
; current_pc
+= 4)
821 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
823 if ((insn
& 0xffff0000) == 0xe92d0000)
824 /* stmfd sp!, {..., fp, ip, lr, pc}
826 stmfd sp!, {a1, a2, a3, a4} */
828 int mask
= insn
& 0xffff;
830 /* Calculate offsets of saved registers. */
831 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
832 if (mask
& (1 << regno
))
835 fi
->saved_regs
[regno
] = sp_offset
;
838 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
840 unsigned imm
= insn
& 0xff; /* immediate value */
841 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
842 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
844 fi
->extra_info
->framereg
= ARM_FP_REGNUM
;
846 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
848 unsigned imm
= insn
& 0xff; /* immediate value */
849 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
850 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
853 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
856 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
857 fi
->saved_regs
[regno
] = sp_offset
;
859 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
862 unsigned int fp_start_reg
, fp_bound_reg
;
864 if ((insn
& 0x800) == 0x800) /* N0 is set */
866 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
873 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
879 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
880 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
881 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
884 fi
->saved_regs
[fp_start_reg
++] = sp_offset
;
887 else if ((insn
& 0xf0000000) != 0xe0000000)
888 break; /* Condition not true, exit early */
889 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
890 break; /* Don't scan past a block load */
892 /* The optimizer might shove anything into the prologue,
893 so we just skip what we don't recognize. */
897 /* The frame size is just the negative of the offset (from the original SP)
898 of the last thing thing we pushed on the stack. The frame offset is
899 [new FP] - [new SP]. */
900 fi
->extra_info
->framesize
= -sp_offset
;
901 if (fi
->extra_info
->framereg
== ARM_FP_REGNUM
)
902 fi
->extra_info
->frameoffset
= fp_offset
- sp_offset
;
904 fi
->extra_info
->frameoffset
= 0;
906 save_prologue_cache (fi
);
909 /* Find REGNUM on the stack. Otherwise, it's in an active register.
910 One thing we might want to do here is to check REGNUM against the
911 clobber mask, and somehow flag it as invalid if it isn't saved on
912 the stack somewhere. This would provide a graceful failure mode
913 when trying to get the value of caller-saves registers for an inner
917 arm_find_callers_reg (struct frame_info
*fi
, int regnum
)
919 for (; fi
; fi
= fi
->next
)
921 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
922 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
923 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
926 if (fi
->saved_regs
[regnum
] != 0)
927 return read_memory_integer (fi
->saved_regs
[regnum
],
928 REGISTER_RAW_SIZE (regnum
));
929 return read_register (regnum
);
931 /* Function: frame_chain Given a GDB frame, determine the address of
932 the calling function's frame. This will be used to create a new
933 GDB frame struct, and then INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC
934 will be called for the new frame. For ARM, we save the frame size
935 when we initialize the frame_info. */
938 arm_frame_chain (struct frame_info
*fi
)
940 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
941 CORE_ADDR fn_start
, callers_pc
, fp
;
943 /* is this a dummy frame? */
944 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
945 return fi
->frame
; /* dummy frame same as caller's frame */
947 /* is caller-of-this a dummy frame? */
948 callers_pc
= FRAME_SAVED_PC (fi
); /* find out who called us: */
949 fp
= arm_find_callers_reg (fi
, ARM_FP_REGNUM
);
950 if (PC_IN_CALL_DUMMY (callers_pc
, fp
, fp
))
951 return fp
; /* dummy frame's frame may bear no relation to ours */
953 if (find_pc_partial_function (fi
->pc
, 0, &fn_start
, 0))
954 if (fn_start
== entry_point_address ())
955 return 0; /* in _start fn, don't chain further */
957 CORE_ADDR caller_pc
, fn_start
;
958 int framereg
= fi
->extra_info
->framereg
;
960 if (fi
->pc
< LOWEST_PC
)
963 /* If the caller is the startup code, we're at the end of the chain. */
964 caller_pc
= FRAME_SAVED_PC (fi
);
965 if (find_pc_partial_function (caller_pc
, 0, &fn_start
, 0))
966 if (fn_start
== entry_point_address ())
969 /* If the caller is Thumb and the caller is ARM, or vice versa,
970 the frame register of the caller is different from ours.
971 So we must scan the prologue of the caller to determine its
972 frame register number. */
973 /* XXX Fixme, we should try to do this without creating a temporary
975 if (arm_pc_is_thumb (caller_pc
) != arm_pc_is_thumb (fi
->pc
))
977 struct frame_info caller_fi
;
978 struct cleanup
*old_chain
;
980 /* Create a temporary frame suitable for scanning the caller's
982 memset (&caller_fi
, 0, sizeof (caller_fi
));
983 caller_fi
.extra_info
= (struct frame_extra_info
*)
984 xcalloc (1, sizeof (struct frame_extra_info
));
985 old_chain
= make_cleanup (xfree
, caller_fi
.extra_info
);
986 caller_fi
.saved_regs
= (CORE_ADDR
*)
987 xcalloc (1, SIZEOF_FRAME_SAVED_REGS
);
988 make_cleanup (xfree
, caller_fi
.saved_regs
);
990 /* Now, scan the prologue and obtain the frame register. */
991 caller_fi
.pc
= caller_pc
;
992 arm_scan_prologue (&caller_fi
);
993 framereg
= caller_fi
.extra_info
->framereg
;
995 /* Deallocate the storage associated with the temporary frame
997 do_cleanups (old_chain
);
1000 /* If the caller used a frame register, return its value.
1001 Otherwise, return the caller's stack pointer. */
1002 if (framereg
== ARM_FP_REGNUM
|| framereg
== THUMB_FP_REGNUM
)
1003 return arm_find_callers_reg (fi
, framereg
);
1005 return fi
->frame
+ fi
->extra_info
->framesize
;
1008 /* This function actually figures out the frame address for a given pc
1009 and sp. This is tricky because we sometimes don't use an explicit
1010 frame pointer, and the previous stack pointer isn't necessarily
1011 recorded on the stack. The only reliable way to get this info is
1012 to examine the prologue. FROMLEAF is a little confusing, it means
1013 this is the next frame up the chain AFTER a frameless function. If
1014 this is true, then the frame value for this frame is still in the
1018 arm_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1023 if (fi
->saved_regs
== NULL
)
1024 frame_saved_regs_zalloc (fi
);
1026 fi
->extra_info
= (struct frame_extra_info
*)
1027 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1029 fi
->extra_info
->framesize
= 0;
1030 fi
->extra_info
->frameoffset
= 0;
1031 fi
->extra_info
->framereg
= 0;
1034 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1036 memset (fi
->saved_regs
, '\000', sizeof fi
->saved_regs
);
1038 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1039 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1041 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1042 by assuming it's always FP. */
1043 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
,
1045 fi
->extra_info
->framesize
= 0;
1046 fi
->extra_info
->frameoffset
= 0;
1052 /* Compute stack pointer for this frame. We use this value for both the
1053 sigtramp and call dummy cases. */
1057 sp
= (fi
->next
->frame
- fi
->next
->extra_info
->frameoffset
1058 + fi
->next
->extra_info
->framesize
);
1060 /* Determine whether or not we're in a sigtramp frame.
1061 Unfortunately, it isn't sufficient to test
1062 fi->signal_handler_caller because this value is sometimes set
1063 after invoking INIT_EXTRA_FRAME_INFO. So we test *both*
1064 fi->signal_handler_caller and IN_SIGTRAMP to determine if we need
1065 to use the sigcontext addresses for the saved registers.
1067 Note: If an ARM IN_SIGTRAMP method ever needs to compare against
1068 the name of the function, the code below will have to be changed
1069 to first fetch the name of the function and then pass this name
1072 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1073 && (fi
->signal_handler_caller
|| IN_SIGTRAMP (fi
->pc
, (char *)0)))
1075 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1076 fi
->saved_regs
[reg
] = SIGCONTEXT_REGISTER_ADDRESS (sp
, fi
->pc
, reg
);
1078 /* FIXME: What about thumb mode? */
1079 fi
->extra_info
->framereg
= ARM_SP_REGNUM
;
1081 read_memory_integer (fi
->saved_regs
[fi
->extra_info
->framereg
],
1082 REGISTER_RAW_SIZE (fi
->extra_info
->framereg
));
1083 fi
->extra_info
->framesize
= 0;
1084 fi
->extra_info
->frameoffset
= 0;
1087 else if (PC_IN_CALL_DUMMY (fi
->pc
, sp
, fi
->frame
))
1090 CORE_ADDR callers_sp
;
1092 /* Set rp point at the high end of the saved registers. */
1093 rp
= fi
->frame
- REGISTER_SIZE
;
1095 /* Fill in addresses of saved registers. */
1096 fi
->saved_regs
[ARM_PS_REGNUM
] = rp
;
1097 rp
-= REGISTER_RAW_SIZE (ARM_PS_REGNUM
);
1098 for (reg
= ARM_PC_REGNUM
; reg
>= 0; reg
--)
1100 fi
->saved_regs
[reg
] = rp
;
1101 rp
-= REGISTER_RAW_SIZE (reg
);
1104 callers_sp
= read_memory_integer (fi
->saved_regs
[ARM_SP_REGNUM
],
1105 REGISTER_RAW_SIZE (ARM_SP_REGNUM
));
1106 fi
->extra_info
->framereg
= ARM_FP_REGNUM
;
1107 fi
->extra_info
->framesize
= callers_sp
- sp
;
1108 fi
->extra_info
->frameoffset
= fi
->frame
- sp
;
1112 arm_scan_prologue (fi
);
1115 /* this is the innermost frame? */
1116 fi
->frame
= read_register (fi
->extra_info
->framereg
);
1117 else if (fi
->extra_info
->framereg
== ARM_FP_REGNUM
1118 || fi
->extra_info
->framereg
== THUMB_FP_REGNUM
)
1120 /* not the innermost frame */
1121 /* If we have an FP, the callee saved it. */
1122 if (fi
->next
->saved_regs
[fi
->extra_info
->framereg
] != 0)
1124 read_memory_integer (fi
->next
1125 ->saved_regs
[fi
->extra_info
->framereg
], 4);
1127 /* If we were called by a frameless fn. then our frame is
1128 still in the frame pointer register on the board... */
1129 fi
->frame
= read_fp ();
1132 /* Calculate actual addresses of saved registers using offsets
1133 determined by arm_scan_prologue. */
1134 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1135 if (fi
->saved_regs
[reg
] != 0)
1136 fi
->saved_regs
[reg
] += (fi
->frame
+ fi
->extra_info
->framesize
1137 - fi
->extra_info
->frameoffset
);
1142 /* Find the caller of this frame. We do this by seeing if ARM_LR_REGNUM
1143 is saved in the stack anywhere, otherwise we get it from the
1146 The old definition of this function was a macro:
1147 #define FRAME_SAVED_PC(FRAME) \
1148 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1151 arm_frame_saved_pc (struct frame_info
*fi
)
1153 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1154 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1155 return generic_read_register_dummy (fi
->pc
, fi
->frame
, ARM_PC_REGNUM
);
1158 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
- fi
->extra_info
->frameoffset
,
1161 return read_memory_integer (fi
->saved_regs
[ARM_PC_REGNUM
],
1162 REGISTER_RAW_SIZE (ARM_PC_REGNUM
));
1166 CORE_ADDR pc
= arm_find_callers_reg (fi
, ARM_LR_REGNUM
);
1167 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1171 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1172 Examine the Program Status Register to decide which state we're in. */
1177 if (read_register (ARM_PS_REGNUM
) & 0x20) /* Bit 5 is Thumb state bit */
1178 return read_register (THUMB_FP_REGNUM
); /* R7 if Thumb */
1180 return read_register (ARM_FP_REGNUM
); /* R11 if ARM */
1183 /* Store into a struct frame_saved_regs the addresses of the saved
1184 registers of frame described by FRAME_INFO. This includes special
1185 registers such as PC and FP saved in special ways in the stack
1186 frame. SP is even more special: the address we return for it IS
1187 the sp for the next frame. */
1190 arm_frame_init_saved_regs (struct frame_info
*fip
)
1193 if (fip
->saved_regs
)
1196 arm_init_extra_frame_info (0, fip
);
1199 /* Push an empty stack frame, to record the current PC, etc. */
1202 arm_push_dummy_frame (void)
1204 CORE_ADDR old_sp
= read_register (ARM_SP_REGNUM
);
1205 CORE_ADDR sp
= old_sp
;
1206 CORE_ADDR fp
, prologue_start
;
1209 /* Push the two dummy prologue instructions in reverse order,
1210 so that they'll be in the correct low-to-high order in memory. */
1211 /* sub fp, ip, #4 */
1212 sp
= push_word (sp
, 0xe24cb004);
1213 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1214 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
1216 /* Push a pointer to the dummy prologue + 12, because when stm
1217 instruction stores the PC, it stores the address of the stm
1218 instruction itself plus 12. */
1219 fp
= sp
= push_word (sp
, prologue_start
+ 12);
1221 /* Push the processor status. */
1222 sp
= push_word (sp
, read_register (ARM_PS_REGNUM
));
1224 /* Push all 16 registers starting with r15. */
1225 for (regnum
= ARM_PC_REGNUM
; regnum
>= 0; regnum
--)
1226 sp
= push_word (sp
, read_register (regnum
));
1228 /* Update fp (for both Thumb and ARM) and sp. */
1229 write_register (ARM_FP_REGNUM
, fp
);
1230 write_register (THUMB_FP_REGNUM
, fp
);
1231 write_register (ARM_SP_REGNUM
, sp
);
1234 /* CALL_DUMMY_WORDS:
1235 This sequence of words is the instructions
1241 Note this is 12 bytes. */
1243 static LONGEST arm_call_dummy_words
[] =
1245 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
1248 /* Fix up the call dummy, based on whether the processor is currently
1249 in Thumb or ARM mode, and whether the target function is Thumb or
1250 ARM. There are three different situations requiring three
1253 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1254 been copied into the dummy parameter to this function.
1255 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1256 "mov pc,r4" instruction patched to be a "bx r4" instead.
1257 * Thumb calling anything: uses the Thumb dummy defined below, which
1258 works for calling both ARM and Thumb functions.
1260 All three call dummies expect to receive the target function
1261 address in R4, with the low bit set if it's a Thumb function. */
1264 arm_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
1265 struct value
**args
, struct type
*type
, int gcc_p
)
1267 static short thumb_dummy
[4] =
1269 0xf000, 0xf801, /* bl label */
1270 0xdf18, /* swi 24 */
1271 0x4720, /* label: bx r4 */
1273 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
1275 /* Set flag indicating whether the current PC is in a Thumb function. */
1276 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
1278 /* If the target function is Thumb, set the low bit of the function
1279 address. And if the CPU is currently in ARM mode, patch the
1280 second instruction of call dummy to use a BX instruction to
1281 switch to Thumb mode. */
1282 target_is_thumb
= arm_pc_is_thumb (fun
);
1283 if (target_is_thumb
)
1286 if (!caller_is_thumb
)
1287 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
1290 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1291 instead of the ARM one that's already been copied. This will
1292 work for both Thumb and ARM target functions. */
1293 if (caller_is_thumb
)
1297 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
1299 for (i
= 0; i
< len
; i
++)
1301 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1302 p
+= sizeof (thumb_dummy
[0]);
1306 /* Put the target address in r4; the call dummy will copy this to
1308 write_register (4, fun
);
1311 /* Return the offset in the call dummy of the instruction that needs
1312 to have a breakpoint placed on it. This is the offset of the 'swi
1313 24' instruction, which is no longer actually used, but simply acts
1314 as a place-holder now.
1316 This implements the CALL_DUMMY_BREAK_OFFSET macro. */
1319 arm_call_dummy_breakpoint_offset (void)
1321 if (caller_is_thumb
)
1329 This function does not support passing parameters using the FPA
1330 variant of the APCS. It passes any floating point arguments in the
1331 general registers and/or on the stack. */
1334 arm_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
1335 int struct_return
, CORE_ADDR struct_addr
)
1338 int argnum
, argreg
, nstack_size
;
1340 /* Walk through the list of args and determine how large a temporary
1341 stack is required. Need to take care here as structs may be
1342 passed on the stack, and we have to to push them. */
1343 nstack_size
= -4 * REGISTER_SIZE
; /* Some arguments go into A1-A4. */
1344 if (struct_return
) /* The struct address goes in A1. */
1345 nstack_size
+= REGISTER_SIZE
;
1347 /* Walk through the arguments and add their size to nstack_size. */
1348 for (argnum
= 0; argnum
< nargs
; argnum
++)
1351 struct type
*arg_type
;
1353 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1354 len
= TYPE_LENGTH (arg_type
);
1359 /* Allocate room on the stack, and initialize our stack frame
1362 if (nstack_size
> 0)
1368 /* Initialize the integer argument register pointer. */
1369 argreg
= ARM_A1_REGNUM
;
1371 /* The struct_return pointer occupies the first parameter passing
1374 write_register (argreg
++, struct_addr
);
1376 /* Process arguments from left to right. Store as many as allowed
1377 in the parameter passing registers (A1-A4), and save the rest on
1378 the temporary stack. */
1379 for (argnum
= 0; argnum
< nargs
; argnum
++)
1384 enum type_code typecode
;
1385 struct type
*arg_type
, *target_type
;
1387 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1388 target_type
= TYPE_TARGET_TYPE (arg_type
);
1389 len
= TYPE_LENGTH (arg_type
);
1390 typecode
= TYPE_CODE (arg_type
);
1391 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
1394 /* I don't know why this code was disable. The only logical use
1395 for a function pointer is to call that function, so setting
1396 the mode bit is perfectly fine. FN */
1397 /* If the argument is a pointer to a function, and it is a Thumb
1398 function, set the low bit of the pointer. */
1399 if (TYPE_CODE_PTR
== typecode
1400 && NULL
!= target_type
1401 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1403 CORE_ADDR regval
= extract_address (val
, len
);
1404 if (arm_pc_is_thumb (regval
))
1405 store_address (val
, len
, MAKE_THUMB_ADDR (regval
));
1408 /* Copy the argument to general registers or the stack in
1409 register-sized pieces. Large arguments are split between
1410 registers and stack. */
1413 int partial_len
= len
< REGISTER_SIZE
? len
: REGISTER_SIZE
;
1415 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1417 /* It's an argument being passed in a general register. */
1418 regval
= extract_address (val
, partial_len
);
1419 write_register (argreg
++, regval
);
1423 /* Push the arguments onto the stack. */
1424 write_memory ((CORE_ADDR
) fp
, val
, REGISTER_SIZE
);
1425 fp
+= REGISTER_SIZE
;
1433 /* Return adjusted stack pointer. */
1437 /* Pop the current frame. So long as the frame info has been initialized
1438 properly (see arm_init_extra_frame_info), this code works for dummy frames
1439 as well as regular frames. I.e, there's no need to have a special case
1440 for dummy frames. */
1442 arm_pop_frame (void)
1445 struct frame_info
*frame
= get_current_frame ();
1446 CORE_ADDR old_SP
= (frame
->frame
- frame
->extra_info
->frameoffset
1447 + frame
->extra_info
->framesize
);
1449 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1450 if (frame
->saved_regs
[regnum
] != 0)
1451 write_register (regnum
,
1452 read_memory_integer (frame
->saved_regs
[regnum
],
1453 REGISTER_RAW_SIZE (regnum
)));
1455 write_register (ARM_PC_REGNUM
, FRAME_SAVED_PC (frame
));
1456 write_register (ARM_SP_REGNUM
, old_SP
);
1458 flush_cached_frames ();
1462 print_fpu_flags (int flags
)
1464 if (flags
& (1 << 0))
1465 fputs ("IVO ", stdout
);
1466 if (flags
& (1 << 1))
1467 fputs ("DVZ ", stdout
);
1468 if (flags
& (1 << 2))
1469 fputs ("OFL ", stdout
);
1470 if (flags
& (1 << 3))
1471 fputs ("UFL ", stdout
);
1472 if (flags
& (1 << 4))
1473 fputs ("INX ", stdout
);
1477 /* Print interesting information about the floating point processor
1478 (if present) or emulator. */
1480 arm_print_float_info (void)
1482 register unsigned long status
= read_register (ARM_FPS_REGNUM
);
1485 type
= (status
>> 24) & 127;
1486 printf ("%s FPU type %d\n",
1487 (status
& (1 << 31)) ? "Hardware" : "Software",
1489 fputs ("mask: ", stdout
);
1490 print_fpu_flags (status
>> 16);
1491 fputs ("flags: ", stdout
);
1492 print_fpu_flags (status
);
1495 /* Return the GDB type object for the "standard" data type of data in
1498 static struct type
*
1499 arm_register_type (int regnum
)
1501 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1503 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1504 return builtin_type_arm_ext_big
;
1506 return builtin_type_arm_ext_littlebyte_bigword
;
1509 return builtin_type_int32
;
1512 /* Index within `registers' of the first byte of the space for
1516 arm_register_byte (int regnum
)
1518 if (regnum
< ARM_F0_REGNUM
)
1519 return regnum
* INT_REGISTER_RAW_SIZE
;
1520 else if (regnum
< ARM_PS_REGNUM
)
1521 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1522 + (regnum
- ARM_F0_REGNUM
) * FP_REGISTER_RAW_SIZE
);
1524 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1525 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
1526 + (regnum
- ARM_FPS_REGNUM
) * STATUS_REGISTER_SIZE
);
1529 /* Number of bytes of storage in the actual machine representation for
1530 register N. All registers are 4 bytes, except fp0 - fp7, which are
1531 12 bytes in length. */
1534 arm_register_raw_size (int regnum
)
1536 if (regnum
< ARM_F0_REGNUM
)
1537 return INT_REGISTER_RAW_SIZE
;
1538 else if (regnum
< ARM_FPS_REGNUM
)
1539 return FP_REGISTER_RAW_SIZE
;
1541 return STATUS_REGISTER_SIZE
;
1544 /* Number of bytes of storage in a program's representation
1547 arm_register_virtual_size (int regnum
)
1549 if (regnum
< ARM_F0_REGNUM
)
1550 return INT_REGISTER_VIRTUAL_SIZE
;
1551 else if (regnum
< ARM_FPS_REGNUM
)
1552 return FP_REGISTER_VIRTUAL_SIZE
;
1554 return STATUS_REGISTER_SIZE
;
1558 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1559 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1560 It is thought that this is is the floating-point register format on
1561 little-endian systems. */
1564 convert_from_extended (void *ptr
, void *dbl
)
1567 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1568 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1570 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1572 floatformat_from_doublest (TARGET_DOUBLE_FORMAT
, &d
, dbl
);
1576 convert_to_extended (void *dbl
, void *ptr
)
1579 floatformat_to_doublest (TARGET_DOUBLE_FORMAT
, ptr
, &d
);
1580 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1581 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1583 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1588 condition_true (unsigned long cond
, unsigned long status_reg
)
1590 if (cond
== INST_AL
|| cond
== INST_NV
)
1596 return ((status_reg
& FLAG_Z
) != 0);
1598 return ((status_reg
& FLAG_Z
) == 0);
1600 return ((status_reg
& FLAG_C
) != 0);
1602 return ((status_reg
& FLAG_C
) == 0);
1604 return ((status_reg
& FLAG_N
) != 0);
1606 return ((status_reg
& FLAG_N
) == 0);
1608 return ((status_reg
& FLAG_V
) != 0);
1610 return ((status_reg
& FLAG_V
) == 0);
1612 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1614 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1616 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1618 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1620 return (((status_reg
& FLAG_Z
) == 0) &&
1621 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1623 return (((status_reg
& FLAG_Z
) != 0) ||
1624 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1629 /* Support routines for single stepping. Calculate the next PC value. */
1630 #define submask(x) ((1L << ((x) + 1)) - 1)
1631 #define bit(obj,st) (((obj) >> (st)) & 1)
1632 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1633 #define sbits(obj,st,fn) \
1634 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1635 #define BranchDest(addr,instr) \
1636 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1639 static unsigned long
1640 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1641 unsigned long status_reg
)
1643 unsigned long res
, shift
;
1644 int rm
= bits (inst
, 0, 3);
1645 unsigned long shifttype
= bits (inst
, 5, 6);
1649 int rs
= bits (inst
, 8, 11);
1650 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1653 shift
= bits (inst
, 7, 11);
1656 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1657 + (bit (inst
, 4) ? 12 : 8))
1658 : read_register (rm
));
1663 res
= shift
>= 32 ? 0 : res
<< shift
;
1667 res
= shift
>= 32 ? 0 : res
>> shift
;
1673 res
= ((res
& 0x80000000L
)
1674 ? ~((~res
) >> shift
) : res
>> shift
);
1677 case 3: /* ROR/RRX */
1680 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1682 res
= (res
>> shift
) | (res
<< (32 - shift
));
1686 return res
& 0xffffffff;
1689 /* Return number of 1-bits in VAL. */
1692 bitcount (unsigned long val
)
1695 for (nbits
= 0; val
!= 0; nbits
++)
1696 val
&= val
- 1; /* delete rightmost 1-bit in val */
1701 thumb_get_next_pc (CORE_ADDR pc
)
1703 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1704 unsigned short inst1
= read_memory_integer (pc
, 2);
1705 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1706 unsigned long offset
;
1708 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1712 /* Fetch the saved PC from the stack. It's stored above
1713 all of the other registers. */
1714 offset
= bitcount (bits (inst1
, 0, 7)) * REGISTER_SIZE
;
1715 sp
= read_register (ARM_SP_REGNUM
);
1716 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1717 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1719 error ("Infinite loop detected");
1721 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1723 unsigned long status
= read_register (ARM_PS_REGNUM
);
1724 unsigned long cond
= bits (inst1
, 8, 11);
1725 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1726 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1728 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1730 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1732 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1734 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1735 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1736 nextpc
= pc_val
+ offset
;
1743 arm_get_next_pc (CORE_ADDR pc
)
1745 unsigned long pc_val
;
1746 unsigned long this_instr
;
1747 unsigned long status
;
1750 if (arm_pc_is_thumb (pc
))
1751 return thumb_get_next_pc (pc
);
1753 pc_val
= (unsigned long) pc
;
1754 this_instr
= read_memory_integer (pc
, 4);
1755 status
= read_register (ARM_PS_REGNUM
);
1756 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1758 if (condition_true (bits (this_instr
, 28, 31), status
))
1760 switch (bits (this_instr
, 24, 27))
1763 case 0x1: /* data processing */
1767 unsigned long operand1
, operand2
, result
= 0;
1771 if (bits (this_instr
, 12, 15) != 15)
1774 if (bits (this_instr
, 22, 25) == 0
1775 && bits (this_instr
, 4, 7) == 9) /* multiply */
1776 error ("Illegal update to pc in instruction");
1778 /* Multiply into PC */
1779 c
= (status
& FLAG_C
) ? 1 : 0;
1780 rn
= bits (this_instr
, 16, 19);
1781 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1783 if (bit (this_instr
, 25))
1785 unsigned long immval
= bits (this_instr
, 0, 7);
1786 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1787 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1790 else /* operand 2 is a shifted register */
1791 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1793 switch (bits (this_instr
, 21, 24))
1796 result
= operand1
& operand2
;
1800 result
= operand1
^ operand2
;
1804 result
= operand1
- operand2
;
1808 result
= operand2
- operand1
;
1812 result
= operand1
+ operand2
;
1816 result
= operand1
+ operand2
+ c
;
1820 result
= operand1
- operand2
+ c
;
1824 result
= operand2
- operand1
+ c
;
1830 case 0xb: /* tst, teq, cmp, cmn */
1831 result
= (unsigned long) nextpc
;
1835 result
= operand1
| operand2
;
1839 /* Always step into a function. */
1844 result
= operand1
& ~operand2
;
1851 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1854 error ("Infinite loop detected");
1859 case 0x5: /* data transfer */
1862 if (bit (this_instr
, 20))
1865 if (bits (this_instr
, 12, 15) == 15)
1871 if (bit (this_instr
, 22))
1872 error ("Illegal update to pc in instruction");
1874 /* byte write to PC */
1875 rn
= bits (this_instr
, 16, 19);
1876 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1877 if (bit (this_instr
, 24))
1880 int c
= (status
& FLAG_C
) ? 1 : 0;
1881 unsigned long offset
=
1882 (bit (this_instr
, 25)
1883 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1884 : bits (this_instr
, 0, 11));
1886 if (bit (this_instr
, 23))
1891 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1894 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1897 error ("Infinite loop detected");
1903 case 0x9: /* block transfer */
1904 if (bit (this_instr
, 20))
1907 if (bit (this_instr
, 15))
1912 if (bit (this_instr
, 23))
1915 unsigned long reglist
= bits (this_instr
, 0, 14);
1916 offset
= bitcount (reglist
) * 4;
1917 if (bit (this_instr
, 24)) /* pre */
1920 else if (bit (this_instr
, 24))
1924 unsigned long rn_val
=
1925 read_register (bits (this_instr
, 16, 19));
1927 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1931 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1933 error ("Infinite loop detected");
1938 case 0xb: /* branch & link */
1939 case 0xa: /* branch */
1941 nextpc
= BranchDest (pc
, this_instr
);
1943 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1945 error ("Infinite loop detected");
1951 case 0xe: /* coproc ops */
1956 fprintf (stderr
, "Bad bit-field extraction\n");
1964 /* single_step() is called just before we want to resume the inferior,
1965 if we want to single-step it but there is no hardware or kernel
1966 single-step support. We find the target of the coming instruction
1969 single_step is also called just after the inferior stops. If we had
1970 set up a simulated single-step, we undo our damage. */
1973 arm_software_single_step (enum target_signal sig
, int insert_bpt
)
1975 static int next_pc
; /* State between setting and unsetting. */
1976 static char break_mem
[BREAKPOINT_MAX
]; /* Temporary storage for mem@bpt */
1980 next_pc
= arm_get_next_pc (read_register (ARM_PC_REGNUM
));
1981 target_insert_breakpoint (next_pc
, break_mem
);
1984 target_remove_breakpoint (next_pc
, break_mem
);
1987 #include "bfd-in2.h"
1988 #include "libcoff.h"
1991 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
1993 if (arm_pc_is_thumb (memaddr
))
1995 static asymbol
*asym
;
1996 static combined_entry_type ce
;
1997 static struct coff_symbol_struct csym
;
1998 static struct _bfd fake_bfd
;
1999 static bfd_target fake_target
;
2001 if (csym
.native
== NULL
)
2003 /* Create a fake symbol vector containing a Thumb symbol. This is
2004 solely so that the code in print_insn_little_arm() and
2005 print_insn_big_arm() in opcodes/arm-dis.c will detect the presence
2006 of a Thumb symbol and switch to decoding Thumb instructions. */
2008 fake_target
.flavour
= bfd_target_coff_flavour
;
2009 fake_bfd
.xvec
= &fake_target
;
2010 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
2012 csym
.symbol
.the_bfd
= &fake_bfd
;
2013 csym
.symbol
.name
= "fake";
2014 asym
= (asymbol
*) & csym
;
2017 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
2018 info
->symbols
= &asym
;
2021 info
->symbols
= NULL
;
2023 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2024 return print_insn_big_arm (memaddr
, info
);
2026 return print_insn_little_arm (memaddr
, info
);
2029 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2030 the program counter value to determine whether a 16-bit or 32-bit
2031 breakpoint should be used. It returns a pointer to a string of
2032 bytes that encode a breakpoint instruction, stores the length of
2033 the string to *lenptr, and adjusts the program counter (if
2034 necessary) to point to the actual memory location where the
2035 breakpoint should be inserted. */
2037 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
2038 breakpoints and storing their handles instread of what was in
2039 memory. It is nice that this is the same size as a handle -
2040 otherwise remote-rdp will have to change. */
2043 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
2045 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
2047 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2049 static char thumb_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2050 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2051 *lenptr
= sizeof (thumb_breakpoint
);
2052 return thumb_breakpoint
;
2056 static char thumb_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2057 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2058 *lenptr
= sizeof (thumb_breakpoint
);
2059 return thumb_breakpoint
;
2064 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2066 static char arm_breakpoint
[] = ARM_BE_BREAKPOINT
;
2067 *lenptr
= sizeof (arm_breakpoint
);
2068 return arm_breakpoint
;
2072 static char arm_breakpoint
[] = ARM_LE_BREAKPOINT
;
2073 *lenptr
= sizeof (arm_breakpoint
);
2074 return arm_breakpoint
;
2079 /* Extract from an array REGBUF containing the (raw) register state a
2080 function return value of type TYPE, and copy that, in virtual
2081 format, into VALBUF. */
2084 arm_extract_return_value (struct type
*type
,
2085 char regbuf
[REGISTER_BYTES
],
2088 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2089 convert_from_extended (®buf
[REGISTER_BYTE (ARM_F0_REGNUM
)], valbuf
);
2091 memcpy (valbuf
, ®buf
[REGISTER_BYTE (ARM_A1_REGNUM
)],
2092 TYPE_LENGTH (type
));
2095 /* Extract from an array REGBUF containing the (raw) register state
2096 the address in which a function should return its structure value. */
2099 arm_extract_struct_value_address (char *regbuf
)
2101 return extract_address (regbuf
, REGISTER_RAW_SIZE(ARM_A1_REGNUM
));
2104 /* Will a function return an aggregate type in memory or in a
2105 register? Return 0 if an aggregate type can be returned in a
2106 register, 1 if it must be returned in memory. */
2109 arm_use_struct_convention (int gcc_p
, struct type
*type
)
2112 register enum type_code code
;
2114 /* In the ARM ABI, "integer" like aggregate types are returned in
2115 registers. For an aggregate type to be integer like, its size
2116 must be less than or equal to REGISTER_SIZE and the offset of
2117 each addressable subfield must be zero. Note that bit fields are
2118 not addressable, and all addressable subfields of unions always
2119 start at offset zero.
2121 This function is based on the behaviour of GCC 2.95.1.
2122 See: gcc/arm.c: arm_return_in_memory() for details.
2124 Note: All versions of GCC before GCC 2.95.2 do not set up the
2125 parameters correctly for a function returning the following
2126 structure: struct { float f;}; This should be returned in memory,
2127 not a register. Richard Earnshaw sent me a patch, but I do not
2128 know of any way to detect if a function like the above has been
2129 compiled with the correct calling convention. */
2131 /* All aggregate types that won't fit in a register must be returned
2133 if (TYPE_LENGTH (type
) > REGISTER_SIZE
)
2138 /* The only aggregate types that can be returned in a register are
2139 structs and unions. Arrays must be returned in memory. */
2140 code
= TYPE_CODE (type
);
2141 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2146 /* Assume all other aggregate types can be returned in a register.
2147 Run a check for structures, unions and arrays. */
2150 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2153 /* Need to check if this struct/union is "integer" like. For
2154 this to be true, its size must be less than or equal to
2155 REGISTER_SIZE and the offset of each addressable subfield
2156 must be zero. Note that bit fields are not addressable, and
2157 unions always start at offset zero. If any of the subfields
2158 is a floating point type, the struct/union cannot be an
2161 /* For each field in the object, check:
2162 1) Is it FP? --> yes, nRc = 1;
2163 2) Is it addressable (bitpos != 0) and
2164 not packed (bitsize == 0)?
2168 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2170 enum type_code field_type_code
;
2171 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
2173 /* Is it a floating point type field? */
2174 if (field_type_code
== TYPE_CODE_FLT
)
2180 /* If bitpos != 0, then we have to care about it. */
2181 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2183 /* Bitfields are not addressable. If the field bitsize is
2184 zero, then the field is not packed. Hence it cannot be
2185 a bitfield or any other packed type. */
2186 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2198 /* Write into appropriate registers a function return value of type
2199 TYPE, given in virtual format. */
2202 arm_store_return_value (struct type
*type
, char *valbuf
)
2204 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2206 char buf
[MAX_REGISTER_RAW_SIZE
];
2208 convert_to_extended (valbuf
, buf
);
2209 /* XXX Is this correct for soft-float? */
2210 write_register_bytes (REGISTER_BYTE (ARM_F0_REGNUM
), buf
,
2211 MAX_REGISTER_RAW_SIZE
);
2214 write_register_bytes (0, valbuf
, TYPE_LENGTH (type
));
2217 /* Store the address of the place in which to copy the structure the
2218 subroutine will return. This is called from call_function. */
2221 arm_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
2223 write_register (ARM_A1_REGNUM
, addr
);
2226 /* Return non-zero if the PC is inside a thumb call thunk. */
2229 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2231 CORE_ADDR start_addr
;
2233 /* Find the starting address of the function containing the PC. If
2234 the caller didn't give us a name, look it up at the same time. */
2235 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
2238 return strncmp (name
, "_call_via_r", 11) == 0;
2241 /* If PC is in a Thumb call or return stub, return the address of the
2242 target PC, which is in a register. The thunk functions are called
2243 _called_via_xx, where x is the register name. The possible names
2244 are r0-r9, sl, fp, ip, sp, and lr. */
2247 arm_skip_stub (CORE_ADDR pc
)
2250 CORE_ADDR start_addr
;
2252 /* Find the starting address and name of the function containing the PC. */
2253 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2256 /* Call thunks always start with "_call_via_". */
2257 if (strncmp (name
, "_call_via_", 10) == 0)
2259 /* Use the name suffix to determine which register contains the
2261 static char *table
[15] =
2262 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2263 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2267 for (regno
= 0; regno
<= 14; regno
++)
2268 if (strcmp (&name
[10], table
[regno
]) == 0)
2269 return read_register (regno
);
2272 return 0; /* not a stub */
2275 /* If the user changes the register disassembly flavor used for info register
2276 and other commands, we have to also switch the flavor used in opcodes
2277 for disassembly output.
2278 This function is run in the set disassembly_flavor command, and does that. */
2281 set_disassembly_flavor_sfunc (char *args
, int from_tty
,
2282 struct cmd_list_element
*c
)
2284 set_disassembly_flavor ();
2287 /* Return the ARM register name corresponding to register I. */
2289 arm_register_name (int i
)
2291 return arm_register_names
[i
];
2295 set_disassembly_flavor (void)
2297 const char *setname
, *setdesc
, **regnames
;
2300 /* Find the flavor that the user wants in the opcodes table. */
2302 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2303 while ((disassembly_flavor
!= setname
)
2304 && (current
< num_flavor_options
))
2305 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2306 current_option
= current
;
2308 /* Fill our copy. */
2309 for (j
= 0; j
< numregs
; j
++)
2310 arm_register_names
[j
] = (char *) regnames
[j
];
2313 if (isupper (*regnames
[ARM_PC_REGNUM
]))
2315 arm_register_names
[ARM_FPS_REGNUM
] = "FPS";
2316 arm_register_names
[ARM_PS_REGNUM
] = "CPSR";
2320 arm_register_names
[ARM_FPS_REGNUM
] = "fps";
2321 arm_register_names
[ARM_PS_REGNUM
] = "cpsr";
2324 /* Synchronize the disassembler. */
2325 set_arm_regname_option (current
);
2328 /* arm_othernames implements the "othernames" command. This is kind
2329 of hacky, and I prefer the set-show disassembly-flavor which is
2330 also used for the x86 gdb. I will keep this around, however, in
2331 case anyone is actually using it. */
2334 arm_othernames (char *names
, int n
)
2336 /* Circle through the various flavors. */
2337 current_option
= (current_option
+ 1) % num_flavor_options
;
2339 disassembly_flavor
= valid_flavors
[current_option
];
2340 set_disassembly_flavor ();
2343 /* Fetch, and possibly build, an appropriate link_map_offsets structure
2344 for ARM linux targets using the struct offsets defined in <link.h>.
2345 Note, however, that link.h is not actually referred to in this file.
2346 Instead, the relevant structs offsets were obtained from examining
2347 link.h. (We can't refer to link.h from this file because the host
2348 system won't necessarily have it, or if it does, the structs which
2349 it defines will refer to the host system, not the target.) */
2351 struct link_map_offsets
*
2352 arm_linux_svr4_fetch_link_map_offsets (void)
2354 static struct link_map_offsets lmo
;
2355 static struct link_map_offsets
*lmp
= 0;
2361 lmo
.r_debug_size
= 8; /* Actual size is 20, but this is all we
2364 lmo
.r_map_offset
= 4;
2367 lmo
.link_map_size
= 20; /* Actual size is 552, but this is all we
2370 lmo
.l_addr_offset
= 0;
2371 lmo
.l_addr_size
= 4;
2373 lmo
.l_name_offset
= 4;
2374 lmo
.l_name_size
= 4;
2376 lmo
.l_next_offset
= 12;
2377 lmo
.l_next_size
= 4;
2379 lmo
.l_prev_offset
= 16;
2380 lmo
.l_prev_size
= 4;
2386 /* Test whether the coff symbol specific value corresponds to a Thumb
2390 coff_sym_is_thumb (int val
)
2392 return (val
== C_THUMBEXT
||
2393 val
== C_THUMBSTAT
||
2394 val
== C_THUMBEXTFUNC
||
2395 val
== C_THUMBSTATFUNC
||
2396 val
== C_THUMBLABEL
);
2399 /* arm_coff_make_msymbol_special()
2400 arm_elf_make_msymbol_special()
2402 These functions test whether the COFF or ELF symbol corresponds to
2403 an address in thumb code, and set a "special" bit in a minimal
2404 symbol to indicate that it does. */
2407 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2409 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2411 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2413 MSYMBOL_SET_SPECIAL (msym
);
2417 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2419 if (coff_sym_is_thumb (val
))
2420 MSYMBOL_SET_SPECIAL (msym
);
2423 static struct gdbarch
*
2424 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2426 struct gdbarch
*gdbarch
;
2429 return arches
->gdbarch
;
2431 /* XXX We'll probably need to set the tdep field soon. */
2432 gdbarch
= gdbarch_alloc (&info
, NULL
);
2434 /* Floating point sizes and format. */
2435 switch (info
.byte_order
)
2437 case BFD_ENDIAN_BIG
:
2438 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
2439 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_big
);
2440 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
2443 case BFD_ENDIAN_LITTLE
:
2444 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
2445 set_gdbarch_double_format (gdbarch
,
2446 &floatformat_ieee_double_littlebyte_bigword
);
2447 set_gdbarch_long_double_format (gdbarch
,
2448 &floatformat_ieee_double_littlebyte_bigword
);
2452 internal_error (__FILE__
, __LINE__
,
2453 "arm_gdbarch_init: bad byte order for float format");
2456 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
2458 /* Call dummy code. */
2459 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
2460 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
2461 set_gdbarch_call_dummy_p (gdbarch
, 1);
2462 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
2464 set_gdbarch_call_dummy_words (gdbarch
, arm_call_dummy_words
);
2465 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (arm_call_dummy_words
));
2466 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
2468 set_gdbarch_fix_call_dummy (gdbarch
, arm_fix_call_dummy
);
2470 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_on_stack
);
2472 set_gdbarch_get_saved_register (gdbarch
, generic_get_saved_register
);
2473 set_gdbarch_push_arguments (gdbarch
, arm_push_arguments
);
2475 /* Frame handling. */
2476 set_gdbarch_frame_chain_valid (gdbarch
, arm_frame_chain_valid
);
2477 set_gdbarch_init_extra_frame_info (gdbarch
, arm_init_extra_frame_info
);
2478 set_gdbarch_read_fp (gdbarch
, arm_read_fp
);
2479 set_gdbarch_frame_chain (gdbarch
, arm_frame_chain
);
2480 set_gdbarch_frameless_function_invocation
2481 (gdbarch
, arm_frameless_function_invocation
);
2482 set_gdbarch_frame_saved_pc (gdbarch
, arm_frame_saved_pc
);
2483 set_gdbarch_frame_args_address (gdbarch
, arm_frame_args_address
);
2484 set_gdbarch_frame_locals_address (gdbarch
, arm_frame_locals_address
);
2485 set_gdbarch_frame_num_args (gdbarch
, arm_frame_num_args
);
2486 set_gdbarch_frame_args_skip (gdbarch
, 0);
2487 set_gdbarch_frame_init_saved_regs (gdbarch
, arm_frame_init_saved_regs
);
2488 set_gdbarch_push_dummy_frame (gdbarch
, arm_push_dummy_frame
);
2489 set_gdbarch_pop_frame (gdbarch
, arm_pop_frame
);
2491 /* Address manipulation. */
2492 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
2493 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
2495 /* Offset from address of function to start of its code. */
2496 set_gdbarch_function_start_offset (gdbarch
, 0);
2498 /* Advance PC across function entry code. */
2499 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
2501 /* Get the PC when a frame might not be available. */
2502 set_gdbarch_saved_pc_after_call (gdbarch
, arm_saved_pc_after_call
);
2504 /* The stack grows downward. */
2505 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2507 /* Breakpoint manipulation. */
2508 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
2509 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2511 /* Information about registers, etc. */
2512 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
2513 set_gdbarch_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
2514 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
2515 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
2516 set_gdbarch_register_byte (gdbarch
, arm_register_byte
);
2517 set_gdbarch_register_bytes (gdbarch
,
2518 (NUM_GREGS
* INT_REGISTER_RAW_SIZE
2519 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
2520 + NUM_SREGS
* STATUS_REGISTER_SIZE
));
2521 set_gdbarch_num_regs (gdbarch
, NUM_GREGS
+ NUM_FREGS
+ NUM_SREGS
);
2522 set_gdbarch_register_raw_size (gdbarch
, arm_register_raw_size
);
2523 set_gdbarch_register_virtual_size (gdbarch
, arm_register_virtual_size
);
2524 set_gdbarch_max_register_raw_size (gdbarch
, FP_REGISTER_RAW_SIZE
);
2525 set_gdbarch_max_register_virtual_size (gdbarch
, FP_REGISTER_VIRTUAL_SIZE
);
2526 set_gdbarch_register_virtual_type (gdbarch
, arm_register_type
);
2528 /* Integer registers are 4 bytes. */
2529 set_gdbarch_register_size (gdbarch
, 4);
2530 set_gdbarch_register_name (gdbarch
, arm_register_name
);
2532 /* Returning results. */
2533 set_gdbarch_extract_return_value (gdbarch
, arm_extract_return_value
);
2534 set_gdbarch_store_return_value (gdbarch
, arm_store_return_value
);
2535 set_gdbarch_store_struct_return (gdbarch
, arm_store_struct_return
);
2536 set_gdbarch_use_struct_convention (gdbarch
, arm_use_struct_convention
);
2537 set_gdbarch_extract_struct_value_address (gdbarch
,
2538 arm_extract_struct_value_address
);
2540 /* Single stepping. */
2541 /* XXX For an RDI target we should ask the target if it can single-step. */
2542 set_gdbarch_software_single_step (gdbarch
, arm_software_single_step
);
2544 /* Minsymbol frobbing. */
2545 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
2546 set_gdbarch_coff_make_msymbol_special (gdbarch
,
2547 arm_coff_make_msymbol_special
);
2549 /* XXX We can't do this until NUM_REGS is set for the architecture.
2550 Even then, we can't use SIZEOF_FRAME_SAVED_REGS, since that still
2551 references the old architecture vector, not the one we are
2553 if (prologue_cache
.saved_regs
!= NULL
)
2554 xfree (prologue_cache
.saved_regs
);
2556 prologue_cache
.saved_regs
= (CORE_ADDR
*)
2557 xcalloc (1, (sizeof (CORE_ADDR
)
2558 * (NUM_GREGS
+ NUM_FREGS
+ NUM_SREGS
+ NUM_PSEUDO_REGS
)));
2564 _initialize_arm_tdep (void)
2566 struct ui_file
*stb
;
2568 struct cmd_list_element
*new_cmd
;
2569 const char *setname
;
2570 const char *setdesc
;
2571 const char **regnames
;
2573 static char *helptext
;
2576 register_gdbarch_init (bfd_arch_arm
, arm_gdbarch_init
);
2578 tm_print_insn
= gdb_print_insn_arm
;
2580 /* Get the number of possible sets of register names defined in opcodes. */
2581 num_flavor_options
= get_arm_regname_num_options ();
2583 /* Sync the opcode insn printer with our register viewer: */
2584 parse_arm_disassembler_option ("reg-names-std");
2586 /* Begin creating the help text. */
2587 stb
= mem_fileopen ();
2588 fprintf_unfiltered (stb
, "Set the disassembly flavor.\n\
2589 The valid values are:\n");
2591 /* Initialize the array that will be passed to add_set_enum_cmd(). */
2592 valid_flavors
= xmalloc ((num_flavor_options
+ 1) * sizeof (char *));
2593 for (i
= 0; i
< num_flavor_options
; i
++)
2595 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
2596 valid_flavors
[i
] = setname
;
2597 fprintf_unfiltered (stb
, "%s - %s\n", setname
,
2599 /* Copy the default names (if found) and synchronize disassembler. */
2600 if (!strcmp (setname
, "std"))
2602 disassembly_flavor
= setname
;
2604 for (j
= 0; j
< numregs
; j
++)
2605 arm_register_names
[j
] = (char *) regnames
[j
];
2606 set_arm_regname_option (i
);
2609 /* Mark the end of valid options. */
2610 valid_flavors
[num_flavor_options
] = NULL
;
2612 /* Finish the creation of the help text. */
2613 fprintf_unfiltered (stb
, "The default is \"std\".");
2614 helptext
= ui_file_xstrdup (stb
, &length
);
2615 ui_file_delete (stb
);
2617 /* Add the disassembly-flavor command */
2618 new_cmd
= add_set_enum_cmd ("disassembly-flavor", no_class
,
2620 &disassembly_flavor
,
2623 set_cmd_sfunc (new_cmd
, set_disassembly_flavor_sfunc
);
2624 add_show_from_set (new_cmd
, &showlist
);
2626 /* ??? Maybe this should be a boolean. */
2627 add_show_from_set (add_set_cmd ("apcs32", no_class
,
2628 var_zinteger
, (char *) &arm_apcs_32
,
2629 "Set usage of ARM 32-bit mode.\n", &setlist
),
2632 /* Add the deprecated "othernames" command */
2634 add_com ("othernames", class_obscure
, arm_othernames
,
2635 "Switch to the next set of register names.");
2637 /* Fill in the prologue_cache fields. */
2638 prologue_cache
.saved_regs
= NULL
;
2639 prologue_cache
.extra_info
= (struct frame_extra_info
*)
2640 xcalloc (1, sizeof (struct frame_extra_info
));