1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "coff/internal.h" /* Internal format of COFF symbols in BFD */
30 #include "dis-asm.h" /* For register flavors. */
31 #include <ctype.h> /* for isupper () */
36 /* Each OS has a different mechanism for accessing the various
37 registers stored in the sigcontext structure.
39 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
40 function pointer) which may be used to determine the addresses
41 of the various saved registers in the sigcontext structure.
43 For the ARM target, there are three parameters to this function.
44 The first is the pc value of the frame under consideration, the
45 second the stack pointer of this frame, and the last is the
46 register number to fetch.
48 If the tm.h file does not define this macro, then it's assumed that
49 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
52 When it comes time to multi-arching this code, see the identically
53 named machinery in ia64-tdep.c for an example of how it could be
54 done. It should not be necessary to modify the code below where
55 this macro is used. */
57 #ifdef SIGCONTEXT_REGISTER_ADDRESS
58 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
59 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
62 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
63 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
66 extern void _initialize_arm_tdep (void);
68 /* Number of different reg name sets (options). */
69 static int num_flavor_options
;
71 /* We have more registers than the disassembler as gdb can print the value
72 of special registers as well.
73 The general register names are overwritten by whatever is being used by
74 the disassembler at the moment. We also adjust the case of cpsr and fps. */
76 /* Initial value: Register names used in ARM's ISA documentation. */
77 static char * arm_register_name_strings
[] =
78 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
79 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
80 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
81 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
82 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
83 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
84 "fps", "cpsr" }; /* 24 25 */
85 char **arm_register_names
= arm_register_name_strings
;
87 /* Valid register name flavors. */
88 static const char **valid_flavors
;
90 /* Disassembly flavor to use. Default to "std" register names. */
91 static const char *disassembly_flavor
;
92 static int current_option
; /* Index to that option in the opcodes table. */
94 /* This is used to keep the bfd arch_info in sync with the disassembly
96 static void set_disassembly_flavor_sfunc(char *, int,
97 struct cmd_list_element
*);
98 static void set_disassembly_flavor (void);
100 static void convert_from_extended (void *ptr
, void *dbl
);
102 /* Define other aspects of the stack frame. We keep the offsets of
103 all saved registers, 'cause we need 'em a lot! We also keep the
104 current size of the stack frame, and the offset of the frame
105 pointer from the stack pointer (for frameless functions, and when
106 we're still in the prologue of a function with a frame) */
108 struct frame_extra_info
110 struct frame_saved_regs fsr
;
116 /* Addresses for calling Thumb functions have the bit 0 set.
117 Here are some macros to test, set, or clear bit 0 of addresses. */
118 #define IS_THUMB_ADDR(addr) ((addr) & 1)
119 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
120 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
122 /* Will a function return an aggregate type in memory or in a
123 register? Return 0 if an aggregate type can be returned in a
124 register, 1 if it must be returned in memory. */
127 arm_use_struct_convention (int gcc_p
, struct type
*type
)
130 register enum type_code code
;
132 /* In the ARM ABI, "integer" like aggregate types are returned in
133 registers. For an aggregate type to be integer like, its size
134 must be less than or equal to REGISTER_SIZE and the offset of
135 each addressable subfield must be zero. Note that bit fields are
136 not addressable, and all addressable subfields of unions always
137 start at offset zero.
139 This function is based on the behaviour of GCC 2.95.1.
140 See: gcc/arm.c: arm_return_in_memory() for details.
142 Note: All versions of GCC before GCC 2.95.2 do not set up the
143 parameters correctly for a function returning the following
144 structure: struct { float f;}; This should be returned in memory,
145 not a register. Richard Earnshaw sent me a patch, but I do not
146 know of any way to detect if a function like the above has been
147 compiled with the correct calling convention. */
149 /* All aggregate types that won't fit in a register must be returned
151 if (TYPE_LENGTH (type
) > REGISTER_SIZE
)
156 /* The only aggregate types that can be returned in a register are
157 structs and unions. Arrays must be returned in memory. */
158 code
= TYPE_CODE (type
);
159 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
164 /* Assume all other aggregate types can be returned in a register.
165 Run a check for structures, unions and arrays. */
168 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
171 /* Need to check if this struct/union is "integer" like. For
172 this to be true, its size must be less than or equal to
173 REGISTER_SIZE and the offset of each addressable subfield
174 must be zero. Note that bit fields are not addressable, and
175 unions always start at offset zero. If any of the subfields
176 is a floating point type, the struct/union cannot be an
179 /* For each field in the object, check:
180 1) Is it FP? --> yes, nRc = 1;
181 2) Is it addressable (bitpos != 0) and
182 not packed (bitsize == 0)?
186 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
188 enum type_code field_type_code
;
189 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
191 /* Is it a floating point type field? */
192 if (field_type_code
== TYPE_CODE_FLT
)
198 /* If bitpos != 0, then we have to care about it. */
199 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
201 /* Bitfields are not addressable. If the field bitsize is
202 zero, then the field is not packed. Hence it cannot be
203 a bitfield or any other packed type. */
204 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
217 arm_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*thisframe
)
219 return (chain
!= 0 && (FRAME_SAVED_PC (thisframe
) >= LOWEST_PC
));
222 /* Set to true if the 32-bit mode is in use. */
226 /* Flag set by arm_fix_call_dummy that tells whether the target
227 function is a Thumb function. This flag is checked by
228 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
229 its use in valops.c) to pass the function address as an additional
232 static int target_is_thumb
;
234 /* Flag set by arm_fix_call_dummy that tells whether the calling
235 function is a Thumb function. This flag is checked by
236 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
238 static int caller_is_thumb
;
240 /* Determine if the program counter specified in MEMADDR is in a Thumb
244 arm_pc_is_thumb (CORE_ADDR memaddr
)
246 struct minimal_symbol
*sym
;
248 /* If bit 0 of the address is set, assume this is a Thumb address. */
249 if (IS_THUMB_ADDR (memaddr
))
252 /* Thumb functions have a "special" bit set in minimal symbols. */
253 sym
= lookup_minimal_symbol_by_pc (memaddr
);
256 return (MSYMBOL_IS_SPECIAL (sym
));
264 /* Determine if the program counter specified in MEMADDR is in a call
265 dummy being called from a Thumb function. */
268 arm_pc_is_thumb_dummy (CORE_ADDR memaddr
)
270 CORE_ADDR sp
= read_sp ();
272 /* FIXME: Until we switch for the new call dummy macros, this heuristic
273 is the best we can do. We are trying to determine if the pc is on
274 the stack, which (hopefully) will only happen in a call dummy.
275 We hope the current stack pointer is not so far alway from the dummy
276 frame location (true if we have not pushed large data structures or
277 gone too many levels deep) and that our 1024 is not enough to consider
278 code regions as part of the stack (true for most practical purposes) */
279 if (PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 1024))
280 return caller_is_thumb
;
286 arm_addr_bits_remove (CORE_ADDR val
)
288 if (arm_pc_is_thumb (val
))
289 return (val
& (arm_apcs_32
? 0xfffffffe : 0x03fffffe));
291 return (val
& (arm_apcs_32
? 0xfffffffc : 0x03fffffc));
295 arm_saved_pc_after_call (struct frame_info
*frame
)
297 return ADDR_BITS_REMOVE (read_register (LR_REGNUM
));
301 arm_frameless_function_invocation (struct frame_info
*fi
)
303 CORE_ADDR func_start
, after_prologue
;
306 func_start
= (get_pc_function_start ((fi
)->pc
) + FUNCTION_START_OFFSET
);
307 after_prologue
= SKIP_PROLOGUE (func_start
);
309 /* There are some frameless functions whose first two instructions
310 follow the standard APCS form, in which case after_prologue will
311 be func_start + 8. */
313 frameless
= (after_prologue
< func_start
+ 12);
317 /* A typical Thumb prologue looks like this:
321 Sometimes the latter instruction may be replaced by:
329 or, on tpcs, like this:
336 There is always one instruction of three classes:
341 When we have found at least one of each class we are done with the prolog.
342 Note that the "sub sp, #NN" before the push does not count.
346 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
348 CORE_ADDR current_pc
;
349 int findmask
= 0; /* findmask:
350 bit 0 - push { rlist }
351 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
352 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
355 for (current_pc
= pc
; current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40; current_pc
+= 2)
357 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
359 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
361 findmask
|= 1; /* push found */
363 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
365 if ((findmask
& 1) == 0) /* before push ? */
368 findmask
|= 4; /* add/sub sp found */
370 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
372 findmask
|= 2; /* setting of r7 found */
374 else if (insn
== 0x466f) /* mov r7, sp */
376 findmask
|= 2; /* setting of r7 found */
379 continue; /* something in the prolog that we don't care about or some
380 instruction from outside the prolog scheduled here for optimization */
386 /* The APCS (ARM Procedure Call Standard) defines the following
390 [stmfd sp!, {a1,a2,a3,a4}]
391 stmfd sp!, {...,fp,ip,lr,pc}
392 [stfe f7, [sp, #-12]!]
393 [stfe f6, [sp, #-12]!]
394 [stfe f5, [sp, #-12]!]
395 [stfe f4, [sp, #-12]!]
396 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
399 arm_skip_prologue (CORE_ADDR pc
)
403 CORE_ADDR func_addr
, func_end
;
404 struct symtab_and_line sal
;
406 /* See what the symbol table says. */
408 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
410 sal
= find_pc_line (func_addr
, 0);
411 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
415 /* Check if this is Thumb code. */
416 if (arm_pc_is_thumb (pc
))
417 return thumb_skip_prologue (pc
, func_end
);
419 /* Can't find the prologue end in the symbol table, try it the hard way
420 by disassembling the instructions. */
422 inst
= read_memory_integer (skip_pc
, 4);
423 if (inst
!= 0xe1a0c00d) /* mov ip, sp */
427 inst
= read_memory_integer (skip_pc
, 4);
428 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
431 inst
= read_memory_integer (skip_pc
, 4);
434 if ((inst
& 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */
438 inst
= read_memory_integer (skip_pc
, 4);
440 /* Any insns after this point may float into the code, if it makes
441 for better instruction scheduling, so we skip them only if we
442 find them, but still consdier the function to be frame-ful. */
444 /* We may have either one sfmfd instruction here, or several stfe
445 insns, depending on the version of floating point code we
447 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
450 inst
= read_memory_integer (skip_pc
, 4);
454 while ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
457 inst
= read_memory_integer (skip_pc
, 4);
461 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
467 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
468 This function decodes a Thumb function prologue to determine:
469 1) the size of the stack frame
470 2) which registers are saved on it
471 3) the offsets of saved regs
472 4) the offset from the stack pointer to the frame pointer
473 This information is stored in the "extra" fields of the frame_info.
475 A typical Thumb function prologue would create this stack frame
476 (offsets relative to FP)
477 old SP -> 24 stack parameters
480 R7 -> 0 local variables (16 bytes)
481 SP -> -12 additional stack space (12 bytes)
482 The frame size would thus be 36 bytes, and the frame offset would be
483 12 bytes. The frame register is R7.
485 The comments for thumb_skip_prolog() describe the algorithm we use to detect
486 the end of the prolog */
490 thumb_scan_prologue (struct frame_info
*fi
)
492 CORE_ADDR prologue_start
;
493 CORE_ADDR prologue_end
;
494 CORE_ADDR current_pc
;
495 int saved_reg
[16]; /* which register has been copied to register n? */
496 int findmask
= 0; /* findmask:
497 bit 0 - push { rlist }
498 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
499 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
503 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
505 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
507 if (sal
.line
== 0) /* no line info, use current PC */
508 prologue_end
= fi
->pc
;
509 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
510 prologue_end
= sal
.end
; /* (probably means no prologue) */
513 prologue_end
= prologue_start
+ 40; /* We're in the boondocks: allow for */
514 /* 16 pushes, an add, and "mv fp,sp" */
516 prologue_end
= min (prologue_end
, fi
->pc
);
518 /* Initialize the saved register map. When register H is copied to
519 register L, we will put H in saved_reg[L]. */
520 for (i
= 0; i
< 16; i
++)
523 /* Search the prologue looking for instructions that set up the
524 frame pointer, adjust the stack pointer, and save registers.
525 Do this until all basic prolog instructions are found. */
528 for (current_pc
= prologue_start
;
529 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
536 insn
= read_memory_unsigned_integer (current_pc
, 2);
538 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
541 findmask
|= 1; /* push found */
542 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
543 whether to save LR (R14). */
544 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
546 /* Calculate offsets of saved R0-R7 and LR. */
547 for (regno
= LR_REGNUM
; regno
>= 0; regno
--)
548 if (mask
& (1 << regno
))
551 fi
->fsr
.regs
[saved_reg
[regno
]] = -(fi
->framesize
);
552 saved_reg
[regno
] = regno
; /* reset saved register map */
555 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
557 if ((findmask
& 1) == 0) /* before push ? */
560 findmask
|= 4; /* add/sub sp found */
562 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
563 if (insn
& 0x80) /* is it signed? (==subtracting) */
565 fi
->frameoffset
+= offset
;
568 fi
->framesize
-= offset
;
570 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
572 findmask
|= 2; /* setting of r7 found */
573 fi
->framereg
= THUMB_FP_REGNUM
;
574 fi
->frameoffset
= (insn
& 0xff) << 2; /* get scaled offset */
576 else if (insn
== 0x466f) /* mov r7, sp */
578 findmask
|= 2; /* setting of r7 found */
579 fi
->framereg
= THUMB_FP_REGNUM
;
581 saved_reg
[THUMB_FP_REGNUM
] = SP_REGNUM
;
583 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
585 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
586 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
587 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
590 continue; /* something in the prolog that we don't care about or some
591 instruction from outside the prolog scheduled here for optimization */
595 /* Check if prologue for this frame's PC has already been scanned. If
596 it has, copy the relevant information about that prologue and
597 return non-zero. Otherwise do not copy anything and return zero.
599 The information saved in the cache includes:
600 * the frame register number;
601 * the size of the stack frame;
602 * the offsets of saved regs (relative to the old SP); and
603 * the offset from the stack pointer to the frame pointer
605 The cache contains only one entry, since this is adequate for the
606 typical sequence of prologue scan requests we get. When performing
607 a backtrace, GDB will usually ask to scan the same function twice
608 in a row (once to get the frame chain, and once to fill in the
609 extra frame information). */
611 static struct frame_info prologue_cache
;
614 check_prologue_cache (struct frame_info
*fi
)
618 if (fi
->pc
== prologue_cache
.pc
)
620 fi
->framereg
= prologue_cache
.framereg
;
621 fi
->framesize
= prologue_cache
.framesize
;
622 fi
->frameoffset
= prologue_cache
.frameoffset
;
623 for (i
= 0; i
< NUM_REGS
; i
++)
624 fi
->fsr
.regs
[i
] = prologue_cache
.fsr
.regs
[i
];
632 /* Copy the prologue information from fi to the prologue cache. */
635 save_prologue_cache (struct frame_info
*fi
)
639 prologue_cache
.pc
= fi
->pc
;
640 prologue_cache
.framereg
= fi
->framereg
;
641 prologue_cache
.framesize
= fi
->framesize
;
642 prologue_cache
.frameoffset
= fi
->frameoffset
;
644 for (i
= 0; i
< NUM_REGS
; i
++)
645 prologue_cache
.fsr
.regs
[i
] = fi
->fsr
.regs
[i
];
649 /* This function decodes an ARM function prologue to determine:
650 1) the size of the stack frame
651 2) which registers are saved on it
652 3) the offsets of saved regs
653 4) the offset from the stack pointer to the frame pointer
654 This information is stored in the "extra" fields of the frame_info.
656 There are two basic forms for the ARM prologue. The fixed argument
657 function call will look like:
660 stmfd sp!, {fp, ip, lr, pc}
664 Which would create this stack frame (offsets relative to FP):
665 IP -> 4 (caller's stack)
666 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
667 -4 LR (return address in caller)
668 -8 IP (copy of caller's SP)
670 SP -> -28 Local variables
672 The frame size would thus be 32 bytes, and the frame offset would be
673 28 bytes. The stmfd call can also save any of the vN registers it
674 plans to use, which increases the frame size accordingly.
676 Note: The stored PC is 8 off of the STMFD instruction that stored it
677 because the ARM Store instructions always store PC + 8 when you read
680 A variable argument function call will look like:
683 stmfd sp!, {a1, a2, a3, a4}
684 stmfd sp!, {fp, ip, lr, pc}
687 Which would create this stack frame (offsets relative to FP):
688 IP -> 20 (caller's stack)
693 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
694 -4 LR (return address in caller)
695 -8 IP (copy of caller's SP)
697 SP -> -28 Local variables
699 The frame size would thus be 48 bytes, and the frame offset would be
702 There is another potential complication, which is that the optimizer
703 will try to separate the store of fp in the "stmfd" instruction from
704 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
705 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
707 Also, note, the original version of the ARM toolchain claimed that there
710 instruction at the end of the prologue. I have never seen GCC produce
711 this, and the ARM docs don't mention it. We still test for it below in
717 arm_scan_prologue (struct frame_info
*fi
)
719 int regno
, sp_offset
, fp_offset
;
720 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
722 /* Check if this function is already in the cache of frame information. */
723 if (check_prologue_cache (fi
))
726 /* Assume there is no frame until proven otherwise. */
727 fi
->framereg
= SP_REGNUM
;
731 /* Check for Thumb prologue. */
732 if (arm_pc_is_thumb (fi
->pc
))
734 thumb_scan_prologue (fi
);
735 save_prologue_cache (fi
);
739 /* Find the function prologue. If we can't find the function in
740 the symbol table, peek in the stack frame to find the PC. */
741 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
743 /* One way to find the end of the prologue (which works well
744 for unoptimized code) is to do the following:
746 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
749 prologue_end = fi->pc;
750 else if (sal.end < prologue_end)
751 prologue_end = sal.end;
753 This mechanism is very accurate so long as the optimizer
754 doesn't move any instructions from the function body into the
755 prologue. If this happens, sal.end will be the last
756 instruction in the first hunk of prologue code just before
757 the first instruction that the scheduler has moved from
758 the body to the prologue.
760 In order to make sure that we scan all of the prologue
761 instructions, we use a slightly less accurate mechanism which
762 may scan more than necessary. To help compensate for this
763 lack of accuracy, the prologue scanning loop below contains
764 several clauses which'll cause the loop to terminate early if
765 an implausible prologue instruction is encountered.
771 is a suitable endpoint since it accounts for the largest
772 possible prologue plus up to five instructions inserted by
775 if (prologue_end
> prologue_start
+ 64)
777 prologue_end
= prologue_start
+ 64; /* See above. */
782 /* Get address of the stmfd in the prologue of the callee; the saved
783 PC is the address of the stmfd + 8. */
784 prologue_start
= ADDR_BITS_REMOVE (read_memory_integer (fi
->frame
, 4))
786 prologue_end
= prologue_start
+ 64; /* See above. */
789 /* Now search the prologue looking for instructions that set up the
790 frame pointer, adjust the stack pointer, and save registers.
792 Be careful, however, and if it doesn't look like a prologue,
793 don't try to scan it. If, for instance, a frameless function
794 begins with stmfd sp!, then we will tell ourselves there is
795 a frame, which will confuse stack traceback, as well ad"finish"
796 and other operations that rely on a knowledge of the stack
799 In the APCS, the prologue should start with "mov ip, sp" so
800 if we don't see this as the first insn, we will stop. */
802 sp_offset
= fp_offset
= 0;
804 if (read_memory_unsigned_integer (prologue_start
, 4)
805 == 0xe1a0c00d) /* mov ip, sp */
807 for (current_pc
= prologue_start
+ 4; current_pc
< prologue_end
;
810 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
812 if ((insn
& 0xffff0000) == 0xe92d0000)
813 /* stmfd sp!, {..., fp, ip, lr, pc}
815 stmfd sp!, {a1, a2, a3, a4} */
817 int mask
= insn
& 0xffff;
819 /* Calculate offsets of saved registers. */
820 for (regno
= PC_REGNUM
; regno
>= 0; regno
--)
821 if (mask
& (1 << regno
))
824 fi
->fsr
.regs
[regno
] = sp_offset
;
827 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
829 unsigned imm
= insn
& 0xff; /* immediate value */
830 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
831 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
833 fi
->framereg
= FP_REGNUM
;
835 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
837 unsigned imm
= insn
& 0xff; /* immediate value */
838 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
839 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
842 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
845 regno
= F0_REGNUM
+ ((insn
>> 12) & 0x07);
846 fi
->fsr
.regs
[regno
] = sp_offset
;
848 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
851 unsigned int fp_start_reg
, fp_bound_reg
;
853 if ((insn
& 0x800) == 0x800) /* N0 is set */
855 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
862 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
868 fp_start_reg
= F0_REGNUM
+ ((insn
>> 12) & 0x7);
869 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
870 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
873 fi
->fsr
.regs
[fp_start_reg
++] = sp_offset
;
876 else if ((insn
& 0xf0000000) != 0xe0000000)
877 break; /* Condition not true, exit early */
878 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
879 break; /* Don't scan past a block load */
881 /* The optimizer might shove anything into the prologue,
882 so we just skip what we don't recognize. */
887 /* The frame size is just the negative of the offset (from the original SP)
888 of the last thing thing we pushed on the stack. The frame offset is
889 [new FP] - [new SP]. */
890 fi
->framesize
= -sp_offset
;
891 fi
->frameoffset
= fp_offset
- sp_offset
;
893 save_prologue_cache (fi
);
896 /* Find REGNUM on the stack. Otherwise, it's in an active register.
897 One thing we might want to do here is to check REGNUM against the
898 clobber mask, and somehow flag it as invalid if it isn't saved on
899 the stack somewhere. This would provide a graceful failure mode
900 when trying to get the value of caller-saves registers for an inner
904 arm_find_callers_reg (struct frame_info
*fi
, int regnum
)
906 for (; fi
; fi
= fi
->next
)
908 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
909 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
910 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
913 if (fi
->fsr
.regs
[regnum
] != 0)
914 return read_memory_integer (fi
->fsr
.regs
[regnum
],
915 REGISTER_RAW_SIZE (regnum
));
916 return read_register (regnum
);
919 /* Function: frame_chain
920 Given a GDB frame, determine the address of the calling function's frame.
921 This will be used to create a new GDB frame struct, and then
922 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
923 For ARM, we save the frame size when we initialize the frame_info.
925 The original definition of this function was a macro in tm-arm.h:
926 { In the case of the ARM, the frame's nominal address is the FP value,
927 and 12 bytes before comes the saved previous FP value as a 4-byte word. }
929 #define FRAME_CHAIN(thisframe) \
930 ((thisframe)->pc >= LOWEST_PC ? \
931 read_memory_integer ((thisframe)->frame - 12, 4) :\
937 arm_frame_chain (struct frame_info
*fi
)
939 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
940 CORE_ADDR fn_start
, callers_pc
, fp
;
942 /* is this a dummy frame? */
943 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
944 return fi
->frame
; /* dummy frame same as caller's frame */
946 /* is caller-of-this a dummy frame? */
947 callers_pc
= FRAME_SAVED_PC (fi
); /* find out who called us: */
948 fp
= arm_find_callers_reg (fi
, FP_REGNUM
);
949 if (PC_IN_CALL_DUMMY (callers_pc
, fp
, fp
))
950 return fp
; /* dummy frame's frame may bear no relation to ours */
952 if (find_pc_partial_function (fi
->pc
, 0, &fn_start
, 0))
953 if (fn_start
== entry_point_address ())
954 return 0; /* in _start fn, don't chain further */
956 CORE_ADDR caller_pc
, fn_start
;
957 struct frame_info caller_fi
;
958 int framereg
= fi
->framereg
;
960 if (fi
->pc
< LOWEST_PC
)
963 /* If the caller is the startup code, we're at the end of the chain. */
964 caller_pc
= FRAME_SAVED_PC (fi
);
965 if (find_pc_partial_function (caller_pc
, 0, &fn_start
, 0))
966 if (fn_start
== entry_point_address ())
969 /* If the caller is Thumb and the caller is ARM, or vice versa,
970 the frame register of the caller is different from ours.
971 So we must scan the prologue of the caller to determine its
972 frame register number. */
973 if (arm_pc_is_thumb (caller_pc
) != arm_pc_is_thumb (fi
->pc
))
975 memset (&caller_fi
, 0, sizeof (caller_fi
));
976 caller_fi
.pc
= caller_pc
;
977 arm_scan_prologue (&caller_fi
);
978 framereg
= caller_fi
.framereg
;
981 /* If the caller used a frame register, return its value.
982 Otherwise, return the caller's stack pointer. */
983 if (framereg
== FP_REGNUM
|| framereg
== THUMB_FP_REGNUM
)
984 return arm_find_callers_reg (fi
, framereg
);
986 return fi
->frame
+ fi
->framesize
;
989 /* This function actually figures out the frame address for a given pc
990 and sp. This is tricky because we sometimes don't use an explicit
991 frame pointer, and the previous stack pointer isn't necessarily
992 recorded on the stack. The only reliable way to get this info is
993 to examine the prologue. FROMLEAF is a little confusing, it means
994 this is the next frame up the chain AFTER a frameless function. If
995 this is true, then the frame value for this frame is still in the
999 arm_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1004 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1006 memset (fi
->fsr
.regs
, '\000', sizeof fi
->fsr
.regs
);
1008 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1009 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1011 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1012 by assuming it's always FP. */
1013 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
, SP_REGNUM
);
1015 fi
->frameoffset
= 0;
1021 /* Determine whether or not we're in a sigtramp frame.
1022 Unfortunately, it isn't sufficient to test
1023 fi->signal_handler_caller because this value is sometimes set
1024 after invoking INIT_EXTRA_FRAME_INFO. So we test *both*
1025 fi->signal_handler_caller and IN_SIGTRAMP to determine if we need
1026 to use the sigcontext addresses for the saved registers.
1028 Note: If an ARM IN_SIGTRAMP method ever needs to compare against
1029 the name of the function, the code below will have to be changed
1030 to first fetch the name of the function and then pass this name
1033 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1034 && (fi
->signal_handler_caller
|| IN_SIGTRAMP (fi
->pc
, 0)))
1041 sp
= fi
->next
->frame
- fi
->next
->frameoffset
+ fi
->next
->framesize
;
1043 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1044 fi
->fsr
.regs
[reg
] = SIGCONTEXT_REGISTER_ADDRESS (sp
, fi
->pc
, reg
);
1046 /* FIXME: What about thumb mode? */
1047 fi
->framereg
= SP_REGNUM
;
1048 fi
->frame
= read_memory_integer (fi
->fsr
.regs
[fi
->framereg
], 4);
1050 fi
->frameoffset
= 0;
1055 arm_scan_prologue (fi
);
1058 /* this is the innermost frame? */
1059 fi
->frame
= read_register (fi
->framereg
);
1060 else if (fi
->framereg
== FP_REGNUM
|| fi
->framereg
== THUMB_FP_REGNUM
)
1062 /* not the innermost frame */
1063 /* If we have an FP, the callee saved it. */
1064 if (fi
->next
->fsr
.regs
[fi
->framereg
] != 0)
1066 read_memory_integer (fi
->next
->fsr
.regs
[fi
->framereg
], 4);
1068 /* If we were called by a frameless fn. then our frame is
1069 still in the frame pointer register on the board... */
1070 fi
->frame
= read_fp ();
1073 /* Calculate actual addresses of saved registers using offsets
1074 determined by arm_scan_prologue. */
1075 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1076 if (fi
->fsr
.regs
[reg
] != 0)
1077 fi
->fsr
.regs
[reg
] += fi
->frame
+ fi
->framesize
- fi
->frameoffset
;
1082 /* Find the caller of this frame. We do this by seeing if LR_REGNUM
1083 is saved in the stack anywhere, otherwise we get it from the
1086 The old definition of this function was a macro:
1087 #define FRAME_SAVED_PC(FRAME) \
1088 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1091 arm_frame_saved_pc (struct frame_info
*fi
)
1093 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1094 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1095 return generic_read_register_dummy (fi
->pc
, fi
->frame
, PC_REGNUM
);
1099 CORE_ADDR pc
= arm_find_callers_reg (fi
, LR_REGNUM
);
1100 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1104 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1105 Examine the Program Status Register to decide which state we're in. */
1108 arm_target_read_fp (void)
1110 if (read_register (PS_REGNUM
) & 0x20) /* Bit 5 is Thumb state bit */
1111 return read_register (THUMB_FP_REGNUM
); /* R7 if Thumb */
1113 return read_register (FP_REGNUM
); /* R11 if ARM */
1116 /* Calculate the frame offsets of the saved registers (ARM version). */
1119 arm_frame_find_saved_regs (struct frame_info
*fi
,
1120 struct frame_saved_regs
*regaddr
)
1122 memcpy (regaddr
, &fi
->fsr
, sizeof (struct frame_saved_regs
));
1126 arm_push_dummy_frame (void)
1128 CORE_ADDR old_sp
= read_register (SP_REGNUM
);
1129 CORE_ADDR sp
= old_sp
;
1130 CORE_ADDR fp
, prologue_start
;
1133 /* Push the two dummy prologue instructions in reverse order,
1134 so that they'll be in the correct low-to-high order in memory. */
1135 /* sub fp, ip, #4 */
1136 sp
= push_word (sp
, 0xe24cb004);
1137 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1138 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
1140 /* Push a pointer to the dummy prologue + 12, because when stm
1141 instruction stores the PC, it stores the address of the stm
1142 instruction itself plus 12. */
1143 fp
= sp
= push_word (sp
, prologue_start
+ 12);
1144 sp
= push_word (sp
, read_register (PC_REGNUM
)); /* FIXME: was PS_REGNUM */
1145 sp
= push_word (sp
, old_sp
);
1146 sp
= push_word (sp
, read_register (FP_REGNUM
));
1148 for (regnum
= 10; regnum
>= 0; regnum
--)
1149 sp
= push_word (sp
, read_register (regnum
));
1151 write_register (FP_REGNUM
, fp
);
1152 write_register (THUMB_FP_REGNUM
, fp
);
1153 write_register (SP_REGNUM
, sp
);
1156 /* Fix up the call dummy, based on whether the processor is currently
1157 in Thumb or ARM mode, and whether the target function is Thumb or
1158 ARM. There are three different situations requiring three
1161 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1162 been copied into the dummy parameter to this function.
1163 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1164 "mov pc,r4" instruction patched to be a "bx r4" instead.
1165 * Thumb calling anything: uses the Thumb dummy defined below, which
1166 works for calling both ARM and Thumb functions.
1168 All three call dummies expect to receive the target function
1169 address in R4, with the low bit set if it's a Thumb function. */
1172 arm_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
1173 struct value
**args
, struct type
*type
, int gcc_p
)
1175 static short thumb_dummy
[4] =
1177 0xf000, 0xf801, /* bl label */
1178 0xdf18, /* swi 24 */
1179 0x4720, /* label: bx r4 */
1181 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
1183 /* Set flag indicating whether the current PC is in a Thumb function. */
1184 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
1186 /* If the target function is Thumb, set the low bit of the function
1187 address. And if the CPU is currently in ARM mode, patch the
1188 second instruction of call dummy to use a BX instruction to
1189 switch to Thumb mode. */
1190 target_is_thumb
= arm_pc_is_thumb (fun
);
1191 if (target_is_thumb
)
1194 if (!caller_is_thumb
)
1195 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
1198 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1199 instead of the ARM one that's already been copied. This will
1200 work for both Thumb and ARM target functions. */
1201 if (caller_is_thumb
)
1205 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
1207 for (i
= 0; i
< len
; i
++)
1209 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1210 p
+= sizeof (thumb_dummy
[0]);
1214 /* Put the target address in r4; the call dummy will copy this to
1216 write_register (4, fun
);
1219 /* Return the offset in the call dummy of the instruction that needs
1220 to have a breakpoint placed on it. This is the offset of the 'swi
1221 24' instruction, which is no longer actually used, but simply acts
1222 as a place-holder now.
1224 This implements the CALL_DUMMY_BREAK_OFFSET macro. */
1227 arm_call_dummy_breakpoint_offset (void)
1229 if (caller_is_thumb
)
1237 This function does not support passing parameters using the FPA
1238 variant of the APCS. It passes any floating point arguments in the
1239 general registers and/or on the stack. */
1242 arm_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
1243 int struct_return
, CORE_ADDR struct_addr
)
1246 int argnum
, argreg
, nstack_size
;
1248 /* Walk through the list of args and determine how large a temporary
1249 stack is required. Need to take care here as structs may be
1250 passed on the stack, and we have to to push them. */
1251 nstack_size
= -4 * REGISTER_SIZE
; /* Some arguments go into A1-A4. */
1252 if (struct_return
) /* The struct address goes in A1. */
1253 nstack_size
+= REGISTER_SIZE
;
1255 /* Walk through the arguments and add their size to nstack_size. */
1256 for (argnum
= 0; argnum
< nargs
; argnum
++)
1259 struct type
*arg_type
;
1261 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1262 len
= TYPE_LENGTH (arg_type
);
1264 /* ANSI C code passes float arguments as integers, K&R code
1265 passes float arguments as doubles. Correct for this here. */
1266 if (TYPE_CODE_FLT
== TYPE_CODE (arg_type
) && REGISTER_SIZE
== len
)
1267 nstack_size
+= FP_REGISTER_VIRTUAL_SIZE
;
1272 /* Allocate room on the stack, and initialize our stack frame
1275 if (nstack_size
> 0)
1281 /* Initialize the integer argument register pointer. */
1284 /* The struct_return pointer occupies the first parameter passing
1287 write_register (argreg
++, struct_addr
);
1289 /* Process arguments from left to right. Store as many as allowed
1290 in the parameter passing registers (A1-A4), and save the rest on
1291 the temporary stack. */
1292 for (argnum
= 0; argnum
< nargs
; argnum
++)
1297 enum type_code typecode
;
1298 struct type
*arg_type
, *target_type
;
1300 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1301 target_type
= TYPE_TARGET_TYPE (arg_type
);
1302 len
= TYPE_LENGTH (arg_type
);
1303 typecode
= TYPE_CODE (arg_type
);
1304 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
1306 /* ANSI C code passes float arguments as integers, K&R code
1307 passes float arguments as doubles. The .stabs record for
1308 for ANSI prototype floating point arguments records the
1309 type as FP_INTEGER, while a K&R style (no prototype)
1310 .stabs records the type as FP_FLOAT. In this latter case
1311 the compiler converts the float arguments to double before
1312 calling the function. */
1313 if (TYPE_CODE_FLT
== typecode
&& REGISTER_SIZE
== len
)
1316 dblval
= extract_floating (val
, len
);
1317 len
= TARGET_DOUBLE_BIT
/ TARGET_CHAR_BIT
;
1319 store_floating (val
, len
, dblval
);
1322 /* I don't know why this code was disable. The only logical use
1323 for a function pointer is to call that function, so setting
1324 the mode bit is perfectly fine. FN */
1325 /* If the argument is a pointer to a function, and it is a Thumb
1326 function, set the low bit of the pointer. */
1327 if (TYPE_CODE_PTR
== typecode
1328 && NULL
!= target_type
1329 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1331 CORE_ADDR regval
= extract_address (val
, len
);
1332 if (arm_pc_is_thumb (regval
))
1333 store_address (val
, len
, MAKE_THUMB_ADDR (regval
));
1336 /* Copy the argument to general registers or the stack in
1337 register-sized pieces. Large arguments are split between
1338 registers and stack. */
1341 int partial_len
= len
< REGISTER_SIZE
? len
: REGISTER_SIZE
;
1343 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1345 /* It's an argument being passed in a general register. */
1346 regval
= extract_address (val
, partial_len
);
1347 write_register (argreg
++, regval
);
1351 /* Push the arguments onto the stack. */
1352 write_memory ((CORE_ADDR
) fp
, val
, REGISTER_SIZE
);
1353 fp
+= REGISTER_SIZE
;
1361 /* Return adjusted stack pointer. */
1366 arm_pop_frame (void)
1369 struct frame_info
*frame
= get_current_frame ();
1371 if (!PC_IN_CALL_DUMMY(frame
->pc
, frame
->frame
, read_fp()))
1375 old_SP
= read_register (frame
->framereg
);
1376 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1377 if (frame
->fsr
.regs
[regnum
] != 0)
1378 write_register (regnum
,
1379 read_memory_integer (frame
->fsr
.regs
[regnum
], 4));
1381 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
1382 write_register (SP_REGNUM
, old_SP
);
1388 sp
= read_register (FP_REGNUM
);
1389 sp
-= sizeof(CORE_ADDR
); /* we don't care about this first word */
1391 write_register (PC_REGNUM
, read_memory_integer (sp
, 4));
1392 sp
-= sizeof(CORE_ADDR
);
1393 write_register (SP_REGNUM
, read_memory_integer (sp
, 4));
1394 sp
-= sizeof(CORE_ADDR
);
1395 write_register (FP_REGNUM
, read_memory_integer (sp
, 4));
1396 sp
-= sizeof(CORE_ADDR
);
1398 for (regnum
= 10; regnum
>= 0; regnum
--)
1400 write_register (regnum
, read_memory_integer (sp
, 4));
1401 sp
-= sizeof(CORE_ADDR
);
1405 flush_cached_frames ();
1409 print_fpu_flags (int flags
)
1411 if (flags
& (1 << 0))
1412 fputs ("IVO ", stdout
);
1413 if (flags
& (1 << 1))
1414 fputs ("DVZ ", stdout
);
1415 if (flags
& (1 << 2))
1416 fputs ("OFL ", stdout
);
1417 if (flags
& (1 << 3))
1418 fputs ("UFL ", stdout
);
1419 if (flags
& (1 << 4))
1420 fputs ("INX ", stdout
);
1425 arm_float_info (void)
1427 register unsigned long status
= read_register (FPS_REGNUM
);
1430 type
= (status
>> 24) & 127;
1431 printf ("%s FPU type %d\n",
1432 (status
& (1 << 31)) ? "Hardware" : "Software",
1434 fputs ("mask: ", stdout
);
1435 print_fpu_flags (status
>> 16);
1436 fputs ("flags: ", stdout
);
1437 print_fpu_flags (status
);
1441 arm_register_type (int regnum
)
1443 if (regnum
>= F0_REGNUM
&& regnum
< F0_REGNUM
+ NUM_FREGS
)
1445 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1446 return builtin_type_arm_ext_big
;
1448 return builtin_type_arm_ext_littlebyte_bigword
;
1451 return builtin_type_int32
;
1454 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1455 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1456 It is thought that this is is the floating-point register format on
1457 little-endian systems. */
1460 convert_from_extended (void *ptr
, void *dbl
)
1463 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1464 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1466 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1468 floatformat_from_doublest (TARGET_DOUBLE_FORMAT
, &d
, dbl
);
1472 convert_to_extended (void *dbl
, void *ptr
)
1475 floatformat_to_doublest (TARGET_DOUBLE_FORMAT
, ptr
, &d
);
1476 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1477 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1479 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1484 condition_true (unsigned long cond
, unsigned long status_reg
)
1486 if (cond
== INST_AL
|| cond
== INST_NV
)
1492 return ((status_reg
& FLAG_Z
) != 0);
1494 return ((status_reg
& FLAG_Z
) == 0);
1496 return ((status_reg
& FLAG_C
) != 0);
1498 return ((status_reg
& FLAG_C
) == 0);
1500 return ((status_reg
& FLAG_N
) != 0);
1502 return ((status_reg
& FLAG_N
) == 0);
1504 return ((status_reg
& FLAG_V
) != 0);
1506 return ((status_reg
& FLAG_V
) == 0);
1508 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1510 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1512 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1514 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1516 return (((status_reg
& FLAG_Z
) == 0) &&
1517 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1519 return (((status_reg
& FLAG_Z
) != 0) ||
1520 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1525 #define submask(x) ((1L << ((x) + 1)) - 1)
1526 #define bit(obj,st) (((obj) >> (st)) & 1)
1527 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1528 #define sbits(obj,st,fn) \
1529 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1530 #define BranchDest(addr,instr) \
1531 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1534 static unsigned long
1535 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1536 unsigned long status_reg
)
1538 unsigned long res
, shift
;
1539 int rm
= bits (inst
, 0, 3);
1540 unsigned long shifttype
= bits (inst
, 5, 6);
1544 int rs
= bits (inst
, 8, 11);
1545 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1548 shift
= bits (inst
, 7, 11);
1551 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1552 + (bit (inst
, 4) ? 12 : 8))
1553 : read_register (rm
));
1558 res
= shift
>= 32 ? 0 : res
<< shift
;
1562 res
= shift
>= 32 ? 0 : res
>> shift
;
1568 res
= ((res
& 0x80000000L
)
1569 ? ~((~res
) >> shift
) : res
>> shift
);
1572 case 3: /* ROR/RRX */
1575 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1577 res
= (res
>> shift
) | (res
<< (32 - shift
));
1581 return res
& 0xffffffff;
1584 /* Return number of 1-bits in VAL. */
1587 bitcount (unsigned long val
)
1590 for (nbits
= 0; val
!= 0; nbits
++)
1591 val
&= val
- 1; /* delete rightmost 1-bit in val */
1596 thumb_get_next_pc (CORE_ADDR pc
)
1598 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1599 unsigned short inst1
= read_memory_integer (pc
, 2);
1600 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1601 unsigned long offset
;
1603 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1607 /* Fetch the saved PC from the stack. It's stored above
1608 all of the other registers. */
1609 offset
= bitcount (bits (inst1
, 0, 7)) * REGISTER_SIZE
;
1610 sp
= read_register (SP_REGNUM
);
1611 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1612 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1614 error ("Infinite loop detected");
1616 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1618 unsigned long status
= read_register (PS_REGNUM
);
1619 unsigned long cond
= bits (inst1
, 8, 11);
1620 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1621 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1623 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1625 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1627 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1629 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1630 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1631 nextpc
= pc_val
+ offset
;
1638 arm_get_next_pc (CORE_ADDR pc
)
1640 unsigned long pc_val
;
1641 unsigned long this_instr
;
1642 unsigned long status
;
1645 if (arm_pc_is_thumb (pc
))
1646 return thumb_get_next_pc (pc
);
1648 pc_val
= (unsigned long) pc
;
1649 this_instr
= read_memory_integer (pc
, 4);
1650 status
= read_register (PS_REGNUM
);
1651 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1653 if (condition_true (bits (this_instr
, 28, 31), status
))
1655 switch (bits (this_instr
, 24, 27))
1658 case 0x1: /* data processing */
1662 unsigned long operand1
, operand2
, result
= 0;
1666 if (bits (this_instr
, 12, 15) != 15)
1669 if (bits (this_instr
, 22, 25) == 0
1670 && bits (this_instr
, 4, 7) == 9) /* multiply */
1671 error ("Illegal update to pc in instruction");
1673 /* Multiply into PC */
1674 c
= (status
& FLAG_C
) ? 1 : 0;
1675 rn
= bits (this_instr
, 16, 19);
1676 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1678 if (bit (this_instr
, 25))
1680 unsigned long immval
= bits (this_instr
, 0, 7);
1681 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1682 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1685 else /* operand 2 is a shifted register */
1686 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1688 switch (bits (this_instr
, 21, 24))
1691 result
= operand1
& operand2
;
1695 result
= operand1
^ operand2
;
1699 result
= operand1
- operand2
;
1703 result
= operand2
- operand1
;
1707 result
= operand1
+ operand2
;
1711 result
= operand1
+ operand2
+ c
;
1715 result
= operand1
- operand2
+ c
;
1719 result
= operand2
- operand1
+ c
;
1725 case 0xb: /* tst, teq, cmp, cmn */
1726 result
= (unsigned long) nextpc
;
1730 result
= operand1
| operand2
;
1734 /* Always step into a function. */
1739 result
= operand1
& ~operand2
;
1746 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1749 error ("Infinite loop detected");
1754 case 0x5: /* data transfer */
1757 if (bit (this_instr
, 20))
1760 if (bits (this_instr
, 12, 15) == 15)
1766 if (bit (this_instr
, 22))
1767 error ("Illegal update to pc in instruction");
1769 /* byte write to PC */
1770 rn
= bits (this_instr
, 16, 19);
1771 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1772 if (bit (this_instr
, 24))
1775 int c
= (status
& FLAG_C
) ? 1 : 0;
1776 unsigned long offset
=
1777 (bit (this_instr
, 25)
1778 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1779 : bits (this_instr
, 0, 11));
1781 if (bit (this_instr
, 23))
1786 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1789 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1792 error ("Infinite loop detected");
1798 case 0x9: /* block transfer */
1799 if (bit (this_instr
, 20))
1802 if (bit (this_instr
, 15))
1807 if (bit (this_instr
, 23))
1810 unsigned long reglist
= bits (this_instr
, 0, 14);
1811 offset
= bitcount (reglist
) * 4;
1812 if (bit (this_instr
, 24)) /* pre */
1815 else if (bit (this_instr
, 24))
1819 unsigned long rn_val
=
1820 read_register (bits (this_instr
, 16, 19));
1822 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1826 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1828 error ("Infinite loop detected");
1833 case 0xb: /* branch & link */
1834 case 0xa: /* branch */
1836 nextpc
= BranchDest (pc
, this_instr
);
1838 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1840 error ("Infinite loop detected");
1846 case 0xe: /* coproc ops */
1851 fprintf (stderr
, "Bad bit-field extraction\n");
1859 #include "bfd-in2.h"
1860 #include "libcoff.h"
1863 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
1865 if (arm_pc_is_thumb (memaddr
))
1867 static asymbol
*asym
;
1868 static combined_entry_type ce
;
1869 static struct coff_symbol_struct csym
;
1870 static struct _bfd fake_bfd
;
1871 static bfd_target fake_target
;
1873 if (csym
.native
== NULL
)
1875 /* Create a fake symbol vector containing a Thumb symbol. This is
1876 solely so that the code in print_insn_little_arm() and
1877 print_insn_big_arm() in opcodes/arm-dis.c will detect the presence
1878 of a Thumb symbol and switch to decoding Thumb instructions. */
1880 fake_target
.flavour
= bfd_target_coff_flavour
;
1881 fake_bfd
.xvec
= &fake_target
;
1882 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
1884 csym
.symbol
.the_bfd
= &fake_bfd
;
1885 csym
.symbol
.name
= "fake";
1886 asym
= (asymbol
*) & csym
;
1889 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
1890 info
->symbols
= &asym
;
1893 info
->symbols
= NULL
;
1895 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1896 return print_insn_big_arm (memaddr
, info
);
1898 return print_insn_little_arm (memaddr
, info
);
1901 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the
1902 program counter value to determine whether a 16-bit or 32-bit
1903 breakpoint should be used. It returns a pointer to a string of
1904 bytes that encode a breakpoint instruction, stores the length of
1905 the string to *lenptr, and adjusts the program counter (if
1906 necessary) to point to the actual memory location where the
1907 breakpoint should be inserted. */
1910 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1912 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
1914 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1916 static char thumb_breakpoint
[] = THUMB_BE_BREAKPOINT
;
1917 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1918 *lenptr
= sizeof (thumb_breakpoint
);
1919 return thumb_breakpoint
;
1923 static char thumb_breakpoint
[] = THUMB_LE_BREAKPOINT
;
1924 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1925 *lenptr
= sizeof (thumb_breakpoint
);
1926 return thumb_breakpoint
;
1931 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1933 static char arm_breakpoint
[] = ARM_BE_BREAKPOINT
;
1934 *lenptr
= sizeof (arm_breakpoint
);
1935 return arm_breakpoint
;
1939 static char arm_breakpoint
[] = ARM_LE_BREAKPOINT
;
1940 *lenptr
= sizeof (arm_breakpoint
);
1941 return arm_breakpoint
;
1946 /* Extract from an array REGBUF containing the (raw) register state a
1947 function return value of type TYPE, and copy that, in virtual
1948 format, into VALBUF. */
1951 arm_extract_return_value (struct type
*type
,
1952 char regbuf
[REGISTER_BYTES
],
1955 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
1956 convert_from_extended (®buf
[REGISTER_BYTE (F0_REGNUM
)], valbuf
);
1958 memcpy (valbuf
, ®buf
[REGISTER_BYTE (A1_REGNUM
)], TYPE_LENGTH (type
));
1961 /* Return non-zero if the PC is inside a thumb call thunk. */
1964 arm_in_call_stub (CORE_ADDR pc
, char *name
)
1966 CORE_ADDR start_addr
;
1968 /* Find the starting address of the function containing the PC. If
1969 the caller didn't give us a name, look it up at the same time. */
1970 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
1973 return strncmp (name
, "_call_via_r", 11) == 0;
1976 /* If PC is in a Thumb call or return stub, return the address of the
1977 target PC, which is in a register. The thunk functions are called
1978 _called_via_xx, where x is the register name. The possible names
1979 are r0-r9, sl, fp, ip, sp, and lr. */
1982 arm_skip_stub (CORE_ADDR pc
)
1985 CORE_ADDR start_addr
;
1987 /* Find the starting address and name of the function containing the PC. */
1988 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1991 /* Call thunks always start with "_call_via_". */
1992 if (strncmp (name
, "_call_via_", 10) == 0)
1994 /* Use the name suffix to determine which register contains the
1996 static char *table
[15] =
1997 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1998 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2002 for (regno
= 0; regno
<= 14; regno
++)
2003 if (strcmp (&name
[10], table
[regno
]) == 0)
2004 return read_register (regno
);
2007 return 0; /* not a stub */
2010 /* If the user changes the register disassembly flavor used for info register
2011 and other commands, we have to also switch the flavor used in opcodes
2012 for disassembly output.
2013 This function is run in the set disassembly_flavor command, and does that. */
2016 set_disassembly_flavor_sfunc (char *args
, int from_tty
,
2017 struct cmd_list_element
*c
)
2019 set_disassembly_flavor ();
2023 set_disassembly_flavor (void)
2025 const char *setname
, *setdesc
, **regnames
;
2028 /* Find the flavor that the user wants in the opcodes table. */
2030 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2031 while ((disassembly_flavor
!= setname
)
2032 && (current
< num_flavor_options
))
2033 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2034 current_option
= current
;
2036 /* Fill our copy. */
2037 for (j
= 0; j
< numregs
; j
++)
2038 arm_register_names
[j
] = (char *) regnames
[j
];
2041 if (isupper (*regnames
[PC_REGNUM
]))
2043 arm_register_names
[FPS_REGNUM
] = "FPS";
2044 arm_register_names
[PS_REGNUM
] = "CPSR";
2048 arm_register_names
[FPS_REGNUM
] = "fps";
2049 arm_register_names
[PS_REGNUM
] = "cpsr";
2052 /* Synchronize the disassembler. */
2053 set_arm_regname_option (current
);
2056 /* arm_othernames implements the "othernames" command. This is kind
2057 of hacky, and I prefer the set-show disassembly-flavor which is
2058 also used for the x86 gdb. I will keep this around, however, in
2059 case anyone is actually using it. */
2062 arm_othernames (char *names
, int n
)
2064 /* Circle through the various flavors. */
2065 current_option
= (current_option
+ 1) % num_flavor_options
;
2067 disassembly_flavor
= valid_flavors
[current_option
];
2068 set_disassembly_flavor ();
2072 _initialize_arm_tdep (void)
2074 struct ui_file
*stb
;
2076 struct cmd_list_element
*new_cmd
;
2077 const char *setname
;
2078 const char *setdesc
;
2079 const char **regnames
;
2081 static char *helptext
;
2083 tm_print_insn
= gdb_print_insn_arm
;
2085 /* Get the number of possible sets of register names defined in opcodes. */
2086 num_flavor_options
= get_arm_regname_num_options ();
2088 /* Sync the opcode insn printer with our register viewer: */
2089 parse_arm_disassembler_option ("reg-names-std");
2091 /* Begin creating the help text. */
2092 stb
= mem_fileopen ();
2093 fprintf_unfiltered (stb
, "Set the disassembly flavor.\n\
2094 The valid values are:\n");
2096 /* Initialize the array that will be passed to add_set_enum_cmd(). */
2097 valid_flavors
= xmalloc ((num_flavor_options
+ 1) * sizeof (char *));
2098 for (i
= 0; i
< num_flavor_options
; i
++)
2100 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
2101 valid_flavors
[i
] = setname
;
2102 fprintf_unfiltered (stb
, "%s - %s\n", setname
,
2104 /* Copy the default names (if found) and synchronize disassembler. */
2105 if (!strcmp (setname
, "std"))
2107 disassembly_flavor
= setname
;
2109 for (j
= 0; j
< numregs
; j
++)
2110 arm_register_names
[j
] = (char *) regnames
[j
];
2111 set_arm_regname_option (i
);
2114 /* Mark the end of valid options. */
2115 valid_flavors
[num_flavor_options
] = NULL
;
2117 /* Finish the creation of the help text. */
2118 fprintf_unfiltered (stb
, "The default is \"std\".");
2119 helptext
= ui_file_xstrdup (stb
, &length
);
2120 ui_file_delete (stb
);
2122 /* Add the disassembly-flavor command */
2123 new_cmd
= add_set_enum_cmd ("disassembly-flavor", no_class
,
2125 &disassembly_flavor
,
2128 new_cmd
->function
.sfunc
= set_disassembly_flavor_sfunc
;
2129 add_show_from_set (new_cmd
, &showlist
);
2131 /* ??? Maybe this should be a boolean. */
2132 add_show_from_set (add_set_cmd ("apcs32", no_class
,
2133 var_zinteger
, (char *) &arm_apcs_32
,
2134 "Set usage of ARM 32-bit mode.\n", &setlist
),
2137 /* Add the deprecated "othernames" command */
2139 add_com ("othernames", class_obscure
, arm_othernames
,
2140 "Switch to the next set of register names.");
2143 /* Test whether the coff symbol specific value corresponds to a Thumb
2147 coff_sym_is_thumb (int val
)
2149 return (val
== C_THUMBEXT
||
2150 val
== C_THUMBSTAT
||
2151 val
== C_THUMBEXTFUNC
||
2152 val
== C_THUMBSTATFUNC
||
2153 val
== C_THUMBLABEL
);