1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
31 #include "reggroups.h"
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "arch/arm-get-next-pcs.h"
51 #include "gdb/sim-arm.h"
54 #include "coff/internal.h"
60 #include "record-full.h"
63 #include "features/arm/arm-with-m.c"
64 #include "features/arm/arm-with-m-fpa-layout.c"
65 #include "features/arm/arm-with-m-vfp-d16.c"
66 #include "features/arm/arm-with-iwmmxt.c"
67 #include "features/arm/arm-with-vfpv2.c"
68 #include "features/arm/arm-with-vfpv3.c"
69 #include "features/arm/arm-with-neon.c"
73 /* Macros for setting and testing a bit in a minimal symbol that marks
74 it as Thumb function. The MSB of the minimal symbol's "info" field
75 is used for this purpose.
77 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
78 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
80 #define MSYMBOL_SET_SPECIAL(msym) \
81 MSYMBOL_TARGET_FLAG_1 (msym) = 1
83 #define MSYMBOL_IS_SPECIAL(msym) \
84 MSYMBOL_TARGET_FLAG_1 (msym)
86 /* Per-objfile data used for mapping symbols. */
87 static const struct objfile_data
*arm_objfile_data_key
;
89 struct arm_mapping_symbol
94 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
95 DEF_VEC_O(arm_mapping_symbol_s
);
97 struct arm_per_objfile
99 VEC(arm_mapping_symbol_s
) **section_maps
;
102 /* The list of available "set arm ..." and "show arm ..." commands. */
103 static struct cmd_list_element
*setarmcmdlist
= NULL
;
104 static struct cmd_list_element
*showarmcmdlist
= NULL
;
106 /* The type of floating-point to use. Keep this in sync with enum
107 arm_float_model, and the help string in _initialize_arm_tdep. */
108 static const char *const fp_model_strings
[] =
118 /* A variable that can be configured by the user. */
119 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
120 static const char *current_fp_model
= "auto";
122 /* The ABI to use. Keep this in sync with arm_abi_kind. */
123 static const char *const arm_abi_strings
[] =
131 /* A variable that can be configured by the user. */
132 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
133 static const char *arm_abi_string
= "auto";
135 /* The execution mode to assume. */
136 static const char *const arm_mode_strings
[] =
144 static const char *arm_fallback_mode_string
= "auto";
145 static const char *arm_force_mode_string
= "auto";
147 /* Number of different reg name sets (options). */
148 static int num_disassembly_options
;
150 /* The standard register names, and all the valid aliases for them. Note
151 that `fp', `sp' and `pc' are not added in this alias list, because they
152 have been added as builtin user registers in
153 std-regs.c:_initialize_frame_reg. */
158 } arm_register_aliases
[] = {
159 /* Basic register numbers. */
176 /* Synonyms (argument and variable registers). */
189 /* Other platform-specific names for r9. */
195 /* Names used by GCC (not listed in the ARM EABI). */
197 /* A special name from the older ATPCS. */
201 static const char *const arm_register_names
[] =
202 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
203 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
204 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
205 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
206 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
207 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
208 "fps", "cpsr" }; /* 24 25 */
210 /* Valid register name styles. */
211 static const char **valid_disassembly_styles
;
213 /* Disassembly style to use. Default to "std" register names. */
214 static const char *disassembly_style
;
216 /* This is used to keep the bfd arch_info in sync with the disassembly
218 static void set_disassembly_style_sfunc(char *, int,
219 struct cmd_list_element
*);
220 static void set_disassembly_style (void);
222 static void convert_from_extended (const struct floatformat
*, const void *,
224 static void convert_to_extended (const struct floatformat
*, void *,
227 static enum register_status
arm_neon_quad_read (struct gdbarch
*gdbarch
,
228 struct regcache
*regcache
,
229 int regnum
, gdb_byte
*buf
);
230 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
231 struct regcache
*regcache
,
232 int regnum
, const gdb_byte
*buf
);
235 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
);
238 /* get_next_pcs operations. */
239 static struct arm_get_next_pcs_ops arm_get_next_pcs_ops
= {
240 arm_get_next_pcs_read_memory_unsigned_integer
,
241 arm_get_next_pcs_syscall_next_pc
,
242 arm_get_next_pcs_addr_bits_remove
,
243 arm_get_next_pcs_is_thumb
,
247 struct arm_prologue_cache
249 /* The stack pointer at the time this frame was created; i.e. the
250 caller's stack pointer when this function was called. It is used
251 to identify this frame. */
254 /* The frame base for this frame is just prev_sp - frame size.
255 FRAMESIZE is the distance from the frame pointer to the
256 initial stack pointer. */
260 /* The register used to hold the frame pointer for this frame. */
263 /* Saved register offsets. */
264 struct trad_frame_saved_reg
*saved_regs
;
267 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
268 CORE_ADDR prologue_start
,
269 CORE_ADDR prologue_end
,
270 struct arm_prologue_cache
*cache
);
272 /* Architecture version for displaced stepping. This effects the behaviour of
273 certain instructions, and really should not be hard-wired. */
275 #define DISPLACED_STEPPING_ARCH_VERSION 5
277 /* Set to true if the 32-bit mode is in use. */
281 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
284 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
286 if (gdbarch_tdep (gdbarch
)->is_m
)
292 /* Determine if the processor is currently executing in Thumb mode. */
295 arm_is_thumb (struct regcache
*regcache
)
298 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regcache
));
300 cpsr
= regcache_raw_get_unsigned (regcache
, ARM_PS_REGNUM
);
302 return (cpsr
& t_bit
) != 0;
305 /* Determine if FRAME is executing in Thumb mode. */
308 arm_frame_is_thumb (struct frame_info
*frame
)
311 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
313 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
314 directly (from a signal frame or dummy frame) or by interpreting
315 the saved LR (from a prologue or DWARF frame). So consult it and
316 trust the unwinders. */
317 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
319 return (cpsr
& t_bit
) != 0;
322 /* Callback for VEC_lower_bound. */
325 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
326 const struct arm_mapping_symbol
*rhs
)
328 return lhs
->value
< rhs
->value
;
331 /* Search for the mapping symbol covering MEMADDR. If one is found,
332 return its type. Otherwise, return 0. If START is non-NULL,
333 set *START to the location of the mapping symbol. */
336 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
338 struct obj_section
*sec
;
340 /* If there are mapping symbols, consult them. */
341 sec
= find_pc_section (memaddr
);
344 struct arm_per_objfile
*data
;
345 VEC(arm_mapping_symbol_s
) *map
;
346 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
350 data
= (struct arm_per_objfile
*) objfile_data (sec
->objfile
,
351 arm_objfile_data_key
);
354 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
355 if (!VEC_empty (arm_mapping_symbol_s
, map
))
357 struct arm_mapping_symbol
*map_sym
;
359 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
360 arm_compare_mapping_symbols
);
362 /* VEC_lower_bound finds the earliest ordered insertion
363 point. If the following symbol starts at this exact
364 address, we use that; otherwise, the preceding
365 mapping symbol covers this address. */
366 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
368 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
369 if (map_sym
->value
== map_key
.value
)
372 *start
= map_sym
->value
+ obj_section_addr (sec
);
373 return map_sym
->type
;
379 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
381 *start
= map_sym
->value
+ obj_section_addr (sec
);
382 return map_sym
->type
;
391 /* Determine if the program counter specified in MEMADDR is in a Thumb
392 function. This function should be called for addresses unrelated to
393 any executing frame; otherwise, prefer arm_frame_is_thumb. */
396 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
398 struct bound_minimal_symbol sym
;
400 struct displaced_step_closure
* dsc
401 = get_displaced_step_closure_by_addr(memaddr
);
403 /* If checking the mode of displaced instruction in copy area, the mode
404 should be determined by instruction on the original address. */
408 fprintf_unfiltered (gdb_stdlog
,
409 "displaced: check mode of %.8lx instead of %.8lx\n",
410 (unsigned long) dsc
->insn_addr
,
411 (unsigned long) memaddr
);
412 memaddr
= dsc
->insn_addr
;
415 /* If bit 0 of the address is set, assume this is a Thumb address. */
416 if (IS_THUMB_ADDR (memaddr
))
419 /* If the user wants to override the symbol table, let him. */
420 if (strcmp (arm_force_mode_string
, "arm") == 0)
422 if (strcmp (arm_force_mode_string
, "thumb") == 0)
425 /* ARM v6-M and v7-M are always in Thumb mode. */
426 if (gdbarch_tdep (gdbarch
)->is_m
)
429 /* If there are mapping symbols, consult them. */
430 type
= arm_find_mapping_symbol (memaddr
, NULL
);
434 /* Thumb functions have a "special" bit set in minimal symbols. */
435 sym
= lookup_minimal_symbol_by_pc (memaddr
);
437 return (MSYMBOL_IS_SPECIAL (sym
.minsym
));
439 /* If the user wants to override the fallback mode, let them. */
440 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
442 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
445 /* If we couldn't find any symbol, but we're talking to a running
446 target, then trust the current value of $cpsr. This lets
447 "display/i $pc" always show the correct mode (though if there is
448 a symbol table we will not reach here, so it still may not be
449 displayed in the mode it will be executed). */
450 if (target_has_registers
)
451 return arm_frame_is_thumb (get_current_frame ());
453 /* Otherwise we're out of luck; we assume ARM. */
457 /* Determine if the address specified equals any of these magic return
458 values, called EXC_RETURN, defined by the ARM v6-M and v7-M
461 From ARMv6-M Reference Manual B1.5.8
462 Table B1-5 Exception return behavior
464 EXC_RETURN Return To Return Stack
465 0xFFFFFFF1 Handler mode Main
466 0xFFFFFFF9 Thread mode Main
467 0xFFFFFFFD Thread mode Process
469 From ARMv7-M Reference Manual B1.5.8
470 Table B1-8 EXC_RETURN definition of exception return behavior, no FP
472 EXC_RETURN Return To Return Stack
473 0xFFFFFFF1 Handler mode Main
474 0xFFFFFFF9 Thread mode Main
475 0xFFFFFFFD Thread mode Process
477 Table B1-9 EXC_RETURN definition of exception return behavior, with
480 EXC_RETURN Return To Return Stack Frame Type
481 0xFFFFFFE1 Handler mode Main Extended
482 0xFFFFFFE9 Thread mode Main Extended
483 0xFFFFFFED Thread mode Process Extended
484 0xFFFFFFF1 Handler mode Main Basic
485 0xFFFFFFF9 Thread mode Main Basic
486 0xFFFFFFFD Thread mode Process Basic
488 For more details see "B1.5.8 Exception return behavior"
489 in both ARMv6-M and ARMv7-M Architecture Reference Manuals. */
492 arm_m_addr_is_magic (CORE_ADDR addr
)
496 /* Values from Tables in B1.5.8 the EXC_RETURN definitions of
497 the exception return behavior. */
504 /* Address is magic. */
508 /* Address is not magic. */
513 /* Remove useless bits from addresses in a running program. */
515 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
517 /* On M-profile devices, do not strip the low bit from EXC_RETURN
518 (the magic exception return address). */
519 if (gdbarch_tdep (gdbarch
)->is_m
520 && arm_m_addr_is_magic (val
))
524 return UNMAKE_THUMB_ADDR (val
);
526 return (val
& 0x03fffffc);
529 /* Return 1 if PC is the start of a compiler helper function which
530 can be safely ignored during prologue skipping. IS_THUMB is true
531 if the function is known to be a Thumb function due to the way it
534 skip_prologue_function (struct gdbarch
*gdbarch
, CORE_ADDR pc
, int is_thumb
)
536 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
537 struct bound_minimal_symbol msym
;
539 msym
= lookup_minimal_symbol_by_pc (pc
);
540 if (msym
.minsym
!= NULL
541 && BMSYMBOL_VALUE_ADDRESS (msym
) == pc
542 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
)
544 const char *name
= MSYMBOL_LINKAGE_NAME (msym
.minsym
);
546 /* The GNU linker's Thumb call stub to foo is named
548 if (strstr (name
, "_from_thumb") != NULL
)
551 /* On soft-float targets, __truncdfsf2 is called to convert promoted
552 arguments to their argument types in non-prototyped
554 if (startswith (name
, "__truncdfsf2"))
556 if (startswith (name
, "__aeabi_d2f"))
559 /* Internal functions related to thread-local storage. */
560 if (startswith (name
, "__tls_get_addr"))
562 if (startswith (name
, "__aeabi_read_tp"))
567 /* If we run against a stripped glibc, we may be unable to identify
568 special functions by name. Check for one important case,
569 __aeabi_read_tp, by comparing the *code* against the default
570 implementation (this is hand-written ARM assembler in glibc). */
573 && read_memory_unsigned_integer (pc
, 4, byte_order_for_code
)
574 == 0xe3e00a0f /* mov r0, #0xffff0fff */
575 && read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
)
576 == 0xe240f01f) /* sub pc, r0, #31 */
583 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
584 the first 16-bit of instruction, and INSN2 is the second 16-bit of
586 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
587 ((bits ((insn1), 0, 3) << 12) \
588 | (bits ((insn1), 10, 10) << 11) \
589 | (bits ((insn2), 12, 14) << 8) \
590 | bits ((insn2), 0, 7))
592 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
593 the 32-bit instruction. */
594 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
595 ((bits ((insn), 16, 19) << 12) \
596 | bits ((insn), 0, 11))
598 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
601 thumb_expand_immediate (unsigned int imm
)
603 unsigned int count
= imm
>> 7;
611 return (imm
& 0xff) | ((imm
& 0xff) << 16);
613 return ((imm
& 0xff) << 8) | ((imm
& 0xff) << 24);
615 return (imm
& 0xff) | ((imm
& 0xff) << 8)
616 | ((imm
& 0xff) << 16) | ((imm
& 0xff) << 24);
619 return (0x80 | (imm
& 0x7f)) << (32 - count
);
622 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
623 epilogue, 0 otherwise. */
626 thumb_instruction_restores_sp (unsigned short insn
)
628 return (insn
== 0x46bd /* mov sp, r7 */
629 || (insn
& 0xff80) == 0xb000 /* add sp, imm */
630 || (insn
& 0xfe00) == 0xbc00); /* pop <registers> */
633 /* Analyze a Thumb prologue, looking for a recognizable stack frame
634 and frame pointer. Scan until we encounter a store that could
635 clobber the stack frame unexpectedly, or an unknown instruction.
636 Return the last address which is definitely safe to skip for an
637 initial breakpoint. */
640 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
641 CORE_ADDR start
, CORE_ADDR limit
,
642 struct arm_prologue_cache
*cache
)
644 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
645 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
648 struct pv_area
*stack
;
649 struct cleanup
*back_to
;
651 CORE_ADDR unrecognized_pc
= 0;
653 for (i
= 0; i
< 16; i
++)
654 regs
[i
] = pv_register (i
, 0);
655 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
656 back_to
= make_cleanup_free_pv_area (stack
);
658 while (start
< limit
)
662 insn
= read_memory_unsigned_integer (start
, 2, byte_order_for_code
);
664 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
669 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
672 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
673 whether to save LR (R14). */
674 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
676 /* Calculate offsets of saved R0-R7 and LR. */
677 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
678 if (mask
& (1 << regno
))
680 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
682 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
685 else if ((insn
& 0xff80) == 0xb080) /* sub sp, #imm */
687 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
688 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
691 else if (thumb_instruction_restores_sp (insn
))
693 /* Don't scan past the epilogue. */
696 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
697 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
699 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
700 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
701 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
703 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
704 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
705 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
707 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
708 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
709 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
710 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
711 regs
[bits (insn
, 6, 8)]);
712 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
713 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
715 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
716 int rm
= bits (insn
, 3, 6);
717 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
719 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
721 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
722 int src_reg
= (insn
& 0x78) >> 3;
723 regs
[dst_reg
] = regs
[src_reg
];
725 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
727 /* Handle stores to the stack. Normally pushes are used,
728 but with GCC -mtpcs-frame, there may be other stores
729 in the prologue to create the frame. */
730 int regno
= (insn
>> 8) & 0x7;
733 offset
= (insn
& 0xff) << 2;
734 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
736 if (pv_area_store_would_trash (stack
, addr
))
739 pv_area_store (stack
, addr
, 4, regs
[regno
]);
741 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
743 int rd
= bits (insn
, 0, 2);
744 int rn
= bits (insn
, 3, 5);
747 offset
= bits (insn
, 6, 10) << 2;
748 addr
= pv_add_constant (regs
[rn
], offset
);
750 if (pv_area_store_would_trash (stack
, addr
))
753 pv_area_store (stack
, addr
, 4, regs
[rd
]);
755 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
756 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
757 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
758 /* Ignore stores of argument registers to the stack. */
760 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
761 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
762 /* Ignore block loads from the stack, potentially copying
763 parameters from memory. */
765 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
766 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
767 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
768 /* Similarly ignore single loads from the stack. */
770 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
771 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
772 /* Skip register copies, i.e. saves to another register
773 instead of the stack. */
775 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
776 /* Recognize constant loads; even with small stacks these are necessary
778 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
779 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
781 /* Constant pool loads, for the same reason. */
782 unsigned int constant
;
785 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
786 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
787 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
789 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instructions. */
791 unsigned short inst2
;
793 inst2
= read_memory_unsigned_integer (start
+ 2, 2,
794 byte_order_for_code
);
796 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
798 /* BL, BLX. Allow some special function calls when
799 skipping the prologue; GCC generates these before
800 storing arguments to the stack. */
802 int j1
, j2
, imm1
, imm2
;
804 imm1
= sbits (insn
, 0, 10);
805 imm2
= bits (inst2
, 0, 10);
806 j1
= bit (inst2
, 13);
807 j2
= bit (inst2
, 11);
809 offset
= ((imm1
<< 12) + (imm2
<< 1));
810 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
812 nextpc
= start
+ 4 + offset
;
813 /* For BLX make sure to clear the low bits. */
814 if (bit (inst2
, 12) == 0)
815 nextpc
= nextpc
& 0xfffffffc;
817 if (!skip_prologue_function (gdbarch
, nextpc
,
818 bit (inst2
, 12) != 0))
822 else if ((insn
& 0xffd0) == 0xe900 /* stmdb Rn{!},
824 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
826 pv_t addr
= regs
[bits (insn
, 0, 3)];
829 if (pv_area_store_would_trash (stack
, addr
))
832 /* Calculate offsets of saved registers. */
833 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
834 if (inst2
& (1 << regno
))
836 addr
= pv_add_constant (addr
, -4);
837 pv_area_store (stack
, addr
, 4, regs
[regno
]);
841 regs
[bits (insn
, 0, 3)] = addr
;
844 else if ((insn
& 0xff50) == 0xe940 /* strd Rt, Rt2,
846 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
848 int regno1
= bits (inst2
, 12, 15);
849 int regno2
= bits (inst2
, 8, 11);
850 pv_t addr
= regs
[bits (insn
, 0, 3)];
852 offset
= inst2
& 0xff;
854 addr
= pv_add_constant (addr
, offset
);
856 addr
= pv_add_constant (addr
, -offset
);
858 if (pv_area_store_would_trash (stack
, addr
))
861 pv_area_store (stack
, addr
, 4, regs
[regno1
]);
862 pv_area_store (stack
, pv_add_constant (addr
, 4),
866 regs
[bits (insn
, 0, 3)] = addr
;
869 else if ((insn
& 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
870 && (inst2
& 0x0c00) == 0x0c00
871 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
873 int regno
= bits (inst2
, 12, 15);
874 pv_t addr
= regs
[bits (insn
, 0, 3)];
876 offset
= inst2
& 0xff;
878 addr
= pv_add_constant (addr
, offset
);
880 addr
= pv_add_constant (addr
, -offset
);
882 if (pv_area_store_would_trash (stack
, addr
))
885 pv_area_store (stack
, addr
, 4, regs
[regno
]);
888 regs
[bits (insn
, 0, 3)] = addr
;
891 else if ((insn
& 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
892 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
894 int regno
= bits (inst2
, 12, 15);
897 offset
= inst2
& 0xfff;
898 addr
= pv_add_constant (regs
[bits (insn
, 0, 3)], offset
);
900 if (pv_area_store_would_trash (stack
, addr
))
903 pv_area_store (stack
, addr
, 4, regs
[regno
]);
906 else if ((insn
& 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
907 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
908 /* Ignore stores of argument registers to the stack. */
911 else if ((insn
& 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
912 && (inst2
& 0x0d00) == 0x0c00
913 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
914 /* Ignore stores of argument registers to the stack. */
917 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!],
919 && (inst2
& 0x8000) == 0x0000
920 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
921 /* Ignore block loads from the stack, potentially copying
922 parameters from memory. */
925 else if ((insn
& 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
927 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
928 /* Similarly ignore dual loads from the stack. */
931 else if ((insn
& 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
932 && (inst2
& 0x0d00) == 0x0c00
933 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
934 /* Similarly ignore single loads from the stack. */
937 else if ((insn
& 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
938 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
939 /* Similarly ignore single loads from the stack. */
942 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
943 && (inst2
& 0x8000) == 0x0000)
945 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
946 | (bits (inst2
, 12, 14) << 8)
947 | bits (inst2
, 0, 7));
949 regs
[bits (inst2
, 8, 11)]
950 = pv_add_constant (regs
[bits (insn
, 0, 3)],
951 thumb_expand_immediate (imm
));
954 else if ((insn
& 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
955 && (inst2
& 0x8000) == 0x0000)
957 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
958 | (bits (inst2
, 12, 14) << 8)
959 | bits (inst2
, 0, 7));
961 regs
[bits (inst2
, 8, 11)]
962 = pv_add_constant (regs
[bits (insn
, 0, 3)], imm
);
965 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
966 && (inst2
& 0x8000) == 0x0000)
968 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
969 | (bits (inst2
, 12, 14) << 8)
970 | bits (inst2
, 0, 7));
972 regs
[bits (inst2
, 8, 11)]
973 = pv_add_constant (regs
[bits (insn
, 0, 3)],
974 - (CORE_ADDR
) thumb_expand_immediate (imm
));
977 else if ((insn
& 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
978 && (inst2
& 0x8000) == 0x0000)
980 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
981 | (bits (inst2
, 12, 14) << 8)
982 | bits (inst2
, 0, 7));
984 regs
[bits (inst2
, 8, 11)]
985 = pv_add_constant (regs
[bits (insn
, 0, 3)], - (CORE_ADDR
) imm
);
988 else if ((insn
& 0xfbff) == 0xf04f) /* mov.w Rd, #const */
990 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
991 | (bits (inst2
, 12, 14) << 8)
992 | bits (inst2
, 0, 7));
994 regs
[bits (inst2
, 8, 11)]
995 = pv_constant (thumb_expand_immediate (imm
));
998 else if ((insn
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1001 = EXTRACT_MOVW_MOVT_IMM_T (insn
, inst2
);
1003 regs
[bits (inst2
, 8, 11)] = pv_constant (imm
);
1006 else if (insn
== 0xea5f /* mov.w Rd,Rm */
1007 && (inst2
& 0xf0f0) == 0)
1009 int dst_reg
= (inst2
& 0x0f00) >> 8;
1010 int src_reg
= inst2
& 0xf;
1011 regs
[dst_reg
] = regs
[src_reg
];
1014 else if ((insn
& 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1016 /* Constant pool loads. */
1017 unsigned int constant
;
1020 offset
= bits (inst2
, 0, 11);
1022 loc
= start
+ 4 + offset
;
1024 loc
= start
+ 4 - offset
;
1026 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1027 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1030 else if ((insn
& 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1032 /* Constant pool loads. */
1033 unsigned int constant
;
1036 offset
= bits (inst2
, 0, 7) << 2;
1038 loc
= start
+ 4 + offset
;
1040 loc
= start
+ 4 - offset
;
1042 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1043 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1045 constant
= read_memory_unsigned_integer (loc
+ 4, 4, byte_order
);
1046 regs
[bits (inst2
, 8, 11)] = pv_constant (constant
);
1049 else if (thumb2_instruction_changes_pc (insn
, inst2
))
1051 /* Don't scan past anything that might change control flow. */
1056 /* The optimizer might shove anything into the prologue,
1057 so we just skip what we don't recognize. */
1058 unrecognized_pc
= start
;
1063 else if (thumb_instruction_changes_pc (insn
))
1065 /* Don't scan past anything that might change control flow. */
1070 /* The optimizer might shove anything into the prologue,
1071 so we just skip what we don't recognize. */
1072 unrecognized_pc
= start
;
1079 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1080 paddress (gdbarch
, start
));
1082 if (unrecognized_pc
== 0)
1083 unrecognized_pc
= start
;
1087 do_cleanups (back_to
);
1088 return unrecognized_pc
;
1091 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1093 /* Frame pointer is fp. Frame size is constant. */
1094 cache
->framereg
= ARM_FP_REGNUM
;
1095 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1097 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
1099 /* Frame pointer is r7. Frame size is constant. */
1100 cache
->framereg
= THUMB_FP_REGNUM
;
1101 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
1105 /* Try the stack pointer... this is a bit desperate. */
1106 cache
->framereg
= ARM_SP_REGNUM
;
1107 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1110 for (i
= 0; i
< 16; i
++)
1111 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
1112 cache
->saved_regs
[i
].addr
= offset
;
1114 do_cleanups (back_to
);
1115 return unrecognized_pc
;
1119 /* Try to analyze the instructions starting from PC, which load symbol
1120 __stack_chk_guard. Return the address of instruction after loading this
1121 symbol, set the dest register number to *BASEREG, and set the size of
1122 instructions for loading symbol in OFFSET. Return 0 if instructions are
1126 arm_analyze_load_stack_chk_guard(CORE_ADDR pc
, struct gdbarch
*gdbarch
,
1127 unsigned int *destreg
, int *offset
)
1129 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1130 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1131 unsigned int low
, high
, address
;
1136 unsigned short insn1
1137 = read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
1139 if ((insn1
& 0xf800) == 0x4800) /* ldr Rd, #immed */
1141 *destreg
= bits (insn1
, 8, 10);
1143 address
= (pc
& 0xfffffffc) + 4 + (bits (insn1
, 0, 7) << 2);
1144 address
= read_memory_unsigned_integer (address
, 4,
1145 byte_order_for_code
);
1147 else if ((insn1
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1149 unsigned short insn2
1150 = read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1152 low
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1155 = read_memory_unsigned_integer (pc
+ 4, 2, byte_order_for_code
);
1157 = read_memory_unsigned_integer (pc
+ 6, 2, byte_order_for_code
);
1159 /* movt Rd, #const */
1160 if ((insn1
& 0xfbc0) == 0xf2c0)
1162 high
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1163 *destreg
= bits (insn2
, 8, 11);
1165 address
= (high
<< 16 | low
);
1172 = read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
1174 if ((insn
& 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1176 address
= bits (insn
, 0, 11) + pc
+ 8;
1177 address
= read_memory_unsigned_integer (address
, 4,
1178 byte_order_for_code
);
1180 *destreg
= bits (insn
, 12, 15);
1183 else if ((insn
& 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1185 low
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1188 = read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
);
1190 if ((insn
& 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1192 high
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1193 *destreg
= bits (insn
, 12, 15);
1195 address
= (high
<< 16 | low
);
1203 /* Try to skip a sequence of instructions used for stack protector. If PC
1204 points to the first instruction of this sequence, return the address of
1205 first instruction after this sequence, otherwise, return original PC.
1207 On arm, this sequence of instructions is composed of mainly three steps,
1208 Step 1: load symbol __stack_chk_guard,
1209 Step 2: load from address of __stack_chk_guard,
1210 Step 3: store it to somewhere else.
1212 Usually, instructions on step 2 and step 3 are the same on various ARM
1213 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1214 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1215 instructions in step 1 vary from different ARM architectures. On ARMv7,
1218 movw Rn, #:lower16:__stack_chk_guard
1219 movt Rn, #:upper16:__stack_chk_guard
1226 .word __stack_chk_guard
1228 Since ldr/str is a very popular instruction, we can't use them as
1229 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1230 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1231 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1234 arm_skip_stack_protector(CORE_ADDR pc
, struct gdbarch
*gdbarch
)
1236 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1237 unsigned int basereg
;
1238 struct bound_minimal_symbol stack_chk_guard
;
1240 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1243 /* Try to parse the instructions in Step 1. */
1244 addr
= arm_analyze_load_stack_chk_guard (pc
, gdbarch
,
1249 stack_chk_guard
= lookup_minimal_symbol_by_pc (addr
);
1250 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1251 Otherwise, this sequence cannot be for stack protector. */
1252 if (stack_chk_guard
.minsym
== NULL
1253 || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard
.minsym
), "__stack_chk_guard"))
1258 unsigned int destreg
;
1260 = read_memory_unsigned_integer (pc
+ offset
, 2, byte_order_for_code
);
1262 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1263 if ((insn
& 0xf800) != 0x6800)
1265 if (bits (insn
, 3, 5) != basereg
)
1267 destreg
= bits (insn
, 0, 2);
1269 insn
= read_memory_unsigned_integer (pc
+ offset
+ 2, 2,
1270 byte_order_for_code
);
1271 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1272 if ((insn
& 0xf800) != 0x6000)
1274 if (destreg
!= bits (insn
, 0, 2))
1279 unsigned int destreg
;
1281 = read_memory_unsigned_integer (pc
+ offset
, 4, byte_order_for_code
);
1283 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1284 if ((insn
& 0x0e500000) != 0x04100000)
1286 if (bits (insn
, 16, 19) != basereg
)
1288 destreg
= bits (insn
, 12, 15);
1289 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1290 insn
= read_memory_unsigned_integer (pc
+ offset
+ 4,
1291 4, byte_order_for_code
);
1292 if ((insn
& 0x0e500000) != 0x04000000)
1294 if (bits (insn
, 12, 15) != destreg
)
1297 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1300 return pc
+ offset
+ 4;
1302 return pc
+ offset
+ 8;
1305 /* Advance the PC across any function entry prologue instructions to
1306 reach some "real" code.
1308 The APCS (ARM Procedure Call Standard) defines the following
1312 [stmfd sp!, {a1,a2,a3,a4}]
1313 stmfd sp!, {...,fp,ip,lr,pc}
1314 [stfe f7, [sp, #-12]!]
1315 [stfe f6, [sp, #-12]!]
1316 [stfe f5, [sp, #-12]!]
1317 [stfe f4, [sp, #-12]!]
1318 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1321 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1323 CORE_ADDR func_addr
, limit_pc
;
1325 /* See if we can determine the end of the prologue via the symbol table.
1326 If so, then return either PC, or the PC after the prologue, whichever
1328 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1330 CORE_ADDR post_prologue_pc
1331 = skip_prologue_using_sal (gdbarch
, func_addr
);
1332 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1334 if (post_prologue_pc
)
1336 = arm_skip_stack_protector (post_prologue_pc
, gdbarch
);
1339 /* GCC always emits a line note before the prologue and another
1340 one after, even if the two are at the same address or on the
1341 same line. Take advantage of this so that we do not need to
1342 know every instruction that might appear in the prologue. We
1343 will have producer information for most binaries; if it is
1344 missing (e.g. for -gstabs), assuming the GNU tools. */
1345 if (post_prologue_pc
1347 || COMPUNIT_PRODUCER (cust
) == NULL
1348 || startswith (COMPUNIT_PRODUCER (cust
), "GNU ")
1349 || startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
1350 return post_prologue_pc
;
1352 if (post_prologue_pc
!= 0)
1354 CORE_ADDR analyzed_limit
;
1356 /* For non-GCC compilers, make sure the entire line is an
1357 acceptable prologue; GDB will round this function's
1358 return value up to the end of the following line so we
1359 can not skip just part of a line (and we do not want to).
1361 RealView does not treat the prologue specially, but does
1362 associate prologue code with the opening brace; so this
1363 lets us skip the first line if we think it is the opening
1365 if (arm_pc_is_thumb (gdbarch
, func_addr
))
1366 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
1367 post_prologue_pc
, NULL
);
1369 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
1370 post_prologue_pc
, NULL
);
1372 if (analyzed_limit
!= post_prologue_pc
)
1375 return post_prologue_pc
;
1379 /* Can't determine prologue from the symbol table, need to examine
1382 /* Find an upper limit on the function prologue using the debug
1383 information. If the debug information could not be used to provide
1384 that bound, then use an arbitrary large number as the upper bound. */
1385 /* Like arm_scan_prologue, stop no later than pc + 64. */
1386 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1388 limit_pc
= pc
+ 64; /* Magic. */
1391 /* Check if this is Thumb code. */
1392 if (arm_pc_is_thumb (gdbarch
, pc
))
1393 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1395 return arm_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1399 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1400 This function decodes a Thumb function prologue to determine:
1401 1) the size of the stack frame
1402 2) which registers are saved on it
1403 3) the offsets of saved regs
1404 4) the offset from the stack pointer to the frame pointer
1406 A typical Thumb function prologue would create this stack frame
1407 (offsets relative to FP)
1408 old SP -> 24 stack parameters
1411 R7 -> 0 local variables (16 bytes)
1412 SP -> -12 additional stack space (12 bytes)
1413 The frame size would thus be 36 bytes, and the frame offset would be
1414 12 bytes. The frame register is R7.
1416 The comments for thumb_skip_prolog() describe the algorithm we use
1417 to detect the end of the prolog. */
1421 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
1422 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
1424 CORE_ADDR prologue_start
;
1425 CORE_ADDR prologue_end
;
1427 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1430 /* See comment in arm_scan_prologue for an explanation of
1432 if (prologue_end
> prologue_start
+ 64)
1434 prologue_end
= prologue_start
+ 64;
1438 /* We're in the boondocks: we have no idea where the start of the
1442 prologue_end
= std::min (prologue_end
, prev_pc
);
1444 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1447 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1451 arm_instruction_restores_sp (unsigned int insn
)
1453 if (bits (insn
, 28, 31) != INST_NV
)
1455 if ((insn
& 0x0df0f000) == 0x0080d000
1456 /* ADD SP (register or immediate). */
1457 || (insn
& 0x0df0f000) == 0x0040d000
1458 /* SUB SP (register or immediate). */
1459 || (insn
& 0x0ffffff0) == 0x01a0d000
1461 || (insn
& 0x0fff0000) == 0x08bd0000
1463 || (insn
& 0x0fff0000) == 0x049d0000)
1464 /* POP of a single register. */
1471 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1472 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1473 fill it in. Return the first address not recognized as a prologue
1476 We recognize all the instructions typically found in ARM prologues,
1477 plus harmless instructions which can be skipped (either for analysis
1478 purposes, or a more restrictive set that can be skipped when finding
1479 the end of the prologue). */
1482 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1483 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1484 struct arm_prologue_cache
*cache
)
1486 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1488 CORE_ADDR offset
, current_pc
;
1489 pv_t regs
[ARM_FPS_REGNUM
];
1490 struct pv_area
*stack
;
1491 struct cleanup
*back_to
;
1492 CORE_ADDR unrecognized_pc
= 0;
1494 /* Search the prologue looking for instructions that set up the
1495 frame pointer, adjust the stack pointer, and save registers.
1497 Be careful, however, and if it doesn't look like a prologue,
1498 don't try to scan it. If, for instance, a frameless function
1499 begins with stmfd sp!, then we will tell ourselves there is
1500 a frame, which will confuse stack traceback, as well as "finish"
1501 and other operations that rely on a knowledge of the stack
1504 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1505 regs
[regno
] = pv_register (regno
, 0);
1506 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1507 back_to
= make_cleanup_free_pv_area (stack
);
1509 for (current_pc
= prologue_start
;
1510 current_pc
< prologue_end
;
1514 = read_memory_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1516 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1518 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1521 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1522 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1524 unsigned imm
= insn
& 0xff; /* immediate value */
1525 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1526 int rd
= bits (insn
, 12, 15);
1527 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1528 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1531 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1532 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1534 unsigned imm
= insn
& 0xff; /* immediate value */
1535 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1536 int rd
= bits (insn
, 12, 15);
1537 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1538 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1541 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd,
1544 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1546 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1547 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4,
1548 regs
[bits (insn
, 12, 15)]);
1551 else if ((insn
& 0xffff0000) == 0xe92d0000)
1552 /* stmfd sp!, {..., fp, ip, lr, pc}
1554 stmfd sp!, {a1, a2, a3, a4} */
1556 int mask
= insn
& 0xffff;
1558 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1561 /* Calculate offsets of saved registers. */
1562 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1563 if (mask
& (1 << regno
))
1566 = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1567 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1570 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1571 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1572 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1574 /* No need to add this to saved_regs -- it's just an arg reg. */
1577 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1578 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1579 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1581 /* No need to add this to saved_regs -- it's just an arg reg. */
1584 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn,
1586 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1588 /* No need to add this to saved_regs -- it's just arg regs. */
1591 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1593 unsigned imm
= insn
& 0xff; /* immediate value */
1594 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1595 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1596 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1598 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1600 unsigned imm
= insn
& 0xff; /* immediate value */
1601 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1602 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1603 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1605 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?,
1607 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1609 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1612 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1613 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1614 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1616 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1618 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1620 int n_saved_fp_regs
;
1621 unsigned int fp_start_reg
, fp_bound_reg
;
1623 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1626 if ((insn
& 0x800) == 0x800) /* N0 is set */
1628 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1629 n_saved_fp_regs
= 3;
1631 n_saved_fp_regs
= 1;
1635 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1636 n_saved_fp_regs
= 2;
1638 n_saved_fp_regs
= 4;
1641 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1642 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1643 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1645 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1646 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
1647 regs
[fp_start_reg
++]);
1650 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1652 /* Allow some special function calls when skipping the
1653 prologue; GCC generates these before storing arguments to
1655 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1657 if (skip_prologue_function (gdbarch
, dest
, 0))
1662 else if ((insn
& 0xf0000000) != 0xe0000000)
1663 break; /* Condition not true, exit early. */
1664 else if (arm_instruction_changes_pc (insn
))
1665 /* Don't scan past anything that might change control flow. */
1667 else if (arm_instruction_restores_sp (insn
))
1669 /* Don't scan past the epilogue. */
1672 else if ((insn
& 0xfe500000) == 0xe8100000 /* ldm */
1673 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1674 /* Ignore block loads from the stack, potentially copying
1675 parameters from memory. */
1677 else if ((insn
& 0xfc500000) == 0xe4100000
1678 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1679 /* Similarly ignore single loads from the stack. */
1681 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1682 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1683 register instead of the stack. */
1687 /* The optimizer might shove anything into the prologue, if
1688 we build up cache (cache != NULL) from scanning prologue,
1689 we just skip what we don't recognize and scan further to
1690 make cache as complete as possible. However, if we skip
1691 prologue, we'll stop immediately on unrecognized
1693 unrecognized_pc
= current_pc
;
1701 if (unrecognized_pc
== 0)
1702 unrecognized_pc
= current_pc
;
1706 int framereg
, framesize
;
1708 /* The frame size is just the distance from the frame register
1709 to the original stack pointer. */
1710 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1712 /* Frame pointer is fp. */
1713 framereg
= ARM_FP_REGNUM
;
1714 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1718 /* Try the stack pointer... this is a bit desperate. */
1719 framereg
= ARM_SP_REGNUM
;
1720 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1723 cache
->framereg
= framereg
;
1724 cache
->framesize
= framesize
;
1726 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1727 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1728 cache
->saved_regs
[regno
].addr
= offset
;
1732 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1733 paddress (gdbarch
, unrecognized_pc
));
1735 do_cleanups (back_to
);
1736 return unrecognized_pc
;
1740 arm_scan_prologue (struct frame_info
*this_frame
,
1741 struct arm_prologue_cache
*cache
)
1743 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1744 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1745 CORE_ADDR prologue_start
, prologue_end
;
1746 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1747 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1749 /* Assume there is no frame until proven otherwise. */
1750 cache
->framereg
= ARM_SP_REGNUM
;
1751 cache
->framesize
= 0;
1753 /* Check for Thumb prologue. */
1754 if (arm_frame_is_thumb (this_frame
))
1756 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1760 /* Find the function prologue. If we can't find the function in
1761 the symbol table, peek in the stack frame to find the PC. */
1762 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1765 /* One way to find the end of the prologue (which works well
1766 for unoptimized code) is to do the following:
1768 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1771 prologue_end = prev_pc;
1772 else if (sal.end < prologue_end)
1773 prologue_end = sal.end;
1775 This mechanism is very accurate so long as the optimizer
1776 doesn't move any instructions from the function body into the
1777 prologue. If this happens, sal.end will be the last
1778 instruction in the first hunk of prologue code just before
1779 the first instruction that the scheduler has moved from
1780 the body to the prologue.
1782 In order to make sure that we scan all of the prologue
1783 instructions, we use a slightly less accurate mechanism which
1784 may scan more than necessary. To help compensate for this
1785 lack of accuracy, the prologue scanning loop below contains
1786 several clauses which'll cause the loop to terminate early if
1787 an implausible prologue instruction is encountered.
1793 is a suitable endpoint since it accounts for the largest
1794 possible prologue plus up to five instructions inserted by
1797 if (prologue_end
> prologue_start
+ 64)
1799 prologue_end
= prologue_start
+ 64; /* See above. */
1804 /* We have no symbol information. Our only option is to assume this
1805 function has a standard stack frame and the normal frame register.
1806 Then, we can find the value of our frame pointer on entrance to
1807 the callee (or at the present moment if this is the innermost frame).
1808 The value stored there should be the address of the stmfd + 8. */
1809 CORE_ADDR frame_loc
;
1810 LONGEST return_value
;
1812 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
1813 if (!safe_read_memory_integer (frame_loc
, 4, byte_order
, &return_value
))
1817 prologue_start
= gdbarch_addr_bits_remove
1818 (gdbarch
, return_value
) - 8;
1819 prologue_end
= prologue_start
+ 64; /* See above. */
1823 if (prev_pc
< prologue_end
)
1824 prologue_end
= prev_pc
;
1826 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1829 static struct arm_prologue_cache
*
1830 arm_make_prologue_cache (struct frame_info
*this_frame
)
1833 struct arm_prologue_cache
*cache
;
1834 CORE_ADDR unwound_fp
;
1836 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1837 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1839 arm_scan_prologue (this_frame
, cache
);
1841 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
1842 if (unwound_fp
== 0)
1845 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
1847 /* Calculate actual addresses of saved registers using offsets
1848 determined by arm_scan_prologue. */
1849 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
1850 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
1851 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
1856 /* Implementation of the stop_reason hook for arm_prologue frames. */
1858 static enum unwind_stop_reason
1859 arm_prologue_unwind_stop_reason (struct frame_info
*this_frame
,
1862 struct arm_prologue_cache
*cache
;
1865 if (*this_cache
== NULL
)
1866 *this_cache
= arm_make_prologue_cache (this_frame
);
1867 cache
= (struct arm_prologue_cache
*) *this_cache
;
1869 /* This is meant to halt the backtrace at "_start". */
1870 pc
= get_frame_pc (this_frame
);
1871 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1872 return UNWIND_OUTERMOST
;
1874 /* If we've hit a wall, stop. */
1875 if (cache
->prev_sp
== 0)
1876 return UNWIND_OUTERMOST
;
1878 return UNWIND_NO_REASON
;
1881 /* Our frame ID for a normal frame is the current function's starting PC
1882 and the caller's SP when we were called. */
1885 arm_prologue_this_id (struct frame_info
*this_frame
,
1887 struct frame_id
*this_id
)
1889 struct arm_prologue_cache
*cache
;
1893 if (*this_cache
== NULL
)
1894 *this_cache
= arm_make_prologue_cache (this_frame
);
1895 cache
= (struct arm_prologue_cache
*) *this_cache
;
1897 /* Use function start address as part of the frame ID. If we cannot
1898 identify the start address (due to missing symbol information),
1899 fall back to just using the current PC. */
1900 pc
= get_frame_pc (this_frame
);
1901 func
= get_frame_func (this_frame
);
1905 id
= frame_id_build (cache
->prev_sp
, func
);
1909 static struct value
*
1910 arm_prologue_prev_register (struct frame_info
*this_frame
,
1914 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1915 struct arm_prologue_cache
*cache
;
1917 if (*this_cache
== NULL
)
1918 *this_cache
= arm_make_prologue_cache (this_frame
);
1919 cache
= (struct arm_prologue_cache
*) *this_cache
;
1921 /* If we are asked to unwind the PC, then we need to return the LR
1922 instead. The prologue may save PC, but it will point into this
1923 frame's prologue, not the next frame's resume location. Also
1924 strip the saved T bit. A valid LR may have the low bit set, but
1925 a valid PC never does. */
1926 if (prev_regnum
== ARM_PC_REGNUM
)
1930 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1931 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1932 arm_addr_bits_remove (gdbarch
, lr
));
1935 /* SP is generally not saved to the stack, but this frame is
1936 identified by the next frame's stack pointer at the time of the call.
1937 The value was already reconstructed into PREV_SP. */
1938 if (prev_regnum
== ARM_SP_REGNUM
)
1939 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1941 /* The CPSR may have been changed by the call instruction and by the
1942 called function. The only bit we can reconstruct is the T bit,
1943 by checking the low bit of LR as of the call. This is a reliable
1944 indicator of Thumb-ness except for some ARM v4T pre-interworking
1945 Thumb code, which could get away with a clear low bit as long as
1946 the called function did not use bx. Guess that all other
1947 bits are unchanged; the condition flags are presumably lost,
1948 but the processor status is likely valid. */
1949 if (prev_regnum
== ARM_PS_REGNUM
)
1952 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
1954 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1955 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1956 if (IS_THUMB_ADDR (lr
))
1960 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1963 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1967 struct frame_unwind arm_prologue_unwind
= {
1969 arm_prologue_unwind_stop_reason
,
1970 arm_prologue_this_id
,
1971 arm_prologue_prev_register
,
1973 default_frame_sniffer
1976 /* Maintain a list of ARM exception table entries per objfile, similar to the
1977 list of mapping symbols. We only cache entries for standard ARM-defined
1978 personality routines; the cache will contain only the frame unwinding
1979 instructions associated with the entry (not the descriptors). */
1981 static const struct objfile_data
*arm_exidx_data_key
;
1983 struct arm_exidx_entry
1988 typedef struct arm_exidx_entry arm_exidx_entry_s
;
1989 DEF_VEC_O(arm_exidx_entry_s
);
1991 struct arm_exidx_data
1993 VEC(arm_exidx_entry_s
) **section_maps
;
1997 arm_exidx_data_free (struct objfile
*objfile
, void *arg
)
1999 struct arm_exidx_data
*data
= (struct arm_exidx_data
*) arg
;
2002 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
2003 VEC_free (arm_exidx_entry_s
, data
->section_maps
[i
]);
2007 arm_compare_exidx_entries (const struct arm_exidx_entry
*lhs
,
2008 const struct arm_exidx_entry
*rhs
)
2010 return lhs
->addr
< rhs
->addr
;
2013 static struct obj_section
*
2014 arm_obj_section_from_vma (struct objfile
*objfile
, bfd_vma vma
)
2016 struct obj_section
*osect
;
2018 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
2019 if (bfd_get_section_flags (objfile
->obfd
,
2020 osect
->the_bfd_section
) & SEC_ALLOC
)
2022 bfd_vma start
, size
;
2023 start
= bfd_get_section_vma (objfile
->obfd
, osect
->the_bfd_section
);
2024 size
= bfd_get_section_size (osect
->the_bfd_section
);
2026 if (start
<= vma
&& vma
< start
+ size
)
2033 /* Parse contents of exception table and exception index sections
2034 of OBJFILE, and fill in the exception table entry cache.
2036 For each entry that refers to a standard ARM-defined personality
2037 routine, extract the frame unwinding instructions (from either
2038 the index or the table section). The unwinding instructions
2040 - extracting them from the rest of the table data
2041 - converting to host endianness
2042 - appending the implicit 0xb0 ("Finish") code
2044 The extracted and normalized instructions are stored for later
2045 retrieval by the arm_find_exidx_entry routine. */
2048 arm_exidx_new_objfile (struct objfile
*objfile
)
2050 struct cleanup
*cleanups
;
2051 struct arm_exidx_data
*data
;
2052 asection
*exidx
, *extab
;
2053 bfd_vma exidx_vma
= 0, extab_vma
= 0;
2054 bfd_size_type exidx_size
= 0, extab_size
= 0;
2055 gdb_byte
*exidx_data
= NULL
, *extab_data
= NULL
;
2058 /* If we've already touched this file, do nothing. */
2059 if (!objfile
|| objfile_data (objfile
, arm_exidx_data_key
) != NULL
)
2061 cleanups
= make_cleanup (null_cleanup
, NULL
);
2063 /* Read contents of exception table and index. */
2064 exidx
= bfd_get_section_by_name (objfile
->obfd
, ELF_STRING_ARM_unwind
);
2067 exidx_vma
= bfd_section_vma (objfile
->obfd
, exidx
);
2068 exidx_size
= bfd_get_section_size (exidx
);
2069 exidx_data
= (gdb_byte
*) xmalloc (exidx_size
);
2070 make_cleanup (xfree
, exidx_data
);
2072 if (!bfd_get_section_contents (objfile
->obfd
, exidx
,
2073 exidx_data
, 0, exidx_size
))
2075 do_cleanups (cleanups
);
2080 extab
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.extab");
2083 extab_vma
= bfd_section_vma (objfile
->obfd
, extab
);
2084 extab_size
= bfd_get_section_size (extab
);
2085 extab_data
= (gdb_byte
*) xmalloc (extab_size
);
2086 make_cleanup (xfree
, extab_data
);
2088 if (!bfd_get_section_contents (objfile
->obfd
, extab
,
2089 extab_data
, 0, extab_size
))
2091 do_cleanups (cleanups
);
2096 /* Allocate exception table data structure. */
2097 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
, struct arm_exidx_data
);
2098 set_objfile_data (objfile
, arm_exidx_data_key
, data
);
2099 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2100 objfile
->obfd
->section_count
,
2101 VEC(arm_exidx_entry_s
) *);
2103 /* Fill in exception table. */
2104 for (i
= 0; i
< exidx_size
/ 8; i
++)
2106 struct arm_exidx_entry new_exidx_entry
;
2107 bfd_vma idx
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8);
2108 bfd_vma val
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8 + 4);
2109 bfd_vma addr
= 0, word
= 0;
2110 int n_bytes
= 0, n_words
= 0;
2111 struct obj_section
*sec
;
2112 gdb_byte
*entry
= NULL
;
2114 /* Extract address of start of function. */
2115 idx
= ((idx
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2116 idx
+= exidx_vma
+ i
* 8;
2118 /* Find section containing function and compute section offset. */
2119 sec
= arm_obj_section_from_vma (objfile
, idx
);
2122 idx
-= bfd_get_section_vma (objfile
->obfd
, sec
->the_bfd_section
);
2124 /* Determine address of exception table entry. */
2127 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2129 else if ((val
& 0xff000000) == 0x80000000)
2131 /* Exception table entry embedded in .ARM.exidx
2132 -- must be short form. */
2136 else if (!(val
& 0x80000000))
2138 /* Exception table entry in .ARM.extab. */
2139 addr
= ((val
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2140 addr
+= exidx_vma
+ i
* 8 + 4;
2142 if (addr
>= extab_vma
&& addr
+ 4 <= extab_vma
+ extab_size
)
2144 word
= bfd_h_get_32 (objfile
->obfd
,
2145 extab_data
+ addr
- extab_vma
);
2148 if ((word
& 0xff000000) == 0x80000000)
2153 else if ((word
& 0xff000000) == 0x81000000
2154 || (word
& 0xff000000) == 0x82000000)
2158 n_words
= ((word
>> 16) & 0xff);
2160 else if (!(word
& 0x80000000))
2163 struct obj_section
*pers_sec
;
2164 int gnu_personality
= 0;
2166 /* Custom personality routine. */
2167 pers
= ((word
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2168 pers
= UNMAKE_THUMB_ADDR (pers
+ addr
- 4);
2170 /* Check whether we've got one of the variants of the
2171 GNU personality routines. */
2172 pers_sec
= arm_obj_section_from_vma (objfile
, pers
);
2175 static const char *personality
[] =
2177 "__gcc_personality_v0",
2178 "__gxx_personality_v0",
2179 "__gcj_personality_v0",
2180 "__gnu_objc_personality_v0",
2184 CORE_ADDR pc
= pers
+ obj_section_offset (pers_sec
);
2187 for (k
= 0; personality
[k
]; k
++)
2188 if (lookup_minimal_symbol_by_pc_name
2189 (pc
, personality
[k
], objfile
))
2191 gnu_personality
= 1;
2196 /* If so, the next word contains a word count in the high
2197 byte, followed by the same unwind instructions as the
2198 pre-defined forms. */
2200 && addr
+ 4 <= extab_vma
+ extab_size
)
2202 word
= bfd_h_get_32 (objfile
->obfd
,
2203 extab_data
+ addr
- extab_vma
);
2206 n_words
= ((word
>> 24) & 0xff);
2212 /* Sanity check address. */
2214 if (addr
< extab_vma
|| addr
+ 4 * n_words
> extab_vma
+ extab_size
)
2215 n_words
= n_bytes
= 0;
2217 /* The unwind instructions reside in WORD (only the N_BYTES least
2218 significant bytes are valid), followed by N_WORDS words in the
2219 extab section starting at ADDR. */
2220 if (n_bytes
|| n_words
)
2223 = (gdb_byte
*) obstack_alloc (&objfile
->objfile_obstack
,
2224 n_bytes
+ n_words
* 4 + 1);
2227 *p
++ = (gdb_byte
) ((word
>> (8 * n_bytes
)) & 0xff);
2231 word
= bfd_h_get_32 (objfile
->obfd
,
2232 extab_data
+ addr
- extab_vma
);
2235 *p
++ = (gdb_byte
) ((word
>> 24) & 0xff);
2236 *p
++ = (gdb_byte
) ((word
>> 16) & 0xff);
2237 *p
++ = (gdb_byte
) ((word
>> 8) & 0xff);
2238 *p
++ = (gdb_byte
) (word
& 0xff);
2241 /* Implied "Finish" to terminate the list. */
2245 /* Push entry onto vector. They are guaranteed to always
2246 appear in order of increasing addresses. */
2247 new_exidx_entry
.addr
= idx
;
2248 new_exidx_entry
.entry
= entry
;
2249 VEC_safe_push (arm_exidx_entry_s
,
2250 data
->section_maps
[sec
->the_bfd_section
->index
],
2254 do_cleanups (cleanups
);
2257 /* Search for the exception table entry covering MEMADDR. If one is found,
2258 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2259 set *START to the start of the region covered by this entry. */
2262 arm_find_exidx_entry (CORE_ADDR memaddr
, CORE_ADDR
*start
)
2264 struct obj_section
*sec
;
2266 sec
= find_pc_section (memaddr
);
2269 struct arm_exidx_data
*data
;
2270 VEC(arm_exidx_entry_s
) *map
;
2271 struct arm_exidx_entry map_key
= { memaddr
- obj_section_addr (sec
), 0 };
2274 data
= ((struct arm_exidx_data
*)
2275 objfile_data (sec
->objfile
, arm_exidx_data_key
));
2278 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
2279 if (!VEC_empty (arm_exidx_entry_s
, map
))
2281 struct arm_exidx_entry
*map_sym
;
2283 idx
= VEC_lower_bound (arm_exidx_entry_s
, map
, &map_key
,
2284 arm_compare_exidx_entries
);
2286 /* VEC_lower_bound finds the earliest ordered insertion
2287 point. If the following symbol starts at this exact
2288 address, we use that; otherwise, the preceding
2289 exception table entry covers this address. */
2290 if (idx
< VEC_length (arm_exidx_entry_s
, map
))
2292 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
);
2293 if (map_sym
->addr
== map_key
.addr
)
2296 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2297 return map_sym
->entry
;
2303 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
- 1);
2305 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2306 return map_sym
->entry
;
2315 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2316 instruction list from the ARM exception table entry ENTRY, allocate and
2317 return a prologue cache structure describing how to unwind this frame.
2319 Return NULL if the unwinding instruction list contains a "spare",
2320 "reserved" or "refuse to unwind" instruction as defined in section
2321 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2322 for the ARM Architecture" document. */
2324 static struct arm_prologue_cache
*
2325 arm_exidx_fill_cache (struct frame_info
*this_frame
, gdb_byte
*entry
)
2330 struct arm_prologue_cache
*cache
;
2331 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2332 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2338 /* Whenever we reload SP, we actually have to retrieve its
2339 actual value in the current frame. */
2342 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2344 int reg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2345 vsp
= get_frame_register_unsigned (this_frame
, reg
);
2349 CORE_ADDR addr
= cache
->saved_regs
[ARM_SP_REGNUM
].addr
;
2350 vsp
= get_frame_memory_unsigned (this_frame
, addr
, 4);
2356 /* Decode next unwind instruction. */
2359 if ((insn
& 0xc0) == 0)
2361 int offset
= insn
& 0x3f;
2362 vsp
+= (offset
<< 2) + 4;
2364 else if ((insn
& 0xc0) == 0x40)
2366 int offset
= insn
& 0x3f;
2367 vsp
-= (offset
<< 2) + 4;
2369 else if ((insn
& 0xf0) == 0x80)
2371 int mask
= ((insn
& 0xf) << 8) | *entry
++;
2374 /* The special case of an all-zero mask identifies
2375 "Refuse to unwind". We return NULL to fall back
2376 to the prologue analyzer. */
2380 /* Pop registers r4..r15 under mask. */
2381 for (i
= 0; i
< 12; i
++)
2382 if (mask
& (1 << i
))
2384 cache
->saved_regs
[4 + i
].addr
= vsp
;
2388 /* Special-case popping SP -- we need to reload vsp. */
2389 if (mask
& (1 << (ARM_SP_REGNUM
- 4)))
2392 else if ((insn
& 0xf0) == 0x90)
2394 int reg
= insn
& 0xf;
2396 /* Reserved cases. */
2397 if (reg
== ARM_SP_REGNUM
|| reg
== ARM_PC_REGNUM
)
2400 /* Set SP from another register and mark VSP for reload. */
2401 cache
->saved_regs
[ARM_SP_REGNUM
] = cache
->saved_regs
[reg
];
2404 else if ((insn
& 0xf0) == 0xa0)
2406 int count
= insn
& 0x7;
2407 int pop_lr
= (insn
& 0x8) != 0;
2410 /* Pop r4..r[4+count]. */
2411 for (i
= 0; i
<= count
; i
++)
2413 cache
->saved_regs
[4 + i
].addr
= vsp
;
2417 /* If indicated by flag, pop LR as well. */
2420 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= vsp
;
2424 else if (insn
== 0xb0)
2426 /* We could only have updated PC by popping into it; if so, it
2427 will show up as address. Otherwise, copy LR into PC. */
2428 if (!trad_frame_addr_p (cache
->saved_regs
, ARM_PC_REGNUM
))
2429 cache
->saved_regs
[ARM_PC_REGNUM
]
2430 = cache
->saved_regs
[ARM_LR_REGNUM
];
2435 else if (insn
== 0xb1)
2437 int mask
= *entry
++;
2440 /* All-zero mask and mask >= 16 is "spare". */
2441 if (mask
== 0 || mask
>= 16)
2444 /* Pop r0..r3 under mask. */
2445 for (i
= 0; i
< 4; i
++)
2446 if (mask
& (1 << i
))
2448 cache
->saved_regs
[i
].addr
= vsp
;
2452 else if (insn
== 0xb2)
2454 ULONGEST offset
= 0;
2459 offset
|= (*entry
& 0x7f) << shift
;
2462 while (*entry
++ & 0x80);
2464 vsp
+= 0x204 + (offset
<< 2);
2466 else if (insn
== 0xb3)
2468 int start
= *entry
>> 4;
2469 int count
= (*entry
++) & 0xf;
2472 /* Only registers D0..D15 are valid here. */
2473 if (start
+ count
>= 16)
2476 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2477 for (i
= 0; i
<= count
; i
++)
2479 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2483 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2486 else if ((insn
& 0xf8) == 0xb8)
2488 int count
= insn
& 0x7;
2491 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2492 for (i
= 0; i
<= count
; i
++)
2494 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2498 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2501 else if (insn
== 0xc6)
2503 int start
= *entry
>> 4;
2504 int count
= (*entry
++) & 0xf;
2507 /* Only registers WR0..WR15 are valid. */
2508 if (start
+ count
>= 16)
2511 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2512 for (i
= 0; i
<= count
; i
++)
2514 cache
->saved_regs
[ARM_WR0_REGNUM
+ start
+ i
].addr
= vsp
;
2518 else if (insn
== 0xc7)
2520 int mask
= *entry
++;
2523 /* All-zero mask and mask >= 16 is "spare". */
2524 if (mask
== 0 || mask
>= 16)
2527 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2528 for (i
= 0; i
< 4; i
++)
2529 if (mask
& (1 << i
))
2531 cache
->saved_regs
[ARM_WCGR0_REGNUM
+ i
].addr
= vsp
;
2535 else if ((insn
& 0xf8) == 0xc0)
2537 int count
= insn
& 0x7;
2540 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2541 for (i
= 0; i
<= count
; i
++)
2543 cache
->saved_regs
[ARM_WR0_REGNUM
+ 10 + i
].addr
= vsp
;
2547 else if (insn
== 0xc8)
2549 int start
= *entry
>> 4;
2550 int count
= (*entry
++) & 0xf;
2553 /* Only registers D0..D31 are valid. */
2554 if (start
+ count
>= 16)
2557 /* Pop VFP double-precision registers
2558 D[16+start]..D[16+start+count]. */
2559 for (i
= 0; i
<= count
; i
++)
2561 cache
->saved_regs
[ARM_D0_REGNUM
+ 16 + start
+ i
].addr
= vsp
;
2565 else if (insn
== 0xc9)
2567 int start
= *entry
>> 4;
2568 int count
= (*entry
++) & 0xf;
2571 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2572 for (i
= 0; i
<= count
; i
++)
2574 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2578 else if ((insn
& 0xf8) == 0xd0)
2580 int count
= insn
& 0x7;
2583 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2584 for (i
= 0; i
<= count
; i
++)
2586 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2592 /* Everything else is "spare". */
2597 /* If we restore SP from a register, assume this was the frame register.
2598 Otherwise just fall back to SP as frame register. */
2599 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2600 cache
->framereg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2602 cache
->framereg
= ARM_SP_REGNUM
;
2604 /* Determine offset to previous frame. */
2606 = vsp
- get_frame_register_unsigned (this_frame
, cache
->framereg
);
2608 /* We already got the previous SP. */
2609 cache
->prev_sp
= vsp
;
2614 /* Unwinding via ARM exception table entries. Note that the sniffer
2615 already computes a filled-in prologue cache, which is then used
2616 with the same arm_prologue_this_id and arm_prologue_prev_register
2617 routines also used for prologue-parsing based unwinding. */
2620 arm_exidx_unwind_sniffer (const struct frame_unwind
*self
,
2621 struct frame_info
*this_frame
,
2622 void **this_prologue_cache
)
2624 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2625 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2626 CORE_ADDR addr_in_block
, exidx_region
, func_start
;
2627 struct arm_prologue_cache
*cache
;
2630 /* See if we have an ARM exception table entry covering this address. */
2631 addr_in_block
= get_frame_address_in_block (this_frame
);
2632 entry
= arm_find_exidx_entry (addr_in_block
, &exidx_region
);
2636 /* The ARM exception table does not describe unwind information
2637 for arbitrary PC values, but is guaranteed to be correct only
2638 at call sites. We have to decide here whether we want to use
2639 ARM exception table information for this frame, or fall back
2640 to using prologue parsing. (Note that if we have DWARF CFI,
2641 this sniffer isn't even called -- CFI is always preferred.)
2643 Before we make this decision, however, we check whether we
2644 actually have *symbol* information for the current frame.
2645 If not, prologue parsing would not work anyway, so we might
2646 as well use the exception table and hope for the best. */
2647 if (find_pc_partial_function (addr_in_block
, NULL
, &func_start
, NULL
))
2651 /* If the next frame is "normal", we are at a call site in this
2652 frame, so exception information is guaranteed to be valid. */
2653 if (get_next_frame (this_frame
)
2654 && get_frame_type (get_next_frame (this_frame
)) == NORMAL_FRAME
)
2657 /* We also assume exception information is valid if we're currently
2658 blocked in a system call. The system library is supposed to
2659 ensure this, so that e.g. pthread cancellation works. */
2660 if (arm_frame_is_thumb (this_frame
))
2664 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 2, 2,
2665 byte_order_for_code
, &insn
)
2666 && (insn
& 0xff00) == 0xdf00 /* svc */)
2673 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 4, 4,
2674 byte_order_for_code
, &insn
)
2675 && (insn
& 0x0f000000) == 0x0f000000 /* svc */)
2679 /* Bail out if we don't know that exception information is valid. */
2683 /* The ARM exception index does not mark the *end* of the region
2684 covered by the entry, and some functions will not have any entry.
2685 To correctly recognize the end of the covered region, the linker
2686 should have inserted dummy records with a CANTUNWIND marker.
2688 Unfortunately, current versions of GNU ld do not reliably do
2689 this, and thus we may have found an incorrect entry above.
2690 As a (temporary) sanity check, we only use the entry if it
2691 lies *within* the bounds of the function. Note that this check
2692 might reject perfectly valid entries that just happen to cover
2693 multiple functions; therefore this check ought to be removed
2694 once the linker is fixed. */
2695 if (func_start
> exidx_region
)
2699 /* Decode the list of unwinding instructions into a prologue cache.
2700 Note that this may fail due to e.g. a "refuse to unwind" code. */
2701 cache
= arm_exidx_fill_cache (this_frame
, entry
);
2705 *this_prologue_cache
= cache
;
2709 struct frame_unwind arm_exidx_unwind
= {
2711 default_frame_unwind_stop_reason
,
2712 arm_prologue_this_id
,
2713 arm_prologue_prev_register
,
2715 arm_exidx_unwind_sniffer
2718 static struct arm_prologue_cache
*
2719 arm_make_epilogue_frame_cache (struct frame_info
*this_frame
)
2721 struct arm_prologue_cache
*cache
;
2724 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2725 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2727 /* Still rely on the offset calculated from prologue. */
2728 arm_scan_prologue (this_frame
, cache
);
2730 /* Since we are in epilogue, the SP has been restored. */
2731 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2733 /* Calculate actual addresses of saved registers using offsets
2734 determined by arm_scan_prologue. */
2735 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
2736 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
2737 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
2742 /* Implementation of function hook 'this_id' in
2743 'struct frame_uwnind' for epilogue unwinder. */
2746 arm_epilogue_frame_this_id (struct frame_info
*this_frame
,
2748 struct frame_id
*this_id
)
2750 struct arm_prologue_cache
*cache
;
2753 if (*this_cache
== NULL
)
2754 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2755 cache
= (struct arm_prologue_cache
*) *this_cache
;
2757 /* Use function start address as part of the frame ID. If we cannot
2758 identify the start address (due to missing symbol information),
2759 fall back to just using the current PC. */
2760 pc
= get_frame_pc (this_frame
);
2761 func
= get_frame_func (this_frame
);
2765 (*this_id
) = frame_id_build (cache
->prev_sp
, pc
);
2768 /* Implementation of function hook 'prev_register' in
2769 'struct frame_uwnind' for epilogue unwinder. */
2771 static struct value
*
2772 arm_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2773 void **this_cache
, int regnum
)
2775 if (*this_cache
== NULL
)
2776 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2778 return arm_prologue_prev_register (this_frame
, this_cache
, regnum
);
2781 static int arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
,
2783 static int thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
,
2786 /* Implementation of function hook 'sniffer' in
2787 'struct frame_uwnind' for epilogue unwinder. */
2790 arm_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2791 struct frame_info
*this_frame
,
2792 void **this_prologue_cache
)
2794 if (frame_relative_level (this_frame
) == 0)
2796 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2797 CORE_ADDR pc
= get_frame_pc (this_frame
);
2799 if (arm_frame_is_thumb (this_frame
))
2800 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
2802 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
2808 /* Frame unwinder from epilogue. */
2810 static const struct frame_unwind arm_epilogue_frame_unwind
=
2813 default_frame_unwind_stop_reason
,
2814 arm_epilogue_frame_this_id
,
2815 arm_epilogue_frame_prev_register
,
2817 arm_epilogue_frame_sniffer
,
2820 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2821 trampoline, return the target PC. Otherwise return 0.
2823 void call0a (char c, short s, int i, long l) {}
2827 (*pointer_to_call0a) (c, s, i, l);
2830 Instead of calling a stub library function _call_via_xx (xx is
2831 the register name), GCC may inline the trampoline in the object
2832 file as below (register r2 has the address of call0a).
2835 .type main, %function
2844 The trampoline 'bx r2' doesn't belong to main. */
2847 arm_skip_bx_reg (struct frame_info
*frame
, CORE_ADDR pc
)
2849 /* The heuristics of recognizing such trampoline is that FRAME is
2850 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2851 if (arm_frame_is_thumb (frame
))
2855 if (target_read_memory (pc
, buf
, 2) == 0)
2857 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2858 enum bfd_endian byte_order_for_code
2859 = gdbarch_byte_order_for_code (gdbarch
);
2861 = extract_unsigned_integer (buf
, 2, byte_order_for_code
);
2863 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
2866 = get_frame_register_unsigned (frame
, bits (insn
, 3, 6));
2868 /* Clear the LSB so that gdb core sets step-resume
2869 breakpoint at the right address. */
2870 return UNMAKE_THUMB_ADDR (dest
);
2878 static struct arm_prologue_cache
*
2879 arm_make_stub_cache (struct frame_info
*this_frame
)
2881 struct arm_prologue_cache
*cache
;
2883 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2884 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2886 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2891 /* Our frame ID for a stub frame is the current SP and LR. */
2894 arm_stub_this_id (struct frame_info
*this_frame
,
2896 struct frame_id
*this_id
)
2898 struct arm_prologue_cache
*cache
;
2900 if (*this_cache
== NULL
)
2901 *this_cache
= arm_make_stub_cache (this_frame
);
2902 cache
= (struct arm_prologue_cache
*) *this_cache
;
2904 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
2908 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
2909 struct frame_info
*this_frame
,
2910 void **this_prologue_cache
)
2912 CORE_ADDR addr_in_block
;
2914 CORE_ADDR pc
, start_addr
;
2917 addr_in_block
= get_frame_address_in_block (this_frame
);
2918 pc
= get_frame_pc (this_frame
);
2919 if (in_plt_section (addr_in_block
)
2920 /* We also use the stub winder if the target memory is unreadable
2921 to avoid having the prologue unwinder trying to read it. */
2922 || target_read_memory (pc
, dummy
, 4) != 0)
2925 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0
2926 && arm_skip_bx_reg (this_frame
, pc
) != 0)
2932 struct frame_unwind arm_stub_unwind
= {
2934 default_frame_unwind_stop_reason
,
2936 arm_prologue_prev_register
,
2938 arm_stub_unwind_sniffer
2941 /* Put here the code to store, into CACHE->saved_regs, the addresses
2942 of the saved registers of frame described by THIS_FRAME. CACHE is
2945 static struct arm_prologue_cache
*
2946 arm_m_exception_cache (struct frame_info
*this_frame
)
2948 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2949 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2950 struct arm_prologue_cache
*cache
;
2951 CORE_ADDR unwound_sp
;
2954 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2955 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2957 unwound_sp
= get_frame_register_unsigned (this_frame
,
2960 /* The hardware saves eight 32-bit words, comprising xPSR,
2961 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
2962 "B1.5.6 Exception entry behavior" in
2963 "ARMv7-M Architecture Reference Manual". */
2964 cache
->saved_regs
[0].addr
= unwound_sp
;
2965 cache
->saved_regs
[1].addr
= unwound_sp
+ 4;
2966 cache
->saved_regs
[2].addr
= unwound_sp
+ 8;
2967 cache
->saved_regs
[3].addr
= unwound_sp
+ 12;
2968 cache
->saved_regs
[12].addr
= unwound_sp
+ 16;
2969 cache
->saved_regs
[14].addr
= unwound_sp
+ 20;
2970 cache
->saved_regs
[15].addr
= unwound_sp
+ 24;
2971 cache
->saved_regs
[ARM_PS_REGNUM
].addr
= unwound_sp
+ 28;
2973 /* If bit 9 of the saved xPSR is set, then there is a four-byte
2974 aligner between the top of the 32-byte stack frame and the
2975 previous context's stack pointer. */
2976 cache
->prev_sp
= unwound_sp
+ 32;
2977 if (safe_read_memory_integer (unwound_sp
+ 28, 4, byte_order
, &xpsr
)
2978 && (xpsr
& (1 << 9)) != 0)
2979 cache
->prev_sp
+= 4;
2984 /* Implementation of function hook 'this_id' in
2985 'struct frame_uwnind'. */
2988 arm_m_exception_this_id (struct frame_info
*this_frame
,
2990 struct frame_id
*this_id
)
2992 struct arm_prologue_cache
*cache
;
2994 if (*this_cache
== NULL
)
2995 *this_cache
= arm_m_exception_cache (this_frame
);
2996 cache
= (struct arm_prologue_cache
*) *this_cache
;
2998 /* Our frame ID for a stub frame is the current SP and LR. */
2999 *this_id
= frame_id_build (cache
->prev_sp
,
3000 get_frame_pc (this_frame
));
3003 /* Implementation of function hook 'prev_register' in
3004 'struct frame_uwnind'. */
3006 static struct value
*
3007 arm_m_exception_prev_register (struct frame_info
*this_frame
,
3011 struct arm_prologue_cache
*cache
;
3013 if (*this_cache
== NULL
)
3014 *this_cache
= arm_m_exception_cache (this_frame
);
3015 cache
= (struct arm_prologue_cache
*) *this_cache
;
3017 /* The value was already reconstructed into PREV_SP. */
3018 if (prev_regnum
== ARM_SP_REGNUM
)
3019 return frame_unwind_got_constant (this_frame
, prev_regnum
,
3022 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
3026 /* Implementation of function hook 'sniffer' in
3027 'struct frame_uwnind'. */
3030 arm_m_exception_unwind_sniffer (const struct frame_unwind
*self
,
3031 struct frame_info
*this_frame
,
3032 void **this_prologue_cache
)
3034 CORE_ADDR this_pc
= get_frame_pc (this_frame
);
3036 /* No need to check is_m; this sniffer is only registered for
3037 M-profile architectures. */
3039 /* Check if exception frame returns to a magic PC value. */
3040 return arm_m_addr_is_magic (this_pc
);
3043 /* Frame unwinder for M-profile exceptions. */
3045 struct frame_unwind arm_m_exception_unwind
=
3048 default_frame_unwind_stop_reason
,
3049 arm_m_exception_this_id
,
3050 arm_m_exception_prev_register
,
3052 arm_m_exception_unwind_sniffer
3056 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
3058 struct arm_prologue_cache
*cache
;
3060 if (*this_cache
== NULL
)
3061 *this_cache
= arm_make_prologue_cache (this_frame
);
3062 cache
= (struct arm_prologue_cache
*) *this_cache
;
3064 return cache
->prev_sp
- cache
->framesize
;
3067 struct frame_base arm_normal_base
= {
3068 &arm_prologue_unwind
,
3069 arm_normal_frame_base
,
3070 arm_normal_frame_base
,
3071 arm_normal_frame_base
3074 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3075 dummy frame. The frame ID's base needs to match the TOS value
3076 saved by save_dummy_frame_tos() and returned from
3077 arm_push_dummy_call, and the PC needs to match the dummy frame's
3080 static struct frame_id
3081 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3083 return frame_id_build (get_frame_register_unsigned (this_frame
,
3085 get_frame_pc (this_frame
));
3088 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3089 be used to construct the previous frame's ID, after looking up the
3090 containing function). */
3093 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3096 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
3097 return arm_addr_bits_remove (gdbarch
, pc
);
3101 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3103 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
3106 static struct value
*
3107 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
3110 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
3112 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
3117 /* The PC is normally copied from the return column, which
3118 describes saves of LR. However, that version may have an
3119 extra bit set to indicate Thumb state. The bit is not
3121 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3122 return frame_unwind_got_constant (this_frame
, regnum
,
3123 arm_addr_bits_remove (gdbarch
, lr
));
3126 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3127 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
3128 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3129 if (IS_THUMB_ADDR (lr
))
3133 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
3136 internal_error (__FILE__
, __LINE__
,
3137 _("Unexpected register %d"), regnum
);
3142 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3143 struct dwarf2_frame_state_reg
*reg
,
3144 struct frame_info
*this_frame
)
3150 reg
->how
= DWARF2_FRAME_REG_FN
;
3151 reg
->loc
.fn
= arm_dwarf2_prev_register
;
3154 reg
->how
= DWARF2_FRAME_REG_CFA
;
3159 /* Implement the stack_frame_destroyed_p gdbarch method. */
3162 thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3164 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3165 unsigned int insn
, insn2
;
3166 int found_return
= 0, found_stack_adjust
= 0;
3167 CORE_ADDR func_start
, func_end
;
3171 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3174 /* The epilogue is a sequence of instructions along the following lines:
3176 - add stack frame size to SP or FP
3177 - [if frame pointer used] restore SP from FP
3178 - restore registers from SP [may include PC]
3179 - a return-type instruction [if PC wasn't already restored]
3181 In a first pass, we scan forward from the current PC and verify the
3182 instructions we find as compatible with this sequence, ending in a
3185 However, this is not sufficient to distinguish indirect function calls
3186 within a function from indirect tail calls in the epilogue in some cases.
3187 Therefore, if we didn't already find any SP-changing instruction during
3188 forward scan, we add a backward scanning heuristic to ensure we actually
3189 are in the epilogue. */
3192 while (scan_pc
< func_end
&& !found_return
)
3194 if (target_read_memory (scan_pc
, buf
, 2))
3198 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3200 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3202 else if (insn
== 0x46f7) /* mov pc, lr */
3204 else if (thumb_instruction_restores_sp (insn
))
3206 if ((insn
& 0xff00) == 0xbd00) /* pop <registers, PC> */
3209 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instruction */
3211 if (target_read_memory (scan_pc
, buf
, 2))
3215 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3217 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3219 if (insn2
& 0x8000) /* <registers> include PC. */
3222 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3223 && (insn2
& 0x0fff) == 0x0b04)
3225 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
3228 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3229 && (insn2
& 0x0e00) == 0x0a00)
3241 /* Since any instruction in the epilogue sequence, with the possible
3242 exception of return itself, updates the stack pointer, we need to
3243 scan backwards for at most one instruction. Try either a 16-bit or
3244 a 32-bit instruction. This is just a heuristic, so we do not worry
3245 too much about false positives. */
3247 if (pc
- 4 < func_start
)
3249 if (target_read_memory (pc
- 4, buf
, 4))
3252 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3253 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
3255 if (thumb_instruction_restores_sp (insn2
))
3256 found_stack_adjust
= 1;
3257 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3258 found_stack_adjust
= 1;
3259 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3260 && (insn2
& 0x0fff) == 0x0b04)
3261 found_stack_adjust
= 1;
3262 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3263 && (insn2
& 0x0e00) == 0x0a00)
3264 found_stack_adjust
= 1;
3266 return found_stack_adjust
;
3270 arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3272 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3275 CORE_ADDR func_start
, func_end
;
3277 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3280 /* We are in the epilogue if the previous instruction was a stack
3281 adjustment and the next instruction is a possible return (bx, mov
3282 pc, or pop). We could have to scan backwards to find the stack
3283 adjustment, or forwards to find the return, but this is a decent
3284 approximation. First scan forwards. */
3287 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3288 if (bits (insn
, 28, 31) != INST_NV
)
3290 if ((insn
& 0x0ffffff0) == 0x012fff10)
3293 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
3296 else if ((insn
& 0x0fff0000) == 0x08bd0000
3297 && (insn
& 0x0000c000) != 0)
3298 /* POP (LDMIA), including PC or LR. */
3305 /* Scan backwards. This is just a heuristic, so do not worry about
3306 false positives from mode changes. */
3308 if (pc
< func_start
+ 4)
3311 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
3312 if (arm_instruction_restores_sp (insn
))
3318 /* Implement the stack_frame_destroyed_p gdbarch method. */
3321 arm_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3323 if (arm_pc_is_thumb (gdbarch
, pc
))
3324 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
3326 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
3329 /* When arguments must be pushed onto the stack, they go on in reverse
3330 order. The code below implements a FILO (stack) to do this. */
3335 struct stack_item
*prev
;
3339 static struct stack_item
*
3340 push_stack_item (struct stack_item
*prev
, const gdb_byte
*contents
, int len
)
3342 struct stack_item
*si
;
3343 si
= XNEW (struct stack_item
);
3344 si
->data
= (gdb_byte
*) xmalloc (len
);
3347 memcpy (si
->data
, contents
, len
);
3351 static struct stack_item
*
3352 pop_stack_item (struct stack_item
*si
)
3354 struct stack_item
*dead
= si
;
3362 /* Return the alignment (in bytes) of the given type. */
3365 arm_type_align (struct type
*t
)
3371 t
= check_typedef (t
);
3372 switch (TYPE_CODE (t
))
3375 /* Should never happen. */
3376 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
3380 case TYPE_CODE_ENUM
:
3384 case TYPE_CODE_RANGE
:
3386 case TYPE_CODE_CHAR
:
3387 case TYPE_CODE_BOOL
:
3388 return TYPE_LENGTH (t
);
3390 case TYPE_CODE_ARRAY
:
3391 if (TYPE_VECTOR (t
))
3393 /* Use the natural alignment for vector types (the same for
3394 scalar type), but the maximum alignment is 64-bit. */
3395 if (TYPE_LENGTH (t
) > 8)
3398 return TYPE_LENGTH (t
);
3401 return arm_type_align (TYPE_TARGET_TYPE (t
));
3402 case TYPE_CODE_COMPLEX
:
3403 return arm_type_align (TYPE_TARGET_TYPE (t
));
3405 case TYPE_CODE_STRUCT
:
3406 case TYPE_CODE_UNION
:
3408 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
3410 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
3418 /* Possible base types for a candidate for passing and returning in
3421 enum arm_vfp_cprc_base_type
3430 /* The length of one element of base type B. */
3433 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
3437 case VFP_CPRC_SINGLE
:
3439 case VFP_CPRC_DOUBLE
:
3441 case VFP_CPRC_VEC64
:
3443 case VFP_CPRC_VEC128
:
3446 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3451 /* The character ('s', 'd' or 'q') for the type of VFP register used
3452 for passing base type B. */
3455 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
3459 case VFP_CPRC_SINGLE
:
3461 case VFP_CPRC_DOUBLE
:
3463 case VFP_CPRC_VEC64
:
3465 case VFP_CPRC_VEC128
:
3468 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3473 /* Determine whether T may be part of a candidate for passing and
3474 returning in VFP registers, ignoring the limit on the total number
3475 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3476 classification of the first valid component found; if it is not
3477 VFP_CPRC_UNKNOWN, all components must have the same classification
3478 as *BASE_TYPE. If it is found that T contains a type not permitted
3479 for passing and returning in VFP registers, a type differently
3480 classified from *BASE_TYPE, or two types differently classified
3481 from each other, return -1, otherwise return the total number of
3482 base-type elements found (possibly 0 in an empty structure or
3483 array). Vector types are not currently supported, matching the
3484 generic AAPCS support. */
3487 arm_vfp_cprc_sub_candidate (struct type
*t
,
3488 enum arm_vfp_cprc_base_type
*base_type
)
3490 t
= check_typedef (t
);
3491 switch (TYPE_CODE (t
))
3494 switch (TYPE_LENGTH (t
))
3497 if (*base_type
== VFP_CPRC_UNKNOWN
)
3498 *base_type
= VFP_CPRC_SINGLE
;
3499 else if (*base_type
!= VFP_CPRC_SINGLE
)
3504 if (*base_type
== VFP_CPRC_UNKNOWN
)
3505 *base_type
= VFP_CPRC_DOUBLE
;
3506 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3515 case TYPE_CODE_COMPLEX
:
3516 /* Arguments of complex T where T is one of the types float or
3517 double get treated as if they are implemented as:
3526 switch (TYPE_LENGTH (t
))
3529 if (*base_type
== VFP_CPRC_UNKNOWN
)
3530 *base_type
= VFP_CPRC_SINGLE
;
3531 else if (*base_type
!= VFP_CPRC_SINGLE
)
3536 if (*base_type
== VFP_CPRC_UNKNOWN
)
3537 *base_type
= VFP_CPRC_DOUBLE
;
3538 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3547 case TYPE_CODE_ARRAY
:
3549 if (TYPE_VECTOR (t
))
3551 /* A 64-bit or 128-bit containerized vector type are VFP
3553 switch (TYPE_LENGTH (t
))
3556 if (*base_type
== VFP_CPRC_UNKNOWN
)
3557 *base_type
= VFP_CPRC_VEC64
;
3560 if (*base_type
== VFP_CPRC_UNKNOWN
)
3561 *base_type
= VFP_CPRC_VEC128
;
3572 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
),
3576 if (TYPE_LENGTH (t
) == 0)
3578 gdb_assert (count
== 0);
3581 else if (count
== 0)
3583 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3584 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
3585 return TYPE_LENGTH (t
) / unitlen
;
3590 case TYPE_CODE_STRUCT
:
3595 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3599 if (!field_is_static (&TYPE_FIELD (t
, i
)))
3600 sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3602 if (sub_count
== -1)
3606 if (TYPE_LENGTH (t
) == 0)
3608 gdb_assert (count
== 0);
3611 else if (count
== 0)
3613 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3614 if (TYPE_LENGTH (t
) != unitlen
* count
)
3619 case TYPE_CODE_UNION
:
3624 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3626 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3628 if (sub_count
== -1)
3630 count
= (count
> sub_count
? count
: sub_count
);
3632 if (TYPE_LENGTH (t
) == 0)
3634 gdb_assert (count
== 0);
3637 else if (count
== 0)
3639 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3640 if (TYPE_LENGTH (t
) != unitlen
* count
)
3652 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3653 if passed to or returned from a non-variadic function with the VFP
3654 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3655 *BASE_TYPE to the base type for T and *COUNT to the number of
3656 elements of that base type before returning. */
3659 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
3662 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
3663 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
3664 if (c
<= 0 || c
> 4)
3671 /* Return 1 if the VFP ABI should be used for passing arguments to and
3672 returning values from a function of type FUNC_TYPE, 0
3676 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
3678 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3679 /* Variadic functions always use the base ABI. Assume that functions
3680 without debug info are not variadic. */
3681 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
3683 /* The VFP ABI is only supported as a variant of AAPCS. */
3684 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
3686 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
3689 /* We currently only support passing parameters in integer registers, which
3690 conforms with GCC's default model, and VFP argument passing following
3691 the VFP variant of AAPCS. Several other variants exist and
3692 we should probably support some of them based on the selected ABI. */
3695 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3696 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3697 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3698 CORE_ADDR struct_addr
)
3700 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3704 struct stack_item
*si
= NULL
;
3707 unsigned vfp_regs_free
= (1 << 16) - 1;
3709 /* Determine the type of this function and whether the VFP ABI
3711 ftype
= check_typedef (value_type (function
));
3712 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
3713 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
3714 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
3716 /* Set the return address. For the ARM, the return breakpoint is
3717 always at BP_ADDR. */
3718 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
3720 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
3722 /* Walk through the list of args and determine how large a temporary
3723 stack is required. Need to take care here as structs may be
3724 passed on the stack, and we have to push them. */
3727 argreg
= ARM_A1_REGNUM
;
3730 /* The struct_return pointer occupies the first parameter
3731 passing register. */
3735 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
3736 gdbarch_register_name (gdbarch
, argreg
),
3737 paddress (gdbarch
, struct_addr
));
3738 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
3742 for (argnum
= 0; argnum
< nargs
; argnum
++)
3745 struct type
*arg_type
;
3746 struct type
*target_type
;
3747 enum type_code typecode
;
3748 const bfd_byte
*val
;
3750 enum arm_vfp_cprc_base_type vfp_base_type
;
3752 int may_use_core_reg
= 1;
3754 arg_type
= check_typedef (value_type (args
[argnum
]));
3755 len
= TYPE_LENGTH (arg_type
);
3756 target_type
= TYPE_TARGET_TYPE (arg_type
);
3757 typecode
= TYPE_CODE (arg_type
);
3758 val
= value_contents (args
[argnum
]);
3760 align
= arm_type_align (arg_type
);
3761 /* Round alignment up to a whole number of words. */
3762 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
3763 /* Different ABIs have different maximum alignments. */
3764 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
3766 /* The APCS ABI only requires word alignment. */
3767 align
= INT_REGISTER_SIZE
;
3771 /* The AAPCS requires at most doubleword alignment. */
3772 if (align
> INT_REGISTER_SIZE
* 2)
3773 align
= INT_REGISTER_SIZE
* 2;
3777 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
3785 /* Because this is a CPRC it cannot go in a core register or
3786 cause a core register to be skipped for alignment.
3787 Either it goes in VFP registers and the rest of this loop
3788 iteration is skipped for this argument, or it goes on the
3789 stack (and the stack alignment code is correct for this
3791 may_use_core_reg
= 0;
3793 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
3794 shift
= unit_length
/ 4;
3795 mask
= (1 << (shift
* vfp_base_count
)) - 1;
3796 for (regno
= 0; regno
< 16; regno
+= shift
)
3797 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
3806 vfp_regs_free
&= ~(mask
<< regno
);
3807 reg_scaled
= regno
/ shift
;
3808 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
3809 for (i
= 0; i
< vfp_base_count
; i
++)
3813 if (reg_char
== 'q')
3814 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
3815 val
+ i
* unit_length
);
3818 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d",
3819 reg_char
, reg_scaled
+ i
);
3820 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3822 regcache_cooked_write (regcache
, regnum
,
3823 val
+ i
* unit_length
);
3830 /* This CPRC could not go in VFP registers, so all VFP
3831 registers are now marked as used. */
3836 /* Push stack padding for dowubleword alignment. */
3837 if (nstack
& (align
- 1))
3839 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3840 nstack
+= INT_REGISTER_SIZE
;
3843 /* Doubleword aligned quantities must go in even register pairs. */
3844 if (may_use_core_reg
3845 && argreg
<= ARM_LAST_ARG_REGNUM
3846 && align
> INT_REGISTER_SIZE
3850 /* If the argument is a pointer to a function, and it is a
3851 Thumb function, create a LOCAL copy of the value and set
3852 the THUMB bit in it. */
3853 if (TYPE_CODE_PTR
== typecode
3854 && target_type
!= NULL
3855 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
3857 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
3858 if (arm_pc_is_thumb (gdbarch
, regval
))
3860 bfd_byte
*copy
= (bfd_byte
*) alloca (len
);
3861 store_unsigned_integer (copy
, len
, byte_order
,
3862 MAKE_THUMB_ADDR (regval
));
3867 /* Copy the argument to general registers or the stack in
3868 register-sized pieces. Large arguments are split between
3869 registers and stack. */
3872 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
3874 = extract_unsigned_integer (val
, partial_len
, byte_order
);
3876 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
3878 /* The argument is being passed in a general purpose
3880 if (byte_order
== BFD_ENDIAN_BIG
)
3881 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
3883 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
3885 gdbarch_register_name
3887 phex (regval
, INT_REGISTER_SIZE
));
3888 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3893 gdb_byte buf
[INT_REGISTER_SIZE
];
3895 memset (buf
, 0, sizeof (buf
));
3896 store_unsigned_integer (buf
, partial_len
, byte_order
, regval
);
3898 /* Push the arguments onto the stack. */
3900 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
3902 si
= push_stack_item (si
, buf
, INT_REGISTER_SIZE
);
3903 nstack
+= INT_REGISTER_SIZE
;
3910 /* If we have an odd number of words to push, then decrement the stack
3911 by one word now, so first stack argument will be dword aligned. */
3918 write_memory (sp
, si
->data
, si
->len
);
3919 si
= pop_stack_item (si
);
3922 /* Finally, update teh SP register. */
3923 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
3929 /* Always align the frame to an 8-byte boundary. This is required on
3930 some platforms and harmless on the rest. */
3933 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3935 /* Align the stack to eight bytes. */
3936 return sp
& ~ (CORE_ADDR
) 7;
3940 print_fpu_flags (struct ui_file
*file
, int flags
)
3942 if (flags
& (1 << 0))
3943 fputs_filtered ("IVO ", file
);
3944 if (flags
& (1 << 1))
3945 fputs_filtered ("DVZ ", file
);
3946 if (flags
& (1 << 2))
3947 fputs_filtered ("OFL ", file
);
3948 if (flags
& (1 << 3))
3949 fputs_filtered ("UFL ", file
);
3950 if (flags
& (1 << 4))
3951 fputs_filtered ("INX ", file
);
3952 fputc_filtered ('\n', file
);
3955 /* Print interesting information about the floating point processor
3956 (if present) or emulator. */
3958 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
3959 struct frame_info
*frame
, const char *args
)
3961 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
3964 type
= (status
>> 24) & 127;
3965 if (status
& (1 << 31))
3966 fprintf_filtered (file
, _("Hardware FPU type %d\n"), type
);
3968 fprintf_filtered (file
, _("Software FPU type %d\n"), type
);
3969 /* i18n: [floating point unit] mask */
3970 fputs_filtered (_("mask: "), file
);
3971 print_fpu_flags (file
, status
>> 16);
3972 /* i18n: [floating point unit] flags */
3973 fputs_filtered (_("flags: "), file
);
3974 print_fpu_flags (file
, status
);
3977 /* Construct the ARM extended floating point type. */
3978 static struct type
*
3979 arm_ext_type (struct gdbarch
*gdbarch
)
3981 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3983 if (!tdep
->arm_ext_type
)
3985 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
3986 floatformats_arm_ext
);
3988 return tdep
->arm_ext_type
;
3991 static struct type
*
3992 arm_neon_double_type (struct gdbarch
*gdbarch
)
3994 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3996 if (tdep
->neon_double_type
== NULL
)
3998 struct type
*t
, *elem
;
4000 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
4002 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4003 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
4004 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4005 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
4006 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4007 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
4008 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4009 append_composite_type_field (t
, "u64", elem
);
4010 elem
= builtin_type (gdbarch
)->builtin_float
;
4011 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
4012 elem
= builtin_type (gdbarch
)->builtin_double
;
4013 append_composite_type_field (t
, "f64", elem
);
4015 TYPE_VECTOR (t
) = 1;
4016 TYPE_NAME (t
) = "neon_d";
4017 tdep
->neon_double_type
= t
;
4020 return tdep
->neon_double_type
;
4023 /* FIXME: The vector types are not correctly ordered on big-endian
4024 targets. Just as s0 is the low bits of d0, d0[0] is also the low
4025 bits of d0 - regardless of what unit size is being held in d0. So
4026 the offset of the first uint8 in d0 is 7, but the offset of the
4027 first float is 4. This code works as-is for little-endian
4030 static struct type
*
4031 arm_neon_quad_type (struct gdbarch
*gdbarch
)
4033 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4035 if (tdep
->neon_quad_type
== NULL
)
4037 struct type
*t
, *elem
;
4039 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
4041 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4042 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
4043 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4044 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
4045 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4046 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
4047 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4048 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
4049 elem
= builtin_type (gdbarch
)->builtin_float
;
4050 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
4051 elem
= builtin_type (gdbarch
)->builtin_double
;
4052 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
4054 TYPE_VECTOR (t
) = 1;
4055 TYPE_NAME (t
) = "neon_q";
4056 tdep
->neon_quad_type
= t
;
4059 return tdep
->neon_quad_type
;
4062 /* Return the GDB type object for the "standard" data type of data in
4065 static struct type
*
4066 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
4068 int num_regs
= gdbarch_num_regs (gdbarch
);
4070 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
4071 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
4072 return builtin_type (gdbarch
)->builtin_float
;
4074 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
4075 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
4076 return arm_neon_quad_type (gdbarch
);
4078 /* If the target description has register information, we are only
4079 in this function so that we can override the types of
4080 double-precision registers for NEON. */
4081 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
4083 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
4085 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
4086 && TYPE_CODE (t
) == TYPE_CODE_FLT
4087 && gdbarch_tdep (gdbarch
)->have_neon
)
4088 return arm_neon_double_type (gdbarch
);
4093 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
4095 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
4096 return builtin_type (gdbarch
)->builtin_void
;
4098 return arm_ext_type (gdbarch
);
4100 else if (regnum
== ARM_SP_REGNUM
)
4101 return builtin_type (gdbarch
)->builtin_data_ptr
;
4102 else if (regnum
== ARM_PC_REGNUM
)
4103 return builtin_type (gdbarch
)->builtin_func_ptr
;
4104 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
4105 /* These registers are only supported on targets which supply
4106 an XML description. */
4107 return builtin_type (gdbarch
)->builtin_int0
;
4109 return builtin_type (gdbarch
)->builtin_uint32
;
4112 /* Map a DWARF register REGNUM onto the appropriate GDB register
4116 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
4118 /* Core integer regs. */
4119 if (reg
>= 0 && reg
<= 15)
4122 /* Legacy FPA encoding. These were once used in a way which
4123 overlapped with VFP register numbering, so their use is
4124 discouraged, but GDB doesn't support the ARM toolchain
4125 which used them for VFP. */
4126 if (reg
>= 16 && reg
<= 23)
4127 return ARM_F0_REGNUM
+ reg
- 16;
4129 /* New assignments for the FPA registers. */
4130 if (reg
>= 96 && reg
<= 103)
4131 return ARM_F0_REGNUM
+ reg
- 96;
4133 /* WMMX register assignments. */
4134 if (reg
>= 104 && reg
<= 111)
4135 return ARM_WCGR0_REGNUM
+ reg
- 104;
4137 if (reg
>= 112 && reg
<= 127)
4138 return ARM_WR0_REGNUM
+ reg
- 112;
4140 if (reg
>= 192 && reg
<= 199)
4141 return ARM_WC0_REGNUM
+ reg
- 192;
4143 /* VFP v2 registers. A double precision value is actually
4144 in d1 rather than s2, but the ABI only defines numbering
4145 for the single precision registers. This will "just work"
4146 in GDB for little endian targets (we'll read eight bytes,
4147 starting in s0 and then progressing to s1), but will be
4148 reversed on big endian targets with VFP. This won't
4149 be a problem for the new Neon quad registers; you're supposed
4150 to use DW_OP_piece for those. */
4151 if (reg
>= 64 && reg
<= 95)
4155 xsnprintf (name_buf
, sizeof (name_buf
), "s%d", reg
- 64);
4156 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4160 /* VFP v3 / Neon registers. This range is also used for VFP v2
4161 registers, except that it now describes d0 instead of s0. */
4162 if (reg
>= 256 && reg
<= 287)
4166 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", reg
- 256);
4167 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4174 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4176 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
4179 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
4181 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
4182 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
4184 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
4185 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
4187 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
4188 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
4190 if (reg
< NUM_GREGS
)
4191 return SIM_ARM_R0_REGNUM
+ reg
;
4194 if (reg
< NUM_FREGS
)
4195 return SIM_ARM_FP0_REGNUM
+ reg
;
4198 if (reg
< NUM_SREGS
)
4199 return SIM_ARM_FPS_REGNUM
+ reg
;
4202 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
4205 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4206 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4207 It is thought that this is is the floating-point register format on
4208 little-endian systems. */
4211 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
4212 void *dbl
, int endianess
)
4216 if (endianess
== BFD_ENDIAN_BIG
)
4217 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
4219 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4221 floatformat_from_doublest (fmt
, &d
, dbl
);
4225 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
4230 floatformat_to_doublest (fmt
, ptr
, &d
);
4231 if (endianess
== BFD_ENDIAN_BIG
)
4232 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
4234 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4238 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
4239 of the appropriate mode (as encoded in the PC value), even if this
4240 differs from what would be expected according to the symbol tables. */
4243 arm_insert_single_step_breakpoint (struct gdbarch
*gdbarch
,
4244 struct address_space
*aspace
,
4247 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4249 insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
4252 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
4253 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
4254 NULL if an error occurs. BUF is freed. */
4257 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
4258 int old_len
, int new_len
)
4261 int bytes_to_read
= new_len
- old_len
;
4263 new_buf
= (gdb_byte
*) xmalloc (new_len
);
4264 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
4266 if (target_read_memory (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
4274 /* An IT block is at most the 2-byte IT instruction followed by
4275 four 4-byte instructions. The furthest back we must search to
4276 find an IT block that affects the current instruction is thus
4277 2 + 3 * 4 == 14 bytes. */
4278 #define MAX_IT_BLOCK_PREFIX 14
4280 /* Use a quick scan if there are more than this many bytes of
4282 #define IT_SCAN_THRESHOLD 32
4284 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
4285 A breakpoint in an IT block may not be hit, depending on the
4288 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
4292 CORE_ADDR boundary
, func_start
;
4294 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
4295 int i
, any
, last_it
, last_it_count
;
4297 /* If we are using BKPT breakpoints, none of this is necessary. */
4298 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
4301 /* ARM mode does not have this problem. */
4302 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
4305 /* We are setting a breakpoint in Thumb code that could potentially
4306 contain an IT block. The first step is to find how much Thumb
4307 code there is; we do not need to read outside of known Thumb
4309 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
4311 /* Thumb-2 code must have mapping symbols to have a chance. */
4314 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
4316 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
4317 && func_start
> boundary
)
4318 boundary
= func_start
;
4320 /* Search for a candidate IT instruction. We have to do some fancy
4321 footwork to distinguish a real IT instruction from the second
4322 half of a 32-bit instruction, but there is no need for that if
4323 there's no candidate. */
4324 buf_len
= std::min (bpaddr
- boundary
, (CORE_ADDR
) MAX_IT_BLOCK_PREFIX
);
4326 /* No room for an IT instruction. */
4329 buf
= (gdb_byte
*) xmalloc (buf_len
);
4330 if (target_read_memory (bpaddr
- buf_len
, buf
, buf_len
) != 0)
4333 for (i
= 0; i
< buf_len
; i
+= 2)
4335 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4336 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4349 /* OK, the code bytes before this instruction contain at least one
4350 halfword which resembles an IT instruction. We know that it's
4351 Thumb code, but there are still two possibilities. Either the
4352 halfword really is an IT instruction, or it is the second half of
4353 a 32-bit Thumb instruction. The only way we can tell is to
4354 scan forwards from a known instruction boundary. */
4355 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
4359 /* There's a lot of code before this instruction. Start with an
4360 optimistic search; it's easy to recognize halfwords that can
4361 not be the start of a 32-bit instruction, and use that to
4362 lock on to the instruction boundaries. */
4363 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
4366 buf_len
= IT_SCAN_THRESHOLD
;
4369 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
4371 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4372 if (thumb_insn_size (inst1
) == 2)
4379 /* At this point, if DEFINITE, BUF[I] is the first place we
4380 are sure that we know the instruction boundaries, and it is far
4381 enough from BPADDR that we could not miss an IT instruction
4382 affecting BPADDR. If ! DEFINITE, give up - start from a
4386 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
,
4390 buf_len
= bpaddr
- boundary
;
4396 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
4399 buf_len
= bpaddr
- boundary
;
4403 /* Scan forwards. Find the last IT instruction before BPADDR. */
4408 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4410 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4415 else if (inst1
& 0x0002)
4417 else if (inst1
& 0x0004)
4422 i
+= thumb_insn_size (inst1
);
4428 /* There wasn't really an IT instruction after all. */
4431 if (last_it_count
< 1)
4432 /* It was too far away. */
4435 /* This really is a trouble spot. Move the breakpoint to the IT
4437 return bpaddr
- buf_len
+ last_it
;
4440 /* ARM displaced stepping support.
4442 Generally ARM displaced stepping works as follows:
4444 1. When an instruction is to be single-stepped, it is first decoded by
4445 arm_process_displaced_insn. Depending on the type of instruction, it is
4446 then copied to a scratch location, possibly in a modified form. The
4447 copy_* set of functions performs such modification, as necessary. A
4448 breakpoint is placed after the modified instruction in the scratch space
4449 to return control to GDB. Note in particular that instructions which
4450 modify the PC will no longer do so after modification.
4452 2. The instruction is single-stepped, by setting the PC to the scratch
4453 location address, and resuming. Control returns to GDB when the
4456 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
4457 function used for the current instruction. This function's job is to
4458 put the CPU/memory state back to what it would have been if the
4459 instruction had been executed unmodified in its original location. */
4461 /* NOP instruction (mov r0, r0). */
4462 #define ARM_NOP 0xe1a00000
4463 #define THUMB_NOP 0x4600
4465 /* Helper for register reads for displaced stepping. In particular, this
4466 returns the PC as it would be seen by the instruction at its original
4470 displaced_read_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4474 CORE_ADDR from
= dsc
->insn_addr
;
4476 if (regno
== ARM_PC_REGNUM
)
4478 /* Compute pipeline offset:
4479 - When executing an ARM instruction, PC reads as the address of the
4480 current instruction plus 8.
4481 - When executing a Thumb instruction, PC reads as the address of the
4482 current instruction plus 4. */
4489 if (debug_displaced
)
4490 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
4491 (unsigned long) from
);
4492 return (ULONGEST
) from
;
4496 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
4497 if (debug_displaced
)
4498 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
4499 regno
, (unsigned long) ret
);
4505 displaced_in_arm_mode (struct regcache
*regs
)
4508 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
4510 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4512 return (ps
& t_bit
) == 0;
4515 /* Write to the PC as from a branch instruction. */
4518 branch_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4522 /* Note: If bits 0/1 are set, this branch would be unpredictable for
4523 architecture versions < 6. */
4524 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4525 val
& ~(ULONGEST
) 0x3);
4527 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4528 val
& ~(ULONGEST
) 0x1);
4531 /* Write to the PC as from a branch-exchange instruction. */
4534 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
4537 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
4539 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4543 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
4544 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
4546 else if ((val
& 2) == 0)
4548 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4549 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
4553 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
4554 mode, align dest to 4 bytes). */
4555 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
4556 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4557 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
4561 /* Write to the PC as if from a load instruction. */
4564 load_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4567 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
4568 bx_write_pc (regs
, val
);
4570 branch_write_pc (regs
, dsc
, val
);
4573 /* Write to the PC as if from an ALU instruction. */
4576 alu_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4579 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && !dsc
->is_thumb
)
4580 bx_write_pc (regs
, val
);
4582 branch_write_pc (regs
, dsc
, val
);
4585 /* Helper for writing to registers for displaced stepping. Writing to the PC
4586 has a varying effects depending on the instruction which does the write:
4587 this is controlled by the WRITE_PC argument. */
4590 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4591 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
4593 if (regno
== ARM_PC_REGNUM
)
4595 if (debug_displaced
)
4596 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
4597 (unsigned long) val
);
4600 case BRANCH_WRITE_PC
:
4601 branch_write_pc (regs
, dsc
, val
);
4605 bx_write_pc (regs
, val
);
4609 load_write_pc (regs
, dsc
, val
);
4613 alu_write_pc (regs
, dsc
, val
);
4616 case CANNOT_WRITE_PC
:
4617 warning (_("Instruction wrote to PC in an unexpected way when "
4618 "single-stepping"));
4622 internal_error (__FILE__
, __LINE__
,
4623 _("Invalid argument to displaced_write_reg"));
4626 dsc
->wrote_to_pc
= 1;
4630 if (debug_displaced
)
4631 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
4632 regno
, (unsigned long) val
);
4633 regcache_cooked_write_unsigned (regs
, regno
, val
);
4637 /* This function is used to concisely determine if an instruction INSN
4638 references PC. Register fields of interest in INSN should have the
4639 corresponding fields of BITMASK set to 0b1111. The function
4640 returns return 1 if any of these fields in INSN reference the PC
4641 (also 0b1111, r15), else it returns 0. */
4644 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
4646 uint32_t lowbit
= 1;
4648 while (bitmask
!= 0)
4652 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
4658 mask
= lowbit
* 0xf;
4660 if ((insn
& mask
) == mask
)
4669 /* The simplest copy function. Many instructions have the same effect no
4670 matter what address they are executed at: in those cases, use this. */
4673 arm_copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
4674 const char *iname
, struct displaced_step_closure
*dsc
)
4676 if (debug_displaced
)
4677 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
4678 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
4681 dsc
->modinsn
[0] = insn
;
4687 thumb_copy_unmodified_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
4688 uint16_t insn2
, const char *iname
,
4689 struct displaced_step_closure
*dsc
)
4691 if (debug_displaced
)
4692 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x %.4x, "
4693 "opcode/class '%s' unmodified\n", insn1
, insn2
,
4696 dsc
->modinsn
[0] = insn1
;
4697 dsc
->modinsn
[1] = insn2
;
4703 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
4706 thumb_copy_unmodified_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
4708 struct displaced_step_closure
*dsc
)
4710 if (debug_displaced
)
4711 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x, "
4712 "opcode/class '%s' unmodified\n", insn
,
4715 dsc
->modinsn
[0] = insn
;
4720 /* Preload instructions with immediate offset. */
4723 cleanup_preload (struct gdbarch
*gdbarch
,
4724 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4726 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4727 if (!dsc
->u
.preload
.immed
)
4728 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
4732 install_preload (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4733 struct displaced_step_closure
*dsc
, unsigned int rn
)
4736 /* Preload instructions:
4738 {pli/pld} [rn, #+/-imm]
4740 {pli/pld} [r0, #+/-imm]. */
4742 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4743 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4744 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4745 dsc
->u
.preload
.immed
= 1;
4747 dsc
->cleanup
= &cleanup_preload
;
4751 arm_copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4752 struct displaced_step_closure
*dsc
)
4754 unsigned int rn
= bits (insn
, 16, 19);
4756 if (!insn_references_pc (insn
, 0x000f0000ul
))
4757 return arm_copy_unmodified (gdbarch
, insn
, "preload", dsc
);
4759 if (debug_displaced
)
4760 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4761 (unsigned long) insn
);
4763 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4765 install_preload (gdbarch
, regs
, dsc
, rn
);
4771 thumb2_copy_preload (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
4772 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4774 unsigned int rn
= bits (insn1
, 0, 3);
4775 unsigned int u_bit
= bit (insn1
, 7);
4776 int imm12
= bits (insn2
, 0, 11);
4779 if (rn
!= ARM_PC_REGNUM
)
4780 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "preload", dsc
);
4782 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
4783 PLD (literal) Encoding T1. */
4784 if (debug_displaced
)
4785 fprintf_unfiltered (gdb_stdlog
,
4786 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
4787 (unsigned int) dsc
->insn_addr
, u_bit
? '+' : '-',
4793 /* Rewrite instruction {pli/pld} PC imm12 into:
4794 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
4798 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
4800 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4801 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4803 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
4805 displaced_write_reg (regs
, dsc
, 0, pc_val
, CANNOT_WRITE_PC
);
4806 displaced_write_reg (regs
, dsc
, 1, imm12
, CANNOT_WRITE_PC
);
4807 dsc
->u
.preload
.immed
= 0;
4809 /* {pli/pld} [r0, r1] */
4810 dsc
->modinsn
[0] = insn1
& 0xfff0;
4811 dsc
->modinsn
[1] = 0xf001;
4814 dsc
->cleanup
= &cleanup_preload
;
4818 /* Preload instructions with register offset. */
4821 install_preload_reg(struct gdbarch
*gdbarch
, struct regcache
*regs
,
4822 struct displaced_step_closure
*dsc
, unsigned int rn
,
4825 ULONGEST rn_val
, rm_val
;
4827 /* Preload register-offset instructions:
4829 {pli/pld} [rn, rm {, shift}]
4831 {pli/pld} [r0, r1 {, shift}]. */
4833 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4834 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4835 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4836 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
4837 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4838 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
4839 dsc
->u
.preload
.immed
= 0;
4841 dsc
->cleanup
= &cleanup_preload
;
4845 arm_copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
4846 struct regcache
*regs
,
4847 struct displaced_step_closure
*dsc
)
4849 unsigned int rn
= bits (insn
, 16, 19);
4850 unsigned int rm
= bits (insn
, 0, 3);
4853 if (!insn_references_pc (insn
, 0x000f000ful
))
4854 return arm_copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
4856 if (debug_displaced
)
4857 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4858 (unsigned long) insn
);
4860 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
4862 install_preload_reg (gdbarch
, regs
, dsc
, rn
, rm
);
4866 /* Copy/cleanup coprocessor load and store instructions. */
4869 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
4870 struct regcache
*regs
,
4871 struct displaced_step_closure
*dsc
)
4873 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 0);
4875 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4877 if (dsc
->u
.ldst
.writeback
)
4878 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
4882 install_copro_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4883 struct displaced_step_closure
*dsc
,
4884 int writeback
, unsigned int rn
)
4888 /* Coprocessor load/store instructions:
4890 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
4892 {stc/stc2} [r0, #+/-imm].
4894 ldc/ldc2 are handled identically. */
4896 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4897 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4898 /* PC should be 4-byte aligned. */
4899 rn_val
= rn_val
& 0xfffffffc;
4900 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4902 dsc
->u
.ldst
.writeback
= writeback
;
4903 dsc
->u
.ldst
.rn
= rn
;
4905 dsc
->cleanup
= &cleanup_copro_load_store
;
4909 arm_copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
4910 struct regcache
*regs
,
4911 struct displaced_step_closure
*dsc
)
4913 unsigned int rn
= bits (insn
, 16, 19);
4915 if (!insn_references_pc (insn
, 0x000f0000ul
))
4916 return arm_copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
4918 if (debug_displaced
)
4919 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4920 "load/store insn %.8lx\n", (unsigned long) insn
);
4922 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4924 install_copro_load_store (gdbarch
, regs
, dsc
, bit (insn
, 25), rn
);
4930 thumb2_copy_copro_load_store (struct gdbarch
*gdbarch
, uint16_t insn1
,
4931 uint16_t insn2
, struct regcache
*regs
,
4932 struct displaced_step_closure
*dsc
)
4934 unsigned int rn
= bits (insn1
, 0, 3);
4936 if (rn
!= ARM_PC_REGNUM
)
4937 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
4938 "copro load/store", dsc
);
4940 if (debug_displaced
)
4941 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4942 "load/store insn %.4x%.4x\n", insn1
, insn2
);
4944 dsc
->modinsn
[0] = insn1
& 0xfff0;
4945 dsc
->modinsn
[1] = insn2
;
4948 /* This function is called for copying instruction LDC/LDC2/VLDR, which
4949 doesn't support writeback, so pass 0. */
4950 install_copro_load_store (gdbarch
, regs
, dsc
, 0, rn
);
4955 /* Clean up branch instructions (actually perform the branch, by setting
4959 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4960 struct displaced_step_closure
*dsc
)
4962 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
4963 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
4964 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
4965 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
4970 if (dsc
->u
.branch
.link
)
4972 /* The value of LR should be the next insn of current one. In order
4973 not to confuse logic hanlding later insn `bx lr', if current insn mode
4974 is Thumb, the bit 0 of LR value should be set to 1. */
4975 ULONGEST next_insn_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
4978 next_insn_addr
|= 0x1;
4980 displaced_write_reg (regs
, dsc
, ARM_LR_REGNUM
, next_insn_addr
,
4984 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, dsc
->u
.branch
.dest
, write_pc
);
4987 /* Copy B/BL/BLX instructions with immediate destinations. */
4990 install_b_bl_blx (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4991 struct displaced_step_closure
*dsc
,
4992 unsigned int cond
, int exchange
, int link
, long offset
)
4994 /* Implement "BL<cond> <label>" as:
4996 Preparation: cond <- instruction condition
4997 Insn: mov r0, r0 (nop)
4998 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
5000 B<cond> similar, but don't set r14 in cleanup. */
5002 dsc
->u
.branch
.cond
= cond
;
5003 dsc
->u
.branch
.link
= link
;
5004 dsc
->u
.branch
.exchange
= exchange
;
5006 dsc
->u
.branch
.dest
= dsc
->insn_addr
;
5007 if (link
&& exchange
)
5008 /* For BLX, offset is computed from the Align (PC, 4). */
5009 dsc
->u
.branch
.dest
= dsc
->u
.branch
.dest
& 0xfffffffc;
5012 dsc
->u
.branch
.dest
+= 4 + offset
;
5014 dsc
->u
.branch
.dest
+= 8 + offset
;
5016 dsc
->cleanup
= &cleanup_branch
;
5019 arm_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
5020 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5022 unsigned int cond
= bits (insn
, 28, 31);
5023 int exchange
= (cond
== 0xf);
5024 int link
= exchange
|| bit (insn
, 24);
5027 if (debug_displaced
)
5028 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
5029 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
5030 (unsigned long) insn
);
5032 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
5033 then arrange the switch into Thumb mode. */
5034 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
5036 offset
= bits (insn
, 0, 23) << 2;
5038 if (bit (offset
, 25))
5039 offset
= offset
| ~0x3ffffff;
5041 dsc
->modinsn
[0] = ARM_NOP
;
5043 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5048 thumb2_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint16_t insn1
,
5049 uint16_t insn2
, struct regcache
*regs
,
5050 struct displaced_step_closure
*dsc
)
5052 int link
= bit (insn2
, 14);
5053 int exchange
= link
&& !bit (insn2
, 12);
5056 int j1
= bit (insn2
, 13);
5057 int j2
= bit (insn2
, 11);
5058 int s
= sbits (insn1
, 10, 10);
5059 int i1
= !(j1
^ bit (insn1
, 10));
5060 int i2
= !(j2
^ bit (insn1
, 10));
5062 if (!link
&& !exchange
) /* B */
5064 offset
= (bits (insn2
, 0, 10) << 1);
5065 if (bit (insn2
, 12)) /* Encoding T4 */
5067 offset
|= (bits (insn1
, 0, 9) << 12)
5073 else /* Encoding T3 */
5075 offset
|= (bits (insn1
, 0, 5) << 12)
5079 cond
= bits (insn1
, 6, 9);
5084 offset
= (bits (insn1
, 0, 9) << 12);
5085 offset
|= ((i2
<< 22) | (i1
<< 23) | (s
<< 24));
5086 offset
|= exchange
?
5087 (bits (insn2
, 1, 10) << 2) : (bits (insn2
, 0, 10) << 1);
5090 if (debug_displaced
)
5091 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s insn "
5092 "%.4x %.4x with offset %.8lx\n",
5093 link
? (exchange
) ? "blx" : "bl" : "b",
5094 insn1
, insn2
, offset
);
5096 dsc
->modinsn
[0] = THUMB_NOP
;
5098 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5102 /* Copy B Thumb instructions. */
5104 thumb_copy_b (struct gdbarch
*gdbarch
, uint16_t insn
,
5105 struct displaced_step_closure
*dsc
)
5107 unsigned int cond
= 0;
5109 unsigned short bit_12_15
= bits (insn
, 12, 15);
5110 CORE_ADDR from
= dsc
->insn_addr
;
5112 if (bit_12_15
== 0xd)
5114 /* offset = SignExtend (imm8:0, 32) */
5115 offset
= sbits ((insn
<< 1), 0, 8);
5116 cond
= bits (insn
, 8, 11);
5118 else if (bit_12_15
== 0xe) /* Encoding T2 */
5120 offset
= sbits ((insn
<< 1), 0, 11);
5124 if (debug_displaced
)
5125 fprintf_unfiltered (gdb_stdlog
,
5126 "displaced: copying b immediate insn %.4x "
5127 "with offset %d\n", insn
, offset
);
5129 dsc
->u
.branch
.cond
= cond
;
5130 dsc
->u
.branch
.link
= 0;
5131 dsc
->u
.branch
.exchange
= 0;
5132 dsc
->u
.branch
.dest
= from
+ 4 + offset
;
5134 dsc
->modinsn
[0] = THUMB_NOP
;
5136 dsc
->cleanup
= &cleanup_branch
;
5141 /* Copy BX/BLX with register-specified destinations. */
5144 install_bx_blx_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5145 struct displaced_step_closure
*dsc
, int link
,
5146 unsigned int cond
, unsigned int rm
)
5148 /* Implement {BX,BLX}<cond> <reg>" as:
5150 Preparation: cond <- instruction condition
5151 Insn: mov r0, r0 (nop)
5152 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
5154 Don't set r14 in cleanup for BX. */
5156 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, dsc
, rm
);
5158 dsc
->u
.branch
.cond
= cond
;
5159 dsc
->u
.branch
.link
= link
;
5161 dsc
->u
.branch
.exchange
= 1;
5163 dsc
->cleanup
= &cleanup_branch
;
5167 arm_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5168 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5170 unsigned int cond
= bits (insn
, 28, 31);
5173 int link
= bit (insn
, 5);
5174 unsigned int rm
= bits (insn
, 0, 3);
5176 if (debug_displaced
)
5177 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx",
5178 (unsigned long) insn
);
5180 dsc
->modinsn
[0] = ARM_NOP
;
5182 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, cond
, rm
);
5187 thumb_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5188 struct regcache
*regs
,
5189 struct displaced_step_closure
*dsc
)
5191 int link
= bit (insn
, 7);
5192 unsigned int rm
= bits (insn
, 3, 6);
5194 if (debug_displaced
)
5195 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x",
5196 (unsigned short) insn
);
5198 dsc
->modinsn
[0] = THUMB_NOP
;
5200 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, INST_AL
, rm
);
5206 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
5209 cleanup_alu_imm (struct gdbarch
*gdbarch
,
5210 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5212 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5213 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5214 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5215 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5219 arm_copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5220 struct displaced_step_closure
*dsc
)
5222 unsigned int rn
= bits (insn
, 16, 19);
5223 unsigned int rd
= bits (insn
, 12, 15);
5224 unsigned int op
= bits (insn
, 21, 24);
5225 int is_mov
= (op
== 0xd);
5226 ULONGEST rd_val
, rn_val
;
5228 if (!insn_references_pc (insn
, 0x000ff000ul
))
5229 return arm_copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
5231 if (debug_displaced
)
5232 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
5233 "%.8lx\n", is_mov
? "move" : "ALU",
5234 (unsigned long) insn
);
5236 /* Instruction is of form:
5238 <op><cond> rd, [rn,] #imm
5242 Preparation: tmp1, tmp2 <- r0, r1;
5244 Insn: <op><cond> r0, r1, #imm
5245 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5248 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5249 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5250 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5251 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5252 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5253 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5257 dsc
->modinsn
[0] = insn
& 0xfff00fff;
5259 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
5261 dsc
->cleanup
= &cleanup_alu_imm
;
5267 thumb2_copy_alu_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5268 uint16_t insn2
, struct regcache
*regs
,
5269 struct displaced_step_closure
*dsc
)
5271 unsigned int op
= bits (insn1
, 5, 8);
5272 unsigned int rn
, rm
, rd
;
5273 ULONGEST rd_val
, rn_val
;
5275 rn
= bits (insn1
, 0, 3); /* Rn */
5276 rm
= bits (insn2
, 0, 3); /* Rm */
5277 rd
= bits (insn2
, 8, 11); /* Rd */
5279 /* This routine is only called for instruction MOV. */
5280 gdb_assert (op
== 0x2 && rn
== 0xf);
5282 if (rm
!= ARM_PC_REGNUM
&& rd
!= ARM_PC_REGNUM
)
5283 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ALU imm", dsc
);
5285 if (debug_displaced
)
5286 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x%.4x\n",
5287 "ALU", insn1
, insn2
);
5289 /* Instruction is of form:
5291 <op><cond> rd, [rn,] #imm
5295 Preparation: tmp1, tmp2 <- r0, r1;
5297 Insn: <op><cond> r0, r1, #imm
5298 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5301 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5302 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5303 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5304 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5305 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5306 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5309 dsc
->modinsn
[0] = insn1
;
5310 dsc
->modinsn
[1] = ((insn2
& 0xf0f0) | 0x1);
5313 dsc
->cleanup
= &cleanup_alu_imm
;
5318 /* Copy/cleanup arithmetic/logic insns with register RHS. */
5321 cleanup_alu_reg (struct gdbarch
*gdbarch
,
5322 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5327 rd_val
= displaced_read_reg (regs
, dsc
, 0);
5329 for (i
= 0; i
< 3; i
++)
5330 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5332 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5336 install_alu_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5337 struct displaced_step_closure
*dsc
,
5338 unsigned int rd
, unsigned int rn
, unsigned int rm
)
5340 ULONGEST rd_val
, rn_val
, rm_val
;
5342 /* Instruction is of form:
5344 <op><cond> rd, [rn,] rm [, <shift>]
5348 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
5349 r0, r1, r2 <- rd, rn, rm
5350 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
5351 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
5354 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5355 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5356 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5357 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5358 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5359 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5360 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5361 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5362 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5365 dsc
->cleanup
= &cleanup_alu_reg
;
5369 arm_copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5370 struct displaced_step_closure
*dsc
)
5372 unsigned int op
= bits (insn
, 21, 24);
5373 int is_mov
= (op
== 0xd);
5375 if (!insn_references_pc (insn
, 0x000ff00ful
))
5376 return arm_copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
5378 if (debug_displaced
)
5379 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
5380 is_mov
? "move" : "ALU", (unsigned long) insn
);
5383 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
5385 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
5387 install_alu_reg (gdbarch
, regs
, dsc
, bits (insn
, 12, 15), bits (insn
, 16, 19),
5393 thumb_copy_alu_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5394 struct regcache
*regs
,
5395 struct displaced_step_closure
*dsc
)
5399 rm
= bits (insn
, 3, 6);
5400 rd
= (bit (insn
, 7) << 3) | bits (insn
, 0, 2);
5402 if (rd
!= ARM_PC_REGNUM
&& rm
!= ARM_PC_REGNUM
)
5403 return thumb_copy_unmodified_16bit (gdbarch
, insn
, "ALU reg", dsc
);
5405 if (debug_displaced
)
5406 fprintf_unfiltered (gdb_stdlog
, "displaced: copying ALU reg insn %.4x\n",
5407 (unsigned short) insn
);
5409 dsc
->modinsn
[0] = ((insn
& 0xff00) | 0x10);
5411 install_alu_reg (gdbarch
, regs
, dsc
, rd
, rd
, rm
);
5416 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
5419 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
5420 struct regcache
*regs
,
5421 struct displaced_step_closure
*dsc
)
5423 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5426 for (i
= 0; i
< 4; i
++)
5427 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5429 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5433 install_alu_shifted_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5434 struct displaced_step_closure
*dsc
,
5435 unsigned int rd
, unsigned int rn
, unsigned int rm
,
5439 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
5441 /* Instruction is of form:
5443 <op><cond> rd, [rn,] rm, <shift> rs
5447 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
5448 r0, r1, r2, r3 <- rd, rn, rm, rs
5449 Insn: <op><cond> r0, r1, r2, <shift> r3
5451 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
5455 for (i
= 0; i
< 4; i
++)
5456 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
5458 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5459 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5460 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5461 rs_val
= displaced_read_reg (regs
, dsc
, rs
);
5462 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5463 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5464 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5465 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
5467 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
5471 arm_copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5472 struct regcache
*regs
,
5473 struct displaced_step_closure
*dsc
)
5475 unsigned int op
= bits (insn
, 21, 24);
5476 int is_mov
= (op
== 0xd);
5477 unsigned int rd
, rn
, rm
, rs
;
5479 if (!insn_references_pc (insn
, 0x000fff0ful
))
5480 return arm_copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
5482 if (debug_displaced
)
5483 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
5484 "%.8lx\n", is_mov
? "move" : "ALU",
5485 (unsigned long) insn
);
5487 rn
= bits (insn
, 16, 19);
5488 rm
= bits (insn
, 0, 3);
5489 rs
= bits (insn
, 8, 11);
5490 rd
= bits (insn
, 12, 15);
5493 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
5495 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
5497 install_alu_shifted_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
, rs
);
5502 /* Clean up load instructions. */
5505 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5506 struct displaced_step_closure
*dsc
)
5508 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
5510 rt_val
= displaced_read_reg (regs
, dsc
, 0);
5511 if (dsc
->u
.ldst
.xfersize
== 8)
5512 rt_val2
= displaced_read_reg (regs
, dsc
, 1);
5513 rn_val
= displaced_read_reg (regs
, dsc
, 2);
5515 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5516 if (dsc
->u
.ldst
.xfersize
> 4)
5517 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5518 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5519 if (!dsc
->u
.ldst
.immed
)
5520 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5522 /* Handle register writeback. */
5523 if (dsc
->u
.ldst
.writeback
)
5524 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5525 /* Put result in right place. */
5526 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
5527 if (dsc
->u
.ldst
.xfersize
== 8)
5528 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
5531 /* Clean up store instructions. */
5534 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5535 struct displaced_step_closure
*dsc
)
5537 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 2);
5539 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5540 if (dsc
->u
.ldst
.xfersize
> 4)
5541 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5542 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5543 if (!dsc
->u
.ldst
.immed
)
5544 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5545 if (!dsc
->u
.ldst
.restore_r4
)
5546 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
5549 if (dsc
->u
.ldst
.writeback
)
5550 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5553 /* Copy "extra" load/store instructions. These are halfword/doubleword
5554 transfers, which have a different encoding to byte/word transfers. */
5557 arm_copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unprivileged
,
5558 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5560 unsigned int op1
= bits (insn
, 20, 24);
5561 unsigned int op2
= bits (insn
, 5, 6);
5562 unsigned int rt
= bits (insn
, 12, 15);
5563 unsigned int rn
= bits (insn
, 16, 19);
5564 unsigned int rm
= bits (insn
, 0, 3);
5565 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
5566 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
5567 int immed
= (op1
& 0x4) != 0;
5569 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
5571 if (!insn_references_pc (insn
, 0x000ff00ful
))
5572 return arm_copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
5574 if (debug_displaced
)
5575 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
5576 "insn %.8lx\n", unprivileged
? "unprivileged " : "",
5577 (unsigned long) insn
);
5579 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
5582 internal_error (__FILE__
, __LINE__
,
5583 _("copy_extra_ld_st: instruction decode error"));
5585 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5586 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5587 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5589 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5591 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5592 if (bytesize
[opcode
] == 8)
5593 rt_val2
= displaced_read_reg (regs
, dsc
, rt
+ 1);
5594 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5596 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5598 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5599 if (bytesize
[opcode
] == 8)
5600 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
5601 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5603 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5606 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
5607 dsc
->u
.ldst
.rn
= rn
;
5608 dsc
->u
.ldst
.immed
= immed
;
5609 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
5610 dsc
->u
.ldst
.restore_r4
= 0;
5613 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
5615 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
5616 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5618 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
5620 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
5621 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5623 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
5628 /* Copy byte/half word/word loads and stores. */
5631 install_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5632 struct displaced_step_closure
*dsc
, int load
,
5633 int immed
, int writeback
, int size
, int usermode
,
5634 int rt
, int rm
, int rn
)
5636 ULONGEST rt_val
, rn_val
, rm_val
= 0;
5638 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5639 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5641 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5643 dsc
->tmp
[4] = displaced_read_reg (regs
, dsc
, 4);
5645 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5646 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5648 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5650 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5651 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5653 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5655 dsc
->u
.ldst
.xfersize
= size
;
5656 dsc
->u
.ldst
.rn
= rn
;
5657 dsc
->u
.ldst
.immed
= immed
;
5658 dsc
->u
.ldst
.writeback
= writeback
;
5660 /* To write PC we can do:
5662 Before this sequence of instructions:
5663 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
5664 r2 is the Rn value got from dispalced_read_reg.
5666 Insn1: push {pc} Write address of STR instruction + offset on stack
5667 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
5668 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
5669 = addr(Insn1) + offset - addr(Insn3) - 8
5671 Insn4: add r4, r4, #8 r4 = offset - 8
5672 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
5674 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
5676 Otherwise we don't know what value to write for PC, since the offset is
5677 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
5678 of this can be found in Section "Saving from r15" in
5679 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
5681 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5686 thumb2_copy_load_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
5687 uint16_t insn2
, struct regcache
*regs
,
5688 struct displaced_step_closure
*dsc
, int size
)
5690 unsigned int u_bit
= bit (insn1
, 7);
5691 unsigned int rt
= bits (insn2
, 12, 15);
5692 int imm12
= bits (insn2
, 0, 11);
5695 if (debug_displaced
)
5696 fprintf_unfiltered (gdb_stdlog
,
5697 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
5698 (unsigned int) dsc
->insn_addr
, rt
, u_bit
? '+' : '-',
5704 /* Rewrite instruction LDR Rt imm12 into:
5706 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
5710 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
5713 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5714 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5715 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5717 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
5719 pc_val
= pc_val
& 0xfffffffc;
5721 displaced_write_reg (regs
, dsc
, 2, pc_val
, CANNOT_WRITE_PC
);
5722 displaced_write_reg (regs
, dsc
, 3, imm12
, CANNOT_WRITE_PC
);
5726 dsc
->u
.ldst
.xfersize
= size
;
5727 dsc
->u
.ldst
.immed
= 0;
5728 dsc
->u
.ldst
.writeback
= 0;
5729 dsc
->u
.ldst
.restore_r4
= 0;
5731 /* LDR R0, R2, R3 */
5732 dsc
->modinsn
[0] = 0xf852;
5733 dsc
->modinsn
[1] = 0x3;
5736 dsc
->cleanup
= &cleanup_load
;
5742 thumb2_copy_load_reg_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5743 uint16_t insn2
, struct regcache
*regs
,
5744 struct displaced_step_closure
*dsc
,
5745 int writeback
, int immed
)
5747 unsigned int rt
= bits (insn2
, 12, 15);
5748 unsigned int rn
= bits (insn1
, 0, 3);
5749 unsigned int rm
= bits (insn2
, 0, 3); /* Only valid if !immed. */
5750 /* In LDR (register), there is also a register Rm, which is not allowed to
5751 be PC, so we don't have to check it. */
5753 if (rt
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
5754 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "load",
5757 if (debug_displaced
)
5758 fprintf_unfiltered (gdb_stdlog
,
5759 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
5760 rt
, rn
, insn1
, insn2
);
5762 install_load_store (gdbarch
, regs
, dsc
, 1, immed
, writeback
, 4,
5765 dsc
->u
.ldst
.restore_r4
= 0;
5768 /* ldr[b]<cond> rt, [rn, #imm], etc.
5770 ldr[b]<cond> r0, [r2, #imm]. */
5772 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5773 dsc
->modinsn
[1] = insn2
& 0x0fff;
5776 /* ldr[b]<cond> rt, [rn, rm], etc.
5778 ldr[b]<cond> r0, [r2, r3]. */
5780 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5781 dsc
->modinsn
[1] = (insn2
& 0x0ff0) | 0x3;
5791 arm_copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
5792 struct regcache
*regs
,
5793 struct displaced_step_closure
*dsc
,
5794 int load
, int size
, int usermode
)
5796 int immed
= !bit (insn
, 25);
5797 int writeback
= (bit (insn
, 24) == 0 || bit (insn
, 21) != 0);
5798 unsigned int rt
= bits (insn
, 12, 15);
5799 unsigned int rn
= bits (insn
, 16, 19);
5800 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
5802 if (!insn_references_pc (insn
, 0x000ff00ful
))
5803 return arm_copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
5805 if (debug_displaced
)
5806 fprintf_unfiltered (gdb_stdlog
,
5807 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
5808 load
? (size
== 1 ? "ldrb" : "ldr")
5809 : (size
== 1 ? "strb" : "str"), usermode
? "t" : "",
5811 (unsigned long) insn
);
5813 install_load_store (gdbarch
, regs
, dsc
, load
, immed
, writeback
, size
,
5814 usermode
, rt
, rm
, rn
);
5816 if (load
|| rt
!= ARM_PC_REGNUM
)
5818 dsc
->u
.ldst
.restore_r4
= 0;
5821 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
5823 {ldr,str}[b]<cond> r0, [r2, #imm]. */
5824 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5826 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
5828 {ldr,str}[b]<cond> r0, [r2, r3]. */
5829 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5833 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
5834 dsc
->u
.ldst
.restore_r4
= 1;
5835 dsc
->modinsn
[0] = 0xe92d8000; /* push {pc} */
5836 dsc
->modinsn
[1] = 0xe8bd0010; /* pop {r4} */
5837 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
5838 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
5839 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
5843 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
5845 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
5850 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5855 /* Cleanup LDM instructions with fully-populated register list. This is an
5856 unfortunate corner case: it's impossible to implement correctly by modifying
5857 the instruction. The issue is as follows: we have an instruction,
5861 which we must rewrite to avoid loading PC. A possible solution would be to
5862 do the load in two halves, something like (with suitable cleanup
5866 ldm[id][ab] r8!, {r0-r7}
5868 ldm[id][ab] r8, {r7-r14}
5871 but at present there's no suitable place for <temp>, since the scratch space
5872 is overwritten before the cleanup routine is called. For now, we simply
5873 emulate the instruction. */
5876 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5877 struct displaced_step_closure
*dsc
)
5879 int inc
= dsc
->u
.block
.increment
;
5880 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
5881 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
5882 uint32_t regmask
= dsc
->u
.block
.regmask
;
5883 int regno
= inc
? 0 : 15;
5884 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
5885 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
5886 && (regmask
& 0x8000) != 0;
5887 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5888 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
5889 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5894 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
5895 sensible we can do here. Complain loudly. */
5896 if (exception_return
)
5897 error (_("Cannot single-step exception return"));
5899 /* We don't handle any stores here for now. */
5900 gdb_assert (dsc
->u
.block
.load
!= 0);
5902 if (debug_displaced
)
5903 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
5904 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
5905 dsc
->u
.block
.increment
? "inc" : "dec",
5906 dsc
->u
.block
.before
? "before" : "after");
5913 while (regno
<= ARM_PC_REGNUM
&& (regmask
& (1 << regno
)) == 0)
5916 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
5919 xfer_addr
+= bump_before
;
5921 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
5922 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
5924 xfer_addr
+= bump_after
;
5926 regmask
&= ~(1 << regno
);
5929 if (dsc
->u
.block
.writeback
)
5930 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
5934 /* Clean up an STM which included the PC in the register list. */
5937 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5938 struct displaced_step_closure
*dsc
)
5940 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5941 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
5942 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
5943 CORE_ADDR stm_insn_addr
;
5946 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5948 /* If condition code fails, there's nothing else to do. */
5949 if (!store_executed
)
5952 if (dsc
->u
.block
.increment
)
5954 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
5956 if (dsc
->u
.block
.before
)
5961 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
5963 if (dsc
->u
.block
.before
)
5967 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
5968 stm_insn_addr
= dsc
->scratch_base
;
5969 offset
= pc_val
- stm_insn_addr
;
5971 if (debug_displaced
)
5972 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
5973 "STM instruction\n", offset
);
5975 /* Rewrite the stored PC to the proper value for the non-displaced original
5977 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
5978 dsc
->insn_addr
+ offset
);
5981 /* Clean up an LDM which includes the PC in the register list. We clumped all
5982 the registers in the transferred list into a contiguous range r0...rX (to
5983 avoid loading PC directly and losing control of the debugged program), so we
5984 must undo that here. */
5987 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
5988 struct regcache
*regs
,
5989 struct displaced_step_closure
*dsc
)
5991 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5992 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
);
5993 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= ARM_PC_REGNUM
;
5994 unsigned int regs_loaded
= bitcount (mask
);
5995 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
5997 /* The method employed here will fail if the register list is fully populated
5998 (we need to avoid loading PC directly). */
5999 gdb_assert (num_to_shuffle
< 16);
6004 clobbered
= (1 << num_to_shuffle
) - 1;
6006 while (num_to_shuffle
> 0)
6008 if ((mask
& (1 << write_reg
)) != 0)
6010 unsigned int read_reg
= num_to_shuffle
- 1;
6012 if (read_reg
!= write_reg
)
6014 ULONGEST rval
= displaced_read_reg (regs
, dsc
, read_reg
);
6015 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
6016 if (debug_displaced
)
6017 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
6018 "loaded register r%d to r%d\n"), read_reg
,
6021 else if (debug_displaced
)
6022 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
6023 "r%d already in the right place\n"),
6026 clobbered
&= ~(1 << write_reg
);
6034 /* Restore any registers we scribbled over. */
6035 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
6037 if ((clobbered
& (1 << write_reg
)) != 0)
6039 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
6041 if (debug_displaced
)
6042 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
6043 "clobbered register r%d\n"), write_reg
);
6044 clobbered
&= ~(1 << write_reg
);
6048 /* Perform register writeback manually. */
6049 if (dsc
->u
.block
.writeback
)
6051 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
6053 if (dsc
->u
.block
.increment
)
6054 new_rn_val
+= regs_loaded
* 4;
6056 new_rn_val
-= regs_loaded
* 4;
6058 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
6063 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
6064 in user-level code (in particular exception return, ldm rn, {...pc}^). */
6067 arm_copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
,
6068 struct regcache
*regs
,
6069 struct displaced_step_closure
*dsc
)
6071 int load
= bit (insn
, 20);
6072 int user
= bit (insn
, 22);
6073 int increment
= bit (insn
, 23);
6074 int before
= bit (insn
, 24);
6075 int writeback
= bit (insn
, 21);
6076 int rn
= bits (insn
, 16, 19);
6078 /* Block transfers which don't mention PC can be run directly
6080 if (rn
!= ARM_PC_REGNUM
&& (insn
& 0x8000) == 0)
6081 return arm_copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
6083 if (rn
== ARM_PC_REGNUM
)
6085 warning (_("displaced: Unpredictable LDM or STM with "
6086 "base register r15"));
6087 return arm_copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
6090 if (debug_displaced
)
6091 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6092 "%.8lx\n", (unsigned long) insn
);
6094 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6095 dsc
->u
.block
.rn
= rn
;
6097 dsc
->u
.block
.load
= load
;
6098 dsc
->u
.block
.user
= user
;
6099 dsc
->u
.block
.increment
= increment
;
6100 dsc
->u
.block
.before
= before
;
6101 dsc
->u
.block
.writeback
= writeback
;
6102 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
6104 dsc
->u
.block
.regmask
= insn
& 0xffff;
6108 if ((insn
& 0xffff) == 0xffff)
6110 /* LDM with a fully-populated register list. This case is
6111 particularly tricky. Implement for now by fully emulating the
6112 instruction (which might not behave perfectly in all cases, but
6113 these instructions should be rare enough for that not to matter
6115 dsc
->modinsn
[0] = ARM_NOP
;
6117 dsc
->cleanup
= &cleanup_block_load_all
;
6121 /* LDM of a list of registers which includes PC. Implement by
6122 rewriting the list of registers to be transferred into a
6123 contiguous chunk r0...rX before doing the transfer, then shuffling
6124 registers into the correct places in the cleanup routine. */
6125 unsigned int regmask
= insn
& 0xffff;
6126 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
6129 for (i
= 0; i
< num_in_list
; i
++)
6130 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6132 /* Writeback makes things complicated. We need to avoid clobbering
6133 the base register with one of the registers in our modified
6134 register list, but just using a different register can't work in
6137 ldm r14!, {r0-r13,pc}
6139 which would need to be rewritten as:
6143 but that can't work, because there's no free register for N.
6145 Solve this by turning off the writeback bit, and emulating
6146 writeback manually in the cleanup routine. */
6151 new_regmask
= (1 << num_in_list
) - 1;
6153 if (debug_displaced
)
6154 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6155 "{..., pc}: original reg list %.4x, modified "
6156 "list %.4x\n"), rn
, writeback
? "!" : "",
6157 (int) insn
& 0xffff, new_regmask
);
6159 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
6161 dsc
->cleanup
= &cleanup_block_load_pc
;
6166 /* STM of a list of registers which includes PC. Run the instruction
6167 as-is, but out of line: this will store the wrong value for the PC,
6168 so we must manually fix up the memory in the cleanup routine.
6169 Doing things this way has the advantage that we can auto-detect
6170 the offset of the PC write (which is architecture-dependent) in
6171 the cleanup routine. */
6172 dsc
->modinsn
[0] = insn
;
6174 dsc
->cleanup
= &cleanup_block_store_pc
;
6181 thumb2_copy_block_xfer (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6182 struct regcache
*regs
,
6183 struct displaced_step_closure
*dsc
)
6185 int rn
= bits (insn1
, 0, 3);
6186 int load
= bit (insn1
, 4);
6187 int writeback
= bit (insn1
, 5);
6189 /* Block transfers which don't mention PC can be run directly
6191 if (rn
!= ARM_PC_REGNUM
&& (insn2
& 0x8000) == 0)
6192 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ldm/stm", dsc
);
6194 if (rn
== ARM_PC_REGNUM
)
6196 warning (_("displaced: Unpredictable LDM or STM with "
6197 "base register r15"));
6198 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6199 "unpredictable ldm/stm", dsc
);
6202 if (debug_displaced
)
6203 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6204 "%.4x%.4x\n", insn1
, insn2
);
6206 /* Clear bit 13, since it should be always zero. */
6207 dsc
->u
.block
.regmask
= (insn2
& 0xdfff);
6208 dsc
->u
.block
.rn
= rn
;
6210 dsc
->u
.block
.load
= load
;
6211 dsc
->u
.block
.user
= 0;
6212 dsc
->u
.block
.increment
= bit (insn1
, 7);
6213 dsc
->u
.block
.before
= bit (insn1
, 8);
6214 dsc
->u
.block
.writeback
= writeback
;
6215 dsc
->u
.block
.cond
= INST_AL
;
6216 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6220 if (dsc
->u
.block
.regmask
== 0xffff)
6222 /* This branch is impossible to happen. */
6227 unsigned int regmask
= dsc
->u
.block
.regmask
;
6228 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
6231 for (i
= 0; i
< num_in_list
; i
++)
6232 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6237 new_regmask
= (1 << num_in_list
) - 1;
6239 if (debug_displaced
)
6240 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6241 "{..., pc}: original reg list %.4x, modified "
6242 "list %.4x\n"), rn
, writeback
? "!" : "",
6243 (int) dsc
->u
.block
.regmask
, new_regmask
);
6245 dsc
->modinsn
[0] = insn1
;
6246 dsc
->modinsn
[1] = (new_regmask
& 0xffff);
6249 dsc
->cleanup
= &cleanup_block_load_pc
;
6254 dsc
->modinsn
[0] = insn1
;
6255 dsc
->modinsn
[1] = insn2
;
6257 dsc
->cleanup
= &cleanup_block_store_pc
;
6262 /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs.
6263 This is used to avoid a dependency on BFD's bfd_endian enum. */
6266 arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr
, int len
,
6269 return read_memory_unsigned_integer (memaddr
, len
,
6270 (enum bfd_endian
) byte_order
);
6273 /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */
6276 arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs
*self
,
6279 return gdbarch_addr_bits_remove (get_regcache_arch (self
->regcache
), val
);
6282 /* Wrapper over syscall_next_pc for use in get_next_pcs. */
6285 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
)
6290 /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */
6293 arm_get_next_pcs_is_thumb (struct arm_get_next_pcs
*self
)
6295 return arm_is_thumb (self
->regcache
);
6298 /* single_step() is called just before we want to resume the inferior,
6299 if we want to single-step it but there is no hardware or kernel
6300 single-step support. We find the target of the coming instructions
6301 and breakpoint them. */
6304 arm_software_single_step (struct frame_info
*frame
)
6306 struct regcache
*regcache
= get_current_regcache ();
6307 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
6308 struct address_space
*aspace
= get_regcache_aspace (regcache
);
6309 struct arm_get_next_pcs next_pcs_ctx
;
6312 VEC (CORE_ADDR
) *next_pcs
= NULL
;
6313 struct cleanup
*old_chain
= make_cleanup (VEC_cleanup (CORE_ADDR
), &next_pcs
);
6315 arm_get_next_pcs_ctor (&next_pcs_ctx
,
6316 &arm_get_next_pcs_ops
,
6317 gdbarch_byte_order (gdbarch
),
6318 gdbarch_byte_order_for_code (gdbarch
),
6322 next_pcs
= arm_get_next_pcs (&next_pcs_ctx
);
6324 for (i
= 0; VEC_iterate (CORE_ADDR
, next_pcs
, i
, pc
); i
++)
6325 arm_insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
6327 do_cleanups (old_chain
);
6332 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
6333 for Linux, where some SVC instructions must be treated specially. */
6336 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6337 struct displaced_step_closure
*dsc
)
6339 CORE_ADDR resume_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
6341 if (debug_displaced
)
6342 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
6343 "%.8lx\n", (unsigned long) resume_addr
);
6345 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
6349 /* Common copy routine for svc instruciton. */
6352 install_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6353 struct displaced_step_closure
*dsc
)
6355 /* Preparation: none.
6356 Insn: unmodified svc.
6357 Cleanup: pc <- insn_addr + insn_size. */
6359 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
6361 dsc
->wrote_to_pc
= 1;
6363 /* Allow OS-specific code to override SVC handling. */
6364 if (dsc
->u
.svc
.copy_svc_os
)
6365 return dsc
->u
.svc
.copy_svc_os (gdbarch
, regs
, dsc
);
6368 dsc
->cleanup
= &cleanup_svc
;
6374 arm_copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
,
6375 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6378 if (debug_displaced
)
6379 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
6380 (unsigned long) insn
);
6382 dsc
->modinsn
[0] = insn
;
6384 return install_svc (gdbarch
, regs
, dsc
);
6388 thumb_copy_svc (struct gdbarch
*gdbarch
, uint16_t insn
,
6389 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6392 if (debug_displaced
)
6393 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.4x\n",
6396 dsc
->modinsn
[0] = insn
;
6398 return install_svc (gdbarch
, regs
, dsc
);
6401 /* Copy undefined instructions. */
6404 arm_copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
6405 struct displaced_step_closure
*dsc
)
6407 if (debug_displaced
)
6408 fprintf_unfiltered (gdb_stdlog
,
6409 "displaced: copying undefined insn %.8lx\n",
6410 (unsigned long) insn
);
6412 dsc
->modinsn
[0] = insn
;
6418 thumb_32bit_copy_undef (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6419 struct displaced_step_closure
*dsc
)
6422 if (debug_displaced
)
6423 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn "
6424 "%.4x %.4x\n", (unsigned short) insn1
,
6425 (unsigned short) insn2
);
6427 dsc
->modinsn
[0] = insn1
;
6428 dsc
->modinsn
[1] = insn2
;
6434 /* Copy unpredictable instructions. */
6437 arm_copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
6438 struct displaced_step_closure
*dsc
)
6440 if (debug_displaced
)
6441 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
6442 "%.8lx\n", (unsigned long) insn
);
6444 dsc
->modinsn
[0] = insn
;
6449 /* The decode_* functions are instruction decoding helpers. They mostly follow
6450 the presentation in the ARM ARM. */
6453 arm_decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
6454 struct regcache
*regs
,
6455 struct displaced_step_closure
*dsc
)
6457 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
6458 unsigned int rn
= bits (insn
, 16, 19);
6460 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
6461 return arm_copy_unmodified (gdbarch
, insn
, "cps", dsc
);
6462 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
6463 return arm_copy_unmodified (gdbarch
, insn
, "setend", dsc
);
6464 else if ((op1
& 0x60) == 0x20)
6465 return arm_copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
6466 else if ((op1
& 0x71) == 0x40)
6467 return arm_copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store",
6469 else if ((op1
& 0x77) == 0x41)
6470 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6471 else if ((op1
& 0x77) == 0x45)
6472 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
6473 else if ((op1
& 0x77) == 0x51)
6476 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6478 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6480 else if ((op1
& 0x77) == 0x55)
6481 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6482 else if (op1
== 0x57)
6485 case 0x1: return arm_copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
6486 case 0x4: return arm_copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
6487 case 0x5: return arm_copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
6488 case 0x6: return arm_copy_unmodified (gdbarch
, insn
, "isb", dsc
);
6489 default: return arm_copy_unpred (gdbarch
, insn
, dsc
);
6491 else if ((op1
& 0x63) == 0x43)
6492 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6493 else if ((op2
& 0x1) == 0x0)
6494 switch (op1
& ~0x80)
6497 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6499 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
6500 case 0x71: case 0x75:
6502 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
6503 case 0x63: case 0x67: case 0x73: case 0x77:
6504 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6506 return arm_copy_undef (gdbarch
, insn
, dsc
);
6509 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
6513 arm_decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
6514 struct regcache
*regs
,
6515 struct displaced_step_closure
*dsc
)
6517 if (bit (insn
, 27) == 0)
6518 return arm_decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
6519 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
6520 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
6523 return arm_copy_unmodified (gdbarch
, insn
, "srs", dsc
);
6526 return arm_copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
6528 case 0x4: case 0x5: case 0x6: case 0x7:
6529 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6532 switch ((insn
& 0xe00000) >> 21)
6534 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
6536 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6539 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6542 return arm_copy_undef (gdbarch
, insn
, dsc
);
6547 int rn_f
= (bits (insn
, 16, 19) == 0xf);
6548 switch ((insn
& 0xe00000) >> 21)
6551 /* ldc/ldc2 imm (undefined for rn == pc). */
6552 return rn_f
? arm_copy_undef (gdbarch
, insn
, dsc
)
6553 : arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6556 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6558 case 0x4: case 0x5: case 0x6: case 0x7:
6559 /* ldc/ldc2 lit (undefined for rn != pc). */
6560 return rn_f
? arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
6561 : arm_copy_undef (gdbarch
, insn
, dsc
);
6564 return arm_copy_undef (gdbarch
, insn
, dsc
);
6569 return arm_copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
6572 if (bits (insn
, 16, 19) == 0xf)
6574 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6576 return arm_copy_undef (gdbarch
, insn
, dsc
);
6580 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6582 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6586 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6588 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6591 return arm_copy_undef (gdbarch
, insn
, dsc
);
6595 /* Decode miscellaneous instructions in dp/misc encoding space. */
6598 arm_decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
6599 struct regcache
*regs
,
6600 struct displaced_step_closure
*dsc
)
6602 unsigned int op2
= bits (insn
, 4, 6);
6603 unsigned int op
= bits (insn
, 21, 22);
6608 return arm_copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
6611 if (op
== 0x1) /* bx. */
6612 return arm_copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
6614 return arm_copy_unmodified (gdbarch
, insn
, "clz", dsc
);
6616 return arm_copy_undef (gdbarch
, insn
, dsc
);
6620 /* Not really supported. */
6621 return arm_copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
6623 return arm_copy_undef (gdbarch
, insn
, dsc
);
6627 return arm_copy_bx_blx_reg (gdbarch
, insn
,
6628 regs
, dsc
); /* blx register. */
6630 return arm_copy_undef (gdbarch
, insn
, dsc
);
6633 return arm_copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
6637 return arm_copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
6639 /* Not really supported. */
6640 return arm_copy_unmodified (gdbarch
, insn
, "smc", dsc
);
6643 return arm_copy_undef (gdbarch
, insn
, dsc
);
6648 arm_decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
,
6649 struct regcache
*regs
,
6650 struct displaced_step_closure
*dsc
)
6653 switch (bits (insn
, 20, 24))
6656 return arm_copy_unmodified (gdbarch
, insn
, "movw", dsc
);
6659 return arm_copy_unmodified (gdbarch
, insn
, "movt", dsc
);
6661 case 0x12: case 0x16:
6662 return arm_copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
6665 return arm_copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
6669 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
6671 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
6672 return arm_copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
6673 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
6674 return arm_copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
6675 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
6676 return arm_decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
6677 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
6678 return arm_copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
6679 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
6680 return arm_copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
6681 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
6682 return arm_copy_unmodified (gdbarch
, insn
, "synch", dsc
);
6683 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
6684 /* 2nd arg means "unprivileged". */
6685 return arm_copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
6689 /* Should be unreachable. */
6694 arm_decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
6695 struct regcache
*regs
,
6696 struct displaced_step_closure
*dsc
)
6698 int a
= bit (insn
, 25), b
= bit (insn
, 4);
6699 uint32_t op1
= bits (insn
, 20, 24);
6701 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
6702 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
6703 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 0);
6704 else if ((!a
&& (op1
& 0x17) == 0x02)
6705 || (a
&& (op1
& 0x17) == 0x02 && !b
))
6706 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 1);
6707 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
6708 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
6709 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 0);
6710 else if ((!a
&& (op1
& 0x17) == 0x03)
6711 || (a
&& (op1
& 0x17) == 0x03 && !b
))
6712 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 1);
6713 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
6714 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
6715 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
6716 else if ((!a
&& (op1
& 0x17) == 0x06)
6717 || (a
&& (op1
& 0x17) == 0x06 && !b
))
6718 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
6719 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
6720 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
6721 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
6722 else if ((!a
&& (op1
& 0x17) == 0x07)
6723 || (a
&& (op1
& 0x17) == 0x07 && !b
))
6724 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
6726 /* Should be unreachable. */
6731 arm_decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
6732 struct displaced_step_closure
*dsc
)
6734 switch (bits (insn
, 20, 24))
6736 case 0x00: case 0x01: case 0x02: case 0x03:
6737 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
6739 case 0x04: case 0x05: case 0x06: case 0x07:
6740 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
6742 case 0x08: case 0x09: case 0x0a: case 0x0b:
6743 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
6744 return arm_copy_unmodified (gdbarch
, insn
,
6745 "decode/pack/unpack/saturate/reverse", dsc
);
6748 if (bits (insn
, 5, 7) == 0) /* op2. */
6750 if (bits (insn
, 12, 15) == 0xf)
6751 return arm_copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
6753 return arm_copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
6756 return arm_copy_undef (gdbarch
, insn
, dsc
);
6758 case 0x1a: case 0x1b:
6759 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6760 return arm_copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
6762 return arm_copy_undef (gdbarch
, insn
, dsc
);
6764 case 0x1c: case 0x1d:
6765 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
6767 if (bits (insn
, 0, 3) == 0xf)
6768 return arm_copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
6770 return arm_copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
6773 return arm_copy_undef (gdbarch
, insn
, dsc
);
6775 case 0x1e: case 0x1f:
6776 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6777 return arm_copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
6779 return arm_copy_undef (gdbarch
, insn
, dsc
);
6782 /* Should be unreachable. */
6787 arm_decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, uint32_t insn
,
6788 struct regcache
*regs
,
6789 struct displaced_step_closure
*dsc
)
6792 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6794 return arm_copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
6798 arm_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
6799 struct regcache
*regs
,
6800 struct displaced_step_closure
*dsc
)
6802 unsigned int opcode
= bits (insn
, 20, 24);
6806 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
6807 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
6809 case 0x08: case 0x0a: case 0x0c: case 0x0e:
6810 case 0x12: case 0x16:
6811 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
6813 case 0x09: case 0x0b: case 0x0d: case 0x0f:
6814 case 0x13: case 0x17:
6815 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
6817 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6818 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6819 /* Note: no writeback for these instructions. Bit 25 will always be
6820 zero though (via caller), so the following works OK. */
6821 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6824 /* Should be unreachable. */
6828 /* Decode shifted register instructions. */
6831 thumb2_decode_dp_shift_reg (struct gdbarch
*gdbarch
, uint16_t insn1
,
6832 uint16_t insn2
, struct regcache
*regs
,
6833 struct displaced_step_closure
*dsc
)
6835 /* PC is only allowed to be used in instruction MOV. */
6837 unsigned int op
= bits (insn1
, 5, 8);
6838 unsigned int rn
= bits (insn1
, 0, 3);
6840 if (op
== 0x2 && rn
== 0xf) /* MOV */
6841 return thumb2_copy_alu_imm (gdbarch
, insn1
, insn2
, regs
, dsc
);
6843 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6844 "dp (shift reg)", dsc
);
6848 /* Decode extension register load/store. Exactly the same as
6849 arm_decode_ext_reg_ld_st. */
6852 thumb2_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint16_t insn1
,
6853 uint16_t insn2
, struct regcache
*regs
,
6854 struct displaced_step_closure
*dsc
)
6856 unsigned int opcode
= bits (insn1
, 4, 8);
6860 case 0x04: case 0x05:
6861 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6862 "vfp/neon vmov", dsc
);
6864 case 0x08: case 0x0c: /* 01x00 */
6865 case 0x0a: case 0x0e: /* 01x10 */
6866 case 0x12: case 0x16: /* 10x10 */
6867 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6868 "vfp/neon vstm/vpush", dsc
);
6870 case 0x09: case 0x0d: /* 01x01 */
6871 case 0x0b: case 0x0f: /* 01x11 */
6872 case 0x13: case 0x17: /* 10x11 */
6873 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6874 "vfp/neon vldm/vpop", dsc
);
6876 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6877 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6879 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6880 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
, regs
, dsc
);
6883 /* Should be unreachable. */
6888 arm_decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
,
6889 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6891 unsigned int op1
= bits (insn
, 20, 25);
6892 int op
= bit (insn
, 4);
6893 unsigned int coproc
= bits (insn
, 8, 11);
6895 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
6896 return arm_decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
6897 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
6898 && (coproc
& 0xe) != 0xa)
6900 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6901 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
6902 && (coproc
& 0xe) != 0xa)
6903 /* ldc/ldc2 imm/lit. */
6904 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6905 else if ((op1
& 0x3e) == 0x00)
6906 return arm_copy_undef (gdbarch
, insn
, dsc
);
6907 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
6908 return arm_copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
6909 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
6910 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6911 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
6912 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6913 else if ((op1
& 0x30) == 0x20 && !op
)
6915 if ((coproc
& 0xe) == 0xa)
6916 return arm_copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
6918 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6920 else if ((op1
& 0x30) == 0x20 && op
)
6921 return arm_copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
6922 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
6923 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6924 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
6925 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6926 else if ((op1
& 0x30) == 0x30)
6927 return arm_copy_svc (gdbarch
, insn
, regs
, dsc
);
6929 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
6933 thumb2_decode_svc_copro (struct gdbarch
*gdbarch
, uint16_t insn1
,
6934 uint16_t insn2
, struct regcache
*regs
,
6935 struct displaced_step_closure
*dsc
)
6937 unsigned int coproc
= bits (insn2
, 8, 11);
6938 unsigned int bit_5_8
= bits (insn1
, 5, 8);
6939 unsigned int bit_9
= bit (insn1
, 9);
6940 unsigned int bit_4
= bit (insn1
, 4);
6945 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6946 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
6948 else if (bit_5_8
== 0) /* UNDEFINED. */
6949 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
6952 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
6953 if ((coproc
& 0xe) == 0xa)
6954 return thumb2_decode_ext_reg_ld_st (gdbarch
, insn1
, insn2
, regs
,
6956 else /* coproc is not 101x. */
6958 if (bit_4
== 0) /* STC/STC2. */
6959 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6961 else /* LDC/LDC2 {literal, immeidate}. */
6962 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
,
6968 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "coproc", dsc
);
6974 install_pc_relative (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6975 struct displaced_step_closure
*dsc
, int rd
)
6981 Preparation: Rd <- PC
6987 int val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
6988 displaced_write_reg (regs
, dsc
, rd
, val
, CANNOT_WRITE_PC
);
6992 thumb_copy_pc_relative_16bit (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6993 struct displaced_step_closure
*dsc
,
6994 int rd
, unsigned int imm
)
6997 /* Encoding T2: ADDS Rd, #imm */
6998 dsc
->modinsn
[0] = (0x3000 | (rd
<< 8) | imm
);
7000 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
7006 thumb_decode_pc_relative_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
7007 struct regcache
*regs
,
7008 struct displaced_step_closure
*dsc
)
7010 unsigned int rd
= bits (insn
, 8, 10);
7011 unsigned int imm8
= bits (insn
, 0, 7);
7013 if (debug_displaced
)
7014 fprintf_unfiltered (gdb_stdlog
,
7015 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
7018 return thumb_copy_pc_relative_16bit (gdbarch
, regs
, dsc
, rd
, imm8
);
7022 thumb_copy_pc_relative_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
7023 uint16_t insn2
, struct regcache
*regs
,
7024 struct displaced_step_closure
*dsc
)
7026 unsigned int rd
= bits (insn2
, 8, 11);
7027 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
7028 extract raw immediate encoding rather than computing immediate. When
7029 generating ADD or SUB instruction, we can simply perform OR operation to
7030 set immediate into ADD. */
7031 unsigned int imm_3_8
= insn2
& 0x70ff;
7032 unsigned int imm_i
= insn1
& 0x0400; /* Clear all bits except bit 10. */
7034 if (debug_displaced
)
7035 fprintf_unfiltered (gdb_stdlog
,
7036 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
7037 rd
, imm_i
, imm_3_8
, insn1
, insn2
);
7039 if (bit (insn1
, 7)) /* Encoding T2 */
7041 /* Encoding T3: SUB Rd, Rd, #imm */
7042 dsc
->modinsn
[0] = (0xf1a0 | rd
| imm_i
);
7043 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7045 else /* Encoding T3 */
7047 /* Encoding T3: ADD Rd, Rd, #imm */
7048 dsc
->modinsn
[0] = (0xf100 | rd
| imm_i
);
7049 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7053 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
7059 thumb_copy_16bit_ldr_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
7060 struct regcache
*regs
,
7061 struct displaced_step_closure
*dsc
)
7063 unsigned int rt
= bits (insn1
, 8, 10);
7065 int imm8
= (bits (insn1
, 0, 7) << 2);
7071 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
7073 Insn: LDR R0, [R2, R3];
7074 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
7076 if (debug_displaced
)
7077 fprintf_unfiltered (gdb_stdlog
,
7078 "displaced: copying thumb ldr r%d [pc #%d]\n"
7081 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
7082 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
7083 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
7084 pc
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
7085 /* The assembler calculates the required value of the offset from the
7086 Align(PC,4) value of this instruction to the label. */
7087 pc
= pc
& 0xfffffffc;
7089 displaced_write_reg (regs
, dsc
, 2, pc
, CANNOT_WRITE_PC
);
7090 displaced_write_reg (regs
, dsc
, 3, imm8
, CANNOT_WRITE_PC
);
7093 dsc
->u
.ldst
.xfersize
= 4;
7095 dsc
->u
.ldst
.immed
= 0;
7096 dsc
->u
.ldst
.writeback
= 0;
7097 dsc
->u
.ldst
.restore_r4
= 0;
7099 dsc
->modinsn
[0] = 0x58d0; /* ldr r0, [r2, r3]*/
7101 dsc
->cleanup
= &cleanup_load
;
7106 /* Copy Thumb cbnz/cbz insruction. */
7109 thumb_copy_cbnz_cbz (struct gdbarch
*gdbarch
, uint16_t insn1
,
7110 struct regcache
*regs
,
7111 struct displaced_step_closure
*dsc
)
7113 int non_zero
= bit (insn1
, 11);
7114 unsigned int imm5
= (bit (insn1
, 9) << 6) | (bits (insn1
, 3, 7) << 1);
7115 CORE_ADDR from
= dsc
->insn_addr
;
7116 int rn
= bits (insn1
, 0, 2);
7117 int rn_val
= displaced_read_reg (regs
, dsc
, rn
);
7119 dsc
->u
.branch
.cond
= (rn_val
&& non_zero
) || (!rn_val
&& !non_zero
);
7120 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
7121 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
7122 condition is false, let it be, cleanup_branch will do nothing. */
7123 if (dsc
->u
.branch
.cond
)
7125 dsc
->u
.branch
.cond
= INST_AL
;
7126 dsc
->u
.branch
.dest
= from
+ 4 + imm5
;
7129 dsc
->u
.branch
.dest
= from
+ 2;
7131 dsc
->u
.branch
.link
= 0;
7132 dsc
->u
.branch
.exchange
= 0;
7134 if (debug_displaced
)
7135 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s [r%d = 0x%x]"
7136 " insn %.4x to %.8lx\n", non_zero
? "cbnz" : "cbz",
7137 rn
, rn_val
, insn1
, dsc
->u
.branch
.dest
);
7139 dsc
->modinsn
[0] = THUMB_NOP
;
7141 dsc
->cleanup
= &cleanup_branch
;
7145 /* Copy Table Branch Byte/Halfword */
7147 thumb2_copy_table_branch (struct gdbarch
*gdbarch
, uint16_t insn1
,
7148 uint16_t insn2
, struct regcache
*regs
,
7149 struct displaced_step_closure
*dsc
)
7151 ULONGEST rn_val
, rm_val
;
7152 int is_tbh
= bit (insn2
, 4);
7153 CORE_ADDR halfwords
= 0;
7154 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7156 rn_val
= displaced_read_reg (regs
, dsc
, bits (insn1
, 0, 3));
7157 rm_val
= displaced_read_reg (regs
, dsc
, bits (insn2
, 0, 3));
7163 target_read_memory (rn_val
+ 2 * rm_val
, buf
, 2);
7164 halfwords
= extract_unsigned_integer (buf
, 2, byte_order
);
7170 target_read_memory (rn_val
+ rm_val
, buf
, 1);
7171 halfwords
= extract_unsigned_integer (buf
, 1, byte_order
);
7174 if (debug_displaced
)
7175 fprintf_unfiltered (gdb_stdlog
, "displaced: %s base 0x%x offset 0x%x"
7176 " offset 0x%x\n", is_tbh
? "tbh" : "tbb",
7177 (unsigned int) rn_val
, (unsigned int) rm_val
,
7178 (unsigned int) halfwords
);
7180 dsc
->u
.branch
.cond
= INST_AL
;
7181 dsc
->u
.branch
.link
= 0;
7182 dsc
->u
.branch
.exchange
= 0;
7183 dsc
->u
.branch
.dest
= dsc
->insn_addr
+ 4 + 2 * halfwords
;
7185 dsc
->cleanup
= &cleanup_branch
;
7191 cleanup_pop_pc_16bit_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7192 struct displaced_step_closure
*dsc
)
7195 int val
= displaced_read_reg (regs
, dsc
, 7);
7196 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, val
, BX_WRITE_PC
);
7199 val
= displaced_read_reg (regs
, dsc
, 8);
7200 displaced_write_reg (regs
, dsc
, 7, val
, CANNOT_WRITE_PC
);
7203 displaced_write_reg (regs
, dsc
, 8, dsc
->tmp
[0], CANNOT_WRITE_PC
);
7208 thumb_copy_pop_pc_16bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
7209 struct regcache
*regs
,
7210 struct displaced_step_closure
*dsc
)
7212 dsc
->u
.block
.regmask
= insn1
& 0x00ff;
7214 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
7217 (1) register list is full, that is, r0-r7 are used.
7218 Prepare: tmp[0] <- r8
7220 POP {r0, r1, ...., r6, r7}; remove PC from reglist
7221 MOV r8, r7; Move value of r7 to r8;
7222 POP {r7}; Store PC value into r7.
7224 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
7226 (2) register list is not full, supposing there are N registers in
7227 register list (except PC, 0 <= N <= 7).
7228 Prepare: for each i, 0 - N, tmp[i] <- ri.
7230 POP {r0, r1, ...., rN};
7232 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
7233 from tmp[] properly.
7235 if (debug_displaced
)
7236 fprintf_unfiltered (gdb_stdlog
,
7237 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
7238 dsc
->u
.block
.regmask
, insn1
);
7240 if (dsc
->u
.block
.regmask
== 0xff)
7242 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 8);
7244 dsc
->modinsn
[0] = (insn1
& 0xfeff); /* POP {r0,r1,...,r6, r7} */
7245 dsc
->modinsn
[1] = 0x46b8; /* MOV r8, r7 */
7246 dsc
->modinsn
[2] = 0xbc80; /* POP {r7} */
7249 dsc
->cleanup
= &cleanup_pop_pc_16bit_all
;
7253 unsigned int num_in_list
= bitcount (dsc
->u
.block
.regmask
);
7255 unsigned int new_regmask
;
7257 for (i
= 0; i
< num_in_list
+ 1; i
++)
7258 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7260 new_regmask
= (1 << (num_in_list
+ 1)) - 1;
7262 if (debug_displaced
)
7263 fprintf_unfiltered (gdb_stdlog
, _("displaced: POP "
7264 "{..., pc}: original reg list %.4x,"
7265 " modified list %.4x\n"),
7266 (int) dsc
->u
.block
.regmask
, new_regmask
);
7268 dsc
->u
.block
.regmask
|= 0x8000;
7269 dsc
->u
.block
.writeback
= 0;
7270 dsc
->u
.block
.cond
= INST_AL
;
7272 dsc
->modinsn
[0] = (insn1
& ~0x1ff) | (new_regmask
& 0xff);
7274 dsc
->cleanup
= &cleanup_block_load_pc
;
7281 thumb_process_displaced_16bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7282 struct regcache
*regs
,
7283 struct displaced_step_closure
*dsc
)
7285 unsigned short op_bit_12_15
= bits (insn1
, 12, 15);
7286 unsigned short op_bit_10_11
= bits (insn1
, 10, 11);
7289 /* 16-bit thumb instructions. */
7290 switch (op_bit_12_15
)
7292 /* Shift (imme), add, subtract, move and compare. */
7293 case 0: case 1: case 2: case 3:
7294 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7295 "shift/add/sub/mov/cmp",
7299 switch (op_bit_10_11
)
7301 case 0: /* Data-processing */
7302 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7306 case 1: /* Special data instructions and branch and exchange. */
7308 unsigned short op
= bits (insn1
, 7, 9);
7309 if (op
== 6 || op
== 7) /* BX or BLX */
7310 err
= thumb_copy_bx_blx_reg (gdbarch
, insn1
, regs
, dsc
);
7311 else if (bits (insn1
, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
7312 err
= thumb_copy_alu_reg (gdbarch
, insn1
, regs
, dsc
);
7314 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "special data",
7318 default: /* LDR (literal) */
7319 err
= thumb_copy_16bit_ldr_literal (gdbarch
, insn1
, regs
, dsc
);
7322 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
7323 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldr/str", dsc
);
7326 if (op_bit_10_11
< 2) /* Generate PC-relative address */
7327 err
= thumb_decode_pc_relative_16bit (gdbarch
, insn1
, regs
, dsc
);
7328 else /* Generate SP-relative address */
7329 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "sp-relative", dsc
);
7331 case 11: /* Misc 16-bit instructions */
7333 switch (bits (insn1
, 8, 11))
7335 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
7336 err
= thumb_copy_cbnz_cbz (gdbarch
, insn1
, regs
, dsc
);
7338 case 12: case 13: /* POP */
7339 if (bit (insn1
, 8)) /* PC is in register list. */
7340 err
= thumb_copy_pop_pc_16bit (gdbarch
, insn1
, regs
, dsc
);
7342 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "pop", dsc
);
7344 case 15: /* If-Then, and hints */
7345 if (bits (insn1
, 0, 3))
7346 /* If-Then makes up to four following instructions conditional.
7347 IT instruction itself is not conditional, so handle it as a
7348 common unmodified instruction. */
7349 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "If-Then",
7352 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "hints", dsc
);
7355 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "misc", dsc
);
7360 if (op_bit_10_11
< 2) /* Store multiple registers */
7361 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "stm", dsc
);
7362 else /* Load multiple registers */
7363 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldm", dsc
);
7365 case 13: /* Conditional branch and supervisor call */
7366 if (bits (insn1
, 9, 11) != 7) /* conditional branch */
7367 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7369 err
= thumb_copy_svc (gdbarch
, insn1
, regs
, dsc
);
7371 case 14: /* Unconditional branch */
7372 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7379 internal_error (__FILE__
, __LINE__
,
7380 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
7384 decode_thumb_32bit_ld_mem_hints (struct gdbarch
*gdbarch
,
7385 uint16_t insn1
, uint16_t insn2
,
7386 struct regcache
*regs
,
7387 struct displaced_step_closure
*dsc
)
7389 int rt
= bits (insn2
, 12, 15);
7390 int rn
= bits (insn1
, 0, 3);
7391 int op1
= bits (insn1
, 7, 8);
7393 switch (bits (insn1
, 5, 6))
7395 case 0: /* Load byte and memory hints */
7396 if (rt
== 0xf) /* PLD/PLI */
7399 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
7400 return thumb2_copy_preload (gdbarch
, insn1
, insn2
, regs
, dsc
);
7402 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7407 if (rn
== 0xf) /* LDRB/LDRSB (literal) */
7408 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7411 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7412 "ldrb{reg, immediate}/ldrbt",
7417 case 1: /* Load halfword and memory hints. */
7418 if (rt
== 0xf) /* PLD{W} and Unalloc memory hint. */
7419 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7420 "pld/unalloc memhint", dsc
);
7424 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7427 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7431 case 2: /* Load word */
7433 int insn2_bit_8_11
= bits (insn2
, 8, 11);
7436 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
, 4);
7437 else if (op1
== 0x1) /* Encoding T3 */
7438 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
, dsc
,
7440 else /* op1 == 0x0 */
7442 if (insn2_bit_8_11
== 0xc || (insn2_bit_8_11
& 0x9) == 0x9)
7443 /* LDR (immediate) */
7444 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7445 dsc
, bit (insn2
, 8), 1);
7446 else if (insn2_bit_8_11
== 0xe) /* LDRT */
7447 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7450 /* LDR (register) */
7451 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7457 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
7464 thumb_process_displaced_32bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7465 uint16_t insn2
, struct regcache
*regs
,
7466 struct displaced_step_closure
*dsc
)
7469 unsigned short op
= bit (insn2
, 15);
7470 unsigned int op1
= bits (insn1
, 11, 12);
7476 switch (bits (insn1
, 9, 10))
7481 /* Load/store {dual, execlusive}, table branch. */
7482 if (bits (insn1
, 7, 8) == 1 && bits (insn1
, 4, 5) == 1
7483 && bits (insn2
, 5, 7) == 0)
7484 err
= thumb2_copy_table_branch (gdbarch
, insn1
, insn2
, regs
,
7487 /* PC is not allowed to use in load/store {dual, exclusive}
7489 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7490 "load/store dual/ex", dsc
);
7492 else /* load/store multiple */
7494 switch (bits (insn1
, 7, 8))
7496 case 0: case 3: /* SRS, RFE */
7497 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7500 case 1: case 2: /* LDM/STM/PUSH/POP */
7501 err
= thumb2_copy_block_xfer (gdbarch
, insn1
, insn2
, regs
, dsc
);
7508 /* Data-processing (shift register). */
7509 err
= thumb2_decode_dp_shift_reg (gdbarch
, insn1
, insn2
, regs
,
7512 default: /* Coprocessor instructions. */
7513 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7518 case 2: /* op1 = 2 */
7519 if (op
) /* Branch and misc control. */
7521 if (bit (insn2
, 14) /* BLX/BL */
7522 || bit (insn2
, 12) /* Unconditional branch */
7523 || (bits (insn1
, 7, 9) != 0x7)) /* Conditional branch */
7524 err
= thumb2_copy_b_bl_blx (gdbarch
, insn1
, insn2
, regs
, dsc
);
7526 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7531 if (bit (insn1
, 9)) /* Data processing (plain binary imm). */
7533 int op
= bits (insn1
, 4, 8);
7534 int rn
= bits (insn1
, 0, 3);
7535 if ((op
== 0 || op
== 0xa) && rn
== 0xf)
7536 err
= thumb_copy_pc_relative_32bit (gdbarch
, insn1
, insn2
,
7539 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7542 else /* Data processing (modified immeidate) */
7543 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7547 case 3: /* op1 = 3 */
7548 switch (bits (insn1
, 9, 10))
7552 err
= decode_thumb_32bit_ld_mem_hints (gdbarch
, insn1
, insn2
,
7554 else /* NEON Load/Store and Store single data item */
7555 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7556 "neon elt/struct load/store",
7559 case 1: /* op1 = 3, bits (9, 10) == 1 */
7560 switch (bits (insn1
, 7, 8))
7562 case 0: case 1: /* Data processing (register) */
7563 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7566 case 2: /* Multiply and absolute difference */
7567 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7568 "mul/mua/diff", dsc
);
7570 case 3: /* Long multiply and divide */
7571 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7576 default: /* Coprocessor instructions */
7577 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7586 internal_error (__FILE__
, __LINE__
,
7587 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
7592 thumb_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7593 struct regcache
*regs
,
7594 struct displaced_step_closure
*dsc
)
7596 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7598 = read_memory_unsigned_integer (from
, 2, byte_order_for_code
);
7600 if (debug_displaced
)
7601 fprintf_unfiltered (gdb_stdlog
, "displaced: process thumb insn %.4x "
7602 "at %.8lx\n", insn1
, (unsigned long) from
);
7605 dsc
->insn_size
= thumb_insn_size (insn1
);
7606 if (thumb_insn_size (insn1
) == 4)
7609 = read_memory_unsigned_integer (from
+ 2, 2, byte_order_for_code
);
7610 thumb_process_displaced_32bit_insn (gdbarch
, insn1
, insn2
, regs
, dsc
);
7613 thumb_process_displaced_16bit_insn (gdbarch
, insn1
, regs
, dsc
);
7617 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7618 CORE_ADDR to
, struct regcache
*regs
,
7619 struct displaced_step_closure
*dsc
)
7622 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7625 /* Most displaced instructions use a 1-instruction scratch space, so set this
7626 here and override below if/when necessary. */
7628 dsc
->insn_addr
= from
;
7629 dsc
->scratch_base
= to
;
7630 dsc
->cleanup
= NULL
;
7631 dsc
->wrote_to_pc
= 0;
7633 if (!displaced_in_arm_mode (regs
))
7634 return thumb_process_displaced_insn (gdbarch
, from
, regs
, dsc
);
7638 insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
7639 if (debug_displaced
)
7640 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
7641 "at %.8lx\n", (unsigned long) insn
,
7642 (unsigned long) from
);
7644 if ((insn
& 0xf0000000) == 0xf0000000)
7645 err
= arm_decode_unconditional (gdbarch
, insn
, regs
, dsc
);
7646 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
7648 case 0x0: case 0x1: case 0x2: case 0x3:
7649 err
= arm_decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
7652 case 0x4: case 0x5: case 0x6:
7653 err
= arm_decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
7657 err
= arm_decode_media (gdbarch
, insn
, dsc
);
7660 case 0x8: case 0x9: case 0xa: case 0xb:
7661 err
= arm_decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
7664 case 0xc: case 0xd: case 0xe: case 0xf:
7665 err
= arm_decode_svc_copro (gdbarch
, insn
, regs
, dsc
);
7670 internal_error (__FILE__
, __LINE__
,
7671 _("arm_process_displaced_insn: Instruction decode error"));
7674 /* Actually set up the scratch space for a displaced instruction. */
7677 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7678 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
7680 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7681 unsigned int i
, len
, offset
;
7682 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7683 int size
= dsc
->is_thumb
? 2 : 4;
7684 const gdb_byte
*bkp_insn
;
7687 /* Poke modified instruction(s). */
7688 for (i
= 0; i
< dsc
->numinsns
; i
++)
7690 if (debug_displaced
)
7692 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn ");
7694 fprintf_unfiltered (gdb_stdlog
, "%.8lx",
7697 fprintf_unfiltered (gdb_stdlog
, "%.4x",
7698 (unsigned short)dsc
->modinsn
[i
]);
7700 fprintf_unfiltered (gdb_stdlog
, " at %.8lx\n",
7701 (unsigned long) to
+ offset
);
7704 write_memory_unsigned_integer (to
+ offset
, size
,
7705 byte_order_for_code
,
7710 /* Choose the correct breakpoint instruction. */
7713 bkp_insn
= tdep
->thumb_breakpoint
;
7714 len
= tdep
->thumb_breakpoint_size
;
7718 bkp_insn
= tdep
->arm_breakpoint
;
7719 len
= tdep
->arm_breakpoint_size
;
7722 /* Put breakpoint afterwards. */
7723 write_memory (to
+ offset
, bkp_insn
, len
);
7725 if (debug_displaced
)
7726 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
7727 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
7730 /* Entry point for cleaning things up after a displaced instruction has been
7734 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
7735 struct displaced_step_closure
*dsc
,
7736 CORE_ADDR from
, CORE_ADDR to
,
7737 struct regcache
*regs
)
7740 dsc
->cleanup (gdbarch
, regs
, dsc
);
7742 if (!dsc
->wrote_to_pc
)
7743 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
7744 dsc
->insn_addr
+ dsc
->insn_size
);
7748 #include "bfd-in2.h"
7749 #include "libcoff.h"
7752 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
7754 struct gdbarch
*gdbarch
= (struct gdbarch
*) info
->application_data
;
7756 if (arm_pc_is_thumb (gdbarch
, memaddr
))
7758 static asymbol
*asym
;
7759 static combined_entry_type ce
;
7760 static struct coff_symbol_struct csym
;
7761 static struct bfd fake_bfd
;
7762 static bfd_target fake_target
;
7764 if (csym
.native
== NULL
)
7766 /* Create a fake symbol vector containing a Thumb symbol.
7767 This is solely so that the code in print_insn_little_arm()
7768 and print_insn_big_arm() in opcodes/arm-dis.c will detect
7769 the presence of a Thumb symbol and switch to decoding
7770 Thumb instructions. */
7772 fake_target
.flavour
= bfd_target_coff_flavour
;
7773 fake_bfd
.xvec
= &fake_target
;
7774 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
7776 csym
.symbol
.the_bfd
= &fake_bfd
;
7777 csym
.symbol
.name
= "fake";
7778 asym
= (asymbol
*) & csym
;
7781 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
7782 info
->symbols
= &asym
;
7785 info
->symbols
= NULL
;
7787 if (info
->endian
== BFD_ENDIAN_BIG
)
7788 return print_insn_big_arm (memaddr
, info
);
7790 return print_insn_little_arm (memaddr
, info
);
7793 /* The following define instruction sequences that will cause ARM
7794 cpu's to take an undefined instruction trap. These are used to
7795 signal a breakpoint to GDB.
7797 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
7798 modes. A different instruction is required for each mode. The ARM
7799 cpu's can also be big or little endian. Thus four different
7800 instructions are needed to support all cases.
7802 Note: ARMv4 defines several new instructions that will take the
7803 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
7804 not in fact add the new instructions. The new undefined
7805 instructions in ARMv4 are all instructions that had no defined
7806 behaviour in earlier chips. There is no guarantee that they will
7807 raise an exception, but may be treated as NOP's. In practice, it
7808 may only safe to rely on instructions matching:
7810 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
7811 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
7812 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
7814 Even this may only true if the condition predicate is true. The
7815 following use a condition predicate of ALWAYS so it is always TRUE.
7817 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
7818 and NetBSD all use a software interrupt rather than an undefined
7819 instruction to force a trap. This can be handled by by the
7820 abi-specific code during establishment of the gdbarch vector. */
7822 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
7823 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
7824 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
7825 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
7827 static const gdb_byte arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
7828 static const gdb_byte arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
7829 static const gdb_byte arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
7830 static const gdb_byte arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
7832 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7835 arm_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7837 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7838 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7840 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
7842 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
7844 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
7845 check whether we are replacing a 32-bit instruction. */
7846 if (tdep
->thumb2_breakpoint
!= NULL
)
7850 if (target_read_memory (*pcptr
, buf
, 2) == 0)
7852 unsigned short inst1
;
7854 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
7855 if (thumb_insn_size (inst1
) == 4)
7856 return ARM_BP_KIND_THUMB2
;
7860 return ARM_BP_KIND_THUMB
;
7863 return ARM_BP_KIND_ARM
;
7867 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7869 static const gdb_byte
*
7870 arm_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7872 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7876 case ARM_BP_KIND_ARM
:
7877 *size
= tdep
->arm_breakpoint_size
;
7878 return tdep
->arm_breakpoint
;
7879 case ARM_BP_KIND_THUMB
:
7880 *size
= tdep
->thumb_breakpoint_size
;
7881 return tdep
->thumb_breakpoint
;
7882 case ARM_BP_KIND_THUMB2
:
7883 *size
= tdep
->thumb2_breakpoint_size
;
7884 return tdep
->thumb2_breakpoint
;
7886 gdb_assert_not_reached ("unexpected arm breakpoint kind");
7890 /* Implement the breakpoint_kind_from_current_state gdbarch method. */
7893 arm_breakpoint_kind_from_current_state (struct gdbarch
*gdbarch
,
7894 struct regcache
*regcache
,
7899 /* Check the memory pointed by PC is readable. */
7900 if (target_read_memory (regcache_read_pc (regcache
), buf
, 4) == 0)
7902 struct arm_get_next_pcs next_pcs_ctx
;
7905 VEC (CORE_ADDR
) *next_pcs
= NULL
;
7906 struct cleanup
*old_chain
7907 = make_cleanup (VEC_cleanup (CORE_ADDR
), &next_pcs
);
7909 arm_get_next_pcs_ctor (&next_pcs_ctx
,
7910 &arm_get_next_pcs_ops
,
7911 gdbarch_byte_order (gdbarch
),
7912 gdbarch_byte_order_for_code (gdbarch
),
7916 next_pcs
= arm_get_next_pcs (&next_pcs_ctx
);
7918 /* If MEMADDR is the next instruction of current pc, do the
7919 software single step computation, and get the thumb mode by
7920 the destination address. */
7921 for (i
= 0; VEC_iterate (CORE_ADDR
, next_pcs
, i
, pc
); i
++)
7923 if (UNMAKE_THUMB_ADDR (pc
) == *pcptr
)
7925 do_cleanups (old_chain
);
7927 if (IS_THUMB_ADDR (pc
))
7929 *pcptr
= MAKE_THUMB_ADDR (*pcptr
);
7930 return arm_breakpoint_kind_from_pc (gdbarch
, pcptr
);
7933 return ARM_BP_KIND_ARM
;
7937 do_cleanups (old_chain
);
7940 return arm_breakpoint_kind_from_pc (gdbarch
, pcptr
);
7943 /* Extract from an array REGBUF containing the (raw) register state a
7944 function return value of type TYPE, and copy that, in virtual
7945 format, into VALBUF. */
7948 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
7951 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
7952 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7954 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
7956 switch (gdbarch_tdep (gdbarch
)->fp_model
)
7960 /* The value is in register F0 in internal format. We need to
7961 extract the raw value and then convert it to the desired
7963 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
7965 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
7966 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
7967 valbuf
, gdbarch_byte_order (gdbarch
));
7971 case ARM_FLOAT_SOFT_FPA
:
7972 case ARM_FLOAT_SOFT_VFP
:
7973 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7974 not using the VFP ABI code. */
7976 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
7977 if (TYPE_LENGTH (type
) > 4)
7978 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
7979 valbuf
+ INT_REGISTER_SIZE
);
7983 internal_error (__FILE__
, __LINE__
,
7984 _("arm_extract_return_value: "
7985 "Floating point model not supported"));
7989 else if (TYPE_CODE (type
) == TYPE_CODE_INT
7990 || TYPE_CODE (type
) == TYPE_CODE_CHAR
7991 || TYPE_CODE (type
) == TYPE_CODE_BOOL
7992 || TYPE_CODE (type
) == TYPE_CODE_PTR
7993 || TYPE_CODE (type
) == TYPE_CODE_REF
7994 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
7996 /* If the type is a plain integer, then the access is
7997 straight-forward. Otherwise we have to play around a bit
7999 int len
= TYPE_LENGTH (type
);
8000 int regno
= ARM_A1_REGNUM
;
8005 /* By using store_unsigned_integer we avoid having to do
8006 anything special for small big-endian values. */
8007 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
8008 store_unsigned_integer (valbuf
,
8009 (len
> INT_REGISTER_SIZE
8010 ? INT_REGISTER_SIZE
: len
),
8012 len
-= INT_REGISTER_SIZE
;
8013 valbuf
+= INT_REGISTER_SIZE
;
8018 /* For a structure or union the behaviour is as if the value had
8019 been stored to word-aligned memory and then loaded into
8020 registers with 32-bit load instruction(s). */
8021 int len
= TYPE_LENGTH (type
);
8022 int regno
= ARM_A1_REGNUM
;
8023 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8027 regcache_cooked_read (regs
, regno
++, tmpbuf
);
8028 memcpy (valbuf
, tmpbuf
,
8029 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
8030 len
-= INT_REGISTER_SIZE
;
8031 valbuf
+= INT_REGISTER_SIZE
;
8037 /* Will a function return an aggregate type in memory or in a
8038 register? Return 0 if an aggregate type can be returned in a
8039 register, 1 if it must be returned in memory. */
8042 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
8044 enum type_code code
;
8046 type
= check_typedef (type
);
8048 /* Simple, non-aggregate types (ie not including vectors and
8049 complex) are always returned in a register (or registers). */
8050 code
= TYPE_CODE (type
);
8051 if (TYPE_CODE_STRUCT
!= code
&& TYPE_CODE_UNION
!= code
8052 && TYPE_CODE_ARRAY
!= code
&& TYPE_CODE_COMPLEX
!= code
)
8055 if (TYPE_CODE_ARRAY
== code
&& TYPE_VECTOR (type
))
8057 /* Vector values should be returned using ARM registers if they
8058 are not over 16 bytes. */
8059 return (TYPE_LENGTH (type
) > 16);
8062 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
8064 /* The AAPCS says all aggregates not larger than a word are returned
8066 if (TYPE_LENGTH (type
) <= INT_REGISTER_SIZE
)
8075 /* All aggregate types that won't fit in a register must be returned
8077 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
8080 /* In the ARM ABI, "integer" like aggregate types are returned in
8081 registers. For an aggregate type to be integer like, its size
8082 must be less than or equal to INT_REGISTER_SIZE and the
8083 offset of each addressable subfield must be zero. Note that bit
8084 fields are not addressable, and all addressable subfields of
8085 unions always start at offset zero.
8087 This function is based on the behaviour of GCC 2.95.1.
8088 See: gcc/arm.c: arm_return_in_memory() for details.
8090 Note: All versions of GCC before GCC 2.95.2 do not set up the
8091 parameters correctly for a function returning the following
8092 structure: struct { float f;}; This should be returned in memory,
8093 not a register. Richard Earnshaw sent me a patch, but I do not
8094 know of any way to detect if a function like the above has been
8095 compiled with the correct calling convention. */
8097 /* Assume all other aggregate types can be returned in a register.
8098 Run a check for structures, unions and arrays. */
8101 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
8104 /* Need to check if this struct/union is "integer" like. For
8105 this to be true, its size must be less than or equal to
8106 INT_REGISTER_SIZE and the offset of each addressable
8107 subfield must be zero. Note that bit fields are not
8108 addressable, and unions always start at offset zero. If any
8109 of the subfields is a floating point type, the struct/union
8110 cannot be an integer type. */
8112 /* For each field in the object, check:
8113 1) Is it FP? --> yes, nRc = 1;
8114 2) Is it addressable (bitpos != 0) and
8115 not packed (bitsize == 0)?
8119 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
8121 enum type_code field_type_code
;
8124 = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
,
8127 /* Is it a floating point type field? */
8128 if (field_type_code
== TYPE_CODE_FLT
)
8134 /* If bitpos != 0, then we have to care about it. */
8135 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
8137 /* Bitfields are not addressable. If the field bitsize is
8138 zero, then the field is not packed. Hence it cannot be
8139 a bitfield or any other packed type. */
8140 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
8153 /* Write into appropriate registers a function return value of type
8154 TYPE, given in virtual format. */
8157 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
8158 const gdb_byte
*valbuf
)
8160 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
8161 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8163 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
8165 gdb_byte buf
[MAX_REGISTER_SIZE
];
8167 switch (gdbarch_tdep (gdbarch
)->fp_model
)
8171 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
8172 gdbarch_byte_order (gdbarch
));
8173 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
8176 case ARM_FLOAT_SOFT_FPA
:
8177 case ARM_FLOAT_SOFT_VFP
:
8178 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8179 not using the VFP ABI code. */
8181 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
8182 if (TYPE_LENGTH (type
) > 4)
8183 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
8184 valbuf
+ INT_REGISTER_SIZE
);
8188 internal_error (__FILE__
, __LINE__
,
8189 _("arm_store_return_value: Floating "
8190 "point model not supported"));
8194 else if (TYPE_CODE (type
) == TYPE_CODE_INT
8195 || TYPE_CODE (type
) == TYPE_CODE_CHAR
8196 || TYPE_CODE (type
) == TYPE_CODE_BOOL
8197 || TYPE_CODE (type
) == TYPE_CODE_PTR
8198 || TYPE_CODE (type
) == TYPE_CODE_REF
8199 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
8201 if (TYPE_LENGTH (type
) <= 4)
8203 /* Values of one word or less are zero/sign-extended and
8205 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8206 LONGEST val
= unpack_long (type
, valbuf
);
8208 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
8209 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
8213 /* Integral values greater than one word are stored in consecutive
8214 registers starting with r0. This will always be a multiple of
8215 the regiser size. */
8216 int len
= TYPE_LENGTH (type
);
8217 int regno
= ARM_A1_REGNUM
;
8221 regcache_cooked_write (regs
, regno
++, valbuf
);
8222 len
-= INT_REGISTER_SIZE
;
8223 valbuf
+= INT_REGISTER_SIZE
;
8229 /* For a structure or union the behaviour is as if the value had
8230 been stored to word-aligned memory and then loaded into
8231 registers with 32-bit load instruction(s). */
8232 int len
= TYPE_LENGTH (type
);
8233 int regno
= ARM_A1_REGNUM
;
8234 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8238 memcpy (tmpbuf
, valbuf
,
8239 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
8240 regcache_cooked_write (regs
, regno
++, tmpbuf
);
8241 len
-= INT_REGISTER_SIZE
;
8242 valbuf
+= INT_REGISTER_SIZE
;
8248 /* Handle function return values. */
8250 static enum return_value_convention
8251 arm_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
8252 struct type
*valtype
, struct regcache
*regcache
,
8253 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
8255 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8256 struct type
*func_type
= function
? value_type (function
) : NULL
;
8257 enum arm_vfp_cprc_base_type vfp_base_type
;
8260 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
8261 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
8263 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
8264 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
8266 for (i
= 0; i
< vfp_base_count
; i
++)
8268 if (reg_char
== 'q')
8271 arm_neon_quad_write (gdbarch
, regcache
, i
,
8272 writebuf
+ i
* unit_length
);
8275 arm_neon_quad_read (gdbarch
, regcache
, i
,
8276 readbuf
+ i
* unit_length
);
8283 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d", reg_char
, i
);
8284 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8287 regcache_cooked_write (regcache
, regnum
,
8288 writebuf
+ i
* unit_length
);
8290 regcache_cooked_read (regcache
, regnum
,
8291 readbuf
+ i
* unit_length
);
8294 return RETURN_VALUE_REGISTER_CONVENTION
;
8297 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
8298 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
8299 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
8301 if (tdep
->struct_return
== pcc_struct_return
8302 || arm_return_in_memory (gdbarch
, valtype
))
8303 return RETURN_VALUE_STRUCT_CONVENTION
;
8305 else if (TYPE_CODE (valtype
) == TYPE_CODE_COMPLEX
)
8307 if (arm_return_in_memory (gdbarch
, valtype
))
8308 return RETURN_VALUE_STRUCT_CONVENTION
;
8312 arm_store_return_value (valtype
, regcache
, writebuf
);
8315 arm_extract_return_value (valtype
, regcache
, readbuf
);
8317 return RETURN_VALUE_REGISTER_CONVENTION
;
8322 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
8324 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
8325 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8326 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8328 gdb_byte buf
[INT_REGISTER_SIZE
];
8330 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
8332 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
8336 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
8340 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
8341 return the target PC. Otherwise return 0. */
8344 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
8348 CORE_ADDR start_addr
;
8350 /* Find the starting address and name of the function containing the PC. */
8351 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
8353 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
8355 start_addr
= arm_skip_bx_reg (frame
, pc
);
8356 if (start_addr
!= 0)
8362 /* If PC is in a Thumb call or return stub, return the address of the
8363 target PC, which is in a register. The thunk functions are called
8364 _call_via_xx, where x is the register name. The possible names
8365 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
8366 functions, named __ARM_call_via_r[0-7]. */
8367 if (startswith (name
, "_call_via_")
8368 || startswith (name
, "__ARM_call_via_"))
8370 /* Use the name suffix to determine which register contains the
8372 static char *table
[15] =
8373 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8374 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
8377 int offset
= strlen (name
) - 2;
8379 for (regno
= 0; regno
<= 14; regno
++)
8380 if (strcmp (&name
[offset
], table
[regno
]) == 0)
8381 return get_frame_register_unsigned (frame
, regno
);
8384 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
8385 non-interworking calls to foo. We could decode the stubs
8386 to find the target but it's easier to use the symbol table. */
8387 namelen
= strlen (name
);
8388 if (name
[0] == '_' && name
[1] == '_'
8389 && ((namelen
> 2 + strlen ("_from_thumb")
8390 && startswith (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb"))
8391 || (namelen
> 2 + strlen ("_from_arm")
8392 && startswith (name
+ namelen
- strlen ("_from_arm"), "_from_arm"))))
8395 int target_len
= namelen
- 2;
8396 struct bound_minimal_symbol minsym
;
8397 struct objfile
*objfile
;
8398 struct obj_section
*sec
;
8400 if (name
[namelen
- 1] == 'b')
8401 target_len
-= strlen ("_from_thumb");
8403 target_len
-= strlen ("_from_arm");
8405 target_name
= (char *) alloca (target_len
+ 1);
8406 memcpy (target_name
, name
+ 2, target_len
);
8407 target_name
[target_len
] = '\0';
8409 sec
= find_pc_section (pc
);
8410 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
8411 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
8412 if (minsym
.minsym
!= NULL
)
8413 return BMSYMBOL_VALUE_ADDRESS (minsym
);
8418 return 0; /* not a stub */
8422 set_arm_command (char *args
, int from_tty
)
8424 printf_unfiltered (_("\
8425 \"set arm\" must be followed by an apporpriate subcommand.\n"));
8426 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
8430 show_arm_command (char *args
, int from_tty
)
8432 cmd_show_list (showarmcmdlist
, from_tty
, "");
8436 arm_update_current_architecture (void)
8438 struct gdbarch_info info
;
8440 /* If the current architecture is not ARM, we have nothing to do. */
8441 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_arm
)
8444 /* Update the architecture. */
8445 gdbarch_info_init (&info
);
8447 if (!gdbarch_update_p (info
))
8448 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
8452 set_fp_model_sfunc (char *args
, int from_tty
,
8453 struct cmd_list_element
*c
)
8457 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
8458 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
8460 arm_fp_model
= (enum arm_float_model
) fp_model
;
8464 if (fp_model
== ARM_FLOAT_LAST
)
8465 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
8468 arm_update_current_architecture ();
8472 show_fp_model (struct ui_file
*file
, int from_tty
,
8473 struct cmd_list_element
*c
, const char *value
)
8475 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8477 if (arm_fp_model
== ARM_FLOAT_AUTO
8478 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8479 fprintf_filtered (file
, _("\
8480 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
8481 fp_model_strings
[tdep
->fp_model
]);
8483 fprintf_filtered (file
, _("\
8484 The current ARM floating point model is \"%s\".\n"),
8485 fp_model_strings
[arm_fp_model
]);
8489 arm_set_abi (char *args
, int from_tty
,
8490 struct cmd_list_element
*c
)
8494 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
8495 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
8497 arm_abi_global
= (enum arm_abi_kind
) arm_abi
;
8501 if (arm_abi
== ARM_ABI_LAST
)
8502 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
8505 arm_update_current_architecture ();
8509 arm_show_abi (struct ui_file
*file
, int from_tty
,
8510 struct cmd_list_element
*c
, const char *value
)
8512 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8514 if (arm_abi_global
== ARM_ABI_AUTO
8515 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8516 fprintf_filtered (file
, _("\
8517 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
8518 arm_abi_strings
[tdep
->arm_abi
]);
8520 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
8525 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
8526 struct cmd_list_element
*c
, const char *value
)
8528 fprintf_filtered (file
,
8529 _("The current execution mode assumed "
8530 "(when symbols are unavailable) is \"%s\".\n"),
8531 arm_fallback_mode_string
);
8535 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
8536 struct cmd_list_element
*c
, const char *value
)
8538 fprintf_filtered (file
,
8539 _("The current execution mode assumed "
8540 "(even when symbols are available) is \"%s\".\n"),
8541 arm_force_mode_string
);
8544 /* If the user changes the register disassembly style used for info
8545 register and other commands, we have to also switch the style used
8546 in opcodes for disassembly output. This function is run in the "set
8547 arm disassembly" command, and does that. */
8550 set_disassembly_style_sfunc (char *args
, int from_tty
,
8551 struct cmd_list_element
*c
)
8553 set_disassembly_style ();
8556 /* Return the ARM register name corresponding to register I. */
8558 arm_register_name (struct gdbarch
*gdbarch
, int i
)
8560 const int num_regs
= gdbarch_num_regs (gdbarch
);
8562 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
8563 && i
>= num_regs
&& i
< num_regs
+ 32)
8565 static const char *const vfp_pseudo_names
[] = {
8566 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
8567 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
8568 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
8569 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
8572 return vfp_pseudo_names
[i
- num_regs
];
8575 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
8576 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
8578 static const char *const neon_pseudo_names
[] = {
8579 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
8580 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
8583 return neon_pseudo_names
[i
- num_regs
- 32];
8586 if (i
>= ARRAY_SIZE (arm_register_names
))
8587 /* These registers are only supported on targets which supply
8588 an XML description. */
8591 return arm_register_names
[i
];
8595 set_disassembly_style (void)
8599 /* Find the style that the user wants. */
8600 for (current
= 0; current
< num_disassembly_options
; current
++)
8601 if (disassembly_style
== valid_disassembly_styles
[current
])
8603 gdb_assert (current
< num_disassembly_options
);
8605 /* Synchronize the disassembler. */
8606 set_arm_regname_option (current
);
8609 /* Test whether the coff symbol specific value corresponds to a Thumb
8613 coff_sym_is_thumb (int val
)
8615 return (val
== C_THUMBEXT
8616 || val
== C_THUMBSTAT
8617 || val
== C_THUMBEXTFUNC
8618 || val
== C_THUMBSTATFUNC
8619 || val
== C_THUMBLABEL
);
8622 /* arm_coff_make_msymbol_special()
8623 arm_elf_make_msymbol_special()
8625 These functions test whether the COFF or ELF symbol corresponds to
8626 an address in thumb code, and set a "special" bit in a minimal
8627 symbol to indicate that it does. */
8630 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
8632 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
8634 if (ARM_GET_SYM_BRANCH_TYPE (elfsym
->internal_elf_sym
.st_target_internal
)
8635 == ST_BRANCH_TO_THUMB
)
8636 MSYMBOL_SET_SPECIAL (msym
);
8640 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
8642 if (coff_sym_is_thumb (val
))
8643 MSYMBOL_SET_SPECIAL (msym
);
8647 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
8649 struct arm_per_objfile
*data
= (struct arm_per_objfile
*) arg
;
8652 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
8653 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
8657 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
8660 const char *name
= bfd_asymbol_name (sym
);
8661 struct arm_per_objfile
*data
;
8662 VEC(arm_mapping_symbol_s
) **map_p
;
8663 struct arm_mapping_symbol new_map_sym
;
8665 gdb_assert (name
[0] == '$');
8666 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
8669 data
= (struct arm_per_objfile
*) objfile_data (objfile
,
8670 arm_objfile_data_key
);
8673 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
8674 struct arm_per_objfile
);
8675 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
8676 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
8677 objfile
->obfd
->section_count
,
8678 VEC(arm_mapping_symbol_s
) *);
8680 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
8682 new_map_sym
.value
= sym
->value
;
8683 new_map_sym
.type
= name
[1];
8685 /* Assume that most mapping symbols appear in order of increasing
8686 value. If they were randomly distributed, it would be faster to
8687 always push here and then sort at first use. */
8688 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
8690 struct arm_mapping_symbol
*prev_map_sym
;
8692 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
8693 if (prev_map_sym
->value
>= sym
->value
)
8696 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
8697 arm_compare_mapping_symbols
);
8698 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
8703 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
8707 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
8709 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
8710 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
8712 /* If necessary, set the T bit. */
8715 ULONGEST val
, t_bit
;
8716 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
8717 t_bit
= arm_psr_thumb_bit (gdbarch
);
8718 if (arm_pc_is_thumb (gdbarch
, pc
))
8719 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8722 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8727 /* Read the contents of a NEON quad register, by reading from two
8728 double registers. This is used to implement the quad pseudo
8729 registers, and for argument passing in case the quad registers are
8730 missing; vectors are passed in quad registers when using the VFP
8731 ABI, even if a NEON unit is not present. REGNUM is the index of
8732 the quad register, in [0, 15]. */
8734 static enum register_status
8735 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8736 int regnum
, gdb_byte
*buf
)
8739 gdb_byte reg_buf
[8];
8740 int offset
, double_regnum
;
8741 enum register_status status
;
8743 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8744 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8747 /* d0 is always the least significant half of q0. */
8748 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8753 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8754 if (status
!= REG_VALID
)
8756 memcpy (buf
+ offset
, reg_buf
, 8);
8758 offset
= 8 - offset
;
8759 status
= regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
8760 if (status
!= REG_VALID
)
8762 memcpy (buf
+ offset
, reg_buf
, 8);
8767 static enum register_status
8768 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8769 int regnum
, gdb_byte
*buf
)
8771 const int num_regs
= gdbarch_num_regs (gdbarch
);
8773 gdb_byte reg_buf
[8];
8774 int offset
, double_regnum
;
8776 gdb_assert (regnum
>= num_regs
);
8779 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8780 /* Quad-precision register. */
8781 return arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
8784 enum register_status status
;
8786 /* Single-precision register. */
8787 gdb_assert (regnum
< 32);
8789 /* s0 is always the least significant half of d0. */
8790 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8791 offset
= (regnum
& 1) ? 0 : 4;
8793 offset
= (regnum
& 1) ? 4 : 0;
8795 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8796 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8799 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8800 if (status
== REG_VALID
)
8801 memcpy (buf
, reg_buf
+ offset
, 4);
8806 /* Store the contents of BUF to a NEON quad register, by writing to
8807 two double registers. This is used to implement the quad pseudo
8808 registers, and for argument passing in case the quad registers are
8809 missing; vectors are passed in quad registers when using the VFP
8810 ABI, even if a NEON unit is not present. REGNUM is the index
8811 of the quad register, in [0, 15]. */
8814 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8815 int regnum
, const gdb_byte
*buf
)
8818 int offset
, double_regnum
;
8820 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8821 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8824 /* d0 is always the least significant half of q0. */
8825 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8830 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
8831 offset
= 8 - offset
;
8832 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
8836 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8837 int regnum
, const gdb_byte
*buf
)
8839 const int num_regs
= gdbarch_num_regs (gdbarch
);
8841 gdb_byte reg_buf
[8];
8842 int offset
, double_regnum
;
8844 gdb_assert (regnum
>= num_regs
);
8847 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8848 /* Quad-precision register. */
8849 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
8852 /* Single-precision register. */
8853 gdb_assert (regnum
< 32);
8855 /* s0 is always the least significant half of d0. */
8856 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8857 offset
= (regnum
& 1) ? 0 : 4;
8859 offset
= (regnum
& 1) ? 4 : 0;
8861 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8862 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8865 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8866 memcpy (reg_buf
+ offset
, buf
, 4);
8867 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
8871 static struct value
*
8872 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
8874 const int *reg_p
= (const int *) baton
;
8875 return value_of_register (*reg_p
, frame
);
8878 static enum gdb_osabi
8879 arm_elf_osabi_sniffer (bfd
*abfd
)
8881 unsigned int elfosabi
;
8882 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
8884 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
8886 if (elfosabi
== ELFOSABI_ARM
)
8887 /* GNU tools use this value. Check note sections in this case,
8889 bfd_map_over_sections (abfd
,
8890 generic_elf_osabi_sniff_abi_tag_sections
,
8893 /* Anything else will be handled by the generic ELF sniffer. */
8898 arm_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
8899 struct reggroup
*group
)
8901 /* FPS register's type is INT, but belongs to float_reggroup. Beside
8902 this, FPS register belongs to save_regroup, restore_reggroup, and
8903 all_reggroup, of course. */
8904 if (regnum
== ARM_FPS_REGNUM
)
8905 return (group
== float_reggroup
8906 || group
== save_reggroup
8907 || group
== restore_reggroup
8908 || group
== all_reggroup
);
8910 return default_register_reggroup_p (gdbarch
, regnum
, group
);
8914 /* For backward-compatibility we allow two 'g' packet lengths with
8915 the remote protocol depending on whether FPA registers are
8916 supplied. M-profile targets do not have FPA registers, but some
8917 stubs already exist in the wild which use a 'g' packet which
8918 supplies them albeit with dummy values. The packet format which
8919 includes FPA registers should be considered deprecated for
8920 M-profile targets. */
8923 arm_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8925 if (gdbarch_tdep (gdbarch
)->is_m
)
8927 /* If we know from the executable this is an M-profile target,
8928 cater for remote targets whose register set layout is the
8929 same as the FPA layout. */
8930 register_remote_g_packet_guess (gdbarch
,
8931 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
8932 (16 * INT_REGISTER_SIZE
)
8933 + (8 * FP_REGISTER_SIZE
)
8934 + (2 * INT_REGISTER_SIZE
),
8935 tdesc_arm_with_m_fpa_layout
);
8937 /* The regular M-profile layout. */
8938 register_remote_g_packet_guess (gdbarch
,
8939 /* r0-r12,sp,lr,pc; xpsr */
8940 (16 * INT_REGISTER_SIZE
)
8941 + INT_REGISTER_SIZE
,
8944 /* M-profile plus M4F VFP. */
8945 register_remote_g_packet_guess (gdbarch
,
8946 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
8947 (16 * INT_REGISTER_SIZE
)
8948 + (16 * VFP_REGISTER_SIZE
)
8949 + (2 * INT_REGISTER_SIZE
),
8950 tdesc_arm_with_m_vfp_d16
);
8953 /* Otherwise we don't have a useful guess. */
8956 /* Implement the code_of_frame_writable gdbarch method. */
8959 arm_code_of_frame_writable (struct gdbarch
*gdbarch
, struct frame_info
*frame
)
8961 if (gdbarch_tdep (gdbarch
)->is_m
8962 && get_frame_type (frame
) == SIGTRAMP_FRAME
)
8964 /* M-profile exception frames return to some magic PCs, where
8965 isn't writable at all. */
8973 /* Initialize the current architecture based on INFO. If possible,
8974 re-use an architecture from ARCHES, which is a list of
8975 architectures already created during this debugging session.
8977 Called e.g. at program startup, when reading a core file, and when
8978 reading a binary file. */
8980 static struct gdbarch
*
8981 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8983 struct gdbarch_tdep
*tdep
;
8984 struct gdbarch
*gdbarch
;
8985 struct gdbarch_list
*best_arch
;
8986 enum arm_abi_kind arm_abi
= arm_abi_global
;
8987 enum arm_float_model fp_model
= arm_fp_model
;
8988 struct tdesc_arch_data
*tdesc_data
= NULL
;
8990 int vfp_register_count
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
8991 int have_wmmx_registers
= 0;
8993 int have_fpa_registers
= 1;
8994 const struct target_desc
*tdesc
= info
.target_desc
;
8996 /* If we have an object to base this architecture on, try to determine
8999 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
9001 int ei_osabi
, e_flags
;
9003 switch (bfd_get_flavour (info
.abfd
))
9005 case bfd_target_aout_flavour
:
9006 /* Assume it's an old APCS-style ABI. */
9007 arm_abi
= ARM_ABI_APCS
;
9010 case bfd_target_coff_flavour
:
9011 /* Assume it's an old APCS-style ABI. */
9013 arm_abi
= ARM_ABI_APCS
;
9016 case bfd_target_elf_flavour
:
9017 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
9018 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9020 if (ei_osabi
== ELFOSABI_ARM
)
9022 /* GNU tools used to use this value, but do not for EABI
9023 objects. There's nowhere to tag an EABI version
9024 anyway, so assume APCS. */
9025 arm_abi
= ARM_ABI_APCS
;
9027 else if (ei_osabi
== ELFOSABI_NONE
|| ei_osabi
== ELFOSABI_GNU
)
9029 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
9030 int attr_arch
, attr_profile
;
9034 case EF_ARM_EABI_UNKNOWN
:
9035 /* Assume GNU tools. */
9036 arm_abi
= ARM_ABI_APCS
;
9039 case EF_ARM_EABI_VER4
:
9040 case EF_ARM_EABI_VER5
:
9041 arm_abi
= ARM_ABI_AAPCS
;
9042 /* EABI binaries default to VFP float ordering.
9043 They may also contain build attributes that can
9044 be used to identify if the VFP argument-passing
9046 if (fp_model
== ARM_FLOAT_AUTO
)
9049 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
9053 case AEABI_VFP_args_base
:
9054 /* "The user intended FP parameter/result
9055 passing to conform to AAPCS, base
9057 fp_model
= ARM_FLOAT_SOFT_VFP
;
9059 case AEABI_VFP_args_vfp
:
9060 /* "The user intended FP parameter/result
9061 passing to conform to AAPCS, VFP
9063 fp_model
= ARM_FLOAT_VFP
;
9065 case AEABI_VFP_args_toolchain
:
9066 /* "The user intended FP parameter/result
9067 passing to conform to tool chain-specific
9068 conventions" - we don't know any such
9069 conventions, so leave it as "auto". */
9071 case AEABI_VFP_args_compatible
:
9072 /* "Code is compatible with both the base
9073 and VFP variants; the user did not permit
9074 non-variadic functions to pass FP
9075 parameters/results" - leave it as
9079 /* Attribute value not mentioned in the
9080 November 2012 ABI, so leave it as
9085 fp_model
= ARM_FLOAT_SOFT_VFP
;
9091 /* Leave it as "auto". */
9092 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
9097 /* Detect M-profile programs. This only works if the
9098 executable file includes build attributes; GCC does
9099 copy them to the executable, but e.g. RealView does
9101 attr_arch
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
9103 attr_profile
= bfd_elf_get_obj_attr_int (info
.abfd
,
9105 Tag_CPU_arch_profile
);
9106 /* GCC specifies the profile for v6-M; RealView only
9107 specifies the profile for architectures starting with
9108 V7 (as opposed to architectures with a tag
9109 numerically greater than TAG_CPU_ARCH_V7). */
9110 if (!tdesc_has_registers (tdesc
)
9111 && (attr_arch
== TAG_CPU_ARCH_V6_M
9112 || attr_arch
== TAG_CPU_ARCH_V6S_M
9113 || attr_profile
== 'M'))
9118 if (fp_model
== ARM_FLOAT_AUTO
)
9120 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9122 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
9125 /* Leave it as "auto". Strictly speaking this case
9126 means FPA, but almost nobody uses that now, and
9127 many toolchains fail to set the appropriate bits
9128 for the floating-point model they use. */
9130 case EF_ARM_SOFT_FLOAT
:
9131 fp_model
= ARM_FLOAT_SOFT_FPA
;
9133 case EF_ARM_VFP_FLOAT
:
9134 fp_model
= ARM_FLOAT_VFP
;
9136 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
9137 fp_model
= ARM_FLOAT_SOFT_VFP
;
9142 if (e_flags
& EF_ARM_BE8
)
9143 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
9148 /* Leave it as "auto". */
9153 /* Check any target description for validity. */
9154 if (tdesc_has_registers (tdesc
))
9156 /* For most registers we require GDB's default names; but also allow
9157 the numeric names for sp / lr / pc, as a convenience. */
9158 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
9159 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
9160 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
9162 const struct tdesc_feature
*feature
;
9165 feature
= tdesc_find_feature (tdesc
,
9166 "org.gnu.gdb.arm.core");
9167 if (feature
== NULL
)
9169 feature
= tdesc_find_feature (tdesc
,
9170 "org.gnu.gdb.arm.m-profile");
9171 if (feature
== NULL
)
9177 tdesc_data
= tdesc_data_alloc ();
9180 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
9181 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9182 arm_register_names
[i
]);
9183 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9186 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9189 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9193 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9194 ARM_PS_REGNUM
, "xpsr");
9196 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9197 ARM_PS_REGNUM
, "cpsr");
9201 tdesc_data_cleanup (tdesc_data
);
9205 feature
= tdesc_find_feature (tdesc
,
9206 "org.gnu.gdb.arm.fpa");
9207 if (feature
!= NULL
)
9210 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
9211 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9212 arm_register_names
[i
]);
9215 tdesc_data_cleanup (tdesc_data
);
9220 have_fpa_registers
= 0;
9222 feature
= tdesc_find_feature (tdesc
,
9223 "org.gnu.gdb.xscale.iwmmxt");
9224 if (feature
!= NULL
)
9226 static const char *const iwmmxt_names
[] = {
9227 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
9228 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
9229 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
9230 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
9234 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
9236 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9237 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9239 /* Check for the control registers, but do not fail if they
9241 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
9242 tdesc_numbered_register (feature
, tdesc_data
, i
,
9243 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9245 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
9247 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9248 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9252 tdesc_data_cleanup (tdesc_data
);
9256 have_wmmx_registers
= 1;
9259 /* If we have a VFP unit, check whether the single precision registers
9260 are present. If not, then we will synthesize them as pseudo
9262 feature
= tdesc_find_feature (tdesc
,
9263 "org.gnu.gdb.arm.vfp");
9264 if (feature
!= NULL
)
9266 static const char *const vfp_double_names
[] = {
9267 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
9268 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
9269 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
9270 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
9273 /* Require the double precision registers. There must be either
9276 for (i
= 0; i
< 32; i
++)
9278 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9280 vfp_double_names
[i
]);
9284 if (!valid_p
&& i
== 16)
9287 /* Also require FPSCR. */
9288 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9289 ARM_FPSCR_REGNUM
, "fpscr");
9292 tdesc_data_cleanup (tdesc_data
);
9296 if (tdesc_unnumbered_register (feature
, "s0") == 0)
9297 have_vfp_pseudos
= 1;
9299 vfp_register_count
= i
;
9301 /* If we have VFP, also check for NEON. The architecture allows
9302 NEON without VFP (integer vector operations only), but GDB
9303 does not support that. */
9304 feature
= tdesc_find_feature (tdesc
,
9305 "org.gnu.gdb.arm.neon");
9306 if (feature
!= NULL
)
9308 /* NEON requires 32 double-precision registers. */
9311 tdesc_data_cleanup (tdesc_data
);
9315 /* If there are quad registers defined by the stub, use
9316 their type; otherwise (normally) provide them with
9317 the default type. */
9318 if (tdesc_unnumbered_register (feature
, "q0") == 0)
9319 have_neon_pseudos
= 1;
9326 /* If there is already a candidate, use it. */
9327 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
9329 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
9331 if (arm_abi
!= ARM_ABI_AUTO
9332 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
9335 if (fp_model
!= ARM_FLOAT_AUTO
9336 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
9339 /* There are various other properties in tdep that we do not
9340 need to check here: those derived from a target description,
9341 since gdbarches with a different target description are
9342 automatically disqualified. */
9344 /* Do check is_m, though, since it might come from the binary. */
9345 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
9348 /* Found a match. */
9352 if (best_arch
!= NULL
)
9354 if (tdesc_data
!= NULL
)
9355 tdesc_data_cleanup (tdesc_data
);
9356 return best_arch
->gdbarch
;
9359 tdep
= XCNEW (struct gdbarch_tdep
);
9360 gdbarch
= gdbarch_alloc (&info
, tdep
);
9362 /* Record additional information about the architecture we are defining.
9363 These are gdbarch discriminators, like the OSABI. */
9364 tdep
->arm_abi
= arm_abi
;
9365 tdep
->fp_model
= fp_model
;
9367 tdep
->have_fpa_registers
= have_fpa_registers
;
9368 tdep
->have_wmmx_registers
= have_wmmx_registers
;
9369 gdb_assert (vfp_register_count
== 0
9370 || vfp_register_count
== 16
9371 || vfp_register_count
== 32);
9372 tdep
->vfp_register_count
= vfp_register_count
;
9373 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
9374 tdep
->have_neon_pseudos
= have_neon_pseudos
;
9375 tdep
->have_neon
= have_neon
;
9377 arm_register_g_packet_guesses (gdbarch
);
9380 switch (info
.byte_order_for_code
)
9382 case BFD_ENDIAN_BIG
:
9383 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
9384 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
9385 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
9386 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
9390 case BFD_ENDIAN_LITTLE
:
9391 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
9392 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
9393 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
9394 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
9399 internal_error (__FILE__
, __LINE__
,
9400 _("arm_gdbarch_init: bad byte order for float format"));
9403 /* On ARM targets char defaults to unsigned. */
9404 set_gdbarch_char_signed (gdbarch
, 0);
9406 /* Note: for displaced stepping, this includes the breakpoint, and one word
9407 of additional scratch space. This setting isn't used for anything beside
9408 displaced stepping at present. */
9409 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
9411 /* This should be low enough for everything. */
9412 tdep
->lowest_pc
= 0x20;
9413 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
9415 /* The default, for both APCS and AAPCS, is to return small
9416 structures in registers. */
9417 tdep
->struct_return
= reg_struct_return
;
9419 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
9420 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
9423 set_gdbarch_code_of_frame_writable (gdbarch
, arm_code_of_frame_writable
);
9425 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
9427 /* Frame handling. */
9428 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
9429 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
9430 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
9432 frame_base_set_default (gdbarch
, &arm_normal_base
);
9434 /* Address manipulation. */
9435 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
9437 /* Advance PC across function entry code. */
9438 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
9440 /* Detect whether PC is at a point where the stack has been destroyed. */
9441 set_gdbarch_stack_frame_destroyed_p (gdbarch
, arm_stack_frame_destroyed_p
);
9443 /* Skip trampolines. */
9444 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
9446 /* The stack grows downward. */
9447 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
9449 /* Breakpoint manipulation. */
9450 SET_GDBARCH_BREAKPOINT_MANIPULATION (arm
);
9451 set_gdbarch_breakpoint_kind_from_current_state (gdbarch
,
9452 arm_breakpoint_kind_from_current_state
);
9454 /* Information about registers, etc. */
9455 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
9456 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
9457 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
9458 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9459 set_gdbarch_register_reggroup_p (gdbarch
, arm_register_reggroup_p
);
9461 /* This "info float" is FPA-specific. Use the generic version if we
9463 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
9464 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
9466 /* Internal <-> external register number maps. */
9467 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
9468 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
9470 set_gdbarch_register_name (gdbarch
, arm_register_name
);
9472 /* Returning results. */
9473 set_gdbarch_return_value (gdbarch
, arm_return_value
);
9476 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
9478 /* Minsymbol frobbing. */
9479 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
9480 set_gdbarch_coff_make_msymbol_special (gdbarch
,
9481 arm_coff_make_msymbol_special
);
9482 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
9484 /* Thumb-2 IT block support. */
9485 set_gdbarch_adjust_breakpoint_address (gdbarch
,
9486 arm_adjust_breakpoint_address
);
9488 /* Virtual tables. */
9489 set_gdbarch_vbit_in_delta (gdbarch
, 1);
9491 /* Hook in the ABI-specific overrides, if they have been registered. */
9492 gdbarch_init_osabi (info
, gdbarch
);
9494 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
9496 /* Add some default predicates. */
9498 frame_unwind_append_unwinder (gdbarch
, &arm_m_exception_unwind
);
9499 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
9500 dwarf2_append_unwinders (gdbarch
);
9501 frame_unwind_append_unwinder (gdbarch
, &arm_exidx_unwind
);
9502 frame_unwind_append_unwinder (gdbarch
, &arm_epilogue_frame_unwind
);
9503 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
9505 /* Now we have tuned the configuration, set a few final things,
9506 based on what the OS ABI has told us. */
9508 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
9509 binaries are always marked. */
9510 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
9511 tdep
->arm_abi
= ARM_ABI_APCS
;
9513 /* Watchpoints are not steppable. */
9514 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
9516 /* We used to default to FPA for generic ARM, but almost nobody
9517 uses that now, and we now provide a way for the user to force
9518 the model. So default to the most useful variant. */
9519 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
9520 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
9522 if (tdep
->jb_pc
>= 0)
9523 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
9525 /* Floating point sizes and format. */
9526 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
9527 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
9529 set_gdbarch_double_format
9530 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9531 set_gdbarch_long_double_format
9532 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9536 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
9537 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
9540 if (have_vfp_pseudos
)
9542 /* NOTE: These are the only pseudo registers used by
9543 the ARM target at the moment. If more are added, a
9544 little more care in numbering will be needed. */
9546 int num_pseudos
= 32;
9547 if (have_neon_pseudos
)
9549 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
9550 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
9551 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
9556 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
9558 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
9560 /* Override tdesc_register_type to adjust the types of VFP
9561 registers for NEON. */
9562 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9565 /* Add standard register aliases. We add aliases even for those
9566 nanes which are used by the current architecture - it's simpler,
9567 and does no harm, since nothing ever lists user registers. */
9568 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
9569 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
9570 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
9576 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
9578 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9583 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
9584 (unsigned long) tdep
->lowest_pc
);
9587 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
9590 _initialize_arm_tdep (void)
9592 struct ui_file
*stb
;
9594 const char *setname
;
9595 const char *setdesc
;
9596 const char *const *regnames
;
9598 static char *helptext
;
9599 char regdesc
[1024], *rdptr
= regdesc
;
9600 size_t rest
= sizeof (regdesc
);
9602 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
9604 arm_objfile_data_key
9605 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
9607 /* Add ourselves to objfile event chain. */
9608 observer_attach_new_objfile (arm_exidx_new_objfile
);
9610 = register_objfile_data_with_cleanup (NULL
, arm_exidx_data_free
);
9612 /* Register an ELF OS ABI sniffer for ARM binaries. */
9613 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
9614 bfd_target_elf_flavour
,
9615 arm_elf_osabi_sniffer
);
9617 /* Initialize the standard target descriptions. */
9618 initialize_tdesc_arm_with_m ();
9619 initialize_tdesc_arm_with_m_fpa_layout ();
9620 initialize_tdesc_arm_with_m_vfp_d16 ();
9621 initialize_tdesc_arm_with_iwmmxt ();
9622 initialize_tdesc_arm_with_vfpv2 ();
9623 initialize_tdesc_arm_with_vfpv3 ();
9624 initialize_tdesc_arm_with_neon ();
9626 /* Get the number of possible sets of register names defined in opcodes. */
9627 num_disassembly_options
= get_arm_regname_num_options ();
9629 /* Add root prefix command for all "set arm"/"show arm" commands. */
9630 add_prefix_cmd ("arm", no_class
, set_arm_command
,
9631 _("Various ARM-specific commands."),
9632 &setarmcmdlist
, "set arm ", 0, &setlist
);
9634 add_prefix_cmd ("arm", no_class
, show_arm_command
,
9635 _("Various ARM-specific commands."),
9636 &showarmcmdlist
, "show arm ", 0, &showlist
);
9638 /* Sync the opcode insn printer with our register viewer. */
9639 parse_arm_disassembler_option ("reg-names-std");
9641 /* Initialize the array that will be passed to
9642 add_setshow_enum_cmd(). */
9643 valid_disassembly_styles
= XNEWVEC (const char *,
9644 num_disassembly_options
+ 1);
9645 for (i
= 0; i
< num_disassembly_options
; i
++)
9647 get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
9648 valid_disassembly_styles
[i
] = setname
;
9649 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
9652 /* When we find the default names, tell the disassembler to use
9654 if (!strcmp (setname
, "std"))
9656 disassembly_style
= setname
;
9657 set_arm_regname_option (i
);
9660 /* Mark the end of valid options. */
9661 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
9663 /* Create the help text. */
9664 stb
= mem_fileopen ();
9665 fprintf_unfiltered (stb
, "%s%s%s",
9666 _("The valid values are:\n"),
9668 _("The default is \"std\"."));
9669 helptext
= ui_file_xstrdup (stb
, NULL
);
9670 ui_file_delete (stb
);
9672 add_setshow_enum_cmd("disassembler", no_class
,
9673 valid_disassembly_styles
, &disassembly_style
,
9674 _("Set the disassembly style."),
9675 _("Show the disassembly style."),
9677 set_disassembly_style_sfunc
,
9678 NULL
, /* FIXME: i18n: The disassembly style is
9680 &setarmcmdlist
, &showarmcmdlist
);
9682 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
9683 _("Set usage of ARM 32-bit mode."),
9684 _("Show usage of ARM 32-bit mode."),
9685 _("When off, a 26-bit PC will be used."),
9687 NULL
, /* FIXME: i18n: Usage of ARM 32-bit
9689 &setarmcmdlist
, &showarmcmdlist
);
9691 /* Add a command to allow the user to force the FPU model. */
9692 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
9693 _("Set the floating point type."),
9694 _("Show the floating point type."),
9695 _("auto - Determine the FP typefrom the OS-ABI.\n\
9696 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
9697 fpa - FPA co-processor (GCC compiled).\n\
9698 softvfp - Software FP with pure-endian doubles.\n\
9699 vfp - VFP co-processor."),
9700 set_fp_model_sfunc
, show_fp_model
,
9701 &setarmcmdlist
, &showarmcmdlist
);
9703 /* Add a command to allow the user to force the ABI. */
9704 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
9707 NULL
, arm_set_abi
, arm_show_abi
,
9708 &setarmcmdlist
, &showarmcmdlist
);
9710 /* Add two commands to allow the user to force the assumed
9712 add_setshow_enum_cmd ("fallback-mode", class_support
,
9713 arm_mode_strings
, &arm_fallback_mode_string
,
9714 _("Set the mode assumed when symbols are unavailable."),
9715 _("Show the mode assumed when symbols are unavailable."),
9716 NULL
, NULL
, arm_show_fallback_mode
,
9717 &setarmcmdlist
, &showarmcmdlist
);
9718 add_setshow_enum_cmd ("force-mode", class_support
,
9719 arm_mode_strings
, &arm_force_mode_string
,
9720 _("Set the mode assumed even when symbols are available."),
9721 _("Show the mode assumed even when symbols are available."),
9722 NULL
, NULL
, arm_show_force_mode
,
9723 &setarmcmdlist
, &showarmcmdlist
);
9725 /* Debugging flag. */
9726 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
9727 _("Set ARM debugging."),
9728 _("Show ARM debugging."),
9729 _("When on, arm-specific debugging is enabled."),
9731 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
9732 &setdebuglist
, &showdebuglist
);
9735 /* ARM-reversible process record data structures. */
9737 #define ARM_INSN_SIZE_BYTES 4
9738 #define THUMB_INSN_SIZE_BYTES 2
9739 #define THUMB2_INSN_SIZE_BYTES 4
9742 /* Position of the bit within a 32-bit ARM instruction
9743 that defines whether the instruction is a load or store. */
9744 #define INSN_S_L_BIT_NUM 20
9746 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
9749 unsigned int reg_len = LENGTH; \
9752 REGS = XNEWVEC (uint32_t, reg_len); \
9753 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
9758 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
9761 unsigned int mem_len = LENGTH; \
9764 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
9765 memcpy(&MEMS->len, &RECORD_BUF[0], \
9766 sizeof(struct arm_mem_r) * LENGTH); \
9771 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
9772 #define INSN_RECORDED(ARM_RECORD) \
9773 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
9775 /* ARM memory record structure. */
9778 uint32_t len
; /* Record length. */
9779 uint32_t addr
; /* Memory address. */
9782 /* ARM instruction record contains opcode of current insn
9783 and execution state (before entry to decode_insn()),
9784 contains list of to-be-modified registers and
9785 memory blocks (on return from decode_insn()). */
9787 typedef struct insn_decode_record_t
9789 struct gdbarch
*gdbarch
;
9790 struct regcache
*regcache
;
9791 CORE_ADDR this_addr
; /* Address of the insn being decoded. */
9792 uint32_t arm_insn
; /* Should accommodate thumb. */
9793 uint32_t cond
; /* Condition code. */
9794 uint32_t opcode
; /* Insn opcode. */
9795 uint32_t decode
; /* Insn decode bits. */
9796 uint32_t mem_rec_count
; /* No of mem records. */
9797 uint32_t reg_rec_count
; /* No of reg records. */
9798 uint32_t *arm_regs
; /* Registers to be saved for this record. */
9799 struct arm_mem_r
*arm_mems
; /* Memory to be saved for this record. */
9800 } insn_decode_record
;
9803 /* Checks ARM SBZ and SBO mandatory fields. */
9806 sbo_sbz (uint32_t insn
, uint32_t bit_num
, uint32_t len
, uint32_t sbo
)
9808 uint32_t ones
= bits (insn
, bit_num
- 1, (bit_num
-1) + (len
- 1));
9827 enum arm_record_result
9829 ARM_RECORD_SUCCESS
= 0,
9830 ARM_RECORD_FAILURE
= 1
9837 } arm_record_strx_t
;
9848 arm_record_strx (insn_decode_record
*arm_insn_r
, uint32_t *record_buf
,
9849 uint32_t *record_buf_mem
, arm_record_strx_t str_type
)
9852 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
9853 ULONGEST u_regval
[2]= {0};
9855 uint32_t reg_src1
= 0, reg_src2
= 0;
9856 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
9858 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
9859 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
9861 if (14 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
9863 /* 1) Handle misc store, immediate offset. */
9864 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9865 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9866 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9867 regcache_raw_read_unsigned (reg_cache
, reg_src1
,
9869 if (ARM_PC_REGNUM
== reg_src1
)
9871 /* If R15 was used as Rn, hence current PC+8. */
9872 u_regval
[0] = u_regval
[0] + 8;
9874 offset_8
= (immed_high
<< 4) | immed_low
;
9875 /* Calculate target store address. */
9876 if (14 == arm_insn_r
->opcode
)
9878 tgt_mem_addr
= u_regval
[0] + offset_8
;
9882 tgt_mem_addr
= u_regval
[0] - offset_8
;
9884 if (ARM_RECORD_STRH
== str_type
)
9886 record_buf_mem
[0] = 2;
9887 record_buf_mem
[1] = tgt_mem_addr
;
9888 arm_insn_r
->mem_rec_count
= 1;
9890 else if (ARM_RECORD_STRD
== str_type
)
9892 record_buf_mem
[0] = 4;
9893 record_buf_mem
[1] = tgt_mem_addr
;
9894 record_buf_mem
[2] = 4;
9895 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9896 arm_insn_r
->mem_rec_count
= 2;
9899 else if (12 == arm_insn_r
->opcode
|| 8 == arm_insn_r
->opcode
)
9901 /* 2) Store, register offset. */
9903 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9905 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9906 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9907 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9910 /* If R15 was used as Rn, hence current PC+8. */
9911 u_regval
[0] = u_regval
[0] + 8;
9913 /* Calculate target store address, Rn +/- Rm, register offset. */
9914 if (12 == arm_insn_r
->opcode
)
9916 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9920 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9922 if (ARM_RECORD_STRH
== str_type
)
9924 record_buf_mem
[0] = 2;
9925 record_buf_mem
[1] = tgt_mem_addr
;
9926 arm_insn_r
->mem_rec_count
= 1;
9928 else if (ARM_RECORD_STRD
== str_type
)
9930 record_buf_mem
[0] = 4;
9931 record_buf_mem
[1] = tgt_mem_addr
;
9932 record_buf_mem
[2] = 4;
9933 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9934 arm_insn_r
->mem_rec_count
= 2;
9937 else if (11 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
9938 || 2 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9940 /* 3) Store, immediate pre-indexed. */
9941 /* 5) Store, immediate post-indexed. */
9942 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9943 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9944 offset_8
= (immed_high
<< 4) | immed_low
;
9945 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9946 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9947 /* Calculate target store address, Rn +/- Rm, register offset. */
9948 if (15 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9950 tgt_mem_addr
= u_regval
[0] + offset_8
;
9954 tgt_mem_addr
= u_regval
[0] - offset_8
;
9956 if (ARM_RECORD_STRH
== str_type
)
9958 record_buf_mem
[0] = 2;
9959 record_buf_mem
[1] = tgt_mem_addr
;
9960 arm_insn_r
->mem_rec_count
= 1;
9962 else if (ARM_RECORD_STRD
== str_type
)
9964 record_buf_mem
[0] = 4;
9965 record_buf_mem
[1] = tgt_mem_addr
;
9966 record_buf_mem
[2] = 4;
9967 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9968 arm_insn_r
->mem_rec_count
= 2;
9970 /* Record Rn also as it changes. */
9971 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
9972 arm_insn_r
->reg_rec_count
= 1;
9974 else if (9 == arm_insn_r
->opcode
|| 13 == arm_insn_r
->opcode
9975 || 0 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9977 /* 4) Store, register pre-indexed. */
9978 /* 6) Store, register post -indexed. */
9979 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9980 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9981 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9982 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9983 /* Calculate target store address, Rn +/- Rm, register offset. */
9984 if (13 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9986 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9990 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9992 if (ARM_RECORD_STRH
== str_type
)
9994 record_buf_mem
[0] = 2;
9995 record_buf_mem
[1] = tgt_mem_addr
;
9996 arm_insn_r
->mem_rec_count
= 1;
9998 else if (ARM_RECORD_STRD
== str_type
)
10000 record_buf_mem
[0] = 4;
10001 record_buf_mem
[1] = tgt_mem_addr
;
10002 record_buf_mem
[2] = 4;
10003 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10004 arm_insn_r
->mem_rec_count
= 2;
10006 /* Record Rn also as it changes. */
10007 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
10008 arm_insn_r
->reg_rec_count
= 1;
10013 /* Handling ARM extension space insns. */
10016 arm_record_extension_space (insn_decode_record
*arm_insn_r
)
10018 uint32_t ret
= 0; /* Return value: -1:record failure ; 0:success */
10019 uint32_t opcode1
= 0, opcode2
= 0, insn_op1
= 0;
10020 uint32_t record_buf
[8], record_buf_mem
[8];
10021 uint32_t reg_src1
= 0;
10022 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10023 ULONGEST u_regval
= 0;
10025 gdb_assert (!INSN_RECORDED(arm_insn_r
));
10026 /* Handle unconditional insn extension space. */
10028 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 27);
10029 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10030 if (arm_insn_r
->cond
)
10032 /* PLD has no affect on architectural state, it just affects
10034 if (5 == ((opcode1
& 0xE0) >> 5))
10037 record_buf
[0] = ARM_PS_REGNUM
;
10038 record_buf
[1] = ARM_LR_REGNUM
;
10039 arm_insn_r
->reg_rec_count
= 2;
10041 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10045 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10046 if (3 == opcode1
&& bit (arm_insn_r
->arm_insn
, 4))
10049 /* Undefined instruction on ARM V5; need to handle if later
10050 versions define it. */
10053 opcode1
= bits (arm_insn_r
->arm_insn
, 24, 27);
10054 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10055 insn_op1
= bits (arm_insn_r
->arm_insn
, 20, 23);
10057 /* Handle arithmetic insn extension space. */
10058 if (!opcode1
&& 9 == opcode2
&& 1 != arm_insn_r
->cond
10059 && !INSN_RECORDED(arm_insn_r
))
10061 /* Handle MLA(S) and MUL(S). */
10062 if (0 <= insn_op1
&& 3 >= insn_op1
)
10064 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10065 record_buf
[1] = ARM_PS_REGNUM
;
10066 arm_insn_r
->reg_rec_count
= 2;
10068 else if (4 <= insn_op1
&& 15 >= insn_op1
)
10070 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
10071 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10072 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10073 record_buf
[2] = ARM_PS_REGNUM
;
10074 arm_insn_r
->reg_rec_count
= 3;
10078 opcode1
= bits (arm_insn_r
->arm_insn
, 26, 27);
10079 opcode2
= bits (arm_insn_r
->arm_insn
, 23, 24);
10080 insn_op1
= bits (arm_insn_r
->arm_insn
, 21, 22);
10082 /* Handle control insn extension space. */
10084 if (!opcode1
&& 2 == opcode2
&& !bit (arm_insn_r
->arm_insn
, 20)
10085 && 1 != arm_insn_r
->cond
&& !INSN_RECORDED(arm_insn_r
))
10087 if (!bit (arm_insn_r
->arm_insn
,25))
10089 if (!bits (arm_insn_r
->arm_insn
, 4, 7))
10091 if ((0 == insn_op1
) || (2 == insn_op1
))
10094 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10095 arm_insn_r
->reg_rec_count
= 1;
10097 else if (1 == insn_op1
)
10099 /* CSPR is going to be changed. */
10100 record_buf
[0] = ARM_PS_REGNUM
;
10101 arm_insn_r
->reg_rec_count
= 1;
10103 else if (3 == insn_op1
)
10105 /* SPSR is going to be changed. */
10106 /* We need to get SPSR value, which is yet to be done. */
10110 else if (1 == bits (arm_insn_r
->arm_insn
, 4, 7))
10115 record_buf
[0] = ARM_PS_REGNUM
;
10116 arm_insn_r
->reg_rec_count
= 1;
10118 else if (3 == insn_op1
)
10121 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10122 arm_insn_r
->reg_rec_count
= 1;
10125 else if (3 == bits (arm_insn_r
->arm_insn
, 4, 7))
10128 record_buf
[0] = ARM_PS_REGNUM
;
10129 record_buf
[1] = ARM_LR_REGNUM
;
10130 arm_insn_r
->reg_rec_count
= 2;
10132 else if (5 == bits (arm_insn_r
->arm_insn
, 4, 7))
10134 /* QADD, QSUB, QDADD, QDSUB */
10135 record_buf
[0] = ARM_PS_REGNUM
;
10136 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10137 arm_insn_r
->reg_rec_count
= 2;
10139 else if (7 == bits (arm_insn_r
->arm_insn
, 4, 7))
10142 record_buf
[0] = ARM_PS_REGNUM
;
10143 record_buf
[1] = ARM_LR_REGNUM
;
10144 arm_insn_r
->reg_rec_count
= 2;
10146 /* Save SPSR also;how? */
10149 else if(8 == bits (arm_insn_r
->arm_insn
, 4, 7)
10150 || 10 == bits (arm_insn_r
->arm_insn
, 4, 7)
10151 || 12 == bits (arm_insn_r
->arm_insn
, 4, 7)
10152 || 14 == bits (arm_insn_r
->arm_insn
, 4, 7)
10155 if (0 == insn_op1
|| 1 == insn_op1
)
10157 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
10158 /* We dont do optimization for SMULW<y> where we
10160 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10161 record_buf
[1] = ARM_PS_REGNUM
;
10162 arm_insn_r
->reg_rec_count
= 2;
10164 else if (2 == insn_op1
)
10167 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10168 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
10169 arm_insn_r
->reg_rec_count
= 2;
10171 else if (3 == insn_op1
)
10174 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10175 arm_insn_r
->reg_rec_count
= 1;
10181 /* MSR : immediate form. */
10184 /* CSPR is going to be changed. */
10185 record_buf
[0] = ARM_PS_REGNUM
;
10186 arm_insn_r
->reg_rec_count
= 1;
10188 else if (3 == insn_op1
)
10190 /* SPSR is going to be changed. */
10191 /* we need to get SPSR value, which is yet to be done */
10197 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10198 opcode2
= bits (arm_insn_r
->arm_insn
, 20, 24);
10199 insn_op1
= bits (arm_insn_r
->arm_insn
, 5, 6);
10201 /* Handle load/store insn extension space. */
10203 if (!opcode1
&& bit (arm_insn_r
->arm_insn
, 7)
10204 && bit (arm_insn_r
->arm_insn
, 4) && 1 != arm_insn_r
->cond
10205 && !INSN_RECORDED(arm_insn_r
))
10210 /* These insn, changes register and memory as well. */
10211 /* SWP or SWPB insn. */
10212 /* Get memory address given by Rn. */
10213 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10214 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
10215 /* SWP insn ?, swaps word. */
10216 if (8 == arm_insn_r
->opcode
)
10218 record_buf_mem
[0] = 4;
10222 /* SWPB insn, swaps only byte. */
10223 record_buf_mem
[0] = 1;
10225 record_buf_mem
[1] = u_regval
;
10226 arm_insn_r
->mem_rec_count
= 1;
10227 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10228 arm_insn_r
->reg_rec_count
= 1;
10230 else if (1 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10233 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10236 else if (2 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10239 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10240 record_buf
[1] = record_buf
[0] + 1;
10241 arm_insn_r
->reg_rec_count
= 2;
10243 else if (3 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10246 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10249 else if (bit (arm_insn_r
->arm_insn
, 20) && insn_op1
<= 3)
10251 /* LDRH, LDRSB, LDRSH. */
10252 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10253 arm_insn_r
->reg_rec_count
= 1;
10258 opcode1
= bits (arm_insn_r
->arm_insn
, 23, 27);
10259 if (24 == opcode1
&& bit (arm_insn_r
->arm_insn
, 21)
10260 && !INSN_RECORDED(arm_insn_r
))
10263 /* Handle coprocessor insn extension space. */
10266 /* To be done for ARMv5 and later; as of now we return -1. */
10270 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10271 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10276 /* Handling opcode 000 insns. */
10279 arm_record_data_proc_misc_ld_str (insn_decode_record
*arm_insn_r
)
10281 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10282 uint32_t record_buf
[8], record_buf_mem
[8];
10283 ULONGEST u_regval
[2] = {0};
10285 uint32_t reg_src1
= 0, reg_dest
= 0;
10286 uint32_t opcode1
= 0;
10288 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10289 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10290 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
10292 /* Data processing insn /multiply insn. */
10293 if (9 == arm_insn_r
->decode
10294 && ((4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
10295 || (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)))
10297 /* Handle multiply instructions. */
10298 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
10299 if (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)
10301 /* Handle MLA and MUL. */
10302 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10303 record_buf
[1] = ARM_PS_REGNUM
;
10304 arm_insn_r
->reg_rec_count
= 2;
10306 else if (4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
10308 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
10309 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10310 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10311 record_buf
[2] = ARM_PS_REGNUM
;
10312 arm_insn_r
->reg_rec_count
= 3;
10315 else if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
10316 && (11 == arm_insn_r
->decode
|| 13 == arm_insn_r
->decode
))
10318 /* Handle misc load insns, as 20th bit (L = 1). */
10319 /* LDR insn has a capability to do branching, if
10320 MOV LR, PC is precceded by LDR insn having Rn as R15
10321 in that case, it emulates branch and link insn, and hence we
10322 need to save CSPR and PC as well. I am not sure this is right
10323 place; as opcode = 010 LDR insn make this happen, if R15 was
10325 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10326 if (15 != reg_dest
)
10328 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10329 arm_insn_r
->reg_rec_count
= 1;
10333 record_buf
[0] = reg_dest
;
10334 record_buf
[1] = ARM_PS_REGNUM
;
10335 arm_insn_r
->reg_rec_count
= 2;
10338 else if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
10339 && sbo_sbz (arm_insn_r
->arm_insn
, 5, 12, 0)
10340 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
10341 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21))
10343 /* Handle MSR insn. */
10344 if (9 == arm_insn_r
->opcode
)
10346 /* CSPR is going to be changed. */
10347 record_buf
[0] = ARM_PS_REGNUM
;
10348 arm_insn_r
->reg_rec_count
= 1;
10352 /* SPSR is going to be changed. */
10353 /* How to read SPSR value? */
10357 else if (9 == arm_insn_r
->decode
10358 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10359 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10361 /* Handling SWP, SWPB. */
10362 /* These insn, changes register and memory as well. */
10363 /* SWP or SWPB insn. */
10365 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10366 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10367 /* SWP insn ?, swaps word. */
10368 if (8 == arm_insn_r
->opcode
)
10370 record_buf_mem
[0] = 4;
10374 /* SWPB insn, swaps only byte. */
10375 record_buf_mem
[0] = 1;
10377 record_buf_mem
[1] = u_regval
[0];
10378 arm_insn_r
->mem_rec_count
= 1;
10379 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10380 arm_insn_r
->reg_rec_count
= 1;
10382 else if (3 == arm_insn_r
->decode
&& 0x12 == opcode1
10383 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10385 /* Handle BLX, branch and link/exchange. */
10386 if (9 == arm_insn_r
->opcode
)
10388 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
10389 and R14 stores the return address. */
10390 record_buf
[0] = ARM_PS_REGNUM
;
10391 record_buf
[1] = ARM_LR_REGNUM
;
10392 arm_insn_r
->reg_rec_count
= 2;
10395 else if (7 == arm_insn_r
->decode
&& 0x12 == opcode1
)
10397 /* Handle enhanced software breakpoint insn, BKPT. */
10398 /* CPSR is changed to be executed in ARM state, disabling normal
10399 interrupts, entering abort mode. */
10400 /* According to high vector configuration PC is set. */
10401 /* user hit breakpoint and type reverse, in
10402 that case, we need to go back with previous CPSR and
10403 Program Counter. */
10404 record_buf
[0] = ARM_PS_REGNUM
;
10405 record_buf
[1] = ARM_LR_REGNUM
;
10406 arm_insn_r
->reg_rec_count
= 2;
10408 /* Save SPSR also; how? */
10411 else if (11 == arm_insn_r
->decode
10412 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10414 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
10416 /* Handle str(x) insn */
10417 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10420 else if (1 == arm_insn_r
->decode
&& 0x12 == opcode1
10421 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10423 /* Handle BX, branch and link/exchange. */
10424 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
10425 record_buf
[0] = ARM_PS_REGNUM
;
10426 arm_insn_r
->reg_rec_count
= 1;
10428 else if (1 == arm_insn_r
->decode
&& 0x16 == opcode1
10429 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 4, 1)
10430 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1))
10432 /* Count leading zeros: CLZ. */
10433 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10434 arm_insn_r
->reg_rec_count
= 1;
10436 else if (!bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
10437 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10438 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1)
10439 && sbo_sbz (arm_insn_r
->arm_insn
, 1, 12, 0)
10442 /* Handle MRS insn. */
10443 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10444 arm_insn_r
->reg_rec_count
= 1;
10446 else if (arm_insn_r
->opcode
<= 15)
10448 /* Normal data processing insns. */
10449 /* Out of 11 shifter operands mode, all the insn modifies destination
10450 register, which is specified by 13-16 decode. */
10451 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10452 record_buf
[1] = ARM_PS_REGNUM
;
10453 arm_insn_r
->reg_rec_count
= 2;
10460 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10461 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10465 /* Handling opcode 001 insns. */
10468 arm_record_data_proc_imm (insn_decode_record
*arm_insn_r
)
10470 uint32_t record_buf
[8], record_buf_mem
[8];
10472 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10473 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10475 if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
10476 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21)
10477 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
10480 /* Handle MSR insn. */
10481 if (9 == arm_insn_r
->opcode
)
10483 /* CSPR is going to be changed. */
10484 record_buf
[0] = ARM_PS_REGNUM
;
10485 arm_insn_r
->reg_rec_count
= 1;
10489 /* SPSR is going to be changed. */
10492 else if (arm_insn_r
->opcode
<= 15)
10494 /* Normal data processing insns. */
10495 /* Out of 11 shifter operands mode, all the insn modifies destination
10496 register, which is specified by 13-16 decode. */
10497 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10498 record_buf
[1] = ARM_PS_REGNUM
;
10499 arm_insn_r
->reg_rec_count
= 2;
10506 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10507 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10512 arm_record_media (insn_decode_record
*arm_insn_r
)
10514 uint32_t record_buf
[8];
10516 switch (bits (arm_insn_r
->arm_insn
, 22, 24))
10519 /* Parallel addition and subtraction, signed */
10521 /* Parallel addition and subtraction, unsigned */
10524 /* Packing, unpacking, saturation and reversal */
10526 int rd
= bits (arm_insn_r
->arm_insn
, 12, 15);
10528 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10534 /* Signed multiplies */
10536 int rd
= bits (arm_insn_r
->arm_insn
, 16, 19);
10537 unsigned int op1
= bits (arm_insn_r
->arm_insn
, 20, 22);
10539 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10541 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10542 else if (op1
== 0x4)
10543 record_buf
[arm_insn_r
->reg_rec_count
++]
10544 = bits (arm_insn_r
->arm_insn
, 12, 15);
10550 if (bit (arm_insn_r
->arm_insn
, 21)
10551 && bits (arm_insn_r
->arm_insn
, 5, 6) == 0x2)
10554 record_buf
[arm_insn_r
->reg_rec_count
++]
10555 = bits (arm_insn_r
->arm_insn
, 12, 15);
10557 else if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x0
10558 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x0)
10560 /* USAD8 and USADA8 */
10561 record_buf
[arm_insn_r
->reg_rec_count
++]
10562 = bits (arm_insn_r
->arm_insn
, 16, 19);
10569 if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x3
10570 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x7)
10572 /* Permanently UNDEFINED */
10577 /* BFC, BFI and UBFX */
10578 record_buf
[arm_insn_r
->reg_rec_count
++]
10579 = bits (arm_insn_r
->arm_insn
, 12, 15);
10588 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10593 /* Handle ARM mode instructions with opcode 010. */
10596 arm_record_ld_st_imm_offset (insn_decode_record
*arm_insn_r
)
10598 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10600 uint32_t reg_base
, reg_dest
;
10601 uint32_t offset_12
, tgt_mem_addr
;
10602 uint32_t record_buf
[8], record_buf_mem
[8];
10603 unsigned char wback
;
10606 /* Calculate wback. */
10607 wback
= (bit (arm_insn_r
->arm_insn
, 24) == 0)
10608 || (bit (arm_insn_r
->arm_insn
, 21) == 1);
10610 arm_insn_r
->reg_rec_count
= 0;
10611 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
10613 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10615 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
10618 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10619 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_dest
;
10621 /* The LDR instruction is capable of doing branching. If MOV LR, PC
10622 preceeds a LDR instruction having R15 as reg_base, it
10623 emulates a branch and link instruction, and hence we need to save
10624 CPSR and PC as well. */
10625 if (ARM_PC_REGNUM
== reg_dest
)
10626 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10628 /* If wback is true, also save the base register, which is going to be
10631 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10635 /* STR (immediate), STRB (immediate), STRBT and STRT. */
10637 offset_12
= bits (arm_insn_r
->arm_insn
, 0, 11);
10638 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
10640 /* Handle bit U. */
10641 if (bit (arm_insn_r
->arm_insn
, 23))
10643 /* U == 1: Add the offset. */
10644 tgt_mem_addr
= (uint32_t) u_regval
+ offset_12
;
10648 /* U == 0: subtract the offset. */
10649 tgt_mem_addr
= (uint32_t) u_regval
- offset_12
;
10652 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
10654 if (bit (arm_insn_r
->arm_insn
, 22))
10656 /* STRB and STRBT: 1 byte. */
10657 record_buf_mem
[0] = 1;
10661 /* STR and STRT: 4 bytes. */
10662 record_buf_mem
[0] = 4;
10665 /* Handle bit P. */
10666 if (bit (arm_insn_r
->arm_insn
, 24))
10667 record_buf_mem
[1] = tgt_mem_addr
;
10669 record_buf_mem
[1] = (uint32_t) u_regval
;
10671 arm_insn_r
->mem_rec_count
= 1;
10673 /* If wback is true, also save the base register, which is going to be
10676 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10679 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10680 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10684 /* Handling opcode 011 insns. */
10687 arm_record_ld_st_reg_offset (insn_decode_record
*arm_insn_r
)
10689 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10691 uint32_t shift_imm
= 0;
10692 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
10693 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
10694 uint32_t record_buf
[8], record_buf_mem
[8];
10697 ULONGEST u_regval
[2];
10699 if (bit (arm_insn_r
->arm_insn
, 4))
10700 return arm_record_media (arm_insn_r
);
10702 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10703 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10705 /* Handle enhanced store insns and LDRD DSP insn,
10706 order begins according to addressing modes for store insns
10710 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10712 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10713 /* LDR insn has a capability to do branching, if
10714 MOV LR, PC is precedded by LDR insn having Rn as R15
10715 in that case, it emulates branch and link insn, and hence we
10716 need to save CSPR and PC as well. */
10717 if (15 != reg_dest
)
10719 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10720 arm_insn_r
->reg_rec_count
= 1;
10724 record_buf
[0] = reg_dest
;
10725 record_buf
[1] = ARM_PS_REGNUM
;
10726 arm_insn_r
->reg_rec_count
= 2;
10731 if (! bits (arm_insn_r
->arm_insn
, 4, 11))
10733 /* Store insn, register offset and register pre-indexed,
10734 register post-indexed. */
10736 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10738 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10739 regcache_raw_read_unsigned (reg_cache
, reg_src1
10741 regcache_raw_read_unsigned (reg_cache
, reg_src2
10743 if (15 == reg_src2
)
10745 /* If R15 was used as Rn, hence current PC+8. */
10746 /* Pre-indexed mode doesnt reach here ; illegal insn. */
10747 u_regval
[0] = u_regval
[0] + 8;
10749 /* Calculate target store address, Rn +/- Rm, register offset. */
10751 if (bit (arm_insn_r
->arm_insn
, 23))
10753 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10757 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10760 switch (arm_insn_r
->opcode
)
10774 record_buf_mem
[0] = 4;
10789 record_buf_mem
[0] = 1;
10793 gdb_assert_not_reached ("no decoding pattern found");
10796 record_buf_mem
[1] = tgt_mem_addr
;
10797 arm_insn_r
->mem_rec_count
= 1;
10799 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10800 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10801 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10802 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10803 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10804 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10807 /* Rn is going to be changed in pre-indexed mode and
10808 post-indexed mode as well. */
10809 record_buf
[0] = reg_src2
;
10810 arm_insn_r
->reg_rec_count
= 1;
10815 /* Store insn, scaled register offset; scaled pre-indexed. */
10816 offset_12
= bits (arm_insn_r
->arm_insn
, 5, 6);
10818 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10820 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10821 /* Get shift_imm. */
10822 shift_imm
= bits (arm_insn_r
->arm_insn
, 7, 11);
10823 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10824 regcache_raw_read_signed (reg_cache
, reg_src1
, &s_word
);
10825 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10826 /* Offset_12 used as shift. */
10830 /* Offset_12 used as index. */
10831 offset_12
= u_regval
[0] << shift_imm
;
10835 offset_12
= (!shift_imm
)?0:u_regval
[0] >> shift_imm
;
10841 if (bit (u_regval
[0], 31))
10843 offset_12
= 0xFFFFFFFF;
10852 /* This is arithmetic shift. */
10853 offset_12
= s_word
>> shift_imm
;
10860 regcache_raw_read_unsigned (reg_cache
, ARM_PS_REGNUM
,
10862 /* Get C flag value and shift it by 31. */
10863 offset_12
= (((bit (u_regval
[1], 29)) << 31) \
10864 | (u_regval
[0]) >> 1);
10868 offset_12
= (u_regval
[0] >> shift_imm
) \
10870 (sizeof(uint32_t) - shift_imm
));
10875 gdb_assert_not_reached ("no decoding pattern found");
10879 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10881 if (bit (arm_insn_r
->arm_insn
, 23))
10883 tgt_mem_addr
= u_regval
[1] + offset_12
;
10887 tgt_mem_addr
= u_regval
[1] - offset_12
;
10890 switch (arm_insn_r
->opcode
)
10904 record_buf_mem
[0] = 4;
10919 record_buf_mem
[0] = 1;
10923 gdb_assert_not_reached ("no decoding pattern found");
10926 record_buf_mem
[1] = tgt_mem_addr
;
10927 arm_insn_r
->mem_rec_count
= 1;
10929 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10930 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10931 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10932 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10933 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10934 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10937 /* Rn is going to be changed in register scaled pre-indexed
10938 mode,and scaled post indexed mode. */
10939 record_buf
[0] = reg_src2
;
10940 arm_insn_r
->reg_rec_count
= 1;
10945 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10946 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10950 /* Handle ARM mode instructions with opcode 100. */
10953 arm_record_ld_st_multiple (insn_decode_record
*arm_insn_r
)
10955 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10956 uint32_t register_count
= 0, register_bits
;
10957 uint32_t reg_base
, addr_mode
;
10958 uint32_t record_buf
[24], record_buf_mem
[48];
10962 /* Fetch the list of registers. */
10963 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
10964 arm_insn_r
->reg_rec_count
= 0;
10966 /* Fetch the base register that contains the address we are loading data
10968 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
10970 /* Calculate wback. */
10971 wback
= (bit (arm_insn_r
->arm_insn
, 21) == 1);
10973 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10975 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
10977 /* Find out which registers are going to be loaded from memory. */
10978 while (register_bits
)
10980 if (register_bits
& 0x00000001)
10981 record_buf
[arm_insn_r
->reg_rec_count
++] = register_count
;
10982 register_bits
= register_bits
>> 1;
10987 /* If wback is true, also save the base register, which is going to be
10990 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10992 /* Save the CPSR register. */
10993 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10997 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
10999 addr_mode
= bits (arm_insn_r
->arm_insn
, 23, 24);
11001 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
11003 /* Find out how many registers are going to be stored to memory. */
11004 while (register_bits
)
11006 if (register_bits
& 0x00000001)
11008 register_bits
= register_bits
>> 1;
11013 /* STMDA (STMED): Decrement after. */
11015 record_buf_mem
[1] = (uint32_t) u_regval
11016 - register_count
* INT_REGISTER_SIZE
+ 4;
11018 /* STM (STMIA, STMEA): Increment after. */
11020 record_buf_mem
[1] = (uint32_t) u_regval
;
11022 /* STMDB (STMFD): Decrement before. */
11024 record_buf_mem
[1] = (uint32_t) u_regval
11025 - register_count
* INT_REGISTER_SIZE
;
11027 /* STMIB (STMFA): Increment before. */
11029 record_buf_mem
[1] = (uint32_t) u_regval
+ INT_REGISTER_SIZE
;
11032 gdb_assert_not_reached ("no decoding pattern found");
11036 record_buf_mem
[0] = register_count
* INT_REGISTER_SIZE
;
11037 arm_insn_r
->mem_rec_count
= 1;
11039 /* If wback is true, also save the base register, which is going to be
11042 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11045 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11046 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11050 /* Handling opcode 101 insns. */
11053 arm_record_b_bl (insn_decode_record
*arm_insn_r
)
11055 uint32_t record_buf
[8];
11057 /* Handle B, BL, BLX(1) insns. */
11058 /* B simply branches so we do nothing here. */
11059 /* Note: BLX(1) doesnt fall here but instead it falls into
11060 extension space. */
11061 if (bit (arm_insn_r
->arm_insn
, 24))
11063 record_buf
[0] = ARM_LR_REGNUM
;
11064 arm_insn_r
->reg_rec_count
= 1;
11067 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11073 arm_record_unsupported_insn (insn_decode_record
*arm_insn_r
)
11075 printf_unfiltered (_("Process record does not support instruction "
11076 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11077 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11082 /* Record handler for vector data transfer instructions. */
11085 arm_record_vdata_transfer_insn (insn_decode_record
*arm_insn_r
)
11087 uint32_t bits_a
, bit_c
, bit_l
, reg_t
, reg_v
;
11088 uint32_t record_buf
[4];
11090 reg_t
= bits (arm_insn_r
->arm_insn
, 12, 15);
11091 reg_v
= bits (arm_insn_r
->arm_insn
, 21, 23);
11092 bits_a
= bits (arm_insn_r
->arm_insn
, 21, 23);
11093 bit_l
= bit (arm_insn_r
->arm_insn
, 20);
11094 bit_c
= bit (arm_insn_r
->arm_insn
, 8);
11096 /* Handle VMOV instruction. */
11097 if (bit_l
&& bit_c
)
11099 record_buf
[0] = reg_t
;
11100 arm_insn_r
->reg_rec_count
= 1;
11102 else if (bit_l
&& !bit_c
)
11104 /* Handle VMOV instruction. */
11105 if (bits_a
== 0x00)
11107 record_buf
[0] = reg_t
;
11108 arm_insn_r
->reg_rec_count
= 1;
11110 /* Handle VMRS instruction. */
11111 else if (bits_a
== 0x07)
11114 reg_t
= ARM_PS_REGNUM
;
11116 record_buf
[0] = reg_t
;
11117 arm_insn_r
->reg_rec_count
= 1;
11120 else if (!bit_l
&& !bit_c
)
11122 /* Handle VMOV instruction. */
11123 if (bits_a
== 0x00)
11125 record_buf
[0] = ARM_D0_REGNUM
+ reg_v
;
11127 arm_insn_r
->reg_rec_count
= 1;
11129 /* Handle VMSR instruction. */
11130 else if (bits_a
== 0x07)
11132 record_buf
[0] = ARM_FPSCR_REGNUM
;
11133 arm_insn_r
->reg_rec_count
= 1;
11136 else if (!bit_l
&& bit_c
)
11138 /* Handle VMOV instruction. */
11139 if (!(bits_a
& 0x04))
11141 record_buf
[0] = (reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4))
11143 arm_insn_r
->reg_rec_count
= 1;
11145 /* Handle VDUP instruction. */
11148 if (bit (arm_insn_r
->arm_insn
, 21))
11150 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11151 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11152 record_buf
[1] = reg_v
+ ARM_D0_REGNUM
+ 1;
11153 arm_insn_r
->reg_rec_count
= 2;
11157 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11158 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11159 arm_insn_r
->reg_rec_count
= 1;
11164 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11168 /* Record handler for extension register load/store instructions. */
11171 arm_record_exreg_ld_st_insn (insn_decode_record
*arm_insn_r
)
11173 uint32_t opcode
, single_reg
;
11174 uint8_t op_vldm_vstm
;
11175 uint32_t record_buf
[8], record_buf_mem
[128];
11176 ULONGEST u_regval
= 0;
11178 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11180 opcode
= bits (arm_insn_r
->arm_insn
, 20, 24);
11181 single_reg
= !bit (arm_insn_r
->arm_insn
, 8);
11182 op_vldm_vstm
= opcode
& 0x1b;
11184 /* Handle VMOV instructions. */
11185 if ((opcode
& 0x1e) == 0x04)
11187 if (bit (arm_insn_r
->arm_insn
, 20)) /* to_arm_registers bit 20? */
11189 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11190 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11191 arm_insn_r
->reg_rec_count
= 2;
11195 uint8_t reg_m
= bits (arm_insn_r
->arm_insn
, 0, 3);
11196 uint8_t bit_m
= bit (arm_insn_r
->arm_insn
, 5);
11200 /* The first S register number m is REG_M:M (M is bit 5),
11201 the corresponding D register number is REG_M:M / 2, which
11203 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_D0_REGNUM
+ reg_m
;
11204 /* The second S register number is REG_M:M + 1, the
11205 corresponding D register number is (REG_M:M + 1) / 2.
11206 IOW, if bit M is 1, the first and second S registers
11207 are mapped to different D registers, otherwise, they are
11208 in the same D register. */
11211 record_buf
[arm_insn_r
->reg_rec_count
++]
11212 = ARM_D0_REGNUM
+ reg_m
+ 1;
11217 record_buf
[0] = ((bit_m
<< 4) + reg_m
+ ARM_D0_REGNUM
);
11218 arm_insn_r
->reg_rec_count
= 1;
11222 /* Handle VSTM and VPUSH instructions. */
11223 else if (op_vldm_vstm
== 0x08 || op_vldm_vstm
== 0x0a
11224 || op_vldm_vstm
== 0x12)
11226 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
11227 uint32_t memory_index
= 0;
11229 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11230 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11231 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11232 imm_off32
= imm_off8
<< 2;
11233 memory_count
= imm_off8
;
11235 if (bit (arm_insn_r
->arm_insn
, 23))
11236 start_address
= u_regval
;
11238 start_address
= u_regval
- imm_off32
;
11240 if (bit (arm_insn_r
->arm_insn
, 21))
11242 record_buf
[0] = reg_rn
;
11243 arm_insn_r
->reg_rec_count
= 1;
11246 while (memory_count
> 0)
11250 record_buf_mem
[memory_index
] = 4;
11251 record_buf_mem
[memory_index
+ 1] = start_address
;
11252 start_address
= start_address
+ 4;
11253 memory_index
= memory_index
+ 2;
11257 record_buf_mem
[memory_index
] = 4;
11258 record_buf_mem
[memory_index
+ 1] = start_address
;
11259 record_buf_mem
[memory_index
+ 2] = 4;
11260 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11261 start_address
= start_address
+ 8;
11262 memory_index
= memory_index
+ 4;
11266 arm_insn_r
->mem_rec_count
= (memory_index
>> 1);
11268 /* Handle VLDM instructions. */
11269 else if (op_vldm_vstm
== 0x09 || op_vldm_vstm
== 0x0b
11270 || op_vldm_vstm
== 0x13)
11272 uint32_t reg_count
, reg_vd
;
11273 uint32_t reg_index
= 0;
11274 uint32_t bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11276 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11277 reg_count
= bits (arm_insn_r
->arm_insn
, 0, 7);
11279 /* REG_VD is the first D register number. If the instruction
11280 loads memory to S registers (SINGLE_REG is TRUE), the register
11281 number is (REG_VD << 1 | bit D), so the corresponding D
11282 register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */
11284 reg_vd
= reg_vd
| (bit_d
<< 4);
11286 if (bit (arm_insn_r
->arm_insn
, 21) /* write back */)
11287 record_buf
[reg_index
++] = bits (arm_insn_r
->arm_insn
, 16, 19);
11289 /* If the instruction loads memory to D register, REG_COUNT should
11290 be divided by 2, according to the ARM Architecture Reference
11291 Manual. If the instruction loads memory to S register, divide by
11292 2 as well because two S registers are mapped to D register. */
11293 reg_count
= reg_count
/ 2;
11294 if (single_reg
&& bit_d
)
11296 /* Increase the register count if S register list starts from
11297 an odd number (bit d is one). */
11301 while (reg_count
> 0)
11303 record_buf
[reg_index
++] = ARM_D0_REGNUM
+ reg_vd
+ reg_count
- 1;
11306 arm_insn_r
->reg_rec_count
= reg_index
;
11308 /* VSTR Vector store register. */
11309 else if ((opcode
& 0x13) == 0x10)
11311 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
;
11312 uint32_t memory_index
= 0;
11314 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11315 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11316 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11317 imm_off32
= imm_off8
<< 2;
11319 if (bit (arm_insn_r
->arm_insn
, 23))
11320 start_address
= u_regval
+ imm_off32
;
11322 start_address
= u_regval
- imm_off32
;
11326 record_buf_mem
[memory_index
] = 4;
11327 record_buf_mem
[memory_index
+ 1] = start_address
;
11328 arm_insn_r
->mem_rec_count
= 1;
11332 record_buf_mem
[memory_index
] = 4;
11333 record_buf_mem
[memory_index
+ 1] = start_address
;
11334 record_buf_mem
[memory_index
+ 2] = 4;
11335 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11336 arm_insn_r
->mem_rec_count
= 2;
11339 /* VLDR Vector load register. */
11340 else if ((opcode
& 0x13) == 0x11)
11342 uint32_t reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11346 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
11347 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
;
11351 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
11352 /* Record register D rather than pseudo register S. */
11353 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
/ 2;
11355 arm_insn_r
->reg_rec_count
= 1;
11358 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11359 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11363 /* Record handler for arm/thumb mode VFP data processing instructions. */
11366 arm_record_vfp_data_proc_insn (insn_decode_record
*arm_insn_r
)
11368 uint32_t opc1
, opc2
, opc3
, dp_op_sz
, bit_d
, reg_vd
;
11369 uint32_t record_buf
[4];
11370 enum insn_types
{INSN_T0
, INSN_T1
, INSN_T2
, INSN_T3
, INSN_INV
};
11371 enum insn_types curr_insn_type
= INSN_INV
;
11373 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11374 opc1
= bits (arm_insn_r
->arm_insn
, 20, 23);
11375 opc2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11376 opc3
= bits (arm_insn_r
->arm_insn
, 6, 7);
11377 dp_op_sz
= bit (arm_insn_r
->arm_insn
, 8);
11378 bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11379 opc1
= opc1
& 0x04;
11381 /* Handle VMLA, VMLS. */
11384 if (bit (arm_insn_r
->arm_insn
, 10))
11386 if (bit (arm_insn_r
->arm_insn
, 6))
11387 curr_insn_type
= INSN_T0
;
11389 curr_insn_type
= INSN_T1
;
11394 curr_insn_type
= INSN_T1
;
11396 curr_insn_type
= INSN_T2
;
11399 /* Handle VNMLA, VNMLS, VNMUL. */
11400 else if (opc1
== 0x01)
11403 curr_insn_type
= INSN_T1
;
11405 curr_insn_type
= INSN_T2
;
11408 else if (opc1
== 0x02 && !(opc3
& 0x01))
11410 if (bit (arm_insn_r
->arm_insn
, 10))
11412 if (bit (arm_insn_r
->arm_insn
, 6))
11413 curr_insn_type
= INSN_T0
;
11415 curr_insn_type
= INSN_T1
;
11420 curr_insn_type
= INSN_T1
;
11422 curr_insn_type
= INSN_T2
;
11425 /* Handle VADD, VSUB. */
11426 else if (opc1
== 0x03)
11428 if (!bit (arm_insn_r
->arm_insn
, 9))
11430 if (bit (arm_insn_r
->arm_insn
, 6))
11431 curr_insn_type
= INSN_T0
;
11433 curr_insn_type
= INSN_T1
;
11438 curr_insn_type
= INSN_T1
;
11440 curr_insn_type
= INSN_T2
;
11444 else if (opc1
== 0x0b)
11447 curr_insn_type
= INSN_T1
;
11449 curr_insn_type
= INSN_T2
;
11451 /* Handle all other vfp data processing instructions. */
11452 else if (opc1
== 0x0b)
11455 if (!(opc3
& 0x01) || (opc2
== 0x00 && opc3
== 0x01))
11457 if (bit (arm_insn_r
->arm_insn
, 4))
11459 if (bit (arm_insn_r
->arm_insn
, 6))
11460 curr_insn_type
= INSN_T0
;
11462 curr_insn_type
= INSN_T1
;
11467 curr_insn_type
= INSN_T1
;
11469 curr_insn_type
= INSN_T2
;
11472 /* Handle VNEG and VABS. */
11473 else if ((opc2
== 0x01 && opc3
== 0x01)
11474 || (opc2
== 0x00 && opc3
== 0x03))
11476 if (!bit (arm_insn_r
->arm_insn
, 11))
11478 if (bit (arm_insn_r
->arm_insn
, 6))
11479 curr_insn_type
= INSN_T0
;
11481 curr_insn_type
= INSN_T1
;
11486 curr_insn_type
= INSN_T1
;
11488 curr_insn_type
= INSN_T2
;
11491 /* Handle VSQRT. */
11492 else if (opc2
== 0x01 && opc3
== 0x03)
11495 curr_insn_type
= INSN_T1
;
11497 curr_insn_type
= INSN_T2
;
11500 else if (opc2
== 0x07 && opc3
== 0x03)
11503 curr_insn_type
= INSN_T1
;
11505 curr_insn_type
= INSN_T2
;
11507 else if (opc3
& 0x01)
11510 if ((opc2
== 0x08) || (opc2
& 0x0e) == 0x0c)
11512 if (!bit (arm_insn_r
->arm_insn
, 18))
11513 curr_insn_type
= INSN_T2
;
11517 curr_insn_type
= INSN_T1
;
11519 curr_insn_type
= INSN_T2
;
11523 else if ((opc2
& 0x0e) == 0x0a || (opc2
& 0x0e) == 0x0e)
11526 curr_insn_type
= INSN_T1
;
11528 curr_insn_type
= INSN_T2
;
11530 /* Handle VCVTB, VCVTT. */
11531 else if ((opc2
& 0x0e) == 0x02)
11532 curr_insn_type
= INSN_T2
;
11533 /* Handle VCMP, VCMPE. */
11534 else if ((opc2
& 0x0e) == 0x04)
11535 curr_insn_type
= INSN_T3
;
11539 switch (curr_insn_type
)
11542 reg_vd
= reg_vd
| (bit_d
<< 4);
11543 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11544 record_buf
[1] = reg_vd
+ ARM_D0_REGNUM
+ 1;
11545 arm_insn_r
->reg_rec_count
= 2;
11549 reg_vd
= reg_vd
| (bit_d
<< 4);
11550 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11551 arm_insn_r
->reg_rec_count
= 1;
11555 reg_vd
= (reg_vd
<< 1) | bit_d
;
11556 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11557 arm_insn_r
->reg_rec_count
= 1;
11561 record_buf
[0] = ARM_FPSCR_REGNUM
;
11562 arm_insn_r
->reg_rec_count
= 1;
11566 gdb_assert_not_reached ("no decoding pattern found");
11570 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11574 /* Handling opcode 110 insns. */
11577 arm_record_asimd_vfp_coproc (insn_decode_record
*arm_insn_r
)
11579 uint32_t op1
, op1_ebit
, coproc
;
11581 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11582 op1
= bits (arm_insn_r
->arm_insn
, 20, 25);
11583 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11585 if ((coproc
& 0x0e) == 0x0a)
11587 /* Handle extension register ld/st instructions. */
11589 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11591 /* 64-bit transfers between arm core and extension registers. */
11592 if ((op1
& 0x3e) == 0x04)
11593 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11597 /* Handle coprocessor ld/st instructions. */
11602 return arm_record_unsupported_insn (arm_insn_r
);
11605 return arm_record_unsupported_insn (arm_insn_r
);
11608 /* Move to coprocessor from two arm core registers. */
11610 return arm_record_unsupported_insn (arm_insn_r
);
11612 /* Move to two arm core registers from coprocessor. */
11617 reg_t
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11618 reg_t
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11619 arm_insn_r
->reg_rec_count
= 2;
11621 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, reg_t
);
11625 return arm_record_unsupported_insn (arm_insn_r
);
11628 /* Handling opcode 111 insns. */
11631 arm_record_coproc_data_proc (insn_decode_record
*arm_insn_r
)
11633 uint32_t op
, op1_sbit
, op1_ebit
, coproc
;
11634 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arm_insn_r
->gdbarch
);
11635 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11637 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 24, 27);
11638 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11639 op1_sbit
= bit (arm_insn_r
->arm_insn
, 24);
11640 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11641 op
= bit (arm_insn_r
->arm_insn
, 4);
11643 /* Handle arm SWI/SVC system call instructions. */
11646 if (tdep
->arm_syscall_record
!= NULL
)
11648 ULONGEST svc_operand
, svc_number
;
11650 svc_operand
= (0x00ffffff & arm_insn_r
->arm_insn
);
11652 if (svc_operand
) /* OABI. */
11653 svc_number
= svc_operand
- 0x900000;
11655 regcache_raw_read_unsigned (reg_cache
, 7, &svc_number
);
11657 return tdep
->arm_syscall_record (reg_cache
, svc_number
);
11661 printf_unfiltered (_("no syscall record support\n"));
11666 if ((coproc
& 0x0e) == 0x0a)
11668 /* VFP data-processing instructions. */
11669 if (!op1_sbit
&& !op
)
11670 return arm_record_vfp_data_proc_insn (arm_insn_r
);
11672 /* Advanced SIMD, VFP instructions. */
11673 if (!op1_sbit
&& op
)
11674 return arm_record_vdata_transfer_insn (arm_insn_r
);
11678 /* Coprocessor data operations. */
11679 if (!op1_sbit
&& !op
)
11680 return arm_record_unsupported_insn (arm_insn_r
);
11682 /* Move to Coprocessor from ARM core register. */
11683 if (!op1_sbit
&& !op1_ebit
&& op
)
11684 return arm_record_unsupported_insn (arm_insn_r
);
11686 /* Move to arm core register from coprocessor. */
11687 if (!op1_sbit
&& op1_ebit
&& op
)
11689 uint32_t record_buf
[1];
11691 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11692 if (record_buf
[0] == 15)
11693 record_buf
[0] = ARM_PS_REGNUM
;
11695 arm_insn_r
->reg_rec_count
= 1;
11696 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
,
11702 return arm_record_unsupported_insn (arm_insn_r
);
11705 /* Handling opcode 000 insns. */
11708 thumb_record_shift_add_sub (insn_decode_record
*thumb_insn_r
)
11710 uint32_t record_buf
[8];
11711 uint32_t reg_src1
= 0;
11713 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11715 record_buf
[0] = ARM_PS_REGNUM
;
11716 record_buf
[1] = reg_src1
;
11717 thumb_insn_r
->reg_rec_count
= 2;
11719 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11725 /* Handling opcode 001 insns. */
11728 thumb_record_add_sub_cmp_mov (insn_decode_record
*thumb_insn_r
)
11730 uint32_t record_buf
[8];
11731 uint32_t reg_src1
= 0;
11733 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11735 record_buf
[0] = ARM_PS_REGNUM
;
11736 record_buf
[1] = reg_src1
;
11737 thumb_insn_r
->reg_rec_count
= 2;
11739 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11744 /* Handling opcode 010 insns. */
11747 thumb_record_ld_st_reg_offset (insn_decode_record
*thumb_insn_r
)
11749 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11750 uint32_t record_buf
[8], record_buf_mem
[8];
11752 uint32_t reg_src1
= 0, reg_src2
= 0;
11753 uint32_t opcode1
= 0, opcode2
= 0, opcode3
= 0;
11755 ULONGEST u_regval
[2] = {0};
11757 opcode1
= bits (thumb_insn_r
->arm_insn
, 10, 12);
11759 if (bit (thumb_insn_r
->arm_insn
, 12))
11761 /* Handle load/store register offset. */
11762 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 10);
11763 if (opcode2
>= 12 && opcode2
<= 15)
11765 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
11766 reg_src1
= bits (thumb_insn_r
->arm_insn
,0, 2);
11767 record_buf
[0] = reg_src1
;
11768 thumb_insn_r
->reg_rec_count
= 1;
11770 else if (opcode2
>= 8 && opcode2
<= 10)
11772 /* STR(2), STRB(2), STRH(2) . */
11773 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11774 reg_src2
= bits (thumb_insn_r
->arm_insn
, 6, 8);
11775 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11776 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11778 record_buf_mem
[0] = 4; /* STR (2). */
11779 else if (10 == opcode2
)
11780 record_buf_mem
[0] = 1; /* STRB (2). */
11781 else if (9 == opcode2
)
11782 record_buf_mem
[0] = 2; /* STRH (2). */
11783 record_buf_mem
[1] = u_regval
[0] + u_regval
[1];
11784 thumb_insn_r
->mem_rec_count
= 1;
11787 else if (bit (thumb_insn_r
->arm_insn
, 11))
11789 /* Handle load from literal pool. */
11791 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11792 record_buf
[0] = reg_src1
;
11793 thumb_insn_r
->reg_rec_count
= 1;
11797 opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 9);
11798 opcode3
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11799 if ((3 == opcode2
) && (!opcode3
))
11801 /* Branch with exchange. */
11802 record_buf
[0] = ARM_PS_REGNUM
;
11803 thumb_insn_r
->reg_rec_count
= 1;
11807 /* Format 8; special data processing insns. */
11808 record_buf
[0] = ARM_PS_REGNUM
;
11809 record_buf
[1] = (bit (thumb_insn_r
->arm_insn
, 7) << 3
11810 | bits (thumb_insn_r
->arm_insn
, 0, 2));
11811 thumb_insn_r
->reg_rec_count
= 2;
11816 /* Format 5; data processing insns. */
11817 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11818 if (bit (thumb_insn_r
->arm_insn
, 7))
11820 reg_src1
= reg_src1
+ 8;
11822 record_buf
[0] = ARM_PS_REGNUM
;
11823 record_buf
[1] = reg_src1
;
11824 thumb_insn_r
->reg_rec_count
= 2;
11827 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11828 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11834 /* Handling opcode 001 insns. */
11837 thumb_record_ld_st_imm_offset (insn_decode_record
*thumb_insn_r
)
11839 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11840 uint32_t record_buf
[8], record_buf_mem
[8];
11842 uint32_t reg_src1
= 0;
11843 uint32_t opcode
= 0, immed_5
= 0;
11845 ULONGEST u_regval
= 0;
11847 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11852 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11853 record_buf
[0] = reg_src1
;
11854 thumb_insn_r
->reg_rec_count
= 1;
11859 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11860 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11861 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11862 record_buf_mem
[0] = 4;
11863 record_buf_mem
[1] = u_regval
+ (immed_5
* 4);
11864 thumb_insn_r
->mem_rec_count
= 1;
11867 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11868 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11874 /* Handling opcode 100 insns. */
11877 thumb_record_ld_st_stack (insn_decode_record
*thumb_insn_r
)
11879 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11880 uint32_t record_buf
[8], record_buf_mem
[8];
11882 uint32_t reg_src1
= 0;
11883 uint32_t opcode
= 0, immed_8
= 0, immed_5
= 0;
11885 ULONGEST u_regval
= 0;
11887 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11892 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11893 record_buf
[0] = reg_src1
;
11894 thumb_insn_r
->reg_rec_count
= 1;
11896 else if (1 == opcode
)
11899 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11900 record_buf
[0] = reg_src1
;
11901 thumb_insn_r
->reg_rec_count
= 1;
11903 else if (2 == opcode
)
11906 immed_8
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11907 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
11908 record_buf_mem
[0] = 4;
11909 record_buf_mem
[1] = u_regval
+ (immed_8
* 4);
11910 thumb_insn_r
->mem_rec_count
= 1;
11912 else if (0 == opcode
)
11915 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11916 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11917 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11918 record_buf_mem
[0] = 2;
11919 record_buf_mem
[1] = u_regval
+ (immed_5
* 2);
11920 thumb_insn_r
->mem_rec_count
= 1;
11923 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11924 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11930 /* Handling opcode 101 insns. */
11933 thumb_record_misc (insn_decode_record
*thumb_insn_r
)
11935 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11937 uint32_t opcode
= 0, opcode1
= 0, opcode2
= 0;
11938 uint32_t register_bits
= 0, register_count
= 0;
11939 uint32_t index
= 0, start_address
= 0;
11940 uint32_t record_buf
[24], record_buf_mem
[48];
11943 ULONGEST u_regval
= 0;
11945 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11946 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
11947 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 12);
11952 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11953 while (register_bits
)
11955 if (register_bits
& 0x00000001)
11956 record_buf
[index
++] = register_count
;
11957 register_bits
= register_bits
>> 1;
11960 record_buf
[index
++] = ARM_PS_REGNUM
;
11961 record_buf
[index
++] = ARM_SP_REGNUM
;
11962 thumb_insn_r
->reg_rec_count
= index
;
11964 else if (10 == opcode2
)
11967 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11968 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
11969 while (register_bits
)
11971 if (register_bits
& 0x00000001)
11973 register_bits
= register_bits
>> 1;
11975 start_address
= u_regval
- \
11976 (4 * (bit (thumb_insn_r
->arm_insn
, 8) + register_count
));
11977 thumb_insn_r
->mem_rec_count
= register_count
;
11978 while (register_count
)
11980 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11981 record_buf_mem
[(register_count
* 2) - 2] = 4;
11982 start_address
= start_address
+ 4;
11985 record_buf
[0] = ARM_SP_REGNUM
;
11986 thumb_insn_r
->reg_rec_count
= 1;
11988 else if (0x1E == opcode1
)
11991 /* Handle enhanced software breakpoint insn, BKPT. */
11992 /* CPSR is changed to be executed in ARM state, disabling normal
11993 interrupts, entering abort mode. */
11994 /* According to high vector configuration PC is set. */
11995 /* User hits breakpoint and type reverse, in that case, we need to go back with
11996 previous CPSR and Program Counter. */
11997 record_buf
[0] = ARM_PS_REGNUM
;
11998 record_buf
[1] = ARM_LR_REGNUM
;
11999 thumb_insn_r
->reg_rec_count
= 2;
12000 /* We need to save SPSR value, which is not yet done. */
12001 printf_unfiltered (_("Process record does not support instruction "
12002 "0x%0x at address %s.\n"),
12003 thumb_insn_r
->arm_insn
,
12004 paddress (thumb_insn_r
->gdbarch
,
12005 thumb_insn_r
->this_addr
));
12008 else if ((0 == opcode
) || (1 == opcode
))
12010 /* ADD(5), ADD(6). */
12011 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12012 record_buf
[0] = reg_src1
;
12013 thumb_insn_r
->reg_rec_count
= 1;
12015 else if (2 == opcode
)
12017 /* ADD(7), SUB(4). */
12018 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12019 record_buf
[0] = ARM_SP_REGNUM
;
12020 thumb_insn_r
->reg_rec_count
= 1;
12023 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12024 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12030 /* Handling opcode 110 insns. */
12033 thumb_record_ldm_stm_swi (insn_decode_record
*thumb_insn_r
)
12035 struct gdbarch_tdep
*tdep
= gdbarch_tdep (thumb_insn_r
->gdbarch
);
12036 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12038 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
12039 uint32_t reg_src1
= 0;
12040 uint32_t opcode1
= 0, opcode2
= 0, register_bits
= 0, register_count
= 0;
12041 uint32_t index
= 0, start_address
= 0;
12042 uint32_t record_buf
[24], record_buf_mem
[48];
12044 ULONGEST u_regval
= 0;
12046 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12047 opcode2
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12053 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12055 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12056 while (register_bits
)
12058 if (register_bits
& 0x00000001)
12059 record_buf
[index
++] = register_count
;
12060 register_bits
= register_bits
>> 1;
12063 record_buf
[index
++] = reg_src1
;
12064 thumb_insn_r
->reg_rec_count
= index
;
12066 else if (0 == opcode2
)
12068 /* It handles both STMIA. */
12069 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12071 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12072 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12073 while (register_bits
)
12075 if (register_bits
& 0x00000001)
12077 register_bits
= register_bits
>> 1;
12079 start_address
= u_regval
;
12080 thumb_insn_r
->mem_rec_count
= register_count
;
12081 while (register_count
)
12083 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12084 record_buf_mem
[(register_count
* 2) - 2] = 4;
12085 start_address
= start_address
+ 4;
12089 else if (0x1F == opcode1
)
12091 /* Handle arm syscall insn. */
12092 if (tdep
->arm_syscall_record
!= NULL
)
12094 regcache_raw_read_unsigned (reg_cache
, 7, &u_regval
);
12095 ret
= tdep
->arm_syscall_record (reg_cache
, u_regval
);
12099 printf_unfiltered (_("no syscall record support\n"));
12104 /* B (1), conditional branch is automatically taken care in process_record,
12105 as PC is saved there. */
12107 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12108 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12114 /* Handling opcode 111 insns. */
12117 thumb_record_branch (insn_decode_record
*thumb_insn_r
)
12119 uint32_t record_buf
[8];
12120 uint32_t bits_h
= 0;
12122 bits_h
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12124 if (2 == bits_h
|| 3 == bits_h
)
12127 record_buf
[0] = ARM_LR_REGNUM
;
12128 thumb_insn_r
->reg_rec_count
= 1;
12130 else if (1 == bits_h
)
12133 record_buf
[0] = ARM_PS_REGNUM
;
12134 record_buf
[1] = ARM_LR_REGNUM
;
12135 thumb_insn_r
->reg_rec_count
= 2;
12138 /* B(2) is automatically taken care in process_record, as PC is
12141 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12146 /* Handler for thumb2 load/store multiple instructions. */
12149 thumb2_record_ld_st_multiple (insn_decode_record
*thumb2_insn_r
)
12151 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12153 uint32_t reg_rn
, op
;
12154 uint32_t register_bits
= 0, register_count
= 0;
12155 uint32_t index
= 0, start_address
= 0;
12156 uint32_t record_buf
[24], record_buf_mem
[48];
12158 ULONGEST u_regval
= 0;
12160 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12161 op
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12163 if (0 == op
|| 3 == op
)
12165 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12167 /* Handle RFE instruction. */
12168 record_buf
[0] = ARM_PS_REGNUM
;
12169 thumb2_insn_r
->reg_rec_count
= 1;
12173 /* Handle SRS instruction after reading banked SP. */
12174 return arm_record_unsupported_insn (thumb2_insn_r
);
12177 else if (1 == op
|| 2 == op
)
12179 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12181 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
12182 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12183 while (register_bits
)
12185 if (register_bits
& 0x00000001)
12186 record_buf
[index
++] = register_count
;
12189 register_bits
= register_bits
>> 1;
12191 record_buf
[index
++] = reg_rn
;
12192 record_buf
[index
++] = ARM_PS_REGNUM
;
12193 thumb2_insn_r
->reg_rec_count
= index
;
12197 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
12198 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12199 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12200 while (register_bits
)
12202 if (register_bits
& 0x00000001)
12205 register_bits
= register_bits
>> 1;
12210 /* Start address calculation for LDMDB/LDMEA. */
12211 start_address
= u_regval
;
12215 /* Start address calculation for LDMDB/LDMEA. */
12216 start_address
= u_regval
- register_count
* 4;
12219 thumb2_insn_r
->mem_rec_count
= register_count
;
12220 while (register_count
)
12222 record_buf_mem
[register_count
* 2 - 1] = start_address
;
12223 record_buf_mem
[register_count
* 2 - 2] = 4;
12224 start_address
= start_address
+ 4;
12227 record_buf
[0] = reg_rn
;
12228 record_buf
[1] = ARM_PS_REGNUM
;
12229 thumb2_insn_r
->reg_rec_count
= 2;
12233 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12235 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12237 return ARM_RECORD_SUCCESS
;
12240 /* Handler for thumb2 load/store (dual/exclusive) and table branch
12244 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record
*thumb2_insn_r
)
12246 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12248 uint32_t reg_rd
, reg_rn
, offset_imm
;
12249 uint32_t reg_dest1
, reg_dest2
;
12250 uint32_t address
, offset_addr
;
12251 uint32_t record_buf
[8], record_buf_mem
[8];
12252 uint32_t op1
, op2
, op3
;
12254 ULONGEST u_regval
[2];
12256 op1
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12257 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 21);
12258 op3
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12260 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12262 if(!(1 == op1
&& 1 == op2
&& (0 == op3
|| 1 == op3
)))
12264 reg_dest1
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12265 record_buf
[0] = reg_dest1
;
12266 record_buf
[1] = ARM_PS_REGNUM
;
12267 thumb2_insn_r
->reg_rec_count
= 2;
12270 if (3 == op2
|| (op1
& 2) || (1 == op1
&& 1 == op2
&& 7 == op3
))
12272 reg_dest2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12273 record_buf
[2] = reg_dest2
;
12274 thumb2_insn_r
->reg_rec_count
= 3;
12279 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12280 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12282 if (0 == op1
&& 0 == op2
)
12284 /* Handle STREX. */
12285 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12286 address
= u_regval
[0] + (offset_imm
* 4);
12287 record_buf_mem
[0] = 4;
12288 record_buf_mem
[1] = address
;
12289 thumb2_insn_r
->mem_rec_count
= 1;
12290 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12291 record_buf
[0] = reg_rd
;
12292 thumb2_insn_r
->reg_rec_count
= 1;
12294 else if (1 == op1
&& 0 == op2
)
12296 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12297 record_buf
[0] = reg_rd
;
12298 thumb2_insn_r
->reg_rec_count
= 1;
12299 address
= u_regval
[0];
12300 record_buf_mem
[1] = address
;
12304 /* Handle STREXB. */
12305 record_buf_mem
[0] = 1;
12306 thumb2_insn_r
->mem_rec_count
= 1;
12310 /* Handle STREXH. */
12311 record_buf_mem
[0] = 2 ;
12312 thumb2_insn_r
->mem_rec_count
= 1;
12316 /* Handle STREXD. */
12317 address
= u_regval
[0];
12318 record_buf_mem
[0] = 4;
12319 record_buf_mem
[2] = 4;
12320 record_buf_mem
[3] = address
+ 4;
12321 thumb2_insn_r
->mem_rec_count
= 2;
12326 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12328 if (bit (thumb2_insn_r
->arm_insn
, 24))
12330 if (bit (thumb2_insn_r
->arm_insn
, 23))
12331 offset_addr
= u_regval
[0] + (offset_imm
* 4);
12333 offset_addr
= u_regval
[0] - (offset_imm
* 4);
12335 address
= offset_addr
;
12338 address
= u_regval
[0];
12340 record_buf_mem
[0] = 4;
12341 record_buf_mem
[1] = address
;
12342 record_buf_mem
[2] = 4;
12343 record_buf_mem
[3] = address
+ 4;
12344 thumb2_insn_r
->mem_rec_count
= 2;
12345 record_buf
[0] = reg_rn
;
12346 thumb2_insn_r
->reg_rec_count
= 1;
12350 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12352 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12354 return ARM_RECORD_SUCCESS
;
12357 /* Handler for thumb2 data processing (shift register and modified immediate)
12361 thumb2_record_data_proc_sreg_mimm (insn_decode_record
*thumb2_insn_r
)
12363 uint32_t reg_rd
, op
;
12364 uint32_t record_buf
[8];
12366 op
= bits (thumb2_insn_r
->arm_insn
, 21, 24);
12367 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12369 if ((0 == op
|| 4 == op
|| 8 == op
|| 13 == op
) && 15 == reg_rd
)
12371 record_buf
[0] = ARM_PS_REGNUM
;
12372 thumb2_insn_r
->reg_rec_count
= 1;
12376 record_buf
[0] = reg_rd
;
12377 record_buf
[1] = ARM_PS_REGNUM
;
12378 thumb2_insn_r
->reg_rec_count
= 2;
12381 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12383 return ARM_RECORD_SUCCESS
;
12386 /* Generic handler for thumb2 instructions which effect destination and PS
12390 thumb2_record_ps_dest_generic (insn_decode_record
*thumb2_insn_r
)
12393 uint32_t record_buf
[8];
12395 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12397 record_buf
[0] = reg_rd
;
12398 record_buf
[1] = ARM_PS_REGNUM
;
12399 thumb2_insn_r
->reg_rec_count
= 2;
12401 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12403 return ARM_RECORD_SUCCESS
;
12406 /* Handler for thumb2 branch and miscellaneous control instructions. */
12409 thumb2_record_branch_misc_cntrl (insn_decode_record
*thumb2_insn_r
)
12411 uint32_t op
, op1
, op2
;
12412 uint32_t record_buf
[8];
12414 op
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12415 op1
= bits (thumb2_insn_r
->arm_insn
, 12, 14);
12416 op2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12418 /* Handle MSR insn. */
12419 if (!(op1
& 0x2) && 0x38 == op
)
12423 /* CPSR is going to be changed. */
12424 record_buf
[0] = ARM_PS_REGNUM
;
12425 thumb2_insn_r
->reg_rec_count
= 1;
12429 arm_record_unsupported_insn(thumb2_insn_r
);
12433 else if (4 == (op1
& 0x5) || 5 == (op1
& 0x5))
12436 record_buf
[0] = ARM_PS_REGNUM
;
12437 record_buf
[1] = ARM_LR_REGNUM
;
12438 thumb2_insn_r
->reg_rec_count
= 2;
12441 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12443 return ARM_RECORD_SUCCESS
;
12446 /* Handler for thumb2 store single data item instructions. */
12449 thumb2_record_str_single_data (insn_decode_record
*thumb2_insn_r
)
12451 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12453 uint32_t reg_rn
, reg_rm
, offset_imm
, shift_imm
;
12454 uint32_t address
, offset_addr
;
12455 uint32_t record_buf
[8], record_buf_mem
[8];
12458 ULONGEST u_regval
[2];
12460 op1
= bits (thumb2_insn_r
->arm_insn
, 21, 23);
12461 op2
= bits (thumb2_insn_r
->arm_insn
, 6, 11);
12462 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12463 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12465 if (bit (thumb2_insn_r
->arm_insn
, 23))
12468 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 11);
12469 offset_addr
= u_regval
[0] + offset_imm
;
12470 address
= offset_addr
;
12475 if ((0 == op1
|| 1 == op1
|| 2 == op1
) && !(op2
& 0x20))
12477 /* Handle STRB (register). */
12478 reg_rm
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12479 regcache_raw_read_unsigned (reg_cache
, reg_rm
, &u_regval
[1]);
12480 shift_imm
= bits (thumb2_insn_r
->arm_insn
, 4, 5);
12481 offset_addr
= u_regval
[1] << shift_imm
;
12482 address
= u_regval
[0] + offset_addr
;
12486 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12487 if (bit (thumb2_insn_r
->arm_insn
, 10))
12489 if (bit (thumb2_insn_r
->arm_insn
, 9))
12490 offset_addr
= u_regval
[0] + offset_imm
;
12492 offset_addr
= u_regval
[0] - offset_imm
;
12494 address
= offset_addr
;
12497 address
= u_regval
[0];
12503 /* Store byte instructions. */
12506 record_buf_mem
[0] = 1;
12508 /* Store half word instructions. */
12511 record_buf_mem
[0] = 2;
12513 /* Store word instructions. */
12516 record_buf_mem
[0] = 4;
12520 gdb_assert_not_reached ("no decoding pattern found");
12524 record_buf_mem
[1] = address
;
12525 thumb2_insn_r
->mem_rec_count
= 1;
12526 record_buf
[0] = reg_rn
;
12527 thumb2_insn_r
->reg_rec_count
= 1;
12529 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12531 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12533 return ARM_RECORD_SUCCESS
;
12536 /* Handler for thumb2 load memory hints instructions. */
12539 thumb2_record_ld_mem_hints (insn_decode_record
*thumb2_insn_r
)
12541 uint32_t record_buf
[8];
12542 uint32_t reg_rt
, reg_rn
;
12544 reg_rt
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12545 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12547 if (ARM_PC_REGNUM
!= reg_rt
)
12549 record_buf
[0] = reg_rt
;
12550 record_buf
[1] = reg_rn
;
12551 record_buf
[2] = ARM_PS_REGNUM
;
12552 thumb2_insn_r
->reg_rec_count
= 3;
12554 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12556 return ARM_RECORD_SUCCESS
;
12559 return ARM_RECORD_FAILURE
;
12562 /* Handler for thumb2 load word instructions. */
12565 thumb2_record_ld_word (insn_decode_record
*thumb2_insn_r
)
12567 uint32_t record_buf
[8];
12569 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12570 record_buf
[1] = ARM_PS_REGNUM
;
12571 thumb2_insn_r
->reg_rec_count
= 2;
12573 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12575 return ARM_RECORD_SUCCESS
;
12578 /* Handler for thumb2 long multiply, long multiply accumulate, and
12579 divide instructions. */
12582 thumb2_record_lmul_lmla_div (insn_decode_record
*thumb2_insn_r
)
12584 uint32_t opcode1
= 0, opcode2
= 0;
12585 uint32_t record_buf
[8];
12587 opcode1
= bits (thumb2_insn_r
->arm_insn
, 20, 22);
12588 opcode2
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12590 if (0 == opcode1
|| 2 == opcode1
|| (opcode1
>= 4 && opcode1
<= 6))
12592 /* Handle SMULL, UMULL, SMULAL. */
12593 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
12594 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12595 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12596 record_buf
[2] = ARM_PS_REGNUM
;
12597 thumb2_insn_r
->reg_rec_count
= 3;
12599 else if (1 == opcode1
|| 3 == opcode2
)
12601 /* Handle SDIV and UDIV. */
12602 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12603 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12604 record_buf
[2] = ARM_PS_REGNUM
;
12605 thumb2_insn_r
->reg_rec_count
= 3;
12608 return ARM_RECORD_FAILURE
;
12610 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12612 return ARM_RECORD_SUCCESS
;
12615 /* Record handler for thumb32 coprocessor instructions. */
12618 thumb2_record_coproc_insn (insn_decode_record
*thumb2_insn_r
)
12620 if (bit (thumb2_insn_r
->arm_insn
, 25))
12621 return arm_record_coproc_data_proc (thumb2_insn_r
);
12623 return arm_record_asimd_vfp_coproc (thumb2_insn_r
);
12626 /* Record handler for advance SIMD structure load/store instructions. */
12629 thumb2_record_asimd_struct_ld_st (insn_decode_record
*thumb2_insn_r
)
12631 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12632 uint32_t l_bit
, a_bit
, b_bits
;
12633 uint32_t record_buf
[128], record_buf_mem
[128];
12634 uint32_t reg_rn
, reg_vd
, address
, f_elem
;
12635 uint32_t index_r
= 0, index_e
= 0, bf_regs
= 0, index_m
= 0, loop_t
= 0;
12638 l_bit
= bit (thumb2_insn_r
->arm_insn
, 21);
12639 a_bit
= bit (thumb2_insn_r
->arm_insn
, 23);
12640 b_bits
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12641 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12642 reg_vd
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12643 reg_vd
= (bit (thumb2_insn_r
->arm_insn
, 22) << 4) | reg_vd
;
12644 f_ebytes
= (1 << bits (thumb2_insn_r
->arm_insn
, 6, 7));
12645 f_elem
= 8 / f_ebytes
;
12649 ULONGEST u_regval
= 0;
12650 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12651 address
= u_regval
;
12656 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12658 if (b_bits
== 0x07)
12660 else if (b_bits
== 0x0a)
12662 else if (b_bits
== 0x06)
12664 else if (b_bits
== 0x02)
12669 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12671 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12673 record_buf_mem
[index_m
++] = f_ebytes
;
12674 record_buf_mem
[index_m
++] = address
;
12675 address
= address
+ f_ebytes
;
12676 thumb2_insn_r
->mem_rec_count
+= 1;
12681 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12683 if (b_bits
== 0x09 || b_bits
== 0x08)
12685 else if (b_bits
== 0x03)
12690 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12691 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12693 for (loop_t
= 0; loop_t
< 2; loop_t
++)
12695 record_buf_mem
[index_m
++] = f_ebytes
;
12696 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12697 thumb2_insn_r
->mem_rec_count
+= 1;
12699 address
= address
+ (2 * f_ebytes
);
12703 else if ((b_bits
& 0x0e) == 0x04)
12705 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12707 for (loop_t
= 0; loop_t
< 3; loop_t
++)
12709 record_buf_mem
[index_m
++] = f_ebytes
;
12710 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12711 thumb2_insn_r
->mem_rec_count
+= 1;
12713 address
= address
+ (3 * f_ebytes
);
12717 else if (!(b_bits
& 0x0e))
12719 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12721 for (loop_t
= 0; loop_t
< 4; loop_t
++)
12723 record_buf_mem
[index_m
++] = f_ebytes
;
12724 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12725 thumb2_insn_r
->mem_rec_count
+= 1;
12727 address
= address
+ (4 * f_ebytes
);
12733 uint8_t bft_size
= bits (thumb2_insn_r
->arm_insn
, 10, 11);
12735 if (bft_size
== 0x00)
12737 else if (bft_size
== 0x01)
12739 else if (bft_size
== 0x02)
12745 if (!(b_bits
& 0x0b) || b_bits
== 0x08)
12746 thumb2_insn_r
->mem_rec_count
= 1;
12748 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09)
12749 thumb2_insn_r
->mem_rec_count
= 2;
12751 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a)
12752 thumb2_insn_r
->mem_rec_count
= 3;
12754 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b)
12755 thumb2_insn_r
->mem_rec_count
= 4;
12757 for (index_m
= 0; index_m
< thumb2_insn_r
->mem_rec_count
; index_m
++)
12759 record_buf_mem
[index_m
] = f_ebytes
;
12760 record_buf_mem
[index_m
] = address
+ (index_m
* f_ebytes
);
12769 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12770 thumb2_insn_r
->reg_rec_count
= 1;
12772 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12773 thumb2_insn_r
->reg_rec_count
= 2;
12775 else if ((b_bits
& 0x0e) == 0x04)
12776 thumb2_insn_r
->reg_rec_count
= 3;
12778 else if (!(b_bits
& 0x0e))
12779 thumb2_insn_r
->reg_rec_count
= 4;
12784 if (!(b_bits
& 0x0b) || b_bits
== 0x08 || b_bits
== 0x0c)
12785 thumb2_insn_r
->reg_rec_count
= 1;
12787 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09 || b_bits
== 0x0d)
12788 thumb2_insn_r
->reg_rec_count
= 2;
12790 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a || b_bits
== 0x0e)
12791 thumb2_insn_r
->reg_rec_count
= 3;
12793 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b || b_bits
== 0x0f)
12794 thumb2_insn_r
->reg_rec_count
= 4;
12796 for (index_r
= 0; index_r
< thumb2_insn_r
->reg_rec_count
; index_r
++)
12797 record_buf
[index_r
] = reg_vd
+ ARM_D0_REGNUM
+ index_r
;
12801 if (bits (thumb2_insn_r
->arm_insn
, 0, 3) != 15)
12803 record_buf
[index_r
] = reg_rn
;
12804 thumb2_insn_r
->reg_rec_count
+= 1;
12807 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12809 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12814 /* Decodes thumb2 instruction type and invokes its record handler. */
12816 static unsigned int
12817 thumb2_record_decode_insn_handler (insn_decode_record
*thumb2_insn_r
)
12819 uint32_t op
, op1
, op2
;
12821 op
= bit (thumb2_insn_r
->arm_insn
, 15);
12822 op1
= bits (thumb2_insn_r
->arm_insn
, 27, 28);
12823 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12827 if (!(op2
& 0x64 ))
12829 /* Load/store multiple instruction. */
12830 return thumb2_record_ld_st_multiple (thumb2_insn_r
);
12832 else if (!((op2
& 0x64) ^ 0x04))
12834 /* Load/store (dual/exclusive) and table branch instruction. */
12835 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r
);
12837 else if (!((op2
& 0x20) ^ 0x20))
12839 /* Data-processing (shifted register). */
12840 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12842 else if (op2
& 0x40)
12844 /* Co-processor instructions. */
12845 return thumb2_record_coproc_insn (thumb2_insn_r
);
12848 else if (op1
== 0x02)
12852 /* Branches and miscellaneous control instructions. */
12853 return thumb2_record_branch_misc_cntrl (thumb2_insn_r
);
12855 else if (op2
& 0x20)
12857 /* Data-processing (plain binary immediate) instruction. */
12858 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12862 /* Data-processing (modified immediate). */
12863 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12866 else if (op1
== 0x03)
12868 if (!(op2
& 0x71 ))
12870 /* Store single data item. */
12871 return thumb2_record_str_single_data (thumb2_insn_r
);
12873 else if (!((op2
& 0x71) ^ 0x10))
12875 /* Advanced SIMD or structure load/store instructions. */
12876 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r
);
12878 else if (!((op2
& 0x67) ^ 0x01))
12880 /* Load byte, memory hints instruction. */
12881 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
12883 else if (!((op2
& 0x67) ^ 0x03))
12885 /* Load halfword, memory hints instruction. */
12886 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
12888 else if (!((op2
& 0x67) ^ 0x05))
12890 /* Load word instruction. */
12891 return thumb2_record_ld_word (thumb2_insn_r
);
12893 else if (!((op2
& 0x70) ^ 0x20))
12895 /* Data-processing (register) instruction. */
12896 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12898 else if (!((op2
& 0x78) ^ 0x30))
12900 /* Multiply, multiply accumulate, abs diff instruction. */
12901 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12903 else if (!((op2
& 0x78) ^ 0x38))
12905 /* Long multiply, long multiply accumulate, and divide. */
12906 return thumb2_record_lmul_lmla_div (thumb2_insn_r
);
12908 else if (op2
& 0x40)
12910 /* Co-processor instructions. */
12911 return thumb2_record_coproc_insn (thumb2_insn_r
);
12918 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12919 and positive val on fauilure. */
12922 extract_arm_insn (insn_decode_record
*insn_record
, uint32_t insn_size
)
12924 gdb_byte buf
[insn_size
];
12926 memset (&buf
[0], 0, insn_size
);
12928 if (target_read_memory (insn_record
->this_addr
, &buf
[0], insn_size
))
12930 insn_record
->arm_insn
= (uint32_t) extract_unsigned_integer (&buf
[0],
12932 gdbarch_byte_order_for_code (insn_record
->gdbarch
));
12936 typedef int (*sti_arm_hdl_fp_t
) (insn_decode_record
*);
12938 /* Decode arm/thumb insn depending on condition cods and opcodes; and
12942 decode_insn (insn_decode_record
*arm_record
, record_type_t record_type
,
12943 uint32_t insn_size
)
12946 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm
12948 static const sti_arm_hdl_fp_t arm_handle_insn
[8] =
12950 arm_record_data_proc_misc_ld_str
, /* 000. */
12951 arm_record_data_proc_imm
, /* 001. */
12952 arm_record_ld_st_imm_offset
, /* 010. */
12953 arm_record_ld_st_reg_offset
, /* 011. */
12954 arm_record_ld_st_multiple
, /* 100. */
12955 arm_record_b_bl
, /* 101. */
12956 arm_record_asimd_vfp_coproc
, /* 110. */
12957 arm_record_coproc_data_proc
/* 111. */
12960 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb
12962 static const sti_arm_hdl_fp_t thumb_handle_insn
[8] =
12964 thumb_record_shift_add_sub
, /* 000. */
12965 thumb_record_add_sub_cmp_mov
, /* 001. */
12966 thumb_record_ld_st_reg_offset
, /* 010. */
12967 thumb_record_ld_st_imm_offset
, /* 011. */
12968 thumb_record_ld_st_stack
, /* 100. */
12969 thumb_record_misc
, /* 101. */
12970 thumb_record_ldm_stm_swi
, /* 110. */
12971 thumb_record_branch
/* 111. */
12974 uint32_t ret
= 0; /* return value: negative:failure 0:success. */
12975 uint32_t insn_id
= 0;
12977 if (extract_arm_insn (arm_record
, insn_size
))
12981 printf_unfiltered (_("Process record: error reading memory at "
12982 "addr %s len = %d.\n"),
12983 paddress (arm_record
->gdbarch
,
12984 arm_record
->this_addr
), insn_size
);
12988 else if (ARM_RECORD
== record_type
)
12990 arm_record
->cond
= bits (arm_record
->arm_insn
, 28, 31);
12991 insn_id
= bits (arm_record
->arm_insn
, 25, 27);
12993 if (arm_record
->cond
== 0xf)
12994 ret
= arm_record_extension_space (arm_record
);
12997 /* If this insn has fallen into extension space
12998 then we need not decode it anymore. */
12999 ret
= arm_handle_insn
[insn_id
] (arm_record
);
13001 if (ret
!= ARM_RECORD_SUCCESS
)
13003 arm_record_unsupported_insn (arm_record
);
13007 else if (THUMB_RECORD
== record_type
)
13009 /* As thumb does not have condition codes, we set negative. */
13010 arm_record
->cond
= -1;
13011 insn_id
= bits (arm_record
->arm_insn
, 13, 15);
13012 ret
= thumb_handle_insn
[insn_id
] (arm_record
);
13013 if (ret
!= ARM_RECORD_SUCCESS
)
13015 arm_record_unsupported_insn (arm_record
);
13019 else if (THUMB2_RECORD
== record_type
)
13021 /* As thumb does not have condition codes, we set negative. */
13022 arm_record
->cond
= -1;
13024 /* Swap first half of 32bit thumb instruction with second half. */
13025 arm_record
->arm_insn
13026 = (arm_record
->arm_insn
>> 16) | (arm_record
->arm_insn
<< 16);
13028 ret
= thumb2_record_decode_insn_handler (arm_record
);
13030 if (ret
!= ARM_RECORD_SUCCESS
)
13032 arm_record_unsupported_insn (arm_record
);
13038 /* Throw assertion. */
13039 gdb_assert_not_reached ("not a valid instruction, could not decode");
13046 /* Cleans up local record registers and memory allocations. */
13049 deallocate_reg_mem (insn_decode_record
*record
)
13051 xfree (record
->arm_regs
);
13052 xfree (record
->arm_mems
);
13056 /* Parse the current instruction and record the values of the registers and
13057 memory that will be changed in current instruction to record_arch_list".
13058 Return -1 if something is wrong. */
13061 arm_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
13062 CORE_ADDR insn_addr
)
13065 uint32_t no_of_rec
= 0;
13066 uint32_t ret
= 0; /* return value: -1:record failure ; 0:success */
13067 ULONGEST t_bit
= 0, insn_id
= 0;
13069 ULONGEST u_regval
= 0;
13071 insn_decode_record arm_record
;
13073 memset (&arm_record
, 0, sizeof (insn_decode_record
));
13074 arm_record
.regcache
= regcache
;
13075 arm_record
.this_addr
= insn_addr
;
13076 arm_record
.gdbarch
= gdbarch
;
13079 if (record_debug
> 1)
13081 fprintf_unfiltered (gdb_stdlog
, "Process record: arm_process_record "
13083 paddress (gdbarch
, arm_record
.this_addr
));
13086 if (extract_arm_insn (&arm_record
, 2))
13090 printf_unfiltered (_("Process record: error reading memory at "
13091 "addr %s len = %d.\n"),
13092 paddress (arm_record
.gdbarch
,
13093 arm_record
.this_addr
), 2);
13098 /* Check the insn, whether it is thumb or arm one. */
13100 t_bit
= arm_psr_thumb_bit (arm_record
.gdbarch
);
13101 regcache_raw_read_unsigned (arm_record
.regcache
, ARM_PS_REGNUM
, &u_regval
);
13104 if (!(u_regval
& t_bit
))
13106 /* We are decoding arm insn. */
13107 ret
= decode_insn (&arm_record
, ARM_RECORD
, ARM_INSN_SIZE_BYTES
);
13111 insn_id
= bits (arm_record
.arm_insn
, 11, 15);
13112 /* is it thumb2 insn? */
13113 if ((0x1D == insn_id
) || (0x1E == insn_id
) || (0x1F == insn_id
))
13115 ret
= decode_insn (&arm_record
, THUMB2_RECORD
,
13116 THUMB2_INSN_SIZE_BYTES
);
13120 /* We are decoding thumb insn. */
13121 ret
= decode_insn (&arm_record
, THUMB_RECORD
, THUMB_INSN_SIZE_BYTES
);
13127 /* Record registers. */
13128 record_full_arch_list_add_reg (arm_record
.regcache
, ARM_PC_REGNUM
);
13129 if (arm_record
.arm_regs
)
13131 for (no_of_rec
= 0; no_of_rec
< arm_record
.reg_rec_count
; no_of_rec
++)
13133 if (record_full_arch_list_add_reg
13134 (arm_record
.regcache
, arm_record
.arm_regs
[no_of_rec
]))
13138 /* Record memories. */
13139 if (arm_record
.arm_mems
)
13141 for (no_of_rec
= 0; no_of_rec
< arm_record
.mem_rec_count
; no_of_rec
++)
13143 if (record_full_arch_list_add_mem
13144 ((CORE_ADDR
)arm_record
.arm_mems
[no_of_rec
].addr
,
13145 arm_record
.arm_mems
[no_of_rec
].len
))
13150 if (record_full_arch_list_add_end ())
13155 deallocate_reg_mem (&arm_record
);