1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
32 #include "reggroups.h"
33 #include "target-float.h"
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
41 #include "dwarf2-frame.h"
43 #include "prologue-value.h"
45 #include "target-descriptions.h"
46 #include "user-regs.h"
47 #include "observable.h"
50 #include "arch/arm-get-next-pcs.h"
52 #include "gdb/sim-arm.h"
55 #include "coff/internal.h"
61 #include "record-full.h"
64 #include "features/arm/arm-with-m.c"
65 #include "features/arm/arm-with-m-fpa-layout.c"
66 #include "features/arm/arm-with-m-vfp-d16.c"
67 #include "features/arm/arm-with-iwmmxt.c"
68 #include "features/arm/arm-with-vfpv2.c"
69 #include "features/arm/arm-with-vfpv3.c"
70 #include "features/arm/arm-with-neon.c"
78 /* Macros for setting and testing a bit in a minimal symbol that marks
79 it as Thumb function. The MSB of the minimal symbol's "info" field
80 is used for this purpose.
82 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
83 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
85 #define MSYMBOL_SET_SPECIAL(msym) \
86 MSYMBOL_TARGET_FLAG_1 (msym) = 1
88 #define MSYMBOL_IS_SPECIAL(msym) \
89 MSYMBOL_TARGET_FLAG_1 (msym)
91 /* Per-objfile data used for mapping symbols. */
92 static const struct objfile_data
*arm_objfile_data_key
;
94 struct arm_mapping_symbol
99 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
100 DEF_VEC_O(arm_mapping_symbol_s
);
102 struct arm_per_objfile
104 VEC(arm_mapping_symbol_s
) **section_maps
;
107 /* The list of available "set arm ..." and "show arm ..." commands. */
108 static struct cmd_list_element
*setarmcmdlist
= NULL
;
109 static struct cmd_list_element
*showarmcmdlist
= NULL
;
111 /* The type of floating-point to use. Keep this in sync with enum
112 arm_float_model, and the help string in _initialize_arm_tdep. */
113 static const char *const fp_model_strings
[] =
123 /* A variable that can be configured by the user. */
124 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
125 static const char *current_fp_model
= "auto";
127 /* The ABI to use. Keep this in sync with arm_abi_kind. */
128 static const char *const arm_abi_strings
[] =
136 /* A variable that can be configured by the user. */
137 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
138 static const char *arm_abi_string
= "auto";
140 /* The execution mode to assume. */
141 static const char *const arm_mode_strings
[] =
149 static const char *arm_fallback_mode_string
= "auto";
150 static const char *arm_force_mode_string
= "auto";
152 /* The standard register names, and all the valid aliases for them. Note
153 that `fp', `sp' and `pc' are not added in this alias list, because they
154 have been added as builtin user registers in
155 std-regs.c:_initialize_frame_reg. */
160 } arm_register_aliases
[] = {
161 /* Basic register numbers. */
178 /* Synonyms (argument and variable registers). */
191 /* Other platform-specific names for r9. */
197 /* Names used by GCC (not listed in the ARM EABI). */
199 /* A special name from the older ATPCS. */
203 static const char *const arm_register_names
[] =
204 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
205 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
206 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
207 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
208 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
209 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
210 "fps", "cpsr" }; /* 24 25 */
212 /* Holds the current set of options to be passed to the disassembler. */
213 static char *arm_disassembler_options
;
215 /* Valid register name styles. */
216 static const char **valid_disassembly_styles
;
218 /* Disassembly style to use. Default to "std" register names. */
219 static const char *disassembly_style
;
221 /* This is used to keep the bfd arch_info in sync with the disassembly
223 static void set_disassembly_style_sfunc (const char *, int,
224 struct cmd_list_element
*);
225 static void show_disassembly_style_sfunc (struct ui_file
*, int,
226 struct cmd_list_element
*,
229 static enum register_status
arm_neon_quad_read (struct gdbarch
*gdbarch
,
230 readable_regcache
*regcache
,
231 int regnum
, gdb_byte
*buf
);
232 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
233 struct regcache
*regcache
,
234 int regnum
, const gdb_byte
*buf
);
237 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
);
240 /* get_next_pcs operations. */
241 static struct arm_get_next_pcs_ops arm_get_next_pcs_ops
= {
242 arm_get_next_pcs_read_memory_unsigned_integer
,
243 arm_get_next_pcs_syscall_next_pc
,
244 arm_get_next_pcs_addr_bits_remove
,
245 arm_get_next_pcs_is_thumb
,
249 struct arm_prologue_cache
251 /* The stack pointer at the time this frame was created; i.e. the
252 caller's stack pointer when this function was called. It is used
253 to identify this frame. */
256 /* The frame base for this frame is just prev_sp - frame size.
257 FRAMESIZE is the distance from the frame pointer to the
258 initial stack pointer. */
262 /* The register used to hold the frame pointer for this frame. */
265 /* Saved register offsets. */
266 struct trad_frame_saved_reg
*saved_regs
;
269 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
270 CORE_ADDR prologue_start
,
271 CORE_ADDR prologue_end
,
272 struct arm_prologue_cache
*cache
);
274 /* Architecture version for displaced stepping. This effects the behaviour of
275 certain instructions, and really should not be hard-wired. */
277 #define DISPLACED_STEPPING_ARCH_VERSION 5
279 /* Set to true if the 32-bit mode is in use. */
283 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
286 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
288 if (gdbarch_tdep (gdbarch
)->is_m
)
294 /* Determine if the processor is currently executing in Thumb mode. */
297 arm_is_thumb (struct regcache
*regcache
)
300 ULONGEST t_bit
= arm_psr_thumb_bit (regcache
->arch ());
302 cpsr
= regcache_raw_get_unsigned (regcache
, ARM_PS_REGNUM
);
304 return (cpsr
& t_bit
) != 0;
307 /* Determine if FRAME is executing in Thumb mode. */
310 arm_frame_is_thumb (struct frame_info
*frame
)
313 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
315 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
316 directly (from a signal frame or dummy frame) or by interpreting
317 the saved LR (from a prologue or DWARF frame). So consult it and
318 trust the unwinders. */
319 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
321 return (cpsr
& t_bit
) != 0;
324 /* Callback for VEC_lower_bound. */
327 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
328 const struct arm_mapping_symbol
*rhs
)
330 return lhs
->value
< rhs
->value
;
333 /* Search for the mapping symbol covering MEMADDR. If one is found,
334 return its type. Otherwise, return 0. If START is non-NULL,
335 set *START to the location of the mapping symbol. */
338 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
340 struct obj_section
*sec
;
342 /* If there are mapping symbols, consult them. */
343 sec
= find_pc_section (memaddr
);
346 struct arm_per_objfile
*data
;
347 VEC(arm_mapping_symbol_s
) *map
;
348 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
352 data
= (struct arm_per_objfile
*) objfile_data (sec
->objfile
,
353 arm_objfile_data_key
);
356 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
357 if (!VEC_empty (arm_mapping_symbol_s
, map
))
359 struct arm_mapping_symbol
*map_sym
;
361 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
362 arm_compare_mapping_symbols
);
364 /* VEC_lower_bound finds the earliest ordered insertion
365 point. If the following symbol starts at this exact
366 address, we use that; otherwise, the preceding
367 mapping symbol covers this address. */
368 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
370 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
371 if (map_sym
->value
== map_key
.value
)
374 *start
= map_sym
->value
+ obj_section_addr (sec
);
375 return map_sym
->type
;
381 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
383 *start
= map_sym
->value
+ obj_section_addr (sec
);
384 return map_sym
->type
;
393 /* Determine if the program counter specified in MEMADDR is in a Thumb
394 function. This function should be called for addresses unrelated to
395 any executing frame; otherwise, prefer arm_frame_is_thumb. */
398 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
400 struct bound_minimal_symbol sym
;
402 arm_displaced_step_closure
*dsc
403 = ((arm_displaced_step_closure
* )
404 get_displaced_step_closure_by_addr (memaddr
));
406 /* If checking the mode of displaced instruction in copy area, the mode
407 should be determined by instruction on the original address. */
411 fprintf_unfiltered (gdb_stdlog
,
412 "displaced: check mode of %.8lx instead of %.8lx\n",
413 (unsigned long) dsc
->insn_addr
,
414 (unsigned long) memaddr
);
415 memaddr
= dsc
->insn_addr
;
418 /* If bit 0 of the address is set, assume this is a Thumb address. */
419 if (IS_THUMB_ADDR (memaddr
))
422 /* If the user wants to override the symbol table, let him. */
423 if (strcmp (arm_force_mode_string
, "arm") == 0)
425 if (strcmp (arm_force_mode_string
, "thumb") == 0)
428 /* ARM v6-M and v7-M are always in Thumb mode. */
429 if (gdbarch_tdep (gdbarch
)->is_m
)
432 /* If there are mapping symbols, consult them. */
433 type
= arm_find_mapping_symbol (memaddr
, NULL
);
437 /* Thumb functions have a "special" bit set in minimal symbols. */
438 sym
= lookup_minimal_symbol_by_pc (memaddr
);
440 return (MSYMBOL_IS_SPECIAL (sym
.minsym
));
442 /* If the user wants to override the fallback mode, let them. */
443 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
445 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
448 /* If we couldn't find any symbol, but we're talking to a running
449 target, then trust the current value of $cpsr. This lets
450 "display/i $pc" always show the correct mode (though if there is
451 a symbol table we will not reach here, so it still may not be
452 displayed in the mode it will be executed). */
453 if (target_has_registers
)
454 return arm_frame_is_thumb (get_current_frame ());
456 /* Otherwise we're out of luck; we assume ARM. */
460 /* Determine if the address specified equals any of these magic return
461 values, called EXC_RETURN, defined by the ARM v6-M and v7-M
464 From ARMv6-M Reference Manual B1.5.8
465 Table B1-5 Exception return behavior
467 EXC_RETURN Return To Return Stack
468 0xFFFFFFF1 Handler mode Main
469 0xFFFFFFF9 Thread mode Main
470 0xFFFFFFFD Thread mode Process
472 From ARMv7-M Reference Manual B1.5.8
473 Table B1-8 EXC_RETURN definition of exception return behavior, no FP
475 EXC_RETURN Return To Return Stack
476 0xFFFFFFF1 Handler mode Main
477 0xFFFFFFF9 Thread mode Main
478 0xFFFFFFFD Thread mode Process
480 Table B1-9 EXC_RETURN definition of exception return behavior, with
483 EXC_RETURN Return To Return Stack Frame Type
484 0xFFFFFFE1 Handler mode Main Extended
485 0xFFFFFFE9 Thread mode Main Extended
486 0xFFFFFFED Thread mode Process Extended
487 0xFFFFFFF1 Handler mode Main Basic
488 0xFFFFFFF9 Thread mode Main Basic
489 0xFFFFFFFD Thread mode Process Basic
491 For more details see "B1.5.8 Exception return behavior"
492 in both ARMv6-M and ARMv7-M Architecture Reference Manuals. */
495 arm_m_addr_is_magic (CORE_ADDR addr
)
499 /* Values from Tables in B1.5.8 the EXC_RETURN definitions of
500 the exception return behavior. */
507 /* Address is magic. */
511 /* Address is not magic. */
516 /* Remove useless bits from addresses in a running program. */
518 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
520 /* On M-profile devices, do not strip the low bit from EXC_RETURN
521 (the magic exception return address). */
522 if (gdbarch_tdep (gdbarch
)->is_m
523 && arm_m_addr_is_magic (val
))
527 return UNMAKE_THUMB_ADDR (val
);
529 return (val
& 0x03fffffc);
532 /* Return 1 if PC is the start of a compiler helper function which
533 can be safely ignored during prologue skipping. IS_THUMB is true
534 if the function is known to be a Thumb function due to the way it
537 skip_prologue_function (struct gdbarch
*gdbarch
, CORE_ADDR pc
, int is_thumb
)
539 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
540 struct bound_minimal_symbol msym
;
542 msym
= lookup_minimal_symbol_by_pc (pc
);
543 if (msym
.minsym
!= NULL
544 && BMSYMBOL_VALUE_ADDRESS (msym
) == pc
545 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
)
547 const char *name
= MSYMBOL_LINKAGE_NAME (msym
.minsym
);
549 /* The GNU linker's Thumb call stub to foo is named
551 if (strstr (name
, "_from_thumb") != NULL
)
554 /* On soft-float targets, __truncdfsf2 is called to convert promoted
555 arguments to their argument types in non-prototyped
557 if (startswith (name
, "__truncdfsf2"))
559 if (startswith (name
, "__aeabi_d2f"))
562 /* Internal functions related to thread-local storage. */
563 if (startswith (name
, "__tls_get_addr"))
565 if (startswith (name
, "__aeabi_read_tp"))
570 /* If we run against a stripped glibc, we may be unable to identify
571 special functions by name. Check for one important case,
572 __aeabi_read_tp, by comparing the *code* against the default
573 implementation (this is hand-written ARM assembler in glibc). */
576 && read_code_unsigned_integer (pc
, 4, byte_order_for_code
)
577 == 0xe3e00a0f /* mov r0, #0xffff0fff */
578 && read_code_unsigned_integer (pc
+ 4, 4, byte_order_for_code
)
579 == 0xe240f01f) /* sub pc, r0, #31 */
586 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
587 the first 16-bit of instruction, and INSN2 is the second 16-bit of
589 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
590 ((bits ((insn1), 0, 3) << 12) \
591 | (bits ((insn1), 10, 10) << 11) \
592 | (bits ((insn2), 12, 14) << 8) \
593 | bits ((insn2), 0, 7))
595 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
596 the 32-bit instruction. */
597 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
598 ((bits ((insn), 16, 19) << 12) \
599 | bits ((insn), 0, 11))
601 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
604 thumb_expand_immediate (unsigned int imm
)
606 unsigned int count
= imm
>> 7;
614 return (imm
& 0xff) | ((imm
& 0xff) << 16);
616 return ((imm
& 0xff) << 8) | ((imm
& 0xff) << 24);
618 return (imm
& 0xff) | ((imm
& 0xff) << 8)
619 | ((imm
& 0xff) << 16) | ((imm
& 0xff) << 24);
622 return (0x80 | (imm
& 0x7f)) << (32 - count
);
625 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
626 epilogue, 0 otherwise. */
629 thumb_instruction_restores_sp (unsigned short insn
)
631 return (insn
== 0x46bd /* mov sp, r7 */
632 || (insn
& 0xff80) == 0xb000 /* add sp, imm */
633 || (insn
& 0xfe00) == 0xbc00); /* pop <registers> */
636 /* Analyze a Thumb prologue, looking for a recognizable stack frame
637 and frame pointer. Scan until we encounter a store that could
638 clobber the stack frame unexpectedly, or an unknown instruction.
639 Return the last address which is definitely safe to skip for an
640 initial breakpoint. */
643 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
644 CORE_ADDR start
, CORE_ADDR limit
,
645 struct arm_prologue_cache
*cache
)
647 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
648 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
652 CORE_ADDR unrecognized_pc
= 0;
654 for (i
= 0; i
< 16; i
++)
655 regs
[i
] = pv_register (i
, 0);
656 pv_area
stack (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
658 while (start
< limit
)
662 insn
= read_code_unsigned_integer (start
, 2, byte_order_for_code
);
664 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
669 if (stack
.store_would_trash (regs
[ARM_SP_REGNUM
]))
672 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
673 whether to save LR (R14). */
674 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
676 /* Calculate offsets of saved R0-R7 and LR. */
677 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
678 if (mask
& (1 << regno
))
680 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
682 stack
.store (regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
685 else if ((insn
& 0xff80) == 0xb080) /* sub sp, #imm */
687 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
688 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
691 else if (thumb_instruction_restores_sp (insn
))
693 /* Don't scan past the epilogue. */
696 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
697 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
699 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
700 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
701 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
703 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
704 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
705 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
707 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
708 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
709 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
710 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
711 regs
[bits (insn
, 6, 8)]);
712 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
713 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
715 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
716 int rm
= bits (insn
, 3, 6);
717 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
719 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
721 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
722 int src_reg
= (insn
& 0x78) >> 3;
723 regs
[dst_reg
] = regs
[src_reg
];
725 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
727 /* Handle stores to the stack. Normally pushes are used,
728 but with GCC -mtpcs-frame, there may be other stores
729 in the prologue to create the frame. */
730 int regno
= (insn
>> 8) & 0x7;
733 offset
= (insn
& 0xff) << 2;
734 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
736 if (stack
.store_would_trash (addr
))
739 stack
.store (addr
, 4, regs
[regno
]);
741 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
743 int rd
= bits (insn
, 0, 2);
744 int rn
= bits (insn
, 3, 5);
747 offset
= bits (insn
, 6, 10) << 2;
748 addr
= pv_add_constant (regs
[rn
], offset
);
750 if (stack
.store_would_trash (addr
))
753 stack
.store (addr
, 4, regs
[rd
]);
755 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
756 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
757 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
758 /* Ignore stores of argument registers to the stack. */
760 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
761 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
762 /* Ignore block loads from the stack, potentially copying
763 parameters from memory. */
765 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
766 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
767 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
768 /* Similarly ignore single loads from the stack. */
770 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
771 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
772 /* Skip register copies, i.e. saves to another register
773 instead of the stack. */
775 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
776 /* Recognize constant loads; even with small stacks these are necessary
778 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
779 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
781 /* Constant pool loads, for the same reason. */
782 unsigned int constant
;
785 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
786 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
787 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
789 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instructions. */
791 unsigned short inst2
;
793 inst2
= read_code_unsigned_integer (start
+ 2, 2,
794 byte_order_for_code
);
796 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
798 /* BL, BLX. Allow some special function calls when
799 skipping the prologue; GCC generates these before
800 storing arguments to the stack. */
802 int j1
, j2
, imm1
, imm2
;
804 imm1
= sbits (insn
, 0, 10);
805 imm2
= bits (inst2
, 0, 10);
806 j1
= bit (inst2
, 13);
807 j2
= bit (inst2
, 11);
809 offset
= ((imm1
<< 12) + (imm2
<< 1));
810 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
812 nextpc
= start
+ 4 + offset
;
813 /* For BLX make sure to clear the low bits. */
814 if (bit (inst2
, 12) == 0)
815 nextpc
= nextpc
& 0xfffffffc;
817 if (!skip_prologue_function (gdbarch
, nextpc
,
818 bit (inst2
, 12) != 0))
822 else if ((insn
& 0xffd0) == 0xe900 /* stmdb Rn{!},
824 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
826 pv_t addr
= regs
[bits (insn
, 0, 3)];
829 if (stack
.store_would_trash (addr
))
832 /* Calculate offsets of saved registers. */
833 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
834 if (inst2
& (1 << regno
))
836 addr
= pv_add_constant (addr
, -4);
837 stack
.store (addr
, 4, regs
[regno
]);
841 regs
[bits (insn
, 0, 3)] = addr
;
844 else if ((insn
& 0xff50) == 0xe940 /* strd Rt, Rt2,
846 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
848 int regno1
= bits (inst2
, 12, 15);
849 int regno2
= bits (inst2
, 8, 11);
850 pv_t addr
= regs
[bits (insn
, 0, 3)];
852 offset
= inst2
& 0xff;
854 addr
= pv_add_constant (addr
, offset
);
856 addr
= pv_add_constant (addr
, -offset
);
858 if (stack
.store_would_trash (addr
))
861 stack
.store (addr
, 4, regs
[regno1
]);
862 stack
.store (pv_add_constant (addr
, 4),
866 regs
[bits (insn
, 0, 3)] = addr
;
869 else if ((insn
& 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
870 && (inst2
& 0x0c00) == 0x0c00
871 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
873 int regno
= bits (inst2
, 12, 15);
874 pv_t addr
= regs
[bits (insn
, 0, 3)];
876 offset
= inst2
& 0xff;
878 addr
= pv_add_constant (addr
, offset
);
880 addr
= pv_add_constant (addr
, -offset
);
882 if (stack
.store_would_trash (addr
))
885 stack
.store (addr
, 4, regs
[regno
]);
888 regs
[bits (insn
, 0, 3)] = addr
;
891 else if ((insn
& 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
892 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
894 int regno
= bits (inst2
, 12, 15);
897 offset
= inst2
& 0xfff;
898 addr
= pv_add_constant (regs
[bits (insn
, 0, 3)], offset
);
900 if (stack
.store_would_trash (addr
))
903 stack
.store (addr
, 4, regs
[regno
]);
906 else if ((insn
& 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
907 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
908 /* Ignore stores of argument registers to the stack. */
911 else if ((insn
& 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
912 && (inst2
& 0x0d00) == 0x0c00
913 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
914 /* Ignore stores of argument registers to the stack. */
917 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!],
919 && (inst2
& 0x8000) == 0x0000
920 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
921 /* Ignore block loads from the stack, potentially copying
922 parameters from memory. */
925 else if ((insn
& 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
927 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
928 /* Similarly ignore dual loads from the stack. */
931 else if ((insn
& 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
932 && (inst2
& 0x0d00) == 0x0c00
933 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
934 /* Similarly ignore single loads from the stack. */
937 else if ((insn
& 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
938 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
939 /* Similarly ignore single loads from the stack. */
942 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
943 && (inst2
& 0x8000) == 0x0000)
945 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
946 | (bits (inst2
, 12, 14) << 8)
947 | bits (inst2
, 0, 7));
949 regs
[bits (inst2
, 8, 11)]
950 = pv_add_constant (regs
[bits (insn
, 0, 3)],
951 thumb_expand_immediate (imm
));
954 else if ((insn
& 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
955 && (inst2
& 0x8000) == 0x0000)
957 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
958 | (bits (inst2
, 12, 14) << 8)
959 | bits (inst2
, 0, 7));
961 regs
[bits (inst2
, 8, 11)]
962 = pv_add_constant (regs
[bits (insn
, 0, 3)], imm
);
965 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
966 && (inst2
& 0x8000) == 0x0000)
968 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
969 | (bits (inst2
, 12, 14) << 8)
970 | bits (inst2
, 0, 7));
972 regs
[bits (inst2
, 8, 11)]
973 = pv_add_constant (regs
[bits (insn
, 0, 3)],
974 - (CORE_ADDR
) thumb_expand_immediate (imm
));
977 else if ((insn
& 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
978 && (inst2
& 0x8000) == 0x0000)
980 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
981 | (bits (inst2
, 12, 14) << 8)
982 | bits (inst2
, 0, 7));
984 regs
[bits (inst2
, 8, 11)]
985 = pv_add_constant (regs
[bits (insn
, 0, 3)], - (CORE_ADDR
) imm
);
988 else if ((insn
& 0xfbff) == 0xf04f) /* mov.w Rd, #const */
990 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
991 | (bits (inst2
, 12, 14) << 8)
992 | bits (inst2
, 0, 7));
994 regs
[bits (inst2
, 8, 11)]
995 = pv_constant (thumb_expand_immediate (imm
));
998 else if ((insn
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1001 = EXTRACT_MOVW_MOVT_IMM_T (insn
, inst2
);
1003 regs
[bits (inst2
, 8, 11)] = pv_constant (imm
);
1006 else if (insn
== 0xea5f /* mov.w Rd,Rm */
1007 && (inst2
& 0xf0f0) == 0)
1009 int dst_reg
= (inst2
& 0x0f00) >> 8;
1010 int src_reg
= inst2
& 0xf;
1011 regs
[dst_reg
] = regs
[src_reg
];
1014 else if ((insn
& 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1016 /* Constant pool loads. */
1017 unsigned int constant
;
1020 offset
= bits (inst2
, 0, 11);
1022 loc
= start
+ 4 + offset
;
1024 loc
= start
+ 4 - offset
;
1026 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1027 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1030 else if ((insn
& 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1032 /* Constant pool loads. */
1033 unsigned int constant
;
1036 offset
= bits (inst2
, 0, 7) << 2;
1038 loc
= start
+ 4 + offset
;
1040 loc
= start
+ 4 - offset
;
1042 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1043 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1045 constant
= read_memory_unsigned_integer (loc
+ 4, 4, byte_order
);
1046 regs
[bits (inst2
, 8, 11)] = pv_constant (constant
);
1049 else if (thumb2_instruction_changes_pc (insn
, inst2
))
1051 /* Don't scan past anything that might change control flow. */
1056 /* The optimizer might shove anything into the prologue,
1057 so we just skip what we don't recognize. */
1058 unrecognized_pc
= start
;
1063 else if (thumb_instruction_changes_pc (insn
))
1065 /* Don't scan past anything that might change control flow. */
1070 /* The optimizer might shove anything into the prologue,
1071 so we just skip what we don't recognize. */
1072 unrecognized_pc
= start
;
1079 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1080 paddress (gdbarch
, start
));
1082 if (unrecognized_pc
== 0)
1083 unrecognized_pc
= start
;
1086 return unrecognized_pc
;
1088 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1090 /* Frame pointer is fp. Frame size is constant. */
1091 cache
->framereg
= ARM_FP_REGNUM
;
1092 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1094 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
1096 /* Frame pointer is r7. Frame size is constant. */
1097 cache
->framereg
= THUMB_FP_REGNUM
;
1098 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
1102 /* Try the stack pointer... this is a bit desperate. */
1103 cache
->framereg
= ARM_SP_REGNUM
;
1104 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1107 for (i
= 0; i
< 16; i
++)
1108 if (stack
.find_reg (gdbarch
, i
, &offset
))
1109 cache
->saved_regs
[i
].addr
= offset
;
1111 return unrecognized_pc
;
1115 /* Try to analyze the instructions starting from PC, which load symbol
1116 __stack_chk_guard. Return the address of instruction after loading this
1117 symbol, set the dest register number to *BASEREG, and set the size of
1118 instructions for loading symbol in OFFSET. Return 0 if instructions are
1122 arm_analyze_load_stack_chk_guard(CORE_ADDR pc
, struct gdbarch
*gdbarch
,
1123 unsigned int *destreg
, int *offset
)
1125 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1126 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1127 unsigned int low
, high
, address
;
1132 unsigned short insn1
1133 = read_code_unsigned_integer (pc
, 2, byte_order_for_code
);
1135 if ((insn1
& 0xf800) == 0x4800) /* ldr Rd, #immed */
1137 *destreg
= bits (insn1
, 8, 10);
1139 address
= (pc
& 0xfffffffc) + 4 + (bits (insn1
, 0, 7) << 2);
1140 address
= read_memory_unsigned_integer (address
, 4,
1141 byte_order_for_code
);
1143 else if ((insn1
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1145 unsigned short insn2
1146 = read_code_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1148 low
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1151 = read_code_unsigned_integer (pc
+ 4, 2, byte_order_for_code
);
1153 = read_code_unsigned_integer (pc
+ 6, 2, byte_order_for_code
);
1155 /* movt Rd, #const */
1156 if ((insn1
& 0xfbc0) == 0xf2c0)
1158 high
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1159 *destreg
= bits (insn2
, 8, 11);
1161 address
= (high
<< 16 | low
);
1168 = read_code_unsigned_integer (pc
, 4, byte_order_for_code
);
1170 if ((insn
& 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1172 address
= bits (insn
, 0, 11) + pc
+ 8;
1173 address
= read_memory_unsigned_integer (address
, 4,
1174 byte_order_for_code
);
1176 *destreg
= bits (insn
, 12, 15);
1179 else if ((insn
& 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1181 low
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1184 = read_code_unsigned_integer (pc
+ 4, 4, byte_order_for_code
);
1186 if ((insn
& 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1188 high
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1189 *destreg
= bits (insn
, 12, 15);
1191 address
= (high
<< 16 | low
);
1199 /* Try to skip a sequence of instructions used for stack protector. If PC
1200 points to the first instruction of this sequence, return the address of
1201 first instruction after this sequence, otherwise, return original PC.
1203 On arm, this sequence of instructions is composed of mainly three steps,
1204 Step 1: load symbol __stack_chk_guard,
1205 Step 2: load from address of __stack_chk_guard,
1206 Step 3: store it to somewhere else.
1208 Usually, instructions on step 2 and step 3 are the same on various ARM
1209 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1210 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1211 instructions in step 1 vary from different ARM architectures. On ARMv7,
1214 movw Rn, #:lower16:__stack_chk_guard
1215 movt Rn, #:upper16:__stack_chk_guard
1222 .word __stack_chk_guard
1224 Since ldr/str is a very popular instruction, we can't use them as
1225 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1226 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1227 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1230 arm_skip_stack_protector(CORE_ADDR pc
, struct gdbarch
*gdbarch
)
1232 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1233 unsigned int basereg
;
1234 struct bound_minimal_symbol stack_chk_guard
;
1236 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1239 /* Try to parse the instructions in Step 1. */
1240 addr
= arm_analyze_load_stack_chk_guard (pc
, gdbarch
,
1245 stack_chk_guard
= lookup_minimal_symbol_by_pc (addr
);
1246 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1247 Otherwise, this sequence cannot be for stack protector. */
1248 if (stack_chk_guard
.minsym
== NULL
1249 || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard
.minsym
), "__stack_chk_guard"))
1254 unsigned int destreg
;
1256 = read_code_unsigned_integer (pc
+ offset
, 2, byte_order_for_code
);
1258 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1259 if ((insn
& 0xf800) != 0x6800)
1261 if (bits (insn
, 3, 5) != basereg
)
1263 destreg
= bits (insn
, 0, 2);
1265 insn
= read_code_unsigned_integer (pc
+ offset
+ 2, 2,
1266 byte_order_for_code
);
1267 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1268 if ((insn
& 0xf800) != 0x6000)
1270 if (destreg
!= bits (insn
, 0, 2))
1275 unsigned int destreg
;
1277 = read_code_unsigned_integer (pc
+ offset
, 4, byte_order_for_code
);
1279 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1280 if ((insn
& 0x0e500000) != 0x04100000)
1282 if (bits (insn
, 16, 19) != basereg
)
1284 destreg
= bits (insn
, 12, 15);
1285 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1286 insn
= read_code_unsigned_integer (pc
+ offset
+ 4,
1287 4, byte_order_for_code
);
1288 if ((insn
& 0x0e500000) != 0x04000000)
1290 if (bits (insn
, 12, 15) != destreg
)
1293 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1296 return pc
+ offset
+ 4;
1298 return pc
+ offset
+ 8;
1301 /* Advance the PC across any function entry prologue instructions to
1302 reach some "real" code.
1304 The APCS (ARM Procedure Call Standard) defines the following
1308 [stmfd sp!, {a1,a2,a3,a4}]
1309 stmfd sp!, {...,fp,ip,lr,pc}
1310 [stfe f7, [sp, #-12]!]
1311 [stfe f6, [sp, #-12]!]
1312 [stfe f5, [sp, #-12]!]
1313 [stfe f4, [sp, #-12]!]
1314 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1317 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1319 CORE_ADDR func_addr
, limit_pc
;
1321 /* See if we can determine the end of the prologue via the symbol table.
1322 If so, then return either PC, or the PC after the prologue, whichever
1324 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1326 CORE_ADDR post_prologue_pc
1327 = skip_prologue_using_sal (gdbarch
, func_addr
);
1328 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1330 if (post_prologue_pc
)
1332 = arm_skip_stack_protector (post_prologue_pc
, gdbarch
);
1335 /* GCC always emits a line note before the prologue and another
1336 one after, even if the two are at the same address or on the
1337 same line. Take advantage of this so that we do not need to
1338 know every instruction that might appear in the prologue. We
1339 will have producer information for most binaries; if it is
1340 missing (e.g. for -gstabs), assuming the GNU tools. */
1341 if (post_prologue_pc
1343 || COMPUNIT_PRODUCER (cust
) == NULL
1344 || startswith (COMPUNIT_PRODUCER (cust
), "GNU ")
1345 || startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
1346 return post_prologue_pc
;
1348 if (post_prologue_pc
!= 0)
1350 CORE_ADDR analyzed_limit
;
1352 /* For non-GCC compilers, make sure the entire line is an
1353 acceptable prologue; GDB will round this function's
1354 return value up to the end of the following line so we
1355 can not skip just part of a line (and we do not want to).
1357 RealView does not treat the prologue specially, but does
1358 associate prologue code with the opening brace; so this
1359 lets us skip the first line if we think it is the opening
1361 if (arm_pc_is_thumb (gdbarch
, func_addr
))
1362 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
1363 post_prologue_pc
, NULL
);
1365 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
1366 post_prologue_pc
, NULL
);
1368 if (analyzed_limit
!= post_prologue_pc
)
1371 return post_prologue_pc
;
1375 /* Can't determine prologue from the symbol table, need to examine
1378 /* Find an upper limit on the function prologue using the debug
1379 information. If the debug information could not be used to provide
1380 that bound, then use an arbitrary large number as the upper bound. */
1381 /* Like arm_scan_prologue, stop no later than pc + 64. */
1382 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1384 limit_pc
= pc
+ 64; /* Magic. */
1387 /* Check if this is Thumb code. */
1388 if (arm_pc_is_thumb (gdbarch
, pc
))
1389 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1391 return arm_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1395 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1396 This function decodes a Thumb function prologue to determine:
1397 1) the size of the stack frame
1398 2) which registers are saved on it
1399 3) the offsets of saved regs
1400 4) the offset from the stack pointer to the frame pointer
1402 A typical Thumb function prologue would create this stack frame
1403 (offsets relative to FP)
1404 old SP -> 24 stack parameters
1407 R7 -> 0 local variables (16 bytes)
1408 SP -> -12 additional stack space (12 bytes)
1409 The frame size would thus be 36 bytes, and the frame offset would be
1410 12 bytes. The frame register is R7.
1412 The comments for thumb_skip_prolog() describe the algorithm we use
1413 to detect the end of the prolog. */
1417 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
1418 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
1420 CORE_ADDR prologue_start
;
1421 CORE_ADDR prologue_end
;
1423 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1426 /* See comment in arm_scan_prologue for an explanation of
1428 if (prologue_end
> prologue_start
+ 64)
1430 prologue_end
= prologue_start
+ 64;
1434 /* We're in the boondocks: we have no idea where the start of the
1438 prologue_end
= std::min (prologue_end
, prev_pc
);
1440 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1443 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1447 arm_instruction_restores_sp (unsigned int insn
)
1449 if (bits (insn
, 28, 31) != INST_NV
)
1451 if ((insn
& 0x0df0f000) == 0x0080d000
1452 /* ADD SP (register or immediate). */
1453 || (insn
& 0x0df0f000) == 0x0040d000
1454 /* SUB SP (register or immediate). */
1455 || (insn
& 0x0ffffff0) == 0x01a0d000
1457 || (insn
& 0x0fff0000) == 0x08bd0000
1459 || (insn
& 0x0fff0000) == 0x049d0000)
1460 /* POP of a single register. */
1467 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1468 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1469 fill it in. Return the first address not recognized as a prologue
1472 We recognize all the instructions typically found in ARM prologues,
1473 plus harmless instructions which can be skipped (either for analysis
1474 purposes, or a more restrictive set that can be skipped when finding
1475 the end of the prologue). */
1478 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1479 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1480 struct arm_prologue_cache
*cache
)
1482 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1484 CORE_ADDR offset
, current_pc
;
1485 pv_t regs
[ARM_FPS_REGNUM
];
1486 CORE_ADDR unrecognized_pc
= 0;
1488 /* Search the prologue looking for instructions that set up the
1489 frame pointer, adjust the stack pointer, and save registers.
1491 Be careful, however, and if it doesn't look like a prologue,
1492 don't try to scan it. If, for instance, a frameless function
1493 begins with stmfd sp!, then we will tell ourselves there is
1494 a frame, which will confuse stack traceback, as well as "finish"
1495 and other operations that rely on a knowledge of the stack
1498 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1499 regs
[regno
] = pv_register (regno
, 0);
1500 pv_area
stack (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1502 for (current_pc
= prologue_start
;
1503 current_pc
< prologue_end
;
1507 = read_code_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1509 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1511 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1514 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1515 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1517 unsigned imm
= insn
& 0xff; /* immediate value */
1518 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1519 int rd
= bits (insn
, 12, 15);
1520 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1521 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1524 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1525 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1527 unsigned imm
= insn
& 0xff; /* immediate value */
1528 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1529 int rd
= bits (insn
, 12, 15);
1530 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1531 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1534 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd,
1537 if (stack
.store_would_trash (regs
[ARM_SP_REGNUM
]))
1539 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1540 stack
.store (regs
[ARM_SP_REGNUM
], 4,
1541 regs
[bits (insn
, 12, 15)]);
1544 else if ((insn
& 0xffff0000) == 0xe92d0000)
1545 /* stmfd sp!, {..., fp, ip, lr, pc}
1547 stmfd sp!, {a1, a2, a3, a4} */
1549 int mask
= insn
& 0xffff;
1551 if (stack
.store_would_trash (regs
[ARM_SP_REGNUM
]))
1554 /* Calculate offsets of saved registers. */
1555 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1556 if (mask
& (1 << regno
))
1559 = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1560 stack
.store (regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1563 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1564 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1565 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1567 /* No need to add this to saved_regs -- it's just an arg reg. */
1570 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1571 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1572 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1574 /* No need to add this to saved_regs -- it's just an arg reg. */
1577 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn,
1579 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1581 /* No need to add this to saved_regs -- it's just arg regs. */
1584 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1586 unsigned imm
= insn
& 0xff; /* immediate value */
1587 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1588 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1589 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1591 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1593 unsigned imm
= insn
& 0xff; /* immediate value */
1594 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1595 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1596 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1598 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?,
1600 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1602 if (stack
.store_would_trash (regs
[ARM_SP_REGNUM
]))
1605 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1606 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1607 stack
.store (regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1609 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1611 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1613 int n_saved_fp_regs
;
1614 unsigned int fp_start_reg
, fp_bound_reg
;
1616 if (stack
.store_would_trash (regs
[ARM_SP_REGNUM
]))
1619 if ((insn
& 0x800) == 0x800) /* N0 is set */
1621 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1622 n_saved_fp_regs
= 3;
1624 n_saved_fp_regs
= 1;
1628 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1629 n_saved_fp_regs
= 2;
1631 n_saved_fp_regs
= 4;
1634 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1635 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1636 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1638 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1639 stack
.store (regs
[ARM_SP_REGNUM
], 12,
1640 regs
[fp_start_reg
++]);
1643 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1645 /* Allow some special function calls when skipping the
1646 prologue; GCC generates these before storing arguments to
1648 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1650 if (skip_prologue_function (gdbarch
, dest
, 0))
1655 else if ((insn
& 0xf0000000) != 0xe0000000)
1656 break; /* Condition not true, exit early. */
1657 else if (arm_instruction_changes_pc (insn
))
1658 /* Don't scan past anything that might change control flow. */
1660 else if (arm_instruction_restores_sp (insn
))
1662 /* Don't scan past the epilogue. */
1665 else if ((insn
& 0xfe500000) == 0xe8100000 /* ldm */
1666 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1667 /* Ignore block loads from the stack, potentially copying
1668 parameters from memory. */
1670 else if ((insn
& 0xfc500000) == 0xe4100000
1671 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1672 /* Similarly ignore single loads from the stack. */
1674 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1675 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1676 register instead of the stack. */
1680 /* The optimizer might shove anything into the prologue, if
1681 we build up cache (cache != NULL) from scanning prologue,
1682 we just skip what we don't recognize and scan further to
1683 make cache as complete as possible. However, if we skip
1684 prologue, we'll stop immediately on unrecognized
1686 unrecognized_pc
= current_pc
;
1694 if (unrecognized_pc
== 0)
1695 unrecognized_pc
= current_pc
;
1699 int framereg
, framesize
;
1701 /* The frame size is just the distance from the frame register
1702 to the original stack pointer. */
1703 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1705 /* Frame pointer is fp. */
1706 framereg
= ARM_FP_REGNUM
;
1707 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1711 /* Try the stack pointer... this is a bit desperate. */
1712 framereg
= ARM_SP_REGNUM
;
1713 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1716 cache
->framereg
= framereg
;
1717 cache
->framesize
= framesize
;
1719 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1720 if (stack
.find_reg (gdbarch
, regno
, &offset
))
1721 cache
->saved_regs
[regno
].addr
= offset
;
1725 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1726 paddress (gdbarch
, unrecognized_pc
));
1728 return unrecognized_pc
;
1732 arm_scan_prologue (struct frame_info
*this_frame
,
1733 struct arm_prologue_cache
*cache
)
1735 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1736 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1737 CORE_ADDR prologue_start
, prologue_end
;
1738 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1739 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1741 /* Assume there is no frame until proven otherwise. */
1742 cache
->framereg
= ARM_SP_REGNUM
;
1743 cache
->framesize
= 0;
1745 /* Check for Thumb prologue. */
1746 if (arm_frame_is_thumb (this_frame
))
1748 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1752 /* Find the function prologue. If we can't find the function in
1753 the symbol table, peek in the stack frame to find the PC. */
1754 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1757 /* One way to find the end of the prologue (which works well
1758 for unoptimized code) is to do the following:
1760 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1763 prologue_end = prev_pc;
1764 else if (sal.end < prologue_end)
1765 prologue_end = sal.end;
1767 This mechanism is very accurate so long as the optimizer
1768 doesn't move any instructions from the function body into the
1769 prologue. If this happens, sal.end will be the last
1770 instruction in the first hunk of prologue code just before
1771 the first instruction that the scheduler has moved from
1772 the body to the prologue.
1774 In order to make sure that we scan all of the prologue
1775 instructions, we use a slightly less accurate mechanism which
1776 may scan more than necessary. To help compensate for this
1777 lack of accuracy, the prologue scanning loop below contains
1778 several clauses which'll cause the loop to terminate early if
1779 an implausible prologue instruction is encountered.
1785 is a suitable endpoint since it accounts for the largest
1786 possible prologue plus up to five instructions inserted by
1789 if (prologue_end
> prologue_start
+ 64)
1791 prologue_end
= prologue_start
+ 64; /* See above. */
1796 /* We have no symbol information. Our only option is to assume this
1797 function has a standard stack frame and the normal frame register.
1798 Then, we can find the value of our frame pointer on entrance to
1799 the callee (or at the present moment if this is the innermost frame).
1800 The value stored there should be the address of the stmfd + 8. */
1801 CORE_ADDR frame_loc
;
1802 ULONGEST return_value
;
1804 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
1805 if (!safe_read_memory_unsigned_integer (frame_loc
, 4, byte_order
,
1810 prologue_start
= gdbarch_addr_bits_remove
1811 (gdbarch
, return_value
) - 8;
1812 prologue_end
= prologue_start
+ 64; /* See above. */
1816 if (prev_pc
< prologue_end
)
1817 prologue_end
= prev_pc
;
1819 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1822 static struct arm_prologue_cache
*
1823 arm_make_prologue_cache (struct frame_info
*this_frame
)
1826 struct arm_prologue_cache
*cache
;
1827 CORE_ADDR unwound_fp
;
1829 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1830 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1832 arm_scan_prologue (this_frame
, cache
);
1834 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
1835 if (unwound_fp
== 0)
1838 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
1840 /* Calculate actual addresses of saved registers using offsets
1841 determined by arm_scan_prologue. */
1842 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
1843 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
1844 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
1849 /* Implementation of the stop_reason hook for arm_prologue frames. */
1851 static enum unwind_stop_reason
1852 arm_prologue_unwind_stop_reason (struct frame_info
*this_frame
,
1855 struct arm_prologue_cache
*cache
;
1858 if (*this_cache
== NULL
)
1859 *this_cache
= arm_make_prologue_cache (this_frame
);
1860 cache
= (struct arm_prologue_cache
*) *this_cache
;
1862 /* This is meant to halt the backtrace at "_start". */
1863 pc
= get_frame_pc (this_frame
);
1864 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1865 return UNWIND_OUTERMOST
;
1867 /* If we've hit a wall, stop. */
1868 if (cache
->prev_sp
== 0)
1869 return UNWIND_OUTERMOST
;
1871 return UNWIND_NO_REASON
;
1874 /* Our frame ID for a normal frame is the current function's starting PC
1875 and the caller's SP when we were called. */
1878 arm_prologue_this_id (struct frame_info
*this_frame
,
1880 struct frame_id
*this_id
)
1882 struct arm_prologue_cache
*cache
;
1886 if (*this_cache
== NULL
)
1887 *this_cache
= arm_make_prologue_cache (this_frame
);
1888 cache
= (struct arm_prologue_cache
*) *this_cache
;
1890 /* Use function start address as part of the frame ID. If we cannot
1891 identify the start address (due to missing symbol information),
1892 fall back to just using the current PC. */
1893 pc
= get_frame_pc (this_frame
);
1894 func
= get_frame_func (this_frame
);
1898 id
= frame_id_build (cache
->prev_sp
, func
);
1902 static struct value
*
1903 arm_prologue_prev_register (struct frame_info
*this_frame
,
1907 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1908 struct arm_prologue_cache
*cache
;
1910 if (*this_cache
== NULL
)
1911 *this_cache
= arm_make_prologue_cache (this_frame
);
1912 cache
= (struct arm_prologue_cache
*) *this_cache
;
1914 /* If we are asked to unwind the PC, then we need to return the LR
1915 instead. The prologue may save PC, but it will point into this
1916 frame's prologue, not the next frame's resume location. Also
1917 strip the saved T bit. A valid LR may have the low bit set, but
1918 a valid PC never does. */
1919 if (prev_regnum
== ARM_PC_REGNUM
)
1923 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1924 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1925 arm_addr_bits_remove (gdbarch
, lr
));
1928 /* SP is generally not saved to the stack, but this frame is
1929 identified by the next frame's stack pointer at the time of the call.
1930 The value was already reconstructed into PREV_SP. */
1931 if (prev_regnum
== ARM_SP_REGNUM
)
1932 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1934 /* The CPSR may have been changed by the call instruction and by the
1935 called function. The only bit we can reconstruct is the T bit,
1936 by checking the low bit of LR as of the call. This is a reliable
1937 indicator of Thumb-ness except for some ARM v4T pre-interworking
1938 Thumb code, which could get away with a clear low bit as long as
1939 the called function did not use bx. Guess that all other
1940 bits are unchanged; the condition flags are presumably lost,
1941 but the processor status is likely valid. */
1942 if (prev_regnum
== ARM_PS_REGNUM
)
1945 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
1947 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1948 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1949 if (IS_THUMB_ADDR (lr
))
1953 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1956 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1960 struct frame_unwind arm_prologue_unwind
= {
1962 arm_prologue_unwind_stop_reason
,
1963 arm_prologue_this_id
,
1964 arm_prologue_prev_register
,
1966 default_frame_sniffer
1969 /* Maintain a list of ARM exception table entries per objfile, similar to the
1970 list of mapping symbols. We only cache entries for standard ARM-defined
1971 personality routines; the cache will contain only the frame unwinding
1972 instructions associated with the entry (not the descriptors). */
1974 static const struct objfile_data
*arm_exidx_data_key
;
1976 struct arm_exidx_entry
1981 typedef struct arm_exidx_entry arm_exidx_entry_s
;
1982 DEF_VEC_O(arm_exidx_entry_s
);
1984 struct arm_exidx_data
1986 VEC(arm_exidx_entry_s
) **section_maps
;
1990 arm_exidx_data_free (struct objfile
*objfile
, void *arg
)
1992 struct arm_exidx_data
*data
= (struct arm_exidx_data
*) arg
;
1995 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
1996 VEC_free (arm_exidx_entry_s
, data
->section_maps
[i
]);
2000 arm_compare_exidx_entries (const struct arm_exidx_entry
*lhs
,
2001 const struct arm_exidx_entry
*rhs
)
2003 return lhs
->addr
< rhs
->addr
;
2006 static struct obj_section
*
2007 arm_obj_section_from_vma (struct objfile
*objfile
, bfd_vma vma
)
2009 struct obj_section
*osect
;
2011 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
2012 if (bfd_get_section_flags (objfile
->obfd
,
2013 osect
->the_bfd_section
) & SEC_ALLOC
)
2015 bfd_vma start
, size
;
2016 start
= bfd_get_section_vma (objfile
->obfd
, osect
->the_bfd_section
);
2017 size
= bfd_get_section_size (osect
->the_bfd_section
);
2019 if (start
<= vma
&& vma
< start
+ size
)
2026 /* Parse contents of exception table and exception index sections
2027 of OBJFILE, and fill in the exception table entry cache.
2029 For each entry that refers to a standard ARM-defined personality
2030 routine, extract the frame unwinding instructions (from either
2031 the index or the table section). The unwinding instructions
2033 - extracting them from the rest of the table data
2034 - converting to host endianness
2035 - appending the implicit 0xb0 ("Finish") code
2037 The extracted and normalized instructions are stored for later
2038 retrieval by the arm_find_exidx_entry routine. */
2041 arm_exidx_new_objfile (struct objfile
*objfile
)
2043 struct arm_exidx_data
*data
;
2044 asection
*exidx
, *extab
;
2045 bfd_vma exidx_vma
= 0, extab_vma
= 0;
2048 /* If we've already touched this file, do nothing. */
2049 if (!objfile
|| objfile_data (objfile
, arm_exidx_data_key
) != NULL
)
2052 /* Read contents of exception table and index. */
2053 exidx
= bfd_get_section_by_name (objfile
->obfd
, ELF_STRING_ARM_unwind
);
2054 gdb::byte_vector exidx_data
;
2057 exidx_vma
= bfd_section_vma (objfile
->obfd
, exidx
);
2058 exidx_data
.resize (bfd_get_section_size (exidx
));
2060 if (!bfd_get_section_contents (objfile
->obfd
, exidx
,
2061 exidx_data
.data (), 0,
2062 exidx_data
.size ()))
2066 extab
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.extab");
2067 gdb::byte_vector extab_data
;
2070 extab_vma
= bfd_section_vma (objfile
->obfd
, extab
);
2071 extab_data
.resize (bfd_get_section_size (extab
));
2073 if (!bfd_get_section_contents (objfile
->obfd
, extab
,
2074 extab_data
.data (), 0,
2075 extab_data
.size ()))
2079 /* Allocate exception table data structure. */
2080 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
, struct arm_exidx_data
);
2081 set_objfile_data (objfile
, arm_exidx_data_key
, data
);
2082 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2083 objfile
->obfd
->section_count
,
2084 VEC(arm_exidx_entry_s
) *);
2086 /* Fill in exception table. */
2087 for (i
= 0; i
< exidx_data
.size () / 8; i
++)
2089 struct arm_exidx_entry new_exidx_entry
;
2090 bfd_vma idx
= bfd_h_get_32 (objfile
->obfd
, exidx_data
.data () + i
* 8);
2091 bfd_vma val
= bfd_h_get_32 (objfile
->obfd
,
2092 exidx_data
.data () + i
* 8 + 4);
2093 bfd_vma addr
= 0, word
= 0;
2094 int n_bytes
= 0, n_words
= 0;
2095 struct obj_section
*sec
;
2096 gdb_byte
*entry
= NULL
;
2098 /* Extract address of start of function. */
2099 idx
= ((idx
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2100 idx
+= exidx_vma
+ i
* 8;
2102 /* Find section containing function and compute section offset. */
2103 sec
= arm_obj_section_from_vma (objfile
, idx
);
2106 idx
-= bfd_get_section_vma (objfile
->obfd
, sec
->the_bfd_section
);
2108 /* Determine address of exception table entry. */
2111 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2113 else if ((val
& 0xff000000) == 0x80000000)
2115 /* Exception table entry embedded in .ARM.exidx
2116 -- must be short form. */
2120 else if (!(val
& 0x80000000))
2122 /* Exception table entry in .ARM.extab. */
2123 addr
= ((val
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2124 addr
+= exidx_vma
+ i
* 8 + 4;
2126 if (addr
>= extab_vma
&& addr
+ 4 <= extab_vma
+ extab_data
.size ())
2128 word
= bfd_h_get_32 (objfile
->obfd
,
2129 extab_data
.data () + addr
- extab_vma
);
2132 if ((word
& 0xff000000) == 0x80000000)
2137 else if ((word
& 0xff000000) == 0x81000000
2138 || (word
& 0xff000000) == 0x82000000)
2142 n_words
= ((word
>> 16) & 0xff);
2144 else if (!(word
& 0x80000000))
2147 struct obj_section
*pers_sec
;
2148 int gnu_personality
= 0;
2150 /* Custom personality routine. */
2151 pers
= ((word
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2152 pers
= UNMAKE_THUMB_ADDR (pers
+ addr
- 4);
2154 /* Check whether we've got one of the variants of the
2155 GNU personality routines. */
2156 pers_sec
= arm_obj_section_from_vma (objfile
, pers
);
2159 static const char *personality
[] =
2161 "__gcc_personality_v0",
2162 "__gxx_personality_v0",
2163 "__gcj_personality_v0",
2164 "__gnu_objc_personality_v0",
2168 CORE_ADDR pc
= pers
+ obj_section_offset (pers_sec
);
2171 for (k
= 0; personality
[k
]; k
++)
2172 if (lookup_minimal_symbol_by_pc_name
2173 (pc
, personality
[k
], objfile
))
2175 gnu_personality
= 1;
2180 /* If so, the next word contains a word count in the high
2181 byte, followed by the same unwind instructions as the
2182 pre-defined forms. */
2184 && addr
+ 4 <= extab_vma
+ extab_data
.size ())
2186 word
= bfd_h_get_32 (objfile
->obfd
,
2188 + addr
- extab_vma
));
2191 n_words
= ((word
>> 24) & 0xff);
2197 /* Sanity check address. */
2199 if (addr
< extab_vma
2200 || addr
+ 4 * n_words
> extab_vma
+ extab_data
.size ())
2201 n_words
= n_bytes
= 0;
2203 /* The unwind instructions reside in WORD (only the N_BYTES least
2204 significant bytes are valid), followed by N_WORDS words in the
2205 extab section starting at ADDR. */
2206 if (n_bytes
|| n_words
)
2209 = (gdb_byte
*) obstack_alloc (&objfile
->objfile_obstack
,
2210 n_bytes
+ n_words
* 4 + 1);
2213 *p
++ = (gdb_byte
) ((word
>> (8 * n_bytes
)) & 0xff);
2217 word
= bfd_h_get_32 (objfile
->obfd
,
2218 extab_data
.data () + addr
- extab_vma
);
2221 *p
++ = (gdb_byte
) ((word
>> 24) & 0xff);
2222 *p
++ = (gdb_byte
) ((word
>> 16) & 0xff);
2223 *p
++ = (gdb_byte
) ((word
>> 8) & 0xff);
2224 *p
++ = (gdb_byte
) (word
& 0xff);
2227 /* Implied "Finish" to terminate the list. */
2231 /* Push entry onto vector. They are guaranteed to always
2232 appear in order of increasing addresses. */
2233 new_exidx_entry
.addr
= idx
;
2234 new_exidx_entry
.entry
= entry
;
2235 VEC_safe_push (arm_exidx_entry_s
,
2236 data
->section_maps
[sec
->the_bfd_section
->index
],
2241 /* Search for the exception table entry covering MEMADDR. If one is found,
2242 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2243 set *START to the start of the region covered by this entry. */
2246 arm_find_exidx_entry (CORE_ADDR memaddr
, CORE_ADDR
*start
)
2248 struct obj_section
*sec
;
2250 sec
= find_pc_section (memaddr
);
2253 struct arm_exidx_data
*data
;
2254 VEC(arm_exidx_entry_s
) *map
;
2255 struct arm_exidx_entry map_key
= { memaddr
- obj_section_addr (sec
), 0 };
2258 data
= ((struct arm_exidx_data
*)
2259 objfile_data (sec
->objfile
, arm_exidx_data_key
));
2262 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
2263 if (!VEC_empty (arm_exidx_entry_s
, map
))
2265 struct arm_exidx_entry
*map_sym
;
2267 idx
= VEC_lower_bound (arm_exidx_entry_s
, map
, &map_key
,
2268 arm_compare_exidx_entries
);
2270 /* VEC_lower_bound finds the earliest ordered insertion
2271 point. If the following symbol starts at this exact
2272 address, we use that; otherwise, the preceding
2273 exception table entry covers this address. */
2274 if (idx
< VEC_length (arm_exidx_entry_s
, map
))
2276 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
);
2277 if (map_sym
->addr
== map_key
.addr
)
2280 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2281 return map_sym
->entry
;
2287 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
- 1);
2289 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2290 return map_sym
->entry
;
2299 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2300 instruction list from the ARM exception table entry ENTRY, allocate and
2301 return a prologue cache structure describing how to unwind this frame.
2303 Return NULL if the unwinding instruction list contains a "spare",
2304 "reserved" or "refuse to unwind" instruction as defined in section
2305 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2306 for the ARM Architecture" document. */
2308 static struct arm_prologue_cache
*
2309 arm_exidx_fill_cache (struct frame_info
*this_frame
, gdb_byte
*entry
)
2314 struct arm_prologue_cache
*cache
;
2315 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2316 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2322 /* Whenever we reload SP, we actually have to retrieve its
2323 actual value in the current frame. */
2326 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2328 int reg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2329 vsp
= get_frame_register_unsigned (this_frame
, reg
);
2333 CORE_ADDR addr
= cache
->saved_regs
[ARM_SP_REGNUM
].addr
;
2334 vsp
= get_frame_memory_unsigned (this_frame
, addr
, 4);
2340 /* Decode next unwind instruction. */
2343 if ((insn
& 0xc0) == 0)
2345 int offset
= insn
& 0x3f;
2346 vsp
+= (offset
<< 2) + 4;
2348 else if ((insn
& 0xc0) == 0x40)
2350 int offset
= insn
& 0x3f;
2351 vsp
-= (offset
<< 2) + 4;
2353 else if ((insn
& 0xf0) == 0x80)
2355 int mask
= ((insn
& 0xf) << 8) | *entry
++;
2358 /* The special case of an all-zero mask identifies
2359 "Refuse to unwind". We return NULL to fall back
2360 to the prologue analyzer. */
2364 /* Pop registers r4..r15 under mask. */
2365 for (i
= 0; i
< 12; i
++)
2366 if (mask
& (1 << i
))
2368 cache
->saved_regs
[4 + i
].addr
= vsp
;
2372 /* Special-case popping SP -- we need to reload vsp. */
2373 if (mask
& (1 << (ARM_SP_REGNUM
- 4)))
2376 else if ((insn
& 0xf0) == 0x90)
2378 int reg
= insn
& 0xf;
2380 /* Reserved cases. */
2381 if (reg
== ARM_SP_REGNUM
|| reg
== ARM_PC_REGNUM
)
2384 /* Set SP from another register and mark VSP for reload. */
2385 cache
->saved_regs
[ARM_SP_REGNUM
] = cache
->saved_regs
[reg
];
2388 else if ((insn
& 0xf0) == 0xa0)
2390 int count
= insn
& 0x7;
2391 int pop_lr
= (insn
& 0x8) != 0;
2394 /* Pop r4..r[4+count]. */
2395 for (i
= 0; i
<= count
; i
++)
2397 cache
->saved_regs
[4 + i
].addr
= vsp
;
2401 /* If indicated by flag, pop LR as well. */
2404 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= vsp
;
2408 else if (insn
== 0xb0)
2410 /* We could only have updated PC by popping into it; if so, it
2411 will show up as address. Otherwise, copy LR into PC. */
2412 if (!trad_frame_addr_p (cache
->saved_regs
, ARM_PC_REGNUM
))
2413 cache
->saved_regs
[ARM_PC_REGNUM
]
2414 = cache
->saved_regs
[ARM_LR_REGNUM
];
2419 else if (insn
== 0xb1)
2421 int mask
= *entry
++;
2424 /* All-zero mask and mask >= 16 is "spare". */
2425 if (mask
== 0 || mask
>= 16)
2428 /* Pop r0..r3 under mask. */
2429 for (i
= 0; i
< 4; i
++)
2430 if (mask
& (1 << i
))
2432 cache
->saved_regs
[i
].addr
= vsp
;
2436 else if (insn
== 0xb2)
2438 ULONGEST offset
= 0;
2443 offset
|= (*entry
& 0x7f) << shift
;
2446 while (*entry
++ & 0x80);
2448 vsp
+= 0x204 + (offset
<< 2);
2450 else if (insn
== 0xb3)
2452 int start
= *entry
>> 4;
2453 int count
= (*entry
++) & 0xf;
2456 /* Only registers D0..D15 are valid here. */
2457 if (start
+ count
>= 16)
2460 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2461 for (i
= 0; i
<= count
; i
++)
2463 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2467 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2470 else if ((insn
& 0xf8) == 0xb8)
2472 int count
= insn
& 0x7;
2475 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2476 for (i
= 0; i
<= count
; i
++)
2478 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2482 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2485 else if (insn
== 0xc6)
2487 int start
= *entry
>> 4;
2488 int count
= (*entry
++) & 0xf;
2491 /* Only registers WR0..WR15 are valid. */
2492 if (start
+ count
>= 16)
2495 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2496 for (i
= 0; i
<= count
; i
++)
2498 cache
->saved_regs
[ARM_WR0_REGNUM
+ start
+ i
].addr
= vsp
;
2502 else if (insn
== 0xc7)
2504 int mask
= *entry
++;
2507 /* All-zero mask and mask >= 16 is "spare". */
2508 if (mask
== 0 || mask
>= 16)
2511 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2512 for (i
= 0; i
< 4; i
++)
2513 if (mask
& (1 << i
))
2515 cache
->saved_regs
[ARM_WCGR0_REGNUM
+ i
].addr
= vsp
;
2519 else if ((insn
& 0xf8) == 0xc0)
2521 int count
= insn
& 0x7;
2524 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2525 for (i
= 0; i
<= count
; i
++)
2527 cache
->saved_regs
[ARM_WR0_REGNUM
+ 10 + i
].addr
= vsp
;
2531 else if (insn
== 0xc8)
2533 int start
= *entry
>> 4;
2534 int count
= (*entry
++) & 0xf;
2537 /* Only registers D0..D31 are valid. */
2538 if (start
+ count
>= 16)
2541 /* Pop VFP double-precision registers
2542 D[16+start]..D[16+start+count]. */
2543 for (i
= 0; i
<= count
; i
++)
2545 cache
->saved_regs
[ARM_D0_REGNUM
+ 16 + start
+ i
].addr
= vsp
;
2549 else if (insn
== 0xc9)
2551 int start
= *entry
>> 4;
2552 int count
= (*entry
++) & 0xf;
2555 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2556 for (i
= 0; i
<= count
; i
++)
2558 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2562 else if ((insn
& 0xf8) == 0xd0)
2564 int count
= insn
& 0x7;
2567 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2568 for (i
= 0; i
<= count
; i
++)
2570 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2576 /* Everything else is "spare". */
2581 /* If we restore SP from a register, assume this was the frame register.
2582 Otherwise just fall back to SP as frame register. */
2583 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2584 cache
->framereg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2586 cache
->framereg
= ARM_SP_REGNUM
;
2588 /* Determine offset to previous frame. */
2590 = vsp
- get_frame_register_unsigned (this_frame
, cache
->framereg
);
2592 /* We already got the previous SP. */
2593 cache
->prev_sp
= vsp
;
2598 /* Unwinding via ARM exception table entries. Note that the sniffer
2599 already computes a filled-in prologue cache, which is then used
2600 with the same arm_prologue_this_id and arm_prologue_prev_register
2601 routines also used for prologue-parsing based unwinding. */
2604 arm_exidx_unwind_sniffer (const struct frame_unwind
*self
,
2605 struct frame_info
*this_frame
,
2606 void **this_prologue_cache
)
2608 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2609 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2610 CORE_ADDR addr_in_block
, exidx_region
, func_start
;
2611 struct arm_prologue_cache
*cache
;
2614 /* See if we have an ARM exception table entry covering this address. */
2615 addr_in_block
= get_frame_address_in_block (this_frame
);
2616 entry
= arm_find_exidx_entry (addr_in_block
, &exidx_region
);
2620 /* The ARM exception table does not describe unwind information
2621 for arbitrary PC values, but is guaranteed to be correct only
2622 at call sites. We have to decide here whether we want to use
2623 ARM exception table information for this frame, or fall back
2624 to using prologue parsing. (Note that if we have DWARF CFI,
2625 this sniffer isn't even called -- CFI is always preferred.)
2627 Before we make this decision, however, we check whether we
2628 actually have *symbol* information for the current frame.
2629 If not, prologue parsing would not work anyway, so we might
2630 as well use the exception table and hope for the best. */
2631 if (find_pc_partial_function (addr_in_block
, NULL
, &func_start
, NULL
))
2635 /* If the next frame is "normal", we are at a call site in this
2636 frame, so exception information is guaranteed to be valid. */
2637 if (get_next_frame (this_frame
)
2638 && get_frame_type (get_next_frame (this_frame
)) == NORMAL_FRAME
)
2641 /* We also assume exception information is valid if we're currently
2642 blocked in a system call. The system library is supposed to
2643 ensure this, so that e.g. pthread cancellation works. */
2644 if (arm_frame_is_thumb (this_frame
))
2648 if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame
) - 2,
2649 2, byte_order_for_code
, &insn
)
2650 && (insn
& 0xff00) == 0xdf00 /* svc */)
2657 if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame
) - 4,
2658 4, byte_order_for_code
, &insn
)
2659 && (insn
& 0x0f000000) == 0x0f000000 /* svc */)
2663 /* Bail out if we don't know that exception information is valid. */
2667 /* The ARM exception index does not mark the *end* of the region
2668 covered by the entry, and some functions will not have any entry.
2669 To correctly recognize the end of the covered region, the linker
2670 should have inserted dummy records with a CANTUNWIND marker.
2672 Unfortunately, current versions of GNU ld do not reliably do
2673 this, and thus we may have found an incorrect entry above.
2674 As a (temporary) sanity check, we only use the entry if it
2675 lies *within* the bounds of the function. Note that this check
2676 might reject perfectly valid entries that just happen to cover
2677 multiple functions; therefore this check ought to be removed
2678 once the linker is fixed. */
2679 if (func_start
> exidx_region
)
2683 /* Decode the list of unwinding instructions into a prologue cache.
2684 Note that this may fail due to e.g. a "refuse to unwind" code. */
2685 cache
= arm_exidx_fill_cache (this_frame
, entry
);
2689 *this_prologue_cache
= cache
;
2693 struct frame_unwind arm_exidx_unwind
= {
2695 default_frame_unwind_stop_reason
,
2696 arm_prologue_this_id
,
2697 arm_prologue_prev_register
,
2699 arm_exidx_unwind_sniffer
2702 static struct arm_prologue_cache
*
2703 arm_make_epilogue_frame_cache (struct frame_info
*this_frame
)
2705 struct arm_prologue_cache
*cache
;
2708 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2709 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2711 /* Still rely on the offset calculated from prologue. */
2712 arm_scan_prologue (this_frame
, cache
);
2714 /* Since we are in epilogue, the SP has been restored. */
2715 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2717 /* Calculate actual addresses of saved registers using offsets
2718 determined by arm_scan_prologue. */
2719 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
2720 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
2721 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
2726 /* Implementation of function hook 'this_id' in
2727 'struct frame_uwnind' for epilogue unwinder. */
2730 arm_epilogue_frame_this_id (struct frame_info
*this_frame
,
2732 struct frame_id
*this_id
)
2734 struct arm_prologue_cache
*cache
;
2737 if (*this_cache
== NULL
)
2738 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2739 cache
= (struct arm_prologue_cache
*) *this_cache
;
2741 /* Use function start address as part of the frame ID. If we cannot
2742 identify the start address (due to missing symbol information),
2743 fall back to just using the current PC. */
2744 pc
= get_frame_pc (this_frame
);
2745 func
= get_frame_func (this_frame
);
2749 (*this_id
) = frame_id_build (cache
->prev_sp
, pc
);
2752 /* Implementation of function hook 'prev_register' in
2753 'struct frame_uwnind' for epilogue unwinder. */
2755 static struct value
*
2756 arm_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2757 void **this_cache
, int regnum
)
2759 if (*this_cache
== NULL
)
2760 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2762 return arm_prologue_prev_register (this_frame
, this_cache
, regnum
);
2765 static int arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
,
2767 static int thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
,
2770 /* Implementation of function hook 'sniffer' in
2771 'struct frame_uwnind' for epilogue unwinder. */
2774 arm_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2775 struct frame_info
*this_frame
,
2776 void **this_prologue_cache
)
2778 if (frame_relative_level (this_frame
) == 0)
2780 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2781 CORE_ADDR pc
= get_frame_pc (this_frame
);
2783 if (arm_frame_is_thumb (this_frame
))
2784 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
2786 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
2792 /* Frame unwinder from epilogue. */
2794 static const struct frame_unwind arm_epilogue_frame_unwind
=
2797 default_frame_unwind_stop_reason
,
2798 arm_epilogue_frame_this_id
,
2799 arm_epilogue_frame_prev_register
,
2801 arm_epilogue_frame_sniffer
,
2804 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2805 trampoline, return the target PC. Otherwise return 0.
2807 void call0a (char c, short s, int i, long l) {}
2811 (*pointer_to_call0a) (c, s, i, l);
2814 Instead of calling a stub library function _call_via_xx (xx is
2815 the register name), GCC may inline the trampoline in the object
2816 file as below (register r2 has the address of call0a).
2819 .type main, %function
2828 The trampoline 'bx r2' doesn't belong to main. */
2831 arm_skip_bx_reg (struct frame_info
*frame
, CORE_ADDR pc
)
2833 /* The heuristics of recognizing such trampoline is that FRAME is
2834 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2835 if (arm_frame_is_thumb (frame
))
2839 if (target_read_memory (pc
, buf
, 2) == 0)
2841 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2842 enum bfd_endian byte_order_for_code
2843 = gdbarch_byte_order_for_code (gdbarch
);
2845 = extract_unsigned_integer (buf
, 2, byte_order_for_code
);
2847 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
2850 = get_frame_register_unsigned (frame
, bits (insn
, 3, 6));
2852 /* Clear the LSB so that gdb core sets step-resume
2853 breakpoint at the right address. */
2854 return UNMAKE_THUMB_ADDR (dest
);
2862 static struct arm_prologue_cache
*
2863 arm_make_stub_cache (struct frame_info
*this_frame
)
2865 struct arm_prologue_cache
*cache
;
2867 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2868 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2870 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2875 /* Our frame ID for a stub frame is the current SP and LR. */
2878 arm_stub_this_id (struct frame_info
*this_frame
,
2880 struct frame_id
*this_id
)
2882 struct arm_prologue_cache
*cache
;
2884 if (*this_cache
== NULL
)
2885 *this_cache
= arm_make_stub_cache (this_frame
);
2886 cache
= (struct arm_prologue_cache
*) *this_cache
;
2888 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
2892 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
2893 struct frame_info
*this_frame
,
2894 void **this_prologue_cache
)
2896 CORE_ADDR addr_in_block
;
2898 CORE_ADDR pc
, start_addr
;
2901 addr_in_block
= get_frame_address_in_block (this_frame
);
2902 pc
= get_frame_pc (this_frame
);
2903 if (in_plt_section (addr_in_block
)
2904 /* We also use the stub winder if the target memory is unreadable
2905 to avoid having the prologue unwinder trying to read it. */
2906 || target_read_memory (pc
, dummy
, 4) != 0)
2909 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0
2910 && arm_skip_bx_reg (this_frame
, pc
) != 0)
2916 struct frame_unwind arm_stub_unwind
= {
2918 default_frame_unwind_stop_reason
,
2920 arm_prologue_prev_register
,
2922 arm_stub_unwind_sniffer
2925 /* Put here the code to store, into CACHE->saved_regs, the addresses
2926 of the saved registers of frame described by THIS_FRAME. CACHE is
2929 static struct arm_prologue_cache
*
2930 arm_m_exception_cache (struct frame_info
*this_frame
)
2932 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2933 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2934 struct arm_prologue_cache
*cache
;
2935 CORE_ADDR unwound_sp
;
2938 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2939 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2941 unwound_sp
= get_frame_register_unsigned (this_frame
,
2944 /* The hardware saves eight 32-bit words, comprising xPSR,
2945 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
2946 "B1.5.6 Exception entry behavior" in
2947 "ARMv7-M Architecture Reference Manual". */
2948 cache
->saved_regs
[0].addr
= unwound_sp
;
2949 cache
->saved_regs
[1].addr
= unwound_sp
+ 4;
2950 cache
->saved_regs
[2].addr
= unwound_sp
+ 8;
2951 cache
->saved_regs
[3].addr
= unwound_sp
+ 12;
2952 cache
->saved_regs
[12].addr
= unwound_sp
+ 16;
2953 cache
->saved_regs
[14].addr
= unwound_sp
+ 20;
2954 cache
->saved_regs
[15].addr
= unwound_sp
+ 24;
2955 cache
->saved_regs
[ARM_PS_REGNUM
].addr
= unwound_sp
+ 28;
2957 /* If bit 9 of the saved xPSR is set, then there is a four-byte
2958 aligner between the top of the 32-byte stack frame and the
2959 previous context's stack pointer. */
2960 cache
->prev_sp
= unwound_sp
+ 32;
2961 if (safe_read_memory_integer (unwound_sp
+ 28, 4, byte_order
, &xpsr
)
2962 && (xpsr
& (1 << 9)) != 0)
2963 cache
->prev_sp
+= 4;
2968 /* Implementation of function hook 'this_id' in
2969 'struct frame_uwnind'. */
2972 arm_m_exception_this_id (struct frame_info
*this_frame
,
2974 struct frame_id
*this_id
)
2976 struct arm_prologue_cache
*cache
;
2978 if (*this_cache
== NULL
)
2979 *this_cache
= arm_m_exception_cache (this_frame
);
2980 cache
= (struct arm_prologue_cache
*) *this_cache
;
2982 /* Our frame ID for a stub frame is the current SP and LR. */
2983 *this_id
= frame_id_build (cache
->prev_sp
,
2984 get_frame_pc (this_frame
));
2987 /* Implementation of function hook 'prev_register' in
2988 'struct frame_uwnind'. */
2990 static struct value
*
2991 arm_m_exception_prev_register (struct frame_info
*this_frame
,
2995 struct arm_prologue_cache
*cache
;
2997 if (*this_cache
== NULL
)
2998 *this_cache
= arm_m_exception_cache (this_frame
);
2999 cache
= (struct arm_prologue_cache
*) *this_cache
;
3001 /* The value was already reconstructed into PREV_SP. */
3002 if (prev_regnum
== ARM_SP_REGNUM
)
3003 return frame_unwind_got_constant (this_frame
, prev_regnum
,
3006 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
3010 /* Implementation of function hook 'sniffer' in
3011 'struct frame_uwnind'. */
3014 arm_m_exception_unwind_sniffer (const struct frame_unwind
*self
,
3015 struct frame_info
*this_frame
,
3016 void **this_prologue_cache
)
3018 CORE_ADDR this_pc
= get_frame_pc (this_frame
);
3020 /* No need to check is_m; this sniffer is only registered for
3021 M-profile architectures. */
3023 /* Check if exception frame returns to a magic PC value. */
3024 return arm_m_addr_is_magic (this_pc
);
3027 /* Frame unwinder for M-profile exceptions. */
3029 struct frame_unwind arm_m_exception_unwind
=
3032 default_frame_unwind_stop_reason
,
3033 arm_m_exception_this_id
,
3034 arm_m_exception_prev_register
,
3036 arm_m_exception_unwind_sniffer
3040 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
3042 struct arm_prologue_cache
*cache
;
3044 if (*this_cache
== NULL
)
3045 *this_cache
= arm_make_prologue_cache (this_frame
);
3046 cache
= (struct arm_prologue_cache
*) *this_cache
;
3048 return cache
->prev_sp
- cache
->framesize
;
3051 struct frame_base arm_normal_base
= {
3052 &arm_prologue_unwind
,
3053 arm_normal_frame_base
,
3054 arm_normal_frame_base
,
3055 arm_normal_frame_base
3058 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3059 dummy frame. The frame ID's base needs to match the TOS value
3060 saved by save_dummy_frame_tos() and returned from
3061 arm_push_dummy_call, and the PC needs to match the dummy frame's
3064 static struct frame_id
3065 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3067 return frame_id_build (get_frame_register_unsigned (this_frame
,
3069 get_frame_pc (this_frame
));
3072 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3073 be used to construct the previous frame's ID, after looking up the
3074 containing function). */
3077 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3080 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
3081 return arm_addr_bits_remove (gdbarch
, pc
);
3085 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3087 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
3090 static struct value
*
3091 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
3094 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
3096 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
3101 /* The PC is normally copied from the return column, which
3102 describes saves of LR. However, that version may have an
3103 extra bit set to indicate Thumb state. The bit is not
3105 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3106 return frame_unwind_got_constant (this_frame
, regnum
,
3107 arm_addr_bits_remove (gdbarch
, lr
));
3110 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3111 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
3112 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3113 if (IS_THUMB_ADDR (lr
))
3117 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
3120 internal_error (__FILE__
, __LINE__
,
3121 _("Unexpected register %d"), regnum
);
3126 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3127 struct dwarf2_frame_state_reg
*reg
,
3128 struct frame_info
*this_frame
)
3134 reg
->how
= DWARF2_FRAME_REG_FN
;
3135 reg
->loc
.fn
= arm_dwarf2_prev_register
;
3138 reg
->how
= DWARF2_FRAME_REG_CFA
;
3143 /* Implement the stack_frame_destroyed_p gdbarch method. */
3146 thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3148 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3149 unsigned int insn
, insn2
;
3150 int found_return
= 0, found_stack_adjust
= 0;
3151 CORE_ADDR func_start
, func_end
;
3155 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3158 /* The epilogue is a sequence of instructions along the following lines:
3160 - add stack frame size to SP or FP
3161 - [if frame pointer used] restore SP from FP
3162 - restore registers from SP [may include PC]
3163 - a return-type instruction [if PC wasn't already restored]
3165 In a first pass, we scan forward from the current PC and verify the
3166 instructions we find as compatible with this sequence, ending in a
3169 However, this is not sufficient to distinguish indirect function calls
3170 within a function from indirect tail calls in the epilogue in some cases.
3171 Therefore, if we didn't already find any SP-changing instruction during
3172 forward scan, we add a backward scanning heuristic to ensure we actually
3173 are in the epilogue. */
3176 while (scan_pc
< func_end
&& !found_return
)
3178 if (target_read_memory (scan_pc
, buf
, 2))
3182 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3184 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3186 else if (insn
== 0x46f7) /* mov pc, lr */
3188 else if (thumb_instruction_restores_sp (insn
))
3190 if ((insn
& 0xff00) == 0xbd00) /* pop <registers, PC> */
3193 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instruction */
3195 if (target_read_memory (scan_pc
, buf
, 2))
3199 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3201 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3203 if (insn2
& 0x8000) /* <registers> include PC. */
3206 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3207 && (insn2
& 0x0fff) == 0x0b04)
3209 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
3212 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3213 && (insn2
& 0x0e00) == 0x0a00)
3225 /* Since any instruction in the epilogue sequence, with the possible
3226 exception of return itself, updates the stack pointer, we need to
3227 scan backwards for at most one instruction. Try either a 16-bit or
3228 a 32-bit instruction. This is just a heuristic, so we do not worry
3229 too much about false positives. */
3231 if (pc
- 4 < func_start
)
3233 if (target_read_memory (pc
- 4, buf
, 4))
3236 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3237 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
3239 if (thumb_instruction_restores_sp (insn2
))
3240 found_stack_adjust
= 1;
3241 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3242 found_stack_adjust
= 1;
3243 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3244 && (insn2
& 0x0fff) == 0x0b04)
3245 found_stack_adjust
= 1;
3246 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3247 && (insn2
& 0x0e00) == 0x0a00)
3248 found_stack_adjust
= 1;
3250 return found_stack_adjust
;
3254 arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3256 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3259 CORE_ADDR func_start
, func_end
;
3261 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3264 /* We are in the epilogue if the previous instruction was a stack
3265 adjustment and the next instruction is a possible return (bx, mov
3266 pc, or pop). We could have to scan backwards to find the stack
3267 adjustment, or forwards to find the return, but this is a decent
3268 approximation. First scan forwards. */
3271 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3272 if (bits (insn
, 28, 31) != INST_NV
)
3274 if ((insn
& 0x0ffffff0) == 0x012fff10)
3277 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
3280 else if ((insn
& 0x0fff0000) == 0x08bd0000
3281 && (insn
& 0x0000c000) != 0)
3282 /* POP (LDMIA), including PC or LR. */
3289 /* Scan backwards. This is just a heuristic, so do not worry about
3290 false positives from mode changes. */
3292 if (pc
< func_start
+ 4)
3295 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
3296 if (arm_instruction_restores_sp (insn
))
3302 /* Implement the stack_frame_destroyed_p gdbarch method. */
3305 arm_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3307 if (arm_pc_is_thumb (gdbarch
, pc
))
3308 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
3310 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
3313 /* When arguments must be pushed onto the stack, they go on in reverse
3314 order. The code below implements a FILO (stack) to do this. */
3319 struct stack_item
*prev
;
3323 static struct stack_item
*
3324 push_stack_item (struct stack_item
*prev
, const gdb_byte
*contents
, int len
)
3326 struct stack_item
*si
;
3327 si
= XNEW (struct stack_item
);
3328 si
->data
= (gdb_byte
*) xmalloc (len
);
3331 memcpy (si
->data
, contents
, len
);
3335 static struct stack_item
*
3336 pop_stack_item (struct stack_item
*si
)
3338 struct stack_item
*dead
= si
;
3346 /* Return the alignment (in bytes) of the given type. */
3349 arm_type_align (struct type
*t
)
3355 t
= check_typedef (t
);
3356 switch (TYPE_CODE (t
))
3359 /* Should never happen. */
3360 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
3364 case TYPE_CODE_ENUM
:
3368 case TYPE_CODE_RANGE
:
3370 case TYPE_CODE_RVALUE_REF
:
3371 case TYPE_CODE_CHAR
:
3372 case TYPE_CODE_BOOL
:
3373 return TYPE_LENGTH (t
);
3375 case TYPE_CODE_ARRAY
:
3376 if (TYPE_VECTOR (t
))
3378 /* Use the natural alignment for vector types (the same for
3379 scalar type), but the maximum alignment is 64-bit. */
3380 if (TYPE_LENGTH (t
) > 8)
3383 return TYPE_LENGTH (t
);
3386 return arm_type_align (TYPE_TARGET_TYPE (t
));
3387 case TYPE_CODE_COMPLEX
:
3388 return arm_type_align (TYPE_TARGET_TYPE (t
));
3390 case TYPE_CODE_STRUCT
:
3391 case TYPE_CODE_UNION
:
3393 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
3395 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
3403 /* Possible base types for a candidate for passing and returning in
3406 enum arm_vfp_cprc_base_type
3415 /* The length of one element of base type B. */
3418 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
3422 case VFP_CPRC_SINGLE
:
3424 case VFP_CPRC_DOUBLE
:
3426 case VFP_CPRC_VEC64
:
3428 case VFP_CPRC_VEC128
:
3431 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3436 /* The character ('s', 'd' or 'q') for the type of VFP register used
3437 for passing base type B. */
3440 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
3444 case VFP_CPRC_SINGLE
:
3446 case VFP_CPRC_DOUBLE
:
3448 case VFP_CPRC_VEC64
:
3450 case VFP_CPRC_VEC128
:
3453 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3458 /* Determine whether T may be part of a candidate for passing and
3459 returning in VFP registers, ignoring the limit on the total number
3460 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3461 classification of the first valid component found; if it is not
3462 VFP_CPRC_UNKNOWN, all components must have the same classification
3463 as *BASE_TYPE. If it is found that T contains a type not permitted
3464 for passing and returning in VFP registers, a type differently
3465 classified from *BASE_TYPE, or two types differently classified
3466 from each other, return -1, otherwise return the total number of
3467 base-type elements found (possibly 0 in an empty structure or
3468 array). Vector types are not currently supported, matching the
3469 generic AAPCS support. */
3472 arm_vfp_cprc_sub_candidate (struct type
*t
,
3473 enum arm_vfp_cprc_base_type
*base_type
)
3475 t
= check_typedef (t
);
3476 switch (TYPE_CODE (t
))
3479 switch (TYPE_LENGTH (t
))
3482 if (*base_type
== VFP_CPRC_UNKNOWN
)
3483 *base_type
= VFP_CPRC_SINGLE
;
3484 else if (*base_type
!= VFP_CPRC_SINGLE
)
3489 if (*base_type
== VFP_CPRC_UNKNOWN
)
3490 *base_type
= VFP_CPRC_DOUBLE
;
3491 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3500 case TYPE_CODE_COMPLEX
:
3501 /* Arguments of complex T where T is one of the types float or
3502 double get treated as if they are implemented as:
3511 switch (TYPE_LENGTH (t
))
3514 if (*base_type
== VFP_CPRC_UNKNOWN
)
3515 *base_type
= VFP_CPRC_SINGLE
;
3516 else if (*base_type
!= VFP_CPRC_SINGLE
)
3521 if (*base_type
== VFP_CPRC_UNKNOWN
)
3522 *base_type
= VFP_CPRC_DOUBLE
;
3523 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3532 case TYPE_CODE_ARRAY
:
3534 if (TYPE_VECTOR (t
))
3536 /* A 64-bit or 128-bit containerized vector type are VFP
3538 switch (TYPE_LENGTH (t
))
3541 if (*base_type
== VFP_CPRC_UNKNOWN
)
3542 *base_type
= VFP_CPRC_VEC64
;
3545 if (*base_type
== VFP_CPRC_UNKNOWN
)
3546 *base_type
= VFP_CPRC_VEC128
;
3557 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
),
3561 if (TYPE_LENGTH (t
) == 0)
3563 gdb_assert (count
== 0);
3566 else if (count
== 0)
3568 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3569 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
3570 return TYPE_LENGTH (t
) / unitlen
;
3575 case TYPE_CODE_STRUCT
:
3580 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3584 if (!field_is_static (&TYPE_FIELD (t
, i
)))
3585 sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3587 if (sub_count
== -1)
3591 if (TYPE_LENGTH (t
) == 0)
3593 gdb_assert (count
== 0);
3596 else if (count
== 0)
3598 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3599 if (TYPE_LENGTH (t
) != unitlen
* count
)
3604 case TYPE_CODE_UNION
:
3609 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3611 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3613 if (sub_count
== -1)
3615 count
= (count
> sub_count
? count
: sub_count
);
3617 if (TYPE_LENGTH (t
) == 0)
3619 gdb_assert (count
== 0);
3622 else if (count
== 0)
3624 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3625 if (TYPE_LENGTH (t
) != unitlen
* count
)
3637 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3638 if passed to or returned from a non-variadic function with the VFP
3639 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3640 *BASE_TYPE to the base type for T and *COUNT to the number of
3641 elements of that base type before returning. */
3644 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
3647 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
3648 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
3649 if (c
<= 0 || c
> 4)
3656 /* Return 1 if the VFP ABI should be used for passing arguments to and
3657 returning values from a function of type FUNC_TYPE, 0
3661 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
3663 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3664 /* Variadic functions always use the base ABI. Assume that functions
3665 without debug info are not variadic. */
3666 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
3668 /* The VFP ABI is only supported as a variant of AAPCS. */
3669 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
3671 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
3674 /* We currently only support passing parameters in integer registers, which
3675 conforms with GCC's default model, and VFP argument passing following
3676 the VFP variant of AAPCS. Several other variants exist and
3677 we should probably support some of them based on the selected ABI. */
3680 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3681 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3682 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3683 CORE_ADDR struct_addr
)
3685 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3689 struct stack_item
*si
= NULL
;
3692 unsigned vfp_regs_free
= (1 << 16) - 1;
3694 /* Determine the type of this function and whether the VFP ABI
3696 ftype
= check_typedef (value_type (function
));
3697 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
3698 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
3699 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
3701 /* Set the return address. For the ARM, the return breakpoint is
3702 always at BP_ADDR. */
3703 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
3705 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
3707 /* Walk through the list of args and determine how large a temporary
3708 stack is required. Need to take care here as structs may be
3709 passed on the stack, and we have to push them. */
3712 argreg
= ARM_A1_REGNUM
;
3715 /* The struct_return pointer occupies the first parameter
3716 passing register. */
3720 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
3721 gdbarch_register_name (gdbarch
, argreg
),
3722 paddress (gdbarch
, struct_addr
));
3723 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
3727 for (argnum
= 0; argnum
< nargs
; argnum
++)
3730 struct type
*arg_type
;
3731 struct type
*target_type
;
3732 enum type_code typecode
;
3733 const bfd_byte
*val
;
3735 enum arm_vfp_cprc_base_type vfp_base_type
;
3737 int may_use_core_reg
= 1;
3739 arg_type
= check_typedef (value_type (args
[argnum
]));
3740 len
= TYPE_LENGTH (arg_type
);
3741 target_type
= TYPE_TARGET_TYPE (arg_type
);
3742 typecode
= TYPE_CODE (arg_type
);
3743 val
= value_contents (args
[argnum
]);
3745 align
= arm_type_align (arg_type
);
3746 /* Round alignment up to a whole number of words. */
3747 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
3748 /* Different ABIs have different maximum alignments. */
3749 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
3751 /* The APCS ABI only requires word alignment. */
3752 align
= INT_REGISTER_SIZE
;
3756 /* The AAPCS requires at most doubleword alignment. */
3757 if (align
> INT_REGISTER_SIZE
* 2)
3758 align
= INT_REGISTER_SIZE
* 2;
3762 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
3770 /* Because this is a CPRC it cannot go in a core register or
3771 cause a core register to be skipped for alignment.
3772 Either it goes in VFP registers and the rest of this loop
3773 iteration is skipped for this argument, or it goes on the
3774 stack (and the stack alignment code is correct for this
3776 may_use_core_reg
= 0;
3778 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
3779 shift
= unit_length
/ 4;
3780 mask
= (1 << (shift
* vfp_base_count
)) - 1;
3781 for (regno
= 0; regno
< 16; regno
+= shift
)
3782 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
3791 vfp_regs_free
&= ~(mask
<< regno
);
3792 reg_scaled
= regno
/ shift
;
3793 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
3794 for (i
= 0; i
< vfp_base_count
; i
++)
3798 if (reg_char
== 'q')
3799 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
3800 val
+ i
* unit_length
);
3803 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d",
3804 reg_char
, reg_scaled
+ i
);
3805 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3807 regcache_cooked_write (regcache
, regnum
,
3808 val
+ i
* unit_length
);
3815 /* This CPRC could not go in VFP registers, so all VFP
3816 registers are now marked as used. */
3821 /* Push stack padding for dowubleword alignment. */
3822 if (nstack
& (align
- 1))
3824 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3825 nstack
+= INT_REGISTER_SIZE
;
3828 /* Doubleword aligned quantities must go in even register pairs. */
3829 if (may_use_core_reg
3830 && argreg
<= ARM_LAST_ARG_REGNUM
3831 && align
> INT_REGISTER_SIZE
3835 /* If the argument is a pointer to a function, and it is a
3836 Thumb function, create a LOCAL copy of the value and set
3837 the THUMB bit in it. */
3838 if (TYPE_CODE_PTR
== typecode
3839 && target_type
!= NULL
3840 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
3842 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
3843 if (arm_pc_is_thumb (gdbarch
, regval
))
3845 bfd_byte
*copy
= (bfd_byte
*) alloca (len
);
3846 store_unsigned_integer (copy
, len
, byte_order
,
3847 MAKE_THUMB_ADDR (regval
));
3852 /* Copy the argument to general registers or the stack in
3853 register-sized pieces. Large arguments are split between
3854 registers and stack. */
3857 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
3859 = extract_unsigned_integer (val
, partial_len
, byte_order
);
3861 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
3863 /* The argument is being passed in a general purpose
3865 if (byte_order
== BFD_ENDIAN_BIG
)
3866 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
3868 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
3870 gdbarch_register_name
3872 phex (regval
, INT_REGISTER_SIZE
));
3873 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3878 gdb_byte buf
[INT_REGISTER_SIZE
];
3880 memset (buf
, 0, sizeof (buf
));
3881 store_unsigned_integer (buf
, partial_len
, byte_order
, regval
);
3883 /* Push the arguments onto the stack. */
3885 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
3887 si
= push_stack_item (si
, buf
, INT_REGISTER_SIZE
);
3888 nstack
+= INT_REGISTER_SIZE
;
3895 /* If we have an odd number of words to push, then decrement the stack
3896 by one word now, so first stack argument will be dword aligned. */
3903 write_memory (sp
, si
->data
, si
->len
);
3904 si
= pop_stack_item (si
);
3907 /* Finally, update teh SP register. */
3908 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
3914 /* Always align the frame to an 8-byte boundary. This is required on
3915 some platforms and harmless on the rest. */
3918 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3920 /* Align the stack to eight bytes. */
3921 return sp
& ~ (CORE_ADDR
) 7;
3925 print_fpu_flags (struct ui_file
*file
, int flags
)
3927 if (flags
& (1 << 0))
3928 fputs_filtered ("IVO ", file
);
3929 if (flags
& (1 << 1))
3930 fputs_filtered ("DVZ ", file
);
3931 if (flags
& (1 << 2))
3932 fputs_filtered ("OFL ", file
);
3933 if (flags
& (1 << 3))
3934 fputs_filtered ("UFL ", file
);
3935 if (flags
& (1 << 4))
3936 fputs_filtered ("INX ", file
);
3937 fputc_filtered ('\n', file
);
3940 /* Print interesting information about the floating point processor
3941 (if present) or emulator. */
3943 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
3944 struct frame_info
*frame
, const char *args
)
3946 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
3949 type
= (status
>> 24) & 127;
3950 if (status
& (1 << 31))
3951 fprintf_filtered (file
, _("Hardware FPU type %d\n"), type
);
3953 fprintf_filtered (file
, _("Software FPU type %d\n"), type
);
3954 /* i18n: [floating point unit] mask */
3955 fputs_filtered (_("mask: "), file
);
3956 print_fpu_flags (file
, status
>> 16);
3957 /* i18n: [floating point unit] flags */
3958 fputs_filtered (_("flags: "), file
);
3959 print_fpu_flags (file
, status
);
3962 /* Construct the ARM extended floating point type. */
3963 static struct type
*
3964 arm_ext_type (struct gdbarch
*gdbarch
)
3966 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3968 if (!tdep
->arm_ext_type
)
3970 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
3971 floatformats_arm_ext
);
3973 return tdep
->arm_ext_type
;
3976 static struct type
*
3977 arm_neon_double_type (struct gdbarch
*gdbarch
)
3979 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3981 if (tdep
->neon_double_type
== NULL
)
3983 struct type
*t
, *elem
;
3985 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
3987 elem
= builtin_type (gdbarch
)->builtin_uint8
;
3988 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
3989 elem
= builtin_type (gdbarch
)->builtin_uint16
;
3990 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
3991 elem
= builtin_type (gdbarch
)->builtin_uint32
;
3992 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
3993 elem
= builtin_type (gdbarch
)->builtin_uint64
;
3994 append_composite_type_field (t
, "u64", elem
);
3995 elem
= builtin_type (gdbarch
)->builtin_float
;
3996 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
3997 elem
= builtin_type (gdbarch
)->builtin_double
;
3998 append_composite_type_field (t
, "f64", elem
);
4000 TYPE_VECTOR (t
) = 1;
4001 TYPE_NAME (t
) = "neon_d";
4002 tdep
->neon_double_type
= t
;
4005 return tdep
->neon_double_type
;
4008 /* FIXME: The vector types are not correctly ordered on big-endian
4009 targets. Just as s0 is the low bits of d0, d0[0] is also the low
4010 bits of d0 - regardless of what unit size is being held in d0. So
4011 the offset of the first uint8 in d0 is 7, but the offset of the
4012 first float is 4. This code works as-is for little-endian
4015 static struct type
*
4016 arm_neon_quad_type (struct gdbarch
*gdbarch
)
4018 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4020 if (tdep
->neon_quad_type
== NULL
)
4022 struct type
*t
, *elem
;
4024 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
4026 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4027 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
4028 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4029 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
4030 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4031 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
4032 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4033 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
4034 elem
= builtin_type (gdbarch
)->builtin_float
;
4035 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
4036 elem
= builtin_type (gdbarch
)->builtin_double
;
4037 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
4039 TYPE_VECTOR (t
) = 1;
4040 TYPE_NAME (t
) = "neon_q";
4041 tdep
->neon_quad_type
= t
;
4044 return tdep
->neon_quad_type
;
4047 /* Return the GDB type object for the "standard" data type of data in
4050 static struct type
*
4051 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
4053 int num_regs
= gdbarch_num_regs (gdbarch
);
4055 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
4056 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
4057 return builtin_type (gdbarch
)->builtin_float
;
4059 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
4060 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
4061 return arm_neon_quad_type (gdbarch
);
4063 /* If the target description has register information, we are only
4064 in this function so that we can override the types of
4065 double-precision registers for NEON. */
4066 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
4068 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
4070 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
4071 && TYPE_CODE (t
) == TYPE_CODE_FLT
4072 && gdbarch_tdep (gdbarch
)->have_neon
)
4073 return arm_neon_double_type (gdbarch
);
4078 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
4080 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
4081 return builtin_type (gdbarch
)->builtin_void
;
4083 return arm_ext_type (gdbarch
);
4085 else if (regnum
== ARM_SP_REGNUM
)
4086 return builtin_type (gdbarch
)->builtin_data_ptr
;
4087 else if (regnum
== ARM_PC_REGNUM
)
4088 return builtin_type (gdbarch
)->builtin_func_ptr
;
4089 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
4090 /* These registers are only supported on targets which supply
4091 an XML description. */
4092 return builtin_type (gdbarch
)->builtin_int0
;
4094 return builtin_type (gdbarch
)->builtin_uint32
;
4097 /* Map a DWARF register REGNUM onto the appropriate GDB register
4101 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
4103 /* Core integer regs. */
4104 if (reg
>= 0 && reg
<= 15)
4107 /* Legacy FPA encoding. These were once used in a way which
4108 overlapped with VFP register numbering, so their use is
4109 discouraged, but GDB doesn't support the ARM toolchain
4110 which used them for VFP. */
4111 if (reg
>= 16 && reg
<= 23)
4112 return ARM_F0_REGNUM
+ reg
- 16;
4114 /* New assignments for the FPA registers. */
4115 if (reg
>= 96 && reg
<= 103)
4116 return ARM_F0_REGNUM
+ reg
- 96;
4118 /* WMMX register assignments. */
4119 if (reg
>= 104 && reg
<= 111)
4120 return ARM_WCGR0_REGNUM
+ reg
- 104;
4122 if (reg
>= 112 && reg
<= 127)
4123 return ARM_WR0_REGNUM
+ reg
- 112;
4125 if (reg
>= 192 && reg
<= 199)
4126 return ARM_WC0_REGNUM
+ reg
- 192;
4128 /* VFP v2 registers. A double precision value is actually
4129 in d1 rather than s2, but the ABI only defines numbering
4130 for the single precision registers. This will "just work"
4131 in GDB for little endian targets (we'll read eight bytes,
4132 starting in s0 and then progressing to s1), but will be
4133 reversed on big endian targets with VFP. This won't
4134 be a problem for the new Neon quad registers; you're supposed
4135 to use DW_OP_piece for those. */
4136 if (reg
>= 64 && reg
<= 95)
4140 xsnprintf (name_buf
, sizeof (name_buf
), "s%d", reg
- 64);
4141 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4145 /* VFP v3 / Neon registers. This range is also used for VFP v2
4146 registers, except that it now describes d0 instead of s0. */
4147 if (reg
>= 256 && reg
<= 287)
4151 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", reg
- 256);
4152 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4159 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4161 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
4164 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
4166 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
4167 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
4169 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
4170 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
4172 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
4173 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
4175 if (reg
< NUM_GREGS
)
4176 return SIM_ARM_R0_REGNUM
+ reg
;
4179 if (reg
< NUM_FREGS
)
4180 return SIM_ARM_FP0_REGNUM
+ reg
;
4183 if (reg
< NUM_SREGS
)
4184 return SIM_ARM_FPS_REGNUM
+ reg
;
4187 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
4190 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
4191 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
4192 NULL if an error occurs. BUF is freed. */
4195 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
4196 int old_len
, int new_len
)
4199 int bytes_to_read
= new_len
- old_len
;
4201 new_buf
= (gdb_byte
*) xmalloc (new_len
);
4202 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
4204 if (target_read_code (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
4212 /* An IT block is at most the 2-byte IT instruction followed by
4213 four 4-byte instructions. The furthest back we must search to
4214 find an IT block that affects the current instruction is thus
4215 2 + 3 * 4 == 14 bytes. */
4216 #define MAX_IT_BLOCK_PREFIX 14
4218 /* Use a quick scan if there are more than this many bytes of
4220 #define IT_SCAN_THRESHOLD 32
4222 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
4223 A breakpoint in an IT block may not be hit, depending on the
4226 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
4230 CORE_ADDR boundary
, func_start
;
4232 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
4233 int i
, any
, last_it
, last_it_count
;
4235 /* If we are using BKPT breakpoints, none of this is necessary. */
4236 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
4239 /* ARM mode does not have this problem. */
4240 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
4243 /* We are setting a breakpoint in Thumb code that could potentially
4244 contain an IT block. The first step is to find how much Thumb
4245 code there is; we do not need to read outside of known Thumb
4247 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
4249 /* Thumb-2 code must have mapping symbols to have a chance. */
4252 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
4254 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
4255 && func_start
> boundary
)
4256 boundary
= func_start
;
4258 /* Search for a candidate IT instruction. We have to do some fancy
4259 footwork to distinguish a real IT instruction from the second
4260 half of a 32-bit instruction, but there is no need for that if
4261 there's no candidate. */
4262 buf_len
= std::min (bpaddr
- boundary
, (CORE_ADDR
) MAX_IT_BLOCK_PREFIX
);
4264 /* No room for an IT instruction. */
4267 buf
= (gdb_byte
*) xmalloc (buf_len
);
4268 if (target_read_code (bpaddr
- buf_len
, buf
, buf_len
) != 0)
4271 for (i
= 0; i
< buf_len
; i
+= 2)
4273 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4274 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4287 /* OK, the code bytes before this instruction contain at least one
4288 halfword which resembles an IT instruction. We know that it's
4289 Thumb code, but there are still two possibilities. Either the
4290 halfword really is an IT instruction, or it is the second half of
4291 a 32-bit Thumb instruction. The only way we can tell is to
4292 scan forwards from a known instruction boundary. */
4293 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
4297 /* There's a lot of code before this instruction. Start with an
4298 optimistic search; it's easy to recognize halfwords that can
4299 not be the start of a 32-bit instruction, and use that to
4300 lock on to the instruction boundaries. */
4301 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
4304 buf_len
= IT_SCAN_THRESHOLD
;
4307 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
4309 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4310 if (thumb_insn_size (inst1
) == 2)
4317 /* At this point, if DEFINITE, BUF[I] is the first place we
4318 are sure that we know the instruction boundaries, and it is far
4319 enough from BPADDR that we could not miss an IT instruction
4320 affecting BPADDR. If ! DEFINITE, give up - start from a
4324 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
,
4328 buf_len
= bpaddr
- boundary
;
4334 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
4337 buf_len
= bpaddr
- boundary
;
4341 /* Scan forwards. Find the last IT instruction before BPADDR. */
4346 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4348 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4353 else if (inst1
& 0x0002)
4355 else if (inst1
& 0x0004)
4360 i
+= thumb_insn_size (inst1
);
4366 /* There wasn't really an IT instruction after all. */
4369 if (last_it_count
< 1)
4370 /* It was too far away. */
4373 /* This really is a trouble spot. Move the breakpoint to the IT
4375 return bpaddr
- buf_len
+ last_it
;
4378 /* ARM displaced stepping support.
4380 Generally ARM displaced stepping works as follows:
4382 1. When an instruction is to be single-stepped, it is first decoded by
4383 arm_process_displaced_insn. Depending on the type of instruction, it is
4384 then copied to a scratch location, possibly in a modified form. The
4385 copy_* set of functions performs such modification, as necessary. A
4386 breakpoint is placed after the modified instruction in the scratch space
4387 to return control to GDB. Note in particular that instructions which
4388 modify the PC will no longer do so after modification.
4390 2. The instruction is single-stepped, by setting the PC to the scratch
4391 location address, and resuming. Control returns to GDB when the
4394 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
4395 function used for the current instruction. This function's job is to
4396 put the CPU/memory state back to what it would have been if the
4397 instruction had been executed unmodified in its original location. */
4399 /* NOP instruction (mov r0, r0). */
4400 #define ARM_NOP 0xe1a00000
4401 #define THUMB_NOP 0x4600
4403 /* Helper for register reads for displaced stepping. In particular, this
4404 returns the PC as it would be seen by the instruction at its original
4408 displaced_read_reg (struct regcache
*regs
, arm_displaced_step_closure
*dsc
,
4412 CORE_ADDR from
= dsc
->insn_addr
;
4414 if (regno
== ARM_PC_REGNUM
)
4416 /* Compute pipeline offset:
4417 - When executing an ARM instruction, PC reads as the address of the
4418 current instruction plus 8.
4419 - When executing a Thumb instruction, PC reads as the address of the
4420 current instruction plus 4. */
4427 if (debug_displaced
)
4428 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
4429 (unsigned long) from
);
4430 return (ULONGEST
) from
;
4434 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
4435 if (debug_displaced
)
4436 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
4437 regno
, (unsigned long) ret
);
4443 displaced_in_arm_mode (struct regcache
*regs
)
4446 ULONGEST t_bit
= arm_psr_thumb_bit (regs
->arch ());
4448 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4450 return (ps
& t_bit
) == 0;
4453 /* Write to the PC as from a branch instruction. */
4456 branch_write_pc (struct regcache
*regs
, arm_displaced_step_closure
*dsc
,
4460 /* Note: If bits 0/1 are set, this branch would be unpredictable for
4461 architecture versions < 6. */
4462 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4463 val
& ~(ULONGEST
) 0x3);
4465 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4466 val
& ~(ULONGEST
) 0x1);
4469 /* Write to the PC as from a branch-exchange instruction. */
4472 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
4475 ULONGEST t_bit
= arm_psr_thumb_bit (regs
->arch ());
4477 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4481 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
4482 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
4484 else if ((val
& 2) == 0)
4486 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4487 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
4491 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
4492 mode, align dest to 4 bytes). */
4493 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
4494 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4495 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
4499 /* Write to the PC as if from a load instruction. */
4502 load_write_pc (struct regcache
*regs
, arm_displaced_step_closure
*dsc
,
4505 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
4506 bx_write_pc (regs
, val
);
4508 branch_write_pc (regs
, dsc
, val
);
4511 /* Write to the PC as if from an ALU instruction. */
4514 alu_write_pc (struct regcache
*regs
, arm_displaced_step_closure
*dsc
,
4517 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && !dsc
->is_thumb
)
4518 bx_write_pc (regs
, val
);
4520 branch_write_pc (regs
, dsc
, val
);
4523 /* Helper for writing to registers for displaced stepping. Writing to the PC
4524 has a varying effects depending on the instruction which does the write:
4525 this is controlled by the WRITE_PC argument. */
4528 displaced_write_reg (struct regcache
*regs
, arm_displaced_step_closure
*dsc
,
4529 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
4531 if (regno
== ARM_PC_REGNUM
)
4533 if (debug_displaced
)
4534 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
4535 (unsigned long) val
);
4538 case BRANCH_WRITE_PC
:
4539 branch_write_pc (regs
, dsc
, val
);
4543 bx_write_pc (regs
, val
);
4547 load_write_pc (regs
, dsc
, val
);
4551 alu_write_pc (regs
, dsc
, val
);
4554 case CANNOT_WRITE_PC
:
4555 warning (_("Instruction wrote to PC in an unexpected way when "
4556 "single-stepping"));
4560 internal_error (__FILE__
, __LINE__
,
4561 _("Invalid argument to displaced_write_reg"));
4564 dsc
->wrote_to_pc
= 1;
4568 if (debug_displaced
)
4569 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
4570 regno
, (unsigned long) val
);
4571 regcache_cooked_write_unsigned (regs
, regno
, val
);
4575 /* This function is used to concisely determine if an instruction INSN
4576 references PC. Register fields of interest in INSN should have the
4577 corresponding fields of BITMASK set to 0b1111. The function
4578 returns return 1 if any of these fields in INSN reference the PC
4579 (also 0b1111, r15), else it returns 0. */
4582 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
4584 uint32_t lowbit
= 1;
4586 while (bitmask
!= 0)
4590 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
4596 mask
= lowbit
* 0xf;
4598 if ((insn
& mask
) == mask
)
4607 /* The simplest copy function. Many instructions have the same effect no
4608 matter what address they are executed at: in those cases, use this. */
4611 arm_copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
4612 const char *iname
, arm_displaced_step_closure
*dsc
)
4614 if (debug_displaced
)
4615 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
4616 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
4619 dsc
->modinsn
[0] = insn
;
4625 thumb_copy_unmodified_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
4626 uint16_t insn2
, const char *iname
,
4627 arm_displaced_step_closure
*dsc
)
4629 if (debug_displaced
)
4630 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x %.4x, "
4631 "opcode/class '%s' unmodified\n", insn1
, insn2
,
4634 dsc
->modinsn
[0] = insn1
;
4635 dsc
->modinsn
[1] = insn2
;
4641 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
4644 thumb_copy_unmodified_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
4646 arm_displaced_step_closure
*dsc
)
4648 if (debug_displaced
)
4649 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x, "
4650 "opcode/class '%s' unmodified\n", insn
,
4653 dsc
->modinsn
[0] = insn
;
4658 /* Preload instructions with immediate offset. */
4661 cleanup_preload (struct gdbarch
*gdbarch
,
4662 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
4664 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4665 if (!dsc
->u
.preload
.immed
)
4666 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
4670 install_preload (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4671 arm_displaced_step_closure
*dsc
, unsigned int rn
)
4674 /* Preload instructions:
4676 {pli/pld} [rn, #+/-imm]
4678 {pli/pld} [r0, #+/-imm]. */
4680 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4681 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4682 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4683 dsc
->u
.preload
.immed
= 1;
4685 dsc
->cleanup
= &cleanup_preload
;
4689 arm_copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4690 arm_displaced_step_closure
*dsc
)
4692 unsigned int rn
= bits (insn
, 16, 19);
4694 if (!insn_references_pc (insn
, 0x000f0000ul
))
4695 return arm_copy_unmodified (gdbarch
, insn
, "preload", dsc
);
4697 if (debug_displaced
)
4698 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4699 (unsigned long) insn
);
4701 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4703 install_preload (gdbarch
, regs
, dsc
, rn
);
4709 thumb2_copy_preload (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
4710 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
4712 unsigned int rn
= bits (insn1
, 0, 3);
4713 unsigned int u_bit
= bit (insn1
, 7);
4714 int imm12
= bits (insn2
, 0, 11);
4717 if (rn
!= ARM_PC_REGNUM
)
4718 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "preload", dsc
);
4720 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
4721 PLD (literal) Encoding T1. */
4722 if (debug_displaced
)
4723 fprintf_unfiltered (gdb_stdlog
,
4724 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
4725 (unsigned int) dsc
->insn_addr
, u_bit
? '+' : '-',
4731 /* Rewrite instruction {pli/pld} PC imm12 into:
4732 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
4736 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
4738 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4739 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4741 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
4743 displaced_write_reg (regs
, dsc
, 0, pc_val
, CANNOT_WRITE_PC
);
4744 displaced_write_reg (regs
, dsc
, 1, imm12
, CANNOT_WRITE_PC
);
4745 dsc
->u
.preload
.immed
= 0;
4747 /* {pli/pld} [r0, r1] */
4748 dsc
->modinsn
[0] = insn1
& 0xfff0;
4749 dsc
->modinsn
[1] = 0xf001;
4752 dsc
->cleanup
= &cleanup_preload
;
4756 /* Preload instructions with register offset. */
4759 install_preload_reg(struct gdbarch
*gdbarch
, struct regcache
*regs
,
4760 arm_displaced_step_closure
*dsc
, unsigned int rn
,
4763 ULONGEST rn_val
, rm_val
;
4765 /* Preload register-offset instructions:
4767 {pli/pld} [rn, rm {, shift}]
4769 {pli/pld} [r0, r1 {, shift}]. */
4771 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4772 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4773 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4774 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
4775 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4776 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
4777 dsc
->u
.preload
.immed
= 0;
4779 dsc
->cleanup
= &cleanup_preload
;
4783 arm_copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
4784 struct regcache
*regs
,
4785 arm_displaced_step_closure
*dsc
)
4787 unsigned int rn
= bits (insn
, 16, 19);
4788 unsigned int rm
= bits (insn
, 0, 3);
4791 if (!insn_references_pc (insn
, 0x000f000ful
))
4792 return arm_copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
4794 if (debug_displaced
)
4795 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4796 (unsigned long) insn
);
4798 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
4800 install_preload_reg (gdbarch
, regs
, dsc
, rn
, rm
);
4804 /* Copy/cleanup coprocessor load and store instructions. */
4807 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
4808 struct regcache
*regs
,
4809 arm_displaced_step_closure
*dsc
)
4811 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 0);
4813 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4815 if (dsc
->u
.ldst
.writeback
)
4816 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
4820 install_copro_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4821 arm_displaced_step_closure
*dsc
,
4822 int writeback
, unsigned int rn
)
4826 /* Coprocessor load/store instructions:
4828 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
4830 {stc/stc2} [r0, #+/-imm].
4832 ldc/ldc2 are handled identically. */
4834 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4835 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4836 /* PC should be 4-byte aligned. */
4837 rn_val
= rn_val
& 0xfffffffc;
4838 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4840 dsc
->u
.ldst
.writeback
= writeback
;
4841 dsc
->u
.ldst
.rn
= rn
;
4843 dsc
->cleanup
= &cleanup_copro_load_store
;
4847 arm_copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
4848 struct regcache
*regs
,
4849 arm_displaced_step_closure
*dsc
)
4851 unsigned int rn
= bits (insn
, 16, 19);
4853 if (!insn_references_pc (insn
, 0x000f0000ul
))
4854 return arm_copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
4856 if (debug_displaced
)
4857 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4858 "load/store insn %.8lx\n", (unsigned long) insn
);
4860 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4862 install_copro_load_store (gdbarch
, regs
, dsc
, bit (insn
, 25), rn
);
4868 thumb2_copy_copro_load_store (struct gdbarch
*gdbarch
, uint16_t insn1
,
4869 uint16_t insn2
, struct regcache
*regs
,
4870 arm_displaced_step_closure
*dsc
)
4872 unsigned int rn
= bits (insn1
, 0, 3);
4874 if (rn
!= ARM_PC_REGNUM
)
4875 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
4876 "copro load/store", dsc
);
4878 if (debug_displaced
)
4879 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4880 "load/store insn %.4x%.4x\n", insn1
, insn2
);
4882 dsc
->modinsn
[0] = insn1
& 0xfff0;
4883 dsc
->modinsn
[1] = insn2
;
4886 /* This function is called for copying instruction LDC/LDC2/VLDR, which
4887 doesn't support writeback, so pass 0. */
4888 install_copro_load_store (gdbarch
, regs
, dsc
, 0, rn
);
4893 /* Clean up branch instructions (actually perform the branch, by setting
4897 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4898 arm_displaced_step_closure
*dsc
)
4900 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
4901 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
4902 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
4903 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
4908 if (dsc
->u
.branch
.link
)
4910 /* The value of LR should be the next insn of current one. In order
4911 not to confuse logic hanlding later insn `bx lr', if current insn mode
4912 is Thumb, the bit 0 of LR value should be set to 1. */
4913 ULONGEST next_insn_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
4916 next_insn_addr
|= 0x1;
4918 displaced_write_reg (regs
, dsc
, ARM_LR_REGNUM
, next_insn_addr
,
4922 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, dsc
->u
.branch
.dest
, write_pc
);
4925 /* Copy B/BL/BLX instructions with immediate destinations. */
4928 install_b_bl_blx (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4929 arm_displaced_step_closure
*dsc
,
4930 unsigned int cond
, int exchange
, int link
, long offset
)
4932 /* Implement "BL<cond> <label>" as:
4934 Preparation: cond <- instruction condition
4935 Insn: mov r0, r0 (nop)
4936 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
4938 B<cond> similar, but don't set r14 in cleanup. */
4940 dsc
->u
.branch
.cond
= cond
;
4941 dsc
->u
.branch
.link
= link
;
4942 dsc
->u
.branch
.exchange
= exchange
;
4944 dsc
->u
.branch
.dest
= dsc
->insn_addr
;
4945 if (link
&& exchange
)
4946 /* For BLX, offset is computed from the Align (PC, 4). */
4947 dsc
->u
.branch
.dest
= dsc
->u
.branch
.dest
& 0xfffffffc;
4950 dsc
->u
.branch
.dest
+= 4 + offset
;
4952 dsc
->u
.branch
.dest
+= 8 + offset
;
4954 dsc
->cleanup
= &cleanup_branch
;
4957 arm_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
4958 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
4960 unsigned int cond
= bits (insn
, 28, 31);
4961 int exchange
= (cond
== 0xf);
4962 int link
= exchange
|| bit (insn
, 24);
4965 if (debug_displaced
)
4966 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
4967 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
4968 (unsigned long) insn
);
4970 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
4971 then arrange the switch into Thumb mode. */
4972 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
4974 offset
= bits (insn
, 0, 23) << 2;
4976 if (bit (offset
, 25))
4977 offset
= offset
| ~0x3ffffff;
4979 dsc
->modinsn
[0] = ARM_NOP
;
4981 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
4986 thumb2_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint16_t insn1
,
4987 uint16_t insn2
, struct regcache
*regs
,
4988 arm_displaced_step_closure
*dsc
)
4990 int link
= bit (insn2
, 14);
4991 int exchange
= link
&& !bit (insn2
, 12);
4994 int j1
= bit (insn2
, 13);
4995 int j2
= bit (insn2
, 11);
4996 int s
= sbits (insn1
, 10, 10);
4997 int i1
= !(j1
^ bit (insn1
, 10));
4998 int i2
= !(j2
^ bit (insn1
, 10));
5000 if (!link
&& !exchange
) /* B */
5002 offset
= (bits (insn2
, 0, 10) << 1);
5003 if (bit (insn2
, 12)) /* Encoding T4 */
5005 offset
|= (bits (insn1
, 0, 9) << 12)
5011 else /* Encoding T3 */
5013 offset
|= (bits (insn1
, 0, 5) << 12)
5017 cond
= bits (insn1
, 6, 9);
5022 offset
= (bits (insn1
, 0, 9) << 12);
5023 offset
|= ((i2
<< 22) | (i1
<< 23) | (s
<< 24));
5024 offset
|= exchange
?
5025 (bits (insn2
, 1, 10) << 2) : (bits (insn2
, 0, 10) << 1);
5028 if (debug_displaced
)
5029 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s insn "
5030 "%.4x %.4x with offset %.8lx\n",
5031 link
? (exchange
) ? "blx" : "bl" : "b",
5032 insn1
, insn2
, offset
);
5034 dsc
->modinsn
[0] = THUMB_NOP
;
5036 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5040 /* Copy B Thumb instructions. */
5042 thumb_copy_b (struct gdbarch
*gdbarch
, uint16_t insn
,
5043 arm_displaced_step_closure
*dsc
)
5045 unsigned int cond
= 0;
5047 unsigned short bit_12_15
= bits (insn
, 12, 15);
5048 CORE_ADDR from
= dsc
->insn_addr
;
5050 if (bit_12_15
== 0xd)
5052 /* offset = SignExtend (imm8:0, 32) */
5053 offset
= sbits ((insn
<< 1), 0, 8);
5054 cond
= bits (insn
, 8, 11);
5056 else if (bit_12_15
== 0xe) /* Encoding T2 */
5058 offset
= sbits ((insn
<< 1), 0, 11);
5062 if (debug_displaced
)
5063 fprintf_unfiltered (gdb_stdlog
,
5064 "displaced: copying b immediate insn %.4x "
5065 "with offset %d\n", insn
, offset
);
5067 dsc
->u
.branch
.cond
= cond
;
5068 dsc
->u
.branch
.link
= 0;
5069 dsc
->u
.branch
.exchange
= 0;
5070 dsc
->u
.branch
.dest
= from
+ 4 + offset
;
5072 dsc
->modinsn
[0] = THUMB_NOP
;
5074 dsc
->cleanup
= &cleanup_branch
;
5079 /* Copy BX/BLX with register-specified destinations. */
5082 install_bx_blx_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5083 arm_displaced_step_closure
*dsc
, int link
,
5084 unsigned int cond
, unsigned int rm
)
5086 /* Implement {BX,BLX}<cond> <reg>" as:
5088 Preparation: cond <- instruction condition
5089 Insn: mov r0, r0 (nop)
5090 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
5092 Don't set r14 in cleanup for BX. */
5094 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, dsc
, rm
);
5096 dsc
->u
.branch
.cond
= cond
;
5097 dsc
->u
.branch
.link
= link
;
5099 dsc
->u
.branch
.exchange
= 1;
5101 dsc
->cleanup
= &cleanup_branch
;
5105 arm_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5106 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
5108 unsigned int cond
= bits (insn
, 28, 31);
5111 int link
= bit (insn
, 5);
5112 unsigned int rm
= bits (insn
, 0, 3);
5114 if (debug_displaced
)
5115 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx",
5116 (unsigned long) insn
);
5118 dsc
->modinsn
[0] = ARM_NOP
;
5120 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, cond
, rm
);
5125 thumb_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5126 struct regcache
*regs
,
5127 arm_displaced_step_closure
*dsc
)
5129 int link
= bit (insn
, 7);
5130 unsigned int rm
= bits (insn
, 3, 6);
5132 if (debug_displaced
)
5133 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x",
5134 (unsigned short) insn
);
5136 dsc
->modinsn
[0] = THUMB_NOP
;
5138 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, INST_AL
, rm
);
5144 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
5147 cleanup_alu_imm (struct gdbarch
*gdbarch
,
5148 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
5150 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5151 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5152 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5153 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5157 arm_copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5158 arm_displaced_step_closure
*dsc
)
5160 unsigned int rn
= bits (insn
, 16, 19);
5161 unsigned int rd
= bits (insn
, 12, 15);
5162 unsigned int op
= bits (insn
, 21, 24);
5163 int is_mov
= (op
== 0xd);
5164 ULONGEST rd_val
, rn_val
;
5166 if (!insn_references_pc (insn
, 0x000ff000ul
))
5167 return arm_copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
5169 if (debug_displaced
)
5170 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
5171 "%.8lx\n", is_mov
? "move" : "ALU",
5172 (unsigned long) insn
);
5174 /* Instruction is of form:
5176 <op><cond> rd, [rn,] #imm
5180 Preparation: tmp1, tmp2 <- r0, r1;
5182 Insn: <op><cond> r0, r1, #imm
5183 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5186 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5187 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5188 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5189 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5190 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5191 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5195 dsc
->modinsn
[0] = insn
& 0xfff00fff;
5197 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
5199 dsc
->cleanup
= &cleanup_alu_imm
;
5205 thumb2_copy_alu_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5206 uint16_t insn2
, struct regcache
*regs
,
5207 arm_displaced_step_closure
*dsc
)
5209 unsigned int op
= bits (insn1
, 5, 8);
5210 unsigned int rn
, rm
, rd
;
5211 ULONGEST rd_val
, rn_val
;
5213 rn
= bits (insn1
, 0, 3); /* Rn */
5214 rm
= bits (insn2
, 0, 3); /* Rm */
5215 rd
= bits (insn2
, 8, 11); /* Rd */
5217 /* This routine is only called for instruction MOV. */
5218 gdb_assert (op
== 0x2 && rn
== 0xf);
5220 if (rm
!= ARM_PC_REGNUM
&& rd
!= ARM_PC_REGNUM
)
5221 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ALU imm", dsc
);
5223 if (debug_displaced
)
5224 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x%.4x\n",
5225 "ALU", insn1
, insn2
);
5227 /* Instruction is of form:
5229 <op><cond> rd, [rn,] #imm
5233 Preparation: tmp1, tmp2 <- r0, r1;
5235 Insn: <op><cond> r0, r1, #imm
5236 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5239 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5240 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5241 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5242 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5243 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5244 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5247 dsc
->modinsn
[0] = insn1
;
5248 dsc
->modinsn
[1] = ((insn2
& 0xf0f0) | 0x1);
5251 dsc
->cleanup
= &cleanup_alu_imm
;
5256 /* Copy/cleanup arithmetic/logic insns with register RHS. */
5259 cleanup_alu_reg (struct gdbarch
*gdbarch
,
5260 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
5265 rd_val
= displaced_read_reg (regs
, dsc
, 0);
5267 for (i
= 0; i
< 3; i
++)
5268 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5270 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5274 install_alu_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5275 arm_displaced_step_closure
*dsc
,
5276 unsigned int rd
, unsigned int rn
, unsigned int rm
)
5278 ULONGEST rd_val
, rn_val
, rm_val
;
5280 /* Instruction is of form:
5282 <op><cond> rd, [rn,] rm [, <shift>]
5286 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
5287 r0, r1, r2 <- rd, rn, rm
5288 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
5289 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
5292 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5293 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5294 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5295 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5296 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5297 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5298 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5299 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5300 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5303 dsc
->cleanup
= &cleanup_alu_reg
;
5307 arm_copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5308 arm_displaced_step_closure
*dsc
)
5310 unsigned int op
= bits (insn
, 21, 24);
5311 int is_mov
= (op
== 0xd);
5313 if (!insn_references_pc (insn
, 0x000ff00ful
))
5314 return arm_copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
5316 if (debug_displaced
)
5317 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
5318 is_mov
? "move" : "ALU", (unsigned long) insn
);
5321 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
5323 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
5325 install_alu_reg (gdbarch
, regs
, dsc
, bits (insn
, 12, 15), bits (insn
, 16, 19),
5331 thumb_copy_alu_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5332 struct regcache
*regs
,
5333 arm_displaced_step_closure
*dsc
)
5337 rm
= bits (insn
, 3, 6);
5338 rd
= (bit (insn
, 7) << 3) | bits (insn
, 0, 2);
5340 if (rd
!= ARM_PC_REGNUM
&& rm
!= ARM_PC_REGNUM
)
5341 return thumb_copy_unmodified_16bit (gdbarch
, insn
, "ALU reg", dsc
);
5343 if (debug_displaced
)
5344 fprintf_unfiltered (gdb_stdlog
, "displaced: copying ALU reg insn %.4x\n",
5345 (unsigned short) insn
);
5347 dsc
->modinsn
[0] = ((insn
& 0xff00) | 0x10);
5349 install_alu_reg (gdbarch
, regs
, dsc
, rd
, rd
, rm
);
5354 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
5357 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
5358 struct regcache
*regs
,
5359 arm_displaced_step_closure
*dsc
)
5361 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5364 for (i
= 0; i
< 4; i
++)
5365 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5367 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5371 install_alu_shifted_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5372 arm_displaced_step_closure
*dsc
,
5373 unsigned int rd
, unsigned int rn
, unsigned int rm
,
5377 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
5379 /* Instruction is of form:
5381 <op><cond> rd, [rn,] rm, <shift> rs
5385 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
5386 r0, r1, r2, r3 <- rd, rn, rm, rs
5387 Insn: <op><cond> r0, r1, r2, <shift> r3
5389 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
5393 for (i
= 0; i
< 4; i
++)
5394 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
5396 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5397 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5398 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5399 rs_val
= displaced_read_reg (regs
, dsc
, rs
);
5400 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5401 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5402 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5403 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
5405 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
5409 arm_copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5410 struct regcache
*regs
,
5411 arm_displaced_step_closure
*dsc
)
5413 unsigned int op
= bits (insn
, 21, 24);
5414 int is_mov
= (op
== 0xd);
5415 unsigned int rd
, rn
, rm
, rs
;
5417 if (!insn_references_pc (insn
, 0x000fff0ful
))
5418 return arm_copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
5420 if (debug_displaced
)
5421 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
5422 "%.8lx\n", is_mov
? "move" : "ALU",
5423 (unsigned long) insn
);
5425 rn
= bits (insn
, 16, 19);
5426 rm
= bits (insn
, 0, 3);
5427 rs
= bits (insn
, 8, 11);
5428 rd
= bits (insn
, 12, 15);
5431 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
5433 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
5435 install_alu_shifted_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
, rs
);
5440 /* Clean up load instructions. */
5443 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5444 arm_displaced_step_closure
*dsc
)
5446 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
5448 rt_val
= displaced_read_reg (regs
, dsc
, 0);
5449 if (dsc
->u
.ldst
.xfersize
== 8)
5450 rt_val2
= displaced_read_reg (regs
, dsc
, 1);
5451 rn_val
= displaced_read_reg (regs
, dsc
, 2);
5453 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5454 if (dsc
->u
.ldst
.xfersize
> 4)
5455 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5456 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5457 if (!dsc
->u
.ldst
.immed
)
5458 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5460 /* Handle register writeback. */
5461 if (dsc
->u
.ldst
.writeback
)
5462 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5463 /* Put result in right place. */
5464 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
5465 if (dsc
->u
.ldst
.xfersize
== 8)
5466 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
5469 /* Clean up store instructions. */
5472 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5473 arm_displaced_step_closure
*dsc
)
5475 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 2);
5477 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5478 if (dsc
->u
.ldst
.xfersize
> 4)
5479 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5480 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5481 if (!dsc
->u
.ldst
.immed
)
5482 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5483 if (!dsc
->u
.ldst
.restore_r4
)
5484 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
5487 if (dsc
->u
.ldst
.writeback
)
5488 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5491 /* Copy "extra" load/store instructions. These are halfword/doubleword
5492 transfers, which have a different encoding to byte/word transfers. */
5495 arm_copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unprivileged
,
5496 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
5498 unsigned int op1
= bits (insn
, 20, 24);
5499 unsigned int op2
= bits (insn
, 5, 6);
5500 unsigned int rt
= bits (insn
, 12, 15);
5501 unsigned int rn
= bits (insn
, 16, 19);
5502 unsigned int rm
= bits (insn
, 0, 3);
5503 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
5504 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
5505 int immed
= (op1
& 0x4) != 0;
5507 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
5509 if (!insn_references_pc (insn
, 0x000ff00ful
))
5510 return arm_copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
5512 if (debug_displaced
)
5513 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
5514 "insn %.8lx\n", unprivileged
? "unprivileged " : "",
5515 (unsigned long) insn
);
5517 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
5520 internal_error (__FILE__
, __LINE__
,
5521 _("copy_extra_ld_st: instruction decode error"));
5523 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5524 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5525 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5527 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5529 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5530 if (bytesize
[opcode
] == 8)
5531 rt_val2
= displaced_read_reg (regs
, dsc
, rt
+ 1);
5532 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5534 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5536 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5537 if (bytesize
[opcode
] == 8)
5538 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
5539 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5541 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5544 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
5545 dsc
->u
.ldst
.rn
= rn
;
5546 dsc
->u
.ldst
.immed
= immed
;
5547 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
5548 dsc
->u
.ldst
.restore_r4
= 0;
5551 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
5553 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
5554 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5556 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
5558 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
5559 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5561 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
5566 /* Copy byte/half word/word loads and stores. */
5569 install_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5570 arm_displaced_step_closure
*dsc
, int load
,
5571 int immed
, int writeback
, int size
, int usermode
,
5572 int rt
, int rm
, int rn
)
5574 ULONGEST rt_val
, rn_val
, rm_val
= 0;
5576 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5577 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5579 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5581 dsc
->tmp
[4] = displaced_read_reg (regs
, dsc
, 4);
5583 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5584 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5586 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5588 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5589 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5591 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5593 dsc
->u
.ldst
.xfersize
= size
;
5594 dsc
->u
.ldst
.rn
= rn
;
5595 dsc
->u
.ldst
.immed
= immed
;
5596 dsc
->u
.ldst
.writeback
= writeback
;
5598 /* To write PC we can do:
5600 Before this sequence of instructions:
5601 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
5602 r2 is the Rn value got from dispalced_read_reg.
5604 Insn1: push {pc} Write address of STR instruction + offset on stack
5605 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
5606 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
5607 = addr(Insn1) + offset - addr(Insn3) - 8
5609 Insn4: add r4, r4, #8 r4 = offset - 8
5610 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
5612 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
5614 Otherwise we don't know what value to write for PC, since the offset is
5615 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
5616 of this can be found in Section "Saving from r15" in
5617 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
5619 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5624 thumb2_copy_load_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
5625 uint16_t insn2
, struct regcache
*regs
,
5626 arm_displaced_step_closure
*dsc
, int size
)
5628 unsigned int u_bit
= bit (insn1
, 7);
5629 unsigned int rt
= bits (insn2
, 12, 15);
5630 int imm12
= bits (insn2
, 0, 11);
5633 if (debug_displaced
)
5634 fprintf_unfiltered (gdb_stdlog
,
5635 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
5636 (unsigned int) dsc
->insn_addr
, rt
, u_bit
? '+' : '-',
5642 /* Rewrite instruction LDR Rt imm12 into:
5644 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
5648 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
5651 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5652 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5653 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5655 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
5657 pc_val
= pc_val
& 0xfffffffc;
5659 displaced_write_reg (regs
, dsc
, 2, pc_val
, CANNOT_WRITE_PC
);
5660 displaced_write_reg (regs
, dsc
, 3, imm12
, CANNOT_WRITE_PC
);
5664 dsc
->u
.ldst
.xfersize
= size
;
5665 dsc
->u
.ldst
.immed
= 0;
5666 dsc
->u
.ldst
.writeback
= 0;
5667 dsc
->u
.ldst
.restore_r4
= 0;
5669 /* LDR R0, R2, R3 */
5670 dsc
->modinsn
[0] = 0xf852;
5671 dsc
->modinsn
[1] = 0x3;
5674 dsc
->cleanup
= &cleanup_load
;
5680 thumb2_copy_load_reg_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5681 uint16_t insn2
, struct regcache
*regs
,
5682 arm_displaced_step_closure
*dsc
,
5683 int writeback
, int immed
)
5685 unsigned int rt
= bits (insn2
, 12, 15);
5686 unsigned int rn
= bits (insn1
, 0, 3);
5687 unsigned int rm
= bits (insn2
, 0, 3); /* Only valid if !immed. */
5688 /* In LDR (register), there is also a register Rm, which is not allowed to
5689 be PC, so we don't have to check it. */
5691 if (rt
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
5692 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "load",
5695 if (debug_displaced
)
5696 fprintf_unfiltered (gdb_stdlog
,
5697 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
5698 rt
, rn
, insn1
, insn2
);
5700 install_load_store (gdbarch
, regs
, dsc
, 1, immed
, writeback
, 4,
5703 dsc
->u
.ldst
.restore_r4
= 0;
5706 /* ldr[b]<cond> rt, [rn, #imm], etc.
5708 ldr[b]<cond> r0, [r2, #imm]. */
5710 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5711 dsc
->modinsn
[1] = insn2
& 0x0fff;
5714 /* ldr[b]<cond> rt, [rn, rm], etc.
5716 ldr[b]<cond> r0, [r2, r3]. */
5718 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5719 dsc
->modinsn
[1] = (insn2
& 0x0ff0) | 0x3;
5729 arm_copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
5730 struct regcache
*regs
,
5731 arm_displaced_step_closure
*dsc
,
5732 int load
, int size
, int usermode
)
5734 int immed
= !bit (insn
, 25);
5735 int writeback
= (bit (insn
, 24) == 0 || bit (insn
, 21) != 0);
5736 unsigned int rt
= bits (insn
, 12, 15);
5737 unsigned int rn
= bits (insn
, 16, 19);
5738 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
5740 if (!insn_references_pc (insn
, 0x000ff00ful
))
5741 return arm_copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
5743 if (debug_displaced
)
5744 fprintf_unfiltered (gdb_stdlog
,
5745 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
5746 load
? (size
== 1 ? "ldrb" : "ldr")
5747 : (size
== 1 ? "strb" : "str"), usermode
? "t" : "",
5749 (unsigned long) insn
);
5751 install_load_store (gdbarch
, regs
, dsc
, load
, immed
, writeback
, size
,
5752 usermode
, rt
, rm
, rn
);
5754 if (load
|| rt
!= ARM_PC_REGNUM
)
5756 dsc
->u
.ldst
.restore_r4
= 0;
5759 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
5761 {ldr,str}[b]<cond> r0, [r2, #imm]. */
5762 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5764 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
5766 {ldr,str}[b]<cond> r0, [r2, r3]. */
5767 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5771 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
5772 dsc
->u
.ldst
.restore_r4
= 1;
5773 dsc
->modinsn
[0] = 0xe92d8000; /* push {pc} */
5774 dsc
->modinsn
[1] = 0xe8bd0010; /* pop {r4} */
5775 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
5776 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
5777 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
5781 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
5783 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
5788 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5793 /* Cleanup LDM instructions with fully-populated register list. This is an
5794 unfortunate corner case: it's impossible to implement correctly by modifying
5795 the instruction. The issue is as follows: we have an instruction,
5799 which we must rewrite to avoid loading PC. A possible solution would be to
5800 do the load in two halves, something like (with suitable cleanup
5804 ldm[id][ab] r8!, {r0-r7}
5806 ldm[id][ab] r8, {r7-r14}
5809 but at present there's no suitable place for <temp>, since the scratch space
5810 is overwritten before the cleanup routine is called. For now, we simply
5811 emulate the instruction. */
5814 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5815 arm_displaced_step_closure
*dsc
)
5817 int inc
= dsc
->u
.block
.increment
;
5818 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
5819 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
5820 uint32_t regmask
= dsc
->u
.block
.regmask
;
5821 int regno
= inc
? 0 : 15;
5822 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
5823 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
5824 && (regmask
& 0x8000) != 0;
5825 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5826 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
5827 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5832 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
5833 sensible we can do here. Complain loudly. */
5834 if (exception_return
)
5835 error (_("Cannot single-step exception return"));
5837 /* We don't handle any stores here for now. */
5838 gdb_assert (dsc
->u
.block
.load
!= 0);
5840 if (debug_displaced
)
5841 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
5842 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
5843 dsc
->u
.block
.increment
? "inc" : "dec",
5844 dsc
->u
.block
.before
? "before" : "after");
5851 while (regno
<= ARM_PC_REGNUM
&& (regmask
& (1 << regno
)) == 0)
5854 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
5857 xfer_addr
+= bump_before
;
5859 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
5860 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
5862 xfer_addr
+= bump_after
;
5864 regmask
&= ~(1 << regno
);
5867 if (dsc
->u
.block
.writeback
)
5868 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
5872 /* Clean up an STM which included the PC in the register list. */
5875 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5876 arm_displaced_step_closure
*dsc
)
5878 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5879 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
5880 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
5881 CORE_ADDR stm_insn_addr
;
5884 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5886 /* If condition code fails, there's nothing else to do. */
5887 if (!store_executed
)
5890 if (dsc
->u
.block
.increment
)
5892 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
5894 if (dsc
->u
.block
.before
)
5899 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
5901 if (dsc
->u
.block
.before
)
5905 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
5906 stm_insn_addr
= dsc
->scratch_base
;
5907 offset
= pc_val
- stm_insn_addr
;
5909 if (debug_displaced
)
5910 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
5911 "STM instruction\n", offset
);
5913 /* Rewrite the stored PC to the proper value for the non-displaced original
5915 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
5916 dsc
->insn_addr
+ offset
);
5919 /* Clean up an LDM which includes the PC in the register list. We clumped all
5920 the registers in the transferred list into a contiguous range r0...rX (to
5921 avoid loading PC directly and losing control of the debugged program), so we
5922 must undo that here. */
5925 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
5926 struct regcache
*regs
,
5927 arm_displaced_step_closure
*dsc
)
5929 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5930 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
);
5931 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= ARM_PC_REGNUM
;
5932 unsigned int regs_loaded
= bitcount (mask
);
5933 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
5935 /* The method employed here will fail if the register list is fully populated
5936 (we need to avoid loading PC directly). */
5937 gdb_assert (num_to_shuffle
< 16);
5942 clobbered
= (1 << num_to_shuffle
) - 1;
5944 while (num_to_shuffle
> 0)
5946 if ((mask
& (1 << write_reg
)) != 0)
5948 unsigned int read_reg
= num_to_shuffle
- 1;
5950 if (read_reg
!= write_reg
)
5952 ULONGEST rval
= displaced_read_reg (regs
, dsc
, read_reg
);
5953 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
5954 if (debug_displaced
)
5955 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
5956 "loaded register r%d to r%d\n"), read_reg
,
5959 else if (debug_displaced
)
5960 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
5961 "r%d already in the right place\n"),
5964 clobbered
&= ~(1 << write_reg
);
5972 /* Restore any registers we scribbled over. */
5973 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
5975 if ((clobbered
& (1 << write_reg
)) != 0)
5977 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
5979 if (debug_displaced
)
5980 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
5981 "clobbered register r%d\n"), write_reg
);
5982 clobbered
&= ~(1 << write_reg
);
5986 /* Perform register writeback manually. */
5987 if (dsc
->u
.block
.writeback
)
5989 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
5991 if (dsc
->u
.block
.increment
)
5992 new_rn_val
+= regs_loaded
* 4;
5994 new_rn_val
-= regs_loaded
* 4;
5996 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
6001 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
6002 in user-level code (in particular exception return, ldm rn, {...pc}^). */
6005 arm_copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
,
6006 struct regcache
*regs
,
6007 arm_displaced_step_closure
*dsc
)
6009 int load
= bit (insn
, 20);
6010 int user
= bit (insn
, 22);
6011 int increment
= bit (insn
, 23);
6012 int before
= bit (insn
, 24);
6013 int writeback
= bit (insn
, 21);
6014 int rn
= bits (insn
, 16, 19);
6016 /* Block transfers which don't mention PC can be run directly
6018 if (rn
!= ARM_PC_REGNUM
&& (insn
& 0x8000) == 0)
6019 return arm_copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
6021 if (rn
== ARM_PC_REGNUM
)
6023 warning (_("displaced: Unpredictable LDM or STM with "
6024 "base register r15"));
6025 return arm_copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
6028 if (debug_displaced
)
6029 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6030 "%.8lx\n", (unsigned long) insn
);
6032 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6033 dsc
->u
.block
.rn
= rn
;
6035 dsc
->u
.block
.load
= load
;
6036 dsc
->u
.block
.user
= user
;
6037 dsc
->u
.block
.increment
= increment
;
6038 dsc
->u
.block
.before
= before
;
6039 dsc
->u
.block
.writeback
= writeback
;
6040 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
6042 dsc
->u
.block
.regmask
= insn
& 0xffff;
6046 if ((insn
& 0xffff) == 0xffff)
6048 /* LDM with a fully-populated register list. This case is
6049 particularly tricky. Implement for now by fully emulating the
6050 instruction (which might not behave perfectly in all cases, but
6051 these instructions should be rare enough for that not to matter
6053 dsc
->modinsn
[0] = ARM_NOP
;
6055 dsc
->cleanup
= &cleanup_block_load_all
;
6059 /* LDM of a list of registers which includes PC. Implement by
6060 rewriting the list of registers to be transferred into a
6061 contiguous chunk r0...rX before doing the transfer, then shuffling
6062 registers into the correct places in the cleanup routine. */
6063 unsigned int regmask
= insn
& 0xffff;
6064 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
6067 for (i
= 0; i
< num_in_list
; i
++)
6068 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6070 /* Writeback makes things complicated. We need to avoid clobbering
6071 the base register with one of the registers in our modified
6072 register list, but just using a different register can't work in
6075 ldm r14!, {r0-r13,pc}
6077 which would need to be rewritten as:
6081 but that can't work, because there's no free register for N.
6083 Solve this by turning off the writeback bit, and emulating
6084 writeback manually in the cleanup routine. */
6089 new_regmask
= (1 << num_in_list
) - 1;
6091 if (debug_displaced
)
6092 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6093 "{..., pc}: original reg list %.4x, modified "
6094 "list %.4x\n"), rn
, writeback
? "!" : "",
6095 (int) insn
& 0xffff, new_regmask
);
6097 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
6099 dsc
->cleanup
= &cleanup_block_load_pc
;
6104 /* STM of a list of registers which includes PC. Run the instruction
6105 as-is, but out of line: this will store the wrong value for the PC,
6106 so we must manually fix up the memory in the cleanup routine.
6107 Doing things this way has the advantage that we can auto-detect
6108 the offset of the PC write (which is architecture-dependent) in
6109 the cleanup routine. */
6110 dsc
->modinsn
[0] = insn
;
6112 dsc
->cleanup
= &cleanup_block_store_pc
;
6119 thumb2_copy_block_xfer (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6120 struct regcache
*regs
,
6121 arm_displaced_step_closure
*dsc
)
6123 int rn
= bits (insn1
, 0, 3);
6124 int load
= bit (insn1
, 4);
6125 int writeback
= bit (insn1
, 5);
6127 /* Block transfers which don't mention PC can be run directly
6129 if (rn
!= ARM_PC_REGNUM
&& (insn2
& 0x8000) == 0)
6130 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ldm/stm", dsc
);
6132 if (rn
== ARM_PC_REGNUM
)
6134 warning (_("displaced: Unpredictable LDM or STM with "
6135 "base register r15"));
6136 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6137 "unpredictable ldm/stm", dsc
);
6140 if (debug_displaced
)
6141 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6142 "%.4x%.4x\n", insn1
, insn2
);
6144 /* Clear bit 13, since it should be always zero. */
6145 dsc
->u
.block
.regmask
= (insn2
& 0xdfff);
6146 dsc
->u
.block
.rn
= rn
;
6148 dsc
->u
.block
.load
= load
;
6149 dsc
->u
.block
.user
= 0;
6150 dsc
->u
.block
.increment
= bit (insn1
, 7);
6151 dsc
->u
.block
.before
= bit (insn1
, 8);
6152 dsc
->u
.block
.writeback
= writeback
;
6153 dsc
->u
.block
.cond
= INST_AL
;
6154 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6158 if (dsc
->u
.block
.regmask
== 0xffff)
6160 /* This branch is impossible to happen. */
6165 unsigned int regmask
= dsc
->u
.block
.regmask
;
6166 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
6169 for (i
= 0; i
< num_in_list
; i
++)
6170 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6175 new_regmask
= (1 << num_in_list
) - 1;
6177 if (debug_displaced
)
6178 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6179 "{..., pc}: original reg list %.4x, modified "
6180 "list %.4x\n"), rn
, writeback
? "!" : "",
6181 (int) dsc
->u
.block
.regmask
, new_regmask
);
6183 dsc
->modinsn
[0] = insn1
;
6184 dsc
->modinsn
[1] = (new_regmask
& 0xffff);
6187 dsc
->cleanup
= &cleanup_block_load_pc
;
6192 dsc
->modinsn
[0] = insn1
;
6193 dsc
->modinsn
[1] = insn2
;
6195 dsc
->cleanup
= &cleanup_block_store_pc
;
6200 /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs.
6201 This is used to avoid a dependency on BFD's bfd_endian enum. */
6204 arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr
, int len
,
6207 return read_memory_unsigned_integer (memaddr
, len
,
6208 (enum bfd_endian
) byte_order
);
6211 /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */
6214 arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs
*self
,
6217 return gdbarch_addr_bits_remove (self
->regcache
->arch (), val
);
6220 /* Wrapper over syscall_next_pc for use in get_next_pcs. */
6223 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
)
6228 /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */
6231 arm_get_next_pcs_is_thumb (struct arm_get_next_pcs
*self
)
6233 return arm_is_thumb (self
->regcache
);
6236 /* single_step() is called just before we want to resume the inferior,
6237 if we want to single-step it but there is no hardware or kernel
6238 single-step support. We find the target of the coming instructions
6239 and breakpoint them. */
6241 std::vector
<CORE_ADDR
>
6242 arm_software_single_step (struct regcache
*regcache
)
6244 struct gdbarch
*gdbarch
= regcache
->arch ();
6245 struct arm_get_next_pcs next_pcs_ctx
;
6247 arm_get_next_pcs_ctor (&next_pcs_ctx
,
6248 &arm_get_next_pcs_ops
,
6249 gdbarch_byte_order (gdbarch
),
6250 gdbarch_byte_order_for_code (gdbarch
),
6254 std::vector
<CORE_ADDR
> next_pcs
= arm_get_next_pcs (&next_pcs_ctx
);
6256 for (CORE_ADDR
&pc_ref
: next_pcs
)
6257 pc_ref
= gdbarch_addr_bits_remove (gdbarch
, pc_ref
);
6262 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
6263 for Linux, where some SVC instructions must be treated specially. */
6266 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6267 arm_displaced_step_closure
*dsc
)
6269 CORE_ADDR resume_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
6271 if (debug_displaced
)
6272 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
6273 "%.8lx\n", (unsigned long) resume_addr
);
6275 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
6279 /* Common copy routine for svc instruciton. */
6282 install_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6283 arm_displaced_step_closure
*dsc
)
6285 /* Preparation: none.
6286 Insn: unmodified svc.
6287 Cleanup: pc <- insn_addr + insn_size. */
6289 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
6291 dsc
->wrote_to_pc
= 1;
6293 /* Allow OS-specific code to override SVC handling. */
6294 if (dsc
->u
.svc
.copy_svc_os
)
6295 return dsc
->u
.svc
.copy_svc_os (gdbarch
, regs
, dsc
);
6298 dsc
->cleanup
= &cleanup_svc
;
6304 arm_copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
,
6305 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
6308 if (debug_displaced
)
6309 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
6310 (unsigned long) insn
);
6312 dsc
->modinsn
[0] = insn
;
6314 return install_svc (gdbarch
, regs
, dsc
);
6318 thumb_copy_svc (struct gdbarch
*gdbarch
, uint16_t insn
,
6319 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
6322 if (debug_displaced
)
6323 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.4x\n",
6326 dsc
->modinsn
[0] = insn
;
6328 return install_svc (gdbarch
, regs
, dsc
);
6331 /* Copy undefined instructions. */
6334 arm_copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
6335 arm_displaced_step_closure
*dsc
)
6337 if (debug_displaced
)
6338 fprintf_unfiltered (gdb_stdlog
,
6339 "displaced: copying undefined insn %.8lx\n",
6340 (unsigned long) insn
);
6342 dsc
->modinsn
[0] = insn
;
6348 thumb_32bit_copy_undef (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6349 arm_displaced_step_closure
*dsc
)
6352 if (debug_displaced
)
6353 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn "
6354 "%.4x %.4x\n", (unsigned short) insn1
,
6355 (unsigned short) insn2
);
6357 dsc
->modinsn
[0] = insn1
;
6358 dsc
->modinsn
[1] = insn2
;
6364 /* Copy unpredictable instructions. */
6367 arm_copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
6368 arm_displaced_step_closure
*dsc
)
6370 if (debug_displaced
)
6371 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
6372 "%.8lx\n", (unsigned long) insn
);
6374 dsc
->modinsn
[0] = insn
;
6379 /* The decode_* functions are instruction decoding helpers. They mostly follow
6380 the presentation in the ARM ARM. */
6383 arm_decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
6384 struct regcache
*regs
,
6385 arm_displaced_step_closure
*dsc
)
6387 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
6388 unsigned int rn
= bits (insn
, 16, 19);
6390 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0x1) == 0x0)
6391 return arm_copy_unmodified (gdbarch
, insn
, "cps", dsc
);
6392 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0x1) == 0x1)
6393 return arm_copy_unmodified (gdbarch
, insn
, "setend", dsc
);
6394 else if ((op1
& 0x60) == 0x20)
6395 return arm_copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
6396 else if ((op1
& 0x71) == 0x40)
6397 return arm_copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store",
6399 else if ((op1
& 0x77) == 0x41)
6400 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6401 else if ((op1
& 0x77) == 0x45)
6402 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
6403 else if ((op1
& 0x77) == 0x51)
6406 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6408 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6410 else if ((op1
& 0x77) == 0x55)
6411 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6412 else if (op1
== 0x57)
6415 case 0x1: return arm_copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
6416 case 0x4: return arm_copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
6417 case 0x5: return arm_copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
6418 case 0x6: return arm_copy_unmodified (gdbarch
, insn
, "isb", dsc
);
6419 default: return arm_copy_unpred (gdbarch
, insn
, dsc
);
6421 else if ((op1
& 0x63) == 0x43)
6422 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6423 else if ((op2
& 0x1) == 0x0)
6424 switch (op1
& ~0x80)
6427 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6429 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
6430 case 0x71: case 0x75:
6432 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
6433 case 0x63: case 0x67: case 0x73: case 0x77:
6434 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6436 return arm_copy_undef (gdbarch
, insn
, dsc
);
6439 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
6443 arm_decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
6444 struct regcache
*regs
,
6445 arm_displaced_step_closure
*dsc
)
6447 if (bit (insn
, 27) == 0)
6448 return arm_decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
6449 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
6450 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
6453 return arm_copy_unmodified (gdbarch
, insn
, "srs", dsc
);
6456 return arm_copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
6458 case 0x4: case 0x5: case 0x6: case 0x7:
6459 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6462 switch ((insn
& 0xe00000) >> 21)
6464 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
6466 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6469 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6472 return arm_copy_undef (gdbarch
, insn
, dsc
);
6477 int rn_f
= (bits (insn
, 16, 19) == 0xf);
6478 switch ((insn
& 0xe00000) >> 21)
6481 /* ldc/ldc2 imm (undefined for rn == pc). */
6482 return rn_f
? arm_copy_undef (gdbarch
, insn
, dsc
)
6483 : arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6486 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6488 case 0x4: case 0x5: case 0x6: case 0x7:
6489 /* ldc/ldc2 lit (undefined for rn != pc). */
6490 return rn_f
? arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
6491 : arm_copy_undef (gdbarch
, insn
, dsc
);
6494 return arm_copy_undef (gdbarch
, insn
, dsc
);
6499 return arm_copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
6502 if (bits (insn
, 16, 19) == 0xf)
6504 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6506 return arm_copy_undef (gdbarch
, insn
, dsc
);
6510 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6512 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6516 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6518 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6521 return arm_copy_undef (gdbarch
, insn
, dsc
);
6525 /* Decode miscellaneous instructions in dp/misc encoding space. */
6528 arm_decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
6529 struct regcache
*regs
,
6530 arm_displaced_step_closure
*dsc
)
6532 unsigned int op2
= bits (insn
, 4, 6);
6533 unsigned int op
= bits (insn
, 21, 22);
6538 return arm_copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
6541 if (op
== 0x1) /* bx. */
6542 return arm_copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
6544 return arm_copy_unmodified (gdbarch
, insn
, "clz", dsc
);
6546 return arm_copy_undef (gdbarch
, insn
, dsc
);
6550 /* Not really supported. */
6551 return arm_copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
6553 return arm_copy_undef (gdbarch
, insn
, dsc
);
6557 return arm_copy_bx_blx_reg (gdbarch
, insn
,
6558 regs
, dsc
); /* blx register. */
6560 return arm_copy_undef (gdbarch
, insn
, dsc
);
6563 return arm_copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
6567 return arm_copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
6569 /* Not really supported. */
6570 return arm_copy_unmodified (gdbarch
, insn
, "smc", dsc
);
6574 return arm_copy_undef (gdbarch
, insn
, dsc
);
6579 arm_decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
,
6580 struct regcache
*regs
,
6581 arm_displaced_step_closure
*dsc
)
6584 switch (bits (insn
, 20, 24))
6587 return arm_copy_unmodified (gdbarch
, insn
, "movw", dsc
);
6590 return arm_copy_unmodified (gdbarch
, insn
, "movt", dsc
);
6592 case 0x12: case 0x16:
6593 return arm_copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
6596 return arm_copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
6600 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
6602 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
6603 return arm_copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
6604 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
6605 return arm_copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
6606 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
6607 return arm_decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
6608 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
6609 return arm_copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
6610 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
6611 return arm_copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
6612 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
6613 return arm_copy_unmodified (gdbarch
, insn
, "synch", dsc
);
6614 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
6615 /* 2nd arg means "unprivileged". */
6616 return arm_copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
6620 /* Should be unreachable. */
6625 arm_decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
6626 struct regcache
*regs
,
6627 arm_displaced_step_closure
*dsc
)
6629 int a
= bit (insn
, 25), b
= bit (insn
, 4);
6630 uint32_t op1
= bits (insn
, 20, 24);
6632 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
6633 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
6634 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 0);
6635 else if ((!a
&& (op1
& 0x17) == 0x02)
6636 || (a
&& (op1
& 0x17) == 0x02 && !b
))
6637 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 1);
6638 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
6639 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
6640 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 0);
6641 else if ((!a
&& (op1
& 0x17) == 0x03)
6642 || (a
&& (op1
& 0x17) == 0x03 && !b
))
6643 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 1);
6644 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
6645 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
6646 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
6647 else if ((!a
&& (op1
& 0x17) == 0x06)
6648 || (a
&& (op1
& 0x17) == 0x06 && !b
))
6649 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
6650 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
6651 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
6652 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
6653 else if ((!a
&& (op1
& 0x17) == 0x07)
6654 || (a
&& (op1
& 0x17) == 0x07 && !b
))
6655 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
6657 /* Should be unreachable. */
6662 arm_decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
6663 arm_displaced_step_closure
*dsc
)
6665 switch (bits (insn
, 20, 24))
6667 case 0x00: case 0x01: case 0x02: case 0x03:
6668 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
6670 case 0x04: case 0x05: case 0x06: case 0x07:
6671 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
6673 case 0x08: case 0x09: case 0x0a: case 0x0b:
6674 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
6675 return arm_copy_unmodified (gdbarch
, insn
,
6676 "decode/pack/unpack/saturate/reverse", dsc
);
6679 if (bits (insn
, 5, 7) == 0) /* op2. */
6681 if (bits (insn
, 12, 15) == 0xf)
6682 return arm_copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
6684 return arm_copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
6687 return arm_copy_undef (gdbarch
, insn
, dsc
);
6689 case 0x1a: case 0x1b:
6690 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6691 return arm_copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
6693 return arm_copy_undef (gdbarch
, insn
, dsc
);
6695 case 0x1c: case 0x1d:
6696 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
6698 if (bits (insn
, 0, 3) == 0xf)
6699 return arm_copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
6701 return arm_copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
6704 return arm_copy_undef (gdbarch
, insn
, dsc
);
6706 case 0x1e: case 0x1f:
6707 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6708 return arm_copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
6710 return arm_copy_undef (gdbarch
, insn
, dsc
);
6713 /* Should be unreachable. */
6718 arm_decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, uint32_t insn
,
6719 struct regcache
*regs
,
6720 arm_displaced_step_closure
*dsc
)
6723 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6725 return arm_copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
6729 arm_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
6730 struct regcache
*regs
,
6731 arm_displaced_step_closure
*dsc
)
6733 unsigned int opcode
= bits (insn
, 20, 24);
6737 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
6738 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
6740 case 0x08: case 0x0a: case 0x0c: case 0x0e:
6741 case 0x12: case 0x16:
6742 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
6744 case 0x09: case 0x0b: case 0x0d: case 0x0f:
6745 case 0x13: case 0x17:
6746 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
6748 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6749 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6750 /* Note: no writeback for these instructions. Bit 25 will always be
6751 zero though (via caller), so the following works OK. */
6752 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6755 /* Should be unreachable. */
6759 /* Decode shifted register instructions. */
6762 thumb2_decode_dp_shift_reg (struct gdbarch
*gdbarch
, uint16_t insn1
,
6763 uint16_t insn2
, struct regcache
*regs
,
6764 arm_displaced_step_closure
*dsc
)
6766 /* PC is only allowed to be used in instruction MOV. */
6768 unsigned int op
= bits (insn1
, 5, 8);
6769 unsigned int rn
= bits (insn1
, 0, 3);
6771 if (op
== 0x2 && rn
== 0xf) /* MOV */
6772 return thumb2_copy_alu_imm (gdbarch
, insn1
, insn2
, regs
, dsc
);
6774 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6775 "dp (shift reg)", dsc
);
6779 /* Decode extension register load/store. Exactly the same as
6780 arm_decode_ext_reg_ld_st. */
6783 thumb2_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint16_t insn1
,
6784 uint16_t insn2
, struct regcache
*regs
,
6785 arm_displaced_step_closure
*dsc
)
6787 unsigned int opcode
= bits (insn1
, 4, 8);
6791 case 0x04: case 0x05:
6792 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6793 "vfp/neon vmov", dsc
);
6795 case 0x08: case 0x0c: /* 01x00 */
6796 case 0x0a: case 0x0e: /* 01x10 */
6797 case 0x12: case 0x16: /* 10x10 */
6798 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6799 "vfp/neon vstm/vpush", dsc
);
6801 case 0x09: case 0x0d: /* 01x01 */
6802 case 0x0b: case 0x0f: /* 01x11 */
6803 case 0x13: case 0x17: /* 10x11 */
6804 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6805 "vfp/neon vldm/vpop", dsc
);
6807 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6808 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6810 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6811 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
, regs
, dsc
);
6814 /* Should be unreachable. */
6819 arm_decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
,
6820 struct regcache
*regs
, arm_displaced_step_closure
*dsc
)
6822 unsigned int op1
= bits (insn
, 20, 25);
6823 int op
= bit (insn
, 4);
6824 unsigned int coproc
= bits (insn
, 8, 11);
6826 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
6827 return arm_decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
6828 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
6829 && (coproc
& 0xe) != 0xa)
6831 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6832 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
6833 && (coproc
& 0xe) != 0xa)
6834 /* ldc/ldc2 imm/lit. */
6835 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6836 else if ((op1
& 0x3e) == 0x00)
6837 return arm_copy_undef (gdbarch
, insn
, dsc
);
6838 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
6839 return arm_copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
6840 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
6841 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6842 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
6843 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6844 else if ((op1
& 0x30) == 0x20 && !op
)
6846 if ((coproc
& 0xe) == 0xa)
6847 return arm_copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
6849 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6851 else if ((op1
& 0x30) == 0x20 && op
)
6852 return arm_copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
6853 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
6854 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6855 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
6856 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6857 else if ((op1
& 0x30) == 0x30)
6858 return arm_copy_svc (gdbarch
, insn
, regs
, dsc
);
6860 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
6864 thumb2_decode_svc_copro (struct gdbarch
*gdbarch
, uint16_t insn1
,
6865 uint16_t insn2
, struct regcache
*regs
,
6866 arm_displaced_step_closure
*dsc
)
6868 unsigned int coproc
= bits (insn2
, 8, 11);
6869 unsigned int bit_5_8
= bits (insn1
, 5, 8);
6870 unsigned int bit_9
= bit (insn1
, 9);
6871 unsigned int bit_4
= bit (insn1
, 4);
6876 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6877 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
6879 else if (bit_5_8
== 0) /* UNDEFINED. */
6880 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
6883 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
6884 if ((coproc
& 0xe) == 0xa)
6885 return thumb2_decode_ext_reg_ld_st (gdbarch
, insn1
, insn2
, regs
,
6887 else /* coproc is not 101x. */
6889 if (bit_4
== 0) /* STC/STC2. */
6890 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6892 else /* LDC/LDC2 {literal, immeidate}. */
6893 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
,
6899 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "coproc", dsc
);
6905 install_pc_relative (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6906 arm_displaced_step_closure
*dsc
, int rd
)
6912 Preparation: Rd <- PC
6918 int val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
6919 displaced_write_reg (regs
, dsc
, rd
, val
, CANNOT_WRITE_PC
);
6923 thumb_copy_pc_relative_16bit (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6924 arm_displaced_step_closure
*dsc
,
6925 int rd
, unsigned int imm
)
6928 /* Encoding T2: ADDS Rd, #imm */
6929 dsc
->modinsn
[0] = (0x3000 | (rd
<< 8) | imm
);
6931 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
6937 thumb_decode_pc_relative_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
6938 struct regcache
*regs
,
6939 arm_displaced_step_closure
*dsc
)
6941 unsigned int rd
= bits (insn
, 8, 10);
6942 unsigned int imm8
= bits (insn
, 0, 7);
6944 if (debug_displaced
)
6945 fprintf_unfiltered (gdb_stdlog
,
6946 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
6949 return thumb_copy_pc_relative_16bit (gdbarch
, regs
, dsc
, rd
, imm8
);
6953 thumb_copy_pc_relative_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
6954 uint16_t insn2
, struct regcache
*regs
,
6955 arm_displaced_step_closure
*dsc
)
6957 unsigned int rd
= bits (insn2
, 8, 11);
6958 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
6959 extract raw immediate encoding rather than computing immediate. When
6960 generating ADD or SUB instruction, we can simply perform OR operation to
6961 set immediate into ADD. */
6962 unsigned int imm_3_8
= insn2
& 0x70ff;
6963 unsigned int imm_i
= insn1
& 0x0400; /* Clear all bits except bit 10. */
6965 if (debug_displaced
)
6966 fprintf_unfiltered (gdb_stdlog
,
6967 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
6968 rd
, imm_i
, imm_3_8
, insn1
, insn2
);
6970 if (bit (insn1
, 7)) /* Encoding T2 */
6972 /* Encoding T3: SUB Rd, Rd, #imm */
6973 dsc
->modinsn
[0] = (0xf1a0 | rd
| imm_i
);
6974 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
6976 else /* Encoding T3 */
6978 /* Encoding T3: ADD Rd, Rd, #imm */
6979 dsc
->modinsn
[0] = (0xf100 | rd
| imm_i
);
6980 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
6984 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
6990 thumb_copy_16bit_ldr_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
6991 struct regcache
*regs
,
6992 arm_displaced_step_closure
*dsc
)
6994 unsigned int rt
= bits (insn1
, 8, 10);
6996 int imm8
= (bits (insn1
, 0, 7) << 2);
7002 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
7004 Insn: LDR R0, [R2, R3];
7005 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
7007 if (debug_displaced
)
7008 fprintf_unfiltered (gdb_stdlog
,
7009 "displaced: copying thumb ldr r%d [pc #%d]\n"
7012 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
7013 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
7014 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
7015 pc
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
7016 /* The assembler calculates the required value of the offset from the
7017 Align(PC,4) value of this instruction to the label. */
7018 pc
= pc
& 0xfffffffc;
7020 displaced_write_reg (regs
, dsc
, 2, pc
, CANNOT_WRITE_PC
);
7021 displaced_write_reg (regs
, dsc
, 3, imm8
, CANNOT_WRITE_PC
);
7024 dsc
->u
.ldst
.xfersize
= 4;
7026 dsc
->u
.ldst
.immed
= 0;
7027 dsc
->u
.ldst
.writeback
= 0;
7028 dsc
->u
.ldst
.restore_r4
= 0;
7030 dsc
->modinsn
[0] = 0x58d0; /* ldr r0, [r2, r3]*/
7032 dsc
->cleanup
= &cleanup_load
;
7037 /* Copy Thumb cbnz/cbz insruction. */
7040 thumb_copy_cbnz_cbz (struct gdbarch
*gdbarch
, uint16_t insn1
,
7041 struct regcache
*regs
,
7042 arm_displaced_step_closure
*dsc
)
7044 int non_zero
= bit (insn1
, 11);
7045 unsigned int imm5
= (bit (insn1
, 9) << 6) | (bits (insn1
, 3, 7) << 1);
7046 CORE_ADDR from
= dsc
->insn_addr
;
7047 int rn
= bits (insn1
, 0, 2);
7048 int rn_val
= displaced_read_reg (regs
, dsc
, rn
);
7050 dsc
->u
.branch
.cond
= (rn_val
&& non_zero
) || (!rn_val
&& !non_zero
);
7051 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
7052 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
7053 condition is false, let it be, cleanup_branch will do nothing. */
7054 if (dsc
->u
.branch
.cond
)
7056 dsc
->u
.branch
.cond
= INST_AL
;
7057 dsc
->u
.branch
.dest
= from
+ 4 + imm5
;
7060 dsc
->u
.branch
.dest
= from
+ 2;
7062 dsc
->u
.branch
.link
= 0;
7063 dsc
->u
.branch
.exchange
= 0;
7065 if (debug_displaced
)
7066 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s [r%d = 0x%x]"
7067 " insn %.4x to %.8lx\n", non_zero
? "cbnz" : "cbz",
7068 rn
, rn_val
, insn1
, dsc
->u
.branch
.dest
);
7070 dsc
->modinsn
[0] = THUMB_NOP
;
7072 dsc
->cleanup
= &cleanup_branch
;
7076 /* Copy Table Branch Byte/Halfword */
7078 thumb2_copy_table_branch (struct gdbarch
*gdbarch
, uint16_t insn1
,
7079 uint16_t insn2
, struct regcache
*regs
,
7080 arm_displaced_step_closure
*dsc
)
7082 ULONGEST rn_val
, rm_val
;
7083 int is_tbh
= bit (insn2
, 4);
7084 CORE_ADDR halfwords
= 0;
7085 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7087 rn_val
= displaced_read_reg (regs
, dsc
, bits (insn1
, 0, 3));
7088 rm_val
= displaced_read_reg (regs
, dsc
, bits (insn2
, 0, 3));
7094 target_read_memory (rn_val
+ 2 * rm_val
, buf
, 2);
7095 halfwords
= extract_unsigned_integer (buf
, 2, byte_order
);
7101 target_read_memory (rn_val
+ rm_val
, buf
, 1);
7102 halfwords
= extract_unsigned_integer (buf
, 1, byte_order
);
7105 if (debug_displaced
)
7106 fprintf_unfiltered (gdb_stdlog
, "displaced: %s base 0x%x offset 0x%x"
7107 " offset 0x%x\n", is_tbh
? "tbh" : "tbb",
7108 (unsigned int) rn_val
, (unsigned int) rm_val
,
7109 (unsigned int) halfwords
);
7111 dsc
->u
.branch
.cond
= INST_AL
;
7112 dsc
->u
.branch
.link
= 0;
7113 dsc
->u
.branch
.exchange
= 0;
7114 dsc
->u
.branch
.dest
= dsc
->insn_addr
+ 4 + 2 * halfwords
;
7116 dsc
->cleanup
= &cleanup_branch
;
7122 cleanup_pop_pc_16bit_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7123 arm_displaced_step_closure
*dsc
)
7126 int val
= displaced_read_reg (regs
, dsc
, 7);
7127 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, val
, BX_WRITE_PC
);
7130 val
= displaced_read_reg (regs
, dsc
, 8);
7131 displaced_write_reg (regs
, dsc
, 7, val
, CANNOT_WRITE_PC
);
7134 displaced_write_reg (regs
, dsc
, 8, dsc
->tmp
[0], CANNOT_WRITE_PC
);
7139 thumb_copy_pop_pc_16bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
7140 struct regcache
*regs
,
7141 arm_displaced_step_closure
*dsc
)
7143 dsc
->u
.block
.regmask
= insn1
& 0x00ff;
7145 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
7148 (1) register list is full, that is, r0-r7 are used.
7149 Prepare: tmp[0] <- r8
7151 POP {r0, r1, ...., r6, r7}; remove PC from reglist
7152 MOV r8, r7; Move value of r7 to r8;
7153 POP {r7}; Store PC value into r7.
7155 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
7157 (2) register list is not full, supposing there are N registers in
7158 register list (except PC, 0 <= N <= 7).
7159 Prepare: for each i, 0 - N, tmp[i] <- ri.
7161 POP {r0, r1, ...., rN};
7163 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
7164 from tmp[] properly.
7166 if (debug_displaced
)
7167 fprintf_unfiltered (gdb_stdlog
,
7168 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
7169 dsc
->u
.block
.regmask
, insn1
);
7171 if (dsc
->u
.block
.regmask
== 0xff)
7173 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 8);
7175 dsc
->modinsn
[0] = (insn1
& 0xfeff); /* POP {r0,r1,...,r6, r7} */
7176 dsc
->modinsn
[1] = 0x46b8; /* MOV r8, r7 */
7177 dsc
->modinsn
[2] = 0xbc80; /* POP {r7} */
7180 dsc
->cleanup
= &cleanup_pop_pc_16bit_all
;
7184 unsigned int num_in_list
= bitcount (dsc
->u
.block
.regmask
);
7186 unsigned int new_regmask
;
7188 for (i
= 0; i
< num_in_list
+ 1; i
++)
7189 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7191 new_regmask
= (1 << (num_in_list
+ 1)) - 1;
7193 if (debug_displaced
)
7194 fprintf_unfiltered (gdb_stdlog
, _("displaced: POP "
7195 "{..., pc}: original reg list %.4x,"
7196 " modified list %.4x\n"),
7197 (int) dsc
->u
.block
.regmask
, new_regmask
);
7199 dsc
->u
.block
.regmask
|= 0x8000;
7200 dsc
->u
.block
.writeback
= 0;
7201 dsc
->u
.block
.cond
= INST_AL
;
7203 dsc
->modinsn
[0] = (insn1
& ~0x1ff) | (new_regmask
& 0xff);
7205 dsc
->cleanup
= &cleanup_block_load_pc
;
7212 thumb_process_displaced_16bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7213 struct regcache
*regs
,
7214 arm_displaced_step_closure
*dsc
)
7216 unsigned short op_bit_12_15
= bits (insn1
, 12, 15);
7217 unsigned short op_bit_10_11
= bits (insn1
, 10, 11);
7220 /* 16-bit thumb instructions. */
7221 switch (op_bit_12_15
)
7223 /* Shift (imme), add, subtract, move and compare. */
7224 case 0: case 1: case 2: case 3:
7225 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7226 "shift/add/sub/mov/cmp",
7230 switch (op_bit_10_11
)
7232 case 0: /* Data-processing */
7233 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7237 case 1: /* Special data instructions and branch and exchange. */
7239 unsigned short op
= bits (insn1
, 7, 9);
7240 if (op
== 6 || op
== 7) /* BX or BLX */
7241 err
= thumb_copy_bx_blx_reg (gdbarch
, insn1
, regs
, dsc
);
7242 else if (bits (insn1
, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
7243 err
= thumb_copy_alu_reg (gdbarch
, insn1
, regs
, dsc
);
7245 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "special data",
7249 default: /* LDR (literal) */
7250 err
= thumb_copy_16bit_ldr_literal (gdbarch
, insn1
, regs
, dsc
);
7253 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
7254 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldr/str", dsc
);
7257 if (op_bit_10_11
< 2) /* Generate PC-relative address */
7258 err
= thumb_decode_pc_relative_16bit (gdbarch
, insn1
, regs
, dsc
);
7259 else /* Generate SP-relative address */
7260 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "sp-relative", dsc
);
7262 case 11: /* Misc 16-bit instructions */
7264 switch (bits (insn1
, 8, 11))
7266 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
7267 err
= thumb_copy_cbnz_cbz (gdbarch
, insn1
, regs
, dsc
);
7269 case 12: case 13: /* POP */
7270 if (bit (insn1
, 8)) /* PC is in register list. */
7271 err
= thumb_copy_pop_pc_16bit (gdbarch
, insn1
, regs
, dsc
);
7273 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "pop", dsc
);
7275 case 15: /* If-Then, and hints */
7276 if (bits (insn1
, 0, 3))
7277 /* If-Then makes up to four following instructions conditional.
7278 IT instruction itself is not conditional, so handle it as a
7279 common unmodified instruction. */
7280 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "If-Then",
7283 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "hints", dsc
);
7286 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "misc", dsc
);
7291 if (op_bit_10_11
< 2) /* Store multiple registers */
7292 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "stm", dsc
);
7293 else /* Load multiple registers */
7294 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldm", dsc
);
7296 case 13: /* Conditional branch and supervisor call */
7297 if (bits (insn1
, 9, 11) != 7) /* conditional branch */
7298 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7300 err
= thumb_copy_svc (gdbarch
, insn1
, regs
, dsc
);
7302 case 14: /* Unconditional branch */
7303 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7310 internal_error (__FILE__
, __LINE__
,
7311 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
7315 decode_thumb_32bit_ld_mem_hints (struct gdbarch
*gdbarch
,
7316 uint16_t insn1
, uint16_t insn2
,
7317 struct regcache
*regs
,
7318 arm_displaced_step_closure
*dsc
)
7320 int rt
= bits (insn2
, 12, 15);
7321 int rn
= bits (insn1
, 0, 3);
7322 int op1
= bits (insn1
, 7, 8);
7324 switch (bits (insn1
, 5, 6))
7326 case 0: /* Load byte and memory hints */
7327 if (rt
== 0xf) /* PLD/PLI */
7330 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
7331 return thumb2_copy_preload (gdbarch
, insn1
, insn2
, regs
, dsc
);
7333 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7338 if (rn
== 0xf) /* LDRB/LDRSB (literal) */
7339 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7342 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7343 "ldrb{reg, immediate}/ldrbt",
7348 case 1: /* Load halfword and memory hints. */
7349 if (rt
== 0xf) /* PLD{W} and Unalloc memory hint. */
7350 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7351 "pld/unalloc memhint", dsc
);
7355 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7358 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7362 case 2: /* Load word */
7364 int insn2_bit_8_11
= bits (insn2
, 8, 11);
7367 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
, 4);
7368 else if (op1
== 0x1) /* Encoding T3 */
7369 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
, dsc
,
7371 else /* op1 == 0x0 */
7373 if (insn2_bit_8_11
== 0xc || (insn2_bit_8_11
& 0x9) == 0x9)
7374 /* LDR (immediate) */
7375 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7376 dsc
, bit (insn2
, 8), 1);
7377 else if (insn2_bit_8_11
== 0xe) /* LDRT */
7378 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7381 /* LDR (register) */
7382 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7388 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
7395 thumb_process_displaced_32bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7396 uint16_t insn2
, struct regcache
*regs
,
7397 arm_displaced_step_closure
*dsc
)
7400 unsigned short op
= bit (insn2
, 15);
7401 unsigned int op1
= bits (insn1
, 11, 12);
7407 switch (bits (insn1
, 9, 10))
7412 /* Load/store {dual, execlusive}, table branch. */
7413 if (bits (insn1
, 7, 8) == 1 && bits (insn1
, 4, 5) == 1
7414 && bits (insn2
, 5, 7) == 0)
7415 err
= thumb2_copy_table_branch (gdbarch
, insn1
, insn2
, regs
,
7418 /* PC is not allowed to use in load/store {dual, exclusive}
7420 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7421 "load/store dual/ex", dsc
);
7423 else /* load/store multiple */
7425 switch (bits (insn1
, 7, 8))
7427 case 0: case 3: /* SRS, RFE */
7428 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7431 case 1: case 2: /* LDM/STM/PUSH/POP */
7432 err
= thumb2_copy_block_xfer (gdbarch
, insn1
, insn2
, regs
, dsc
);
7439 /* Data-processing (shift register). */
7440 err
= thumb2_decode_dp_shift_reg (gdbarch
, insn1
, insn2
, regs
,
7443 default: /* Coprocessor instructions. */
7444 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7449 case 2: /* op1 = 2 */
7450 if (op
) /* Branch and misc control. */
7452 if (bit (insn2
, 14) /* BLX/BL */
7453 || bit (insn2
, 12) /* Unconditional branch */
7454 || (bits (insn1
, 7, 9) != 0x7)) /* Conditional branch */
7455 err
= thumb2_copy_b_bl_blx (gdbarch
, insn1
, insn2
, regs
, dsc
);
7457 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7462 if (bit (insn1
, 9)) /* Data processing (plain binary imm). */
7464 int op
= bits (insn1
, 4, 8);
7465 int rn
= bits (insn1
, 0, 3);
7466 if ((op
== 0 || op
== 0xa) && rn
== 0xf)
7467 err
= thumb_copy_pc_relative_32bit (gdbarch
, insn1
, insn2
,
7470 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7473 else /* Data processing (modified immeidate) */
7474 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7478 case 3: /* op1 = 3 */
7479 switch (bits (insn1
, 9, 10))
7483 err
= decode_thumb_32bit_ld_mem_hints (gdbarch
, insn1
, insn2
,
7485 else /* NEON Load/Store and Store single data item */
7486 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7487 "neon elt/struct load/store",
7490 case 1: /* op1 = 3, bits (9, 10) == 1 */
7491 switch (bits (insn1
, 7, 8))
7493 case 0: case 1: /* Data processing (register) */
7494 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7497 case 2: /* Multiply and absolute difference */
7498 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7499 "mul/mua/diff", dsc
);
7501 case 3: /* Long multiply and divide */
7502 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7507 default: /* Coprocessor instructions */
7508 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7517 internal_error (__FILE__
, __LINE__
,
7518 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
7523 thumb_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7524 struct regcache
*regs
,
7525 arm_displaced_step_closure
*dsc
)
7527 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7529 = read_memory_unsigned_integer (from
, 2, byte_order_for_code
);
7531 if (debug_displaced
)
7532 fprintf_unfiltered (gdb_stdlog
, "displaced: process thumb insn %.4x "
7533 "at %.8lx\n", insn1
, (unsigned long) from
);
7536 dsc
->insn_size
= thumb_insn_size (insn1
);
7537 if (thumb_insn_size (insn1
) == 4)
7540 = read_memory_unsigned_integer (from
+ 2, 2, byte_order_for_code
);
7541 thumb_process_displaced_32bit_insn (gdbarch
, insn1
, insn2
, regs
, dsc
);
7544 thumb_process_displaced_16bit_insn (gdbarch
, insn1
, regs
, dsc
);
7548 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7549 CORE_ADDR to
, struct regcache
*regs
,
7550 arm_displaced_step_closure
*dsc
)
7553 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7556 /* Most displaced instructions use a 1-instruction scratch space, so set this
7557 here and override below if/when necessary. */
7559 dsc
->insn_addr
= from
;
7560 dsc
->scratch_base
= to
;
7561 dsc
->cleanup
= NULL
;
7562 dsc
->wrote_to_pc
= 0;
7564 if (!displaced_in_arm_mode (regs
))
7565 return thumb_process_displaced_insn (gdbarch
, from
, regs
, dsc
);
7569 insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
7570 if (debug_displaced
)
7571 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
7572 "at %.8lx\n", (unsigned long) insn
,
7573 (unsigned long) from
);
7575 if ((insn
& 0xf0000000) == 0xf0000000)
7576 err
= arm_decode_unconditional (gdbarch
, insn
, regs
, dsc
);
7577 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
7579 case 0x0: case 0x1: case 0x2: case 0x3:
7580 err
= arm_decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
7583 case 0x4: case 0x5: case 0x6:
7584 err
= arm_decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
7588 err
= arm_decode_media (gdbarch
, insn
, dsc
);
7591 case 0x8: case 0x9: case 0xa: case 0xb:
7592 err
= arm_decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
7595 case 0xc: case 0xd: case 0xe: case 0xf:
7596 err
= arm_decode_svc_copro (gdbarch
, insn
, regs
, dsc
);
7601 internal_error (__FILE__
, __LINE__
,
7602 _("arm_process_displaced_insn: Instruction decode error"));
7605 /* Actually set up the scratch space for a displaced instruction. */
7608 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7609 CORE_ADDR to
, arm_displaced_step_closure
*dsc
)
7611 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7612 unsigned int i
, len
, offset
;
7613 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7614 int size
= dsc
->is_thumb
? 2 : 4;
7615 const gdb_byte
*bkp_insn
;
7618 /* Poke modified instruction(s). */
7619 for (i
= 0; i
< dsc
->numinsns
; i
++)
7621 if (debug_displaced
)
7623 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn ");
7625 fprintf_unfiltered (gdb_stdlog
, "%.8lx",
7628 fprintf_unfiltered (gdb_stdlog
, "%.4x",
7629 (unsigned short)dsc
->modinsn
[i
]);
7631 fprintf_unfiltered (gdb_stdlog
, " at %.8lx\n",
7632 (unsigned long) to
+ offset
);
7635 write_memory_unsigned_integer (to
+ offset
, size
,
7636 byte_order_for_code
,
7641 /* Choose the correct breakpoint instruction. */
7644 bkp_insn
= tdep
->thumb_breakpoint
;
7645 len
= tdep
->thumb_breakpoint_size
;
7649 bkp_insn
= tdep
->arm_breakpoint
;
7650 len
= tdep
->arm_breakpoint_size
;
7653 /* Put breakpoint afterwards. */
7654 write_memory (to
+ offset
, bkp_insn
, len
);
7656 if (debug_displaced
)
7657 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
7658 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
7661 /* Entry point for cleaning things up after a displaced instruction has been
7665 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
7666 struct displaced_step_closure
*dsc_
,
7667 CORE_ADDR from
, CORE_ADDR to
,
7668 struct regcache
*regs
)
7670 arm_displaced_step_closure
*dsc
= (arm_displaced_step_closure
*) dsc_
;
7673 dsc
->cleanup (gdbarch
, regs
, dsc
);
7675 if (!dsc
->wrote_to_pc
)
7676 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
7677 dsc
->insn_addr
+ dsc
->insn_size
);
7681 #include "bfd-in2.h"
7682 #include "libcoff.h"
7685 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
7687 gdb_disassembler
*di
7688 = static_cast<gdb_disassembler
*>(info
->application_data
);
7689 struct gdbarch
*gdbarch
= di
->arch ();
7691 if (arm_pc_is_thumb (gdbarch
, memaddr
))
7693 static asymbol
*asym
;
7694 static combined_entry_type ce
;
7695 static struct coff_symbol_struct csym
;
7696 static struct bfd fake_bfd
;
7697 static bfd_target fake_target
;
7699 if (csym
.native
== NULL
)
7701 /* Create a fake symbol vector containing a Thumb symbol.
7702 This is solely so that the code in print_insn_little_arm()
7703 and print_insn_big_arm() in opcodes/arm-dis.c will detect
7704 the presence of a Thumb symbol and switch to decoding
7705 Thumb instructions. */
7707 fake_target
.flavour
= bfd_target_coff_flavour
;
7708 fake_bfd
.xvec
= &fake_target
;
7709 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
7711 csym
.symbol
.the_bfd
= &fake_bfd
;
7712 csym
.symbol
.name
= "fake";
7713 asym
= (asymbol
*) & csym
;
7716 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
7717 info
->symbols
= &asym
;
7720 info
->symbols
= NULL
;
7722 /* GDB is able to get bfd_mach from the exe_bfd, info->mach is
7723 accurate, so mark USER_SPECIFIED_MACHINE_TYPE bit. Otherwise,
7724 opcodes/arm-dis.c:print_insn reset info->mach, and it will trigger
7725 the assert on the mismatch of info->mach and bfd_get_mach (exec_bfd)
7726 in default_print_insn. */
7727 if (exec_bfd
!= NULL
)
7728 info
->flags
|= USER_SPECIFIED_MACHINE_TYPE
;
7730 return default_print_insn (memaddr
, info
);
7733 /* The following define instruction sequences that will cause ARM
7734 cpu's to take an undefined instruction trap. These are used to
7735 signal a breakpoint to GDB.
7737 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
7738 modes. A different instruction is required for each mode. The ARM
7739 cpu's can also be big or little endian. Thus four different
7740 instructions are needed to support all cases.
7742 Note: ARMv4 defines several new instructions that will take the
7743 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
7744 not in fact add the new instructions. The new undefined
7745 instructions in ARMv4 are all instructions that had no defined
7746 behaviour in earlier chips. There is no guarantee that they will
7747 raise an exception, but may be treated as NOP's. In practice, it
7748 may only safe to rely on instructions matching:
7750 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
7751 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
7752 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
7754 Even this may only true if the condition predicate is true. The
7755 following use a condition predicate of ALWAYS so it is always TRUE.
7757 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
7758 and NetBSD all use a software interrupt rather than an undefined
7759 instruction to force a trap. This can be handled by by the
7760 abi-specific code during establishment of the gdbarch vector. */
7762 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
7763 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
7764 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
7765 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
7767 static const gdb_byte arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
7768 static const gdb_byte arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
7769 static const gdb_byte arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
7770 static const gdb_byte arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
7772 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7775 arm_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7777 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7778 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7780 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
7782 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
7784 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
7785 check whether we are replacing a 32-bit instruction. */
7786 if (tdep
->thumb2_breakpoint
!= NULL
)
7790 if (target_read_memory (*pcptr
, buf
, 2) == 0)
7792 unsigned short inst1
;
7794 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
7795 if (thumb_insn_size (inst1
) == 4)
7796 return ARM_BP_KIND_THUMB2
;
7800 return ARM_BP_KIND_THUMB
;
7803 return ARM_BP_KIND_ARM
;
7807 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7809 static const gdb_byte
*
7810 arm_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7812 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7816 case ARM_BP_KIND_ARM
:
7817 *size
= tdep
->arm_breakpoint_size
;
7818 return tdep
->arm_breakpoint
;
7819 case ARM_BP_KIND_THUMB
:
7820 *size
= tdep
->thumb_breakpoint_size
;
7821 return tdep
->thumb_breakpoint
;
7822 case ARM_BP_KIND_THUMB2
:
7823 *size
= tdep
->thumb2_breakpoint_size
;
7824 return tdep
->thumb2_breakpoint
;
7826 gdb_assert_not_reached ("unexpected arm breakpoint kind");
7830 /* Implement the breakpoint_kind_from_current_state gdbarch method. */
7833 arm_breakpoint_kind_from_current_state (struct gdbarch
*gdbarch
,
7834 struct regcache
*regcache
,
7839 /* Check the memory pointed by PC is readable. */
7840 if (target_read_memory (regcache_read_pc (regcache
), buf
, 4) == 0)
7842 struct arm_get_next_pcs next_pcs_ctx
;
7844 arm_get_next_pcs_ctor (&next_pcs_ctx
,
7845 &arm_get_next_pcs_ops
,
7846 gdbarch_byte_order (gdbarch
),
7847 gdbarch_byte_order_for_code (gdbarch
),
7851 std::vector
<CORE_ADDR
> next_pcs
= arm_get_next_pcs (&next_pcs_ctx
);
7853 /* If MEMADDR is the next instruction of current pc, do the
7854 software single step computation, and get the thumb mode by
7855 the destination address. */
7856 for (CORE_ADDR pc
: next_pcs
)
7858 if (UNMAKE_THUMB_ADDR (pc
) == *pcptr
)
7860 if (IS_THUMB_ADDR (pc
))
7862 *pcptr
= MAKE_THUMB_ADDR (*pcptr
);
7863 return arm_breakpoint_kind_from_pc (gdbarch
, pcptr
);
7866 return ARM_BP_KIND_ARM
;
7871 return arm_breakpoint_kind_from_pc (gdbarch
, pcptr
);
7874 /* Extract from an array REGBUF containing the (raw) register state a
7875 function return value of type TYPE, and copy that, in virtual
7876 format, into VALBUF. */
7879 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
7882 struct gdbarch
*gdbarch
= regs
->arch ();
7883 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7885 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
7887 switch (gdbarch_tdep (gdbarch
)->fp_model
)
7891 /* The value is in register F0 in internal format. We need to
7892 extract the raw value and then convert it to the desired
7894 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
7896 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
7897 target_float_convert (tmpbuf
, arm_ext_type (gdbarch
),
7902 case ARM_FLOAT_SOFT_FPA
:
7903 case ARM_FLOAT_SOFT_VFP
:
7904 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7905 not using the VFP ABI code. */
7907 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
7908 if (TYPE_LENGTH (type
) > 4)
7909 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
7910 valbuf
+ INT_REGISTER_SIZE
);
7914 internal_error (__FILE__
, __LINE__
,
7915 _("arm_extract_return_value: "
7916 "Floating point model not supported"));
7920 else if (TYPE_CODE (type
) == TYPE_CODE_INT
7921 || TYPE_CODE (type
) == TYPE_CODE_CHAR
7922 || TYPE_CODE (type
) == TYPE_CODE_BOOL
7923 || TYPE_CODE (type
) == TYPE_CODE_PTR
7924 || TYPE_IS_REFERENCE (type
)
7925 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
7927 /* If the type is a plain integer, then the access is
7928 straight-forward. Otherwise we have to play around a bit
7930 int len
= TYPE_LENGTH (type
);
7931 int regno
= ARM_A1_REGNUM
;
7936 /* By using store_unsigned_integer we avoid having to do
7937 anything special for small big-endian values. */
7938 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
7939 store_unsigned_integer (valbuf
,
7940 (len
> INT_REGISTER_SIZE
7941 ? INT_REGISTER_SIZE
: len
),
7943 len
-= INT_REGISTER_SIZE
;
7944 valbuf
+= INT_REGISTER_SIZE
;
7949 /* For a structure or union the behaviour is as if the value had
7950 been stored to word-aligned memory and then loaded into
7951 registers with 32-bit load instruction(s). */
7952 int len
= TYPE_LENGTH (type
);
7953 int regno
= ARM_A1_REGNUM
;
7954 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
7958 regcache_cooked_read (regs
, regno
++, tmpbuf
);
7959 memcpy (valbuf
, tmpbuf
,
7960 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
7961 len
-= INT_REGISTER_SIZE
;
7962 valbuf
+= INT_REGISTER_SIZE
;
7968 /* Will a function return an aggregate type in memory or in a
7969 register? Return 0 if an aggregate type can be returned in a
7970 register, 1 if it must be returned in memory. */
7973 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
7975 enum type_code code
;
7977 type
= check_typedef (type
);
7979 /* Simple, non-aggregate types (ie not including vectors and
7980 complex) are always returned in a register (or registers). */
7981 code
= TYPE_CODE (type
);
7982 if (TYPE_CODE_STRUCT
!= code
&& TYPE_CODE_UNION
!= code
7983 && TYPE_CODE_ARRAY
!= code
&& TYPE_CODE_COMPLEX
!= code
)
7986 if (TYPE_CODE_ARRAY
== code
&& TYPE_VECTOR (type
))
7988 /* Vector values should be returned using ARM registers if they
7989 are not over 16 bytes. */
7990 return (TYPE_LENGTH (type
) > 16);
7993 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
7995 /* The AAPCS says all aggregates not larger than a word are returned
7997 if (TYPE_LENGTH (type
) <= INT_REGISTER_SIZE
)
8006 /* All aggregate types that won't fit in a register must be returned
8008 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
8011 /* In the ARM ABI, "integer" like aggregate types are returned in
8012 registers. For an aggregate type to be integer like, its size
8013 must be less than or equal to INT_REGISTER_SIZE and the
8014 offset of each addressable subfield must be zero. Note that bit
8015 fields are not addressable, and all addressable subfields of
8016 unions always start at offset zero.
8018 This function is based on the behaviour of GCC 2.95.1.
8019 See: gcc/arm.c: arm_return_in_memory() for details.
8021 Note: All versions of GCC before GCC 2.95.2 do not set up the
8022 parameters correctly for a function returning the following
8023 structure: struct { float f;}; This should be returned in memory,
8024 not a register. Richard Earnshaw sent me a patch, but I do not
8025 know of any way to detect if a function like the above has been
8026 compiled with the correct calling convention. */
8028 /* Assume all other aggregate types can be returned in a register.
8029 Run a check for structures, unions and arrays. */
8032 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
8035 /* Need to check if this struct/union is "integer" like. For
8036 this to be true, its size must be less than or equal to
8037 INT_REGISTER_SIZE and the offset of each addressable
8038 subfield must be zero. Note that bit fields are not
8039 addressable, and unions always start at offset zero. If any
8040 of the subfields is a floating point type, the struct/union
8041 cannot be an integer type. */
8043 /* For each field in the object, check:
8044 1) Is it FP? --> yes, nRc = 1;
8045 2) Is it addressable (bitpos != 0) and
8046 not packed (bitsize == 0)?
8050 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
8052 enum type_code field_type_code
;
8055 = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
,
8058 /* Is it a floating point type field? */
8059 if (field_type_code
== TYPE_CODE_FLT
)
8065 /* If bitpos != 0, then we have to care about it. */
8066 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
8068 /* Bitfields are not addressable. If the field bitsize is
8069 zero, then the field is not packed. Hence it cannot be
8070 a bitfield or any other packed type. */
8071 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
8084 /* Write into appropriate registers a function return value of type
8085 TYPE, given in virtual format. */
8088 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
8089 const gdb_byte
*valbuf
)
8091 struct gdbarch
*gdbarch
= regs
->arch ();
8092 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8094 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
8096 gdb_byte buf
[FP_REGISTER_SIZE
];
8098 switch (gdbarch_tdep (gdbarch
)->fp_model
)
8102 target_float_convert (valbuf
, type
, buf
, arm_ext_type (gdbarch
));
8103 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
8106 case ARM_FLOAT_SOFT_FPA
:
8107 case ARM_FLOAT_SOFT_VFP
:
8108 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8109 not using the VFP ABI code. */
8111 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
8112 if (TYPE_LENGTH (type
) > 4)
8113 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
8114 valbuf
+ INT_REGISTER_SIZE
);
8118 internal_error (__FILE__
, __LINE__
,
8119 _("arm_store_return_value: Floating "
8120 "point model not supported"));
8124 else if (TYPE_CODE (type
) == TYPE_CODE_INT
8125 || TYPE_CODE (type
) == TYPE_CODE_CHAR
8126 || TYPE_CODE (type
) == TYPE_CODE_BOOL
8127 || TYPE_CODE (type
) == TYPE_CODE_PTR
8128 || TYPE_IS_REFERENCE (type
)
8129 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
8131 if (TYPE_LENGTH (type
) <= 4)
8133 /* Values of one word or less are zero/sign-extended and
8135 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8136 LONGEST val
= unpack_long (type
, valbuf
);
8138 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
8139 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
8143 /* Integral values greater than one word are stored in consecutive
8144 registers starting with r0. This will always be a multiple of
8145 the regiser size. */
8146 int len
= TYPE_LENGTH (type
);
8147 int regno
= ARM_A1_REGNUM
;
8151 regcache_cooked_write (regs
, regno
++, valbuf
);
8152 len
-= INT_REGISTER_SIZE
;
8153 valbuf
+= INT_REGISTER_SIZE
;
8159 /* For a structure or union the behaviour is as if the value had
8160 been stored to word-aligned memory and then loaded into
8161 registers with 32-bit load instruction(s). */
8162 int len
= TYPE_LENGTH (type
);
8163 int regno
= ARM_A1_REGNUM
;
8164 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8168 memcpy (tmpbuf
, valbuf
,
8169 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
8170 regcache_cooked_write (regs
, regno
++, tmpbuf
);
8171 len
-= INT_REGISTER_SIZE
;
8172 valbuf
+= INT_REGISTER_SIZE
;
8178 /* Handle function return values. */
8180 static enum return_value_convention
8181 arm_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
8182 struct type
*valtype
, struct regcache
*regcache
,
8183 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
8185 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8186 struct type
*func_type
= function
? value_type (function
) : NULL
;
8187 enum arm_vfp_cprc_base_type vfp_base_type
;
8190 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
8191 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
8193 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
8194 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
8196 for (i
= 0; i
< vfp_base_count
; i
++)
8198 if (reg_char
== 'q')
8201 arm_neon_quad_write (gdbarch
, regcache
, i
,
8202 writebuf
+ i
* unit_length
);
8205 arm_neon_quad_read (gdbarch
, regcache
, i
,
8206 readbuf
+ i
* unit_length
);
8213 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d", reg_char
, i
);
8214 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8217 regcache_cooked_write (regcache
, regnum
,
8218 writebuf
+ i
* unit_length
);
8220 regcache_cooked_read (regcache
, regnum
,
8221 readbuf
+ i
* unit_length
);
8224 return RETURN_VALUE_REGISTER_CONVENTION
;
8227 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
8228 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
8229 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
8231 if (tdep
->struct_return
== pcc_struct_return
8232 || arm_return_in_memory (gdbarch
, valtype
))
8233 return RETURN_VALUE_STRUCT_CONVENTION
;
8235 else if (TYPE_CODE (valtype
) == TYPE_CODE_COMPLEX
)
8237 if (arm_return_in_memory (gdbarch
, valtype
))
8238 return RETURN_VALUE_STRUCT_CONVENTION
;
8242 arm_store_return_value (valtype
, regcache
, writebuf
);
8245 arm_extract_return_value (valtype
, regcache
, readbuf
);
8247 return RETURN_VALUE_REGISTER_CONVENTION
;
8252 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
8254 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
8255 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8256 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8258 gdb_byte buf
[INT_REGISTER_SIZE
];
8260 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
8262 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
8266 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
8270 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
8271 return the target PC. Otherwise return 0. */
8274 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
8278 CORE_ADDR start_addr
;
8280 /* Find the starting address and name of the function containing the PC. */
8281 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
8283 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
8285 start_addr
= arm_skip_bx_reg (frame
, pc
);
8286 if (start_addr
!= 0)
8292 /* If PC is in a Thumb call or return stub, return the address of the
8293 target PC, which is in a register. The thunk functions are called
8294 _call_via_xx, where x is the register name. The possible names
8295 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
8296 functions, named __ARM_call_via_r[0-7]. */
8297 if (startswith (name
, "_call_via_")
8298 || startswith (name
, "__ARM_call_via_"))
8300 /* Use the name suffix to determine which register contains the
8302 static const char *table
[15] =
8303 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8304 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
8307 int offset
= strlen (name
) - 2;
8309 for (regno
= 0; regno
<= 14; regno
++)
8310 if (strcmp (&name
[offset
], table
[regno
]) == 0)
8311 return get_frame_register_unsigned (frame
, regno
);
8314 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
8315 non-interworking calls to foo. We could decode the stubs
8316 to find the target but it's easier to use the symbol table. */
8317 namelen
= strlen (name
);
8318 if (name
[0] == '_' && name
[1] == '_'
8319 && ((namelen
> 2 + strlen ("_from_thumb")
8320 && startswith (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb"))
8321 || (namelen
> 2 + strlen ("_from_arm")
8322 && startswith (name
+ namelen
- strlen ("_from_arm"), "_from_arm"))))
8325 int target_len
= namelen
- 2;
8326 struct bound_minimal_symbol minsym
;
8327 struct objfile
*objfile
;
8328 struct obj_section
*sec
;
8330 if (name
[namelen
- 1] == 'b')
8331 target_len
-= strlen ("_from_thumb");
8333 target_len
-= strlen ("_from_arm");
8335 target_name
= (char *) alloca (target_len
+ 1);
8336 memcpy (target_name
, name
+ 2, target_len
);
8337 target_name
[target_len
] = '\0';
8339 sec
= find_pc_section (pc
);
8340 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
8341 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
8342 if (minsym
.minsym
!= NULL
)
8343 return BMSYMBOL_VALUE_ADDRESS (minsym
);
8348 return 0; /* not a stub */
8352 set_arm_command (const char *args
, int from_tty
)
8354 printf_unfiltered (_("\
8355 \"set arm\" must be followed by an apporpriate subcommand.\n"));
8356 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
8360 show_arm_command (const char *args
, int from_tty
)
8362 cmd_show_list (showarmcmdlist
, from_tty
, "");
8366 arm_update_current_architecture (void)
8368 struct gdbarch_info info
;
8370 /* If the current architecture is not ARM, we have nothing to do. */
8371 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_arm
)
8374 /* Update the architecture. */
8375 gdbarch_info_init (&info
);
8377 if (!gdbarch_update_p (info
))
8378 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
8382 set_fp_model_sfunc (const char *args
, int from_tty
,
8383 struct cmd_list_element
*c
)
8387 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
8388 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
8390 arm_fp_model
= (enum arm_float_model
) fp_model
;
8394 if (fp_model
== ARM_FLOAT_LAST
)
8395 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
8398 arm_update_current_architecture ();
8402 show_fp_model (struct ui_file
*file
, int from_tty
,
8403 struct cmd_list_element
*c
, const char *value
)
8405 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8407 if (arm_fp_model
== ARM_FLOAT_AUTO
8408 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8409 fprintf_filtered (file
, _("\
8410 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
8411 fp_model_strings
[tdep
->fp_model
]);
8413 fprintf_filtered (file
, _("\
8414 The current ARM floating point model is \"%s\".\n"),
8415 fp_model_strings
[arm_fp_model
]);
8419 arm_set_abi (const char *args
, int from_tty
,
8420 struct cmd_list_element
*c
)
8424 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
8425 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
8427 arm_abi_global
= (enum arm_abi_kind
) arm_abi
;
8431 if (arm_abi
== ARM_ABI_LAST
)
8432 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
8435 arm_update_current_architecture ();
8439 arm_show_abi (struct ui_file
*file
, int from_tty
,
8440 struct cmd_list_element
*c
, const char *value
)
8442 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8444 if (arm_abi_global
== ARM_ABI_AUTO
8445 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8446 fprintf_filtered (file
, _("\
8447 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
8448 arm_abi_strings
[tdep
->arm_abi
]);
8450 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
8455 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
8456 struct cmd_list_element
*c
, const char *value
)
8458 fprintf_filtered (file
,
8459 _("The current execution mode assumed "
8460 "(when symbols are unavailable) is \"%s\".\n"),
8461 arm_fallback_mode_string
);
8465 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
8466 struct cmd_list_element
*c
, const char *value
)
8468 fprintf_filtered (file
,
8469 _("The current execution mode assumed "
8470 "(even when symbols are available) is \"%s\".\n"),
8471 arm_force_mode_string
);
8474 /* If the user changes the register disassembly style used for info
8475 register and other commands, we have to also switch the style used
8476 in opcodes for disassembly output. This function is run in the "set
8477 arm disassembly" command, and does that. */
8480 set_disassembly_style_sfunc (const char *args
, int from_tty
,
8481 struct cmd_list_element
*c
)
8483 /* Convert the short style name into the long style name (eg, reg-names-*)
8484 before calling the generic set_disassembler_options() function. */
8485 std::string long_name
= std::string ("reg-names-") + disassembly_style
;
8486 set_disassembler_options (&long_name
[0]);
8490 show_disassembly_style_sfunc (struct ui_file
*file
, int from_tty
,
8491 struct cmd_list_element
*c
, const char *value
)
8493 struct gdbarch
*gdbarch
= get_current_arch ();
8494 char *options
= get_disassembler_options (gdbarch
);
8495 const char *style
= "";
8499 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
8500 if (CONST_STRNEQ (opt
, "reg-names-"))
8502 style
= &opt
[strlen ("reg-names-")];
8503 len
= strcspn (style
, ",");
8506 fprintf_unfiltered (file
, "The disassembly style is \"%.*s\".\n", len
, style
);
8509 /* Return the ARM register name corresponding to register I. */
8511 arm_register_name (struct gdbarch
*gdbarch
, int i
)
8513 const int num_regs
= gdbarch_num_regs (gdbarch
);
8515 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
8516 && i
>= num_regs
&& i
< num_regs
+ 32)
8518 static const char *const vfp_pseudo_names
[] = {
8519 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
8520 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
8521 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
8522 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
8525 return vfp_pseudo_names
[i
- num_regs
];
8528 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
8529 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
8531 static const char *const neon_pseudo_names
[] = {
8532 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
8533 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
8536 return neon_pseudo_names
[i
- num_regs
- 32];
8539 if (i
>= ARRAY_SIZE (arm_register_names
))
8540 /* These registers are only supported on targets which supply
8541 an XML description. */
8544 return arm_register_names
[i
];
8547 /* Test whether the coff symbol specific value corresponds to a Thumb
8551 coff_sym_is_thumb (int val
)
8553 return (val
== C_THUMBEXT
8554 || val
== C_THUMBSTAT
8555 || val
== C_THUMBEXTFUNC
8556 || val
== C_THUMBSTATFUNC
8557 || val
== C_THUMBLABEL
);
8560 /* arm_coff_make_msymbol_special()
8561 arm_elf_make_msymbol_special()
8563 These functions test whether the COFF or ELF symbol corresponds to
8564 an address in thumb code, and set a "special" bit in a minimal
8565 symbol to indicate that it does. */
8568 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
8570 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
8572 if (ARM_GET_SYM_BRANCH_TYPE (elfsym
->internal_elf_sym
.st_target_internal
)
8573 == ST_BRANCH_TO_THUMB
)
8574 MSYMBOL_SET_SPECIAL (msym
);
8578 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
8580 if (coff_sym_is_thumb (val
))
8581 MSYMBOL_SET_SPECIAL (msym
);
8585 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
8587 struct arm_per_objfile
*data
= (struct arm_per_objfile
*) arg
;
8590 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
8591 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
8595 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
8598 const char *name
= bfd_asymbol_name (sym
);
8599 struct arm_per_objfile
*data
;
8600 VEC(arm_mapping_symbol_s
) **map_p
;
8601 struct arm_mapping_symbol new_map_sym
;
8603 gdb_assert (name
[0] == '$');
8604 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
8607 data
= (struct arm_per_objfile
*) objfile_data (objfile
,
8608 arm_objfile_data_key
);
8611 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
8612 struct arm_per_objfile
);
8613 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
8614 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
8615 objfile
->obfd
->section_count
,
8616 VEC(arm_mapping_symbol_s
) *);
8618 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
8620 new_map_sym
.value
= sym
->value
;
8621 new_map_sym
.type
= name
[1];
8623 /* Assume that most mapping symbols appear in order of increasing
8624 value. If they were randomly distributed, it would be faster to
8625 always push here and then sort at first use. */
8626 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
8628 struct arm_mapping_symbol
*prev_map_sym
;
8630 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
8631 if (prev_map_sym
->value
>= sym
->value
)
8634 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
8635 arm_compare_mapping_symbols
);
8636 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
8641 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
8645 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
8647 struct gdbarch
*gdbarch
= regcache
->arch ();
8648 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
8650 /* If necessary, set the T bit. */
8653 ULONGEST val
, t_bit
;
8654 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
8655 t_bit
= arm_psr_thumb_bit (gdbarch
);
8656 if (arm_pc_is_thumb (gdbarch
, pc
))
8657 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8660 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8665 /* Read the contents of a NEON quad register, by reading from two
8666 double registers. This is used to implement the quad pseudo
8667 registers, and for argument passing in case the quad registers are
8668 missing; vectors are passed in quad registers when using the VFP
8669 ABI, even if a NEON unit is not present. REGNUM is the index of
8670 the quad register, in [0, 15]. */
8672 static enum register_status
8673 arm_neon_quad_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
8674 int regnum
, gdb_byte
*buf
)
8677 gdb_byte reg_buf
[8];
8678 int offset
, double_regnum
;
8679 enum register_status status
;
8681 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8682 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8685 /* d0 is always the least significant half of q0. */
8686 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8691 status
= regcache
->raw_read (double_regnum
, reg_buf
);
8692 if (status
!= REG_VALID
)
8694 memcpy (buf
+ offset
, reg_buf
, 8);
8696 offset
= 8 - offset
;
8697 status
= regcache
->raw_read (double_regnum
+ 1, reg_buf
);
8698 if (status
!= REG_VALID
)
8700 memcpy (buf
+ offset
, reg_buf
, 8);
8705 static enum register_status
8706 arm_pseudo_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
8707 int regnum
, gdb_byte
*buf
)
8709 const int num_regs
= gdbarch_num_regs (gdbarch
);
8711 gdb_byte reg_buf
[8];
8712 int offset
, double_regnum
;
8714 gdb_assert (regnum
>= num_regs
);
8717 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8718 /* Quad-precision register. */
8719 return arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
8722 enum register_status status
;
8724 /* Single-precision register. */
8725 gdb_assert (regnum
< 32);
8727 /* s0 is always the least significant half of d0. */
8728 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8729 offset
= (regnum
& 1) ? 0 : 4;
8731 offset
= (regnum
& 1) ? 4 : 0;
8733 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8734 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8737 status
= regcache
->raw_read (double_regnum
, reg_buf
);
8738 if (status
== REG_VALID
)
8739 memcpy (buf
, reg_buf
+ offset
, 4);
8744 /* Store the contents of BUF to a NEON quad register, by writing to
8745 two double registers. This is used to implement the quad pseudo
8746 registers, and for argument passing in case the quad registers are
8747 missing; vectors are passed in quad registers when using the VFP
8748 ABI, even if a NEON unit is not present. REGNUM is the index
8749 of the quad register, in [0, 15]. */
8752 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8753 int regnum
, const gdb_byte
*buf
)
8756 int offset
, double_regnum
;
8758 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8759 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8762 /* d0 is always the least significant half of q0. */
8763 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8768 regcache
->raw_write (double_regnum
, buf
+ offset
);
8769 offset
= 8 - offset
;
8770 regcache
->raw_write (double_regnum
+ 1, buf
+ offset
);
8774 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8775 int regnum
, const gdb_byte
*buf
)
8777 const int num_regs
= gdbarch_num_regs (gdbarch
);
8779 gdb_byte reg_buf
[8];
8780 int offset
, double_regnum
;
8782 gdb_assert (regnum
>= num_regs
);
8785 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8786 /* Quad-precision register. */
8787 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
8790 /* Single-precision register. */
8791 gdb_assert (regnum
< 32);
8793 /* s0 is always the least significant half of d0. */
8794 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8795 offset
= (regnum
& 1) ? 0 : 4;
8797 offset
= (regnum
& 1) ? 4 : 0;
8799 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8800 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8803 regcache
->raw_read (double_regnum
, reg_buf
);
8804 memcpy (reg_buf
+ offset
, buf
, 4);
8805 regcache
->raw_write (double_regnum
, reg_buf
);
8809 static struct value
*
8810 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
8812 const int *reg_p
= (const int *) baton
;
8813 return value_of_register (*reg_p
, frame
);
8816 static enum gdb_osabi
8817 arm_elf_osabi_sniffer (bfd
*abfd
)
8819 unsigned int elfosabi
;
8820 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
8822 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
8824 if (elfosabi
== ELFOSABI_ARM
)
8825 /* GNU tools use this value. Check note sections in this case,
8827 bfd_map_over_sections (abfd
,
8828 generic_elf_osabi_sniff_abi_tag_sections
,
8831 /* Anything else will be handled by the generic ELF sniffer. */
8836 arm_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
8837 struct reggroup
*group
)
8839 /* FPS register's type is INT, but belongs to float_reggroup. Beside
8840 this, FPS register belongs to save_regroup, restore_reggroup, and
8841 all_reggroup, of course. */
8842 if (regnum
== ARM_FPS_REGNUM
)
8843 return (group
== float_reggroup
8844 || group
== save_reggroup
8845 || group
== restore_reggroup
8846 || group
== all_reggroup
);
8848 return default_register_reggroup_p (gdbarch
, regnum
, group
);
8852 /* For backward-compatibility we allow two 'g' packet lengths with
8853 the remote protocol depending on whether FPA registers are
8854 supplied. M-profile targets do not have FPA registers, but some
8855 stubs already exist in the wild which use a 'g' packet which
8856 supplies them albeit with dummy values. The packet format which
8857 includes FPA registers should be considered deprecated for
8858 M-profile targets. */
8861 arm_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8863 if (gdbarch_tdep (gdbarch
)->is_m
)
8865 /* If we know from the executable this is an M-profile target,
8866 cater for remote targets whose register set layout is the
8867 same as the FPA layout. */
8868 register_remote_g_packet_guess (gdbarch
,
8869 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
8870 (16 * INT_REGISTER_SIZE
)
8871 + (8 * FP_REGISTER_SIZE
)
8872 + (2 * INT_REGISTER_SIZE
),
8873 tdesc_arm_with_m_fpa_layout
);
8875 /* The regular M-profile layout. */
8876 register_remote_g_packet_guess (gdbarch
,
8877 /* r0-r12,sp,lr,pc; xpsr */
8878 (16 * INT_REGISTER_SIZE
)
8879 + INT_REGISTER_SIZE
,
8882 /* M-profile plus M4F VFP. */
8883 register_remote_g_packet_guess (gdbarch
,
8884 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
8885 (16 * INT_REGISTER_SIZE
)
8886 + (16 * VFP_REGISTER_SIZE
)
8887 + (2 * INT_REGISTER_SIZE
),
8888 tdesc_arm_with_m_vfp_d16
);
8891 /* Otherwise we don't have a useful guess. */
8894 /* Implement the code_of_frame_writable gdbarch method. */
8897 arm_code_of_frame_writable (struct gdbarch
*gdbarch
, struct frame_info
*frame
)
8899 if (gdbarch_tdep (gdbarch
)->is_m
8900 && get_frame_type (frame
) == SIGTRAMP_FRAME
)
8902 /* M-profile exception frames return to some magic PCs, where
8903 isn't writable at all. */
8911 /* Initialize the current architecture based on INFO. If possible,
8912 re-use an architecture from ARCHES, which is a list of
8913 architectures already created during this debugging session.
8915 Called e.g. at program startup, when reading a core file, and when
8916 reading a binary file. */
8918 static struct gdbarch
*
8919 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8921 struct gdbarch_tdep
*tdep
;
8922 struct gdbarch
*gdbarch
;
8923 struct gdbarch_list
*best_arch
;
8924 enum arm_abi_kind arm_abi
= arm_abi_global
;
8925 enum arm_float_model fp_model
= arm_fp_model
;
8926 struct tdesc_arch_data
*tdesc_data
= NULL
;
8928 int vfp_register_count
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
8929 int have_wmmx_registers
= 0;
8931 int have_fpa_registers
= 1;
8932 const struct target_desc
*tdesc
= info
.target_desc
;
8934 /* If we have an object to base this architecture on, try to determine
8937 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
8939 int ei_osabi
, e_flags
;
8941 switch (bfd_get_flavour (info
.abfd
))
8943 case bfd_target_coff_flavour
:
8944 /* Assume it's an old APCS-style ABI. */
8946 arm_abi
= ARM_ABI_APCS
;
8949 case bfd_target_elf_flavour
:
8950 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
8951 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8953 if (ei_osabi
== ELFOSABI_ARM
)
8955 /* GNU tools used to use this value, but do not for EABI
8956 objects. There's nowhere to tag an EABI version
8957 anyway, so assume APCS. */
8958 arm_abi
= ARM_ABI_APCS
;
8960 else if (ei_osabi
== ELFOSABI_NONE
|| ei_osabi
== ELFOSABI_GNU
)
8962 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
8963 int attr_arch
, attr_profile
;
8967 case EF_ARM_EABI_UNKNOWN
:
8968 /* Assume GNU tools. */
8969 arm_abi
= ARM_ABI_APCS
;
8972 case EF_ARM_EABI_VER4
:
8973 case EF_ARM_EABI_VER5
:
8974 arm_abi
= ARM_ABI_AAPCS
;
8975 /* EABI binaries default to VFP float ordering.
8976 They may also contain build attributes that can
8977 be used to identify if the VFP argument-passing
8979 if (fp_model
== ARM_FLOAT_AUTO
)
8982 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
8986 case AEABI_VFP_args_base
:
8987 /* "The user intended FP parameter/result
8988 passing to conform to AAPCS, base
8990 fp_model
= ARM_FLOAT_SOFT_VFP
;
8992 case AEABI_VFP_args_vfp
:
8993 /* "The user intended FP parameter/result
8994 passing to conform to AAPCS, VFP
8996 fp_model
= ARM_FLOAT_VFP
;
8998 case AEABI_VFP_args_toolchain
:
8999 /* "The user intended FP parameter/result
9000 passing to conform to tool chain-specific
9001 conventions" - we don't know any such
9002 conventions, so leave it as "auto". */
9004 case AEABI_VFP_args_compatible
:
9005 /* "Code is compatible with both the base
9006 and VFP variants; the user did not permit
9007 non-variadic functions to pass FP
9008 parameters/results" - leave it as
9012 /* Attribute value not mentioned in the
9013 November 2012 ABI, so leave it as
9018 fp_model
= ARM_FLOAT_SOFT_VFP
;
9024 /* Leave it as "auto". */
9025 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
9030 /* Detect M-profile programs. This only works if the
9031 executable file includes build attributes; GCC does
9032 copy them to the executable, but e.g. RealView does
9034 attr_arch
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
9036 attr_profile
= bfd_elf_get_obj_attr_int (info
.abfd
,
9038 Tag_CPU_arch_profile
);
9039 /* GCC specifies the profile for v6-M; RealView only
9040 specifies the profile for architectures starting with
9041 V7 (as opposed to architectures with a tag
9042 numerically greater than TAG_CPU_ARCH_V7). */
9043 if (!tdesc_has_registers (tdesc
)
9044 && (attr_arch
== TAG_CPU_ARCH_V6_M
9045 || attr_arch
== TAG_CPU_ARCH_V6S_M
9046 || attr_profile
== 'M'))
9051 if (fp_model
== ARM_FLOAT_AUTO
)
9053 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9055 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
9058 /* Leave it as "auto". Strictly speaking this case
9059 means FPA, but almost nobody uses that now, and
9060 many toolchains fail to set the appropriate bits
9061 for the floating-point model they use. */
9063 case EF_ARM_SOFT_FLOAT
:
9064 fp_model
= ARM_FLOAT_SOFT_FPA
;
9066 case EF_ARM_VFP_FLOAT
:
9067 fp_model
= ARM_FLOAT_VFP
;
9069 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
9070 fp_model
= ARM_FLOAT_SOFT_VFP
;
9075 if (e_flags
& EF_ARM_BE8
)
9076 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
9081 /* Leave it as "auto". */
9086 /* Check any target description for validity. */
9087 if (tdesc_has_registers (tdesc
))
9089 /* For most registers we require GDB's default names; but also allow
9090 the numeric names for sp / lr / pc, as a convenience. */
9091 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
9092 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
9093 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
9095 const struct tdesc_feature
*feature
;
9098 feature
= tdesc_find_feature (tdesc
,
9099 "org.gnu.gdb.arm.core");
9100 if (feature
== NULL
)
9102 feature
= tdesc_find_feature (tdesc
,
9103 "org.gnu.gdb.arm.m-profile");
9104 if (feature
== NULL
)
9110 tdesc_data
= tdesc_data_alloc ();
9113 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
9114 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9115 arm_register_names
[i
]);
9116 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9119 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9122 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9126 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9127 ARM_PS_REGNUM
, "xpsr");
9129 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9130 ARM_PS_REGNUM
, "cpsr");
9134 tdesc_data_cleanup (tdesc_data
);
9138 feature
= tdesc_find_feature (tdesc
,
9139 "org.gnu.gdb.arm.fpa");
9140 if (feature
!= NULL
)
9143 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
9144 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9145 arm_register_names
[i
]);
9148 tdesc_data_cleanup (tdesc_data
);
9153 have_fpa_registers
= 0;
9155 feature
= tdesc_find_feature (tdesc
,
9156 "org.gnu.gdb.xscale.iwmmxt");
9157 if (feature
!= NULL
)
9159 static const char *const iwmmxt_names
[] = {
9160 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
9161 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
9162 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
9163 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
9167 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
9169 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9170 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9172 /* Check for the control registers, but do not fail if they
9174 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
9175 tdesc_numbered_register (feature
, tdesc_data
, i
,
9176 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9178 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
9180 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9181 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9185 tdesc_data_cleanup (tdesc_data
);
9189 have_wmmx_registers
= 1;
9192 /* If we have a VFP unit, check whether the single precision registers
9193 are present. If not, then we will synthesize them as pseudo
9195 feature
= tdesc_find_feature (tdesc
,
9196 "org.gnu.gdb.arm.vfp");
9197 if (feature
!= NULL
)
9199 static const char *const vfp_double_names
[] = {
9200 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
9201 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
9202 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
9203 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
9206 /* Require the double precision registers. There must be either
9209 for (i
= 0; i
< 32; i
++)
9211 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9213 vfp_double_names
[i
]);
9217 if (!valid_p
&& i
== 16)
9220 /* Also require FPSCR. */
9221 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9222 ARM_FPSCR_REGNUM
, "fpscr");
9225 tdesc_data_cleanup (tdesc_data
);
9229 if (tdesc_unnumbered_register (feature
, "s0") == 0)
9230 have_vfp_pseudos
= 1;
9232 vfp_register_count
= i
;
9234 /* If we have VFP, also check for NEON. The architecture allows
9235 NEON without VFP (integer vector operations only), but GDB
9236 does not support that. */
9237 feature
= tdesc_find_feature (tdesc
,
9238 "org.gnu.gdb.arm.neon");
9239 if (feature
!= NULL
)
9241 /* NEON requires 32 double-precision registers. */
9244 tdesc_data_cleanup (tdesc_data
);
9248 /* If there are quad registers defined by the stub, use
9249 their type; otherwise (normally) provide them with
9250 the default type. */
9251 if (tdesc_unnumbered_register (feature
, "q0") == 0)
9252 have_neon_pseudos
= 1;
9259 /* If there is already a candidate, use it. */
9260 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
9262 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
9264 if (arm_abi
!= ARM_ABI_AUTO
9265 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
9268 if (fp_model
!= ARM_FLOAT_AUTO
9269 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
9272 /* There are various other properties in tdep that we do not
9273 need to check here: those derived from a target description,
9274 since gdbarches with a different target description are
9275 automatically disqualified. */
9277 /* Do check is_m, though, since it might come from the binary. */
9278 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
9281 /* Found a match. */
9285 if (best_arch
!= NULL
)
9287 if (tdesc_data
!= NULL
)
9288 tdesc_data_cleanup (tdesc_data
);
9289 return best_arch
->gdbarch
;
9292 tdep
= XCNEW (struct gdbarch_tdep
);
9293 gdbarch
= gdbarch_alloc (&info
, tdep
);
9295 /* Record additional information about the architecture we are defining.
9296 These are gdbarch discriminators, like the OSABI. */
9297 tdep
->arm_abi
= arm_abi
;
9298 tdep
->fp_model
= fp_model
;
9300 tdep
->have_fpa_registers
= have_fpa_registers
;
9301 tdep
->have_wmmx_registers
= have_wmmx_registers
;
9302 gdb_assert (vfp_register_count
== 0
9303 || vfp_register_count
== 16
9304 || vfp_register_count
== 32);
9305 tdep
->vfp_register_count
= vfp_register_count
;
9306 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
9307 tdep
->have_neon_pseudos
= have_neon_pseudos
;
9308 tdep
->have_neon
= have_neon
;
9310 arm_register_g_packet_guesses (gdbarch
);
9313 switch (info
.byte_order_for_code
)
9315 case BFD_ENDIAN_BIG
:
9316 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
9317 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
9318 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
9319 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
9323 case BFD_ENDIAN_LITTLE
:
9324 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
9325 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
9326 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
9327 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
9332 internal_error (__FILE__
, __LINE__
,
9333 _("arm_gdbarch_init: bad byte order for float format"));
9336 /* On ARM targets char defaults to unsigned. */
9337 set_gdbarch_char_signed (gdbarch
, 0);
9339 /* wchar_t is unsigned under the AAPCS. */
9340 if (tdep
->arm_abi
== ARM_ABI_AAPCS
)
9341 set_gdbarch_wchar_signed (gdbarch
, 0);
9343 set_gdbarch_wchar_signed (gdbarch
, 1);
9345 /* Note: for displaced stepping, this includes the breakpoint, and one word
9346 of additional scratch space. This setting isn't used for anything beside
9347 displaced stepping at present. */
9348 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
9350 /* This should be low enough for everything. */
9351 tdep
->lowest_pc
= 0x20;
9352 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
9354 /* The default, for both APCS and AAPCS, is to return small
9355 structures in registers. */
9356 tdep
->struct_return
= reg_struct_return
;
9358 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
9359 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
9362 set_gdbarch_code_of_frame_writable (gdbarch
, arm_code_of_frame_writable
);
9364 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
9366 /* Frame handling. */
9367 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
9368 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
9369 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
9371 frame_base_set_default (gdbarch
, &arm_normal_base
);
9373 /* Address manipulation. */
9374 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
9376 /* Advance PC across function entry code. */
9377 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
9379 /* Detect whether PC is at a point where the stack has been destroyed. */
9380 set_gdbarch_stack_frame_destroyed_p (gdbarch
, arm_stack_frame_destroyed_p
);
9382 /* Skip trampolines. */
9383 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
9385 /* The stack grows downward. */
9386 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
9388 /* Breakpoint manipulation. */
9389 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, arm_breakpoint_kind_from_pc
);
9390 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, arm_sw_breakpoint_from_kind
);
9391 set_gdbarch_breakpoint_kind_from_current_state (gdbarch
,
9392 arm_breakpoint_kind_from_current_state
);
9394 /* Information about registers, etc. */
9395 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
9396 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
9397 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
9398 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9399 set_gdbarch_register_reggroup_p (gdbarch
, arm_register_reggroup_p
);
9401 /* This "info float" is FPA-specific. Use the generic version if we
9403 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
9404 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
9406 /* Internal <-> external register number maps. */
9407 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
9408 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
9410 set_gdbarch_register_name (gdbarch
, arm_register_name
);
9412 /* Returning results. */
9413 set_gdbarch_return_value (gdbarch
, arm_return_value
);
9416 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
9418 /* Minsymbol frobbing. */
9419 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
9420 set_gdbarch_coff_make_msymbol_special (gdbarch
,
9421 arm_coff_make_msymbol_special
);
9422 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
9424 /* Thumb-2 IT block support. */
9425 set_gdbarch_adjust_breakpoint_address (gdbarch
,
9426 arm_adjust_breakpoint_address
);
9428 /* Virtual tables. */
9429 set_gdbarch_vbit_in_delta (gdbarch
, 1);
9431 /* Hook in the ABI-specific overrides, if they have been registered. */
9432 gdbarch_init_osabi (info
, gdbarch
);
9434 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
9436 /* Add some default predicates. */
9438 frame_unwind_append_unwinder (gdbarch
, &arm_m_exception_unwind
);
9439 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
9440 dwarf2_append_unwinders (gdbarch
);
9441 frame_unwind_append_unwinder (gdbarch
, &arm_exidx_unwind
);
9442 frame_unwind_append_unwinder (gdbarch
, &arm_epilogue_frame_unwind
);
9443 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
9445 /* Now we have tuned the configuration, set a few final things,
9446 based on what the OS ABI has told us. */
9448 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
9449 binaries are always marked. */
9450 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
9451 tdep
->arm_abi
= ARM_ABI_APCS
;
9453 /* Watchpoints are not steppable. */
9454 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
9456 /* We used to default to FPA for generic ARM, but almost nobody
9457 uses that now, and we now provide a way for the user to force
9458 the model. So default to the most useful variant. */
9459 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
9460 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
9462 if (tdep
->jb_pc
>= 0)
9463 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
9465 /* Floating point sizes and format. */
9466 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
9467 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
9469 set_gdbarch_double_format
9470 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9471 set_gdbarch_long_double_format
9472 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9476 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
9477 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
9480 if (have_vfp_pseudos
)
9482 /* NOTE: These are the only pseudo registers used by
9483 the ARM target at the moment. If more are added, a
9484 little more care in numbering will be needed. */
9486 int num_pseudos
= 32;
9487 if (have_neon_pseudos
)
9489 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
9490 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
9491 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
9496 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
9498 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
9500 /* Override tdesc_register_type to adjust the types of VFP
9501 registers for NEON. */
9502 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9505 /* Add standard register aliases. We add aliases even for those
9506 nanes which are used by the current architecture - it's simpler,
9507 and does no harm, since nothing ever lists user registers. */
9508 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
9509 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
9510 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
9512 set_gdbarch_disassembler_options (gdbarch
, &arm_disassembler_options
);
9513 set_gdbarch_valid_disassembler_options (gdbarch
, disassembler_options_arm ());
9519 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
9521 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9526 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
9527 (unsigned long) tdep
->lowest_pc
);
9533 static void arm_record_test (void);
9538 _initialize_arm_tdep (void)
9542 char regdesc
[1024], *rdptr
= regdesc
;
9543 size_t rest
= sizeof (regdesc
);
9545 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
9547 arm_objfile_data_key
9548 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
9550 /* Add ourselves to objfile event chain. */
9551 gdb::observers::new_objfile
.attach (arm_exidx_new_objfile
);
9553 = register_objfile_data_with_cleanup (NULL
, arm_exidx_data_free
);
9555 /* Register an ELF OS ABI sniffer for ARM binaries. */
9556 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
9557 bfd_target_elf_flavour
,
9558 arm_elf_osabi_sniffer
);
9560 /* Initialize the standard target descriptions. */
9561 initialize_tdesc_arm_with_m ();
9562 initialize_tdesc_arm_with_m_fpa_layout ();
9563 initialize_tdesc_arm_with_m_vfp_d16 ();
9564 initialize_tdesc_arm_with_iwmmxt ();
9565 initialize_tdesc_arm_with_vfpv2 ();
9566 initialize_tdesc_arm_with_vfpv3 ();
9567 initialize_tdesc_arm_with_neon ();
9569 /* Add root prefix command for all "set arm"/"show arm" commands. */
9570 add_prefix_cmd ("arm", no_class
, set_arm_command
,
9571 _("Various ARM-specific commands."),
9572 &setarmcmdlist
, "set arm ", 0, &setlist
);
9574 add_prefix_cmd ("arm", no_class
, show_arm_command
,
9575 _("Various ARM-specific commands."),
9576 &showarmcmdlist
, "show arm ", 0, &showlist
);
9579 arm_disassembler_options
= xstrdup ("reg-names-std");
9580 const disasm_options_t
*disasm_options
= disassembler_options_arm ();
9581 int num_disassembly_styles
= 0;
9582 for (i
= 0; disasm_options
->name
[i
] != NULL
; i
++)
9583 if (CONST_STRNEQ (disasm_options
->name
[i
], "reg-names-"))
9584 num_disassembly_styles
++;
9586 /* Initialize the array that will be passed to add_setshow_enum_cmd(). */
9587 valid_disassembly_styles
= XNEWVEC (const char *,
9588 num_disassembly_styles
+ 1);
9589 for (i
= j
= 0; disasm_options
->name
[i
] != NULL
; i
++)
9590 if (CONST_STRNEQ (disasm_options
->name
[i
], "reg-names-"))
9592 size_t offset
= strlen ("reg-names-");
9593 const char *style
= disasm_options
->name
[i
];
9594 valid_disassembly_styles
[j
++] = &style
[offset
];
9595 length
= snprintf (rdptr
, rest
, "%s - %s\n", &style
[offset
],
9596 disasm_options
->description
[i
]);
9600 /* Mark the end of valid options. */
9601 valid_disassembly_styles
[num_disassembly_styles
] = NULL
;
9603 /* Create the help text. */
9604 std::string helptext
= string_printf ("%s%s%s",
9605 _("The valid values are:\n"),
9607 _("The default is \"std\"."));
9609 add_setshow_enum_cmd("disassembler", no_class
,
9610 valid_disassembly_styles
, &disassembly_style
,
9611 _("Set the disassembly style."),
9612 _("Show the disassembly style."),
9614 set_disassembly_style_sfunc
,
9615 show_disassembly_style_sfunc
,
9616 &setarmcmdlist
, &showarmcmdlist
);
9618 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
9619 _("Set usage of ARM 32-bit mode."),
9620 _("Show usage of ARM 32-bit mode."),
9621 _("When off, a 26-bit PC will be used."),
9623 NULL
, /* FIXME: i18n: Usage of ARM 32-bit
9625 &setarmcmdlist
, &showarmcmdlist
);
9627 /* Add a command to allow the user to force the FPU model. */
9628 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
9629 _("Set the floating point type."),
9630 _("Show the floating point type."),
9631 _("auto - Determine the FP typefrom the OS-ABI.\n\
9632 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
9633 fpa - FPA co-processor (GCC compiled).\n\
9634 softvfp - Software FP with pure-endian doubles.\n\
9635 vfp - VFP co-processor."),
9636 set_fp_model_sfunc
, show_fp_model
,
9637 &setarmcmdlist
, &showarmcmdlist
);
9639 /* Add a command to allow the user to force the ABI. */
9640 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
9643 NULL
, arm_set_abi
, arm_show_abi
,
9644 &setarmcmdlist
, &showarmcmdlist
);
9646 /* Add two commands to allow the user to force the assumed
9648 add_setshow_enum_cmd ("fallback-mode", class_support
,
9649 arm_mode_strings
, &arm_fallback_mode_string
,
9650 _("Set the mode assumed when symbols are unavailable."),
9651 _("Show the mode assumed when symbols are unavailable."),
9652 NULL
, NULL
, arm_show_fallback_mode
,
9653 &setarmcmdlist
, &showarmcmdlist
);
9654 add_setshow_enum_cmd ("force-mode", class_support
,
9655 arm_mode_strings
, &arm_force_mode_string
,
9656 _("Set the mode assumed even when symbols are available."),
9657 _("Show the mode assumed even when symbols are available."),
9658 NULL
, NULL
, arm_show_force_mode
,
9659 &setarmcmdlist
, &showarmcmdlist
);
9661 /* Debugging flag. */
9662 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
9663 _("Set ARM debugging."),
9664 _("Show ARM debugging."),
9665 _("When on, arm-specific debugging is enabled."),
9667 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
9668 &setdebuglist
, &showdebuglist
);
9671 selftests::register_test ("arm-record", selftests::arm_record_test
);
9676 /* ARM-reversible process record data structures. */
9678 #define ARM_INSN_SIZE_BYTES 4
9679 #define THUMB_INSN_SIZE_BYTES 2
9680 #define THUMB2_INSN_SIZE_BYTES 4
9683 /* Position of the bit within a 32-bit ARM instruction
9684 that defines whether the instruction is a load or store. */
9685 #define INSN_S_L_BIT_NUM 20
9687 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
9690 unsigned int reg_len = LENGTH; \
9693 REGS = XNEWVEC (uint32_t, reg_len); \
9694 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
9699 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
9702 unsigned int mem_len = LENGTH; \
9705 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
9706 memcpy(&MEMS->len, &RECORD_BUF[0], \
9707 sizeof(struct arm_mem_r) * LENGTH); \
9712 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
9713 #define INSN_RECORDED(ARM_RECORD) \
9714 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
9716 /* ARM memory record structure. */
9719 uint32_t len
; /* Record length. */
9720 uint32_t addr
; /* Memory address. */
9723 /* ARM instruction record contains opcode of current insn
9724 and execution state (before entry to decode_insn()),
9725 contains list of to-be-modified registers and
9726 memory blocks (on return from decode_insn()). */
9728 typedef struct insn_decode_record_t
9730 struct gdbarch
*gdbarch
;
9731 struct regcache
*regcache
;
9732 CORE_ADDR this_addr
; /* Address of the insn being decoded. */
9733 uint32_t arm_insn
; /* Should accommodate thumb. */
9734 uint32_t cond
; /* Condition code. */
9735 uint32_t opcode
; /* Insn opcode. */
9736 uint32_t decode
; /* Insn decode bits. */
9737 uint32_t mem_rec_count
; /* No of mem records. */
9738 uint32_t reg_rec_count
; /* No of reg records. */
9739 uint32_t *arm_regs
; /* Registers to be saved for this record. */
9740 struct arm_mem_r
*arm_mems
; /* Memory to be saved for this record. */
9741 } insn_decode_record
;
9744 /* Checks ARM SBZ and SBO mandatory fields. */
9747 sbo_sbz (uint32_t insn
, uint32_t bit_num
, uint32_t len
, uint32_t sbo
)
9749 uint32_t ones
= bits (insn
, bit_num
- 1, (bit_num
-1) + (len
- 1));
9768 enum arm_record_result
9770 ARM_RECORD_SUCCESS
= 0,
9771 ARM_RECORD_FAILURE
= 1
9778 } arm_record_strx_t
;
9789 arm_record_strx (insn_decode_record
*arm_insn_r
, uint32_t *record_buf
,
9790 uint32_t *record_buf_mem
, arm_record_strx_t str_type
)
9793 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
9794 ULONGEST u_regval
[2]= {0};
9796 uint32_t reg_src1
= 0, reg_src2
= 0;
9797 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
9799 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
9800 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
9802 if (14 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
9804 /* 1) Handle misc store, immediate offset. */
9805 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9806 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9807 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9808 regcache_raw_read_unsigned (reg_cache
, reg_src1
,
9810 if (ARM_PC_REGNUM
== reg_src1
)
9812 /* If R15 was used as Rn, hence current PC+8. */
9813 u_regval
[0] = u_regval
[0] + 8;
9815 offset_8
= (immed_high
<< 4) | immed_low
;
9816 /* Calculate target store address. */
9817 if (14 == arm_insn_r
->opcode
)
9819 tgt_mem_addr
= u_regval
[0] + offset_8
;
9823 tgt_mem_addr
= u_regval
[0] - offset_8
;
9825 if (ARM_RECORD_STRH
== str_type
)
9827 record_buf_mem
[0] = 2;
9828 record_buf_mem
[1] = tgt_mem_addr
;
9829 arm_insn_r
->mem_rec_count
= 1;
9831 else if (ARM_RECORD_STRD
== str_type
)
9833 record_buf_mem
[0] = 4;
9834 record_buf_mem
[1] = tgt_mem_addr
;
9835 record_buf_mem
[2] = 4;
9836 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9837 arm_insn_r
->mem_rec_count
= 2;
9840 else if (12 == arm_insn_r
->opcode
|| 8 == arm_insn_r
->opcode
)
9842 /* 2) Store, register offset. */
9844 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9846 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9847 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9848 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9851 /* If R15 was used as Rn, hence current PC+8. */
9852 u_regval
[0] = u_regval
[0] + 8;
9854 /* Calculate target store address, Rn +/- Rm, register offset. */
9855 if (12 == arm_insn_r
->opcode
)
9857 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9861 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9863 if (ARM_RECORD_STRH
== str_type
)
9865 record_buf_mem
[0] = 2;
9866 record_buf_mem
[1] = tgt_mem_addr
;
9867 arm_insn_r
->mem_rec_count
= 1;
9869 else if (ARM_RECORD_STRD
== str_type
)
9871 record_buf_mem
[0] = 4;
9872 record_buf_mem
[1] = tgt_mem_addr
;
9873 record_buf_mem
[2] = 4;
9874 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9875 arm_insn_r
->mem_rec_count
= 2;
9878 else if (11 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
9879 || 2 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9881 /* 3) Store, immediate pre-indexed. */
9882 /* 5) Store, immediate post-indexed. */
9883 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9884 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9885 offset_8
= (immed_high
<< 4) | immed_low
;
9886 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9887 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9888 /* Calculate target store address, Rn +/- Rm, register offset. */
9889 if (15 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9891 tgt_mem_addr
= u_regval
[0] + offset_8
;
9895 tgt_mem_addr
= u_regval
[0] - offset_8
;
9897 if (ARM_RECORD_STRH
== str_type
)
9899 record_buf_mem
[0] = 2;
9900 record_buf_mem
[1] = tgt_mem_addr
;
9901 arm_insn_r
->mem_rec_count
= 1;
9903 else if (ARM_RECORD_STRD
== str_type
)
9905 record_buf_mem
[0] = 4;
9906 record_buf_mem
[1] = tgt_mem_addr
;
9907 record_buf_mem
[2] = 4;
9908 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9909 arm_insn_r
->mem_rec_count
= 2;
9911 /* Record Rn also as it changes. */
9912 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
9913 arm_insn_r
->reg_rec_count
= 1;
9915 else if (9 == arm_insn_r
->opcode
|| 13 == arm_insn_r
->opcode
9916 || 0 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9918 /* 4) Store, register pre-indexed. */
9919 /* 6) Store, register post -indexed. */
9920 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9921 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9922 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9923 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9924 /* Calculate target store address, Rn +/- Rm, register offset. */
9925 if (13 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9927 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9931 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9933 if (ARM_RECORD_STRH
== str_type
)
9935 record_buf_mem
[0] = 2;
9936 record_buf_mem
[1] = tgt_mem_addr
;
9937 arm_insn_r
->mem_rec_count
= 1;
9939 else if (ARM_RECORD_STRD
== str_type
)
9941 record_buf_mem
[0] = 4;
9942 record_buf_mem
[1] = tgt_mem_addr
;
9943 record_buf_mem
[2] = 4;
9944 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9945 arm_insn_r
->mem_rec_count
= 2;
9947 /* Record Rn also as it changes. */
9948 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
9949 arm_insn_r
->reg_rec_count
= 1;
9954 /* Handling ARM extension space insns. */
9957 arm_record_extension_space (insn_decode_record
*arm_insn_r
)
9959 int ret
= 0; /* Return value: -1:record failure ; 0:success */
9960 uint32_t opcode1
= 0, opcode2
= 0, insn_op1
= 0;
9961 uint32_t record_buf
[8], record_buf_mem
[8];
9962 uint32_t reg_src1
= 0;
9963 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
9964 ULONGEST u_regval
= 0;
9966 gdb_assert (!INSN_RECORDED(arm_insn_r
));
9967 /* Handle unconditional insn extension space. */
9969 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 27);
9970 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
9971 if (arm_insn_r
->cond
)
9973 /* PLD has no affect on architectural state, it just affects
9975 if (5 == ((opcode1
& 0xE0) >> 5))
9978 record_buf
[0] = ARM_PS_REGNUM
;
9979 record_buf
[1] = ARM_LR_REGNUM
;
9980 arm_insn_r
->reg_rec_count
= 2;
9982 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
9986 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
9987 if (3 == opcode1
&& bit (arm_insn_r
->arm_insn
, 4))
9990 /* Undefined instruction on ARM V5; need to handle if later
9991 versions define it. */
9994 opcode1
= bits (arm_insn_r
->arm_insn
, 24, 27);
9995 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
9996 insn_op1
= bits (arm_insn_r
->arm_insn
, 20, 23);
9998 /* Handle arithmetic insn extension space. */
9999 if (!opcode1
&& 9 == opcode2
&& 1 != arm_insn_r
->cond
10000 && !INSN_RECORDED(arm_insn_r
))
10002 /* Handle MLA(S) and MUL(S). */
10003 if (in_inclusive_range (insn_op1
, 0U, 3U))
10005 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10006 record_buf
[1] = ARM_PS_REGNUM
;
10007 arm_insn_r
->reg_rec_count
= 2;
10009 else if (in_inclusive_range (insn_op1
, 4U, 15U))
10011 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
10012 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10013 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10014 record_buf
[2] = ARM_PS_REGNUM
;
10015 arm_insn_r
->reg_rec_count
= 3;
10019 opcode1
= bits (arm_insn_r
->arm_insn
, 26, 27);
10020 opcode2
= bits (arm_insn_r
->arm_insn
, 23, 24);
10021 insn_op1
= bits (arm_insn_r
->arm_insn
, 21, 22);
10023 /* Handle control insn extension space. */
10025 if (!opcode1
&& 2 == opcode2
&& !bit (arm_insn_r
->arm_insn
, 20)
10026 && 1 != arm_insn_r
->cond
&& !INSN_RECORDED(arm_insn_r
))
10028 if (!bit (arm_insn_r
->arm_insn
,25))
10030 if (!bits (arm_insn_r
->arm_insn
, 4, 7))
10032 if ((0 == insn_op1
) || (2 == insn_op1
))
10035 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10036 arm_insn_r
->reg_rec_count
= 1;
10038 else if (1 == insn_op1
)
10040 /* CSPR is going to be changed. */
10041 record_buf
[0] = ARM_PS_REGNUM
;
10042 arm_insn_r
->reg_rec_count
= 1;
10044 else if (3 == insn_op1
)
10046 /* SPSR is going to be changed. */
10047 /* We need to get SPSR value, which is yet to be done. */
10051 else if (1 == bits (arm_insn_r
->arm_insn
, 4, 7))
10056 record_buf
[0] = ARM_PS_REGNUM
;
10057 arm_insn_r
->reg_rec_count
= 1;
10059 else if (3 == insn_op1
)
10062 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10063 arm_insn_r
->reg_rec_count
= 1;
10066 else if (3 == bits (arm_insn_r
->arm_insn
, 4, 7))
10069 record_buf
[0] = ARM_PS_REGNUM
;
10070 record_buf
[1] = ARM_LR_REGNUM
;
10071 arm_insn_r
->reg_rec_count
= 2;
10073 else if (5 == bits (arm_insn_r
->arm_insn
, 4, 7))
10075 /* QADD, QSUB, QDADD, QDSUB */
10076 record_buf
[0] = ARM_PS_REGNUM
;
10077 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10078 arm_insn_r
->reg_rec_count
= 2;
10080 else if (7 == bits (arm_insn_r
->arm_insn
, 4, 7))
10083 record_buf
[0] = ARM_PS_REGNUM
;
10084 record_buf
[1] = ARM_LR_REGNUM
;
10085 arm_insn_r
->reg_rec_count
= 2;
10087 /* Save SPSR also;how? */
10090 else if(8 == bits (arm_insn_r
->arm_insn
, 4, 7)
10091 || 10 == bits (arm_insn_r
->arm_insn
, 4, 7)
10092 || 12 == bits (arm_insn_r
->arm_insn
, 4, 7)
10093 || 14 == bits (arm_insn_r
->arm_insn
, 4, 7)
10096 if (0 == insn_op1
|| 1 == insn_op1
)
10098 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
10099 /* We dont do optimization for SMULW<y> where we
10101 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10102 record_buf
[1] = ARM_PS_REGNUM
;
10103 arm_insn_r
->reg_rec_count
= 2;
10105 else if (2 == insn_op1
)
10108 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10109 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
10110 arm_insn_r
->reg_rec_count
= 2;
10112 else if (3 == insn_op1
)
10115 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10116 arm_insn_r
->reg_rec_count
= 1;
10122 /* MSR : immediate form. */
10125 /* CSPR is going to be changed. */
10126 record_buf
[0] = ARM_PS_REGNUM
;
10127 arm_insn_r
->reg_rec_count
= 1;
10129 else if (3 == insn_op1
)
10131 /* SPSR is going to be changed. */
10132 /* we need to get SPSR value, which is yet to be done */
10138 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10139 opcode2
= bits (arm_insn_r
->arm_insn
, 20, 24);
10140 insn_op1
= bits (arm_insn_r
->arm_insn
, 5, 6);
10142 /* Handle load/store insn extension space. */
10144 if (!opcode1
&& bit (arm_insn_r
->arm_insn
, 7)
10145 && bit (arm_insn_r
->arm_insn
, 4) && 1 != arm_insn_r
->cond
10146 && !INSN_RECORDED(arm_insn_r
))
10151 /* These insn, changes register and memory as well. */
10152 /* SWP or SWPB insn. */
10153 /* Get memory address given by Rn. */
10154 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10155 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
10156 /* SWP insn ?, swaps word. */
10157 if (8 == arm_insn_r
->opcode
)
10159 record_buf_mem
[0] = 4;
10163 /* SWPB insn, swaps only byte. */
10164 record_buf_mem
[0] = 1;
10166 record_buf_mem
[1] = u_regval
;
10167 arm_insn_r
->mem_rec_count
= 1;
10168 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10169 arm_insn_r
->reg_rec_count
= 1;
10171 else if (1 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10174 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10177 else if (2 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10180 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10181 record_buf
[1] = record_buf
[0] + 1;
10182 arm_insn_r
->reg_rec_count
= 2;
10184 else if (3 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10187 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10190 else if (bit (arm_insn_r
->arm_insn
, 20) && insn_op1
<= 3)
10192 /* LDRH, LDRSB, LDRSH. */
10193 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10194 arm_insn_r
->reg_rec_count
= 1;
10199 opcode1
= bits (arm_insn_r
->arm_insn
, 23, 27);
10200 if (24 == opcode1
&& bit (arm_insn_r
->arm_insn
, 21)
10201 && !INSN_RECORDED(arm_insn_r
))
10204 /* Handle coprocessor insn extension space. */
10207 /* To be done for ARMv5 and later; as of now we return -1. */
10211 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10212 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10217 /* Handling opcode 000 insns. */
10220 arm_record_data_proc_misc_ld_str (insn_decode_record
*arm_insn_r
)
10222 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10223 uint32_t record_buf
[8], record_buf_mem
[8];
10224 ULONGEST u_regval
[2] = {0};
10226 uint32_t reg_src1
= 0, reg_dest
= 0;
10227 uint32_t opcode1
= 0;
10229 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10230 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10231 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
10233 if (!((opcode1
& 0x19) == 0x10))
10235 /* Data-processing (register) and Data-processing (register-shifted
10237 /* Out of 11 shifter operands mode, all the insn modifies destination
10238 register, which is specified by 13-16 decode. */
10239 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10240 record_buf
[1] = ARM_PS_REGNUM
;
10241 arm_insn_r
->reg_rec_count
= 2;
10243 else if ((arm_insn_r
->decode
< 8) && ((opcode1
& 0x19) == 0x10))
10245 /* Miscellaneous instructions */
10247 if (3 == arm_insn_r
->decode
&& 0x12 == opcode1
10248 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10250 /* Handle BLX, branch and link/exchange. */
10251 if (9 == arm_insn_r
->opcode
)
10253 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
10254 and R14 stores the return address. */
10255 record_buf
[0] = ARM_PS_REGNUM
;
10256 record_buf
[1] = ARM_LR_REGNUM
;
10257 arm_insn_r
->reg_rec_count
= 2;
10260 else if (7 == arm_insn_r
->decode
&& 0x12 == opcode1
)
10262 /* Handle enhanced software breakpoint insn, BKPT. */
10263 /* CPSR is changed to be executed in ARM state, disabling normal
10264 interrupts, entering abort mode. */
10265 /* According to high vector configuration PC is set. */
10266 /* user hit breakpoint and type reverse, in
10267 that case, we need to go back with previous CPSR and
10268 Program Counter. */
10269 record_buf
[0] = ARM_PS_REGNUM
;
10270 record_buf
[1] = ARM_LR_REGNUM
;
10271 arm_insn_r
->reg_rec_count
= 2;
10273 /* Save SPSR also; how? */
10276 else if (1 == arm_insn_r
->decode
&& 0x12 == opcode1
10277 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10279 /* Handle BX, branch and link/exchange. */
10280 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
10281 record_buf
[0] = ARM_PS_REGNUM
;
10282 arm_insn_r
->reg_rec_count
= 1;
10284 else if (1 == arm_insn_r
->decode
&& 0x16 == opcode1
10285 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 4, 1)
10286 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1))
10288 /* Count leading zeros: CLZ. */
10289 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10290 arm_insn_r
->reg_rec_count
= 1;
10292 else if (!bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
10293 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10294 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1)
10295 && sbo_sbz (arm_insn_r
->arm_insn
, 1, 12, 0))
10297 /* Handle MRS insn. */
10298 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10299 arm_insn_r
->reg_rec_count
= 1;
10302 else if (9 == arm_insn_r
->decode
&& opcode1
< 0x10)
10304 /* Multiply and multiply-accumulate */
10306 /* Handle multiply instructions. */
10307 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
10308 if (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)
10310 /* Handle MLA and MUL. */
10311 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10312 record_buf
[1] = ARM_PS_REGNUM
;
10313 arm_insn_r
->reg_rec_count
= 2;
10315 else if (4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
10317 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
10318 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10319 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10320 record_buf
[2] = ARM_PS_REGNUM
;
10321 arm_insn_r
->reg_rec_count
= 3;
10324 else if (9 == arm_insn_r
->decode
&& opcode1
> 0x10)
10326 /* Synchronization primitives */
10328 /* Handling SWP, SWPB. */
10329 /* These insn, changes register and memory as well. */
10330 /* SWP or SWPB insn. */
10332 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10333 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10334 /* SWP insn ?, swaps word. */
10335 if (8 == arm_insn_r
->opcode
)
10337 record_buf_mem
[0] = 4;
10341 /* SWPB insn, swaps only byte. */
10342 record_buf_mem
[0] = 1;
10344 record_buf_mem
[1] = u_regval
[0];
10345 arm_insn_r
->mem_rec_count
= 1;
10346 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10347 arm_insn_r
->reg_rec_count
= 1;
10349 else if (11 == arm_insn_r
->decode
|| 13 == arm_insn_r
->decode
10350 || 15 == arm_insn_r
->decode
)
10352 if ((opcode1
& 0x12) == 2)
10354 /* Extra load/store (unprivileged) */
10359 /* Extra load/store */
10360 switch (bits (arm_insn_r
->arm_insn
, 5, 6))
10363 if ((opcode1
& 0x05) == 0x0 || (opcode1
& 0x05) == 0x4)
10365 /* STRH (register), STRH (immediate) */
10366 arm_record_strx (arm_insn_r
, &record_buf
[0],
10367 &record_buf_mem
[0], ARM_RECORD_STRH
);
10369 else if ((opcode1
& 0x05) == 0x1)
10371 /* LDRH (register) */
10372 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10373 arm_insn_r
->reg_rec_count
= 1;
10375 if (bit (arm_insn_r
->arm_insn
, 21))
10377 /* Write back to Rn. */
10378 record_buf
[arm_insn_r
->reg_rec_count
++]
10379 = bits (arm_insn_r
->arm_insn
, 16, 19);
10382 else if ((opcode1
& 0x05) == 0x5)
10384 /* LDRH (immediate), LDRH (literal) */
10385 int rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
10387 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10388 arm_insn_r
->reg_rec_count
= 1;
10392 /*LDRH (immediate) */
10393 if (bit (arm_insn_r
->arm_insn
, 21))
10395 /* Write back to Rn. */
10396 record_buf
[arm_insn_r
->reg_rec_count
++] = rn
;
10404 if ((opcode1
& 0x05) == 0x0)
10406 /* LDRD (register) */
10407 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10408 record_buf
[1] = record_buf
[0] + 1;
10409 arm_insn_r
->reg_rec_count
= 2;
10411 if (bit (arm_insn_r
->arm_insn
, 21))
10413 /* Write back to Rn. */
10414 record_buf
[arm_insn_r
->reg_rec_count
++]
10415 = bits (arm_insn_r
->arm_insn
, 16, 19);
10418 else if ((opcode1
& 0x05) == 0x1)
10420 /* LDRSB (register) */
10421 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10422 arm_insn_r
->reg_rec_count
= 1;
10424 if (bit (arm_insn_r
->arm_insn
, 21))
10426 /* Write back to Rn. */
10427 record_buf
[arm_insn_r
->reg_rec_count
++]
10428 = bits (arm_insn_r
->arm_insn
, 16, 19);
10431 else if ((opcode1
& 0x05) == 0x4 || (opcode1
& 0x05) == 0x5)
10433 /* LDRD (immediate), LDRD (literal), LDRSB (immediate),
10435 int rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
10437 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10438 arm_insn_r
->reg_rec_count
= 1;
10442 /*LDRD (immediate), LDRSB (immediate) */
10443 if (bit (arm_insn_r
->arm_insn
, 21))
10445 /* Write back to Rn. */
10446 record_buf
[arm_insn_r
->reg_rec_count
++] = rn
;
10454 if ((opcode1
& 0x05) == 0x0)
10456 /* STRD (register) */
10457 arm_record_strx (arm_insn_r
, &record_buf
[0],
10458 &record_buf_mem
[0], ARM_RECORD_STRD
);
10460 else if ((opcode1
& 0x05) == 0x1)
10462 /* LDRSH (register) */
10463 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10464 arm_insn_r
->reg_rec_count
= 1;
10466 if (bit (arm_insn_r
->arm_insn
, 21))
10468 /* Write back to Rn. */
10469 record_buf
[arm_insn_r
->reg_rec_count
++]
10470 = bits (arm_insn_r
->arm_insn
, 16, 19);
10473 else if ((opcode1
& 0x05) == 0x4)
10475 /* STRD (immediate) */
10476 arm_record_strx (arm_insn_r
, &record_buf
[0],
10477 &record_buf_mem
[0], ARM_RECORD_STRD
);
10479 else if ((opcode1
& 0x05) == 0x5)
10481 /* LDRSH (immediate), LDRSH (literal) */
10482 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10483 arm_insn_r
->reg_rec_count
= 1;
10485 if (bit (arm_insn_r
->arm_insn
, 21))
10487 /* Write back to Rn. */
10488 record_buf
[arm_insn_r
->reg_rec_count
++]
10489 = bits (arm_insn_r
->arm_insn
, 16, 19);
10505 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10506 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10510 /* Handling opcode 001 insns. */
10513 arm_record_data_proc_imm (insn_decode_record
*arm_insn_r
)
10515 uint32_t record_buf
[8], record_buf_mem
[8];
10517 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10518 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10520 if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
10521 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21)
10522 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
10525 /* Handle MSR insn. */
10526 if (9 == arm_insn_r
->opcode
)
10528 /* CSPR is going to be changed. */
10529 record_buf
[0] = ARM_PS_REGNUM
;
10530 arm_insn_r
->reg_rec_count
= 1;
10534 /* SPSR is going to be changed. */
10537 else if (arm_insn_r
->opcode
<= 15)
10539 /* Normal data processing insns. */
10540 /* Out of 11 shifter operands mode, all the insn modifies destination
10541 register, which is specified by 13-16 decode. */
10542 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10543 record_buf
[1] = ARM_PS_REGNUM
;
10544 arm_insn_r
->reg_rec_count
= 2;
10551 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10552 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10557 arm_record_media (insn_decode_record
*arm_insn_r
)
10559 uint32_t record_buf
[8];
10561 switch (bits (arm_insn_r
->arm_insn
, 22, 24))
10564 /* Parallel addition and subtraction, signed */
10566 /* Parallel addition and subtraction, unsigned */
10569 /* Packing, unpacking, saturation and reversal */
10571 int rd
= bits (arm_insn_r
->arm_insn
, 12, 15);
10573 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10579 /* Signed multiplies */
10581 int rd
= bits (arm_insn_r
->arm_insn
, 16, 19);
10582 unsigned int op1
= bits (arm_insn_r
->arm_insn
, 20, 22);
10584 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10586 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10587 else if (op1
== 0x4)
10588 record_buf
[arm_insn_r
->reg_rec_count
++]
10589 = bits (arm_insn_r
->arm_insn
, 12, 15);
10595 if (bit (arm_insn_r
->arm_insn
, 21)
10596 && bits (arm_insn_r
->arm_insn
, 5, 6) == 0x2)
10599 record_buf
[arm_insn_r
->reg_rec_count
++]
10600 = bits (arm_insn_r
->arm_insn
, 12, 15);
10602 else if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x0
10603 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x0)
10605 /* USAD8 and USADA8 */
10606 record_buf
[arm_insn_r
->reg_rec_count
++]
10607 = bits (arm_insn_r
->arm_insn
, 16, 19);
10614 if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x3
10615 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x7)
10617 /* Permanently UNDEFINED */
10622 /* BFC, BFI and UBFX */
10623 record_buf
[arm_insn_r
->reg_rec_count
++]
10624 = bits (arm_insn_r
->arm_insn
, 12, 15);
10633 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10638 /* Handle ARM mode instructions with opcode 010. */
10641 arm_record_ld_st_imm_offset (insn_decode_record
*arm_insn_r
)
10643 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10645 uint32_t reg_base
, reg_dest
;
10646 uint32_t offset_12
, tgt_mem_addr
;
10647 uint32_t record_buf
[8], record_buf_mem
[8];
10648 unsigned char wback
;
10651 /* Calculate wback. */
10652 wback
= (bit (arm_insn_r
->arm_insn
, 24) == 0)
10653 || (bit (arm_insn_r
->arm_insn
, 21) == 1);
10655 arm_insn_r
->reg_rec_count
= 0;
10656 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
10658 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10660 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
10663 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10664 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_dest
;
10666 /* The LDR instruction is capable of doing branching. If MOV LR, PC
10667 preceeds a LDR instruction having R15 as reg_base, it
10668 emulates a branch and link instruction, and hence we need to save
10669 CPSR and PC as well. */
10670 if (ARM_PC_REGNUM
== reg_dest
)
10671 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10673 /* If wback is true, also save the base register, which is going to be
10676 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10680 /* STR (immediate), STRB (immediate), STRBT and STRT. */
10682 offset_12
= bits (arm_insn_r
->arm_insn
, 0, 11);
10683 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
10685 /* Handle bit U. */
10686 if (bit (arm_insn_r
->arm_insn
, 23))
10688 /* U == 1: Add the offset. */
10689 tgt_mem_addr
= (uint32_t) u_regval
+ offset_12
;
10693 /* U == 0: subtract the offset. */
10694 tgt_mem_addr
= (uint32_t) u_regval
- offset_12
;
10697 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
10699 if (bit (arm_insn_r
->arm_insn
, 22))
10701 /* STRB and STRBT: 1 byte. */
10702 record_buf_mem
[0] = 1;
10706 /* STR and STRT: 4 bytes. */
10707 record_buf_mem
[0] = 4;
10710 /* Handle bit P. */
10711 if (bit (arm_insn_r
->arm_insn
, 24))
10712 record_buf_mem
[1] = tgt_mem_addr
;
10714 record_buf_mem
[1] = (uint32_t) u_regval
;
10716 arm_insn_r
->mem_rec_count
= 1;
10718 /* If wback is true, also save the base register, which is going to be
10721 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10724 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10725 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10729 /* Handling opcode 011 insns. */
10732 arm_record_ld_st_reg_offset (insn_decode_record
*arm_insn_r
)
10734 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10736 uint32_t shift_imm
= 0;
10737 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
10738 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
10739 uint32_t record_buf
[8], record_buf_mem
[8];
10742 ULONGEST u_regval
[2];
10744 if (bit (arm_insn_r
->arm_insn
, 4))
10745 return arm_record_media (arm_insn_r
);
10747 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10748 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10750 /* Handle enhanced store insns and LDRD DSP insn,
10751 order begins according to addressing modes for store insns
10755 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10757 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10758 /* LDR insn has a capability to do branching, if
10759 MOV LR, PC is precedded by LDR insn having Rn as R15
10760 in that case, it emulates branch and link insn, and hence we
10761 need to save CSPR and PC as well. */
10762 if (15 != reg_dest
)
10764 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10765 arm_insn_r
->reg_rec_count
= 1;
10769 record_buf
[0] = reg_dest
;
10770 record_buf
[1] = ARM_PS_REGNUM
;
10771 arm_insn_r
->reg_rec_count
= 2;
10776 if (! bits (arm_insn_r
->arm_insn
, 4, 11))
10778 /* Store insn, register offset and register pre-indexed,
10779 register post-indexed. */
10781 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10783 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10784 regcache_raw_read_unsigned (reg_cache
, reg_src1
10786 regcache_raw_read_unsigned (reg_cache
, reg_src2
10788 if (15 == reg_src2
)
10790 /* If R15 was used as Rn, hence current PC+8. */
10791 /* Pre-indexed mode doesnt reach here ; illegal insn. */
10792 u_regval
[0] = u_regval
[0] + 8;
10794 /* Calculate target store address, Rn +/- Rm, register offset. */
10796 if (bit (arm_insn_r
->arm_insn
, 23))
10798 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10802 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10805 switch (arm_insn_r
->opcode
)
10819 record_buf_mem
[0] = 4;
10834 record_buf_mem
[0] = 1;
10838 gdb_assert_not_reached ("no decoding pattern found");
10841 record_buf_mem
[1] = tgt_mem_addr
;
10842 arm_insn_r
->mem_rec_count
= 1;
10844 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10845 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10846 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10847 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10848 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10849 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10852 /* Rn is going to be changed in pre-indexed mode and
10853 post-indexed mode as well. */
10854 record_buf
[0] = reg_src2
;
10855 arm_insn_r
->reg_rec_count
= 1;
10860 /* Store insn, scaled register offset; scaled pre-indexed. */
10861 offset_12
= bits (arm_insn_r
->arm_insn
, 5, 6);
10863 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10865 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10866 /* Get shift_imm. */
10867 shift_imm
= bits (arm_insn_r
->arm_insn
, 7, 11);
10868 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10869 regcache_raw_read_signed (reg_cache
, reg_src1
, &s_word
);
10870 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10871 /* Offset_12 used as shift. */
10875 /* Offset_12 used as index. */
10876 offset_12
= u_regval
[0] << shift_imm
;
10880 offset_12
= (!shift_imm
)?0:u_regval
[0] >> shift_imm
;
10886 if (bit (u_regval
[0], 31))
10888 offset_12
= 0xFFFFFFFF;
10897 /* This is arithmetic shift. */
10898 offset_12
= s_word
>> shift_imm
;
10905 regcache_raw_read_unsigned (reg_cache
, ARM_PS_REGNUM
,
10907 /* Get C flag value and shift it by 31. */
10908 offset_12
= (((bit (u_regval
[1], 29)) << 31) \
10909 | (u_regval
[0]) >> 1);
10913 offset_12
= (u_regval
[0] >> shift_imm
) \
10915 (sizeof(uint32_t) - shift_imm
));
10920 gdb_assert_not_reached ("no decoding pattern found");
10924 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10926 if (bit (arm_insn_r
->arm_insn
, 23))
10928 tgt_mem_addr
= u_regval
[1] + offset_12
;
10932 tgt_mem_addr
= u_regval
[1] - offset_12
;
10935 switch (arm_insn_r
->opcode
)
10949 record_buf_mem
[0] = 4;
10964 record_buf_mem
[0] = 1;
10968 gdb_assert_not_reached ("no decoding pattern found");
10971 record_buf_mem
[1] = tgt_mem_addr
;
10972 arm_insn_r
->mem_rec_count
= 1;
10974 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10975 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10976 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10977 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10978 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10979 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10982 /* Rn is going to be changed in register scaled pre-indexed
10983 mode,and scaled post indexed mode. */
10984 record_buf
[0] = reg_src2
;
10985 arm_insn_r
->reg_rec_count
= 1;
10990 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10991 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10995 /* Handle ARM mode instructions with opcode 100. */
10998 arm_record_ld_st_multiple (insn_decode_record
*arm_insn_r
)
11000 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11001 uint32_t register_count
= 0, register_bits
;
11002 uint32_t reg_base
, addr_mode
;
11003 uint32_t record_buf
[24], record_buf_mem
[48];
11007 /* Fetch the list of registers. */
11008 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
11009 arm_insn_r
->reg_rec_count
= 0;
11011 /* Fetch the base register that contains the address we are loading data
11013 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
11015 /* Calculate wback. */
11016 wback
= (bit (arm_insn_r
->arm_insn
, 21) == 1);
11018 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11020 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
11022 /* Find out which registers are going to be loaded from memory. */
11023 while (register_bits
)
11025 if (register_bits
& 0x00000001)
11026 record_buf
[arm_insn_r
->reg_rec_count
++] = register_count
;
11027 register_bits
= register_bits
>> 1;
11032 /* If wback is true, also save the base register, which is going to be
11035 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11037 /* Save the CPSR register. */
11038 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
11042 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
11044 addr_mode
= bits (arm_insn_r
->arm_insn
, 23, 24);
11046 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
11048 /* Find out how many registers are going to be stored to memory. */
11049 while (register_bits
)
11051 if (register_bits
& 0x00000001)
11053 register_bits
= register_bits
>> 1;
11058 /* STMDA (STMED): Decrement after. */
11060 record_buf_mem
[1] = (uint32_t) u_regval
11061 - register_count
* INT_REGISTER_SIZE
+ 4;
11063 /* STM (STMIA, STMEA): Increment after. */
11065 record_buf_mem
[1] = (uint32_t) u_regval
;
11067 /* STMDB (STMFD): Decrement before. */
11069 record_buf_mem
[1] = (uint32_t) u_regval
11070 - register_count
* INT_REGISTER_SIZE
;
11072 /* STMIB (STMFA): Increment before. */
11074 record_buf_mem
[1] = (uint32_t) u_regval
+ INT_REGISTER_SIZE
;
11077 gdb_assert_not_reached ("no decoding pattern found");
11081 record_buf_mem
[0] = register_count
* INT_REGISTER_SIZE
;
11082 arm_insn_r
->mem_rec_count
= 1;
11084 /* If wback is true, also save the base register, which is going to be
11087 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11090 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11091 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11095 /* Handling opcode 101 insns. */
11098 arm_record_b_bl (insn_decode_record
*arm_insn_r
)
11100 uint32_t record_buf
[8];
11102 /* Handle B, BL, BLX(1) insns. */
11103 /* B simply branches so we do nothing here. */
11104 /* Note: BLX(1) doesnt fall here but instead it falls into
11105 extension space. */
11106 if (bit (arm_insn_r
->arm_insn
, 24))
11108 record_buf
[0] = ARM_LR_REGNUM
;
11109 arm_insn_r
->reg_rec_count
= 1;
11112 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11118 arm_record_unsupported_insn (insn_decode_record
*arm_insn_r
)
11120 printf_unfiltered (_("Process record does not support instruction "
11121 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11122 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11127 /* Record handler for vector data transfer instructions. */
11130 arm_record_vdata_transfer_insn (insn_decode_record
*arm_insn_r
)
11132 uint32_t bits_a
, bit_c
, bit_l
, reg_t
, reg_v
;
11133 uint32_t record_buf
[4];
11135 reg_t
= bits (arm_insn_r
->arm_insn
, 12, 15);
11136 reg_v
= bits (arm_insn_r
->arm_insn
, 21, 23);
11137 bits_a
= bits (arm_insn_r
->arm_insn
, 21, 23);
11138 bit_l
= bit (arm_insn_r
->arm_insn
, 20);
11139 bit_c
= bit (arm_insn_r
->arm_insn
, 8);
11141 /* Handle VMOV instruction. */
11142 if (bit_l
&& bit_c
)
11144 record_buf
[0] = reg_t
;
11145 arm_insn_r
->reg_rec_count
= 1;
11147 else if (bit_l
&& !bit_c
)
11149 /* Handle VMOV instruction. */
11150 if (bits_a
== 0x00)
11152 record_buf
[0] = reg_t
;
11153 arm_insn_r
->reg_rec_count
= 1;
11155 /* Handle VMRS instruction. */
11156 else if (bits_a
== 0x07)
11159 reg_t
= ARM_PS_REGNUM
;
11161 record_buf
[0] = reg_t
;
11162 arm_insn_r
->reg_rec_count
= 1;
11165 else if (!bit_l
&& !bit_c
)
11167 /* Handle VMOV instruction. */
11168 if (bits_a
== 0x00)
11170 record_buf
[0] = ARM_D0_REGNUM
+ reg_v
;
11172 arm_insn_r
->reg_rec_count
= 1;
11174 /* Handle VMSR instruction. */
11175 else if (bits_a
== 0x07)
11177 record_buf
[0] = ARM_FPSCR_REGNUM
;
11178 arm_insn_r
->reg_rec_count
= 1;
11181 else if (!bit_l
&& bit_c
)
11183 /* Handle VMOV instruction. */
11184 if (!(bits_a
& 0x04))
11186 record_buf
[0] = (reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4))
11188 arm_insn_r
->reg_rec_count
= 1;
11190 /* Handle VDUP instruction. */
11193 if (bit (arm_insn_r
->arm_insn
, 21))
11195 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11196 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11197 record_buf
[1] = reg_v
+ ARM_D0_REGNUM
+ 1;
11198 arm_insn_r
->reg_rec_count
= 2;
11202 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11203 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11204 arm_insn_r
->reg_rec_count
= 1;
11209 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11213 /* Record handler for extension register load/store instructions. */
11216 arm_record_exreg_ld_st_insn (insn_decode_record
*arm_insn_r
)
11218 uint32_t opcode
, single_reg
;
11219 uint8_t op_vldm_vstm
;
11220 uint32_t record_buf
[8], record_buf_mem
[128];
11221 ULONGEST u_regval
= 0;
11223 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11225 opcode
= bits (arm_insn_r
->arm_insn
, 20, 24);
11226 single_reg
= !bit (arm_insn_r
->arm_insn
, 8);
11227 op_vldm_vstm
= opcode
& 0x1b;
11229 /* Handle VMOV instructions. */
11230 if ((opcode
& 0x1e) == 0x04)
11232 if (bit (arm_insn_r
->arm_insn
, 20)) /* to_arm_registers bit 20? */
11234 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11235 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11236 arm_insn_r
->reg_rec_count
= 2;
11240 uint8_t reg_m
= bits (arm_insn_r
->arm_insn
, 0, 3);
11241 uint8_t bit_m
= bit (arm_insn_r
->arm_insn
, 5);
11245 /* The first S register number m is REG_M:M (M is bit 5),
11246 the corresponding D register number is REG_M:M / 2, which
11248 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_D0_REGNUM
+ reg_m
;
11249 /* The second S register number is REG_M:M + 1, the
11250 corresponding D register number is (REG_M:M + 1) / 2.
11251 IOW, if bit M is 1, the first and second S registers
11252 are mapped to different D registers, otherwise, they are
11253 in the same D register. */
11256 record_buf
[arm_insn_r
->reg_rec_count
++]
11257 = ARM_D0_REGNUM
+ reg_m
+ 1;
11262 record_buf
[0] = ((bit_m
<< 4) + reg_m
+ ARM_D0_REGNUM
);
11263 arm_insn_r
->reg_rec_count
= 1;
11267 /* Handle VSTM and VPUSH instructions. */
11268 else if (op_vldm_vstm
== 0x08 || op_vldm_vstm
== 0x0a
11269 || op_vldm_vstm
== 0x12)
11271 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
11272 uint32_t memory_index
= 0;
11274 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11275 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11276 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11277 imm_off32
= imm_off8
<< 2;
11278 memory_count
= imm_off8
;
11280 if (bit (arm_insn_r
->arm_insn
, 23))
11281 start_address
= u_regval
;
11283 start_address
= u_regval
- imm_off32
;
11285 if (bit (arm_insn_r
->arm_insn
, 21))
11287 record_buf
[0] = reg_rn
;
11288 arm_insn_r
->reg_rec_count
= 1;
11291 while (memory_count
> 0)
11295 record_buf_mem
[memory_index
] = 4;
11296 record_buf_mem
[memory_index
+ 1] = start_address
;
11297 start_address
= start_address
+ 4;
11298 memory_index
= memory_index
+ 2;
11302 record_buf_mem
[memory_index
] = 4;
11303 record_buf_mem
[memory_index
+ 1] = start_address
;
11304 record_buf_mem
[memory_index
+ 2] = 4;
11305 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11306 start_address
= start_address
+ 8;
11307 memory_index
= memory_index
+ 4;
11311 arm_insn_r
->mem_rec_count
= (memory_index
>> 1);
11313 /* Handle VLDM instructions. */
11314 else if (op_vldm_vstm
== 0x09 || op_vldm_vstm
== 0x0b
11315 || op_vldm_vstm
== 0x13)
11317 uint32_t reg_count
, reg_vd
;
11318 uint32_t reg_index
= 0;
11319 uint32_t bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11321 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11322 reg_count
= bits (arm_insn_r
->arm_insn
, 0, 7);
11324 /* REG_VD is the first D register number. If the instruction
11325 loads memory to S registers (SINGLE_REG is TRUE), the register
11326 number is (REG_VD << 1 | bit D), so the corresponding D
11327 register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */
11329 reg_vd
= reg_vd
| (bit_d
<< 4);
11331 if (bit (arm_insn_r
->arm_insn
, 21) /* write back */)
11332 record_buf
[reg_index
++] = bits (arm_insn_r
->arm_insn
, 16, 19);
11334 /* If the instruction loads memory to D register, REG_COUNT should
11335 be divided by 2, according to the ARM Architecture Reference
11336 Manual. If the instruction loads memory to S register, divide by
11337 2 as well because two S registers are mapped to D register. */
11338 reg_count
= reg_count
/ 2;
11339 if (single_reg
&& bit_d
)
11341 /* Increase the register count if S register list starts from
11342 an odd number (bit d is one). */
11346 while (reg_count
> 0)
11348 record_buf
[reg_index
++] = ARM_D0_REGNUM
+ reg_vd
+ reg_count
- 1;
11351 arm_insn_r
->reg_rec_count
= reg_index
;
11353 /* VSTR Vector store register. */
11354 else if ((opcode
& 0x13) == 0x10)
11356 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
;
11357 uint32_t memory_index
= 0;
11359 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11360 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11361 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11362 imm_off32
= imm_off8
<< 2;
11364 if (bit (arm_insn_r
->arm_insn
, 23))
11365 start_address
= u_regval
+ imm_off32
;
11367 start_address
= u_regval
- imm_off32
;
11371 record_buf_mem
[memory_index
] = 4;
11372 record_buf_mem
[memory_index
+ 1] = start_address
;
11373 arm_insn_r
->mem_rec_count
= 1;
11377 record_buf_mem
[memory_index
] = 4;
11378 record_buf_mem
[memory_index
+ 1] = start_address
;
11379 record_buf_mem
[memory_index
+ 2] = 4;
11380 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11381 arm_insn_r
->mem_rec_count
= 2;
11384 /* VLDR Vector load register. */
11385 else if ((opcode
& 0x13) == 0x11)
11387 uint32_t reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11391 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
11392 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
;
11396 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
11397 /* Record register D rather than pseudo register S. */
11398 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
/ 2;
11400 arm_insn_r
->reg_rec_count
= 1;
11403 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11404 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11408 /* Record handler for arm/thumb mode VFP data processing instructions. */
11411 arm_record_vfp_data_proc_insn (insn_decode_record
*arm_insn_r
)
11413 uint32_t opc1
, opc2
, opc3
, dp_op_sz
, bit_d
, reg_vd
;
11414 uint32_t record_buf
[4];
11415 enum insn_types
{INSN_T0
, INSN_T1
, INSN_T2
, INSN_T3
, INSN_INV
};
11416 enum insn_types curr_insn_type
= INSN_INV
;
11418 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11419 opc1
= bits (arm_insn_r
->arm_insn
, 20, 23);
11420 opc2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11421 opc3
= bits (arm_insn_r
->arm_insn
, 6, 7);
11422 dp_op_sz
= bit (arm_insn_r
->arm_insn
, 8);
11423 bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11424 /* Mask off the "D" bit. */
11425 opc1
= opc1
& ~0x04;
11427 /* Handle VMLA, VMLS. */
11430 if (bit (arm_insn_r
->arm_insn
, 10))
11432 if (bit (arm_insn_r
->arm_insn
, 6))
11433 curr_insn_type
= INSN_T0
;
11435 curr_insn_type
= INSN_T1
;
11440 curr_insn_type
= INSN_T1
;
11442 curr_insn_type
= INSN_T2
;
11445 /* Handle VNMLA, VNMLS, VNMUL. */
11446 else if (opc1
== 0x01)
11449 curr_insn_type
= INSN_T1
;
11451 curr_insn_type
= INSN_T2
;
11454 else if (opc1
== 0x02 && !(opc3
& 0x01))
11456 if (bit (arm_insn_r
->arm_insn
, 10))
11458 if (bit (arm_insn_r
->arm_insn
, 6))
11459 curr_insn_type
= INSN_T0
;
11461 curr_insn_type
= INSN_T1
;
11466 curr_insn_type
= INSN_T1
;
11468 curr_insn_type
= INSN_T2
;
11471 /* Handle VADD, VSUB. */
11472 else if (opc1
== 0x03)
11474 if (!bit (arm_insn_r
->arm_insn
, 9))
11476 if (bit (arm_insn_r
->arm_insn
, 6))
11477 curr_insn_type
= INSN_T0
;
11479 curr_insn_type
= INSN_T1
;
11484 curr_insn_type
= INSN_T1
;
11486 curr_insn_type
= INSN_T2
;
11490 else if (opc1
== 0x08)
11493 curr_insn_type
= INSN_T1
;
11495 curr_insn_type
= INSN_T2
;
11497 /* Handle all other vfp data processing instructions. */
11498 else if (opc1
== 0x0b)
11501 if (!(opc3
& 0x01) || (opc2
== 0x00 && opc3
== 0x01))
11503 if (bit (arm_insn_r
->arm_insn
, 4))
11505 if (bit (arm_insn_r
->arm_insn
, 6))
11506 curr_insn_type
= INSN_T0
;
11508 curr_insn_type
= INSN_T1
;
11513 curr_insn_type
= INSN_T1
;
11515 curr_insn_type
= INSN_T2
;
11518 /* Handle VNEG and VABS. */
11519 else if ((opc2
== 0x01 && opc3
== 0x01)
11520 || (opc2
== 0x00 && opc3
== 0x03))
11522 if (!bit (arm_insn_r
->arm_insn
, 11))
11524 if (bit (arm_insn_r
->arm_insn
, 6))
11525 curr_insn_type
= INSN_T0
;
11527 curr_insn_type
= INSN_T1
;
11532 curr_insn_type
= INSN_T1
;
11534 curr_insn_type
= INSN_T2
;
11537 /* Handle VSQRT. */
11538 else if (opc2
== 0x01 && opc3
== 0x03)
11541 curr_insn_type
= INSN_T1
;
11543 curr_insn_type
= INSN_T2
;
11546 else if (opc2
== 0x07 && opc3
== 0x03)
11549 curr_insn_type
= INSN_T1
;
11551 curr_insn_type
= INSN_T2
;
11553 else if (opc3
& 0x01)
11556 if ((opc2
== 0x08) || (opc2
& 0x0e) == 0x0c)
11558 if (!bit (arm_insn_r
->arm_insn
, 18))
11559 curr_insn_type
= INSN_T2
;
11563 curr_insn_type
= INSN_T1
;
11565 curr_insn_type
= INSN_T2
;
11569 else if ((opc2
& 0x0e) == 0x0a || (opc2
& 0x0e) == 0x0e)
11572 curr_insn_type
= INSN_T1
;
11574 curr_insn_type
= INSN_T2
;
11576 /* Handle VCVTB, VCVTT. */
11577 else if ((opc2
& 0x0e) == 0x02)
11578 curr_insn_type
= INSN_T2
;
11579 /* Handle VCMP, VCMPE. */
11580 else if ((opc2
& 0x0e) == 0x04)
11581 curr_insn_type
= INSN_T3
;
11585 switch (curr_insn_type
)
11588 reg_vd
= reg_vd
| (bit_d
<< 4);
11589 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11590 record_buf
[1] = reg_vd
+ ARM_D0_REGNUM
+ 1;
11591 arm_insn_r
->reg_rec_count
= 2;
11595 reg_vd
= reg_vd
| (bit_d
<< 4);
11596 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11597 arm_insn_r
->reg_rec_count
= 1;
11601 reg_vd
= (reg_vd
<< 1) | bit_d
;
11602 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11603 arm_insn_r
->reg_rec_count
= 1;
11607 record_buf
[0] = ARM_FPSCR_REGNUM
;
11608 arm_insn_r
->reg_rec_count
= 1;
11612 gdb_assert_not_reached ("no decoding pattern found");
11616 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11620 /* Handling opcode 110 insns. */
11623 arm_record_asimd_vfp_coproc (insn_decode_record
*arm_insn_r
)
11625 uint32_t op1
, op1_ebit
, coproc
;
11627 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11628 op1
= bits (arm_insn_r
->arm_insn
, 20, 25);
11629 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11631 if ((coproc
& 0x0e) == 0x0a)
11633 /* Handle extension register ld/st instructions. */
11635 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11637 /* 64-bit transfers between arm core and extension registers. */
11638 if ((op1
& 0x3e) == 0x04)
11639 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11643 /* Handle coprocessor ld/st instructions. */
11648 return arm_record_unsupported_insn (arm_insn_r
);
11651 return arm_record_unsupported_insn (arm_insn_r
);
11654 /* Move to coprocessor from two arm core registers. */
11656 return arm_record_unsupported_insn (arm_insn_r
);
11658 /* Move to two arm core registers from coprocessor. */
11663 reg_t
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11664 reg_t
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11665 arm_insn_r
->reg_rec_count
= 2;
11667 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, reg_t
);
11671 return arm_record_unsupported_insn (arm_insn_r
);
11674 /* Handling opcode 111 insns. */
11677 arm_record_coproc_data_proc (insn_decode_record
*arm_insn_r
)
11679 uint32_t op
, op1_ebit
, coproc
, bits_24_25
;
11680 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arm_insn_r
->gdbarch
);
11681 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11683 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 24, 27);
11684 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11685 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11686 op
= bit (arm_insn_r
->arm_insn
, 4);
11687 bits_24_25
= bits (arm_insn_r
->arm_insn
, 24, 25);
11689 /* Handle arm SWI/SVC system call instructions. */
11690 if (bits_24_25
== 0x3)
11692 if (tdep
->arm_syscall_record
!= NULL
)
11694 ULONGEST svc_operand
, svc_number
;
11696 svc_operand
= (0x00ffffff & arm_insn_r
->arm_insn
);
11698 if (svc_operand
) /* OABI. */
11699 svc_number
= svc_operand
- 0x900000;
11701 regcache_raw_read_unsigned (reg_cache
, 7, &svc_number
);
11703 return tdep
->arm_syscall_record (reg_cache
, svc_number
);
11707 printf_unfiltered (_("no syscall record support\n"));
11711 else if (bits_24_25
== 0x02)
11715 if ((coproc
& 0x0e) == 0x0a)
11717 /* 8, 16, and 32-bit transfer */
11718 return arm_record_vdata_transfer_insn (arm_insn_r
);
11725 uint32_t record_buf
[1];
11727 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11728 if (record_buf
[0] == 15)
11729 record_buf
[0] = ARM_PS_REGNUM
;
11731 arm_insn_r
->reg_rec_count
= 1;
11732 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
,
11745 if ((coproc
& 0x0e) == 0x0a)
11747 /* VFP data-processing instructions. */
11748 return arm_record_vfp_data_proc_insn (arm_insn_r
);
11759 unsigned int op1
= bits (arm_insn_r
->arm_insn
, 20, 25);
11763 if ((coproc
& 0x0e) != 0x0a)
11769 else if (op1
== 4 || op1
== 5)
11771 if ((coproc
& 0x0e) == 0x0a)
11773 /* 64-bit transfers between ARM core and extension */
11782 else if (op1
== 0 || op1
== 1)
11789 if ((coproc
& 0x0e) == 0x0a)
11791 /* Extension register load/store */
11795 /* STC, STC2, LDC, LDC2 */
11804 /* Handling opcode 000 insns. */
11807 thumb_record_shift_add_sub (insn_decode_record
*thumb_insn_r
)
11809 uint32_t record_buf
[8];
11810 uint32_t reg_src1
= 0;
11812 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11814 record_buf
[0] = ARM_PS_REGNUM
;
11815 record_buf
[1] = reg_src1
;
11816 thumb_insn_r
->reg_rec_count
= 2;
11818 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11824 /* Handling opcode 001 insns. */
11827 thumb_record_add_sub_cmp_mov (insn_decode_record
*thumb_insn_r
)
11829 uint32_t record_buf
[8];
11830 uint32_t reg_src1
= 0;
11832 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11834 record_buf
[0] = ARM_PS_REGNUM
;
11835 record_buf
[1] = reg_src1
;
11836 thumb_insn_r
->reg_rec_count
= 2;
11838 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11843 /* Handling opcode 010 insns. */
11846 thumb_record_ld_st_reg_offset (insn_decode_record
*thumb_insn_r
)
11848 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11849 uint32_t record_buf
[8], record_buf_mem
[8];
11851 uint32_t reg_src1
= 0, reg_src2
= 0;
11852 uint32_t opcode1
= 0, opcode2
= 0, opcode3
= 0;
11854 ULONGEST u_regval
[2] = {0};
11856 opcode1
= bits (thumb_insn_r
->arm_insn
, 10, 12);
11858 if (bit (thumb_insn_r
->arm_insn
, 12))
11860 /* Handle load/store register offset. */
11861 uint32_t opB
= bits (thumb_insn_r
->arm_insn
, 9, 11);
11863 if (in_inclusive_range (opB
, 4U, 7U))
11865 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
11866 reg_src1
= bits (thumb_insn_r
->arm_insn
,0, 2);
11867 record_buf
[0] = reg_src1
;
11868 thumb_insn_r
->reg_rec_count
= 1;
11870 else if (in_inclusive_range (opB
, 0U, 2U))
11872 /* STR(2), STRB(2), STRH(2) . */
11873 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11874 reg_src2
= bits (thumb_insn_r
->arm_insn
, 6, 8);
11875 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11876 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11878 record_buf_mem
[0] = 4; /* STR (2). */
11880 record_buf_mem
[0] = 1; /* STRB (2). */
11882 record_buf_mem
[0] = 2; /* STRH (2). */
11883 record_buf_mem
[1] = u_regval
[0] + u_regval
[1];
11884 thumb_insn_r
->mem_rec_count
= 1;
11887 else if (bit (thumb_insn_r
->arm_insn
, 11))
11889 /* Handle load from literal pool. */
11891 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11892 record_buf
[0] = reg_src1
;
11893 thumb_insn_r
->reg_rec_count
= 1;
11897 /* Special data instructions and branch and exchange */
11898 opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 9);
11899 opcode3
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11900 if ((3 == opcode2
) && (!opcode3
))
11902 /* Branch with exchange. */
11903 record_buf
[0] = ARM_PS_REGNUM
;
11904 thumb_insn_r
->reg_rec_count
= 1;
11908 /* Format 8; special data processing insns. */
11909 record_buf
[0] = ARM_PS_REGNUM
;
11910 record_buf
[1] = (bit (thumb_insn_r
->arm_insn
, 7) << 3
11911 | bits (thumb_insn_r
->arm_insn
, 0, 2));
11912 thumb_insn_r
->reg_rec_count
= 2;
11917 /* Format 5; data processing insns. */
11918 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11919 if (bit (thumb_insn_r
->arm_insn
, 7))
11921 reg_src1
= reg_src1
+ 8;
11923 record_buf
[0] = ARM_PS_REGNUM
;
11924 record_buf
[1] = reg_src1
;
11925 thumb_insn_r
->reg_rec_count
= 2;
11928 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11929 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11935 /* Handling opcode 001 insns. */
11938 thumb_record_ld_st_imm_offset (insn_decode_record
*thumb_insn_r
)
11940 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11941 uint32_t record_buf
[8], record_buf_mem
[8];
11943 uint32_t reg_src1
= 0;
11944 uint32_t opcode
= 0, immed_5
= 0;
11946 ULONGEST u_regval
= 0;
11948 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11953 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11954 record_buf
[0] = reg_src1
;
11955 thumb_insn_r
->reg_rec_count
= 1;
11960 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11961 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11962 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11963 record_buf_mem
[0] = 4;
11964 record_buf_mem
[1] = u_regval
+ (immed_5
* 4);
11965 thumb_insn_r
->mem_rec_count
= 1;
11968 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11969 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11975 /* Handling opcode 100 insns. */
11978 thumb_record_ld_st_stack (insn_decode_record
*thumb_insn_r
)
11980 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11981 uint32_t record_buf
[8], record_buf_mem
[8];
11983 uint32_t reg_src1
= 0;
11984 uint32_t opcode
= 0, immed_8
= 0, immed_5
= 0;
11986 ULONGEST u_regval
= 0;
11988 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11993 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11994 record_buf
[0] = reg_src1
;
11995 thumb_insn_r
->reg_rec_count
= 1;
11997 else if (1 == opcode
)
12000 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12001 record_buf
[0] = reg_src1
;
12002 thumb_insn_r
->reg_rec_count
= 1;
12004 else if (2 == opcode
)
12007 immed_8
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12008 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
12009 record_buf_mem
[0] = 4;
12010 record_buf_mem
[1] = u_regval
+ (immed_8
* 4);
12011 thumb_insn_r
->mem_rec_count
= 1;
12013 else if (0 == opcode
)
12016 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
12017 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12018 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12019 record_buf_mem
[0] = 2;
12020 record_buf_mem
[1] = u_regval
+ (immed_5
* 2);
12021 thumb_insn_r
->mem_rec_count
= 1;
12024 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12025 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12031 /* Handling opcode 101 insns. */
12034 thumb_record_misc (insn_decode_record
*thumb_insn_r
)
12036 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12038 uint32_t opcode
= 0;
12039 uint32_t register_bits
= 0, register_count
= 0;
12040 uint32_t index
= 0, start_address
= 0;
12041 uint32_t record_buf
[24], record_buf_mem
[48];
12044 ULONGEST u_regval
= 0;
12046 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12048 if (opcode
== 0 || opcode
== 1)
12050 /* ADR and ADD (SP plus immediate) */
12052 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12053 record_buf
[0] = reg_src1
;
12054 thumb_insn_r
->reg_rec_count
= 1;
12058 /* Miscellaneous 16-bit instructions */
12059 uint32_t opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 11);
12064 /* SETEND and CPS */
12067 /* ADD/SUB (SP plus immediate) */
12068 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12069 record_buf
[0] = ARM_SP_REGNUM
;
12070 thumb_insn_r
->reg_rec_count
= 1;
12072 case 1: /* fall through */
12073 case 3: /* fall through */
12074 case 9: /* fall through */
12079 /* SXTH, SXTB, UXTH, UXTB */
12080 record_buf
[0] = bits (thumb_insn_r
->arm_insn
, 0, 2);
12081 thumb_insn_r
->reg_rec_count
= 1;
12083 case 4: /* fall through */
12086 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12087 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
12088 while (register_bits
)
12090 if (register_bits
& 0x00000001)
12092 register_bits
= register_bits
>> 1;
12094 start_address
= u_regval
- \
12095 (4 * (bit (thumb_insn_r
->arm_insn
, 8) + register_count
));
12096 thumb_insn_r
->mem_rec_count
= register_count
;
12097 while (register_count
)
12099 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12100 record_buf_mem
[(register_count
* 2) - 2] = 4;
12101 start_address
= start_address
+ 4;
12104 record_buf
[0] = ARM_SP_REGNUM
;
12105 thumb_insn_r
->reg_rec_count
= 1;
12108 /* REV, REV16, REVSH */
12109 record_buf
[0] = bits (thumb_insn_r
->arm_insn
, 0, 2);
12110 thumb_insn_r
->reg_rec_count
= 1;
12112 case 12: /* fall through */
12115 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12116 while (register_bits
)
12118 if (register_bits
& 0x00000001)
12119 record_buf
[index
++] = register_count
;
12120 register_bits
= register_bits
>> 1;
12123 record_buf
[index
++] = ARM_PS_REGNUM
;
12124 record_buf
[index
++] = ARM_SP_REGNUM
;
12125 thumb_insn_r
->reg_rec_count
= index
;
12129 /* Handle enhanced software breakpoint insn, BKPT. */
12130 /* CPSR is changed to be executed in ARM state, disabling normal
12131 interrupts, entering abort mode. */
12132 /* According to high vector configuration PC is set. */
12133 /* User hits breakpoint and type reverse, in that case, we need to go back with
12134 previous CPSR and Program Counter. */
12135 record_buf
[0] = ARM_PS_REGNUM
;
12136 record_buf
[1] = ARM_LR_REGNUM
;
12137 thumb_insn_r
->reg_rec_count
= 2;
12138 /* We need to save SPSR value, which is not yet done. */
12139 printf_unfiltered (_("Process record does not support instruction "
12140 "0x%0x at address %s.\n"),
12141 thumb_insn_r
->arm_insn
,
12142 paddress (thumb_insn_r
->gdbarch
,
12143 thumb_insn_r
->this_addr
));
12147 /* If-Then, and hints */
12154 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12155 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12161 /* Handling opcode 110 insns. */
12164 thumb_record_ldm_stm_swi (insn_decode_record
*thumb_insn_r
)
12166 struct gdbarch_tdep
*tdep
= gdbarch_tdep (thumb_insn_r
->gdbarch
);
12167 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12169 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
12170 uint32_t reg_src1
= 0;
12171 uint32_t opcode1
= 0, opcode2
= 0, register_bits
= 0, register_count
= 0;
12172 uint32_t index
= 0, start_address
= 0;
12173 uint32_t record_buf
[24], record_buf_mem
[48];
12175 ULONGEST u_regval
= 0;
12177 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12178 opcode2
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12184 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12186 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12187 while (register_bits
)
12189 if (register_bits
& 0x00000001)
12190 record_buf
[index
++] = register_count
;
12191 register_bits
= register_bits
>> 1;
12194 record_buf
[index
++] = reg_src1
;
12195 thumb_insn_r
->reg_rec_count
= index
;
12197 else if (0 == opcode2
)
12199 /* It handles both STMIA. */
12200 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12202 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12203 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12204 while (register_bits
)
12206 if (register_bits
& 0x00000001)
12208 register_bits
= register_bits
>> 1;
12210 start_address
= u_regval
;
12211 thumb_insn_r
->mem_rec_count
= register_count
;
12212 while (register_count
)
12214 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12215 record_buf_mem
[(register_count
* 2) - 2] = 4;
12216 start_address
= start_address
+ 4;
12220 else if (0x1F == opcode1
)
12222 /* Handle arm syscall insn. */
12223 if (tdep
->arm_syscall_record
!= NULL
)
12225 regcache_raw_read_unsigned (reg_cache
, 7, &u_regval
);
12226 ret
= tdep
->arm_syscall_record (reg_cache
, u_regval
);
12230 printf_unfiltered (_("no syscall record support\n"));
12235 /* B (1), conditional branch is automatically taken care in process_record,
12236 as PC is saved there. */
12238 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12239 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12245 /* Handling opcode 111 insns. */
12248 thumb_record_branch (insn_decode_record
*thumb_insn_r
)
12250 uint32_t record_buf
[8];
12251 uint32_t bits_h
= 0;
12253 bits_h
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12255 if (2 == bits_h
|| 3 == bits_h
)
12258 record_buf
[0] = ARM_LR_REGNUM
;
12259 thumb_insn_r
->reg_rec_count
= 1;
12261 else if (1 == bits_h
)
12264 record_buf
[0] = ARM_PS_REGNUM
;
12265 record_buf
[1] = ARM_LR_REGNUM
;
12266 thumb_insn_r
->reg_rec_count
= 2;
12269 /* B(2) is automatically taken care in process_record, as PC is
12272 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12277 /* Handler for thumb2 load/store multiple instructions. */
12280 thumb2_record_ld_st_multiple (insn_decode_record
*thumb2_insn_r
)
12282 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12284 uint32_t reg_rn
, op
;
12285 uint32_t register_bits
= 0, register_count
= 0;
12286 uint32_t index
= 0, start_address
= 0;
12287 uint32_t record_buf
[24], record_buf_mem
[48];
12289 ULONGEST u_regval
= 0;
12291 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12292 op
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12294 if (0 == op
|| 3 == op
)
12296 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12298 /* Handle RFE instruction. */
12299 record_buf
[0] = ARM_PS_REGNUM
;
12300 thumb2_insn_r
->reg_rec_count
= 1;
12304 /* Handle SRS instruction after reading banked SP. */
12305 return arm_record_unsupported_insn (thumb2_insn_r
);
12308 else if (1 == op
|| 2 == op
)
12310 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12312 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
12313 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12314 while (register_bits
)
12316 if (register_bits
& 0x00000001)
12317 record_buf
[index
++] = register_count
;
12320 register_bits
= register_bits
>> 1;
12322 record_buf
[index
++] = reg_rn
;
12323 record_buf
[index
++] = ARM_PS_REGNUM
;
12324 thumb2_insn_r
->reg_rec_count
= index
;
12328 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
12329 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12330 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12331 while (register_bits
)
12333 if (register_bits
& 0x00000001)
12336 register_bits
= register_bits
>> 1;
12341 /* Start address calculation for LDMDB/LDMEA. */
12342 start_address
= u_regval
;
12346 /* Start address calculation for LDMDB/LDMEA. */
12347 start_address
= u_regval
- register_count
* 4;
12350 thumb2_insn_r
->mem_rec_count
= register_count
;
12351 while (register_count
)
12353 record_buf_mem
[register_count
* 2 - 1] = start_address
;
12354 record_buf_mem
[register_count
* 2 - 2] = 4;
12355 start_address
= start_address
+ 4;
12358 record_buf
[0] = reg_rn
;
12359 record_buf
[1] = ARM_PS_REGNUM
;
12360 thumb2_insn_r
->reg_rec_count
= 2;
12364 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12366 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12368 return ARM_RECORD_SUCCESS
;
12371 /* Handler for thumb2 load/store (dual/exclusive) and table branch
12375 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record
*thumb2_insn_r
)
12377 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12379 uint32_t reg_rd
, reg_rn
, offset_imm
;
12380 uint32_t reg_dest1
, reg_dest2
;
12381 uint32_t address
, offset_addr
;
12382 uint32_t record_buf
[8], record_buf_mem
[8];
12383 uint32_t op1
, op2
, op3
;
12385 ULONGEST u_regval
[2];
12387 op1
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12388 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 21);
12389 op3
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12391 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12393 if(!(1 == op1
&& 1 == op2
&& (0 == op3
|| 1 == op3
)))
12395 reg_dest1
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12396 record_buf
[0] = reg_dest1
;
12397 record_buf
[1] = ARM_PS_REGNUM
;
12398 thumb2_insn_r
->reg_rec_count
= 2;
12401 if (3 == op2
|| (op1
& 2) || (1 == op1
&& 1 == op2
&& 7 == op3
))
12403 reg_dest2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12404 record_buf
[2] = reg_dest2
;
12405 thumb2_insn_r
->reg_rec_count
= 3;
12410 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12411 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12413 if (0 == op1
&& 0 == op2
)
12415 /* Handle STREX. */
12416 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12417 address
= u_regval
[0] + (offset_imm
* 4);
12418 record_buf_mem
[0] = 4;
12419 record_buf_mem
[1] = address
;
12420 thumb2_insn_r
->mem_rec_count
= 1;
12421 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12422 record_buf
[0] = reg_rd
;
12423 thumb2_insn_r
->reg_rec_count
= 1;
12425 else if (1 == op1
&& 0 == op2
)
12427 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12428 record_buf
[0] = reg_rd
;
12429 thumb2_insn_r
->reg_rec_count
= 1;
12430 address
= u_regval
[0];
12431 record_buf_mem
[1] = address
;
12435 /* Handle STREXB. */
12436 record_buf_mem
[0] = 1;
12437 thumb2_insn_r
->mem_rec_count
= 1;
12441 /* Handle STREXH. */
12442 record_buf_mem
[0] = 2 ;
12443 thumb2_insn_r
->mem_rec_count
= 1;
12447 /* Handle STREXD. */
12448 address
= u_regval
[0];
12449 record_buf_mem
[0] = 4;
12450 record_buf_mem
[2] = 4;
12451 record_buf_mem
[3] = address
+ 4;
12452 thumb2_insn_r
->mem_rec_count
= 2;
12457 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12459 if (bit (thumb2_insn_r
->arm_insn
, 24))
12461 if (bit (thumb2_insn_r
->arm_insn
, 23))
12462 offset_addr
= u_regval
[0] + (offset_imm
* 4);
12464 offset_addr
= u_regval
[0] - (offset_imm
* 4);
12466 address
= offset_addr
;
12469 address
= u_regval
[0];
12471 record_buf_mem
[0] = 4;
12472 record_buf_mem
[1] = address
;
12473 record_buf_mem
[2] = 4;
12474 record_buf_mem
[3] = address
+ 4;
12475 thumb2_insn_r
->mem_rec_count
= 2;
12476 record_buf
[0] = reg_rn
;
12477 thumb2_insn_r
->reg_rec_count
= 1;
12481 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12483 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12485 return ARM_RECORD_SUCCESS
;
12488 /* Handler for thumb2 data processing (shift register and modified immediate)
12492 thumb2_record_data_proc_sreg_mimm (insn_decode_record
*thumb2_insn_r
)
12494 uint32_t reg_rd
, op
;
12495 uint32_t record_buf
[8];
12497 op
= bits (thumb2_insn_r
->arm_insn
, 21, 24);
12498 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12500 if ((0 == op
|| 4 == op
|| 8 == op
|| 13 == op
) && 15 == reg_rd
)
12502 record_buf
[0] = ARM_PS_REGNUM
;
12503 thumb2_insn_r
->reg_rec_count
= 1;
12507 record_buf
[0] = reg_rd
;
12508 record_buf
[1] = ARM_PS_REGNUM
;
12509 thumb2_insn_r
->reg_rec_count
= 2;
12512 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12514 return ARM_RECORD_SUCCESS
;
12517 /* Generic handler for thumb2 instructions which effect destination and PS
12521 thumb2_record_ps_dest_generic (insn_decode_record
*thumb2_insn_r
)
12524 uint32_t record_buf
[8];
12526 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12528 record_buf
[0] = reg_rd
;
12529 record_buf
[1] = ARM_PS_REGNUM
;
12530 thumb2_insn_r
->reg_rec_count
= 2;
12532 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12534 return ARM_RECORD_SUCCESS
;
12537 /* Handler for thumb2 branch and miscellaneous control instructions. */
12540 thumb2_record_branch_misc_cntrl (insn_decode_record
*thumb2_insn_r
)
12542 uint32_t op
, op1
, op2
;
12543 uint32_t record_buf
[8];
12545 op
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12546 op1
= bits (thumb2_insn_r
->arm_insn
, 12, 14);
12547 op2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12549 /* Handle MSR insn. */
12550 if (!(op1
& 0x2) && 0x38 == op
)
12554 /* CPSR is going to be changed. */
12555 record_buf
[0] = ARM_PS_REGNUM
;
12556 thumb2_insn_r
->reg_rec_count
= 1;
12560 arm_record_unsupported_insn(thumb2_insn_r
);
12564 else if (4 == (op1
& 0x5) || 5 == (op1
& 0x5))
12567 record_buf
[0] = ARM_PS_REGNUM
;
12568 record_buf
[1] = ARM_LR_REGNUM
;
12569 thumb2_insn_r
->reg_rec_count
= 2;
12572 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12574 return ARM_RECORD_SUCCESS
;
12577 /* Handler for thumb2 store single data item instructions. */
12580 thumb2_record_str_single_data (insn_decode_record
*thumb2_insn_r
)
12582 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12584 uint32_t reg_rn
, reg_rm
, offset_imm
, shift_imm
;
12585 uint32_t address
, offset_addr
;
12586 uint32_t record_buf
[8], record_buf_mem
[8];
12589 ULONGEST u_regval
[2];
12591 op1
= bits (thumb2_insn_r
->arm_insn
, 21, 23);
12592 op2
= bits (thumb2_insn_r
->arm_insn
, 6, 11);
12593 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12594 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12596 if (bit (thumb2_insn_r
->arm_insn
, 23))
12599 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 11);
12600 offset_addr
= u_regval
[0] + offset_imm
;
12601 address
= offset_addr
;
12606 if ((0 == op1
|| 1 == op1
|| 2 == op1
) && !(op2
& 0x20))
12608 /* Handle STRB (register). */
12609 reg_rm
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12610 regcache_raw_read_unsigned (reg_cache
, reg_rm
, &u_regval
[1]);
12611 shift_imm
= bits (thumb2_insn_r
->arm_insn
, 4, 5);
12612 offset_addr
= u_regval
[1] << shift_imm
;
12613 address
= u_regval
[0] + offset_addr
;
12617 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12618 if (bit (thumb2_insn_r
->arm_insn
, 10))
12620 if (bit (thumb2_insn_r
->arm_insn
, 9))
12621 offset_addr
= u_regval
[0] + offset_imm
;
12623 offset_addr
= u_regval
[0] - offset_imm
;
12625 address
= offset_addr
;
12628 address
= u_regval
[0];
12634 /* Store byte instructions. */
12637 record_buf_mem
[0] = 1;
12639 /* Store half word instructions. */
12642 record_buf_mem
[0] = 2;
12644 /* Store word instructions. */
12647 record_buf_mem
[0] = 4;
12651 gdb_assert_not_reached ("no decoding pattern found");
12655 record_buf_mem
[1] = address
;
12656 thumb2_insn_r
->mem_rec_count
= 1;
12657 record_buf
[0] = reg_rn
;
12658 thumb2_insn_r
->reg_rec_count
= 1;
12660 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12662 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12664 return ARM_RECORD_SUCCESS
;
12667 /* Handler for thumb2 load memory hints instructions. */
12670 thumb2_record_ld_mem_hints (insn_decode_record
*thumb2_insn_r
)
12672 uint32_t record_buf
[8];
12673 uint32_t reg_rt
, reg_rn
;
12675 reg_rt
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12676 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12678 if (ARM_PC_REGNUM
!= reg_rt
)
12680 record_buf
[0] = reg_rt
;
12681 record_buf
[1] = reg_rn
;
12682 record_buf
[2] = ARM_PS_REGNUM
;
12683 thumb2_insn_r
->reg_rec_count
= 3;
12685 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12687 return ARM_RECORD_SUCCESS
;
12690 return ARM_RECORD_FAILURE
;
12693 /* Handler for thumb2 load word instructions. */
12696 thumb2_record_ld_word (insn_decode_record
*thumb2_insn_r
)
12698 uint32_t record_buf
[8];
12700 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12701 record_buf
[1] = ARM_PS_REGNUM
;
12702 thumb2_insn_r
->reg_rec_count
= 2;
12704 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12706 return ARM_RECORD_SUCCESS
;
12709 /* Handler for thumb2 long multiply, long multiply accumulate, and
12710 divide instructions. */
12713 thumb2_record_lmul_lmla_div (insn_decode_record
*thumb2_insn_r
)
12715 uint32_t opcode1
= 0, opcode2
= 0;
12716 uint32_t record_buf
[8];
12718 opcode1
= bits (thumb2_insn_r
->arm_insn
, 20, 22);
12719 opcode2
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12721 if (0 == opcode1
|| 2 == opcode1
|| (opcode1
>= 4 && opcode1
<= 6))
12723 /* Handle SMULL, UMULL, SMULAL. */
12724 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
12725 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12726 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12727 record_buf
[2] = ARM_PS_REGNUM
;
12728 thumb2_insn_r
->reg_rec_count
= 3;
12730 else if (1 == opcode1
|| 3 == opcode2
)
12732 /* Handle SDIV and UDIV. */
12733 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12734 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12735 record_buf
[2] = ARM_PS_REGNUM
;
12736 thumb2_insn_r
->reg_rec_count
= 3;
12739 return ARM_RECORD_FAILURE
;
12741 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12743 return ARM_RECORD_SUCCESS
;
12746 /* Record handler for thumb32 coprocessor instructions. */
12749 thumb2_record_coproc_insn (insn_decode_record
*thumb2_insn_r
)
12751 if (bit (thumb2_insn_r
->arm_insn
, 25))
12752 return arm_record_coproc_data_proc (thumb2_insn_r
);
12754 return arm_record_asimd_vfp_coproc (thumb2_insn_r
);
12757 /* Record handler for advance SIMD structure load/store instructions. */
12760 thumb2_record_asimd_struct_ld_st (insn_decode_record
*thumb2_insn_r
)
12762 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12763 uint32_t l_bit
, a_bit
, b_bits
;
12764 uint32_t record_buf
[128], record_buf_mem
[128];
12765 uint32_t reg_rn
, reg_vd
, address
, f_elem
;
12766 uint32_t index_r
= 0, index_e
= 0, bf_regs
= 0, index_m
= 0, loop_t
= 0;
12769 l_bit
= bit (thumb2_insn_r
->arm_insn
, 21);
12770 a_bit
= bit (thumb2_insn_r
->arm_insn
, 23);
12771 b_bits
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12772 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12773 reg_vd
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12774 reg_vd
= (bit (thumb2_insn_r
->arm_insn
, 22) << 4) | reg_vd
;
12775 f_ebytes
= (1 << bits (thumb2_insn_r
->arm_insn
, 6, 7));
12776 f_elem
= 8 / f_ebytes
;
12780 ULONGEST u_regval
= 0;
12781 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12782 address
= u_regval
;
12787 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12789 if (b_bits
== 0x07)
12791 else if (b_bits
== 0x0a)
12793 else if (b_bits
== 0x06)
12795 else if (b_bits
== 0x02)
12800 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12802 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12804 record_buf_mem
[index_m
++] = f_ebytes
;
12805 record_buf_mem
[index_m
++] = address
;
12806 address
= address
+ f_ebytes
;
12807 thumb2_insn_r
->mem_rec_count
+= 1;
12812 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12814 if (b_bits
== 0x09 || b_bits
== 0x08)
12816 else if (b_bits
== 0x03)
12821 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12822 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12824 for (loop_t
= 0; loop_t
< 2; loop_t
++)
12826 record_buf_mem
[index_m
++] = f_ebytes
;
12827 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12828 thumb2_insn_r
->mem_rec_count
+= 1;
12830 address
= address
+ (2 * f_ebytes
);
12834 else if ((b_bits
& 0x0e) == 0x04)
12836 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12838 for (loop_t
= 0; loop_t
< 3; loop_t
++)
12840 record_buf_mem
[index_m
++] = f_ebytes
;
12841 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12842 thumb2_insn_r
->mem_rec_count
+= 1;
12844 address
= address
+ (3 * f_ebytes
);
12848 else if (!(b_bits
& 0x0e))
12850 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12852 for (loop_t
= 0; loop_t
< 4; loop_t
++)
12854 record_buf_mem
[index_m
++] = f_ebytes
;
12855 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12856 thumb2_insn_r
->mem_rec_count
+= 1;
12858 address
= address
+ (4 * f_ebytes
);
12864 uint8_t bft_size
= bits (thumb2_insn_r
->arm_insn
, 10, 11);
12866 if (bft_size
== 0x00)
12868 else if (bft_size
== 0x01)
12870 else if (bft_size
== 0x02)
12876 if (!(b_bits
& 0x0b) || b_bits
== 0x08)
12877 thumb2_insn_r
->mem_rec_count
= 1;
12879 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09)
12880 thumb2_insn_r
->mem_rec_count
= 2;
12882 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a)
12883 thumb2_insn_r
->mem_rec_count
= 3;
12885 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b)
12886 thumb2_insn_r
->mem_rec_count
= 4;
12888 for (index_m
= 0; index_m
< thumb2_insn_r
->mem_rec_count
; index_m
++)
12890 record_buf_mem
[index_m
] = f_ebytes
;
12891 record_buf_mem
[index_m
] = address
+ (index_m
* f_ebytes
);
12900 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12901 thumb2_insn_r
->reg_rec_count
= 1;
12903 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12904 thumb2_insn_r
->reg_rec_count
= 2;
12906 else if ((b_bits
& 0x0e) == 0x04)
12907 thumb2_insn_r
->reg_rec_count
= 3;
12909 else if (!(b_bits
& 0x0e))
12910 thumb2_insn_r
->reg_rec_count
= 4;
12915 if (!(b_bits
& 0x0b) || b_bits
== 0x08 || b_bits
== 0x0c)
12916 thumb2_insn_r
->reg_rec_count
= 1;
12918 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09 || b_bits
== 0x0d)
12919 thumb2_insn_r
->reg_rec_count
= 2;
12921 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a || b_bits
== 0x0e)
12922 thumb2_insn_r
->reg_rec_count
= 3;
12924 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b || b_bits
== 0x0f)
12925 thumb2_insn_r
->reg_rec_count
= 4;
12927 for (index_r
= 0; index_r
< thumb2_insn_r
->reg_rec_count
; index_r
++)
12928 record_buf
[index_r
] = reg_vd
+ ARM_D0_REGNUM
+ index_r
;
12932 if (bits (thumb2_insn_r
->arm_insn
, 0, 3) != 15)
12934 record_buf
[index_r
] = reg_rn
;
12935 thumb2_insn_r
->reg_rec_count
+= 1;
12938 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12940 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12945 /* Decodes thumb2 instruction type and invokes its record handler. */
12947 static unsigned int
12948 thumb2_record_decode_insn_handler (insn_decode_record
*thumb2_insn_r
)
12950 uint32_t op
, op1
, op2
;
12952 op
= bit (thumb2_insn_r
->arm_insn
, 15);
12953 op1
= bits (thumb2_insn_r
->arm_insn
, 27, 28);
12954 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12958 if (!(op2
& 0x64 ))
12960 /* Load/store multiple instruction. */
12961 return thumb2_record_ld_st_multiple (thumb2_insn_r
);
12963 else if ((op2
& 0x64) == 0x4)
12965 /* Load/store (dual/exclusive) and table branch instruction. */
12966 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r
);
12968 else if ((op2
& 0x60) == 0x20)
12970 /* Data-processing (shifted register). */
12971 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12973 else if (op2
& 0x40)
12975 /* Co-processor instructions. */
12976 return thumb2_record_coproc_insn (thumb2_insn_r
);
12979 else if (op1
== 0x02)
12983 /* Branches and miscellaneous control instructions. */
12984 return thumb2_record_branch_misc_cntrl (thumb2_insn_r
);
12986 else if (op2
& 0x20)
12988 /* Data-processing (plain binary immediate) instruction. */
12989 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12993 /* Data-processing (modified immediate). */
12994 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12997 else if (op1
== 0x03)
12999 if (!(op2
& 0x71 ))
13001 /* Store single data item. */
13002 return thumb2_record_str_single_data (thumb2_insn_r
);
13004 else if (!((op2
& 0x71) ^ 0x10))
13006 /* Advanced SIMD or structure load/store instructions. */
13007 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r
);
13009 else if (!((op2
& 0x67) ^ 0x01))
13011 /* Load byte, memory hints instruction. */
13012 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
13014 else if (!((op2
& 0x67) ^ 0x03))
13016 /* Load halfword, memory hints instruction. */
13017 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
13019 else if (!((op2
& 0x67) ^ 0x05))
13021 /* Load word instruction. */
13022 return thumb2_record_ld_word (thumb2_insn_r
);
13024 else if (!((op2
& 0x70) ^ 0x20))
13026 /* Data-processing (register) instruction. */
13027 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
13029 else if (!((op2
& 0x78) ^ 0x30))
13031 /* Multiply, multiply accumulate, abs diff instruction. */
13032 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
13034 else if (!((op2
& 0x78) ^ 0x38))
13036 /* Long multiply, long multiply accumulate, and divide. */
13037 return thumb2_record_lmul_lmla_div (thumb2_insn_r
);
13039 else if (op2
& 0x40)
13041 /* Co-processor instructions. */
13042 return thumb2_record_coproc_insn (thumb2_insn_r
);
13050 /* Abstract memory reader. */
13052 class abstract_memory_reader
13055 /* Read LEN bytes of target memory at address MEMADDR, placing the
13056 results in GDB's memory at BUF. Return true on success. */
13058 virtual bool read (CORE_ADDR memaddr
, gdb_byte
*buf
, const size_t len
) = 0;
13061 /* Instruction reader from real target. */
13063 class instruction_reader
: public abstract_memory_reader
13066 bool read (CORE_ADDR memaddr
, gdb_byte
*buf
, const size_t len
) override
13068 if (target_read_memory (memaddr
, buf
, len
))
13077 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
13078 and positive val on fauilure. */
13081 extract_arm_insn (abstract_memory_reader
& reader
,
13082 insn_decode_record
*insn_record
, uint32_t insn_size
)
13084 gdb_byte buf
[insn_size
];
13086 memset (&buf
[0], 0, insn_size
);
13088 if (!reader
.read (insn_record
->this_addr
, buf
, insn_size
))
13090 insn_record
->arm_insn
= (uint32_t) extract_unsigned_integer (&buf
[0],
13092 gdbarch_byte_order_for_code (insn_record
->gdbarch
));
13096 typedef int (*sti_arm_hdl_fp_t
) (insn_decode_record
*);
13098 /* Decode arm/thumb insn depending on condition cods and opcodes; and
13102 decode_insn (abstract_memory_reader
&reader
, insn_decode_record
*arm_record
,
13103 record_type_t record_type
, uint32_t insn_size
)
13106 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm
13108 static const sti_arm_hdl_fp_t arm_handle_insn
[8] =
13110 arm_record_data_proc_misc_ld_str
, /* 000. */
13111 arm_record_data_proc_imm
, /* 001. */
13112 arm_record_ld_st_imm_offset
, /* 010. */
13113 arm_record_ld_st_reg_offset
, /* 011. */
13114 arm_record_ld_st_multiple
, /* 100. */
13115 arm_record_b_bl
, /* 101. */
13116 arm_record_asimd_vfp_coproc
, /* 110. */
13117 arm_record_coproc_data_proc
/* 111. */
13120 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb
13122 static const sti_arm_hdl_fp_t thumb_handle_insn
[8] =
13124 thumb_record_shift_add_sub
, /* 000. */
13125 thumb_record_add_sub_cmp_mov
, /* 001. */
13126 thumb_record_ld_st_reg_offset
, /* 010. */
13127 thumb_record_ld_st_imm_offset
, /* 011. */
13128 thumb_record_ld_st_stack
, /* 100. */
13129 thumb_record_misc
, /* 101. */
13130 thumb_record_ldm_stm_swi
, /* 110. */
13131 thumb_record_branch
/* 111. */
13134 uint32_t ret
= 0; /* return value: negative:failure 0:success. */
13135 uint32_t insn_id
= 0;
13137 if (extract_arm_insn (reader
, arm_record
, insn_size
))
13141 printf_unfiltered (_("Process record: error reading memory at "
13142 "addr %s len = %d.\n"),
13143 paddress (arm_record
->gdbarch
,
13144 arm_record
->this_addr
), insn_size
);
13148 else if (ARM_RECORD
== record_type
)
13150 arm_record
->cond
= bits (arm_record
->arm_insn
, 28, 31);
13151 insn_id
= bits (arm_record
->arm_insn
, 25, 27);
13153 if (arm_record
->cond
== 0xf)
13154 ret
= arm_record_extension_space (arm_record
);
13157 /* If this insn has fallen into extension space
13158 then we need not decode it anymore. */
13159 ret
= arm_handle_insn
[insn_id
] (arm_record
);
13161 if (ret
!= ARM_RECORD_SUCCESS
)
13163 arm_record_unsupported_insn (arm_record
);
13167 else if (THUMB_RECORD
== record_type
)
13169 /* As thumb does not have condition codes, we set negative. */
13170 arm_record
->cond
= -1;
13171 insn_id
= bits (arm_record
->arm_insn
, 13, 15);
13172 ret
= thumb_handle_insn
[insn_id
] (arm_record
);
13173 if (ret
!= ARM_RECORD_SUCCESS
)
13175 arm_record_unsupported_insn (arm_record
);
13179 else if (THUMB2_RECORD
== record_type
)
13181 /* As thumb does not have condition codes, we set negative. */
13182 arm_record
->cond
= -1;
13184 /* Swap first half of 32bit thumb instruction with second half. */
13185 arm_record
->arm_insn
13186 = (arm_record
->arm_insn
>> 16) | (arm_record
->arm_insn
<< 16);
13188 ret
= thumb2_record_decode_insn_handler (arm_record
);
13190 if (ret
!= ARM_RECORD_SUCCESS
)
13192 arm_record_unsupported_insn (arm_record
);
13198 /* Throw assertion. */
13199 gdb_assert_not_reached ("not a valid instruction, could not decode");
13206 namespace selftests
{
13208 /* Provide both 16-bit and 32-bit thumb instructions. */
13210 class instruction_reader_thumb
: public abstract_memory_reader
13213 template<size_t SIZE
>
13214 instruction_reader_thumb (enum bfd_endian endian
,
13215 const uint16_t (&insns
)[SIZE
])
13216 : m_endian (endian
), m_insns (insns
), m_insns_size (SIZE
)
13219 bool read (CORE_ADDR memaddr
, gdb_byte
*buf
, const size_t len
) override
13221 SELF_CHECK (len
== 4 || len
== 2);
13222 SELF_CHECK (memaddr
% 2 == 0);
13223 SELF_CHECK ((memaddr
/ 2) < m_insns_size
);
13225 store_unsigned_integer (buf
, 2, m_endian
, m_insns
[memaddr
/ 2]);
13228 store_unsigned_integer (&buf
[2], 2, m_endian
,
13229 m_insns
[memaddr
/ 2 + 1]);
13235 enum bfd_endian m_endian
;
13236 const uint16_t *m_insns
;
13237 size_t m_insns_size
;
13241 arm_record_test (void)
13243 struct gdbarch_info info
;
13244 gdbarch_info_init (&info
);
13245 info
.bfd_arch_info
= bfd_scan_arch ("arm");
13247 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
13249 SELF_CHECK (gdbarch
!= NULL
);
13251 /* 16-bit Thumb instructions. */
13253 insn_decode_record arm_record
;
13255 memset (&arm_record
, 0, sizeof (insn_decode_record
));
13256 arm_record
.gdbarch
= gdbarch
;
13258 static const uint16_t insns
[] = {
13259 /* db b2 uxtb r3, r3 */
13261 /* cd 58 ldr r5, [r1, r3] */
13265 enum bfd_endian endian
= gdbarch_byte_order_for_code (arm_record
.gdbarch
);
13266 instruction_reader_thumb
reader (endian
, insns
);
13267 int ret
= decode_insn (reader
, &arm_record
, THUMB_RECORD
,
13268 THUMB_INSN_SIZE_BYTES
);
13270 SELF_CHECK (ret
== 0);
13271 SELF_CHECK (arm_record
.mem_rec_count
== 0);
13272 SELF_CHECK (arm_record
.reg_rec_count
== 1);
13273 SELF_CHECK (arm_record
.arm_regs
[0] == 3);
13275 arm_record
.this_addr
+= 2;
13276 ret
= decode_insn (reader
, &arm_record
, THUMB_RECORD
,
13277 THUMB_INSN_SIZE_BYTES
);
13279 SELF_CHECK (ret
== 0);
13280 SELF_CHECK (arm_record
.mem_rec_count
== 0);
13281 SELF_CHECK (arm_record
.reg_rec_count
== 1);
13282 SELF_CHECK (arm_record
.arm_regs
[0] == 5);
13285 /* 32-bit Thumb-2 instructions. */
13287 insn_decode_record arm_record
;
13289 memset (&arm_record
, 0, sizeof (insn_decode_record
));
13290 arm_record
.gdbarch
= gdbarch
;
13292 static const uint16_t insns
[] = {
13293 /* 1d ee 70 7f mrc 15, 0, r7, cr13, cr0, {3} */
13297 enum bfd_endian endian
= gdbarch_byte_order_for_code (arm_record
.gdbarch
);
13298 instruction_reader_thumb
reader (endian
, insns
);
13299 int ret
= decode_insn (reader
, &arm_record
, THUMB2_RECORD
,
13300 THUMB2_INSN_SIZE_BYTES
);
13302 SELF_CHECK (ret
== 0);
13303 SELF_CHECK (arm_record
.mem_rec_count
== 0);
13304 SELF_CHECK (arm_record
.reg_rec_count
== 1);
13305 SELF_CHECK (arm_record
.arm_regs
[0] == 7);
13308 } // namespace selftests
13309 #endif /* GDB_SELF_TEST */
13311 /* Cleans up local record registers and memory allocations. */
13314 deallocate_reg_mem (insn_decode_record
*record
)
13316 xfree (record
->arm_regs
);
13317 xfree (record
->arm_mems
);
13321 /* Parse the current instruction and record the values of the registers and
13322 memory that will be changed in current instruction to record_arch_list".
13323 Return -1 if something is wrong. */
13326 arm_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
13327 CORE_ADDR insn_addr
)
13330 uint32_t no_of_rec
= 0;
13331 uint32_t ret
= 0; /* return value: -1:record failure ; 0:success */
13332 ULONGEST t_bit
= 0, insn_id
= 0;
13334 ULONGEST u_regval
= 0;
13336 insn_decode_record arm_record
;
13338 memset (&arm_record
, 0, sizeof (insn_decode_record
));
13339 arm_record
.regcache
= regcache
;
13340 arm_record
.this_addr
= insn_addr
;
13341 arm_record
.gdbarch
= gdbarch
;
13344 if (record_debug
> 1)
13346 fprintf_unfiltered (gdb_stdlog
, "Process record: arm_process_record "
13348 paddress (gdbarch
, arm_record
.this_addr
));
13351 instruction_reader reader
;
13352 if (extract_arm_insn (reader
, &arm_record
, 2))
13356 printf_unfiltered (_("Process record: error reading memory at "
13357 "addr %s len = %d.\n"),
13358 paddress (arm_record
.gdbarch
,
13359 arm_record
.this_addr
), 2);
13364 /* Check the insn, whether it is thumb or arm one. */
13366 t_bit
= arm_psr_thumb_bit (arm_record
.gdbarch
);
13367 regcache_raw_read_unsigned (arm_record
.regcache
, ARM_PS_REGNUM
, &u_regval
);
13370 if (!(u_regval
& t_bit
))
13372 /* We are decoding arm insn. */
13373 ret
= decode_insn (reader
, &arm_record
, ARM_RECORD
, ARM_INSN_SIZE_BYTES
);
13377 insn_id
= bits (arm_record
.arm_insn
, 11, 15);
13378 /* is it thumb2 insn? */
13379 if ((0x1D == insn_id
) || (0x1E == insn_id
) || (0x1F == insn_id
))
13381 ret
= decode_insn (reader
, &arm_record
, THUMB2_RECORD
,
13382 THUMB2_INSN_SIZE_BYTES
);
13386 /* We are decoding thumb insn. */
13387 ret
= decode_insn (reader
, &arm_record
, THUMB_RECORD
,
13388 THUMB_INSN_SIZE_BYTES
);
13394 /* Record registers. */
13395 record_full_arch_list_add_reg (arm_record
.regcache
, ARM_PC_REGNUM
);
13396 if (arm_record
.arm_regs
)
13398 for (no_of_rec
= 0; no_of_rec
< arm_record
.reg_rec_count
; no_of_rec
++)
13400 if (record_full_arch_list_add_reg
13401 (arm_record
.regcache
, arm_record
.arm_regs
[no_of_rec
]))
13405 /* Record memories. */
13406 if (arm_record
.arm_mems
)
13408 for (no_of_rec
= 0; no_of_rec
< arm_record
.mem_rec_count
; no_of_rec
++)
13410 if (record_full_arch_list_add_mem
13411 ((CORE_ADDR
)arm_record
.arm_mems
[no_of_rec
].addr
,
13412 arm_record
.arm_mems
[no_of_rec
].len
))
13417 if (record_full_arch_list_add_end ())
13422 deallocate_reg_mem (&arm_record
);