1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper () */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
43 #include "target-descriptions.h"
44 #include "user-regs.h"
47 #include "gdb/sim-arm.h"
50 #include "coff/internal.h"
53 #include "gdb_assert.h"
58 /* Macros for setting and testing a bit in a minimal symbol that marks
59 it as Thumb function. The MSB of the minimal symbol's "info" field
60 is used for this purpose.
62 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
63 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
65 #define MSYMBOL_SET_SPECIAL(msym) \
66 MSYMBOL_TARGET_FLAG_1 (msym) = 1
68 #define MSYMBOL_IS_SPECIAL(msym) \
69 MSYMBOL_TARGET_FLAG_1 (msym)
71 /* Per-objfile data used for mapping symbols. */
72 static const struct objfile_data
*arm_objfile_data_key
;
74 struct arm_mapping_symbol
79 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
80 DEF_VEC_O(arm_mapping_symbol_s
);
82 struct arm_per_objfile
84 VEC(arm_mapping_symbol_s
) **section_maps
;
87 /* The list of available "set arm ..." and "show arm ..." commands. */
88 static struct cmd_list_element
*setarmcmdlist
= NULL
;
89 static struct cmd_list_element
*showarmcmdlist
= NULL
;
91 /* The type of floating-point to use. Keep this in sync with enum
92 arm_float_model, and the help string in _initialize_arm_tdep. */
93 static const char *fp_model_strings
[] =
103 /* A variable that can be configured by the user. */
104 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
105 static const char *current_fp_model
= "auto";
107 /* The ABI to use. Keep this in sync with arm_abi_kind. */
108 static const char *arm_abi_strings
[] =
116 /* A variable that can be configured by the user. */
117 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
118 static const char *arm_abi_string
= "auto";
120 /* The execution mode to assume. */
121 static const char *arm_mode_strings
[] =
128 static const char *arm_fallback_mode_string
= "auto";
129 static const char *arm_force_mode_string
= "auto";
131 /* Number of different reg name sets (options). */
132 static int num_disassembly_options
;
134 /* The standard register names, and all the valid aliases for them. */
139 } arm_register_aliases
[] = {
140 /* Basic register numbers. */
157 /* Synonyms (argument and variable registers). */
170 /* Other platform-specific names for r9. */
178 /* Names used by GCC (not listed in the ARM EABI). */
181 /* A special name from the older ATPCS. */
185 static const char *const arm_register_names
[] =
186 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
187 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
188 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
189 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
190 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
191 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
192 "fps", "cpsr" }; /* 24 25 */
194 /* Valid register name styles. */
195 static const char **valid_disassembly_styles
;
197 /* Disassembly style to use. Default to "std" register names. */
198 static const char *disassembly_style
;
200 /* This is used to keep the bfd arch_info in sync with the disassembly
202 static void set_disassembly_style_sfunc(char *, int,
203 struct cmd_list_element
*);
204 static void set_disassembly_style (void);
206 static void convert_from_extended (const struct floatformat
*, const void *,
208 static void convert_to_extended (const struct floatformat
*, void *,
211 struct arm_prologue_cache
213 /* The stack pointer at the time this frame was created; i.e. the
214 caller's stack pointer when this function was called. It is used
215 to identify this frame. */
218 /* The frame base for this frame is just prev_sp - frame size.
219 FRAMESIZE is the distance from the frame pointer to the
220 initial stack pointer. */
224 /* The register used to hold the frame pointer for this frame. */
227 /* Saved register offsets. */
228 struct trad_frame_saved_reg
*saved_regs
;
231 /* Addresses for calling Thumb functions have the bit 0 set.
232 Here are some macros to test, set, or clear bit 0 of addresses. */
233 #define IS_THUMB_ADDR(addr) ((addr) & 1)
234 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
235 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
237 /* Set to true if the 32-bit mode is in use. */
241 /* Determine if FRAME is executing in Thumb mode. */
244 arm_frame_is_thumb (struct frame_info
*frame
)
248 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
249 directly (from a signal frame or dummy frame) or by interpreting
250 the saved LR (from a prologue or DWARF frame). So consult it and
251 trust the unwinders. */
252 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
254 return (cpsr
& CPSR_T
) != 0;
257 /* Callback for VEC_lower_bound. */
260 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
261 const struct arm_mapping_symbol
*rhs
)
263 return lhs
->value
< rhs
->value
;
266 /* Determine if the program counter specified in MEMADDR is in a Thumb
267 function. This function should be called for addresses unrelated to
268 any executing frame; otherwise, prefer arm_frame_is_thumb. */
271 arm_pc_is_thumb (CORE_ADDR memaddr
)
273 struct obj_section
*sec
;
274 struct minimal_symbol
*sym
;
276 /* If bit 0 of the address is set, assume this is a Thumb address. */
277 if (IS_THUMB_ADDR (memaddr
))
280 /* If the user wants to override the symbol table, let him. */
281 if (strcmp (arm_force_mode_string
, "arm") == 0)
283 if (strcmp (arm_force_mode_string
, "thumb") == 0)
286 /* If there are mapping symbols, consult them. */
287 sec
= find_pc_section (memaddr
);
290 struct arm_per_objfile
*data
;
291 VEC(arm_mapping_symbol_s
) *map
;
292 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
296 data
= objfile_data (sec
->objfile
, arm_objfile_data_key
);
299 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
300 if (!VEC_empty (arm_mapping_symbol_s
, map
))
302 struct arm_mapping_symbol
*map_sym
;
304 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
305 arm_compare_mapping_symbols
);
307 /* VEC_lower_bound finds the earliest ordered insertion
308 point. If the following symbol starts at this exact
309 address, we use that; otherwise, the preceding
310 mapping symbol covers this address. */
311 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
313 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
314 if (map_sym
->value
== map_key
.value
)
315 return map_sym
->type
== 't';
320 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
321 return map_sym
->type
== 't';
327 /* Thumb functions have a "special" bit set in minimal symbols. */
328 sym
= lookup_minimal_symbol_by_pc (memaddr
);
330 return (MSYMBOL_IS_SPECIAL (sym
));
332 /* If the user wants to override the fallback mode, let them. */
333 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
335 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
338 /* If we couldn't find any symbol, but we're talking to a running
339 target, then trust the current value of $cpsr. This lets
340 "display/i $pc" always show the correct mode (though if there is
341 a symbol table we will not reach here, so it still may not be
342 displayed in the mode it will be executed). */
343 if (target_has_registers
)
344 return arm_frame_is_thumb (get_current_frame ());
346 /* Otherwise we're out of luck; we assume ARM. */
350 /* Remove useless bits from addresses in a running program. */
352 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
355 return UNMAKE_THUMB_ADDR (val
);
357 return (val
& 0x03fffffc);
360 /* When reading symbols, we need to zap the low bit of the address,
361 which may be set to 1 for Thumb functions. */
363 arm_smash_text_address (struct gdbarch
*gdbarch
, CORE_ADDR val
)
368 /* Analyze a Thumb prologue, looking for a recognizable stack frame
369 and frame pointer. Scan until we encounter a store that could
370 clobber the stack frame unexpectedly, or an unknown instruction. */
373 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
374 CORE_ADDR start
, CORE_ADDR limit
,
375 struct arm_prologue_cache
*cache
)
377 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
380 struct pv_area
*stack
;
381 struct cleanup
*back_to
;
384 for (i
= 0; i
< 16; i
++)
385 regs
[i
] = pv_register (i
, 0);
386 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
387 back_to
= make_cleanup_free_pv_area (stack
);
389 while (start
< limit
)
393 insn
= read_memory_unsigned_integer (start
, 2, byte_order_for_code
);
395 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
400 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
403 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
404 whether to save LR (R14). */
405 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
407 /* Calculate offsets of saved R0-R7 and LR. */
408 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
409 if (mask
& (1 << regno
))
411 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
413 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
416 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
419 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
420 if (insn
& 0x80) /* Check for SUB. */
421 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
424 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
427 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
428 regs
[THUMB_FP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
430 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
432 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
433 int src_reg
= (insn
& 0x78) >> 3;
434 regs
[dst_reg
] = regs
[src_reg
];
436 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
438 /* Handle stores to the stack. Normally pushes are used,
439 but with GCC -mtpcs-frame, there may be other stores
440 in the prologue to create the frame. */
441 int regno
= (insn
>> 8) & 0x7;
444 offset
= (insn
& 0xff) << 2;
445 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
447 if (pv_area_store_would_trash (stack
, addr
))
450 pv_area_store (stack
, addr
, 4, regs
[regno
]);
454 /* We don't know what this instruction is. We're finished
455 scanning. NOTE: Recognizing more safe-to-ignore
456 instructions here will improve support for optimized
466 do_cleanups (back_to
);
470 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
472 /* Frame pointer is fp. Frame size is constant. */
473 cache
->framereg
= ARM_FP_REGNUM
;
474 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
476 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
478 /* Frame pointer is r7. Frame size is constant. */
479 cache
->framereg
= THUMB_FP_REGNUM
;
480 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
482 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
484 /* Try the stack pointer... this is a bit desperate. */
485 cache
->framereg
= ARM_SP_REGNUM
;
486 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
490 /* We're just out of luck. We don't know where the frame is. */
491 cache
->framereg
= -1;
492 cache
->framesize
= 0;
495 for (i
= 0; i
< 16; i
++)
496 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
497 cache
->saved_regs
[i
].addr
= offset
;
499 do_cleanups (back_to
);
503 /* Advance the PC across any function entry prologue instructions to
504 reach some "real" code.
506 The APCS (ARM Procedure Call Standard) defines the following
510 [stmfd sp!, {a1,a2,a3,a4}]
511 stmfd sp!, {...,fp,ip,lr,pc}
512 [stfe f7, [sp, #-12]!]
513 [stfe f6, [sp, #-12]!]
514 [stfe f5, [sp, #-12]!]
515 [stfe f4, [sp, #-12]!]
516 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
519 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
521 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
524 CORE_ADDR func_addr
, limit_pc
;
525 struct symtab_and_line sal
;
527 /* If we're in a dummy frame, don't even try to skip the prologue. */
528 if (deprecated_pc_in_call_dummy (gdbarch
, pc
))
531 /* See if we can determine the end of the prologue via the symbol table.
532 If so, then return either PC, or the PC after the prologue, whichever
534 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
536 CORE_ADDR post_prologue_pc
537 = skip_prologue_using_sal (gdbarch
, func_addr
);
538 if (post_prologue_pc
!= 0)
539 return max (pc
, post_prologue_pc
);
542 /* Can't determine prologue from the symbol table, need to examine
545 /* Find an upper limit on the function prologue using the debug
546 information. If the debug information could not be used to provide
547 that bound, then use an arbitrary large number as the upper bound. */
548 /* Like arm_scan_prologue, stop no later than pc + 64. */
549 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
551 limit_pc
= pc
+ 64; /* Magic. */
554 /* Check if this is Thumb code. */
555 if (arm_pc_is_thumb (pc
))
556 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
558 for (skip_pc
= pc
; skip_pc
< limit_pc
; skip_pc
+= 4)
560 inst
= read_memory_unsigned_integer (skip_pc
, 4, byte_order_for_code
);
562 /* "mov ip, sp" is no longer a required part of the prologue. */
563 if (inst
== 0xe1a0c00d) /* mov ip, sp */
566 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
569 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
572 /* Some prologues begin with "str lr, [sp, #-4]!". */
573 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
576 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
579 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
582 /* Any insns after this point may float into the code, if it makes
583 for better instruction scheduling, so we skip them only if we
584 find them, but still consider the function to be frame-ful. */
586 /* We may have either one sfmfd instruction here, or several stfe
587 insns, depending on the version of floating point code we
589 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
592 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
595 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
598 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
601 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
602 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
603 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
606 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
607 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
608 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
611 /* Un-recognized instruction; stop scanning. */
615 return skip_pc
; /* End of prologue */
619 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
620 This function decodes a Thumb function prologue to determine:
621 1) the size of the stack frame
622 2) which registers are saved on it
623 3) the offsets of saved regs
624 4) the offset from the stack pointer to the frame pointer
626 A typical Thumb function prologue would create this stack frame
627 (offsets relative to FP)
628 old SP -> 24 stack parameters
631 R7 -> 0 local variables (16 bytes)
632 SP -> -12 additional stack space (12 bytes)
633 The frame size would thus be 36 bytes, and the frame offset would be
634 12 bytes. The frame register is R7.
636 The comments for thumb_skip_prolog() describe the algorithm we use
637 to detect the end of the prolog. */
641 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
642 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
644 CORE_ADDR prologue_start
;
645 CORE_ADDR prologue_end
;
646 CORE_ADDR current_pc
;
648 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
651 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
653 if (sal
.line
== 0) /* no line info, use current PC */
654 prologue_end
= prev_pc
;
655 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
656 prologue_end
= sal
.end
; /* (probably means no prologue) */
659 /* We're in the boondocks: we have no idea where the start of the
663 prologue_end
= min (prologue_end
, prev_pc
);
665 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
668 /* This function decodes an ARM function prologue to determine:
669 1) the size of the stack frame
670 2) which registers are saved on it
671 3) the offsets of saved regs
672 4) the offset from the stack pointer to the frame pointer
673 This information is stored in the "extra" fields of the frame_info.
675 There are two basic forms for the ARM prologue. The fixed argument
676 function call will look like:
679 stmfd sp!, {fp, ip, lr, pc}
683 Which would create this stack frame (offsets relative to FP):
684 IP -> 4 (caller's stack)
685 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
686 -4 LR (return address in caller)
687 -8 IP (copy of caller's SP)
689 SP -> -28 Local variables
691 The frame size would thus be 32 bytes, and the frame offset would be
692 28 bytes. The stmfd call can also save any of the vN registers it
693 plans to use, which increases the frame size accordingly.
695 Note: The stored PC is 8 off of the STMFD instruction that stored it
696 because the ARM Store instructions always store PC + 8 when you read
699 A variable argument function call will look like:
702 stmfd sp!, {a1, a2, a3, a4}
703 stmfd sp!, {fp, ip, lr, pc}
706 Which would create this stack frame (offsets relative to FP):
707 IP -> 20 (caller's stack)
712 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
713 -4 LR (return address in caller)
714 -8 IP (copy of caller's SP)
716 SP -> -28 Local variables
718 The frame size would thus be 48 bytes, and the frame offset would be
721 There is another potential complication, which is that the optimizer
722 will try to separate the store of fp in the "stmfd" instruction from
723 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
724 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
726 Also, note, the original version of the ARM toolchain claimed that there
729 instruction at the end of the prologue. I have never seen GCC produce
730 this, and the ARM docs don't mention it. We still test for it below in
736 arm_scan_prologue (struct frame_info
*this_frame
,
737 struct arm_prologue_cache
*cache
)
739 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
740 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
741 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
743 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
744 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
745 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
746 pv_t regs
[ARM_FPS_REGNUM
];
747 struct pv_area
*stack
;
748 struct cleanup
*back_to
;
751 /* Assume there is no frame until proven otherwise. */
752 cache
->framereg
= ARM_SP_REGNUM
;
753 cache
->framesize
= 0;
755 /* Check for Thumb prologue. */
756 if (arm_frame_is_thumb (this_frame
))
758 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
762 /* Find the function prologue. If we can't find the function in
763 the symbol table, peek in the stack frame to find the PC. */
764 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
767 /* One way to find the end of the prologue (which works well
768 for unoptimized code) is to do the following:
770 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
773 prologue_end = prev_pc;
774 else if (sal.end < prologue_end)
775 prologue_end = sal.end;
777 This mechanism is very accurate so long as the optimizer
778 doesn't move any instructions from the function body into the
779 prologue. If this happens, sal.end will be the last
780 instruction in the first hunk of prologue code just before
781 the first instruction that the scheduler has moved from
782 the body to the prologue.
784 In order to make sure that we scan all of the prologue
785 instructions, we use a slightly less accurate mechanism which
786 may scan more than necessary. To help compensate for this
787 lack of accuracy, the prologue scanning loop below contains
788 several clauses which'll cause the loop to terminate early if
789 an implausible prologue instruction is encountered.
795 is a suitable endpoint since it accounts for the largest
796 possible prologue plus up to five instructions inserted by
799 if (prologue_end
> prologue_start
+ 64)
801 prologue_end
= prologue_start
+ 64; /* See above. */
806 /* We have no symbol information. Our only option is to assume this
807 function has a standard stack frame and the normal frame register.
808 Then, we can find the value of our frame pointer on entrance to
809 the callee (or at the present moment if this is the innermost frame).
810 The value stored there should be the address of the stmfd + 8. */
812 LONGEST return_value
;
814 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
815 if (!safe_read_memory_integer (frame_loc
, 4, byte_order
, &return_value
))
819 prologue_start
= gdbarch_addr_bits_remove
820 (gdbarch
, return_value
) - 8;
821 prologue_end
= prologue_start
+ 64; /* See above. */
825 if (prev_pc
< prologue_end
)
826 prologue_end
= prev_pc
;
828 /* Now search the prologue looking for instructions that set up the
829 frame pointer, adjust the stack pointer, and save registers.
831 Be careful, however, and if it doesn't look like a prologue,
832 don't try to scan it. If, for instance, a frameless function
833 begins with stmfd sp!, then we will tell ourselves there is
834 a frame, which will confuse stack traceback, as well as "finish"
835 and other operations that rely on a knowledge of the stack
838 In the APCS, the prologue should start with "mov ip, sp" so
839 if we don't see this as the first insn, we will stop.
841 [Note: This doesn't seem to be true any longer, so it's now an
842 optional part of the prologue. - Kevin Buettner, 2001-11-20]
844 [Note further: The "mov ip,sp" only seems to be missing in
845 frameless functions at optimization level "-O2" or above,
846 in which case it is often (but not always) replaced by
847 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
849 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
850 regs
[regno
] = pv_register (regno
, 0);
851 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
852 back_to
= make_cleanup_free_pv_area (stack
);
854 for (current_pc
= prologue_start
;
855 current_pc
< prologue_end
;
859 = read_memory_unsigned_integer (current_pc
, 4, byte_order_for_code
);
861 if (insn
== 0xe1a0c00d) /* mov ip, sp */
863 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
866 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
868 unsigned imm
= insn
& 0xff; /* immediate value */
869 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
870 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
871 regs
[ARM_IP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], imm
);
874 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
876 unsigned imm
= insn
& 0xff; /* immediate value */
877 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
878 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
879 regs
[ARM_IP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
882 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
884 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
886 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
887 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[ARM_LR_REGNUM
]);
890 else if ((insn
& 0xffff0000) == 0xe92d0000)
891 /* stmfd sp!, {..., fp, ip, lr, pc}
893 stmfd sp!, {a1, a2, a3, a4} */
895 int mask
= insn
& 0xffff;
897 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
900 /* Calculate offsets of saved registers. */
901 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
902 if (mask
& (1 << regno
))
904 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
905 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
908 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
909 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
910 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
912 /* No need to add this to saved_regs -- it's just an arg reg. */
915 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
916 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
917 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
919 /* No need to add this to saved_regs -- it's just an arg reg. */
922 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
924 unsigned imm
= insn
& 0xff; /* immediate value */
925 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
926 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
927 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
929 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
931 unsigned imm
= insn
& 0xff; /* immediate value */
932 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
933 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
934 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
936 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
937 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
939 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
942 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
943 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
944 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
946 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
947 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
950 unsigned int fp_start_reg
, fp_bound_reg
;
952 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
955 if ((insn
& 0x800) == 0x800) /* N0 is set */
957 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
964 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
970 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
971 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
972 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
974 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
975 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
976 regs
[fp_start_reg
++]);
979 else if ((insn
& 0xf0000000) != 0xe0000000)
980 break; /* Condition not true, exit early */
981 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
982 break; /* Don't scan past a block load */
984 /* The optimizer might shove anything into the prologue,
985 so we just skip what we don't recognize. */
989 /* The frame size is just the distance from the frame register
990 to the original stack pointer. */
991 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
993 /* Frame pointer is fp. */
994 cache
->framereg
= ARM_FP_REGNUM
;
995 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
997 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
999 /* Try the stack pointer... this is a bit desperate. */
1000 cache
->framereg
= ARM_SP_REGNUM
;
1001 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1005 /* We're just out of luck. We don't know where the frame is. */
1006 cache
->framereg
= -1;
1007 cache
->framesize
= 0;
1010 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1011 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1012 cache
->saved_regs
[regno
].addr
= offset
;
1014 do_cleanups (back_to
);
1017 static struct arm_prologue_cache
*
1018 arm_make_prologue_cache (struct frame_info
*this_frame
)
1021 struct arm_prologue_cache
*cache
;
1022 CORE_ADDR unwound_fp
;
1024 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1025 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1027 arm_scan_prologue (this_frame
, cache
);
1029 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
1030 if (unwound_fp
== 0)
1033 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
1035 /* Calculate actual addresses of saved registers using offsets
1036 determined by arm_scan_prologue. */
1037 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
1038 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
1039 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
1044 /* Our frame ID for a normal frame is the current function's starting PC
1045 and the caller's SP when we were called. */
1048 arm_prologue_this_id (struct frame_info
*this_frame
,
1050 struct frame_id
*this_id
)
1052 struct arm_prologue_cache
*cache
;
1056 if (*this_cache
== NULL
)
1057 *this_cache
= arm_make_prologue_cache (this_frame
);
1058 cache
= *this_cache
;
1060 /* This is meant to halt the backtrace at "_start". */
1061 pc
= get_frame_pc (this_frame
);
1062 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1065 /* If we've hit a wall, stop. */
1066 if (cache
->prev_sp
== 0)
1069 func
= get_frame_func (this_frame
);
1070 id
= frame_id_build (cache
->prev_sp
, func
);
1074 static struct value
*
1075 arm_prologue_prev_register (struct frame_info
*this_frame
,
1079 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1080 struct arm_prologue_cache
*cache
;
1082 if (*this_cache
== NULL
)
1083 *this_cache
= arm_make_prologue_cache (this_frame
);
1084 cache
= *this_cache
;
1086 /* If we are asked to unwind the PC, then we need to return the LR
1087 instead. The prologue may save PC, but it will point into this
1088 frame's prologue, not the next frame's resume location. Also
1089 strip the saved T bit. A valid LR may have the low bit set, but
1090 a valid PC never does. */
1091 if (prev_regnum
== ARM_PC_REGNUM
)
1095 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1096 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1097 arm_addr_bits_remove (gdbarch
, lr
));
1100 /* SP is generally not saved to the stack, but this frame is
1101 identified by the next frame's stack pointer at the time of the call.
1102 The value was already reconstructed into PREV_SP. */
1103 if (prev_regnum
== ARM_SP_REGNUM
)
1104 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1106 /* The CPSR may have been changed by the call instruction and by the
1107 called function. The only bit we can reconstruct is the T bit,
1108 by checking the low bit of LR as of the call. This is a reliable
1109 indicator of Thumb-ness except for some ARM v4T pre-interworking
1110 Thumb code, which could get away with a clear low bit as long as
1111 the called function did not use bx. Guess that all other
1112 bits are unchanged; the condition flags are presumably lost,
1113 but the processor status is likely valid. */
1114 if (prev_regnum
== ARM_PS_REGNUM
)
1118 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1119 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1120 if (IS_THUMB_ADDR (lr
))
1124 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1127 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1131 struct frame_unwind arm_prologue_unwind
= {
1133 arm_prologue_this_id
,
1134 arm_prologue_prev_register
,
1136 default_frame_sniffer
1139 static struct arm_prologue_cache
*
1140 arm_make_stub_cache (struct frame_info
*this_frame
)
1143 struct arm_prologue_cache
*cache
;
1144 CORE_ADDR unwound_fp
;
1146 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1147 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1149 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1154 /* Our frame ID for a stub frame is the current SP and LR. */
1157 arm_stub_this_id (struct frame_info
*this_frame
,
1159 struct frame_id
*this_id
)
1161 struct arm_prologue_cache
*cache
;
1163 if (*this_cache
== NULL
)
1164 *this_cache
= arm_make_stub_cache (this_frame
);
1165 cache
= *this_cache
;
1167 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
1171 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
1172 struct frame_info
*this_frame
,
1173 void **this_prologue_cache
)
1175 CORE_ADDR addr_in_block
;
1178 addr_in_block
= get_frame_address_in_block (this_frame
);
1179 if (in_plt_section (addr_in_block
, NULL
)
1180 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
1186 struct frame_unwind arm_stub_unwind
= {
1189 arm_prologue_prev_register
,
1191 arm_stub_unwind_sniffer
1195 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
1197 struct arm_prologue_cache
*cache
;
1199 if (*this_cache
== NULL
)
1200 *this_cache
= arm_make_prologue_cache (this_frame
);
1201 cache
= *this_cache
;
1203 return cache
->prev_sp
- cache
->framesize
;
1206 struct frame_base arm_normal_base
= {
1207 &arm_prologue_unwind
,
1208 arm_normal_frame_base
,
1209 arm_normal_frame_base
,
1210 arm_normal_frame_base
1213 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1214 dummy frame. The frame ID's base needs to match the TOS value
1215 saved by save_dummy_frame_tos() and returned from
1216 arm_push_dummy_call, and the PC needs to match the dummy frame's
1219 static struct frame_id
1220 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1222 return frame_id_build (get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
),
1223 get_frame_pc (this_frame
));
1226 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1227 be used to construct the previous frame's ID, after looking up the
1228 containing function). */
1231 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1234 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1235 return arm_addr_bits_remove (gdbarch
, pc
);
1239 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1241 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1244 static struct value
*
1245 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1248 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
1254 /* The PC is normally copied from the return column, which
1255 describes saves of LR. However, that version may have an
1256 extra bit set to indicate Thumb state. The bit is not
1258 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1259 return frame_unwind_got_constant (this_frame
, regnum
,
1260 arm_addr_bits_remove (gdbarch
, lr
));
1263 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
1264 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
1265 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1266 if (IS_THUMB_ADDR (lr
))
1270 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
1273 internal_error (__FILE__
, __LINE__
,
1274 _("Unexpected register %d"), regnum
);
1279 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1280 struct dwarf2_frame_state_reg
*reg
,
1281 struct frame_info
*this_frame
)
1287 reg
->how
= DWARF2_FRAME_REG_FN
;
1288 reg
->loc
.fn
= arm_dwarf2_prev_register
;
1291 reg
->how
= DWARF2_FRAME_REG_CFA
;
1296 /* When arguments must be pushed onto the stack, they go on in reverse
1297 order. The code below implements a FILO (stack) to do this. */
1302 struct stack_item
*prev
;
1306 static struct stack_item
*
1307 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1309 struct stack_item
*si
;
1310 si
= xmalloc (sizeof (struct stack_item
));
1311 si
->data
= xmalloc (len
);
1314 memcpy (si
->data
, contents
, len
);
1318 static struct stack_item
*
1319 pop_stack_item (struct stack_item
*si
)
1321 struct stack_item
*dead
= si
;
1329 /* Return the alignment (in bytes) of the given type. */
1332 arm_type_align (struct type
*t
)
1338 t
= check_typedef (t
);
1339 switch (TYPE_CODE (t
))
1342 /* Should never happen. */
1343 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1347 case TYPE_CODE_ENUM
:
1351 case TYPE_CODE_RANGE
:
1352 case TYPE_CODE_BITSTRING
:
1354 case TYPE_CODE_CHAR
:
1355 case TYPE_CODE_BOOL
:
1356 return TYPE_LENGTH (t
);
1358 case TYPE_CODE_ARRAY
:
1359 case TYPE_CODE_COMPLEX
:
1360 /* TODO: What about vector types? */
1361 return arm_type_align (TYPE_TARGET_TYPE (t
));
1363 case TYPE_CODE_STRUCT
:
1364 case TYPE_CODE_UNION
:
1366 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1368 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
1376 /* We currently only support passing parameters in integer registers. This
1377 conforms with GCC's default model. Several other variants exist and
1378 we should probably support some of them based on the selected ABI. */
1381 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1382 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1383 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1384 CORE_ADDR struct_addr
)
1386 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1390 struct stack_item
*si
= NULL
;
1392 /* Set the return address. For the ARM, the return breakpoint is
1393 always at BP_ADDR. */
1394 /* XXX Fix for Thumb. */
1395 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1397 /* Walk through the list of args and determine how large a temporary
1398 stack is required. Need to take care here as structs may be
1399 passed on the stack, and we have to to push them. */
1402 argreg
= ARM_A1_REGNUM
;
1405 /* The struct_return pointer occupies the first parameter
1406 passing register. */
1410 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
1411 gdbarch_register_name (gdbarch
, argreg
),
1412 paddress (gdbarch
, struct_addr
));
1413 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1417 for (argnum
= 0; argnum
< nargs
; argnum
++)
1420 struct type
*arg_type
;
1421 struct type
*target_type
;
1422 enum type_code typecode
;
1426 arg_type
= check_typedef (value_type (args
[argnum
]));
1427 len
= TYPE_LENGTH (arg_type
);
1428 target_type
= TYPE_TARGET_TYPE (arg_type
);
1429 typecode
= TYPE_CODE (arg_type
);
1430 val
= value_contents_writeable (args
[argnum
]);
1432 align
= arm_type_align (arg_type
);
1433 /* Round alignment up to a whole number of words. */
1434 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
1435 /* Different ABIs have different maximum alignments. */
1436 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
1438 /* The APCS ABI only requires word alignment. */
1439 align
= INT_REGISTER_SIZE
;
1443 /* The AAPCS requires at most doubleword alignment. */
1444 if (align
> INT_REGISTER_SIZE
* 2)
1445 align
= INT_REGISTER_SIZE
* 2;
1448 /* Push stack padding for dowubleword alignment. */
1449 if (nstack
& (align
- 1))
1451 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1452 nstack
+= INT_REGISTER_SIZE
;
1455 /* Doubleword aligned quantities must go in even register pairs. */
1456 if (argreg
<= ARM_LAST_ARG_REGNUM
1457 && align
> INT_REGISTER_SIZE
1461 /* If the argument is a pointer to a function, and it is a
1462 Thumb function, create a LOCAL copy of the value and set
1463 the THUMB bit in it. */
1464 if (TYPE_CODE_PTR
== typecode
1465 && target_type
!= NULL
1466 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1468 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
1469 if (arm_pc_is_thumb (regval
))
1472 store_unsigned_integer (val
, len
, byte_order
,
1473 MAKE_THUMB_ADDR (regval
));
1477 /* Copy the argument to general registers or the stack in
1478 register-sized pieces. Large arguments are split between
1479 registers and stack. */
1482 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
1484 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1486 /* The argument is being passed in a general purpose
1489 = extract_unsigned_integer (val
, partial_len
, byte_order
);
1490 if (byte_order
== BFD_ENDIAN_BIG
)
1491 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
1493 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1495 gdbarch_register_name
1497 phex (regval
, INT_REGISTER_SIZE
));
1498 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1503 /* Push the arguments onto the stack. */
1505 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1507 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1508 nstack
+= INT_REGISTER_SIZE
;
1515 /* If we have an odd number of words to push, then decrement the stack
1516 by one word now, so first stack argument will be dword aligned. */
1523 write_memory (sp
, si
->data
, si
->len
);
1524 si
= pop_stack_item (si
);
1527 /* Finally, update teh SP register. */
1528 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1534 /* Always align the frame to an 8-byte boundary. This is required on
1535 some platforms and harmless on the rest. */
1538 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1540 /* Align the stack to eight bytes. */
1541 return sp
& ~ (CORE_ADDR
) 7;
1545 print_fpu_flags (int flags
)
1547 if (flags
& (1 << 0))
1548 fputs ("IVO ", stdout
);
1549 if (flags
& (1 << 1))
1550 fputs ("DVZ ", stdout
);
1551 if (flags
& (1 << 2))
1552 fputs ("OFL ", stdout
);
1553 if (flags
& (1 << 3))
1554 fputs ("UFL ", stdout
);
1555 if (flags
& (1 << 4))
1556 fputs ("INX ", stdout
);
1560 /* Print interesting information about the floating point processor
1561 (if present) or emulator. */
1563 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1564 struct frame_info
*frame
, const char *args
)
1566 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
1569 type
= (status
>> 24) & 127;
1570 if (status
& (1 << 31))
1571 printf (_("Hardware FPU type %d\n"), type
);
1573 printf (_("Software FPU type %d\n"), type
);
1574 /* i18n: [floating point unit] mask */
1575 fputs (_("mask: "), stdout
);
1576 print_fpu_flags (status
>> 16);
1577 /* i18n: [floating point unit] flags */
1578 fputs (_("flags: "), stdout
);
1579 print_fpu_flags (status
);
1582 /* Construct the ARM extended floating point type. */
1583 static struct type
*
1584 arm_ext_type (struct gdbarch
*gdbarch
)
1586 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1588 if (!tdep
->arm_ext_type
)
1590 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
1591 floatformats_arm_ext
);
1593 return tdep
->arm_ext_type
;
1596 /* Return the GDB type object for the "standard" data type of data in
1599 static struct type
*
1600 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
1602 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1603 return arm_ext_type (gdbarch
);
1604 else if (regnum
== ARM_SP_REGNUM
)
1605 return builtin_type (gdbarch
)->builtin_data_ptr
;
1606 else if (regnum
== ARM_PC_REGNUM
)
1607 return builtin_type (gdbarch
)->builtin_func_ptr
;
1608 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
1609 /* These registers are only supported on targets which supply
1610 an XML description. */
1611 return builtin_type (gdbarch
)->builtin_int0
;
1613 return builtin_type (gdbarch
)->builtin_uint32
;
1616 /* Map a DWARF register REGNUM onto the appropriate GDB register
1620 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
1622 /* Core integer regs. */
1623 if (reg
>= 0 && reg
<= 15)
1626 /* Legacy FPA encoding. These were once used in a way which
1627 overlapped with VFP register numbering, so their use is
1628 discouraged, but GDB doesn't support the ARM toolchain
1629 which used them for VFP. */
1630 if (reg
>= 16 && reg
<= 23)
1631 return ARM_F0_REGNUM
+ reg
- 16;
1633 /* New assignments for the FPA registers. */
1634 if (reg
>= 96 && reg
<= 103)
1635 return ARM_F0_REGNUM
+ reg
- 96;
1637 /* WMMX register assignments. */
1638 if (reg
>= 104 && reg
<= 111)
1639 return ARM_WCGR0_REGNUM
+ reg
- 104;
1641 if (reg
>= 112 && reg
<= 127)
1642 return ARM_WR0_REGNUM
+ reg
- 112;
1644 if (reg
>= 192 && reg
<= 199)
1645 return ARM_WC0_REGNUM
+ reg
- 192;
1650 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1652 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
1655 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
1657 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
1658 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
1660 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
1661 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
1663 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
1664 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
1666 if (reg
< NUM_GREGS
)
1667 return SIM_ARM_R0_REGNUM
+ reg
;
1670 if (reg
< NUM_FREGS
)
1671 return SIM_ARM_FP0_REGNUM
+ reg
;
1674 if (reg
< NUM_SREGS
)
1675 return SIM_ARM_FPS_REGNUM
+ reg
;
1678 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
1681 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1682 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1683 It is thought that this is is the floating-point register format on
1684 little-endian systems. */
1687 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
1688 void *dbl
, int endianess
)
1692 if (endianess
== BFD_ENDIAN_BIG
)
1693 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1695 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1697 floatformat_from_doublest (fmt
, &d
, dbl
);
1701 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
1706 floatformat_to_doublest (fmt
, ptr
, &d
);
1707 if (endianess
== BFD_ENDIAN_BIG
)
1708 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1710 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1715 condition_true (unsigned long cond
, unsigned long status_reg
)
1717 if (cond
== INST_AL
|| cond
== INST_NV
)
1723 return ((status_reg
& FLAG_Z
) != 0);
1725 return ((status_reg
& FLAG_Z
) == 0);
1727 return ((status_reg
& FLAG_C
) != 0);
1729 return ((status_reg
& FLAG_C
) == 0);
1731 return ((status_reg
& FLAG_N
) != 0);
1733 return ((status_reg
& FLAG_N
) == 0);
1735 return ((status_reg
& FLAG_V
) != 0);
1737 return ((status_reg
& FLAG_V
) == 0);
1739 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1741 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1743 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1745 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1747 return (((status_reg
& FLAG_Z
) == 0) &&
1748 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1750 return (((status_reg
& FLAG_Z
) != 0) ||
1751 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1756 /* Support routines for single stepping. Calculate the next PC value. */
1757 #define submask(x) ((1L << ((x) + 1)) - 1)
1758 #define bit(obj,st) (((obj) >> (st)) & 1)
1759 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1760 #define sbits(obj,st,fn) \
1761 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1762 #define BranchDest(addr,instr) \
1763 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1766 static unsigned long
1767 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
1768 unsigned long pc_val
, unsigned long status_reg
)
1770 unsigned long res
, shift
;
1771 int rm
= bits (inst
, 0, 3);
1772 unsigned long shifttype
= bits (inst
, 5, 6);
1776 int rs
= bits (inst
, 8, 11);
1777 shift
= (rs
== 15 ? pc_val
+ 8
1778 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
1781 shift
= bits (inst
, 7, 11);
1784 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1785 + (bit (inst
, 4) ? 12 : 8))
1786 : get_frame_register_unsigned (frame
, rm
));
1791 res
= shift
>= 32 ? 0 : res
<< shift
;
1795 res
= shift
>= 32 ? 0 : res
>> shift
;
1801 res
= ((res
& 0x80000000L
)
1802 ? ~((~res
) >> shift
) : res
>> shift
);
1805 case 3: /* ROR/RRX */
1808 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1810 res
= (res
>> shift
) | (res
<< (32 - shift
));
1814 return res
& 0xffffffff;
1817 /* Return number of 1-bits in VAL. */
1820 bitcount (unsigned long val
)
1823 for (nbits
= 0; val
!= 0; nbits
++)
1824 val
&= val
- 1; /* delete rightmost 1-bit in val */
1829 thumb_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1831 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1832 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1833 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1834 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1835 unsigned short inst1
;
1836 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1837 unsigned long offset
;
1839 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
1841 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1845 /* Fetch the saved PC from the stack. It's stored above
1846 all of the other registers. */
1847 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
1848 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
1849 nextpc
= read_memory_unsigned_integer (sp
+ offset
, 4, byte_order
);
1850 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1852 error (_("Infinite loop detected"));
1854 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1856 unsigned long status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
1857 unsigned long cond
= bits (inst1
, 8, 11);
1858 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1859 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1861 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1863 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1865 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link, and blx */
1867 unsigned short inst2
;
1868 inst2
= read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1869 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1870 nextpc
= pc_val
+ offset
;
1871 /* For BLX make sure to clear the low bits. */
1872 if (bits (inst2
, 11, 12) == 1)
1873 nextpc
= nextpc
& 0xfffffffc;
1875 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
1877 if (bits (inst1
, 3, 6) == 0x0f)
1880 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
1882 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1884 error (_("Infinite loop detected"));
1891 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1893 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1894 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1895 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1896 unsigned long pc_val
;
1897 unsigned long this_instr
;
1898 unsigned long status
;
1901 if (arm_frame_is_thumb (frame
))
1902 return thumb_get_next_pc (frame
, pc
);
1904 pc_val
= (unsigned long) pc
;
1905 this_instr
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
1907 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
1908 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1910 if (bits (this_instr
, 28, 31) == INST_NV
)
1911 switch (bits (this_instr
, 24, 27))
1916 /* Branch with Link and change to Thumb. */
1917 nextpc
= BranchDest (pc
, this_instr
);
1918 nextpc
|= bit (this_instr
, 24) << 1;
1920 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1922 error (_("Infinite loop detected"));
1928 /* Coprocessor register transfer. */
1929 if (bits (this_instr
, 12, 15) == 15)
1930 error (_("Invalid update to pc in instruction"));
1933 else if (condition_true (bits (this_instr
, 28, 31), status
))
1935 switch (bits (this_instr
, 24, 27))
1938 case 0x1: /* data processing */
1942 unsigned long operand1
, operand2
, result
= 0;
1946 if (bits (this_instr
, 12, 15) != 15)
1949 if (bits (this_instr
, 22, 25) == 0
1950 && bits (this_instr
, 4, 7) == 9) /* multiply */
1951 error (_("Invalid update to pc in instruction"));
1953 /* BX <reg>, BLX <reg> */
1954 if (bits (this_instr
, 4, 27) == 0x12fff1
1955 || bits (this_instr
, 4, 27) == 0x12fff3)
1957 rn
= bits (this_instr
, 0, 3);
1958 result
= (rn
== 15) ? pc_val
+ 8
1959 : get_frame_register_unsigned (frame
, rn
);
1960 nextpc
= (CORE_ADDR
) gdbarch_addr_bits_remove
1964 error (_("Infinite loop detected"));
1969 /* Multiply into PC */
1970 c
= (status
& FLAG_C
) ? 1 : 0;
1971 rn
= bits (this_instr
, 16, 19);
1972 operand1
= (rn
== 15) ? pc_val
+ 8
1973 : get_frame_register_unsigned (frame
, rn
);
1975 if (bit (this_instr
, 25))
1977 unsigned long immval
= bits (this_instr
, 0, 7);
1978 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1979 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1982 else /* operand 2 is a shifted register */
1983 operand2
= shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
);
1985 switch (bits (this_instr
, 21, 24))
1988 result
= operand1
& operand2
;
1992 result
= operand1
^ operand2
;
1996 result
= operand1
- operand2
;
2000 result
= operand2
- operand1
;
2004 result
= operand1
+ operand2
;
2008 result
= operand1
+ operand2
+ c
;
2012 result
= operand1
- operand2
+ c
;
2016 result
= operand2
- operand1
+ c
;
2022 case 0xb: /* tst, teq, cmp, cmn */
2023 result
= (unsigned long) nextpc
;
2027 result
= operand1
| operand2
;
2031 /* Always step into a function. */
2036 result
= operand1
& ~operand2
;
2043 nextpc
= (CORE_ADDR
) gdbarch_addr_bits_remove
2047 error (_("Infinite loop detected"));
2052 case 0x5: /* data transfer */
2055 if (bit (this_instr
, 20))
2058 if (bits (this_instr
, 12, 15) == 15)
2064 if (bit (this_instr
, 22))
2065 error (_("Invalid update to pc in instruction"));
2067 /* byte write to PC */
2068 rn
= bits (this_instr
, 16, 19);
2069 base
= (rn
== 15) ? pc_val
+ 8
2070 : get_frame_register_unsigned (frame
, rn
);
2071 if (bit (this_instr
, 24))
2074 int c
= (status
& FLAG_C
) ? 1 : 0;
2075 unsigned long offset
=
2076 (bit (this_instr
, 25)
2077 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
2078 : bits (this_instr
, 0, 11));
2080 if (bit (this_instr
, 23))
2085 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
2088 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
2091 error (_("Infinite loop detected"));
2097 case 0x9: /* block transfer */
2098 if (bit (this_instr
, 20))
2101 if (bit (this_instr
, 15))
2106 if (bit (this_instr
, 23))
2109 unsigned long reglist
= bits (this_instr
, 0, 14);
2110 offset
= bitcount (reglist
) * 4;
2111 if (bit (this_instr
, 24)) /* pre */
2114 else if (bit (this_instr
, 24))
2118 unsigned long rn_val
=
2119 get_frame_register_unsigned (frame
,
2120 bits (this_instr
, 16, 19));
2122 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
2126 nextpc
= gdbarch_addr_bits_remove
2129 error (_("Infinite loop detected"));
2134 case 0xb: /* branch & link */
2135 case 0xa: /* branch */
2137 nextpc
= BranchDest (pc
, this_instr
);
2139 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
2141 error (_("Infinite loop detected"));
2147 case 0xe: /* coproc ops */
2152 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
2160 /* single_step() is called just before we want to resume the inferior,
2161 if we want to single-step it but there is no hardware or kernel
2162 single-step support. We find the target of the coming instruction
2163 and breakpoint it. */
2166 arm_software_single_step (struct frame_info
*frame
)
2168 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2170 /* NOTE: This may insert the wrong breakpoint instruction when
2171 single-stepping over a mode-changing instruction, if the
2172 CPSR heuristics are used. */
2174 CORE_ADDR next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
2175 insert_single_step_breakpoint (gdbarch
, next_pc
);
2180 #include "bfd-in2.h"
2181 #include "libcoff.h"
2184 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
2186 if (arm_pc_is_thumb (memaddr
))
2188 static asymbol
*asym
;
2189 static combined_entry_type ce
;
2190 static struct coff_symbol_struct csym
;
2191 static struct bfd fake_bfd
;
2192 static bfd_target fake_target
;
2194 if (csym
.native
== NULL
)
2196 /* Create a fake symbol vector containing a Thumb symbol.
2197 This is solely so that the code in print_insn_little_arm()
2198 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2199 the presence of a Thumb symbol and switch to decoding
2200 Thumb instructions. */
2202 fake_target
.flavour
= bfd_target_coff_flavour
;
2203 fake_bfd
.xvec
= &fake_target
;
2204 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
2206 csym
.symbol
.the_bfd
= &fake_bfd
;
2207 csym
.symbol
.name
= "fake";
2208 asym
= (asymbol
*) & csym
;
2211 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
2212 info
->symbols
= &asym
;
2215 info
->symbols
= NULL
;
2217 if (info
->endian
== BFD_ENDIAN_BIG
)
2218 return print_insn_big_arm (memaddr
, info
);
2220 return print_insn_little_arm (memaddr
, info
);
2223 /* The following define instruction sequences that will cause ARM
2224 cpu's to take an undefined instruction trap. These are used to
2225 signal a breakpoint to GDB.
2227 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2228 modes. A different instruction is required for each mode. The ARM
2229 cpu's can also be big or little endian. Thus four different
2230 instructions are needed to support all cases.
2232 Note: ARMv4 defines several new instructions that will take the
2233 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2234 not in fact add the new instructions. The new undefined
2235 instructions in ARMv4 are all instructions that had no defined
2236 behaviour in earlier chips. There is no guarantee that they will
2237 raise an exception, but may be treated as NOP's. In practice, it
2238 may only safe to rely on instructions matching:
2240 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2241 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2242 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2244 Even this may only true if the condition predicate is true. The
2245 following use a condition predicate of ALWAYS so it is always TRUE.
2247 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2248 and NetBSD all use a software interrupt rather than an undefined
2249 instruction to force a trap. This can be handled by by the
2250 abi-specific code during establishment of the gdbarch vector. */
2252 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2253 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2254 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
2255 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
2257 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
2258 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
2259 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2260 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2262 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2263 the program counter value to determine whether a 16-bit or 32-bit
2264 breakpoint should be used. It returns a pointer to a string of
2265 bytes that encode a breakpoint instruction, stores the length of
2266 the string to *lenptr, and adjusts the program counter (if
2267 necessary) to point to the actual memory location where the
2268 breakpoint should be inserted. */
2270 static const unsigned char *
2271 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
2273 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2275 if (arm_pc_is_thumb (*pcptr
))
2277 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2278 *lenptr
= tdep
->thumb_breakpoint_size
;
2279 return tdep
->thumb_breakpoint
;
2283 *lenptr
= tdep
->arm_breakpoint_size
;
2284 return tdep
->arm_breakpoint
;
2288 /* Extract from an array REGBUF containing the (raw) register state a
2289 function return value of type TYPE, and copy that, in virtual
2290 format, into VALBUF. */
2293 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
2296 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
2297 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2299 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2301 switch (gdbarch_tdep (gdbarch
)->fp_model
)
2305 /* The value is in register F0 in internal format. We need to
2306 extract the raw value and then convert it to the desired
2308 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
2310 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
2311 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
2312 valbuf
, gdbarch_byte_order (gdbarch
));
2316 case ARM_FLOAT_SOFT_FPA
:
2317 case ARM_FLOAT_SOFT_VFP
:
2318 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
2319 if (TYPE_LENGTH (type
) > 4)
2320 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
2321 valbuf
+ INT_REGISTER_SIZE
);
2326 (__FILE__
, __LINE__
,
2327 _("arm_extract_return_value: Floating point model not supported"));
2331 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2332 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2333 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2334 || TYPE_CODE (type
) == TYPE_CODE_PTR
2335 || TYPE_CODE (type
) == TYPE_CODE_REF
2336 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2338 /* If the the type is a plain integer, then the access is
2339 straight-forward. Otherwise we have to play around a bit more. */
2340 int len
= TYPE_LENGTH (type
);
2341 int regno
= ARM_A1_REGNUM
;
2346 /* By using store_unsigned_integer we avoid having to do
2347 anything special for small big-endian values. */
2348 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2349 store_unsigned_integer (valbuf
,
2350 (len
> INT_REGISTER_SIZE
2351 ? INT_REGISTER_SIZE
: len
),
2353 len
-= INT_REGISTER_SIZE
;
2354 valbuf
+= INT_REGISTER_SIZE
;
2359 /* For a structure or union the behaviour is as if the value had
2360 been stored to word-aligned memory and then loaded into
2361 registers with 32-bit load instruction(s). */
2362 int len
= TYPE_LENGTH (type
);
2363 int regno
= ARM_A1_REGNUM
;
2364 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2368 regcache_cooked_read (regs
, regno
++, tmpbuf
);
2369 memcpy (valbuf
, tmpbuf
,
2370 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2371 len
-= INT_REGISTER_SIZE
;
2372 valbuf
+= INT_REGISTER_SIZE
;
2378 /* Will a function return an aggregate type in memory or in a
2379 register? Return 0 if an aggregate type can be returned in a
2380 register, 1 if it must be returned in memory. */
2383 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2386 enum type_code code
;
2388 CHECK_TYPEDEF (type
);
2390 /* In the ARM ABI, "integer" like aggregate types are returned in
2391 registers. For an aggregate type to be integer like, its size
2392 must be less than or equal to INT_REGISTER_SIZE and the
2393 offset of each addressable subfield must be zero. Note that bit
2394 fields are not addressable, and all addressable subfields of
2395 unions always start at offset zero.
2397 This function is based on the behaviour of GCC 2.95.1.
2398 See: gcc/arm.c: arm_return_in_memory() for details.
2400 Note: All versions of GCC before GCC 2.95.2 do not set up the
2401 parameters correctly for a function returning the following
2402 structure: struct { float f;}; This should be returned in memory,
2403 not a register. Richard Earnshaw sent me a patch, but I do not
2404 know of any way to detect if a function like the above has been
2405 compiled with the correct calling convention. */
2407 /* All aggregate types that won't fit in a register must be returned
2409 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
2414 /* The AAPCS says all aggregates not larger than a word are returned
2416 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
2419 /* The only aggregate types that can be returned in a register are
2420 structs and unions. Arrays must be returned in memory. */
2421 code
= TYPE_CODE (type
);
2422 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2427 /* Assume all other aggregate types can be returned in a register.
2428 Run a check for structures, unions and arrays. */
2431 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2434 /* Need to check if this struct/union is "integer" like. For
2435 this to be true, its size must be less than or equal to
2436 INT_REGISTER_SIZE and the offset of each addressable
2437 subfield must be zero. Note that bit fields are not
2438 addressable, and unions always start at offset zero. If any
2439 of the subfields is a floating point type, the struct/union
2440 cannot be an integer type. */
2442 /* For each field in the object, check:
2443 1) Is it FP? --> yes, nRc = 1;
2444 2) Is it addressable (bitpos != 0) and
2445 not packed (bitsize == 0)?
2449 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2451 enum type_code field_type_code
;
2452 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, i
)));
2454 /* Is it a floating point type field? */
2455 if (field_type_code
== TYPE_CODE_FLT
)
2461 /* If bitpos != 0, then we have to care about it. */
2462 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2464 /* Bitfields are not addressable. If the field bitsize is
2465 zero, then the field is not packed. Hence it cannot be
2466 a bitfield or any other packed type. */
2467 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2479 /* Write into appropriate registers a function return value of type
2480 TYPE, given in virtual format. */
2483 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
2484 const gdb_byte
*valbuf
)
2486 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
2487 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2489 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2491 char buf
[MAX_REGISTER_SIZE
];
2493 switch (gdbarch_tdep (gdbarch
)->fp_model
)
2497 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
2498 gdbarch_byte_order (gdbarch
));
2499 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
2502 case ARM_FLOAT_SOFT_FPA
:
2503 case ARM_FLOAT_SOFT_VFP
:
2504 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
2505 if (TYPE_LENGTH (type
) > 4)
2506 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
2507 valbuf
+ INT_REGISTER_SIZE
);
2512 (__FILE__
, __LINE__
,
2513 _("arm_store_return_value: Floating point model not supported"));
2517 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2518 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2519 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2520 || TYPE_CODE (type
) == TYPE_CODE_PTR
2521 || TYPE_CODE (type
) == TYPE_CODE_REF
2522 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2524 if (TYPE_LENGTH (type
) <= 4)
2526 /* Values of one word or less are zero/sign-extended and
2528 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2529 LONGEST val
= unpack_long (type
, valbuf
);
2531 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
2532 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
2536 /* Integral values greater than one word are stored in consecutive
2537 registers starting with r0. This will always be a multiple of
2538 the regiser size. */
2539 int len
= TYPE_LENGTH (type
);
2540 int regno
= ARM_A1_REGNUM
;
2544 regcache_cooked_write (regs
, regno
++, valbuf
);
2545 len
-= INT_REGISTER_SIZE
;
2546 valbuf
+= INT_REGISTER_SIZE
;
2552 /* For a structure or union the behaviour is as if the value had
2553 been stored to word-aligned memory and then loaded into
2554 registers with 32-bit load instruction(s). */
2555 int len
= TYPE_LENGTH (type
);
2556 int regno
= ARM_A1_REGNUM
;
2557 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2561 memcpy (tmpbuf
, valbuf
,
2562 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2563 regcache_cooked_write (regs
, regno
++, tmpbuf
);
2564 len
-= INT_REGISTER_SIZE
;
2565 valbuf
+= INT_REGISTER_SIZE
;
2571 /* Handle function return values. */
2573 static enum return_value_convention
2574 arm_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2575 struct type
*valtype
, struct regcache
*regcache
,
2576 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2578 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2580 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2581 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2582 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2584 if (tdep
->struct_return
== pcc_struct_return
2585 || arm_return_in_memory (gdbarch
, valtype
))
2586 return RETURN_VALUE_STRUCT_CONVENTION
;
2590 arm_store_return_value (valtype
, regcache
, writebuf
);
2593 arm_extract_return_value (valtype
, regcache
, readbuf
);
2595 return RETURN_VALUE_REGISTER_CONVENTION
;
2600 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2602 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2603 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2604 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2606 char buf
[INT_REGISTER_SIZE
];
2608 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
2610 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2614 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
2618 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
2619 return the target PC. Otherwise return 0. */
2622 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
2626 CORE_ADDR start_addr
;
2628 /* Find the starting address and name of the function containing the PC. */
2629 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2632 /* If PC is in a Thumb call or return stub, return the address of the
2633 target PC, which is in a register. The thunk functions are called
2634 _call_via_xx, where x is the register name. The possible names
2635 are r0-r9, sl, fp, ip, sp, and lr. */
2636 if (strncmp (name
, "_call_via_", 10) == 0)
2638 /* Use the name suffix to determine which register contains the
2640 static char *table
[15] =
2641 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2642 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2645 int offset
= strlen (name
) - 2;
2647 for (regno
= 0; regno
<= 14; regno
++)
2648 if (strcmp (&name
[offset
], table
[regno
]) == 0)
2649 return get_frame_register_unsigned (frame
, regno
);
2652 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
2653 non-interworking calls to foo. We could decode the stubs
2654 to find the target but it's easier to use the symbol table. */
2655 namelen
= strlen (name
);
2656 if (name
[0] == '_' && name
[1] == '_'
2657 && ((namelen
> 2 + strlen ("_from_thumb")
2658 && strncmp (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb",
2659 strlen ("_from_thumb")) == 0)
2660 || (namelen
> 2 + strlen ("_from_arm")
2661 && strncmp (name
+ namelen
- strlen ("_from_arm"), "_from_arm",
2662 strlen ("_from_arm")) == 0)))
2665 int target_len
= namelen
- 2;
2666 struct minimal_symbol
*minsym
;
2667 struct objfile
*objfile
;
2668 struct obj_section
*sec
;
2670 if (name
[namelen
- 1] == 'b')
2671 target_len
-= strlen ("_from_thumb");
2673 target_len
-= strlen ("_from_arm");
2675 target_name
= alloca (target_len
+ 1);
2676 memcpy (target_name
, name
+ 2, target_len
);
2677 target_name
[target_len
] = '\0';
2679 sec
= find_pc_section (pc
);
2680 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
2681 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
2683 return SYMBOL_VALUE_ADDRESS (minsym
);
2688 return 0; /* not a stub */
2692 set_arm_command (char *args
, int from_tty
)
2694 printf_unfiltered (_("\
2695 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2696 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
2700 show_arm_command (char *args
, int from_tty
)
2702 cmd_show_list (showarmcmdlist
, from_tty
, "");
2706 arm_update_current_architecture (void)
2708 struct gdbarch_info info
;
2710 /* If the current architecture is not ARM, we have nothing to do. */
2711 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_arm
)
2714 /* Update the architecture. */
2715 gdbarch_info_init (&info
);
2717 if (!gdbarch_update_p (info
))
2718 internal_error (__FILE__
, __LINE__
, "could not update architecture");
2722 set_fp_model_sfunc (char *args
, int from_tty
,
2723 struct cmd_list_element
*c
)
2725 enum arm_float_model fp_model
;
2727 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
2728 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
2730 arm_fp_model
= fp_model
;
2734 if (fp_model
== ARM_FLOAT_LAST
)
2735 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
2738 arm_update_current_architecture ();
2742 show_fp_model (struct ui_file
*file
, int from_tty
,
2743 struct cmd_list_element
*c
, const char *value
)
2745 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
2747 if (arm_fp_model
== ARM_FLOAT_AUTO
2748 && gdbarch_bfd_arch_info (target_gdbarch
)->arch
== bfd_arch_arm
)
2749 fprintf_filtered (file
, _("\
2750 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2751 fp_model_strings
[tdep
->fp_model
]);
2753 fprintf_filtered (file
, _("\
2754 The current ARM floating point model is \"%s\".\n"),
2755 fp_model_strings
[arm_fp_model
]);
2759 arm_set_abi (char *args
, int from_tty
,
2760 struct cmd_list_element
*c
)
2762 enum arm_abi_kind arm_abi
;
2764 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
2765 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
2767 arm_abi_global
= arm_abi
;
2771 if (arm_abi
== ARM_ABI_LAST
)
2772 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
2775 arm_update_current_architecture ();
2779 arm_show_abi (struct ui_file
*file
, int from_tty
,
2780 struct cmd_list_element
*c
, const char *value
)
2782 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
2784 if (arm_abi_global
== ARM_ABI_AUTO
2785 && gdbarch_bfd_arch_info (target_gdbarch
)->arch
== bfd_arch_arm
)
2786 fprintf_filtered (file
, _("\
2787 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2788 arm_abi_strings
[tdep
->arm_abi
]);
2790 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
2795 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
2796 struct cmd_list_element
*c
, const char *value
)
2798 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
2800 fprintf_filtered (file
, _("\
2801 The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"),
2802 arm_fallback_mode_string
);
2806 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
2807 struct cmd_list_element
*c
, const char *value
)
2809 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
2811 fprintf_filtered (file
, _("\
2812 The current execution mode assumed (even when symbols are available) is \"%s\".\n"),
2813 arm_force_mode_string
);
2816 /* If the user changes the register disassembly style used for info
2817 register and other commands, we have to also switch the style used
2818 in opcodes for disassembly output. This function is run in the "set
2819 arm disassembly" command, and does that. */
2822 set_disassembly_style_sfunc (char *args
, int from_tty
,
2823 struct cmd_list_element
*c
)
2825 set_disassembly_style ();
2828 /* Return the ARM register name corresponding to register I. */
2830 arm_register_name (struct gdbarch
*gdbarch
, int i
)
2832 if (i
>= ARRAY_SIZE (arm_register_names
))
2833 /* These registers are only supported on targets which supply
2834 an XML description. */
2837 return arm_register_names
[i
];
2841 set_disassembly_style (void)
2845 /* Find the style that the user wants. */
2846 for (current
= 0; current
< num_disassembly_options
; current
++)
2847 if (disassembly_style
== valid_disassembly_styles
[current
])
2849 gdb_assert (current
< num_disassembly_options
);
2851 /* Synchronize the disassembler. */
2852 set_arm_regname_option (current
);
2855 /* Test whether the coff symbol specific value corresponds to a Thumb
2859 coff_sym_is_thumb (int val
)
2861 return (val
== C_THUMBEXT
||
2862 val
== C_THUMBSTAT
||
2863 val
== C_THUMBEXTFUNC
||
2864 val
== C_THUMBSTATFUNC
||
2865 val
== C_THUMBLABEL
);
2868 /* arm_coff_make_msymbol_special()
2869 arm_elf_make_msymbol_special()
2871 These functions test whether the COFF or ELF symbol corresponds to
2872 an address in thumb code, and set a "special" bit in a minimal
2873 symbol to indicate that it does. */
2876 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2878 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2880 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2882 MSYMBOL_SET_SPECIAL (msym
);
2886 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2888 if (coff_sym_is_thumb (val
))
2889 MSYMBOL_SET_SPECIAL (msym
);
2893 arm_objfile_data_cleanup (struct objfile
*objfile
, void *arg
)
2895 struct arm_per_objfile
*data
= arg
;
2898 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
2899 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
2903 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
2906 const char *name
= bfd_asymbol_name (sym
);
2907 struct arm_per_objfile
*data
;
2908 VEC(arm_mapping_symbol_s
) **map_p
;
2909 struct arm_mapping_symbol new_map_sym
;
2911 gdb_assert (name
[0] == '$');
2912 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
2915 data
= objfile_data (objfile
, arm_objfile_data_key
);
2918 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
2919 struct arm_per_objfile
);
2920 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
2921 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2922 objfile
->obfd
->section_count
,
2923 VEC(arm_mapping_symbol_s
) *);
2925 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
2927 new_map_sym
.value
= sym
->value
;
2928 new_map_sym
.type
= name
[1];
2930 /* Assume that most mapping symbols appear in order of increasing
2931 value. If they were randomly distributed, it would be faster to
2932 always push here and then sort at first use. */
2933 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
2935 struct arm_mapping_symbol
*prev_map_sym
;
2937 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
2938 if (prev_map_sym
->value
>= sym
->value
)
2941 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
2942 arm_compare_mapping_symbols
);
2943 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
2948 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
2952 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2954 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
2956 /* If necessary, set the T bit. */
2960 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
2961 if (arm_pc_is_thumb (pc
))
2962 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
, val
| CPSR_T
);
2964 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
2965 val
& ~(ULONGEST
) CPSR_T
);
2969 static struct value
*
2970 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
2972 const int *reg_p
= baton
;
2973 return value_of_register (*reg_p
, frame
);
2976 static enum gdb_osabi
2977 arm_elf_osabi_sniffer (bfd
*abfd
)
2979 unsigned int elfosabi
;
2980 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2982 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2984 if (elfosabi
== ELFOSABI_ARM
)
2985 /* GNU tools use this value. Check note sections in this case,
2987 bfd_map_over_sections (abfd
,
2988 generic_elf_osabi_sniff_abi_tag_sections
,
2991 /* Anything else will be handled by the generic ELF sniffer. */
2996 /* Initialize the current architecture based on INFO. If possible,
2997 re-use an architecture from ARCHES, which is a list of
2998 architectures already created during this debugging session.
3000 Called e.g. at program startup, when reading a core file, and when
3001 reading a binary file. */
3003 static struct gdbarch
*
3004 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3006 struct gdbarch_tdep
*tdep
;
3007 struct gdbarch
*gdbarch
;
3008 struct gdbarch_list
*best_arch
;
3009 enum arm_abi_kind arm_abi
= arm_abi_global
;
3010 enum arm_float_model fp_model
= arm_fp_model
;
3011 struct tdesc_arch_data
*tdesc_data
= NULL
;
3013 int have_fpa_registers
= 1;
3015 /* Check any target description for validity. */
3016 if (tdesc_has_registers (info
.target_desc
))
3018 /* For most registers we require GDB's default names; but also allow
3019 the numeric names for sp / lr / pc, as a convenience. */
3020 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
3021 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
3022 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
3024 const struct tdesc_feature
*feature
;
3027 feature
= tdesc_find_feature (info
.target_desc
,
3028 "org.gnu.gdb.arm.core");
3029 if (feature
== NULL
)
3032 tdesc_data
= tdesc_data_alloc ();
3035 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
3036 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
3037 arm_register_names
[i
]);
3038 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
3041 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
3044 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
3047 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3048 ARM_PS_REGNUM
, "cpsr");
3052 tdesc_data_cleanup (tdesc_data
);
3056 feature
= tdesc_find_feature (info
.target_desc
,
3057 "org.gnu.gdb.arm.fpa");
3058 if (feature
!= NULL
)
3061 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
3062 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
3063 arm_register_names
[i
]);
3066 tdesc_data_cleanup (tdesc_data
);
3071 have_fpa_registers
= 0;
3073 feature
= tdesc_find_feature (info
.target_desc
,
3074 "org.gnu.gdb.xscale.iwmmxt");
3075 if (feature
!= NULL
)
3077 static const char *const iwmmxt_names
[] = {
3078 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
3079 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
3080 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
3081 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
3085 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
3087 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
3088 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
3090 /* Check for the control registers, but do not fail if they
3092 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
3093 tdesc_numbered_register (feature
, tdesc_data
, i
,
3094 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
3096 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
3098 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
3099 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
3103 tdesc_data_cleanup (tdesc_data
);
3109 /* If we have an object to base this architecture on, try to determine
3112 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
3114 int ei_osabi
, e_flags
;
3116 switch (bfd_get_flavour (info
.abfd
))
3118 case bfd_target_aout_flavour
:
3119 /* Assume it's an old APCS-style ABI. */
3120 arm_abi
= ARM_ABI_APCS
;
3123 case bfd_target_coff_flavour
:
3124 /* Assume it's an old APCS-style ABI. */
3126 arm_abi
= ARM_ABI_APCS
;
3129 case bfd_target_elf_flavour
:
3130 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
3131 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
3133 if (ei_osabi
== ELFOSABI_ARM
)
3135 /* GNU tools used to use this value, but do not for EABI
3136 objects. There's nowhere to tag an EABI version
3137 anyway, so assume APCS. */
3138 arm_abi
= ARM_ABI_APCS
;
3140 else if (ei_osabi
== ELFOSABI_NONE
)
3142 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
3146 case EF_ARM_EABI_UNKNOWN
:
3147 /* Assume GNU tools. */
3148 arm_abi
= ARM_ABI_APCS
;
3151 case EF_ARM_EABI_VER4
:
3152 case EF_ARM_EABI_VER5
:
3153 arm_abi
= ARM_ABI_AAPCS
;
3154 /* EABI binaries default to VFP float ordering. */
3155 if (fp_model
== ARM_FLOAT_AUTO
)
3156 fp_model
= ARM_FLOAT_SOFT_VFP
;
3160 /* Leave it as "auto". */
3161 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
3166 if (fp_model
== ARM_FLOAT_AUTO
)
3168 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
3170 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
3173 /* Leave it as "auto". Strictly speaking this case
3174 means FPA, but almost nobody uses that now, and
3175 many toolchains fail to set the appropriate bits
3176 for the floating-point model they use. */
3178 case EF_ARM_SOFT_FLOAT
:
3179 fp_model
= ARM_FLOAT_SOFT_FPA
;
3181 case EF_ARM_VFP_FLOAT
:
3182 fp_model
= ARM_FLOAT_VFP
;
3184 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
3185 fp_model
= ARM_FLOAT_SOFT_VFP
;
3190 if (e_flags
& EF_ARM_BE8
)
3191 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
3196 /* Leave it as "auto". */
3201 /* If there is already a candidate, use it. */
3202 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
3204 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
3206 if (arm_abi
!= ARM_ABI_AUTO
3207 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
3210 if (fp_model
!= ARM_FLOAT_AUTO
3211 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
3214 /* Found a match. */
3218 if (best_arch
!= NULL
)
3220 if (tdesc_data
!= NULL
)
3221 tdesc_data_cleanup (tdesc_data
);
3222 return best_arch
->gdbarch
;
3225 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
3226 gdbarch
= gdbarch_alloc (&info
, tdep
);
3228 /* Record additional information about the architecture we are defining.
3229 These are gdbarch discriminators, like the OSABI. */
3230 tdep
->arm_abi
= arm_abi
;
3231 tdep
->fp_model
= fp_model
;
3232 tdep
->have_fpa_registers
= have_fpa_registers
;
3235 switch (info
.byte_order_for_code
)
3237 case BFD_ENDIAN_BIG
:
3238 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
3239 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
3240 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
3241 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
3245 case BFD_ENDIAN_LITTLE
:
3246 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
3247 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
3248 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
3249 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
3254 internal_error (__FILE__
, __LINE__
,
3255 _("arm_gdbarch_init: bad byte order for float format"));
3258 /* On ARM targets char defaults to unsigned. */
3259 set_gdbarch_char_signed (gdbarch
, 0);
3261 /* This should be low enough for everything. */
3262 tdep
->lowest_pc
= 0x20;
3263 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
3265 /* The default, for both APCS and AAPCS, is to return small
3266 structures in registers. */
3267 tdep
->struct_return
= reg_struct_return
;
3269 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
3270 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
3272 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
3274 /* Frame handling. */
3275 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
3276 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
3277 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
3279 frame_base_set_default (gdbarch
, &arm_normal_base
);
3281 /* Address manipulation. */
3282 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
3283 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
3285 /* Advance PC across function entry code. */
3286 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
3288 /* Skip trampolines. */
3289 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
3291 /* The stack grows downward. */
3292 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3294 /* Breakpoint manipulation. */
3295 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
3297 /* Information about registers, etc. */
3298 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
3299 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
3300 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
3301 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
3302 set_gdbarch_register_type (gdbarch
, arm_register_type
);
3304 /* This "info float" is FPA-specific. Use the generic version if we
3306 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
3307 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
3309 /* Internal <-> external register number maps. */
3310 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
3311 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
3313 set_gdbarch_register_name (gdbarch
, arm_register_name
);
3315 /* Returning results. */
3316 set_gdbarch_return_value (gdbarch
, arm_return_value
);
3319 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
3321 /* Minsymbol frobbing. */
3322 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
3323 set_gdbarch_coff_make_msymbol_special (gdbarch
,
3324 arm_coff_make_msymbol_special
);
3325 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
3327 /* Virtual tables. */
3328 set_gdbarch_vbit_in_delta (gdbarch
, 1);
3330 /* Hook in the ABI-specific overrides, if they have been registered. */
3331 gdbarch_init_osabi (info
, gdbarch
);
3333 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
3335 /* Add some default predicates. */
3336 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
3337 dwarf2_append_unwinders (gdbarch
);
3338 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
3340 /* Now we have tuned the configuration, set a few final things,
3341 based on what the OS ABI has told us. */
3343 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
3344 binaries are always marked. */
3345 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
3346 tdep
->arm_abi
= ARM_ABI_APCS
;
3348 /* We used to default to FPA for generic ARM, but almost nobody
3349 uses that now, and we now provide a way for the user to force
3350 the model. So default to the most useful variant. */
3351 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
3352 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
3354 if (tdep
->jb_pc
>= 0)
3355 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
3357 /* Floating point sizes and format. */
3358 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
3359 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
3361 set_gdbarch_double_format
3362 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
3363 set_gdbarch_long_double_format
3364 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
3368 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
3369 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
3373 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
3375 /* Add standard register aliases. We add aliases even for those
3376 nanes which are used by the current architecture - it's simpler,
3377 and does no harm, since nothing ever lists user registers. */
3378 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
3379 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
3380 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
3386 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3388 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3393 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
3394 (unsigned long) tdep
->lowest_pc
);
3397 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
3400 _initialize_arm_tdep (void)
3402 struct ui_file
*stb
;
3404 struct cmd_list_element
*new_set
, *new_show
;
3405 const char *setname
;
3406 const char *setdesc
;
3407 const char *const *regnames
;
3409 static char *helptext
;
3410 char regdesc
[1024], *rdptr
= regdesc
;
3411 size_t rest
= sizeof (regdesc
);
3413 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
3415 arm_objfile_data_key
3416 = register_objfile_data_with_cleanup (arm_objfile_data_cleanup
);
3418 /* Register an ELF OS ABI sniffer for ARM binaries. */
3419 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
3420 bfd_target_elf_flavour
,
3421 arm_elf_osabi_sniffer
);
3423 /* Get the number of possible sets of register names defined in opcodes. */
3424 num_disassembly_options
= get_arm_regname_num_options ();
3426 /* Add root prefix command for all "set arm"/"show arm" commands. */
3427 add_prefix_cmd ("arm", no_class
, set_arm_command
,
3428 _("Various ARM-specific commands."),
3429 &setarmcmdlist
, "set arm ", 0, &setlist
);
3431 add_prefix_cmd ("arm", no_class
, show_arm_command
,
3432 _("Various ARM-specific commands."),
3433 &showarmcmdlist
, "show arm ", 0, &showlist
);
3435 /* Sync the opcode insn printer with our register viewer. */
3436 parse_arm_disassembler_option ("reg-names-std");
3438 /* Initialize the array that will be passed to
3439 add_setshow_enum_cmd(). */
3440 valid_disassembly_styles
3441 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
3442 for (i
= 0; i
< num_disassembly_options
; i
++)
3444 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
3445 valid_disassembly_styles
[i
] = setname
;
3446 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
3449 /* When we find the default names, tell the disassembler to use
3451 if (!strcmp (setname
, "std"))
3453 disassembly_style
= setname
;
3454 set_arm_regname_option (i
);
3457 /* Mark the end of valid options. */
3458 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
3460 /* Create the help text. */
3461 stb
= mem_fileopen ();
3462 fprintf_unfiltered (stb
, "%s%s%s",
3463 _("The valid values are:\n"),
3465 _("The default is \"std\"."));
3466 helptext
= ui_file_xstrdup (stb
, &length
);
3467 ui_file_delete (stb
);
3469 add_setshow_enum_cmd("disassembler", no_class
,
3470 valid_disassembly_styles
, &disassembly_style
,
3471 _("Set the disassembly style."),
3472 _("Show the disassembly style."),
3474 set_disassembly_style_sfunc
,
3475 NULL
, /* FIXME: i18n: The disassembly style is \"%s\". */
3476 &setarmcmdlist
, &showarmcmdlist
);
3478 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
3479 _("Set usage of ARM 32-bit mode."),
3480 _("Show usage of ARM 32-bit mode."),
3481 _("When off, a 26-bit PC will be used."),
3483 NULL
, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
3484 &setarmcmdlist
, &showarmcmdlist
);
3486 /* Add a command to allow the user to force the FPU model. */
3487 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
3488 _("Set the floating point type."),
3489 _("Show the floating point type."),
3490 _("auto - Determine the FP typefrom the OS-ABI.\n\
3491 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
3492 fpa - FPA co-processor (GCC compiled).\n\
3493 softvfp - Software FP with pure-endian doubles.\n\
3494 vfp - VFP co-processor."),
3495 set_fp_model_sfunc
, show_fp_model
,
3496 &setarmcmdlist
, &showarmcmdlist
);
3498 /* Add a command to allow the user to force the ABI. */
3499 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
3502 NULL
, arm_set_abi
, arm_show_abi
,
3503 &setarmcmdlist
, &showarmcmdlist
);
3505 /* Add two commands to allow the user to force the assumed
3507 add_setshow_enum_cmd ("fallback-mode", class_support
,
3508 arm_mode_strings
, &arm_fallback_mode_string
,
3509 _("Set the mode assumed when symbols are unavailable."),
3510 _("Show the mode assumed when symbols are unavailable."),
3511 NULL
, NULL
, arm_show_fallback_mode
,
3512 &setarmcmdlist
, &showarmcmdlist
);
3513 add_setshow_enum_cmd ("force-mode", class_support
,
3514 arm_mode_strings
, &arm_force_mode_string
,
3515 _("Set the mode assumed even when symbols are available."),
3516 _("Show the mode assumed even when symbols are available."),
3517 NULL
, NULL
, arm_show_force_mode
,
3518 &setarmcmdlist
, &showarmcmdlist
);
3520 /* Debugging flag. */
3521 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
3522 _("Set ARM debugging."),
3523 _("Show ARM debugging."),
3524 _("When on, arm-specific debugging is enabled."),
3526 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
3527 &setdebuglist
, &showdebuglist
);