1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper () */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
43 #include "target-descriptions.h"
44 #include "user-regs.h"
47 #include "gdb/sim-arm.h"
50 #include "coff/internal.h"
53 #include "gdb_assert.h"
56 #include "features/arm-with-m.c"
60 /* Macros for setting and testing a bit in a minimal symbol that marks
61 it as Thumb function. The MSB of the minimal symbol's "info" field
62 is used for this purpose.
64 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
65 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
67 #define MSYMBOL_SET_SPECIAL(msym) \
68 MSYMBOL_TARGET_FLAG_1 (msym) = 1
70 #define MSYMBOL_IS_SPECIAL(msym) \
71 MSYMBOL_TARGET_FLAG_1 (msym)
73 /* Per-objfile data used for mapping symbols. */
74 static const struct objfile_data
*arm_objfile_data_key
;
76 struct arm_mapping_symbol
81 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
82 DEF_VEC_O(arm_mapping_symbol_s
);
84 struct arm_per_objfile
86 VEC(arm_mapping_symbol_s
) **section_maps
;
89 /* The list of available "set arm ..." and "show arm ..." commands. */
90 static struct cmd_list_element
*setarmcmdlist
= NULL
;
91 static struct cmd_list_element
*showarmcmdlist
= NULL
;
93 /* The type of floating-point to use. Keep this in sync with enum
94 arm_float_model, and the help string in _initialize_arm_tdep. */
95 static const char *fp_model_strings
[] =
105 /* A variable that can be configured by the user. */
106 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
107 static const char *current_fp_model
= "auto";
109 /* The ABI to use. Keep this in sync with arm_abi_kind. */
110 static const char *arm_abi_strings
[] =
118 /* A variable that can be configured by the user. */
119 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
120 static const char *arm_abi_string
= "auto";
122 /* The execution mode to assume. */
123 static const char *arm_mode_strings
[] =
130 static const char *arm_fallback_mode_string
= "auto";
131 static const char *arm_force_mode_string
= "auto";
133 /* Number of different reg name sets (options). */
134 static int num_disassembly_options
;
136 /* The standard register names, and all the valid aliases for them. */
141 } arm_register_aliases
[] = {
142 /* Basic register numbers. */
159 /* Synonyms (argument and variable registers). */
172 /* Other platform-specific names for r9. */
180 /* Names used by GCC (not listed in the ARM EABI). */
183 /* A special name from the older ATPCS. */
187 static const char *const arm_register_names
[] =
188 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
189 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
190 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
191 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
192 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
193 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
194 "fps", "cpsr" }; /* 24 25 */
196 /* Valid register name styles. */
197 static const char **valid_disassembly_styles
;
199 /* Disassembly style to use. Default to "std" register names. */
200 static const char *disassembly_style
;
202 /* This is used to keep the bfd arch_info in sync with the disassembly
204 static void set_disassembly_style_sfunc(char *, int,
205 struct cmd_list_element
*);
206 static void set_disassembly_style (void);
208 static void convert_from_extended (const struct floatformat
*, const void *,
210 static void convert_to_extended (const struct floatformat
*, void *,
213 static void arm_neon_quad_read (struct gdbarch
*gdbarch
,
214 struct regcache
*regcache
,
215 int regnum
, gdb_byte
*buf
);
216 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
217 struct regcache
*regcache
,
218 int regnum
, const gdb_byte
*buf
);
220 struct arm_prologue_cache
222 /* The stack pointer at the time this frame was created; i.e. the
223 caller's stack pointer when this function was called. It is used
224 to identify this frame. */
227 /* The frame base for this frame is just prev_sp - frame size.
228 FRAMESIZE is the distance from the frame pointer to the
229 initial stack pointer. */
233 /* The register used to hold the frame pointer for this frame. */
236 /* Saved register offsets. */
237 struct trad_frame_saved_reg
*saved_regs
;
240 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
241 CORE_ADDR prologue_start
,
242 CORE_ADDR prologue_end
,
243 struct arm_prologue_cache
*cache
);
245 /* Architecture version for displaced stepping. This effects the behaviour of
246 certain instructions, and really should not be hard-wired. */
248 #define DISPLACED_STEPPING_ARCH_VERSION 5
250 /* Addresses for calling Thumb functions have the bit 0 set.
251 Here are some macros to test, set, or clear bit 0 of addresses. */
252 #define IS_THUMB_ADDR(addr) ((addr) & 1)
253 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
254 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
256 /* Set to true if the 32-bit mode is in use. */
260 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
263 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
265 if (gdbarch_tdep (gdbarch
)->is_m
)
271 /* Determine if FRAME is executing in Thumb mode. */
274 arm_frame_is_thumb (struct frame_info
*frame
)
277 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
279 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
280 directly (from a signal frame or dummy frame) or by interpreting
281 the saved LR (from a prologue or DWARF frame). So consult it and
282 trust the unwinders. */
283 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
285 return (cpsr
& t_bit
) != 0;
288 /* Callback for VEC_lower_bound. */
291 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
292 const struct arm_mapping_symbol
*rhs
)
294 return lhs
->value
< rhs
->value
;
297 /* Search for the mapping symbol covering MEMADDR. If one is found,
298 return its type. Otherwise, return 0. If START is non-NULL,
299 set *START to the location of the mapping symbol. */
302 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
304 struct obj_section
*sec
;
306 /* If there are mapping symbols, consult them. */
307 sec
= find_pc_section (memaddr
);
310 struct arm_per_objfile
*data
;
311 VEC(arm_mapping_symbol_s
) *map
;
312 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
316 data
= objfile_data (sec
->objfile
, arm_objfile_data_key
);
319 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
320 if (!VEC_empty (arm_mapping_symbol_s
, map
))
322 struct arm_mapping_symbol
*map_sym
;
324 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
325 arm_compare_mapping_symbols
);
327 /* VEC_lower_bound finds the earliest ordered insertion
328 point. If the following symbol starts at this exact
329 address, we use that; otherwise, the preceding
330 mapping symbol covers this address. */
331 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
333 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
334 if (map_sym
->value
== map_key
.value
)
337 *start
= map_sym
->value
+ obj_section_addr (sec
);
338 return map_sym
->type
;
344 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
346 *start
= map_sym
->value
+ obj_section_addr (sec
);
347 return map_sym
->type
;
356 static CORE_ADDR
arm_get_next_pc_raw (struct frame_info
*frame
,
357 CORE_ADDR pc
, int insert_bkpt
);
359 /* Determine if the program counter specified in MEMADDR is in a Thumb
360 function. This function should be called for addresses unrelated to
361 any executing frame; otherwise, prefer arm_frame_is_thumb. */
364 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
366 struct obj_section
*sec
;
367 struct minimal_symbol
*sym
;
370 /* If bit 0 of the address is set, assume this is a Thumb address. */
371 if (IS_THUMB_ADDR (memaddr
))
374 /* If the user wants to override the symbol table, let him. */
375 if (strcmp (arm_force_mode_string
, "arm") == 0)
377 if (strcmp (arm_force_mode_string
, "thumb") == 0)
380 /* ARM v6-M and v7-M are always in Thumb mode. */
381 if (gdbarch_tdep (gdbarch
)->is_m
)
384 /* If there are mapping symbols, consult them. */
385 type
= arm_find_mapping_symbol (memaddr
, NULL
);
389 /* Thumb functions have a "special" bit set in minimal symbols. */
390 sym
= lookup_minimal_symbol_by_pc (memaddr
);
392 return (MSYMBOL_IS_SPECIAL (sym
));
394 /* If the user wants to override the fallback mode, let them. */
395 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
397 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
400 /* If we couldn't find any symbol, but we're talking to a running
401 target, then trust the current value of $cpsr. This lets
402 "display/i $pc" always show the correct mode (though if there is
403 a symbol table we will not reach here, so it still may not be
404 displayed in the mode it will be executed).
406 As a further heuristic if we detect that we are doing a single-step we
407 see what state executing the current instruction ends up with us being
409 if (target_has_registers
)
411 struct frame_info
*current_frame
= get_current_frame ();
412 CORE_ADDR current_pc
= get_frame_pc (current_frame
);
413 int is_thumb
= arm_frame_is_thumb (current_frame
);
415 if (memaddr
== current_pc
)
419 struct gdbarch
*gdbarch
= get_frame_arch (current_frame
);
420 next_pc
= arm_get_next_pc_raw (current_frame
, current_pc
, FALSE
);
421 if (memaddr
== gdbarch_addr_bits_remove (gdbarch
, next_pc
))
422 return IS_THUMB_ADDR (next_pc
);
428 /* Otherwise we're out of luck; we assume ARM. */
432 /* Remove useless bits from addresses in a running program. */
434 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
437 return UNMAKE_THUMB_ADDR (val
);
439 return (val
& 0x03fffffc);
442 /* When reading symbols, we need to zap the low bit of the address,
443 which may be set to 1 for Thumb functions. */
445 arm_smash_text_address (struct gdbarch
*gdbarch
, CORE_ADDR val
)
450 /* Return 1 if PC is the start of a compiler helper function which
451 can be safely ignored during prologue skipping. */
453 skip_prologue_function (CORE_ADDR pc
)
455 struct minimal_symbol
*msym
;
458 msym
= lookup_minimal_symbol_by_pc (pc
);
459 if (msym
== NULL
|| SYMBOL_VALUE_ADDRESS (msym
) != pc
)
462 name
= SYMBOL_LINKAGE_NAME (msym
);
466 /* The GNU linker's Thumb call stub to foo is named
468 if (strstr (name
, "_from_thumb") != NULL
)
471 /* On soft-float targets, __truncdfsf2 is called to convert promoted
472 arguments to their argument types in non-prototyped
474 if (strncmp (name
, "__truncdfsf2", strlen ("__truncdfsf2")) == 0)
476 if (strncmp (name
, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
482 /* Support routines for instruction parsing. */
483 #define submask(x) ((1L << ((x) + 1)) - 1)
484 #define bit(obj,st) (((obj) >> (st)) & 1)
485 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
486 #define sbits(obj,st,fn) \
487 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
488 #define BranchDest(addr,instr) \
489 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
491 /* Analyze a Thumb prologue, looking for a recognizable stack frame
492 and frame pointer. Scan until we encounter a store that could
493 clobber the stack frame unexpectedly, or an unknown instruction.
494 Return the last address which is definitely safe to skip for an
495 initial breakpoint. */
498 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
499 CORE_ADDR start
, CORE_ADDR limit
,
500 struct arm_prologue_cache
*cache
)
502 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
503 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
506 struct pv_area
*stack
;
507 struct cleanup
*back_to
;
510 for (i
= 0; i
< 16; i
++)
511 regs
[i
] = pv_register (i
, 0);
512 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
513 back_to
= make_cleanup_free_pv_area (stack
);
515 while (start
< limit
)
519 insn
= read_memory_unsigned_integer (start
, 2, byte_order_for_code
);
521 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
526 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
529 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
530 whether to save LR (R14). */
531 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
533 /* Calculate offsets of saved R0-R7 and LR. */
534 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
535 if (mask
& (1 << regno
))
537 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
539 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
542 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
545 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
546 if (insn
& 0x80) /* Check for SUB. */
547 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
550 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
553 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
554 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
556 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
557 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
558 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
560 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
561 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
562 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
564 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
565 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
566 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
567 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
568 regs
[bits (insn
, 6, 8)]);
569 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
570 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
572 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
573 int rm
= bits (insn
, 3, 6);
574 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
576 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
578 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
579 int src_reg
= (insn
& 0x78) >> 3;
580 regs
[dst_reg
] = regs
[src_reg
];
582 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
584 /* Handle stores to the stack. Normally pushes are used,
585 but with GCC -mtpcs-frame, there may be other stores
586 in the prologue to create the frame. */
587 int regno
= (insn
>> 8) & 0x7;
590 offset
= (insn
& 0xff) << 2;
591 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
593 if (pv_area_store_would_trash (stack
, addr
))
596 pv_area_store (stack
, addr
, 4, regs
[regno
]);
598 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
600 int rd
= bits (insn
, 0, 2);
601 int rn
= bits (insn
, 3, 5);
604 offset
= bits (insn
, 6, 10) << 2;
605 addr
= pv_add_constant (regs
[rn
], offset
);
607 if (pv_area_store_would_trash (stack
, addr
))
610 pv_area_store (stack
, addr
, 4, regs
[rd
]);
612 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
613 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
614 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
615 /* Ignore stores of argument registers to the stack. */
617 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
618 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
619 /* Ignore block loads from the stack, potentially copying
620 parameters from memory. */
622 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
623 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
624 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
625 /* Similarly ignore single loads from the stack. */
627 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
628 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
629 /* Skip register copies, i.e. saves to another register
630 instead of the stack. */
632 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
633 /* Recognize constant loads; even with small stacks these are necessary
635 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
636 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
638 /* Constant pool loads, for the same reason. */
639 unsigned int constant
;
642 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
643 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
644 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
646 else if ((insn
& 0xe000) == 0xe000 && cache
== NULL
)
648 /* Only recognize 32-bit instructions for prologue skipping. */
649 unsigned short inst2
;
651 inst2
= read_memory_unsigned_integer (start
+ 2, 2,
652 byte_order_for_code
);
654 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
656 /* BL, BLX. Allow some special function calls when
657 skipping the prologue; GCC generates these before
658 storing arguments to the stack. */
660 int j1
, j2
, imm1
, imm2
;
662 imm1
= sbits (insn
, 0, 10);
663 imm2
= bits (inst2
, 0, 10);
664 j1
= bit (inst2
, 13);
665 j2
= bit (inst2
, 11);
667 offset
= ((imm1
<< 12) + (imm2
<< 1));
668 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
670 nextpc
= start
+ 4 + offset
;
671 /* For BLX make sure to clear the low bits. */
672 if (bit (inst2
, 12) == 0)
673 nextpc
= nextpc
& 0xfffffffc;
675 if (!skip_prologue_function (nextpc
))
678 else if ((insn
& 0xfe50) == 0xe800 /* stm{db,ia} Rn[!], { registers } */
679 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
681 else if ((insn
& 0xfe50) == 0xe840 /* strd Rt, Rt2, [Rn, #imm] */
682 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
684 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!], { registers } */
685 && (inst2
& 0x8000) == 0x0000
686 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
688 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
689 && (inst2
& 0x8000) == 0x0000)
690 /* Since we only recognize this for prologue skipping, do not bother
691 to compute the constant. */
692 regs
[bits (inst2
, 8, 11)] = regs
[bits (insn
, 0, 3)];
693 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm12 */
694 && (inst2
& 0x8000) == 0x0000)
695 /* Since we only recognize this for prologue skipping, do not bother
696 to compute the constant. */
697 regs
[bits (inst2
, 8, 11)] = regs
[bits (insn
, 0, 3)];
698 else if ((insn
& 0xfbf0) == 0xf2a0 /* sub.w Rd, Rn, #imm8 */
699 && (inst2
& 0x8000) == 0x0000)
700 /* Since we only recognize this for prologue skipping, do not bother
701 to compute the constant. */
702 regs
[bits (inst2
, 8, 11)] = regs
[bits (insn
, 0, 3)];
703 else if ((insn
& 0xff50) == 0xf850 /* ldr.w Rd, [Rn, #imm]{!} */
704 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
706 else if ((insn
& 0xff50) == 0xe950 /* ldrd Rt, Rt2, [Rn, #imm]{!} */
707 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
709 else if ((insn
& 0xff50) == 0xf800 /* strb.w or strh.w */
710 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
714 /* We don't know what this instruction is. We're finished
715 scanning. NOTE: Recognizing more safe-to-ignore
716 instructions here will improve support for optimized
725 /* We don't know what this instruction is. We're finished
726 scanning. NOTE: Recognizing more safe-to-ignore
727 instructions here will improve support for optimized
736 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
737 paddress (gdbarch
, start
));
741 do_cleanups (back_to
);
745 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
747 /* Frame pointer is fp. Frame size is constant. */
748 cache
->framereg
= ARM_FP_REGNUM
;
749 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
751 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
753 /* Frame pointer is r7. Frame size is constant. */
754 cache
->framereg
= THUMB_FP_REGNUM
;
755 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
757 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
759 /* Try the stack pointer... this is a bit desperate. */
760 cache
->framereg
= ARM_SP_REGNUM
;
761 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
765 /* We're just out of luck. We don't know where the frame is. */
766 cache
->framereg
= -1;
767 cache
->framesize
= 0;
770 for (i
= 0; i
< 16; i
++)
771 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
772 cache
->saved_regs
[i
].addr
= offset
;
774 do_cleanups (back_to
);
778 /* Advance the PC across any function entry prologue instructions to
779 reach some "real" code.
781 The APCS (ARM Procedure Call Standard) defines the following
785 [stmfd sp!, {a1,a2,a3,a4}]
786 stmfd sp!, {...,fp,ip,lr,pc}
787 [stfe f7, [sp, #-12]!]
788 [stfe f6, [sp, #-12]!]
789 [stfe f5, [sp, #-12]!]
790 [stfe f4, [sp, #-12]!]
791 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
794 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
796 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
799 CORE_ADDR func_addr
, limit_pc
;
800 struct symtab_and_line sal
;
802 /* See if we can determine the end of the prologue via the symbol table.
803 If so, then return either PC, or the PC after the prologue, whichever
805 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
807 CORE_ADDR post_prologue_pc
808 = skip_prologue_using_sal (gdbarch
, func_addr
);
809 struct symtab
*s
= find_pc_symtab (func_addr
);
811 /* GCC always emits a line note before the prologue and another
812 one after, even if the two are at the same address or on the
813 same line. Take advantage of this so that we do not need to
814 know every instruction that might appear in the prologue. We
815 will have producer information for most binaries; if it is
816 missing (e.g. for -gstabs), assuming the GNU tools. */
819 || s
->producer
== NULL
820 || strncmp (s
->producer
, "GNU ", sizeof ("GNU ") - 1) == 0))
821 return post_prologue_pc
;
823 if (post_prologue_pc
!= 0)
825 CORE_ADDR analyzed_limit
;
827 /* For non-GCC compilers, make sure the entire line is an
828 acceptable prologue; GDB will round this function's
829 return value up to the end of the following line so we
830 can not skip just part of a line (and we do not want to).
832 RealView does not treat the prologue specially, but does
833 associate prologue code with the opening brace; so this
834 lets us skip the first line if we think it is the opening
836 if (arm_pc_is_thumb (gdbarch
, func_addr
))
837 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
838 post_prologue_pc
, NULL
);
840 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
841 post_prologue_pc
, NULL
);
843 if (analyzed_limit
!= post_prologue_pc
)
846 return post_prologue_pc
;
850 /* Can't determine prologue from the symbol table, need to examine
853 /* Find an upper limit on the function prologue using the debug
854 information. If the debug information could not be used to provide
855 that bound, then use an arbitrary large number as the upper bound. */
856 /* Like arm_scan_prologue, stop no later than pc + 64. */
857 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
859 limit_pc
= pc
+ 64; /* Magic. */
862 /* Check if this is Thumb code. */
863 if (arm_pc_is_thumb (gdbarch
, pc
))
864 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
866 for (skip_pc
= pc
; skip_pc
< limit_pc
; skip_pc
+= 4)
868 inst
= read_memory_unsigned_integer (skip_pc
, 4, byte_order_for_code
);
870 /* "mov ip, sp" is no longer a required part of the prologue. */
871 if (inst
== 0xe1a0c00d) /* mov ip, sp */
874 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
877 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
880 /* Some prologues begin with "str lr, [sp, #-4]!". */
881 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
884 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
887 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
890 /* Any insns after this point may float into the code, if it makes
891 for better instruction scheduling, so we skip them only if we
892 find them, but still consider the function to be frame-ful. */
894 /* We may have either one sfmfd instruction here, or several stfe
895 insns, depending on the version of floating point code we
897 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
900 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
903 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
906 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
909 if ((inst
& 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */
910 || (inst
& 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */
911 || (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
914 if ((inst
& 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */
915 || (inst
& 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */
916 || (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
919 /* Un-recognized instruction; stop scanning. */
923 return skip_pc
; /* End of prologue */
927 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
928 This function decodes a Thumb function prologue to determine:
929 1) the size of the stack frame
930 2) which registers are saved on it
931 3) the offsets of saved regs
932 4) the offset from the stack pointer to the frame pointer
934 A typical Thumb function prologue would create this stack frame
935 (offsets relative to FP)
936 old SP -> 24 stack parameters
939 R7 -> 0 local variables (16 bytes)
940 SP -> -12 additional stack space (12 bytes)
941 The frame size would thus be 36 bytes, and the frame offset would be
942 12 bytes. The frame register is R7.
944 The comments for thumb_skip_prolog() describe the algorithm we use
945 to detect the end of the prolog. */
949 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
950 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
952 CORE_ADDR prologue_start
;
953 CORE_ADDR prologue_end
;
954 CORE_ADDR current_pc
;
956 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
959 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
961 if (sal
.line
== 0) /* no line info, use current PC */
962 prologue_end
= prev_pc
;
963 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
964 prologue_end
= sal
.end
; /* (probably means no prologue) */
967 /* We're in the boondocks: we have no idea where the start of the
971 prologue_end
= min (prologue_end
, prev_pc
);
973 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
976 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
979 arm_instruction_changes_pc (uint32_t this_instr
)
981 if (bits (this_instr
, 28, 31) == INST_NV
)
982 /* Unconditional instructions. */
983 switch (bits (this_instr
, 24, 27))
987 /* Branch with Link and change to Thumb. */
992 /* Coprocessor register transfer. */
993 if (bits (this_instr
, 12, 15) == 15)
994 error (_("Invalid update to pc in instruction"));
1000 switch (bits (this_instr
, 25, 27))
1003 if (bits (this_instr
, 23, 24) == 2 && bit (this_instr
, 20) == 0)
1005 /* Multiplies and extra load/stores. */
1006 if (bit (this_instr
, 4) == 1 && bit (this_instr
, 7) == 1)
1007 /* Neither multiplies nor extension load/stores are allowed
1011 /* Otherwise, miscellaneous instructions. */
1013 /* BX <reg>, BXJ <reg>, BLX <reg> */
1014 if (bits (this_instr
, 4, 27) == 0x12fff1
1015 || bits (this_instr
, 4, 27) == 0x12fff2
1016 || bits (this_instr
, 4, 27) == 0x12fff3)
1019 /* Other miscellaneous instructions are unpredictable if they
1023 /* Data processing instruction. Fall through. */
1026 if (bits (this_instr
, 12, 15) == 15)
1033 /* Media instructions and architecturally undefined instructions. */
1034 if (bits (this_instr
, 25, 27) == 3 && bit (this_instr
, 4) == 1)
1038 if (bit (this_instr
, 20) == 0)
1042 if (bits (this_instr
, 12, 15) == ARM_PC_REGNUM
)
1048 /* Load/store multiple. */
1049 if (bit (this_instr
, 20) == 1 && bit (this_instr
, 15) == 1)
1055 /* Branch and branch with link. */
1060 /* Coprocessor transfers or SWIs can not affect PC. */
1064 internal_error (__FILE__
, __LINE__
, "bad value in switch");
1068 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1069 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1070 fill it in. Return the first address not recognized as a prologue
1073 We recognize all the instructions typically found in ARM prologues,
1074 plus harmless instructions which can be skipped (either for analysis
1075 purposes, or a more restrictive set that can be skipped when finding
1076 the end of the prologue). */
1079 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1080 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1081 struct arm_prologue_cache
*cache
)
1083 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1084 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1086 CORE_ADDR offset
, current_pc
;
1087 pv_t regs
[ARM_FPS_REGNUM
];
1088 struct pv_area
*stack
;
1089 struct cleanup
*back_to
;
1090 int framereg
, framesize
;
1091 CORE_ADDR unrecognized_pc
= 0;
1093 /* Search the prologue looking for instructions that set up the
1094 frame pointer, adjust the stack pointer, and save registers.
1096 Be careful, however, and if it doesn't look like a prologue,
1097 don't try to scan it. If, for instance, a frameless function
1098 begins with stmfd sp!, then we will tell ourselves there is
1099 a frame, which will confuse stack traceback, as well as "finish"
1100 and other operations that rely on a knowledge of the stack
1103 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1104 regs
[regno
] = pv_register (regno
, 0);
1105 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1106 back_to
= make_cleanup_free_pv_area (stack
);
1108 for (current_pc
= prologue_start
;
1109 current_pc
< prologue_end
;
1113 = read_memory_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1115 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1117 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1120 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1121 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1123 unsigned imm
= insn
& 0xff; /* immediate value */
1124 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1125 int rd
= bits (insn
, 12, 15);
1126 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1127 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1130 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1131 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1133 unsigned imm
= insn
& 0xff; /* immediate value */
1134 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1135 int rd
= bits (insn
, 12, 15);
1136 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1137 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1140 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd, [sp, #-4]! */
1142 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1144 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1145 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4,
1146 regs
[bits (insn
, 12, 15)]);
1149 else if ((insn
& 0xffff0000) == 0xe92d0000)
1150 /* stmfd sp!, {..., fp, ip, lr, pc}
1152 stmfd sp!, {a1, a2, a3, a4} */
1154 int mask
= insn
& 0xffff;
1156 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1159 /* Calculate offsets of saved registers. */
1160 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1161 if (mask
& (1 << regno
))
1163 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1164 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1167 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1168 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1169 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1171 /* No need to add this to saved_regs -- it's just an arg reg. */
1174 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1175 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1176 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1178 /* No need to add this to saved_regs -- it's just an arg reg. */
1181 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn, { registers } */
1182 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1184 /* No need to add this to saved_regs -- it's just arg regs. */
1187 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1189 unsigned imm
= insn
& 0xff; /* immediate value */
1190 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1191 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1192 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1194 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1196 unsigned imm
= insn
& 0xff; /* immediate value */
1197 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1198 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1199 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1201 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
1202 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1204 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1207 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1208 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1209 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1211 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
1212 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1214 int n_saved_fp_regs
;
1215 unsigned int fp_start_reg
, fp_bound_reg
;
1217 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1220 if ((insn
& 0x800) == 0x800) /* N0 is set */
1222 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1223 n_saved_fp_regs
= 3;
1225 n_saved_fp_regs
= 1;
1229 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1230 n_saved_fp_regs
= 2;
1232 n_saved_fp_regs
= 4;
1235 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1236 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1237 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1239 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1240 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
1241 regs
[fp_start_reg
++]);
1244 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1246 /* Allow some special function calls when skipping the
1247 prologue; GCC generates these before storing arguments to
1249 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1251 if (skip_prologue_function (dest
))
1256 else if ((insn
& 0xf0000000) != 0xe0000000)
1257 break; /* Condition not true, exit early */
1258 else if (arm_instruction_changes_pc (insn
))
1259 /* Don't scan past anything that might change control flow. */
1261 else if ((insn
& 0xfe500000) == 0xe8100000) /* ldm */
1263 /* Ignore block loads from the stack, potentially copying
1264 parameters from memory. */
1265 if (pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1270 else if ((insn
& 0xfc500000) == 0xe4100000)
1272 /* Similarly ignore single loads from the stack. */
1273 if (pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1278 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1279 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1280 register instead of the stack. */
1284 /* The optimizer might shove anything into the prologue,
1285 so we just skip what we don't recognize. */
1286 unrecognized_pc
= current_pc
;
1291 if (unrecognized_pc
== 0)
1292 unrecognized_pc
= current_pc
;
1294 /* The frame size is just the distance from the frame register
1295 to the original stack pointer. */
1296 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1298 /* Frame pointer is fp. */
1299 framereg
= ARM_FP_REGNUM
;
1300 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1302 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
1304 /* Try the stack pointer... this is a bit desperate. */
1305 framereg
= ARM_SP_REGNUM
;
1306 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1310 /* We're just out of luck. We don't know where the frame is. */
1317 cache
->framereg
= framereg
;
1318 cache
->framesize
= framesize
;
1320 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1321 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1322 cache
->saved_regs
[regno
].addr
= offset
;
1326 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1327 paddress (gdbarch
, unrecognized_pc
));
1329 do_cleanups (back_to
);
1330 return unrecognized_pc
;
1334 arm_scan_prologue (struct frame_info
*this_frame
,
1335 struct arm_prologue_cache
*cache
)
1337 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1338 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1340 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
1341 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1342 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1343 pv_t regs
[ARM_FPS_REGNUM
];
1344 struct pv_area
*stack
;
1345 struct cleanup
*back_to
;
1348 /* Assume there is no frame until proven otherwise. */
1349 cache
->framereg
= ARM_SP_REGNUM
;
1350 cache
->framesize
= 0;
1352 /* Check for Thumb prologue. */
1353 if (arm_frame_is_thumb (this_frame
))
1355 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1359 /* Find the function prologue. If we can't find the function in
1360 the symbol table, peek in the stack frame to find the PC. */
1361 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1364 /* One way to find the end of the prologue (which works well
1365 for unoptimized code) is to do the following:
1367 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1370 prologue_end = prev_pc;
1371 else if (sal.end < prologue_end)
1372 prologue_end = sal.end;
1374 This mechanism is very accurate so long as the optimizer
1375 doesn't move any instructions from the function body into the
1376 prologue. If this happens, sal.end will be the last
1377 instruction in the first hunk of prologue code just before
1378 the first instruction that the scheduler has moved from
1379 the body to the prologue.
1381 In order to make sure that we scan all of the prologue
1382 instructions, we use a slightly less accurate mechanism which
1383 may scan more than necessary. To help compensate for this
1384 lack of accuracy, the prologue scanning loop below contains
1385 several clauses which'll cause the loop to terminate early if
1386 an implausible prologue instruction is encountered.
1392 is a suitable endpoint since it accounts for the largest
1393 possible prologue plus up to five instructions inserted by
1396 if (prologue_end
> prologue_start
+ 64)
1398 prologue_end
= prologue_start
+ 64; /* See above. */
1403 /* We have no symbol information. Our only option is to assume this
1404 function has a standard stack frame and the normal frame register.
1405 Then, we can find the value of our frame pointer on entrance to
1406 the callee (or at the present moment if this is the innermost frame).
1407 The value stored there should be the address of the stmfd + 8. */
1408 CORE_ADDR frame_loc
;
1409 LONGEST return_value
;
1411 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
1412 if (!safe_read_memory_integer (frame_loc
, 4, byte_order
, &return_value
))
1416 prologue_start
= gdbarch_addr_bits_remove
1417 (gdbarch
, return_value
) - 8;
1418 prologue_end
= prologue_start
+ 64; /* See above. */
1422 if (prev_pc
< prologue_end
)
1423 prologue_end
= prev_pc
;
1425 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1428 static struct arm_prologue_cache
*
1429 arm_make_prologue_cache (struct frame_info
*this_frame
)
1432 struct arm_prologue_cache
*cache
;
1433 CORE_ADDR unwound_fp
;
1435 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1436 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1438 arm_scan_prologue (this_frame
, cache
);
1440 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
1441 if (unwound_fp
== 0)
1444 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
1446 /* Calculate actual addresses of saved registers using offsets
1447 determined by arm_scan_prologue. */
1448 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
1449 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
1450 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
1455 /* Our frame ID for a normal frame is the current function's starting PC
1456 and the caller's SP when we were called. */
1459 arm_prologue_this_id (struct frame_info
*this_frame
,
1461 struct frame_id
*this_id
)
1463 struct arm_prologue_cache
*cache
;
1467 if (*this_cache
== NULL
)
1468 *this_cache
= arm_make_prologue_cache (this_frame
);
1469 cache
= *this_cache
;
1471 /* This is meant to halt the backtrace at "_start". */
1472 pc
= get_frame_pc (this_frame
);
1473 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1476 /* If we've hit a wall, stop. */
1477 if (cache
->prev_sp
== 0)
1480 func
= get_frame_func (this_frame
);
1481 id
= frame_id_build (cache
->prev_sp
, func
);
1485 static struct value
*
1486 arm_prologue_prev_register (struct frame_info
*this_frame
,
1490 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1491 struct arm_prologue_cache
*cache
;
1493 if (*this_cache
== NULL
)
1494 *this_cache
= arm_make_prologue_cache (this_frame
);
1495 cache
= *this_cache
;
1497 /* If we are asked to unwind the PC, then we need to return the LR
1498 instead. The prologue may save PC, but it will point into this
1499 frame's prologue, not the next frame's resume location. Also
1500 strip the saved T bit. A valid LR may have the low bit set, but
1501 a valid PC never does. */
1502 if (prev_regnum
== ARM_PC_REGNUM
)
1506 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1507 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1508 arm_addr_bits_remove (gdbarch
, lr
));
1511 /* SP is generally not saved to the stack, but this frame is
1512 identified by the next frame's stack pointer at the time of the call.
1513 The value was already reconstructed into PREV_SP. */
1514 if (prev_regnum
== ARM_SP_REGNUM
)
1515 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1517 /* The CPSR may have been changed by the call instruction and by the
1518 called function. The only bit we can reconstruct is the T bit,
1519 by checking the low bit of LR as of the call. This is a reliable
1520 indicator of Thumb-ness except for some ARM v4T pre-interworking
1521 Thumb code, which could get away with a clear low bit as long as
1522 the called function did not use bx. Guess that all other
1523 bits are unchanged; the condition flags are presumably lost,
1524 but the processor status is likely valid. */
1525 if (prev_regnum
== ARM_PS_REGNUM
)
1528 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
1530 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1531 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1532 if (IS_THUMB_ADDR (lr
))
1536 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1539 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1543 struct frame_unwind arm_prologue_unwind
= {
1545 arm_prologue_this_id
,
1546 arm_prologue_prev_register
,
1548 default_frame_sniffer
1551 static struct arm_prologue_cache
*
1552 arm_make_stub_cache (struct frame_info
*this_frame
)
1554 struct arm_prologue_cache
*cache
;
1556 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1557 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1559 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1564 /* Our frame ID for a stub frame is the current SP and LR. */
1567 arm_stub_this_id (struct frame_info
*this_frame
,
1569 struct frame_id
*this_id
)
1571 struct arm_prologue_cache
*cache
;
1573 if (*this_cache
== NULL
)
1574 *this_cache
= arm_make_stub_cache (this_frame
);
1575 cache
= *this_cache
;
1577 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
1581 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
1582 struct frame_info
*this_frame
,
1583 void **this_prologue_cache
)
1585 CORE_ADDR addr_in_block
;
1588 addr_in_block
= get_frame_address_in_block (this_frame
);
1589 if (in_plt_section (addr_in_block
, NULL
)
1590 /* We also use the stub winder if the target memory is unreadable
1591 to avoid having the prologue unwinder trying to read it. */
1592 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
1598 struct frame_unwind arm_stub_unwind
= {
1601 arm_prologue_prev_register
,
1603 arm_stub_unwind_sniffer
1607 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
1609 struct arm_prologue_cache
*cache
;
1611 if (*this_cache
== NULL
)
1612 *this_cache
= arm_make_prologue_cache (this_frame
);
1613 cache
= *this_cache
;
1615 return cache
->prev_sp
- cache
->framesize
;
1618 struct frame_base arm_normal_base
= {
1619 &arm_prologue_unwind
,
1620 arm_normal_frame_base
,
1621 arm_normal_frame_base
,
1622 arm_normal_frame_base
1625 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1626 dummy frame. The frame ID's base needs to match the TOS value
1627 saved by save_dummy_frame_tos() and returned from
1628 arm_push_dummy_call, and the PC needs to match the dummy frame's
1631 static struct frame_id
1632 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1634 return frame_id_build (get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
),
1635 get_frame_pc (this_frame
));
1638 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1639 be used to construct the previous frame's ID, after looking up the
1640 containing function). */
1643 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1646 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1647 return arm_addr_bits_remove (gdbarch
, pc
);
1651 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1653 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1656 static struct value
*
1657 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1660 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
1662 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
1667 /* The PC is normally copied from the return column, which
1668 describes saves of LR. However, that version may have an
1669 extra bit set to indicate Thumb state. The bit is not
1671 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1672 return frame_unwind_got_constant (this_frame
, regnum
,
1673 arm_addr_bits_remove (gdbarch
, lr
));
1676 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
1677 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
1678 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1679 if (IS_THUMB_ADDR (lr
))
1683 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
1686 internal_error (__FILE__
, __LINE__
,
1687 _("Unexpected register %d"), regnum
);
1692 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1693 struct dwarf2_frame_state_reg
*reg
,
1694 struct frame_info
*this_frame
)
1700 reg
->how
= DWARF2_FRAME_REG_FN
;
1701 reg
->loc
.fn
= arm_dwarf2_prev_register
;
1704 reg
->how
= DWARF2_FRAME_REG_CFA
;
1709 /* When arguments must be pushed onto the stack, they go on in reverse
1710 order. The code below implements a FILO (stack) to do this. */
1715 struct stack_item
*prev
;
1719 static struct stack_item
*
1720 push_stack_item (struct stack_item
*prev
, const void *contents
, int len
)
1722 struct stack_item
*si
;
1723 si
= xmalloc (sizeof (struct stack_item
));
1724 si
->data
= xmalloc (len
);
1727 memcpy (si
->data
, contents
, len
);
1731 static struct stack_item
*
1732 pop_stack_item (struct stack_item
*si
)
1734 struct stack_item
*dead
= si
;
1742 /* Return the alignment (in bytes) of the given type. */
1745 arm_type_align (struct type
*t
)
1751 t
= check_typedef (t
);
1752 switch (TYPE_CODE (t
))
1755 /* Should never happen. */
1756 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1760 case TYPE_CODE_ENUM
:
1764 case TYPE_CODE_RANGE
:
1765 case TYPE_CODE_BITSTRING
:
1767 case TYPE_CODE_CHAR
:
1768 case TYPE_CODE_BOOL
:
1769 return TYPE_LENGTH (t
);
1771 case TYPE_CODE_ARRAY
:
1772 case TYPE_CODE_COMPLEX
:
1773 /* TODO: What about vector types? */
1774 return arm_type_align (TYPE_TARGET_TYPE (t
));
1776 case TYPE_CODE_STRUCT
:
1777 case TYPE_CODE_UNION
:
1779 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1781 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
1789 /* Possible base types for a candidate for passing and returning in
1792 enum arm_vfp_cprc_base_type
1801 /* The length of one element of base type B. */
1804 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
1808 case VFP_CPRC_SINGLE
:
1810 case VFP_CPRC_DOUBLE
:
1812 case VFP_CPRC_VEC64
:
1814 case VFP_CPRC_VEC128
:
1817 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
1822 /* The character ('s', 'd' or 'q') for the type of VFP register used
1823 for passing base type B. */
1826 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
1830 case VFP_CPRC_SINGLE
:
1832 case VFP_CPRC_DOUBLE
:
1834 case VFP_CPRC_VEC64
:
1836 case VFP_CPRC_VEC128
:
1839 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
1844 /* Determine whether T may be part of a candidate for passing and
1845 returning in VFP registers, ignoring the limit on the total number
1846 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
1847 classification of the first valid component found; if it is not
1848 VFP_CPRC_UNKNOWN, all components must have the same classification
1849 as *BASE_TYPE. If it is found that T contains a type not permitted
1850 for passing and returning in VFP registers, a type differently
1851 classified from *BASE_TYPE, or two types differently classified
1852 from each other, return -1, otherwise return the total number of
1853 base-type elements found (possibly 0 in an empty structure or
1854 array). Vectors and complex types are not currently supported,
1855 matching the generic AAPCS support. */
1858 arm_vfp_cprc_sub_candidate (struct type
*t
,
1859 enum arm_vfp_cprc_base_type
*base_type
)
1861 t
= check_typedef (t
);
1862 switch (TYPE_CODE (t
))
1865 switch (TYPE_LENGTH (t
))
1868 if (*base_type
== VFP_CPRC_UNKNOWN
)
1869 *base_type
= VFP_CPRC_SINGLE
;
1870 else if (*base_type
!= VFP_CPRC_SINGLE
)
1875 if (*base_type
== VFP_CPRC_UNKNOWN
)
1876 *base_type
= VFP_CPRC_DOUBLE
;
1877 else if (*base_type
!= VFP_CPRC_DOUBLE
)
1886 case TYPE_CODE_ARRAY
:
1890 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
), base_type
);
1893 if (TYPE_LENGTH (t
) == 0)
1895 gdb_assert (count
== 0);
1898 else if (count
== 0)
1900 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
1901 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
1902 return TYPE_LENGTH (t
) / unitlen
;
1906 case TYPE_CODE_STRUCT
:
1911 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
1913 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
1915 if (sub_count
== -1)
1919 if (TYPE_LENGTH (t
) == 0)
1921 gdb_assert (count
== 0);
1924 else if (count
== 0)
1926 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
1927 if (TYPE_LENGTH (t
) != unitlen
* count
)
1932 case TYPE_CODE_UNION
:
1937 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
1939 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
1941 if (sub_count
== -1)
1943 count
= (count
> sub_count
? count
: sub_count
);
1945 if (TYPE_LENGTH (t
) == 0)
1947 gdb_assert (count
== 0);
1950 else if (count
== 0)
1952 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
1953 if (TYPE_LENGTH (t
) != unitlen
* count
)
1965 /* Determine whether T is a VFP co-processor register candidate (CPRC)
1966 if passed to or returned from a non-variadic function with the VFP
1967 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
1968 *BASE_TYPE to the base type for T and *COUNT to the number of
1969 elements of that base type before returning. */
1972 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
1975 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
1976 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
1977 if (c
<= 0 || c
> 4)
1984 /* Return 1 if the VFP ABI should be used for passing arguments to and
1985 returning values from a function of type FUNC_TYPE, 0
1989 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
1991 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1992 /* Variadic functions always use the base ABI. Assume that functions
1993 without debug info are not variadic. */
1994 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
1996 /* The VFP ABI is only supported as a variant of AAPCS. */
1997 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
1999 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
2002 /* We currently only support passing parameters in integer registers, which
2003 conforms with GCC's default model, and VFP argument passing following
2004 the VFP variant of AAPCS. Several other variants exist and
2005 we should probably support some of them based on the selected ABI. */
2008 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2009 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2010 struct value
**args
, CORE_ADDR sp
, int struct_return
,
2011 CORE_ADDR struct_addr
)
2013 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2017 struct stack_item
*si
= NULL
;
2020 unsigned vfp_regs_free
= (1 << 16) - 1;
2022 /* Determine the type of this function and whether the VFP ABI
2024 ftype
= check_typedef (value_type (function
));
2025 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
2026 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
2027 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
2029 /* Set the return address. For the ARM, the return breakpoint is
2030 always at BP_ADDR. */
2031 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
2033 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
2035 /* Walk through the list of args and determine how large a temporary
2036 stack is required. Need to take care here as structs may be
2037 passed on the stack, and we have to to push them. */
2040 argreg
= ARM_A1_REGNUM
;
2043 /* The struct_return pointer occupies the first parameter
2044 passing register. */
2048 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
2049 gdbarch_register_name (gdbarch
, argreg
),
2050 paddress (gdbarch
, struct_addr
));
2051 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
2055 for (argnum
= 0; argnum
< nargs
; argnum
++)
2058 struct type
*arg_type
;
2059 struct type
*target_type
;
2060 enum type_code typecode
;
2061 const bfd_byte
*val
;
2063 enum arm_vfp_cprc_base_type vfp_base_type
;
2065 int may_use_core_reg
= 1;
2067 arg_type
= check_typedef (value_type (args
[argnum
]));
2068 len
= TYPE_LENGTH (arg_type
);
2069 target_type
= TYPE_TARGET_TYPE (arg_type
);
2070 typecode
= TYPE_CODE (arg_type
);
2071 val
= value_contents (args
[argnum
]);
2073 align
= arm_type_align (arg_type
);
2074 /* Round alignment up to a whole number of words. */
2075 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
2076 /* Different ABIs have different maximum alignments. */
2077 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
2079 /* The APCS ABI only requires word alignment. */
2080 align
= INT_REGISTER_SIZE
;
2084 /* The AAPCS requires at most doubleword alignment. */
2085 if (align
> INT_REGISTER_SIZE
* 2)
2086 align
= INT_REGISTER_SIZE
* 2;
2090 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
2098 /* Because this is a CPRC it cannot go in a core register or
2099 cause a core register to be skipped for alignment.
2100 Either it goes in VFP registers and the rest of this loop
2101 iteration is skipped for this argument, or it goes on the
2102 stack (and the stack alignment code is correct for this
2104 may_use_core_reg
= 0;
2106 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
2107 shift
= unit_length
/ 4;
2108 mask
= (1 << (shift
* vfp_base_count
)) - 1;
2109 for (regno
= 0; regno
< 16; regno
+= shift
)
2110 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
2119 vfp_regs_free
&= ~(mask
<< regno
);
2120 reg_scaled
= regno
/ shift
;
2121 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
2122 for (i
= 0; i
< vfp_base_count
; i
++)
2126 if (reg_char
== 'q')
2127 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
2128 val
+ i
* unit_length
);
2131 sprintf (name_buf
, "%c%d", reg_char
, reg_scaled
+ i
);
2132 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
2134 regcache_cooked_write (regcache
, regnum
,
2135 val
+ i
* unit_length
);
2142 /* This CPRC could not go in VFP registers, so all VFP
2143 registers are now marked as used. */
2148 /* Push stack padding for dowubleword alignment. */
2149 if (nstack
& (align
- 1))
2151 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
2152 nstack
+= INT_REGISTER_SIZE
;
2155 /* Doubleword aligned quantities must go in even register pairs. */
2156 if (may_use_core_reg
2157 && argreg
<= ARM_LAST_ARG_REGNUM
2158 && align
> INT_REGISTER_SIZE
2162 /* If the argument is a pointer to a function, and it is a
2163 Thumb function, create a LOCAL copy of the value and set
2164 the THUMB bit in it. */
2165 if (TYPE_CODE_PTR
== typecode
2166 && target_type
!= NULL
2167 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
2169 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
2170 if (arm_pc_is_thumb (gdbarch
, regval
))
2172 bfd_byte
*copy
= alloca (len
);
2173 store_unsigned_integer (copy
, len
, byte_order
,
2174 MAKE_THUMB_ADDR (regval
));
2179 /* Copy the argument to general registers or the stack in
2180 register-sized pieces. Large arguments are split between
2181 registers and stack. */
2184 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
2186 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
2188 /* The argument is being passed in a general purpose
2191 = extract_unsigned_integer (val
, partial_len
, byte_order
);
2192 if (byte_order
== BFD_ENDIAN_BIG
)
2193 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
2195 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
2197 gdbarch_register_name
2199 phex (regval
, INT_REGISTER_SIZE
));
2200 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2205 /* Push the arguments onto the stack. */
2207 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
2209 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
2210 nstack
+= INT_REGISTER_SIZE
;
2217 /* If we have an odd number of words to push, then decrement the stack
2218 by one word now, so first stack argument will be dword aligned. */
2225 write_memory (sp
, si
->data
, si
->len
);
2226 si
= pop_stack_item (si
);
2229 /* Finally, update teh SP register. */
2230 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
2236 /* Always align the frame to an 8-byte boundary. This is required on
2237 some platforms and harmless on the rest. */
2240 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2242 /* Align the stack to eight bytes. */
2243 return sp
& ~ (CORE_ADDR
) 7;
2247 print_fpu_flags (int flags
)
2249 if (flags
& (1 << 0))
2250 fputs ("IVO ", stdout
);
2251 if (flags
& (1 << 1))
2252 fputs ("DVZ ", stdout
);
2253 if (flags
& (1 << 2))
2254 fputs ("OFL ", stdout
);
2255 if (flags
& (1 << 3))
2256 fputs ("UFL ", stdout
);
2257 if (flags
& (1 << 4))
2258 fputs ("INX ", stdout
);
2262 /* Print interesting information about the floating point processor
2263 (if present) or emulator. */
2265 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2266 struct frame_info
*frame
, const char *args
)
2268 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
2271 type
= (status
>> 24) & 127;
2272 if (status
& (1 << 31))
2273 printf (_("Hardware FPU type %d\n"), type
);
2275 printf (_("Software FPU type %d\n"), type
);
2276 /* i18n: [floating point unit] mask */
2277 fputs (_("mask: "), stdout
);
2278 print_fpu_flags (status
>> 16);
2279 /* i18n: [floating point unit] flags */
2280 fputs (_("flags: "), stdout
);
2281 print_fpu_flags (status
);
2284 /* Construct the ARM extended floating point type. */
2285 static struct type
*
2286 arm_ext_type (struct gdbarch
*gdbarch
)
2288 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2290 if (!tdep
->arm_ext_type
)
2292 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
2293 floatformats_arm_ext
);
2295 return tdep
->arm_ext_type
;
2298 static struct type
*
2299 arm_neon_double_type (struct gdbarch
*gdbarch
)
2301 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2303 if (tdep
->neon_double_type
== NULL
)
2305 struct type
*t
, *elem
;
2307 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
2309 elem
= builtin_type (gdbarch
)->builtin_uint8
;
2310 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
2311 elem
= builtin_type (gdbarch
)->builtin_uint16
;
2312 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
2313 elem
= builtin_type (gdbarch
)->builtin_uint32
;
2314 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
2315 elem
= builtin_type (gdbarch
)->builtin_uint64
;
2316 append_composite_type_field (t
, "u64", elem
);
2317 elem
= builtin_type (gdbarch
)->builtin_float
;
2318 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
2319 elem
= builtin_type (gdbarch
)->builtin_double
;
2320 append_composite_type_field (t
, "f64", elem
);
2322 TYPE_VECTOR (t
) = 1;
2323 TYPE_NAME (t
) = "neon_d";
2324 tdep
->neon_double_type
= t
;
2327 return tdep
->neon_double_type
;
2330 /* FIXME: The vector types are not correctly ordered on big-endian
2331 targets. Just as s0 is the low bits of d0, d0[0] is also the low
2332 bits of d0 - regardless of what unit size is being held in d0. So
2333 the offset of the first uint8 in d0 is 7, but the offset of the
2334 first float is 4. This code works as-is for little-endian
2337 static struct type
*
2338 arm_neon_quad_type (struct gdbarch
*gdbarch
)
2340 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2342 if (tdep
->neon_quad_type
== NULL
)
2344 struct type
*t
, *elem
;
2346 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
2348 elem
= builtin_type (gdbarch
)->builtin_uint8
;
2349 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
2350 elem
= builtin_type (gdbarch
)->builtin_uint16
;
2351 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
2352 elem
= builtin_type (gdbarch
)->builtin_uint32
;
2353 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
2354 elem
= builtin_type (gdbarch
)->builtin_uint64
;
2355 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
2356 elem
= builtin_type (gdbarch
)->builtin_float
;
2357 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
2358 elem
= builtin_type (gdbarch
)->builtin_double
;
2359 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
2361 TYPE_VECTOR (t
) = 1;
2362 TYPE_NAME (t
) = "neon_q";
2363 tdep
->neon_quad_type
= t
;
2366 return tdep
->neon_quad_type
;
2369 /* Return the GDB type object for the "standard" data type of data in
2372 static struct type
*
2373 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
2375 int num_regs
= gdbarch_num_regs (gdbarch
);
2377 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
2378 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
2379 return builtin_type (gdbarch
)->builtin_float
;
2381 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
2382 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
2383 return arm_neon_quad_type (gdbarch
);
2385 /* If the target description has register information, we are only
2386 in this function so that we can override the types of
2387 double-precision registers for NEON. */
2388 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
2390 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
2392 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
2393 && TYPE_CODE (t
) == TYPE_CODE_FLT
2394 && gdbarch_tdep (gdbarch
)->have_neon
)
2395 return arm_neon_double_type (gdbarch
);
2400 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
2402 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
2403 return builtin_type (gdbarch
)->builtin_void
;
2405 return arm_ext_type (gdbarch
);
2407 else if (regnum
== ARM_SP_REGNUM
)
2408 return builtin_type (gdbarch
)->builtin_data_ptr
;
2409 else if (regnum
== ARM_PC_REGNUM
)
2410 return builtin_type (gdbarch
)->builtin_func_ptr
;
2411 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
2412 /* These registers are only supported on targets which supply
2413 an XML description. */
2414 return builtin_type (gdbarch
)->builtin_int0
;
2416 return builtin_type (gdbarch
)->builtin_uint32
;
2419 /* Map a DWARF register REGNUM onto the appropriate GDB register
2423 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
2425 /* Core integer regs. */
2426 if (reg
>= 0 && reg
<= 15)
2429 /* Legacy FPA encoding. These were once used in a way which
2430 overlapped with VFP register numbering, so their use is
2431 discouraged, but GDB doesn't support the ARM toolchain
2432 which used them for VFP. */
2433 if (reg
>= 16 && reg
<= 23)
2434 return ARM_F0_REGNUM
+ reg
- 16;
2436 /* New assignments for the FPA registers. */
2437 if (reg
>= 96 && reg
<= 103)
2438 return ARM_F0_REGNUM
+ reg
- 96;
2440 /* WMMX register assignments. */
2441 if (reg
>= 104 && reg
<= 111)
2442 return ARM_WCGR0_REGNUM
+ reg
- 104;
2444 if (reg
>= 112 && reg
<= 127)
2445 return ARM_WR0_REGNUM
+ reg
- 112;
2447 if (reg
>= 192 && reg
<= 199)
2448 return ARM_WC0_REGNUM
+ reg
- 192;
2450 /* VFP v2 registers. A double precision value is actually
2451 in d1 rather than s2, but the ABI only defines numbering
2452 for the single precision registers. This will "just work"
2453 in GDB for little endian targets (we'll read eight bytes,
2454 starting in s0 and then progressing to s1), but will be
2455 reversed on big endian targets with VFP. This won't
2456 be a problem for the new Neon quad registers; you're supposed
2457 to use DW_OP_piece for those. */
2458 if (reg
>= 64 && reg
<= 95)
2462 sprintf (name_buf
, "s%d", reg
- 64);
2463 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
2467 /* VFP v3 / Neon registers. This range is also used for VFP v2
2468 registers, except that it now describes d0 instead of s0. */
2469 if (reg
>= 256 && reg
<= 287)
2473 sprintf (name_buf
, "d%d", reg
- 256);
2474 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
2481 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
2483 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
2486 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
2488 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
2489 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
2491 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
2492 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
2494 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
2495 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
2497 if (reg
< NUM_GREGS
)
2498 return SIM_ARM_R0_REGNUM
+ reg
;
2501 if (reg
< NUM_FREGS
)
2502 return SIM_ARM_FP0_REGNUM
+ reg
;
2505 if (reg
< NUM_SREGS
)
2506 return SIM_ARM_FPS_REGNUM
+ reg
;
2509 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
2512 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
2513 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
2514 It is thought that this is is the floating-point register format on
2515 little-endian systems. */
2518 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
2519 void *dbl
, int endianess
)
2523 if (endianess
== BFD_ENDIAN_BIG
)
2524 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
2526 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
2528 floatformat_from_doublest (fmt
, &d
, dbl
);
2532 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
2537 floatformat_to_doublest (fmt
, ptr
, &d
);
2538 if (endianess
== BFD_ENDIAN_BIG
)
2539 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
2541 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
2546 condition_true (unsigned long cond
, unsigned long status_reg
)
2548 if (cond
== INST_AL
|| cond
== INST_NV
)
2554 return ((status_reg
& FLAG_Z
) != 0);
2556 return ((status_reg
& FLAG_Z
) == 0);
2558 return ((status_reg
& FLAG_C
) != 0);
2560 return ((status_reg
& FLAG_C
) == 0);
2562 return ((status_reg
& FLAG_N
) != 0);
2564 return ((status_reg
& FLAG_N
) == 0);
2566 return ((status_reg
& FLAG_V
) != 0);
2568 return ((status_reg
& FLAG_V
) == 0);
2570 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
2572 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
2574 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
2576 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
2578 return (((status_reg
& FLAG_Z
) == 0)
2579 && (((status_reg
& FLAG_N
) == 0)
2580 == ((status_reg
& FLAG_V
) == 0)));
2582 return (((status_reg
& FLAG_Z
) != 0)
2583 || (((status_reg
& FLAG_N
) == 0)
2584 != ((status_reg
& FLAG_V
) == 0)));
2589 static unsigned long
2590 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
2591 unsigned long pc_val
, unsigned long status_reg
)
2593 unsigned long res
, shift
;
2594 int rm
= bits (inst
, 0, 3);
2595 unsigned long shifttype
= bits (inst
, 5, 6);
2599 int rs
= bits (inst
, 8, 11);
2600 shift
= (rs
== 15 ? pc_val
+ 8
2601 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
2604 shift
= bits (inst
, 7, 11);
2607 ? (pc_val
+ (bit (inst
, 4) ? 12 : 8))
2608 : get_frame_register_unsigned (frame
, rm
));
2613 res
= shift
>= 32 ? 0 : res
<< shift
;
2617 res
= shift
>= 32 ? 0 : res
>> shift
;
2623 res
= ((res
& 0x80000000L
)
2624 ? ~((~res
) >> shift
) : res
>> shift
);
2627 case 3: /* ROR/RRX */
2630 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
2632 res
= (res
>> shift
) | (res
<< (32 - shift
));
2636 return res
& 0xffffffff;
2639 /* Return number of 1-bits in VAL. */
2642 bitcount (unsigned long val
)
2645 for (nbits
= 0; val
!= 0; nbits
++)
2646 val
&= val
- 1; /* delete rightmost 1-bit in val */
2650 /* Return the size in bytes of the complete Thumb instruction whose
2651 first halfword is INST1. */
2654 thumb_insn_size (unsigned short inst1
)
2656 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
2663 thumb_advance_itstate (unsigned int itstate
)
2665 /* Preserve IT[7:5], the first three bits of the condition. Shift
2666 the upcoming condition flags left by one bit. */
2667 itstate
= (itstate
& 0xe0) | ((itstate
<< 1) & 0x1f);
2669 /* If we have finished the IT block, clear the state. */
2670 if ((itstate
& 0x0f) == 0)
2676 /* Find the next PC after the current instruction executes. In some
2677 cases we can not statically determine the answer (see the IT state
2678 handling in this function); in that case, a breakpoint may be
2679 inserted in addition to the returned PC, which will be used to set
2680 another breakpoint by our caller. */
2683 thumb_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
, int insert_bkpt
)
2685 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2686 struct address_space
*aspace
= get_frame_address_space (frame
);
2687 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2688 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2689 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
2690 unsigned short inst1
;
2691 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
2692 unsigned long offset
;
2693 ULONGEST status
, itstate
;
2695 nextpc
= MAKE_THUMB_ADDR (nextpc
);
2696 pc_val
= MAKE_THUMB_ADDR (pc_val
);
2698 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
2700 /* Thumb-2 conditional execution support. There are eight bits in
2701 the CPSR which describe conditional execution state. Once
2702 reconstructed (they're in a funny order), the low five bits
2703 describe the low bit of the condition for each instruction and
2704 how many instructions remain. The high three bits describe the
2705 base condition. One of the low four bits will be set if an IT
2706 block is active. These bits read as zero on earlier
2708 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
2709 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
2711 /* If-Then handling. On GNU/Linux, where this routine is used, we
2712 use an undefined instruction as a breakpoint. Unlike BKPT, IT
2713 can disable execution of the undefined instruction. So we might
2714 miss the breakpoint if we set it on a skipped conditional
2715 instruction. Because conditional instructions can change the
2716 flags, affecting the execution of further instructions, we may
2717 need to set two breakpoints. */
2719 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
!= NULL
)
2721 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
2723 /* An IT instruction. Because this instruction does not
2724 modify the flags, we can accurately predict the next
2725 executed instruction. */
2726 itstate
= inst1
& 0x00ff;
2727 pc
+= thumb_insn_size (inst1
);
2729 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
2731 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
2732 pc
+= thumb_insn_size (inst1
);
2733 itstate
= thumb_advance_itstate (itstate
);
2736 return MAKE_THUMB_ADDR (pc
);
2738 else if (itstate
!= 0)
2740 /* We are in a conditional block. Check the condition. */
2741 if (! condition_true (itstate
>> 4, status
))
2743 /* Advance to the next executed instruction. */
2744 pc
+= thumb_insn_size (inst1
);
2745 itstate
= thumb_advance_itstate (itstate
);
2747 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
2749 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
2750 pc
+= thumb_insn_size (inst1
);
2751 itstate
= thumb_advance_itstate (itstate
);
2754 return MAKE_THUMB_ADDR (pc
);
2756 else if ((itstate
& 0x0f) == 0x08)
2758 /* This is the last instruction of the conditional
2759 block, and it is executed. We can handle it normally
2760 because the following instruction is not conditional,
2761 and we must handle it normally because it is
2762 permitted to branch. Fall through. */
2768 /* There are conditional instructions after this one.
2769 If this instruction modifies the flags, then we can
2770 not predict what the next executed instruction will
2771 be. Fortunately, this instruction is architecturally
2772 forbidden to branch; we know it will fall through.
2773 Start by skipping past it. */
2774 pc
+= thumb_insn_size (inst1
);
2775 itstate
= thumb_advance_itstate (itstate
);
2777 /* Set a breakpoint on the following instruction. */
2778 gdb_assert ((itstate
& 0x0f) != 0);
2780 insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
2781 cond_negated
= (itstate
>> 4) & 1;
2783 /* Skip all following instructions with the same
2784 condition. If there is a later instruction in the IT
2785 block with the opposite condition, set the other
2786 breakpoint there. If not, then set a breakpoint on
2787 the instruction after the IT block. */
2790 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
2791 pc
+= thumb_insn_size (inst1
);
2792 itstate
= thumb_advance_itstate (itstate
);
2794 while (itstate
!= 0 && ((itstate
>> 4) & 1) == cond_negated
);
2796 return MAKE_THUMB_ADDR (pc
);
2800 else if (itstate
& 0x0f)
2802 /* We are in a conditional block. Check the condition. */
2803 int cond
= itstate
>> 4;
2805 if (! condition_true (cond
, status
))
2807 /* Advance to the next instruction. All the 32-bit
2808 instructions share a common prefix. */
2809 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
2810 return MAKE_THUMB_ADDR (pc
+ 4);
2812 return MAKE_THUMB_ADDR (pc
+ 2);
2815 /* Otherwise, handle the instruction normally. */
2818 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
2822 /* Fetch the saved PC from the stack. It's stored above
2823 all of the other registers. */
2824 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
2825 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
2826 nextpc
= read_memory_unsigned_integer (sp
+ offset
, 4, byte_order
);
2828 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
2830 unsigned long cond
= bits (inst1
, 8, 11);
2831 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
2832 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
2834 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
2836 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
2838 else if ((inst1
& 0xe000) == 0xe000) /* 32-bit instruction */
2840 unsigned short inst2
;
2841 inst2
= read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
2843 /* Default to the next instruction. */
2845 nextpc
= MAKE_THUMB_ADDR (nextpc
);
2847 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
2849 /* Branches and miscellaneous control instructions. */
2851 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
2854 int j1
, j2
, imm1
, imm2
;
2856 imm1
= sbits (inst1
, 0, 10);
2857 imm2
= bits (inst2
, 0, 10);
2858 j1
= bit (inst2
, 13);
2859 j2
= bit (inst2
, 11);
2861 offset
= ((imm1
<< 12) + (imm2
<< 1));
2862 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
2864 nextpc
= pc_val
+ offset
;
2865 /* For BLX make sure to clear the low bits. */
2866 if (bit (inst2
, 12) == 0)
2867 nextpc
= nextpc
& 0xfffffffc;
2869 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
2871 /* SUBS PC, LR, #imm8. */
2872 nextpc
= get_frame_register_unsigned (frame
, ARM_LR_REGNUM
);
2873 nextpc
-= inst2
& 0x00ff;
2875 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
2877 /* Conditional branch. */
2878 if (condition_true (bits (inst1
, 6, 9), status
))
2880 int sign
, j1
, j2
, imm1
, imm2
;
2882 sign
= sbits (inst1
, 10, 10);
2883 imm1
= bits (inst1
, 0, 5);
2884 imm2
= bits (inst2
, 0, 10);
2885 j1
= bit (inst2
, 13);
2886 j2
= bit (inst2
, 11);
2888 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
2889 offset
+= (imm1
<< 12) + (imm2
<< 1);
2891 nextpc
= pc_val
+ offset
;
2895 else if ((inst1
& 0xfe50) == 0xe810)
2897 /* Load multiple or RFE. */
2898 int rn
, offset
, load_pc
= 1;
2900 rn
= bits (inst1
, 0, 3);
2901 if (bit (inst1
, 7) && !bit (inst1
, 8))
2904 if (!bit (inst2
, 15))
2906 offset
= bitcount (inst2
) * 4 - 4;
2908 else if (!bit (inst1
, 7) && bit (inst1
, 8))
2911 if (!bit (inst2
, 15))
2915 else if (bit (inst1
, 7) && bit (inst1
, 8))
2920 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
2930 CORE_ADDR addr
= get_frame_register_unsigned (frame
, rn
);
2931 nextpc
= get_frame_memory_unsigned (frame
, addr
+ offset
, 4);
2934 else if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
2936 /* MOV PC or MOVS PC. */
2937 nextpc
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
2938 nextpc
= MAKE_THUMB_ADDR (nextpc
);
2940 else if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
2944 int rn
, load_pc
= 1;
2946 rn
= bits (inst1
, 0, 3);
2947 base
= get_frame_register_unsigned (frame
, rn
);
2950 base
= (base
+ 4) & ~(CORE_ADDR
) 0x3;
2952 base
+= bits (inst2
, 0, 11);
2954 base
-= bits (inst2
, 0, 11);
2956 else if (bit (inst1
, 7))
2957 base
+= bits (inst2
, 0, 11);
2958 else if (bit (inst2
, 11))
2960 if (bit (inst2
, 10))
2963 base
+= bits (inst2
, 0, 7);
2965 base
-= bits (inst2
, 0, 7);
2968 else if ((inst2
& 0x0fc0) == 0x0000)
2970 int shift
= bits (inst2
, 4, 5), rm
= bits (inst2
, 0, 3);
2971 base
+= get_frame_register_unsigned (frame
, rm
) << shift
;
2978 nextpc
= get_frame_memory_unsigned (frame
, base
, 4);
2980 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
2983 CORE_ADDR tbl_reg
, table
, offset
, length
;
2985 tbl_reg
= bits (inst1
, 0, 3);
2986 if (tbl_reg
== 0x0f)
2987 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
2989 table
= get_frame_register_unsigned (frame
, tbl_reg
);
2991 offset
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
2992 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 1);
2993 nextpc
= pc_val
+ length
;
2995 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
2998 CORE_ADDR tbl_reg
, table
, offset
, length
;
3000 tbl_reg
= bits (inst1
, 0, 3);
3001 if (tbl_reg
== 0x0f)
3002 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
3004 table
= get_frame_register_unsigned (frame
, tbl_reg
);
3006 offset
= 2 * get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
3007 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 2);
3008 nextpc
= pc_val
+ length
;
3011 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
3013 if (bits (inst1
, 3, 6) == 0x0f)
3016 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
3018 else if ((inst1
& 0xf500) == 0xb100)
3021 int imm
= (bit (inst1
, 9) << 6) + (bits (inst1
, 3, 7) << 1);
3022 ULONGEST reg
= get_frame_register_unsigned (frame
, bits (inst1
, 0, 2));
3024 if (bit (inst1
, 11) && reg
!= 0)
3025 nextpc
= pc_val
+ imm
;
3026 else if (!bit (inst1
, 11) && reg
== 0)
3027 nextpc
= pc_val
+ imm
;
3032 /* Get the raw next address. PC is the current program counter, in
3033 FRAME. INSERT_BKPT should be TRUE if we want a breakpoint set on
3034 the alternative next instruction if there are two options.
3036 The value returned has the execution state of the next instruction
3037 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
3038 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
3042 arm_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
, int insert_bkpt
)
3044 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3045 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3046 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3047 unsigned long pc_val
;
3048 unsigned long this_instr
;
3049 unsigned long status
;
3052 if (arm_frame_is_thumb (frame
))
3053 return thumb_get_next_pc_raw (frame
, pc
, insert_bkpt
);
3055 pc_val
= (unsigned long) pc
;
3056 this_instr
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3058 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
3059 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
3061 if (bits (this_instr
, 28, 31) == INST_NV
)
3062 switch (bits (this_instr
, 24, 27))
3067 /* Branch with Link and change to Thumb. */
3068 nextpc
= BranchDest (pc
, this_instr
);
3069 nextpc
|= bit (this_instr
, 24) << 1;
3070 nextpc
= MAKE_THUMB_ADDR (nextpc
);
3076 /* Coprocessor register transfer. */
3077 if (bits (this_instr
, 12, 15) == 15)
3078 error (_("Invalid update to pc in instruction"));
3081 else if (condition_true (bits (this_instr
, 28, 31), status
))
3083 switch (bits (this_instr
, 24, 27))
3086 case 0x1: /* data processing */
3090 unsigned long operand1
, operand2
, result
= 0;
3094 if (bits (this_instr
, 12, 15) != 15)
3097 if (bits (this_instr
, 22, 25) == 0
3098 && bits (this_instr
, 4, 7) == 9) /* multiply */
3099 error (_("Invalid update to pc in instruction"));
3101 /* BX <reg>, BLX <reg> */
3102 if (bits (this_instr
, 4, 27) == 0x12fff1
3103 || bits (this_instr
, 4, 27) == 0x12fff3)
3105 rn
= bits (this_instr
, 0, 3);
3106 nextpc
= (rn
== 15) ? pc_val
+ 8
3107 : get_frame_register_unsigned (frame
, rn
);
3111 /* Multiply into PC */
3112 c
= (status
& FLAG_C
) ? 1 : 0;
3113 rn
= bits (this_instr
, 16, 19);
3114 operand1
= (rn
== 15) ? pc_val
+ 8
3115 : get_frame_register_unsigned (frame
, rn
);
3117 if (bit (this_instr
, 25))
3119 unsigned long immval
= bits (this_instr
, 0, 7);
3120 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
3121 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
3124 else /* operand 2 is a shifted register */
3125 operand2
= shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
);
3127 switch (bits (this_instr
, 21, 24))
3130 result
= operand1
& operand2
;
3134 result
= operand1
^ operand2
;
3138 result
= operand1
- operand2
;
3142 result
= operand2
- operand1
;
3146 result
= operand1
+ operand2
;
3150 result
= operand1
+ operand2
+ c
;
3154 result
= operand1
- operand2
+ c
;
3158 result
= operand2
- operand1
+ c
;
3164 case 0xb: /* tst, teq, cmp, cmn */
3165 result
= (unsigned long) nextpc
;
3169 result
= operand1
| operand2
;
3173 /* Always step into a function. */
3178 result
= operand1
& ~operand2
;
3186 /* In 26-bit APCS the bottom two bits of the result are
3187 ignored, and we always end up in ARM state. */
3189 nextpc
= arm_addr_bits_remove (gdbarch
, result
);
3197 case 0x5: /* data transfer */
3200 if (bit (this_instr
, 20))
3203 if (bits (this_instr
, 12, 15) == 15)
3209 if (bit (this_instr
, 22))
3210 error (_("Invalid update to pc in instruction"));
3212 /* byte write to PC */
3213 rn
= bits (this_instr
, 16, 19);
3214 base
= (rn
== 15) ? pc_val
+ 8
3215 : get_frame_register_unsigned (frame
, rn
);
3216 if (bit (this_instr
, 24))
3219 int c
= (status
& FLAG_C
) ? 1 : 0;
3220 unsigned long offset
=
3221 (bit (this_instr
, 25)
3222 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
3223 : bits (this_instr
, 0, 11));
3225 if (bit (this_instr
, 23))
3230 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
3237 case 0x9: /* block transfer */
3238 if (bit (this_instr
, 20))
3241 if (bit (this_instr
, 15))
3246 if (bit (this_instr
, 23))
3249 unsigned long reglist
= bits (this_instr
, 0, 14);
3250 offset
= bitcount (reglist
) * 4;
3251 if (bit (this_instr
, 24)) /* pre */
3254 else if (bit (this_instr
, 24))
3258 unsigned long rn_val
=
3259 get_frame_register_unsigned (frame
,
3260 bits (this_instr
, 16, 19));
3262 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
3270 case 0xb: /* branch & link */
3271 case 0xa: /* branch */
3273 nextpc
= BranchDest (pc
, this_instr
);
3279 case 0xe: /* coproc ops */
3284 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
3293 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
3295 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3297 gdbarch_addr_bits_remove (gdbarch
,
3298 arm_get_next_pc_raw (frame
, pc
, TRUE
));
3300 error (_("Infinite loop detected"));
3304 /* single_step() is called just before we want to resume the inferior,
3305 if we want to single-step it but there is no hardware or kernel
3306 single-step support. We find the target of the coming instruction
3307 and breakpoint it. */
3310 arm_software_single_step (struct frame_info
*frame
)
3312 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3313 struct address_space
*aspace
= get_frame_address_space (frame
);
3315 /* NOTE: This may insert the wrong breakpoint instruction when
3316 single-stepping over a mode-changing instruction, if the
3317 CPSR heuristics are used. */
3319 CORE_ADDR next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
3320 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
3325 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
3326 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
3327 NULL if an error occurs. BUF is freed. */
3330 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
3331 int old_len
, int new_len
)
3333 gdb_byte
*new_buf
, *middle
;
3334 int bytes_to_read
= new_len
- old_len
;
3336 new_buf
= xmalloc (new_len
);
3337 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
3339 if (target_read_memory (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
3347 /* An IT block is at most the 2-byte IT instruction followed by
3348 four 4-byte instructions. The furthest back we must search to
3349 find an IT block that affects the current instruction is thus
3350 2 + 3 * 4 == 14 bytes. */
3351 #define MAX_IT_BLOCK_PREFIX 14
3353 /* Use a quick scan if there are more than this many bytes of
3355 #define IT_SCAN_THRESHOLD 32
3357 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
3358 A breakpoint in an IT block may not be hit, depending on the
3361 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
3365 CORE_ADDR boundary
, func_start
;
3366 int buf_len
, buf2_len
;
3367 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
3368 int i
, any
, last_it
, last_it_count
;
3370 /* If we are using BKPT breakpoints, none of this is necessary. */
3371 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
3374 /* ARM mode does not have this problem. */
3375 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
3378 /* We are setting a breakpoint in Thumb code that could potentially
3379 contain an IT block. The first step is to find how much Thumb
3380 code there is; we do not need to read outside of known Thumb
3382 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
3384 /* Thumb-2 code must have mapping symbols to have a chance. */
3387 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
3389 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
3390 && func_start
> boundary
)
3391 boundary
= func_start
;
3393 /* Search for a candidate IT instruction. We have to do some fancy
3394 footwork to distinguish a real IT instruction from the second
3395 half of a 32-bit instruction, but there is no need for that if
3396 there's no candidate. */
3397 buf_len
= min (bpaddr
- boundary
, MAX_IT_BLOCK_PREFIX
);
3399 /* No room for an IT instruction. */
3402 buf
= xmalloc (buf_len
);
3403 if (target_read_memory (bpaddr
- buf_len
, buf
, buf_len
) != 0)
3406 for (i
= 0; i
< buf_len
; i
+= 2)
3408 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
3409 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
3421 /* OK, the code bytes before this instruction contain at least one
3422 halfword which resembles an IT instruction. We know that it's
3423 Thumb code, but there are still two possibilities. Either the
3424 halfword really is an IT instruction, or it is the second half of
3425 a 32-bit Thumb instruction. The only way we can tell is to
3426 scan forwards from a known instruction boundary. */
3427 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
3431 /* There's a lot of code before this instruction. Start with an
3432 optimistic search; it's easy to recognize halfwords that can
3433 not be the start of a 32-bit instruction, and use that to
3434 lock on to the instruction boundaries. */
3435 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
3438 buf_len
= IT_SCAN_THRESHOLD
;
3441 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
3443 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
3444 if (thumb_insn_size (inst1
) == 2)
3451 /* At this point, if DEFINITE, BUF[I] is the first place we
3452 are sure that we know the instruction boundaries, and it is far
3453 enough from BPADDR that we could not miss an IT instruction
3454 affecting BPADDR. If ! DEFINITE, give up - start from a
3458 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
3461 buf_len
= bpaddr
- boundary
;
3467 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
3470 buf_len
= bpaddr
- boundary
;
3474 /* Scan forwards. Find the last IT instruction before BPADDR. */
3479 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
3481 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
3486 else if (inst1
& 0x0002)
3488 else if (inst1
& 0x0004)
3493 i
+= thumb_insn_size (inst1
);
3499 /* There wasn't really an IT instruction after all. */
3502 if (last_it_count
< 1)
3503 /* It was too far away. */
3506 /* This really is a trouble spot. Move the breakpoint to the IT
3508 return bpaddr
- buf_len
+ last_it
;
3511 /* ARM displaced stepping support.
3513 Generally ARM displaced stepping works as follows:
3515 1. When an instruction is to be single-stepped, it is first decoded by
3516 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
3517 Depending on the type of instruction, it is then copied to a scratch
3518 location, possibly in a modified form. The copy_* set of functions
3519 performs such modification, as necessary. A breakpoint is placed after
3520 the modified instruction in the scratch space to return control to GDB.
3521 Note in particular that instructions which modify the PC will no longer
3522 do so after modification.
3524 2. The instruction is single-stepped, by setting the PC to the scratch
3525 location address, and resuming. Control returns to GDB when the
3528 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
3529 function used for the current instruction. This function's job is to
3530 put the CPU/memory state back to what it would have been if the
3531 instruction had been executed unmodified in its original location. */
3533 /* NOP instruction (mov r0, r0). */
3534 #define ARM_NOP 0xe1a00000
3536 /* Helper for register reads for displaced stepping. In particular, this
3537 returns the PC as it would be seen by the instruction at its original
3541 displaced_read_reg (struct regcache
*regs
, CORE_ADDR from
, int regno
)
3547 if (debug_displaced
)
3548 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
3549 (unsigned long) from
+ 8);
3550 return (ULONGEST
) from
+ 8; /* Pipeline offset. */
3554 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
3555 if (debug_displaced
)
3556 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
3557 regno
, (unsigned long) ret
);
3563 displaced_in_arm_mode (struct regcache
*regs
)
3566 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
3568 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
3570 return (ps
& t_bit
) == 0;
3573 /* Write to the PC as from a branch instruction. */
3576 branch_write_pc (struct regcache
*regs
, ULONGEST val
)
3578 if (displaced_in_arm_mode (regs
))
3579 /* Note: If bits 0/1 are set, this branch would be unpredictable for
3580 architecture versions < 6. */
3581 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& ~(ULONGEST
) 0x3);
3583 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& ~(ULONGEST
) 0x1);
3586 /* Write to the PC as from a branch-exchange instruction. */
3589 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
3592 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
3594 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
3598 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
3599 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
3601 else if ((val
& 2) == 0)
3603 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
3604 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
3608 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
3609 mode, align dest to 4 bytes). */
3610 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
3611 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
3612 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
3616 /* Write to the PC as if from a load instruction. */
3619 load_write_pc (struct regcache
*regs
, ULONGEST val
)
3621 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
3622 bx_write_pc (regs
, val
);
3624 branch_write_pc (regs
, val
);
3627 /* Write to the PC as if from an ALU instruction. */
3630 alu_write_pc (struct regcache
*regs
, ULONGEST val
)
3632 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && displaced_in_arm_mode (regs
))
3633 bx_write_pc (regs
, val
);
3635 branch_write_pc (regs
, val
);
3638 /* Helper for writing to registers for displaced stepping. Writing to the PC
3639 has a varying effects depending on the instruction which does the write:
3640 this is controlled by the WRITE_PC argument. */
3643 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
3644 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
3648 if (debug_displaced
)
3649 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
3650 (unsigned long) val
);
3653 case BRANCH_WRITE_PC
:
3654 branch_write_pc (regs
, val
);
3658 bx_write_pc (regs
, val
);
3662 load_write_pc (regs
, val
);
3666 alu_write_pc (regs
, val
);
3669 case CANNOT_WRITE_PC
:
3670 warning (_("Instruction wrote to PC in an unexpected way when "
3671 "single-stepping"));
3675 internal_error (__FILE__
, __LINE__
,
3676 _("Invalid argument to displaced_write_reg"));
3679 dsc
->wrote_to_pc
= 1;
3683 if (debug_displaced
)
3684 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
3685 regno
, (unsigned long) val
);
3686 regcache_cooked_write_unsigned (regs
, regno
, val
);
3690 /* This function is used to concisely determine if an instruction INSN
3691 references PC. Register fields of interest in INSN should have the
3692 corresponding fields of BITMASK set to 0b1111. The function returns return 1
3693 if any of these fields in INSN reference the PC (also 0b1111, r15), else it
3697 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
3699 uint32_t lowbit
= 1;
3701 while (bitmask
!= 0)
3705 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
3711 mask
= lowbit
* 0xf;
3713 if ((insn
& mask
) == mask
)
3722 /* The simplest copy function. Many instructions have the same effect no
3723 matter what address they are executed at: in those cases, use this. */
3726 copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
3727 const char *iname
, struct displaced_step_closure
*dsc
)
3729 if (debug_displaced
)
3730 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
3731 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
3734 dsc
->modinsn
[0] = insn
;
3739 /* Preload instructions with immediate offset. */
3742 cleanup_preload (struct gdbarch
*gdbarch
,
3743 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3745 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
3746 if (!dsc
->u
.preload
.immed
)
3747 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
3751 copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
3752 struct displaced_step_closure
*dsc
)
3754 unsigned int rn
= bits (insn
, 16, 19);
3756 CORE_ADDR from
= dsc
->insn_addr
;
3758 if (!insn_references_pc (insn
, 0x000f0000ul
))
3759 return copy_unmodified (gdbarch
, insn
, "preload", dsc
);
3761 if (debug_displaced
)
3762 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
3763 (unsigned long) insn
);
3765 /* Preload instructions:
3767 {pli/pld} [rn, #+/-imm]
3769 {pli/pld} [r0, #+/-imm]. */
3771 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3772 rn_val
= displaced_read_reg (regs
, from
, rn
);
3773 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
3775 dsc
->u
.preload
.immed
= 1;
3777 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
3779 dsc
->cleanup
= &cleanup_preload
;
3784 /* Preload instructions with register offset. */
3787 copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
3788 struct displaced_step_closure
*dsc
)
3790 unsigned int rn
= bits (insn
, 16, 19);
3791 unsigned int rm
= bits (insn
, 0, 3);
3792 ULONGEST rn_val
, rm_val
;
3793 CORE_ADDR from
= dsc
->insn_addr
;
3795 if (!insn_references_pc (insn
, 0x000f000ful
))
3796 return copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
3798 if (debug_displaced
)
3799 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
3800 (unsigned long) insn
);
3802 /* Preload register-offset instructions:
3804 {pli/pld} [rn, rm {, shift}]
3806 {pli/pld} [r0, r1 {, shift}]. */
3808 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3809 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
3810 rn_val
= displaced_read_reg (regs
, from
, rn
);
3811 rm_val
= displaced_read_reg (regs
, from
, rm
);
3812 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
3813 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
3815 dsc
->u
.preload
.immed
= 0;
3817 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
3819 dsc
->cleanup
= &cleanup_preload
;
3824 /* Copy/cleanup coprocessor load and store instructions. */
3827 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
3828 struct regcache
*regs
,
3829 struct displaced_step_closure
*dsc
)
3831 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
3833 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
3835 if (dsc
->u
.ldst
.writeback
)
3836 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
3840 copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
3841 struct regcache
*regs
,
3842 struct displaced_step_closure
*dsc
)
3844 unsigned int rn
= bits (insn
, 16, 19);
3846 CORE_ADDR from
= dsc
->insn_addr
;
3848 if (!insn_references_pc (insn
, 0x000f0000ul
))
3849 return copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
3851 if (debug_displaced
)
3852 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
3853 "load/store insn %.8lx\n", (unsigned long) insn
);
3855 /* Coprocessor load/store instructions:
3857 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
3859 {stc/stc2} [r0, #+/-imm].
3861 ldc/ldc2 are handled identically. */
3863 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3864 rn_val
= displaced_read_reg (regs
, from
, rn
);
3865 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
3867 dsc
->u
.ldst
.writeback
= bit (insn
, 25);
3868 dsc
->u
.ldst
.rn
= rn
;
3870 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
3872 dsc
->cleanup
= &cleanup_copro_load_store
;
3877 /* Clean up branch instructions (actually perform the branch, by setting
3881 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
3882 struct displaced_step_closure
*dsc
)
3884 ULONGEST from
= dsc
->insn_addr
;
3885 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
3886 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
3887 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
3888 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
3893 if (dsc
->u
.branch
.link
)
3895 ULONGEST pc
= displaced_read_reg (regs
, from
, 15);
3896 displaced_write_reg (regs
, dsc
, 14, pc
- 4, CANNOT_WRITE_PC
);
3899 displaced_write_reg (regs
, dsc
, 15, dsc
->u
.branch
.dest
, write_pc
);
3902 /* Copy B/BL/BLX instructions with immediate destinations. */
3905 copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
3906 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3908 unsigned int cond
= bits (insn
, 28, 31);
3909 int exchange
= (cond
== 0xf);
3910 int link
= exchange
|| bit (insn
, 24);
3911 CORE_ADDR from
= dsc
->insn_addr
;
3914 if (debug_displaced
)
3915 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
3916 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
3917 (unsigned long) insn
);
3919 /* Implement "BL<cond> <label>" as:
3921 Preparation: cond <- instruction condition
3922 Insn: mov r0, r0 (nop)
3923 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
3925 B<cond> similar, but don't set r14 in cleanup. */
3928 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
3929 then arrange the switch into Thumb mode. */
3930 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
3932 offset
= bits (insn
, 0, 23) << 2;
3934 if (bit (offset
, 25))
3935 offset
= offset
| ~0x3ffffff;
3937 dsc
->u
.branch
.cond
= cond
;
3938 dsc
->u
.branch
.link
= link
;
3939 dsc
->u
.branch
.exchange
= exchange
;
3940 dsc
->u
.branch
.dest
= from
+ 8 + offset
;
3942 dsc
->modinsn
[0] = ARM_NOP
;
3944 dsc
->cleanup
= &cleanup_branch
;
3949 /* Copy BX/BLX with register-specified destinations. */
3952 copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
3953 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3955 unsigned int cond
= bits (insn
, 28, 31);
3958 int link
= bit (insn
, 5);
3959 unsigned int rm
= bits (insn
, 0, 3);
3960 CORE_ADDR from
= dsc
->insn_addr
;
3962 if (debug_displaced
)
3963 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s register insn "
3964 "%.8lx\n", (link
) ? "blx" : "bx", (unsigned long) insn
);
3966 /* Implement {BX,BLX}<cond> <reg>" as:
3968 Preparation: cond <- instruction condition
3969 Insn: mov r0, r0 (nop)
3970 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
3972 Don't set r14 in cleanup for BX. */
3974 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, from
, rm
);
3976 dsc
->u
.branch
.cond
= cond
;
3977 dsc
->u
.branch
.link
= link
;
3978 dsc
->u
.branch
.exchange
= 1;
3980 dsc
->modinsn
[0] = ARM_NOP
;
3982 dsc
->cleanup
= &cleanup_branch
;
3987 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
3990 cleanup_alu_imm (struct gdbarch
*gdbarch
,
3991 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3993 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
3994 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
3995 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
3996 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
4000 copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4001 struct displaced_step_closure
*dsc
)
4003 unsigned int rn
= bits (insn
, 16, 19);
4004 unsigned int rd
= bits (insn
, 12, 15);
4005 unsigned int op
= bits (insn
, 21, 24);
4006 int is_mov
= (op
== 0xd);
4007 ULONGEST rd_val
, rn_val
;
4008 CORE_ADDR from
= dsc
->insn_addr
;
4010 if (!insn_references_pc (insn
, 0x000ff000ul
))
4011 return copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
4013 if (debug_displaced
)
4014 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
4015 "%.8lx\n", is_mov
? "move" : "ALU",
4016 (unsigned long) insn
);
4018 /* Instruction is of form:
4020 <op><cond> rd, [rn,] #imm
4024 Preparation: tmp1, tmp2 <- r0, r1;
4026 Insn: <op><cond> r0, r1, #imm
4027 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
4030 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
4031 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
4032 rn_val
= displaced_read_reg (regs
, from
, rn
);
4033 rd_val
= displaced_read_reg (regs
, from
, rd
);
4034 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
4035 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
4039 dsc
->modinsn
[0] = insn
& 0xfff00fff;
4041 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
4043 dsc
->cleanup
= &cleanup_alu_imm
;
4048 /* Copy/cleanup arithmetic/logic insns with register RHS. */
4051 cleanup_alu_reg (struct gdbarch
*gdbarch
,
4052 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4057 rd_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
4059 for (i
= 0; i
< 3; i
++)
4060 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
4062 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
4066 copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4067 struct displaced_step_closure
*dsc
)
4069 unsigned int rn
= bits (insn
, 16, 19);
4070 unsigned int rm
= bits (insn
, 0, 3);
4071 unsigned int rd
= bits (insn
, 12, 15);
4072 unsigned int op
= bits (insn
, 21, 24);
4073 int is_mov
= (op
== 0xd);
4074 ULONGEST rd_val
, rn_val
, rm_val
;
4075 CORE_ADDR from
= dsc
->insn_addr
;
4077 if (!insn_references_pc (insn
, 0x000ff00ful
))
4078 return copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
4080 if (debug_displaced
)
4081 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
4082 is_mov
? "move" : "ALU", (unsigned long) insn
);
4084 /* Instruction is of form:
4086 <op><cond> rd, [rn,] rm [, <shift>]
4090 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
4091 r0, r1, r2 <- rd, rn, rm
4092 Insn: <op><cond> r0, r1, r2 [, <shift>]
4093 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
4096 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
4097 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
4098 dsc
->tmp
[2] = displaced_read_reg (regs
, from
, 2);
4099 rd_val
= displaced_read_reg (regs
, from
, rd
);
4100 rn_val
= displaced_read_reg (regs
, from
, rn
);
4101 rm_val
= displaced_read_reg (regs
, from
, rm
);
4102 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
4103 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
4104 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
4108 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
4110 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
4112 dsc
->cleanup
= &cleanup_alu_reg
;
4117 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
4120 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
4121 struct regcache
*regs
,
4122 struct displaced_step_closure
*dsc
)
4124 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
4127 for (i
= 0; i
< 4; i
++)
4128 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
4130 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
4134 copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
4135 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4137 unsigned int rn
= bits (insn
, 16, 19);
4138 unsigned int rm
= bits (insn
, 0, 3);
4139 unsigned int rd
= bits (insn
, 12, 15);
4140 unsigned int rs
= bits (insn
, 8, 11);
4141 unsigned int op
= bits (insn
, 21, 24);
4142 int is_mov
= (op
== 0xd), i
;
4143 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
4144 CORE_ADDR from
= dsc
->insn_addr
;
4146 if (!insn_references_pc (insn
, 0x000fff0ful
))
4147 return copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
4149 if (debug_displaced
)
4150 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
4151 "%.8lx\n", is_mov
? "move" : "ALU",
4152 (unsigned long) insn
);
4154 /* Instruction is of form:
4156 <op><cond> rd, [rn,] rm, <shift> rs
4160 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
4161 r0, r1, r2, r3 <- rd, rn, rm, rs
4162 Insn: <op><cond> r0, r1, r2, <shift> r3
4164 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
4168 for (i
= 0; i
< 4; i
++)
4169 dsc
->tmp
[i
] = displaced_read_reg (regs
, from
, i
);
4171 rd_val
= displaced_read_reg (regs
, from
, rd
);
4172 rn_val
= displaced_read_reg (regs
, from
, rn
);
4173 rm_val
= displaced_read_reg (regs
, from
, rm
);
4174 rs_val
= displaced_read_reg (regs
, from
, rs
);
4175 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
4176 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
4177 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
4178 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
4182 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
4184 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
4186 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
4191 /* Clean up load instructions. */
4194 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4195 struct displaced_step_closure
*dsc
)
4197 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
4198 CORE_ADDR from
= dsc
->insn_addr
;
4200 rt_val
= displaced_read_reg (regs
, from
, 0);
4201 if (dsc
->u
.ldst
.xfersize
== 8)
4202 rt_val2
= displaced_read_reg (regs
, from
, 1);
4203 rn_val
= displaced_read_reg (regs
, from
, 2);
4205 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4206 if (dsc
->u
.ldst
.xfersize
> 4)
4207 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
4208 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
4209 if (!dsc
->u
.ldst
.immed
)
4210 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
4212 /* Handle register writeback. */
4213 if (dsc
->u
.ldst
.writeback
)
4214 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
4215 /* Put result in right place. */
4216 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
4217 if (dsc
->u
.ldst
.xfersize
== 8)
4218 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
4221 /* Clean up store instructions. */
4224 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4225 struct displaced_step_closure
*dsc
)
4227 CORE_ADDR from
= dsc
->insn_addr
;
4228 ULONGEST rn_val
= displaced_read_reg (regs
, from
, 2);
4230 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4231 if (dsc
->u
.ldst
.xfersize
> 4)
4232 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
4233 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
4234 if (!dsc
->u
.ldst
.immed
)
4235 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
4236 if (!dsc
->u
.ldst
.restore_r4
)
4237 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
4240 if (dsc
->u
.ldst
.writeback
)
4241 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
4244 /* Copy "extra" load/store instructions. These are halfword/doubleword
4245 transfers, which have a different encoding to byte/word transfers. */
4248 copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unpriveleged
,
4249 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4251 unsigned int op1
= bits (insn
, 20, 24);
4252 unsigned int op2
= bits (insn
, 5, 6);
4253 unsigned int rt
= bits (insn
, 12, 15);
4254 unsigned int rn
= bits (insn
, 16, 19);
4255 unsigned int rm
= bits (insn
, 0, 3);
4256 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
4257 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
4258 int immed
= (op1
& 0x4) != 0;
4260 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
4261 CORE_ADDR from
= dsc
->insn_addr
;
4263 if (!insn_references_pc (insn
, 0x000ff00ful
))
4264 return copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
4266 if (debug_displaced
)
4267 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
4268 "insn %.8lx\n", unpriveleged
? "unpriveleged " : "",
4269 (unsigned long) insn
);
4271 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
4274 internal_error (__FILE__
, __LINE__
,
4275 _("copy_extra_ld_st: instruction decode error"));
4277 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
4278 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
4279 dsc
->tmp
[2] = displaced_read_reg (regs
, from
, 2);
4281 dsc
->tmp
[3] = displaced_read_reg (regs
, from
, 3);
4283 rt_val
= displaced_read_reg (regs
, from
, rt
);
4284 if (bytesize
[opcode
] == 8)
4285 rt_val2
= displaced_read_reg (regs
, from
, rt
+ 1);
4286 rn_val
= displaced_read_reg (regs
, from
, rn
);
4288 rm_val
= displaced_read_reg (regs
, from
, rm
);
4290 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
4291 if (bytesize
[opcode
] == 8)
4292 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
4293 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
4295 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
4298 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
4299 dsc
->u
.ldst
.rn
= rn
;
4300 dsc
->u
.ldst
.immed
= immed
;
4301 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
4302 dsc
->u
.ldst
.restore_r4
= 0;
4305 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
4307 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
4308 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
4310 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
4312 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
4313 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
4315 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
4320 /* Copy byte/word loads and stores. */
4323 copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
4324 struct regcache
*regs
,
4325 struct displaced_step_closure
*dsc
, int load
, int byte
,
4328 int immed
= !bit (insn
, 25);
4329 unsigned int rt
= bits (insn
, 12, 15);
4330 unsigned int rn
= bits (insn
, 16, 19);
4331 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
4332 ULONGEST rt_val
, rn_val
, rm_val
= 0;
4333 CORE_ADDR from
= dsc
->insn_addr
;
4335 if (!insn_references_pc (insn
, 0x000ff00ful
))
4336 return copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
4338 if (debug_displaced
)
4339 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s%s insn %.8lx\n",
4340 load
? (byte
? "ldrb" : "ldr")
4341 : (byte
? "strb" : "str"), usermode
? "t" : "",
4342 (unsigned long) insn
);
4344 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
4345 dsc
->tmp
[2] = displaced_read_reg (regs
, from
, 2);
4347 dsc
->tmp
[3] = displaced_read_reg (regs
, from
, 3);
4349 dsc
->tmp
[4] = displaced_read_reg (regs
, from
, 4);
4351 rt_val
= displaced_read_reg (regs
, from
, rt
);
4352 rn_val
= displaced_read_reg (regs
, from
, rn
);
4354 rm_val
= displaced_read_reg (regs
, from
, rm
);
4356 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
4357 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
4359 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
4362 dsc
->u
.ldst
.xfersize
= byte
? 1 : 4;
4363 dsc
->u
.ldst
.rn
= rn
;
4364 dsc
->u
.ldst
.immed
= immed
;
4365 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
4367 /* To write PC we can do:
4369 scratch+0: str pc, temp (*temp = scratch + 8 + offset)
4370 scratch+4: ldr r4, temp
4371 scratch+8: sub r4, r4, pc (r4 = scratch + 8 + offset - scratch - 8 - 8)
4372 scratch+12: add r4, r4, #8 (r4 = offset)
4373 scratch+16: add r0, r0, r4
4374 scratch+20: str r0, [r2, #imm] (or str r0, [r2, r3])
4377 Otherwise we don't know what value to write for PC, since the offset is
4378 architecture-dependent (sometimes PC+8, sometimes PC+12). */
4380 if (load
|| rt
!= 15)
4382 dsc
->u
.ldst
.restore_r4
= 0;
4385 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
4387 {ldr,str}[b]<cond> r0, [r2, #imm]. */
4388 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
4390 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
4392 {ldr,str}[b]<cond> r0, [r2, r3]. */
4393 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
4397 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
4398 dsc
->u
.ldst
.restore_r4
= 1;
4400 dsc
->modinsn
[0] = 0xe58ff014; /* str pc, [pc, #20]. */
4401 dsc
->modinsn
[1] = 0xe59f4010; /* ldr r4, [pc, #16]. */
4402 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
4403 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
4404 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
4408 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
4410 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
4412 dsc
->modinsn
[6] = 0x0; /* breakpoint location. */
4413 dsc
->modinsn
[7] = 0x0; /* scratch space. */
4418 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
4423 /* Cleanup LDM instructions with fully-populated register list. This is an
4424 unfortunate corner case: it's impossible to implement correctly by modifying
4425 the instruction. The issue is as follows: we have an instruction,
4429 which we must rewrite to avoid loading PC. A possible solution would be to
4430 do the load in two halves, something like (with suitable cleanup
4434 ldm[id][ab] r8!, {r0-r7}
4436 ldm[id][ab] r8, {r7-r14}
4439 but at present there's no suitable place for <temp>, since the scratch space
4440 is overwritten before the cleanup routine is called. For now, we simply
4441 emulate the instruction. */
4444 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4445 struct displaced_step_closure
*dsc
)
4447 ULONGEST from
= dsc
->insn_addr
;
4448 int inc
= dsc
->u
.block
.increment
;
4449 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
4450 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
4451 uint32_t regmask
= dsc
->u
.block
.regmask
;
4452 int regno
= inc
? 0 : 15;
4453 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
4454 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
4455 && (regmask
& 0x8000) != 0;
4456 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
4457 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
4458 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4463 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
4464 sensible we can do here. Complain loudly. */
4465 if (exception_return
)
4466 error (_("Cannot single-step exception return"));
4468 /* We don't handle any stores here for now. */
4469 gdb_assert (dsc
->u
.block
.load
!= 0);
4471 if (debug_displaced
)
4472 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
4473 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
4474 dsc
->u
.block
.increment
? "inc" : "dec",
4475 dsc
->u
.block
.before
? "before" : "after");
4482 while (regno
<= 15 && (regmask
& (1 << regno
)) == 0)
4485 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
4488 xfer_addr
+= bump_before
;
4490 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
4491 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
4493 xfer_addr
+= bump_after
;
4495 regmask
&= ~(1 << regno
);
4498 if (dsc
->u
.block
.writeback
)
4499 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
4503 /* Clean up an STM which included the PC in the register list. */
4506 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4507 struct displaced_step_closure
*dsc
)
4509 ULONGEST from
= dsc
->insn_addr
;
4510 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
4511 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
4512 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
4513 CORE_ADDR stm_insn_addr
;
4516 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4518 /* If condition code fails, there's nothing else to do. */
4519 if (!store_executed
)
4522 if (dsc
->u
.block
.increment
)
4524 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
4526 if (dsc
->u
.block
.before
)
4531 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
4533 if (dsc
->u
.block
.before
)
4537 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
4538 stm_insn_addr
= dsc
->scratch_base
;
4539 offset
= pc_val
- stm_insn_addr
;
4541 if (debug_displaced
)
4542 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
4543 "STM instruction\n", offset
);
4545 /* Rewrite the stored PC to the proper value for the non-displaced original
4547 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
4548 dsc
->insn_addr
+ offset
);
4551 /* Clean up an LDM which includes the PC in the register list. We clumped all
4552 the registers in the transferred list into a contiguous range r0...rX (to
4553 avoid loading PC directly and losing control of the debugged program), so we
4554 must undo that here. */
4557 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
4558 struct regcache
*regs
,
4559 struct displaced_step_closure
*dsc
)
4561 ULONGEST from
= dsc
->insn_addr
;
4562 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
4563 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
), i
;
4564 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= 15;
4565 unsigned int regs_loaded
= bitcount (mask
);
4566 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
4568 /* The method employed here will fail if the register list is fully populated
4569 (we need to avoid loading PC directly). */
4570 gdb_assert (num_to_shuffle
< 16);
4575 clobbered
= (1 << num_to_shuffle
) - 1;
4577 while (num_to_shuffle
> 0)
4579 if ((mask
& (1 << write_reg
)) != 0)
4581 unsigned int read_reg
= num_to_shuffle
- 1;
4583 if (read_reg
!= write_reg
)
4585 ULONGEST rval
= displaced_read_reg (regs
, from
, read_reg
);
4586 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
4587 if (debug_displaced
)
4588 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
4589 "loaded register r%d to r%d\n"), read_reg
,
4592 else if (debug_displaced
)
4593 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
4594 "r%d already in the right place\n"),
4597 clobbered
&= ~(1 << write_reg
);
4605 /* Restore any registers we scribbled over. */
4606 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
4608 if ((clobbered
& (1 << write_reg
)) != 0)
4610 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
4612 if (debug_displaced
)
4613 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
4614 "clobbered register r%d\n"), write_reg
);
4615 clobbered
&= ~(1 << write_reg
);
4619 /* Perform register writeback manually. */
4620 if (dsc
->u
.block
.writeback
)
4622 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
4624 if (dsc
->u
.block
.increment
)
4625 new_rn_val
+= regs_loaded
* 4;
4627 new_rn_val
-= regs_loaded
* 4;
4629 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
4634 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
4635 in user-level code (in particular exception return, ldm rn, {...pc}^). */
4638 copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4639 struct displaced_step_closure
*dsc
)
4641 int load
= bit (insn
, 20);
4642 int user
= bit (insn
, 22);
4643 int increment
= bit (insn
, 23);
4644 int before
= bit (insn
, 24);
4645 int writeback
= bit (insn
, 21);
4646 int rn
= bits (insn
, 16, 19);
4647 CORE_ADDR from
= dsc
->insn_addr
;
4649 /* Block transfers which don't mention PC can be run directly out-of-line. */
4650 if (rn
!= 15 && (insn
& 0x8000) == 0)
4651 return copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
4655 warning (_("displaced: Unpredictable LDM or STM with base register r15"));
4656 return copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
4659 if (debug_displaced
)
4660 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
4661 "%.8lx\n", (unsigned long) insn
);
4663 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, from
, rn
);
4664 dsc
->u
.block
.rn
= rn
;
4666 dsc
->u
.block
.load
= load
;
4667 dsc
->u
.block
.user
= user
;
4668 dsc
->u
.block
.increment
= increment
;
4669 dsc
->u
.block
.before
= before
;
4670 dsc
->u
.block
.writeback
= writeback
;
4671 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
4673 dsc
->u
.block
.regmask
= insn
& 0xffff;
4677 if ((insn
& 0xffff) == 0xffff)
4679 /* LDM with a fully-populated register list. This case is
4680 particularly tricky. Implement for now by fully emulating the
4681 instruction (which might not behave perfectly in all cases, but
4682 these instructions should be rare enough for that not to matter
4684 dsc
->modinsn
[0] = ARM_NOP
;
4686 dsc
->cleanup
= &cleanup_block_load_all
;
4690 /* LDM of a list of registers which includes PC. Implement by
4691 rewriting the list of registers to be transferred into a
4692 contiguous chunk r0...rX before doing the transfer, then shuffling
4693 registers into the correct places in the cleanup routine. */
4694 unsigned int regmask
= insn
& 0xffff;
4695 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
4696 unsigned int to
= 0, from
= 0, i
, new_rn
;
4698 for (i
= 0; i
< num_in_list
; i
++)
4699 dsc
->tmp
[i
] = displaced_read_reg (regs
, from
, i
);
4701 /* Writeback makes things complicated. We need to avoid clobbering
4702 the base register with one of the registers in our modified
4703 register list, but just using a different register can't work in
4706 ldm r14!, {r0-r13,pc}
4708 which would need to be rewritten as:
4712 but that can't work, because there's no free register for N.
4714 Solve this by turning off the writeback bit, and emulating
4715 writeback manually in the cleanup routine. */
4720 new_regmask
= (1 << num_in_list
) - 1;
4722 if (debug_displaced
)
4723 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
4724 "{..., pc}: original reg list %.4x, modified "
4725 "list %.4x\n"), rn
, writeback
? "!" : "",
4726 (int) insn
& 0xffff, new_regmask
);
4728 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
4730 dsc
->cleanup
= &cleanup_block_load_pc
;
4735 /* STM of a list of registers which includes PC. Run the instruction
4736 as-is, but out of line: this will store the wrong value for the PC,
4737 so we must manually fix up the memory in the cleanup routine.
4738 Doing things this way has the advantage that we can auto-detect
4739 the offset of the PC write (which is architecture-dependent) in
4740 the cleanup routine. */
4741 dsc
->modinsn
[0] = insn
;
4743 dsc
->cleanup
= &cleanup_block_store_pc
;
4749 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
4750 for Linux, where some SVC instructions must be treated specially. */
4753 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4754 struct displaced_step_closure
*dsc
)
4756 CORE_ADDR from
= dsc
->insn_addr
;
4757 CORE_ADDR resume_addr
= from
+ 4;
4759 if (debug_displaced
)
4760 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
4761 "%.8lx\n", (unsigned long) resume_addr
);
4763 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
4767 copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
4768 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4770 CORE_ADDR from
= dsc
->insn_addr
;
4772 /* Allow OS-specific code to override SVC handling. */
4773 if (dsc
->u
.svc
.copy_svc_os
)
4774 return dsc
->u
.svc
.copy_svc_os (gdbarch
, insn
, to
, regs
, dsc
);
4776 if (debug_displaced
)
4777 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
4778 (unsigned long) insn
);
4780 /* Preparation: none.
4781 Insn: unmodified svc.
4782 Cleanup: pc <- insn_addr + 4. */
4784 dsc
->modinsn
[0] = insn
;
4786 dsc
->cleanup
= &cleanup_svc
;
4787 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
4789 dsc
->wrote_to_pc
= 1;
4794 /* Copy undefined instructions. */
4797 copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
4798 struct displaced_step_closure
*dsc
)
4800 if (debug_displaced
)
4801 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn %.8lx\n",
4802 (unsigned long) insn
);
4804 dsc
->modinsn
[0] = insn
;
4809 /* Copy unpredictable instructions. */
4812 copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
4813 struct displaced_step_closure
*dsc
)
4815 if (debug_displaced
)
4816 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
4817 "%.8lx\n", (unsigned long) insn
);
4819 dsc
->modinsn
[0] = insn
;
4824 /* The decode_* functions are instruction decoding helpers. They mostly follow
4825 the presentation in the ARM ARM. */
4828 decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
4829 struct regcache
*regs
,
4830 struct displaced_step_closure
*dsc
)
4832 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
4833 unsigned int rn
= bits (insn
, 16, 19);
4835 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
4836 return copy_unmodified (gdbarch
, insn
, "cps", dsc
);
4837 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
4838 return copy_unmodified (gdbarch
, insn
, "setend", dsc
);
4839 else if ((op1
& 0x60) == 0x20)
4840 return copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
4841 else if ((op1
& 0x71) == 0x40)
4842 return copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store", dsc
);
4843 else if ((op1
& 0x77) == 0x41)
4844 return copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
4845 else if ((op1
& 0x77) == 0x45)
4846 return copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
4847 else if ((op1
& 0x77) == 0x51)
4850 return copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
4852 return copy_unpred (gdbarch
, insn
, dsc
);
4854 else if ((op1
& 0x77) == 0x55)
4855 return copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
4856 else if (op1
== 0x57)
4859 case 0x1: return copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
4860 case 0x4: return copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
4861 case 0x5: return copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
4862 case 0x6: return copy_unmodified (gdbarch
, insn
, "isb", dsc
);
4863 default: return copy_unpred (gdbarch
, insn
, dsc
);
4865 else if ((op1
& 0x63) == 0x43)
4866 return copy_unpred (gdbarch
, insn
, dsc
);
4867 else if ((op2
& 0x1) == 0x0)
4868 switch (op1
& ~0x80)
4871 return copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
4873 return copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
4874 case 0x71: case 0x75:
4876 return copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
4877 case 0x63: case 0x67: case 0x73: case 0x77:
4878 return copy_unpred (gdbarch
, insn
, dsc
);
4880 return copy_undef (gdbarch
, insn
, dsc
);
4883 return copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
4887 decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
4888 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4890 if (bit (insn
, 27) == 0)
4891 return decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
4892 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
4893 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
4896 return copy_unmodified (gdbarch
, insn
, "srs", dsc
);
4899 return copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
4901 case 0x4: case 0x5: case 0x6: case 0x7:
4902 return copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
4905 switch ((insn
& 0xe00000) >> 21)
4907 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
4909 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4912 return copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
4915 return copy_undef (gdbarch
, insn
, dsc
);
4920 int rn_f
= (bits (insn
, 16, 19) == 0xf);
4921 switch ((insn
& 0xe00000) >> 21)
4924 /* ldc/ldc2 imm (undefined for rn == pc). */
4925 return rn_f
? copy_undef (gdbarch
, insn
, dsc
)
4926 : copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4929 return copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
4931 case 0x4: case 0x5: case 0x6: case 0x7:
4932 /* ldc/ldc2 lit (undefined for rn != pc). */
4933 return rn_f
? copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
4934 : copy_undef (gdbarch
, insn
, dsc
);
4937 return copy_undef (gdbarch
, insn
, dsc
);
4942 return copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
4945 if (bits (insn
, 16, 19) == 0xf)
4947 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4949 return copy_undef (gdbarch
, insn
, dsc
);
4953 return copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
4955 return copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
4959 return copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
4961 return copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
4964 return copy_undef (gdbarch
, insn
, dsc
);
4968 /* Decode miscellaneous instructions in dp/misc encoding space. */
4971 decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
4972 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4974 unsigned int op2
= bits (insn
, 4, 6);
4975 unsigned int op
= bits (insn
, 21, 22);
4976 unsigned int op1
= bits (insn
, 16, 19);
4981 return copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
4984 if (op
== 0x1) /* bx. */
4985 return copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
4987 return copy_unmodified (gdbarch
, insn
, "clz", dsc
);
4989 return copy_undef (gdbarch
, insn
, dsc
);
4993 /* Not really supported. */
4994 return copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
4996 return copy_undef (gdbarch
, insn
, dsc
);
5000 return copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
); /* blx register. */
5002 return copy_undef (gdbarch
, insn
, dsc
);
5005 return copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
5009 return copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
5011 /* Not really supported. */
5012 return copy_unmodified (gdbarch
, insn
, "smc", dsc
);
5015 return copy_undef (gdbarch
, insn
, dsc
);
5020 decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5021 struct displaced_step_closure
*dsc
)
5024 switch (bits (insn
, 20, 24))
5027 return copy_unmodified (gdbarch
, insn
, "movw", dsc
);
5030 return copy_unmodified (gdbarch
, insn
, "movt", dsc
);
5032 case 0x12: case 0x16:
5033 return copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
5036 return copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
5040 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
5042 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
5043 return copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
5044 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
5045 return copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
5046 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
5047 return decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
5048 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
5049 return copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
5050 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
5051 return copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
5052 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
5053 return copy_unmodified (gdbarch
, insn
, "synch", dsc
);
5054 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
5055 /* 2nd arg means "unpriveleged". */
5056 return copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
5060 /* Should be unreachable. */
5065 decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
5066 struct regcache
*regs
,
5067 struct displaced_step_closure
*dsc
)
5069 int a
= bit (insn
, 25), b
= bit (insn
, 4);
5070 uint32_t op1
= bits (insn
, 20, 24);
5071 int rn_f
= bits (insn
, 16, 19) == 0xf;
5073 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
5074 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
5075 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 0, 0);
5076 else if ((!a
&& (op1
& 0x17) == 0x02)
5077 || (a
&& (op1
& 0x17) == 0x02 && !b
))
5078 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 0, 1);
5079 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
5080 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
5081 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 0, 0);
5082 else if ((!a
&& (op1
& 0x17) == 0x03)
5083 || (a
&& (op1
& 0x17) == 0x03 && !b
))
5084 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 0, 1);
5085 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
5086 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
5087 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
5088 else if ((!a
&& (op1
& 0x17) == 0x06)
5089 || (a
&& (op1
& 0x17) == 0x06 && !b
))
5090 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
5091 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
5092 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
5093 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
5094 else if ((!a
&& (op1
& 0x17) == 0x07)
5095 || (a
&& (op1
& 0x17) == 0x07 && !b
))
5096 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
5098 /* Should be unreachable. */
5103 decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
5104 struct displaced_step_closure
*dsc
)
5106 switch (bits (insn
, 20, 24))
5108 case 0x00: case 0x01: case 0x02: case 0x03:
5109 return copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
5111 case 0x04: case 0x05: case 0x06: case 0x07:
5112 return copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
5114 case 0x08: case 0x09: case 0x0a: case 0x0b:
5115 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
5116 return copy_unmodified (gdbarch
, insn
,
5117 "decode/pack/unpack/saturate/reverse", dsc
);
5120 if (bits (insn
, 5, 7) == 0) /* op2. */
5122 if (bits (insn
, 12, 15) == 0xf)
5123 return copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
5125 return copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
5128 return copy_undef (gdbarch
, insn
, dsc
);
5130 case 0x1a: case 0x1b:
5131 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
5132 return copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
5134 return copy_undef (gdbarch
, insn
, dsc
);
5136 case 0x1c: case 0x1d:
5137 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
5139 if (bits (insn
, 0, 3) == 0xf)
5140 return copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
5142 return copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
5145 return copy_undef (gdbarch
, insn
, dsc
);
5147 case 0x1e: case 0x1f:
5148 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
5149 return copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
5151 return copy_undef (gdbarch
, insn
, dsc
);
5154 /* Should be unreachable. */
5159 decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, int32_t insn
,
5160 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5163 return copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
5165 return copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
5169 decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
5170 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5172 unsigned int opcode
= bits (insn
, 20, 24);
5176 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
5177 return copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
5179 case 0x08: case 0x0a: case 0x0c: case 0x0e:
5180 case 0x12: case 0x16:
5181 return copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
5183 case 0x09: case 0x0b: case 0x0d: case 0x0f:
5184 case 0x13: case 0x17:
5185 return copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
5187 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
5188 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
5189 /* Note: no writeback for these instructions. Bit 25 will always be
5190 zero though (via caller), so the following works OK. */
5191 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
5194 /* Should be unreachable. */
5199 decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
5200 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5202 unsigned int op1
= bits (insn
, 20, 25);
5203 int op
= bit (insn
, 4);
5204 unsigned int coproc
= bits (insn
, 8, 11);
5205 unsigned int rn
= bits (insn
, 16, 19);
5207 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
5208 return decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
5209 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
5210 && (coproc
& 0xe) != 0xa)
5212 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
5213 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
5214 && (coproc
& 0xe) != 0xa)
5215 /* ldc/ldc2 imm/lit. */
5216 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
5217 else if ((op1
& 0x3e) == 0x00)
5218 return copy_undef (gdbarch
, insn
, dsc
);
5219 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
5220 return copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
5221 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
5222 return copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
5223 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
5224 return copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
5225 else if ((op1
& 0x30) == 0x20 && !op
)
5227 if ((coproc
& 0xe) == 0xa)
5228 return copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
5230 return copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
5232 else if ((op1
& 0x30) == 0x20 && op
)
5233 return copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
5234 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
5235 return copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
5236 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
5237 return copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
5238 else if ((op1
& 0x30) == 0x30)
5239 return copy_svc (gdbarch
, insn
, to
, regs
, dsc
);
5241 return copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
5245 arm_process_displaced_insn (struct gdbarch
*gdbarch
, uint32_t insn
,
5246 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
,
5247 struct displaced_step_closure
*dsc
)
5251 if (!displaced_in_arm_mode (regs
))
5252 error (_("Displaced stepping is only supported in ARM mode"));
5254 /* Most displaced instructions use a 1-instruction scratch space, so set this
5255 here and override below if/when necessary. */
5257 dsc
->insn_addr
= from
;
5258 dsc
->scratch_base
= to
;
5259 dsc
->cleanup
= NULL
;
5260 dsc
->wrote_to_pc
= 0;
5262 if ((insn
& 0xf0000000) == 0xf0000000)
5263 err
= decode_unconditional (gdbarch
, insn
, regs
, dsc
);
5264 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
5266 case 0x0: case 0x1: case 0x2: case 0x3:
5267 err
= decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
5270 case 0x4: case 0x5: case 0x6:
5271 err
= decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
5275 err
= decode_media (gdbarch
, insn
, dsc
);
5278 case 0x8: case 0x9: case 0xa: case 0xb:
5279 err
= decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
5282 case 0xc: case 0xd: case 0xe: case 0xf:
5283 err
= decode_svc_copro (gdbarch
, insn
, to
, regs
, dsc
);
5288 internal_error (__FILE__
, __LINE__
,
5289 _("arm_process_displaced_insn: Instruction decode error"));
5292 /* Actually set up the scratch space for a displaced instruction. */
5295 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
5296 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
5298 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5300 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5302 /* Poke modified instruction(s). */
5303 for (i
= 0; i
< dsc
->numinsns
; i
++)
5305 if (debug_displaced
)
5306 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn %.8lx at "
5307 "%.8lx\n", (unsigned long) dsc
->modinsn
[i
],
5308 (unsigned long) to
+ i
* 4);
5309 write_memory_unsigned_integer (to
+ i
* 4, 4, byte_order_for_code
,
5313 /* Put breakpoint afterwards. */
5314 write_memory (to
+ dsc
->numinsns
* 4, tdep
->arm_breakpoint
,
5315 tdep
->arm_breakpoint_size
);
5317 if (debug_displaced
)
5318 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
5319 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
5322 /* Entry point for copying an instruction into scratch space for displaced
5325 struct displaced_step_closure
*
5326 arm_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
5327 CORE_ADDR from
, CORE_ADDR to
,
5328 struct regcache
*regs
)
5330 struct displaced_step_closure
*dsc
5331 = xmalloc (sizeof (struct displaced_step_closure
));
5332 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5333 uint32_t insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
5335 if (debug_displaced
)
5336 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
5337 "at %.8lx\n", (unsigned long) insn
,
5338 (unsigned long) from
);
5340 arm_process_displaced_insn (gdbarch
, insn
, from
, to
, regs
, dsc
);
5341 arm_displaced_init_closure (gdbarch
, from
, to
, dsc
);
5346 /* Entry point for cleaning things up after a displaced instruction has been
5350 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
5351 struct displaced_step_closure
*dsc
,
5352 CORE_ADDR from
, CORE_ADDR to
,
5353 struct regcache
*regs
)
5356 dsc
->cleanup (gdbarch
, regs
, dsc
);
5358 if (!dsc
->wrote_to_pc
)
5359 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, dsc
->insn_addr
+ 4);
5362 #include "bfd-in2.h"
5363 #include "libcoff.h"
5366 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
5368 struct gdbarch
*gdbarch
= info
->application_data
;
5370 if (arm_pc_is_thumb (gdbarch
, memaddr
))
5372 static asymbol
*asym
;
5373 static combined_entry_type ce
;
5374 static struct coff_symbol_struct csym
;
5375 static struct bfd fake_bfd
;
5376 static bfd_target fake_target
;
5378 if (csym
.native
== NULL
)
5380 /* Create a fake symbol vector containing a Thumb symbol.
5381 This is solely so that the code in print_insn_little_arm()
5382 and print_insn_big_arm() in opcodes/arm-dis.c will detect
5383 the presence of a Thumb symbol and switch to decoding
5384 Thumb instructions. */
5386 fake_target
.flavour
= bfd_target_coff_flavour
;
5387 fake_bfd
.xvec
= &fake_target
;
5388 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
5390 csym
.symbol
.the_bfd
= &fake_bfd
;
5391 csym
.symbol
.name
= "fake";
5392 asym
= (asymbol
*) & csym
;
5395 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
5396 info
->symbols
= &asym
;
5399 info
->symbols
= NULL
;
5401 if (info
->endian
== BFD_ENDIAN_BIG
)
5402 return print_insn_big_arm (memaddr
, info
);
5404 return print_insn_little_arm (memaddr
, info
);
5407 /* The following define instruction sequences that will cause ARM
5408 cpu's to take an undefined instruction trap. These are used to
5409 signal a breakpoint to GDB.
5411 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
5412 modes. A different instruction is required for each mode. The ARM
5413 cpu's can also be big or little endian. Thus four different
5414 instructions are needed to support all cases.
5416 Note: ARMv4 defines several new instructions that will take the
5417 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
5418 not in fact add the new instructions. The new undefined
5419 instructions in ARMv4 are all instructions that had no defined
5420 behaviour in earlier chips. There is no guarantee that they will
5421 raise an exception, but may be treated as NOP's. In practice, it
5422 may only safe to rely on instructions matching:
5424 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
5425 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
5426 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
5428 Even this may only true if the condition predicate is true. The
5429 following use a condition predicate of ALWAYS so it is always TRUE.
5431 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
5432 and NetBSD all use a software interrupt rather than an undefined
5433 instruction to force a trap. This can be handled by by the
5434 abi-specific code during establishment of the gdbarch vector. */
5436 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
5437 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
5438 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
5439 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
5441 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
5442 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
5443 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
5444 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
5446 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
5447 the program counter value to determine whether a 16-bit or 32-bit
5448 breakpoint should be used. It returns a pointer to a string of
5449 bytes that encode a breakpoint instruction, stores the length of
5450 the string to *lenptr, and adjusts the program counter (if
5451 necessary) to point to the actual memory location where the
5452 breakpoint should be inserted. */
5454 static const unsigned char *
5455 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
5457 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5458 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5460 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
5462 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
5464 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
5465 check whether we are replacing a 32-bit instruction. */
5466 if (tdep
->thumb2_breakpoint
!= NULL
)
5469 if (target_read_memory (*pcptr
, buf
, 2) == 0)
5471 unsigned short inst1
;
5472 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
5473 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
5475 *lenptr
= tdep
->thumb2_breakpoint_size
;
5476 return tdep
->thumb2_breakpoint
;
5481 *lenptr
= tdep
->thumb_breakpoint_size
;
5482 return tdep
->thumb_breakpoint
;
5486 *lenptr
= tdep
->arm_breakpoint_size
;
5487 return tdep
->arm_breakpoint
;
5492 arm_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
5495 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5497 arm_breakpoint_from_pc (gdbarch
, pcptr
, kindptr
);
5499 if (arm_pc_is_thumb (gdbarch
, *pcptr
) && *kindptr
== 4)
5500 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
5501 that this is not confused with a 32-bit ARM breakpoint. */
5505 /* Extract from an array REGBUF containing the (raw) register state a
5506 function return value of type TYPE, and copy that, in virtual
5507 format, into VALBUF. */
5510 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
5513 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
5514 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5516 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
5518 switch (gdbarch_tdep (gdbarch
)->fp_model
)
5522 /* The value is in register F0 in internal format. We need to
5523 extract the raw value and then convert it to the desired
5525 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
5527 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
5528 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
5529 valbuf
, gdbarch_byte_order (gdbarch
));
5533 case ARM_FLOAT_SOFT_FPA
:
5534 case ARM_FLOAT_SOFT_VFP
:
5535 /* ARM_FLOAT_VFP can arise if this is a variadic function so
5536 not using the VFP ABI code. */
5538 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
5539 if (TYPE_LENGTH (type
) > 4)
5540 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
5541 valbuf
+ INT_REGISTER_SIZE
);
5546 (__FILE__
, __LINE__
,
5547 _("arm_extract_return_value: Floating point model not supported"));
5551 else if (TYPE_CODE (type
) == TYPE_CODE_INT
5552 || TYPE_CODE (type
) == TYPE_CODE_CHAR
5553 || TYPE_CODE (type
) == TYPE_CODE_BOOL
5554 || TYPE_CODE (type
) == TYPE_CODE_PTR
5555 || TYPE_CODE (type
) == TYPE_CODE_REF
5556 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
5558 /* If the the type is a plain integer, then the access is
5559 straight-forward. Otherwise we have to play around a bit more. */
5560 int len
= TYPE_LENGTH (type
);
5561 int regno
= ARM_A1_REGNUM
;
5566 /* By using store_unsigned_integer we avoid having to do
5567 anything special for small big-endian values. */
5568 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
5569 store_unsigned_integer (valbuf
,
5570 (len
> INT_REGISTER_SIZE
5571 ? INT_REGISTER_SIZE
: len
),
5573 len
-= INT_REGISTER_SIZE
;
5574 valbuf
+= INT_REGISTER_SIZE
;
5579 /* For a structure or union the behaviour is as if the value had
5580 been stored to word-aligned memory and then loaded into
5581 registers with 32-bit load instruction(s). */
5582 int len
= TYPE_LENGTH (type
);
5583 int regno
= ARM_A1_REGNUM
;
5584 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
5588 regcache_cooked_read (regs
, regno
++, tmpbuf
);
5589 memcpy (valbuf
, tmpbuf
,
5590 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
5591 len
-= INT_REGISTER_SIZE
;
5592 valbuf
+= INT_REGISTER_SIZE
;
5598 /* Will a function return an aggregate type in memory or in a
5599 register? Return 0 if an aggregate type can be returned in a
5600 register, 1 if it must be returned in memory. */
5603 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
5606 enum type_code code
;
5608 CHECK_TYPEDEF (type
);
5610 /* In the ARM ABI, "integer" like aggregate types are returned in
5611 registers. For an aggregate type to be integer like, its size
5612 must be less than or equal to INT_REGISTER_SIZE and the
5613 offset of each addressable subfield must be zero. Note that bit
5614 fields are not addressable, and all addressable subfields of
5615 unions always start at offset zero.
5617 This function is based on the behaviour of GCC 2.95.1.
5618 See: gcc/arm.c: arm_return_in_memory() for details.
5620 Note: All versions of GCC before GCC 2.95.2 do not set up the
5621 parameters correctly for a function returning the following
5622 structure: struct { float f;}; This should be returned in memory,
5623 not a register. Richard Earnshaw sent me a patch, but I do not
5624 know of any way to detect if a function like the above has been
5625 compiled with the correct calling convention. */
5627 /* All aggregate types that won't fit in a register must be returned
5629 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
5634 /* The AAPCS says all aggregates not larger than a word are returned
5636 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
5639 /* The only aggregate types that can be returned in a register are
5640 structs and unions. Arrays must be returned in memory. */
5641 code
= TYPE_CODE (type
);
5642 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
5647 /* Assume all other aggregate types can be returned in a register.
5648 Run a check for structures, unions and arrays. */
5651 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
5654 /* Need to check if this struct/union is "integer" like. For
5655 this to be true, its size must be less than or equal to
5656 INT_REGISTER_SIZE and the offset of each addressable
5657 subfield must be zero. Note that bit fields are not
5658 addressable, and unions always start at offset zero. If any
5659 of the subfields is a floating point type, the struct/union
5660 cannot be an integer type. */
5662 /* For each field in the object, check:
5663 1) Is it FP? --> yes, nRc = 1;
5664 2) Is it addressable (bitpos != 0) and
5665 not packed (bitsize == 0)?
5669 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
5671 enum type_code field_type_code
;
5672 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, i
)));
5674 /* Is it a floating point type field? */
5675 if (field_type_code
== TYPE_CODE_FLT
)
5681 /* If bitpos != 0, then we have to care about it. */
5682 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
5684 /* Bitfields are not addressable. If the field bitsize is
5685 zero, then the field is not packed. Hence it cannot be
5686 a bitfield or any other packed type. */
5687 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
5699 /* Write into appropriate registers a function return value of type
5700 TYPE, given in virtual format. */
5703 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
5704 const gdb_byte
*valbuf
)
5706 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
5707 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5709 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
5711 char buf
[MAX_REGISTER_SIZE
];
5713 switch (gdbarch_tdep (gdbarch
)->fp_model
)
5717 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
5718 gdbarch_byte_order (gdbarch
));
5719 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
5722 case ARM_FLOAT_SOFT_FPA
:
5723 case ARM_FLOAT_SOFT_VFP
:
5724 /* ARM_FLOAT_VFP can arise if this is a variadic function so
5725 not using the VFP ABI code. */
5727 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
5728 if (TYPE_LENGTH (type
) > 4)
5729 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
5730 valbuf
+ INT_REGISTER_SIZE
);
5735 (__FILE__
, __LINE__
,
5736 _("arm_store_return_value: Floating point model not supported"));
5740 else if (TYPE_CODE (type
) == TYPE_CODE_INT
5741 || TYPE_CODE (type
) == TYPE_CODE_CHAR
5742 || TYPE_CODE (type
) == TYPE_CODE_BOOL
5743 || TYPE_CODE (type
) == TYPE_CODE_PTR
5744 || TYPE_CODE (type
) == TYPE_CODE_REF
5745 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
5747 if (TYPE_LENGTH (type
) <= 4)
5749 /* Values of one word or less are zero/sign-extended and
5751 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
5752 LONGEST val
= unpack_long (type
, valbuf
);
5754 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
5755 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
5759 /* Integral values greater than one word are stored in consecutive
5760 registers starting with r0. This will always be a multiple of
5761 the regiser size. */
5762 int len
= TYPE_LENGTH (type
);
5763 int regno
= ARM_A1_REGNUM
;
5767 regcache_cooked_write (regs
, regno
++, valbuf
);
5768 len
-= INT_REGISTER_SIZE
;
5769 valbuf
+= INT_REGISTER_SIZE
;
5775 /* For a structure or union the behaviour is as if the value had
5776 been stored to word-aligned memory and then loaded into
5777 registers with 32-bit load instruction(s). */
5778 int len
= TYPE_LENGTH (type
);
5779 int regno
= ARM_A1_REGNUM
;
5780 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
5784 memcpy (tmpbuf
, valbuf
,
5785 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
5786 regcache_cooked_write (regs
, regno
++, tmpbuf
);
5787 len
-= INT_REGISTER_SIZE
;
5788 valbuf
+= INT_REGISTER_SIZE
;
5794 /* Handle function return values. */
5796 static enum return_value_convention
5797 arm_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
5798 struct type
*valtype
, struct regcache
*regcache
,
5799 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5801 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5802 enum arm_vfp_cprc_base_type vfp_base_type
;
5805 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
5806 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
5808 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
5809 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
5811 for (i
= 0; i
< vfp_base_count
; i
++)
5813 if (reg_char
== 'q')
5816 arm_neon_quad_write (gdbarch
, regcache
, i
,
5817 writebuf
+ i
* unit_length
);
5820 arm_neon_quad_read (gdbarch
, regcache
, i
,
5821 readbuf
+ i
* unit_length
);
5828 sprintf (name_buf
, "%c%d", reg_char
, i
);
5829 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
5832 regcache_cooked_write (regcache
, regnum
,
5833 writebuf
+ i
* unit_length
);
5835 regcache_cooked_read (regcache
, regnum
,
5836 readbuf
+ i
* unit_length
);
5839 return RETURN_VALUE_REGISTER_CONVENTION
;
5842 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
5843 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
5844 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
5846 if (tdep
->struct_return
== pcc_struct_return
5847 || arm_return_in_memory (gdbarch
, valtype
))
5848 return RETURN_VALUE_STRUCT_CONVENTION
;
5852 arm_store_return_value (valtype
, regcache
, writebuf
);
5855 arm_extract_return_value (valtype
, regcache
, readbuf
);
5857 return RETURN_VALUE_REGISTER_CONVENTION
;
5862 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
5864 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5865 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5866 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5868 char buf
[INT_REGISTER_SIZE
];
5870 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
5872 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
5876 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
5880 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
5881 return the target PC. Otherwise return 0. */
5884 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
5888 CORE_ADDR start_addr
;
5890 /* Find the starting address and name of the function containing the PC. */
5891 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5894 /* If PC is in a Thumb call or return stub, return the address of the
5895 target PC, which is in a register. The thunk functions are called
5896 _call_via_xx, where x is the register name. The possible names
5897 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
5898 functions, named __ARM_call_via_r[0-7]. */
5899 if (strncmp (name
, "_call_via_", 10) == 0
5900 || strncmp (name
, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0)
5902 /* Use the name suffix to determine which register contains the
5904 static char *table
[15] =
5905 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5906 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
5909 int offset
= strlen (name
) - 2;
5911 for (regno
= 0; regno
<= 14; regno
++)
5912 if (strcmp (&name
[offset
], table
[regno
]) == 0)
5913 return get_frame_register_unsigned (frame
, regno
);
5916 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
5917 non-interworking calls to foo. We could decode the stubs
5918 to find the target but it's easier to use the symbol table. */
5919 namelen
= strlen (name
);
5920 if (name
[0] == '_' && name
[1] == '_'
5921 && ((namelen
> 2 + strlen ("_from_thumb")
5922 && strncmp (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb",
5923 strlen ("_from_thumb")) == 0)
5924 || (namelen
> 2 + strlen ("_from_arm")
5925 && strncmp (name
+ namelen
- strlen ("_from_arm"), "_from_arm",
5926 strlen ("_from_arm")) == 0)))
5929 int target_len
= namelen
- 2;
5930 struct minimal_symbol
*minsym
;
5931 struct objfile
*objfile
;
5932 struct obj_section
*sec
;
5934 if (name
[namelen
- 1] == 'b')
5935 target_len
-= strlen ("_from_thumb");
5937 target_len
-= strlen ("_from_arm");
5939 target_name
= alloca (target_len
+ 1);
5940 memcpy (target_name
, name
+ 2, target_len
);
5941 target_name
[target_len
] = '\0';
5943 sec
= find_pc_section (pc
);
5944 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
5945 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
5947 return SYMBOL_VALUE_ADDRESS (minsym
);
5952 return 0; /* not a stub */
5956 set_arm_command (char *args
, int from_tty
)
5958 printf_unfiltered (_("\
5959 \"set arm\" must be followed by an apporpriate subcommand.\n"));
5960 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
5964 show_arm_command (char *args
, int from_tty
)
5966 cmd_show_list (showarmcmdlist
, from_tty
, "");
5970 arm_update_current_architecture (void)
5972 struct gdbarch_info info
;
5974 /* If the current architecture is not ARM, we have nothing to do. */
5975 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_arm
)
5978 /* Update the architecture. */
5979 gdbarch_info_init (&info
);
5981 if (!gdbarch_update_p (info
))
5982 internal_error (__FILE__
, __LINE__
, "could not update architecture");
5986 set_fp_model_sfunc (char *args
, int from_tty
,
5987 struct cmd_list_element
*c
)
5989 enum arm_float_model fp_model
;
5991 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
5992 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
5994 arm_fp_model
= fp_model
;
5998 if (fp_model
== ARM_FLOAT_LAST
)
5999 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
6002 arm_update_current_architecture ();
6006 show_fp_model (struct ui_file
*file
, int from_tty
,
6007 struct cmd_list_element
*c
, const char *value
)
6009 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
6011 if (arm_fp_model
== ARM_FLOAT_AUTO
6012 && gdbarch_bfd_arch_info (target_gdbarch
)->arch
== bfd_arch_arm
)
6013 fprintf_filtered (file
, _("\
6014 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
6015 fp_model_strings
[tdep
->fp_model
]);
6017 fprintf_filtered (file
, _("\
6018 The current ARM floating point model is \"%s\".\n"),
6019 fp_model_strings
[arm_fp_model
]);
6023 arm_set_abi (char *args
, int from_tty
,
6024 struct cmd_list_element
*c
)
6026 enum arm_abi_kind arm_abi
;
6028 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
6029 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
6031 arm_abi_global
= arm_abi
;
6035 if (arm_abi
== ARM_ABI_LAST
)
6036 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
6039 arm_update_current_architecture ();
6043 arm_show_abi (struct ui_file
*file
, int from_tty
,
6044 struct cmd_list_element
*c
, const char *value
)
6046 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
6048 if (arm_abi_global
== ARM_ABI_AUTO
6049 && gdbarch_bfd_arch_info (target_gdbarch
)->arch
== bfd_arch_arm
)
6050 fprintf_filtered (file
, _("\
6051 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
6052 arm_abi_strings
[tdep
->arm_abi
]);
6054 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
6059 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
6060 struct cmd_list_element
*c
, const char *value
)
6062 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
6064 fprintf_filtered (file
, _("\
6065 The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"),
6066 arm_fallback_mode_string
);
6070 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
6071 struct cmd_list_element
*c
, const char *value
)
6073 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
6075 fprintf_filtered (file
, _("\
6076 The current execution mode assumed (even when symbols are available) is \"%s\".\n"),
6077 arm_force_mode_string
);
6080 /* If the user changes the register disassembly style used for info
6081 register and other commands, we have to also switch the style used
6082 in opcodes for disassembly output. This function is run in the "set
6083 arm disassembly" command, and does that. */
6086 set_disassembly_style_sfunc (char *args
, int from_tty
,
6087 struct cmd_list_element
*c
)
6089 set_disassembly_style ();
6092 /* Return the ARM register name corresponding to register I. */
6094 arm_register_name (struct gdbarch
*gdbarch
, int i
)
6096 const int num_regs
= gdbarch_num_regs (gdbarch
);
6098 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
6099 && i
>= num_regs
&& i
< num_regs
+ 32)
6101 static const char *const vfp_pseudo_names
[] = {
6102 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
6103 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
6104 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
6105 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
6108 return vfp_pseudo_names
[i
- num_regs
];
6111 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
6112 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
6114 static const char *const neon_pseudo_names
[] = {
6115 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
6116 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
6119 return neon_pseudo_names
[i
- num_regs
- 32];
6122 if (i
>= ARRAY_SIZE (arm_register_names
))
6123 /* These registers are only supported on targets which supply
6124 an XML description. */
6127 return arm_register_names
[i
];
6131 set_disassembly_style (void)
6135 /* Find the style that the user wants. */
6136 for (current
= 0; current
< num_disassembly_options
; current
++)
6137 if (disassembly_style
== valid_disassembly_styles
[current
])
6139 gdb_assert (current
< num_disassembly_options
);
6141 /* Synchronize the disassembler. */
6142 set_arm_regname_option (current
);
6145 /* Test whether the coff symbol specific value corresponds to a Thumb
6149 coff_sym_is_thumb (int val
)
6151 return (val
== C_THUMBEXT
6152 || val
== C_THUMBSTAT
6153 || val
== C_THUMBEXTFUNC
6154 || val
== C_THUMBSTATFUNC
6155 || val
== C_THUMBLABEL
);
6158 /* arm_coff_make_msymbol_special()
6159 arm_elf_make_msymbol_special()
6161 These functions test whether the COFF or ELF symbol corresponds to
6162 an address in thumb code, and set a "special" bit in a minimal
6163 symbol to indicate that it does. */
6166 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
6168 /* Thumb symbols are of type STT_LOPROC, (synonymous with
6170 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
6172 MSYMBOL_SET_SPECIAL (msym
);
6176 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
6178 if (coff_sym_is_thumb (val
))
6179 MSYMBOL_SET_SPECIAL (msym
);
6183 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
6185 struct arm_per_objfile
*data
= arg
;
6188 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
6189 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
6193 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
6196 const char *name
= bfd_asymbol_name (sym
);
6197 struct arm_per_objfile
*data
;
6198 VEC(arm_mapping_symbol_s
) **map_p
;
6199 struct arm_mapping_symbol new_map_sym
;
6201 gdb_assert (name
[0] == '$');
6202 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
6205 data
= objfile_data (objfile
, arm_objfile_data_key
);
6208 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
6209 struct arm_per_objfile
);
6210 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
6211 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
6212 objfile
->obfd
->section_count
,
6213 VEC(arm_mapping_symbol_s
) *);
6215 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
6217 new_map_sym
.value
= sym
->value
;
6218 new_map_sym
.type
= name
[1];
6220 /* Assume that most mapping symbols appear in order of increasing
6221 value. If they were randomly distributed, it would be faster to
6222 always push here and then sort at first use. */
6223 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
6225 struct arm_mapping_symbol
*prev_map_sym
;
6227 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
6228 if (prev_map_sym
->value
>= sym
->value
)
6231 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
6232 arm_compare_mapping_symbols
);
6233 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
6238 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
6242 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
6244 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
6245 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
6247 /* If necessary, set the T bit. */
6250 ULONGEST val
, t_bit
;
6251 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
6252 t_bit
= arm_psr_thumb_bit (gdbarch
);
6253 if (arm_pc_is_thumb (gdbarch
, pc
))
6254 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
6257 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
6262 /* Read the contents of a NEON quad register, by reading from two
6263 double registers. This is used to implement the quad pseudo
6264 registers, and for argument passing in case the quad registers are
6265 missing; vectors are passed in quad registers when using the VFP
6266 ABI, even if a NEON unit is not present. REGNUM is the index of
6267 the quad register, in [0, 15]. */
6270 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
6271 int regnum
, gdb_byte
*buf
)
6274 gdb_byte reg_buf
[8];
6275 int offset
, double_regnum
;
6277 sprintf (name_buf
, "d%d", regnum
<< 1);
6278 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
6281 /* d0 is always the least significant half of q0. */
6282 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6287 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
6288 memcpy (buf
+ offset
, reg_buf
, 8);
6290 offset
= 8 - offset
;
6291 regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
6292 memcpy (buf
+ offset
, reg_buf
, 8);
6296 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
6297 int regnum
, gdb_byte
*buf
)
6299 const int num_regs
= gdbarch_num_regs (gdbarch
);
6301 gdb_byte reg_buf
[8];
6302 int offset
, double_regnum
;
6304 gdb_assert (regnum
>= num_regs
);
6307 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
6308 /* Quad-precision register. */
6309 arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
6312 /* Single-precision register. */
6313 gdb_assert (regnum
< 32);
6315 /* s0 is always the least significant half of d0. */
6316 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6317 offset
= (regnum
& 1) ? 0 : 4;
6319 offset
= (regnum
& 1) ? 4 : 0;
6321 sprintf (name_buf
, "d%d", regnum
>> 1);
6322 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
6325 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
6326 memcpy (buf
, reg_buf
+ offset
, 4);
6330 /* Store the contents of BUF to a NEON quad register, by writing to
6331 two double registers. This is used to implement the quad pseudo
6332 registers, and for argument passing in case the quad registers are
6333 missing; vectors are passed in quad registers when using the VFP
6334 ABI, even if a NEON unit is not present. REGNUM is the index
6335 of the quad register, in [0, 15]. */
6338 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
6339 int regnum
, const gdb_byte
*buf
)
6342 gdb_byte reg_buf
[8];
6343 int offset
, double_regnum
;
6345 sprintf (name_buf
, "d%d", regnum
<< 1);
6346 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
6349 /* d0 is always the least significant half of q0. */
6350 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6355 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
6356 offset
= 8 - offset
;
6357 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
6361 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
6362 int regnum
, const gdb_byte
*buf
)
6364 const int num_regs
= gdbarch_num_regs (gdbarch
);
6366 gdb_byte reg_buf
[8];
6367 int offset
, double_regnum
;
6369 gdb_assert (regnum
>= num_regs
);
6372 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
6373 /* Quad-precision register. */
6374 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
6377 /* Single-precision register. */
6378 gdb_assert (regnum
< 32);
6380 /* s0 is always the least significant half of d0. */
6381 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6382 offset
= (regnum
& 1) ? 0 : 4;
6384 offset
= (regnum
& 1) ? 4 : 0;
6386 sprintf (name_buf
, "d%d", regnum
>> 1);
6387 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
6390 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
6391 memcpy (reg_buf
+ offset
, buf
, 4);
6392 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
6396 static struct value
*
6397 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
6399 const int *reg_p
= baton
;
6400 return value_of_register (*reg_p
, frame
);
6403 static enum gdb_osabi
6404 arm_elf_osabi_sniffer (bfd
*abfd
)
6406 unsigned int elfosabi
;
6407 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
6409 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
6411 if (elfosabi
== ELFOSABI_ARM
)
6412 /* GNU tools use this value. Check note sections in this case,
6414 bfd_map_over_sections (abfd
,
6415 generic_elf_osabi_sniff_abi_tag_sections
,
6418 /* Anything else will be handled by the generic ELF sniffer. */
6423 /* Initialize the current architecture based on INFO. If possible,
6424 re-use an architecture from ARCHES, which is a list of
6425 architectures already created during this debugging session.
6427 Called e.g. at program startup, when reading a core file, and when
6428 reading a binary file. */
6430 static struct gdbarch
*
6431 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6433 struct gdbarch_tdep
*tdep
;
6434 struct gdbarch
*gdbarch
;
6435 struct gdbarch_list
*best_arch
;
6436 enum arm_abi_kind arm_abi
= arm_abi_global
;
6437 enum arm_float_model fp_model
= arm_fp_model
;
6438 struct tdesc_arch_data
*tdesc_data
= NULL
;
6440 int have_vfp_registers
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
6442 int have_fpa_registers
= 1;
6443 const struct target_desc
*tdesc
= info
.target_desc
;
6445 /* If we have an object to base this architecture on, try to determine
6448 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
6450 int ei_osabi
, e_flags
;
6452 switch (bfd_get_flavour (info
.abfd
))
6454 case bfd_target_aout_flavour
:
6455 /* Assume it's an old APCS-style ABI. */
6456 arm_abi
= ARM_ABI_APCS
;
6459 case bfd_target_coff_flavour
:
6460 /* Assume it's an old APCS-style ABI. */
6462 arm_abi
= ARM_ABI_APCS
;
6465 case bfd_target_elf_flavour
:
6466 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
6467 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6469 if (ei_osabi
== ELFOSABI_ARM
)
6471 /* GNU tools used to use this value, but do not for EABI
6472 objects. There's nowhere to tag an EABI version
6473 anyway, so assume APCS. */
6474 arm_abi
= ARM_ABI_APCS
;
6476 else if (ei_osabi
== ELFOSABI_NONE
)
6478 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
6479 int attr_arch
, attr_profile
;
6483 case EF_ARM_EABI_UNKNOWN
:
6484 /* Assume GNU tools. */
6485 arm_abi
= ARM_ABI_APCS
;
6488 case EF_ARM_EABI_VER4
:
6489 case EF_ARM_EABI_VER5
:
6490 arm_abi
= ARM_ABI_AAPCS
;
6491 /* EABI binaries default to VFP float ordering.
6492 They may also contain build attributes that can
6493 be used to identify if the VFP argument-passing
6495 if (fp_model
== ARM_FLOAT_AUTO
)
6498 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
6503 /* "The user intended FP parameter/result
6504 passing to conform to AAPCS, base
6506 fp_model
= ARM_FLOAT_SOFT_VFP
;
6509 /* "The user intended FP parameter/result
6510 passing to conform to AAPCS, VFP
6512 fp_model
= ARM_FLOAT_VFP
;
6515 /* "The user intended FP parameter/result
6516 passing to conform to tool chain-specific
6517 conventions" - we don't know any such
6518 conventions, so leave it as "auto". */
6521 /* Attribute value not mentioned in the
6522 October 2008 ABI, so leave it as
6527 fp_model
= ARM_FLOAT_SOFT_VFP
;
6533 /* Leave it as "auto". */
6534 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
6539 /* Detect M-profile programs. This only works if the
6540 executable file includes build attributes; GCC does
6541 copy them to the executable, but e.g. RealView does
6543 attr_arch
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
6545 attr_profile
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
6546 Tag_CPU_arch_profile
);
6547 /* GCC specifies the profile for v6-M; RealView only
6548 specifies the profile for architectures starting with
6549 V7 (as opposed to architectures with a tag
6550 numerically greater than TAG_CPU_ARCH_V7). */
6551 if (!tdesc_has_registers (tdesc
)
6552 && (attr_arch
== TAG_CPU_ARCH_V6_M
6553 || attr_arch
== TAG_CPU_ARCH_V6S_M
6554 || attr_profile
== 'M'))
6555 tdesc
= tdesc_arm_with_m
;
6559 if (fp_model
== ARM_FLOAT_AUTO
)
6561 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6563 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
6566 /* Leave it as "auto". Strictly speaking this case
6567 means FPA, but almost nobody uses that now, and
6568 many toolchains fail to set the appropriate bits
6569 for the floating-point model they use. */
6571 case EF_ARM_SOFT_FLOAT
:
6572 fp_model
= ARM_FLOAT_SOFT_FPA
;
6574 case EF_ARM_VFP_FLOAT
:
6575 fp_model
= ARM_FLOAT_VFP
;
6577 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
6578 fp_model
= ARM_FLOAT_SOFT_VFP
;
6583 if (e_flags
& EF_ARM_BE8
)
6584 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
6589 /* Leave it as "auto". */
6594 /* Check any target description for validity. */
6595 if (tdesc_has_registers (tdesc
))
6597 /* For most registers we require GDB's default names; but also allow
6598 the numeric names for sp / lr / pc, as a convenience. */
6599 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
6600 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
6601 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
6603 const struct tdesc_feature
*feature
;
6606 feature
= tdesc_find_feature (tdesc
,
6607 "org.gnu.gdb.arm.core");
6608 if (feature
== NULL
)
6610 feature
= tdesc_find_feature (tdesc
,
6611 "org.gnu.gdb.arm.m-profile");
6612 if (feature
== NULL
)
6618 tdesc_data
= tdesc_data_alloc ();
6621 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
6622 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
6623 arm_register_names
[i
]);
6624 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6627 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6630 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6634 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6635 ARM_PS_REGNUM
, "xpsr");
6637 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6638 ARM_PS_REGNUM
, "cpsr");
6642 tdesc_data_cleanup (tdesc_data
);
6646 feature
= tdesc_find_feature (tdesc
,
6647 "org.gnu.gdb.arm.fpa");
6648 if (feature
!= NULL
)
6651 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
6652 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
6653 arm_register_names
[i
]);
6656 tdesc_data_cleanup (tdesc_data
);
6661 have_fpa_registers
= 0;
6663 feature
= tdesc_find_feature (tdesc
,
6664 "org.gnu.gdb.xscale.iwmmxt");
6665 if (feature
!= NULL
)
6667 static const char *const iwmmxt_names
[] = {
6668 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
6669 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
6670 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
6671 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
6675 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
6677 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
6678 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
6680 /* Check for the control registers, but do not fail if they
6682 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
6683 tdesc_numbered_register (feature
, tdesc_data
, i
,
6684 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
6686 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
6688 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
6689 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
6693 tdesc_data_cleanup (tdesc_data
);
6698 /* If we have a VFP unit, check whether the single precision registers
6699 are present. If not, then we will synthesize them as pseudo
6701 feature
= tdesc_find_feature (tdesc
,
6702 "org.gnu.gdb.arm.vfp");
6703 if (feature
!= NULL
)
6705 static const char *const vfp_double_names
[] = {
6706 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
6707 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
6708 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
6709 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
6712 /* Require the double precision registers. There must be either
6715 for (i
= 0; i
< 32; i
++)
6717 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6719 vfp_double_names
[i
]);
6724 if (!valid_p
&& i
!= 16)
6726 tdesc_data_cleanup (tdesc_data
);
6730 if (tdesc_unnumbered_register (feature
, "s0") == 0)
6731 have_vfp_pseudos
= 1;
6733 have_vfp_registers
= 1;
6735 /* If we have VFP, also check for NEON. The architecture allows
6736 NEON without VFP (integer vector operations only), but GDB
6737 does not support that. */
6738 feature
= tdesc_find_feature (tdesc
,
6739 "org.gnu.gdb.arm.neon");
6740 if (feature
!= NULL
)
6742 /* NEON requires 32 double-precision registers. */
6745 tdesc_data_cleanup (tdesc_data
);
6749 /* If there are quad registers defined by the stub, use
6750 their type; otherwise (normally) provide them with
6751 the default type. */
6752 if (tdesc_unnumbered_register (feature
, "q0") == 0)
6753 have_neon_pseudos
= 1;
6760 /* If there is already a candidate, use it. */
6761 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
6763 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
6765 if (arm_abi
!= ARM_ABI_AUTO
6766 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
6769 if (fp_model
!= ARM_FLOAT_AUTO
6770 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
6773 /* There are various other properties in tdep that we do not
6774 need to check here: those derived from a target description,
6775 since gdbarches with a different target description are
6776 automatically disqualified. */
6778 /* Do check is_m, though, since it might come from the binary. */
6779 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
6782 /* Found a match. */
6786 if (best_arch
!= NULL
)
6788 if (tdesc_data
!= NULL
)
6789 tdesc_data_cleanup (tdesc_data
);
6790 return best_arch
->gdbarch
;
6793 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
6794 gdbarch
= gdbarch_alloc (&info
, tdep
);
6796 /* Record additional information about the architecture we are defining.
6797 These are gdbarch discriminators, like the OSABI. */
6798 tdep
->arm_abi
= arm_abi
;
6799 tdep
->fp_model
= fp_model
;
6801 tdep
->have_fpa_registers
= have_fpa_registers
;
6802 tdep
->have_vfp_registers
= have_vfp_registers
;
6803 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
6804 tdep
->have_neon_pseudos
= have_neon_pseudos
;
6805 tdep
->have_neon
= have_neon
;
6808 switch (info
.byte_order_for_code
)
6810 case BFD_ENDIAN_BIG
:
6811 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
6812 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
6813 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
6814 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
6818 case BFD_ENDIAN_LITTLE
:
6819 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
6820 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
6821 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
6822 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
6827 internal_error (__FILE__
, __LINE__
,
6828 _("arm_gdbarch_init: bad byte order for float format"));
6831 /* On ARM targets char defaults to unsigned. */
6832 set_gdbarch_char_signed (gdbarch
, 0);
6834 /* Note: for displaced stepping, this includes the breakpoint, and one word
6835 of additional scratch space. This setting isn't used for anything beside
6836 displaced stepping at present. */
6837 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
6839 /* This should be low enough for everything. */
6840 tdep
->lowest_pc
= 0x20;
6841 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
6843 /* The default, for both APCS and AAPCS, is to return small
6844 structures in registers. */
6845 tdep
->struct_return
= reg_struct_return
;
6847 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
6848 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
6850 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
6852 /* Frame handling. */
6853 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
6854 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
6855 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
6857 frame_base_set_default (gdbarch
, &arm_normal_base
);
6859 /* Address manipulation. */
6860 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
6861 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
6863 /* Advance PC across function entry code. */
6864 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
6866 /* Skip trampolines. */
6867 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
6869 /* The stack grows downward. */
6870 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6872 /* Breakpoint manipulation. */
6873 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
6874 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
6875 arm_remote_breakpoint_from_pc
);
6877 /* Information about registers, etc. */
6878 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
6879 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
6880 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
6881 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
6882 set_gdbarch_register_type (gdbarch
, arm_register_type
);
6884 /* This "info float" is FPA-specific. Use the generic version if we
6886 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
6887 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
6889 /* Internal <-> external register number maps. */
6890 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
6891 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
6893 set_gdbarch_register_name (gdbarch
, arm_register_name
);
6895 /* Returning results. */
6896 set_gdbarch_return_value (gdbarch
, arm_return_value
);
6899 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
6901 /* Minsymbol frobbing. */
6902 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
6903 set_gdbarch_coff_make_msymbol_special (gdbarch
,
6904 arm_coff_make_msymbol_special
);
6905 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
6907 /* Thumb-2 IT block support. */
6908 set_gdbarch_adjust_breakpoint_address (gdbarch
,
6909 arm_adjust_breakpoint_address
);
6911 /* Virtual tables. */
6912 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6914 /* Hook in the ABI-specific overrides, if they have been registered. */
6915 gdbarch_init_osabi (info
, gdbarch
);
6917 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
6919 /* Add some default predicates. */
6920 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
6921 dwarf2_append_unwinders (gdbarch
);
6922 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
6924 /* Now we have tuned the configuration, set a few final things,
6925 based on what the OS ABI has told us. */
6927 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
6928 binaries are always marked. */
6929 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
6930 tdep
->arm_abi
= ARM_ABI_APCS
;
6932 /* We used to default to FPA for generic ARM, but almost nobody
6933 uses that now, and we now provide a way for the user to force
6934 the model. So default to the most useful variant. */
6935 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
6936 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
6938 if (tdep
->jb_pc
>= 0)
6939 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
6941 /* Floating point sizes and format. */
6942 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
6943 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
6945 set_gdbarch_double_format
6946 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
6947 set_gdbarch_long_double_format
6948 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
6952 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
6953 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
6956 if (have_vfp_pseudos
)
6958 /* NOTE: These are the only pseudo registers used by
6959 the ARM target at the moment. If more are added, a
6960 little more care in numbering will be needed. */
6962 int num_pseudos
= 32;
6963 if (have_neon_pseudos
)
6965 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
6966 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
6967 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
6972 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
6974 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
6976 /* Override tdesc_register_type to adjust the types of VFP
6977 registers for NEON. */
6978 set_gdbarch_register_type (gdbarch
, arm_register_type
);
6981 /* Add standard register aliases. We add aliases even for those
6982 nanes which are used by the current architecture - it's simpler,
6983 and does no harm, since nothing ever lists user registers. */
6984 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
6985 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
6986 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
6992 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6994 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6999 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
7000 (unsigned long) tdep
->lowest_pc
);
7003 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
7006 _initialize_arm_tdep (void)
7008 struct ui_file
*stb
;
7010 struct cmd_list_element
*new_set
, *new_show
;
7011 const char *setname
;
7012 const char *setdesc
;
7013 const char *const *regnames
;
7015 static char *helptext
;
7016 char regdesc
[1024], *rdptr
= regdesc
;
7017 size_t rest
= sizeof (regdesc
);
7019 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
7021 arm_objfile_data_key
7022 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
7024 /* Register an ELF OS ABI sniffer for ARM binaries. */
7025 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
7026 bfd_target_elf_flavour
,
7027 arm_elf_osabi_sniffer
);
7029 /* Initialize the standard target descriptions. */
7030 initialize_tdesc_arm_with_m ();
7032 /* Get the number of possible sets of register names defined in opcodes. */
7033 num_disassembly_options
= get_arm_regname_num_options ();
7035 /* Add root prefix command for all "set arm"/"show arm" commands. */
7036 add_prefix_cmd ("arm", no_class
, set_arm_command
,
7037 _("Various ARM-specific commands."),
7038 &setarmcmdlist
, "set arm ", 0, &setlist
);
7040 add_prefix_cmd ("arm", no_class
, show_arm_command
,
7041 _("Various ARM-specific commands."),
7042 &showarmcmdlist
, "show arm ", 0, &showlist
);
7044 /* Sync the opcode insn printer with our register viewer. */
7045 parse_arm_disassembler_option ("reg-names-std");
7047 /* Initialize the array that will be passed to
7048 add_setshow_enum_cmd(). */
7049 valid_disassembly_styles
7050 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
7051 for (i
= 0; i
< num_disassembly_options
; i
++)
7053 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
7054 valid_disassembly_styles
[i
] = setname
;
7055 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
7058 /* When we find the default names, tell the disassembler to use
7060 if (!strcmp (setname
, "std"))
7062 disassembly_style
= setname
;
7063 set_arm_regname_option (i
);
7066 /* Mark the end of valid options. */
7067 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
7069 /* Create the help text. */
7070 stb
= mem_fileopen ();
7071 fprintf_unfiltered (stb
, "%s%s%s",
7072 _("The valid values are:\n"),
7074 _("The default is \"std\"."));
7075 helptext
= ui_file_xstrdup (stb
, NULL
);
7076 ui_file_delete (stb
);
7078 add_setshow_enum_cmd("disassembler", no_class
,
7079 valid_disassembly_styles
, &disassembly_style
,
7080 _("Set the disassembly style."),
7081 _("Show the disassembly style."),
7083 set_disassembly_style_sfunc
,
7084 NULL
, /* FIXME: i18n: The disassembly style is \"%s\". */
7085 &setarmcmdlist
, &showarmcmdlist
);
7087 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
7088 _("Set usage of ARM 32-bit mode."),
7089 _("Show usage of ARM 32-bit mode."),
7090 _("When off, a 26-bit PC will be used."),
7092 NULL
, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
7093 &setarmcmdlist
, &showarmcmdlist
);
7095 /* Add a command to allow the user to force the FPU model. */
7096 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
7097 _("Set the floating point type."),
7098 _("Show the floating point type."),
7099 _("auto - Determine the FP typefrom the OS-ABI.\n\
7100 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
7101 fpa - FPA co-processor (GCC compiled).\n\
7102 softvfp - Software FP with pure-endian doubles.\n\
7103 vfp - VFP co-processor."),
7104 set_fp_model_sfunc
, show_fp_model
,
7105 &setarmcmdlist
, &showarmcmdlist
);
7107 /* Add a command to allow the user to force the ABI. */
7108 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
7111 NULL
, arm_set_abi
, arm_show_abi
,
7112 &setarmcmdlist
, &showarmcmdlist
);
7114 /* Add two commands to allow the user to force the assumed
7116 add_setshow_enum_cmd ("fallback-mode", class_support
,
7117 arm_mode_strings
, &arm_fallback_mode_string
,
7118 _("Set the mode assumed when symbols are unavailable."),
7119 _("Show the mode assumed when symbols are unavailable."),
7120 NULL
, NULL
, arm_show_fallback_mode
,
7121 &setarmcmdlist
, &showarmcmdlist
);
7122 add_setshow_enum_cmd ("force-mode", class_support
,
7123 arm_mode_strings
, &arm_force_mode_string
,
7124 _("Set the mode assumed even when symbols are available."),
7125 _("Show the mode assumed even when symbols are available."),
7126 NULL
, NULL
, arm_show_force_mode
,
7127 &setarmcmdlist
, &showarmcmdlist
);
7129 /* Debugging flag. */
7130 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
7131 _("Set ARM debugging."),
7132 _("Show ARM debugging."),
7133 _("When on, arm-specific debugging is enabled."),
7135 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
7136 &setdebuglist
, &showdebuglist
);