1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2014 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
31 #include "reggroups.h"
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "gdb/sim-arm.h"
52 #include "coff/internal.h"
58 #include "record-full.h"
60 #include "features/arm-with-m.c"
61 #include "features/arm-with-m-fpa-layout.c"
62 #include "features/arm-with-m-vfp-d16.c"
63 #include "features/arm-with-iwmmxt.c"
64 #include "features/arm-with-vfpv2.c"
65 #include "features/arm-with-vfpv3.c"
66 #include "features/arm-with-neon.c"
70 /* Macros for setting and testing a bit in a minimal symbol that marks
71 it as Thumb function. The MSB of the minimal symbol's "info" field
72 is used for this purpose.
74 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
75 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
77 #define MSYMBOL_SET_SPECIAL(msym) \
78 MSYMBOL_TARGET_FLAG_1 (msym) = 1
80 #define MSYMBOL_IS_SPECIAL(msym) \
81 MSYMBOL_TARGET_FLAG_1 (msym)
83 /* Per-objfile data used for mapping symbols. */
84 static const struct objfile_data
*arm_objfile_data_key
;
86 struct arm_mapping_symbol
91 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
92 DEF_VEC_O(arm_mapping_symbol_s
);
94 struct arm_per_objfile
96 VEC(arm_mapping_symbol_s
) **section_maps
;
99 /* The list of available "set arm ..." and "show arm ..." commands. */
100 static struct cmd_list_element
*setarmcmdlist
= NULL
;
101 static struct cmd_list_element
*showarmcmdlist
= NULL
;
103 /* The type of floating-point to use. Keep this in sync with enum
104 arm_float_model, and the help string in _initialize_arm_tdep. */
105 static const char *const fp_model_strings
[] =
115 /* A variable that can be configured by the user. */
116 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
117 static const char *current_fp_model
= "auto";
119 /* The ABI to use. Keep this in sync with arm_abi_kind. */
120 static const char *const arm_abi_strings
[] =
128 /* A variable that can be configured by the user. */
129 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
130 static const char *arm_abi_string
= "auto";
132 /* The execution mode to assume. */
133 static const char *const arm_mode_strings
[] =
141 static const char *arm_fallback_mode_string
= "auto";
142 static const char *arm_force_mode_string
= "auto";
144 /* Internal override of the execution mode. -1 means no override,
145 0 means override to ARM mode, 1 means override to Thumb mode.
146 The effect is the same as if arm_force_mode has been set by the
147 user (except the internal override has precedence over a user's
148 arm_force_mode override). */
149 static int arm_override_mode
= -1;
151 /* Number of different reg name sets (options). */
152 static int num_disassembly_options
;
154 /* The standard register names, and all the valid aliases for them. Note
155 that `fp', `sp' and `pc' are not added in this alias list, because they
156 have been added as builtin user registers in
157 std-regs.c:_initialize_frame_reg. */
162 } arm_register_aliases
[] = {
163 /* Basic register numbers. */
180 /* Synonyms (argument and variable registers). */
193 /* Other platform-specific names for r9. */
199 /* Names used by GCC (not listed in the ARM EABI). */
201 /* A special name from the older ATPCS. */
205 static const char *const arm_register_names
[] =
206 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
207 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
208 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
209 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
210 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
211 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
212 "fps", "cpsr" }; /* 24 25 */
214 /* Valid register name styles. */
215 static const char **valid_disassembly_styles
;
217 /* Disassembly style to use. Default to "std" register names. */
218 static const char *disassembly_style
;
220 /* This is used to keep the bfd arch_info in sync with the disassembly
222 static void set_disassembly_style_sfunc(char *, int,
223 struct cmd_list_element
*);
224 static void set_disassembly_style (void);
226 static void convert_from_extended (const struct floatformat
*, const void *,
228 static void convert_to_extended (const struct floatformat
*, void *,
231 static enum register_status
arm_neon_quad_read (struct gdbarch
*gdbarch
,
232 struct regcache
*regcache
,
233 int regnum
, gdb_byte
*buf
);
234 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
235 struct regcache
*regcache
,
236 int regnum
, const gdb_byte
*buf
);
238 static int thumb_insn_size (unsigned short inst1
);
240 struct arm_prologue_cache
242 /* The stack pointer at the time this frame was created; i.e. the
243 caller's stack pointer when this function was called. It is used
244 to identify this frame. */
247 /* The frame base for this frame is just prev_sp - frame size.
248 FRAMESIZE is the distance from the frame pointer to the
249 initial stack pointer. */
253 /* The register used to hold the frame pointer for this frame. */
256 /* Saved register offsets. */
257 struct trad_frame_saved_reg
*saved_regs
;
260 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
261 CORE_ADDR prologue_start
,
262 CORE_ADDR prologue_end
,
263 struct arm_prologue_cache
*cache
);
265 /* Architecture version for displaced stepping. This effects the behaviour of
266 certain instructions, and really should not be hard-wired. */
268 #define DISPLACED_STEPPING_ARCH_VERSION 5
270 /* Addresses for calling Thumb functions have the bit 0 set.
271 Here are some macros to test, set, or clear bit 0 of addresses. */
272 #define IS_THUMB_ADDR(addr) ((addr) & 1)
273 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
274 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
276 /* Set to true if the 32-bit mode is in use. */
280 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
283 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
285 if (gdbarch_tdep (gdbarch
)->is_m
)
291 /* Determine if FRAME is executing in Thumb mode. */
294 arm_frame_is_thumb (struct frame_info
*frame
)
297 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
299 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
300 directly (from a signal frame or dummy frame) or by interpreting
301 the saved LR (from a prologue or DWARF frame). So consult it and
302 trust the unwinders. */
303 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
305 return (cpsr
& t_bit
) != 0;
308 /* Callback for VEC_lower_bound. */
311 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
312 const struct arm_mapping_symbol
*rhs
)
314 return lhs
->value
< rhs
->value
;
317 /* Search for the mapping symbol covering MEMADDR. If one is found,
318 return its type. Otherwise, return 0. If START is non-NULL,
319 set *START to the location of the mapping symbol. */
322 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
324 struct obj_section
*sec
;
326 /* If there are mapping symbols, consult them. */
327 sec
= find_pc_section (memaddr
);
330 struct arm_per_objfile
*data
;
331 VEC(arm_mapping_symbol_s
) *map
;
332 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
336 data
= objfile_data (sec
->objfile
, arm_objfile_data_key
);
339 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
340 if (!VEC_empty (arm_mapping_symbol_s
, map
))
342 struct arm_mapping_symbol
*map_sym
;
344 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
345 arm_compare_mapping_symbols
);
347 /* VEC_lower_bound finds the earliest ordered insertion
348 point. If the following symbol starts at this exact
349 address, we use that; otherwise, the preceding
350 mapping symbol covers this address. */
351 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
353 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
354 if (map_sym
->value
== map_key
.value
)
357 *start
= map_sym
->value
+ obj_section_addr (sec
);
358 return map_sym
->type
;
364 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
366 *start
= map_sym
->value
+ obj_section_addr (sec
);
367 return map_sym
->type
;
376 /* Determine if the program counter specified in MEMADDR is in a Thumb
377 function. This function should be called for addresses unrelated to
378 any executing frame; otherwise, prefer arm_frame_is_thumb. */
381 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
383 struct bound_minimal_symbol sym
;
385 struct displaced_step_closure
* dsc
386 = get_displaced_step_closure_by_addr(memaddr
);
388 /* If checking the mode of displaced instruction in copy area, the mode
389 should be determined by instruction on the original address. */
393 fprintf_unfiltered (gdb_stdlog
,
394 "displaced: check mode of %.8lx instead of %.8lx\n",
395 (unsigned long) dsc
->insn_addr
,
396 (unsigned long) memaddr
);
397 memaddr
= dsc
->insn_addr
;
400 /* If bit 0 of the address is set, assume this is a Thumb address. */
401 if (IS_THUMB_ADDR (memaddr
))
404 /* Respect internal mode override if active. */
405 if (arm_override_mode
!= -1)
406 return arm_override_mode
;
408 /* If the user wants to override the symbol table, let him. */
409 if (strcmp (arm_force_mode_string
, "arm") == 0)
411 if (strcmp (arm_force_mode_string
, "thumb") == 0)
414 /* ARM v6-M and v7-M are always in Thumb mode. */
415 if (gdbarch_tdep (gdbarch
)->is_m
)
418 /* If there are mapping symbols, consult them. */
419 type
= arm_find_mapping_symbol (memaddr
, NULL
);
423 /* Thumb functions have a "special" bit set in minimal symbols. */
424 sym
= lookup_minimal_symbol_by_pc (memaddr
);
426 return (MSYMBOL_IS_SPECIAL (sym
.minsym
));
428 /* If the user wants to override the fallback mode, let them. */
429 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
431 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
434 /* If we couldn't find any symbol, but we're talking to a running
435 target, then trust the current value of $cpsr. This lets
436 "display/i $pc" always show the correct mode (though if there is
437 a symbol table we will not reach here, so it still may not be
438 displayed in the mode it will be executed). */
439 if (target_has_registers
)
440 return arm_frame_is_thumb (get_current_frame ());
442 /* Otherwise we're out of luck; we assume ARM. */
446 /* Remove useless bits from addresses in a running program. */
448 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
450 /* On M-profile devices, do not strip the low bit from EXC_RETURN
451 (the magic exception return address). */
452 if (gdbarch_tdep (gdbarch
)->is_m
453 && (val
& 0xfffffff0) == 0xfffffff0)
457 return UNMAKE_THUMB_ADDR (val
);
459 return (val
& 0x03fffffc);
462 /* Return 1 if PC is the start of a compiler helper function which
463 can be safely ignored during prologue skipping. IS_THUMB is true
464 if the function is known to be a Thumb function due to the way it
467 skip_prologue_function (struct gdbarch
*gdbarch
, CORE_ADDR pc
, int is_thumb
)
469 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
470 struct bound_minimal_symbol msym
;
472 msym
= lookup_minimal_symbol_by_pc (pc
);
473 if (msym
.minsym
!= NULL
474 && BMSYMBOL_VALUE_ADDRESS (msym
) == pc
475 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
)
477 const char *name
= MSYMBOL_LINKAGE_NAME (msym
.minsym
);
479 /* The GNU linker's Thumb call stub to foo is named
481 if (strstr (name
, "_from_thumb") != NULL
)
484 /* On soft-float targets, __truncdfsf2 is called to convert promoted
485 arguments to their argument types in non-prototyped
487 if (strncmp (name
, "__truncdfsf2", strlen ("__truncdfsf2")) == 0)
489 if (strncmp (name
, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
492 /* Internal functions related to thread-local storage. */
493 if (strncmp (name
, "__tls_get_addr", strlen ("__tls_get_addr")) == 0)
495 if (strncmp (name
, "__aeabi_read_tp", strlen ("__aeabi_read_tp")) == 0)
500 /* If we run against a stripped glibc, we may be unable to identify
501 special functions by name. Check for one important case,
502 __aeabi_read_tp, by comparing the *code* against the default
503 implementation (this is hand-written ARM assembler in glibc). */
506 && read_memory_unsigned_integer (pc
, 4, byte_order_for_code
)
507 == 0xe3e00a0f /* mov r0, #0xffff0fff */
508 && read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
)
509 == 0xe240f01f) /* sub pc, r0, #31 */
516 /* Support routines for instruction parsing. */
517 #define submask(x) ((1L << ((x) + 1)) - 1)
518 #define bit(obj,st) (((obj) >> (st)) & 1)
519 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
520 #define sbits(obj,st,fn) \
521 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
522 #define BranchDest(addr,instr) \
523 ((CORE_ADDR) (((unsigned long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
525 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
526 the first 16-bit of instruction, and INSN2 is the second 16-bit of
528 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
529 ((bits ((insn1), 0, 3) << 12) \
530 | (bits ((insn1), 10, 10) << 11) \
531 | (bits ((insn2), 12, 14) << 8) \
532 | bits ((insn2), 0, 7))
534 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
535 the 32-bit instruction. */
536 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
537 ((bits ((insn), 16, 19) << 12) \
538 | bits ((insn), 0, 11))
540 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
543 thumb_expand_immediate (unsigned int imm
)
545 unsigned int count
= imm
>> 7;
553 return (imm
& 0xff) | ((imm
& 0xff) << 16);
555 return ((imm
& 0xff) << 8) | ((imm
& 0xff) << 24);
557 return (imm
& 0xff) | ((imm
& 0xff) << 8)
558 | ((imm
& 0xff) << 16) | ((imm
& 0xff) << 24);
561 return (0x80 | (imm
& 0x7f)) << (32 - count
);
564 /* Return 1 if the 16-bit Thumb instruction INST might change
565 control flow, 0 otherwise. */
568 thumb_instruction_changes_pc (unsigned short inst
)
570 if ((inst
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
573 if ((inst
& 0xf000) == 0xd000) /* conditional branch */
576 if ((inst
& 0xf800) == 0xe000) /* unconditional branch */
579 if ((inst
& 0xff00) == 0x4700) /* bx REG, blx REG */
582 if ((inst
& 0xff87) == 0x4687) /* mov pc, REG */
585 if ((inst
& 0xf500) == 0xb100) /* CBNZ or CBZ. */
591 /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
592 might change control flow, 0 otherwise. */
595 thumb2_instruction_changes_pc (unsigned short inst1
, unsigned short inst2
)
597 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
599 /* Branches and miscellaneous control instructions. */
601 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
606 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
608 /* SUBS PC, LR, #imm8. */
611 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
613 /* Conditional branch. */
620 if ((inst1
& 0xfe50) == 0xe810)
622 /* Load multiple or RFE. */
624 if (bit (inst1
, 7) && !bit (inst1
, 8))
630 else if (!bit (inst1
, 7) && bit (inst1
, 8))
636 else if (bit (inst1
, 7) && bit (inst1
, 8))
641 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
650 if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
652 /* MOV PC or MOVS PC. */
656 if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
659 if (bits (inst1
, 0, 3) == 15)
665 if ((inst2
& 0x0fc0) == 0x0000)
671 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
677 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
686 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
687 epilogue, 0 otherwise. */
690 thumb_instruction_restores_sp (unsigned short insn
)
692 return (insn
== 0x46bd /* mov sp, r7 */
693 || (insn
& 0xff80) == 0xb000 /* add sp, imm */
694 || (insn
& 0xfe00) == 0xbc00); /* pop <registers> */
697 /* Analyze a Thumb prologue, looking for a recognizable stack frame
698 and frame pointer. Scan until we encounter a store that could
699 clobber the stack frame unexpectedly, or an unknown instruction.
700 Return the last address which is definitely safe to skip for an
701 initial breakpoint. */
704 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
705 CORE_ADDR start
, CORE_ADDR limit
,
706 struct arm_prologue_cache
*cache
)
708 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
709 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
712 struct pv_area
*stack
;
713 struct cleanup
*back_to
;
715 CORE_ADDR unrecognized_pc
= 0;
717 for (i
= 0; i
< 16; i
++)
718 regs
[i
] = pv_register (i
, 0);
719 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
720 back_to
= make_cleanup_free_pv_area (stack
);
722 while (start
< limit
)
726 insn
= read_memory_unsigned_integer (start
, 2, byte_order_for_code
);
728 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
733 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
736 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
737 whether to save LR (R14). */
738 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
740 /* Calculate offsets of saved R0-R7 and LR. */
741 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
742 if (mask
& (1 << regno
))
744 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
746 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
749 else if ((insn
& 0xff80) == 0xb080) /* sub sp, #imm */
751 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
752 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
755 else if (thumb_instruction_restores_sp (insn
))
757 /* Don't scan past the epilogue. */
760 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
761 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
763 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
764 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
765 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
767 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
768 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
769 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
771 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
772 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
773 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
774 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
775 regs
[bits (insn
, 6, 8)]);
776 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
777 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
779 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
780 int rm
= bits (insn
, 3, 6);
781 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
783 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
785 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
786 int src_reg
= (insn
& 0x78) >> 3;
787 regs
[dst_reg
] = regs
[src_reg
];
789 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
791 /* Handle stores to the stack. Normally pushes are used,
792 but with GCC -mtpcs-frame, there may be other stores
793 in the prologue to create the frame. */
794 int regno
= (insn
>> 8) & 0x7;
797 offset
= (insn
& 0xff) << 2;
798 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
800 if (pv_area_store_would_trash (stack
, addr
))
803 pv_area_store (stack
, addr
, 4, regs
[regno
]);
805 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
807 int rd
= bits (insn
, 0, 2);
808 int rn
= bits (insn
, 3, 5);
811 offset
= bits (insn
, 6, 10) << 2;
812 addr
= pv_add_constant (regs
[rn
], offset
);
814 if (pv_area_store_would_trash (stack
, addr
))
817 pv_area_store (stack
, addr
, 4, regs
[rd
]);
819 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
820 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
821 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
822 /* Ignore stores of argument registers to the stack. */
824 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
825 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
826 /* Ignore block loads from the stack, potentially copying
827 parameters from memory. */
829 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
830 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
831 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
832 /* Similarly ignore single loads from the stack. */
834 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
835 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
836 /* Skip register copies, i.e. saves to another register
837 instead of the stack. */
839 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
840 /* Recognize constant loads; even with small stacks these are necessary
842 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
843 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
845 /* Constant pool loads, for the same reason. */
846 unsigned int constant
;
849 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
850 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
851 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
853 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instructions. */
855 unsigned short inst2
;
857 inst2
= read_memory_unsigned_integer (start
+ 2, 2,
858 byte_order_for_code
);
860 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
862 /* BL, BLX. Allow some special function calls when
863 skipping the prologue; GCC generates these before
864 storing arguments to the stack. */
866 int j1
, j2
, imm1
, imm2
;
868 imm1
= sbits (insn
, 0, 10);
869 imm2
= bits (inst2
, 0, 10);
870 j1
= bit (inst2
, 13);
871 j2
= bit (inst2
, 11);
873 offset
= ((imm1
<< 12) + (imm2
<< 1));
874 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
876 nextpc
= start
+ 4 + offset
;
877 /* For BLX make sure to clear the low bits. */
878 if (bit (inst2
, 12) == 0)
879 nextpc
= nextpc
& 0xfffffffc;
881 if (!skip_prologue_function (gdbarch
, nextpc
,
882 bit (inst2
, 12) != 0))
886 else if ((insn
& 0xffd0) == 0xe900 /* stmdb Rn{!},
888 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
890 pv_t addr
= regs
[bits (insn
, 0, 3)];
893 if (pv_area_store_would_trash (stack
, addr
))
896 /* Calculate offsets of saved registers. */
897 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
898 if (inst2
& (1 << regno
))
900 addr
= pv_add_constant (addr
, -4);
901 pv_area_store (stack
, addr
, 4, regs
[regno
]);
905 regs
[bits (insn
, 0, 3)] = addr
;
908 else if ((insn
& 0xff50) == 0xe940 /* strd Rt, Rt2,
910 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
912 int regno1
= bits (inst2
, 12, 15);
913 int regno2
= bits (inst2
, 8, 11);
914 pv_t addr
= regs
[bits (insn
, 0, 3)];
916 offset
= inst2
& 0xff;
918 addr
= pv_add_constant (addr
, offset
);
920 addr
= pv_add_constant (addr
, -offset
);
922 if (pv_area_store_would_trash (stack
, addr
))
925 pv_area_store (stack
, addr
, 4, regs
[regno1
]);
926 pv_area_store (stack
, pv_add_constant (addr
, 4),
930 regs
[bits (insn
, 0, 3)] = addr
;
933 else if ((insn
& 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
934 && (inst2
& 0x0c00) == 0x0c00
935 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
937 int regno
= bits (inst2
, 12, 15);
938 pv_t addr
= regs
[bits (insn
, 0, 3)];
940 offset
= inst2
& 0xff;
942 addr
= pv_add_constant (addr
, offset
);
944 addr
= pv_add_constant (addr
, -offset
);
946 if (pv_area_store_would_trash (stack
, addr
))
949 pv_area_store (stack
, addr
, 4, regs
[regno
]);
952 regs
[bits (insn
, 0, 3)] = addr
;
955 else if ((insn
& 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
956 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
958 int regno
= bits (inst2
, 12, 15);
961 offset
= inst2
& 0xfff;
962 addr
= pv_add_constant (regs
[bits (insn
, 0, 3)], offset
);
964 if (pv_area_store_would_trash (stack
, addr
))
967 pv_area_store (stack
, addr
, 4, regs
[regno
]);
970 else if ((insn
& 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
971 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
972 /* Ignore stores of argument registers to the stack. */
975 else if ((insn
& 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
976 && (inst2
& 0x0d00) == 0x0c00
977 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
978 /* Ignore stores of argument registers to the stack. */
981 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!],
983 && (inst2
& 0x8000) == 0x0000
984 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
985 /* Ignore block loads from the stack, potentially copying
986 parameters from memory. */
989 else if ((insn
& 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
991 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
992 /* Similarly ignore dual loads from the stack. */
995 else if ((insn
& 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
996 && (inst2
& 0x0d00) == 0x0c00
997 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
998 /* Similarly ignore single loads from the stack. */
1001 else if ((insn
& 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
1002 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
1003 /* Similarly ignore single loads from the stack. */
1006 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
1007 && (inst2
& 0x8000) == 0x0000)
1009 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1010 | (bits (inst2
, 12, 14) << 8)
1011 | bits (inst2
, 0, 7));
1013 regs
[bits (inst2
, 8, 11)]
1014 = pv_add_constant (regs
[bits (insn
, 0, 3)],
1015 thumb_expand_immediate (imm
));
1018 else if ((insn
& 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
1019 && (inst2
& 0x8000) == 0x0000)
1021 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1022 | (bits (inst2
, 12, 14) << 8)
1023 | bits (inst2
, 0, 7));
1025 regs
[bits (inst2
, 8, 11)]
1026 = pv_add_constant (regs
[bits (insn
, 0, 3)], imm
);
1029 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
1030 && (inst2
& 0x8000) == 0x0000)
1032 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1033 | (bits (inst2
, 12, 14) << 8)
1034 | bits (inst2
, 0, 7));
1036 regs
[bits (inst2
, 8, 11)]
1037 = pv_add_constant (regs
[bits (insn
, 0, 3)],
1038 - (CORE_ADDR
) thumb_expand_immediate (imm
));
1041 else if ((insn
& 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
1042 && (inst2
& 0x8000) == 0x0000)
1044 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1045 | (bits (inst2
, 12, 14) << 8)
1046 | bits (inst2
, 0, 7));
1048 regs
[bits (inst2
, 8, 11)]
1049 = pv_add_constant (regs
[bits (insn
, 0, 3)], - (CORE_ADDR
) imm
);
1052 else if ((insn
& 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1054 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1055 | (bits (inst2
, 12, 14) << 8)
1056 | bits (inst2
, 0, 7));
1058 regs
[bits (inst2
, 8, 11)]
1059 = pv_constant (thumb_expand_immediate (imm
));
1062 else if ((insn
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1065 = EXTRACT_MOVW_MOVT_IMM_T (insn
, inst2
);
1067 regs
[bits (inst2
, 8, 11)] = pv_constant (imm
);
1070 else if (insn
== 0xea5f /* mov.w Rd,Rm */
1071 && (inst2
& 0xf0f0) == 0)
1073 int dst_reg
= (inst2
& 0x0f00) >> 8;
1074 int src_reg
= inst2
& 0xf;
1075 regs
[dst_reg
] = regs
[src_reg
];
1078 else if ((insn
& 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1080 /* Constant pool loads. */
1081 unsigned int constant
;
1084 offset
= bits (inst2
, 0, 11);
1086 loc
= start
+ 4 + offset
;
1088 loc
= start
+ 4 - offset
;
1090 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1091 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1094 else if ((insn
& 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1096 /* Constant pool loads. */
1097 unsigned int constant
;
1100 offset
= bits (inst2
, 0, 7) << 2;
1102 loc
= start
+ 4 + offset
;
1104 loc
= start
+ 4 - offset
;
1106 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1107 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1109 constant
= read_memory_unsigned_integer (loc
+ 4, 4, byte_order
);
1110 regs
[bits (inst2
, 8, 11)] = pv_constant (constant
);
1113 else if (thumb2_instruction_changes_pc (insn
, inst2
))
1115 /* Don't scan past anything that might change control flow. */
1120 /* The optimizer might shove anything into the prologue,
1121 so we just skip what we don't recognize. */
1122 unrecognized_pc
= start
;
1127 else if (thumb_instruction_changes_pc (insn
))
1129 /* Don't scan past anything that might change control flow. */
1134 /* The optimizer might shove anything into the prologue,
1135 so we just skip what we don't recognize. */
1136 unrecognized_pc
= start
;
1143 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1144 paddress (gdbarch
, start
));
1146 if (unrecognized_pc
== 0)
1147 unrecognized_pc
= start
;
1151 do_cleanups (back_to
);
1152 return unrecognized_pc
;
1155 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1157 /* Frame pointer is fp. Frame size is constant. */
1158 cache
->framereg
= ARM_FP_REGNUM
;
1159 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1161 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
1163 /* Frame pointer is r7. Frame size is constant. */
1164 cache
->framereg
= THUMB_FP_REGNUM
;
1165 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
1169 /* Try the stack pointer... this is a bit desperate. */
1170 cache
->framereg
= ARM_SP_REGNUM
;
1171 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1174 for (i
= 0; i
< 16; i
++)
1175 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
1176 cache
->saved_regs
[i
].addr
= offset
;
1178 do_cleanups (back_to
);
1179 return unrecognized_pc
;
1183 /* Try to analyze the instructions starting from PC, which load symbol
1184 __stack_chk_guard. Return the address of instruction after loading this
1185 symbol, set the dest register number to *BASEREG, and set the size of
1186 instructions for loading symbol in OFFSET. Return 0 if instructions are
1190 arm_analyze_load_stack_chk_guard(CORE_ADDR pc
, struct gdbarch
*gdbarch
,
1191 unsigned int *destreg
, int *offset
)
1193 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1194 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1195 unsigned int low
, high
, address
;
1200 unsigned short insn1
1201 = read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
1203 if ((insn1
& 0xf800) == 0x4800) /* ldr Rd, #immed */
1205 *destreg
= bits (insn1
, 8, 10);
1207 address
= (pc
& 0xfffffffc) + 4 + (bits (insn1
, 0, 7) << 2);
1208 address
= read_memory_unsigned_integer (address
, 4,
1209 byte_order_for_code
);
1211 else if ((insn1
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1213 unsigned short insn2
1214 = read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1216 low
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1219 = read_memory_unsigned_integer (pc
+ 4, 2, byte_order_for_code
);
1221 = read_memory_unsigned_integer (pc
+ 6, 2, byte_order_for_code
);
1223 /* movt Rd, #const */
1224 if ((insn1
& 0xfbc0) == 0xf2c0)
1226 high
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1227 *destreg
= bits (insn2
, 8, 11);
1229 address
= (high
<< 16 | low
);
1236 = read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
1238 if ((insn
& 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1240 address
= bits (insn
, 0, 11) + pc
+ 8;
1241 address
= read_memory_unsigned_integer (address
, 4,
1242 byte_order_for_code
);
1244 *destreg
= bits (insn
, 12, 15);
1247 else if ((insn
& 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1249 low
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1252 = read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
);
1254 if ((insn
& 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1256 high
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1257 *destreg
= bits (insn
, 12, 15);
1259 address
= (high
<< 16 | low
);
1267 /* Try to skip a sequence of instructions used for stack protector. If PC
1268 points to the first instruction of this sequence, return the address of
1269 first instruction after this sequence, otherwise, return original PC.
1271 On arm, this sequence of instructions is composed of mainly three steps,
1272 Step 1: load symbol __stack_chk_guard,
1273 Step 2: load from address of __stack_chk_guard,
1274 Step 3: store it to somewhere else.
1276 Usually, instructions on step 2 and step 3 are the same on various ARM
1277 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1278 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1279 instructions in step 1 vary from different ARM architectures. On ARMv7,
1282 movw Rn, #:lower16:__stack_chk_guard
1283 movt Rn, #:upper16:__stack_chk_guard
1290 .word __stack_chk_guard
1292 Since ldr/str is a very popular instruction, we can't use them as
1293 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1294 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1295 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1298 arm_skip_stack_protector(CORE_ADDR pc
, struct gdbarch
*gdbarch
)
1300 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1301 unsigned int basereg
;
1302 struct bound_minimal_symbol stack_chk_guard
;
1304 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1307 /* Try to parse the instructions in Step 1. */
1308 addr
= arm_analyze_load_stack_chk_guard (pc
, gdbarch
,
1313 stack_chk_guard
= lookup_minimal_symbol_by_pc (addr
);
1314 /* If name of symbol doesn't start with '__stack_chk_guard', this
1315 instruction sequence is not for stack protector. If symbol is
1316 removed, we conservatively think this sequence is for stack protector. */
1317 if (stack_chk_guard
.minsym
1318 && strncmp (MSYMBOL_LINKAGE_NAME (stack_chk_guard
.minsym
),
1319 "__stack_chk_guard",
1320 strlen ("__stack_chk_guard")) != 0)
1325 unsigned int destreg
;
1327 = read_memory_unsigned_integer (pc
+ offset
, 2, byte_order_for_code
);
1329 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1330 if ((insn
& 0xf800) != 0x6800)
1332 if (bits (insn
, 3, 5) != basereg
)
1334 destreg
= bits (insn
, 0, 2);
1336 insn
= read_memory_unsigned_integer (pc
+ offset
+ 2, 2,
1337 byte_order_for_code
);
1338 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1339 if ((insn
& 0xf800) != 0x6000)
1341 if (destreg
!= bits (insn
, 0, 2))
1346 unsigned int destreg
;
1348 = read_memory_unsigned_integer (pc
+ offset
, 4, byte_order_for_code
);
1350 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1351 if ((insn
& 0x0e500000) != 0x04100000)
1353 if (bits (insn
, 16, 19) != basereg
)
1355 destreg
= bits (insn
, 12, 15);
1356 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1357 insn
= read_memory_unsigned_integer (pc
+ offset
+ 4,
1358 4, byte_order_for_code
);
1359 if ((insn
& 0x0e500000) != 0x04000000)
1361 if (bits (insn
, 12, 15) != destreg
)
1364 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1367 return pc
+ offset
+ 4;
1369 return pc
+ offset
+ 8;
1372 /* Advance the PC across any function entry prologue instructions to
1373 reach some "real" code.
1375 The APCS (ARM Procedure Call Standard) defines the following
1379 [stmfd sp!, {a1,a2,a3,a4}]
1380 stmfd sp!, {...,fp,ip,lr,pc}
1381 [stfe f7, [sp, #-12]!]
1382 [stfe f6, [sp, #-12]!]
1383 [stfe f5, [sp, #-12]!]
1384 [stfe f4, [sp, #-12]!]
1385 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1388 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1390 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1393 CORE_ADDR func_addr
, limit_pc
;
1395 /* See if we can determine the end of the prologue via the symbol table.
1396 If so, then return either PC, or the PC after the prologue, whichever
1398 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1400 CORE_ADDR post_prologue_pc
1401 = skip_prologue_using_sal (gdbarch
, func_addr
);
1402 struct symtab
*s
= find_pc_symtab (func_addr
);
1404 if (post_prologue_pc
)
1406 = arm_skip_stack_protector (post_prologue_pc
, gdbarch
);
1409 /* GCC always emits a line note before the prologue and another
1410 one after, even if the two are at the same address or on the
1411 same line. Take advantage of this so that we do not need to
1412 know every instruction that might appear in the prologue. We
1413 will have producer information for most binaries; if it is
1414 missing (e.g. for -gstabs), assuming the GNU tools. */
1415 if (post_prologue_pc
1417 || s
->producer
== NULL
1418 || strncmp (s
->producer
, "GNU ", sizeof ("GNU ") - 1) == 0
1419 || strncmp (s
->producer
, "clang ", sizeof ("clang ") - 1) == 0))
1420 return post_prologue_pc
;
1422 if (post_prologue_pc
!= 0)
1424 CORE_ADDR analyzed_limit
;
1426 /* For non-GCC compilers, make sure the entire line is an
1427 acceptable prologue; GDB will round this function's
1428 return value up to the end of the following line so we
1429 can not skip just part of a line (and we do not want to).
1431 RealView does not treat the prologue specially, but does
1432 associate prologue code with the opening brace; so this
1433 lets us skip the first line if we think it is the opening
1435 if (arm_pc_is_thumb (gdbarch
, func_addr
))
1436 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
1437 post_prologue_pc
, NULL
);
1439 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
1440 post_prologue_pc
, NULL
);
1442 if (analyzed_limit
!= post_prologue_pc
)
1445 return post_prologue_pc
;
1449 /* Can't determine prologue from the symbol table, need to examine
1452 /* Find an upper limit on the function prologue using the debug
1453 information. If the debug information could not be used to provide
1454 that bound, then use an arbitrary large number as the upper bound. */
1455 /* Like arm_scan_prologue, stop no later than pc + 64. */
1456 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1458 limit_pc
= pc
+ 64; /* Magic. */
1461 /* Check if this is Thumb code. */
1462 if (arm_pc_is_thumb (gdbarch
, pc
))
1463 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1465 for (skip_pc
= pc
; skip_pc
< limit_pc
; skip_pc
+= 4)
1467 inst
= read_memory_unsigned_integer (skip_pc
, 4, byte_order_for_code
);
1469 /* "mov ip, sp" is no longer a required part of the prologue. */
1470 if (inst
== 0xe1a0c00d) /* mov ip, sp */
1473 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
1476 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
1479 /* Some prologues begin with "str lr, [sp, #-4]!". */
1480 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
1483 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
1486 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
1489 /* Any insns after this point may float into the code, if it makes
1490 for better instruction scheduling, so we skip them only if we
1491 find them, but still consider the function to be frame-ful. */
1493 /* We may have either one sfmfd instruction here, or several stfe
1494 insns, depending on the version of floating point code we
1496 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
1499 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
1502 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
1505 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
1508 if ((inst
& 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */
1509 || (inst
& 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */
1510 || (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
1513 if ((inst
& 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */
1514 || (inst
& 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */
1515 || (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
1518 /* Un-recognized instruction; stop scanning. */
1522 return skip_pc
; /* End of prologue. */
1526 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1527 This function decodes a Thumb function prologue to determine:
1528 1) the size of the stack frame
1529 2) which registers are saved on it
1530 3) the offsets of saved regs
1531 4) the offset from the stack pointer to the frame pointer
1533 A typical Thumb function prologue would create this stack frame
1534 (offsets relative to FP)
1535 old SP -> 24 stack parameters
1538 R7 -> 0 local variables (16 bytes)
1539 SP -> -12 additional stack space (12 bytes)
1540 The frame size would thus be 36 bytes, and the frame offset would be
1541 12 bytes. The frame register is R7.
1543 The comments for thumb_skip_prolog() describe the algorithm we use
1544 to detect the end of the prolog. */
1548 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
1549 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
1551 CORE_ADDR prologue_start
;
1552 CORE_ADDR prologue_end
;
1554 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1557 /* See comment in arm_scan_prologue for an explanation of
1559 if (prologue_end
> prologue_start
+ 64)
1561 prologue_end
= prologue_start
+ 64;
1565 /* We're in the boondocks: we have no idea where the start of the
1569 prologue_end
= min (prologue_end
, prev_pc
);
1571 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1574 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
1577 arm_instruction_changes_pc (uint32_t this_instr
)
1579 if (bits (this_instr
, 28, 31) == INST_NV
)
1580 /* Unconditional instructions. */
1581 switch (bits (this_instr
, 24, 27))
1585 /* Branch with Link and change to Thumb. */
1590 /* Coprocessor register transfer. */
1591 if (bits (this_instr
, 12, 15) == 15)
1592 error (_("Invalid update to pc in instruction"));
1598 switch (bits (this_instr
, 25, 27))
1601 if (bits (this_instr
, 23, 24) == 2 && bit (this_instr
, 20) == 0)
1603 /* Multiplies and extra load/stores. */
1604 if (bit (this_instr
, 4) == 1 && bit (this_instr
, 7) == 1)
1605 /* Neither multiplies nor extension load/stores are allowed
1609 /* Otherwise, miscellaneous instructions. */
1611 /* BX <reg>, BXJ <reg>, BLX <reg> */
1612 if (bits (this_instr
, 4, 27) == 0x12fff1
1613 || bits (this_instr
, 4, 27) == 0x12fff2
1614 || bits (this_instr
, 4, 27) == 0x12fff3)
1617 /* Other miscellaneous instructions are unpredictable if they
1621 /* Data processing instruction. Fall through. */
1624 if (bits (this_instr
, 12, 15) == 15)
1631 /* Media instructions and architecturally undefined instructions. */
1632 if (bits (this_instr
, 25, 27) == 3 && bit (this_instr
, 4) == 1)
1636 if (bit (this_instr
, 20) == 0)
1640 if (bits (this_instr
, 12, 15) == ARM_PC_REGNUM
)
1646 /* Load/store multiple. */
1647 if (bit (this_instr
, 20) == 1 && bit (this_instr
, 15) == 1)
1653 /* Branch and branch with link. */
1658 /* Coprocessor transfers or SWIs can not affect PC. */
1662 internal_error (__FILE__
, __LINE__
, _("bad value in switch"));
1666 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1667 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1668 fill it in. Return the first address not recognized as a prologue
1671 We recognize all the instructions typically found in ARM prologues,
1672 plus harmless instructions which can be skipped (either for analysis
1673 purposes, or a more restrictive set that can be skipped when finding
1674 the end of the prologue). */
1677 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1678 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1679 struct arm_prologue_cache
*cache
)
1681 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1682 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1684 CORE_ADDR offset
, current_pc
;
1685 pv_t regs
[ARM_FPS_REGNUM
];
1686 struct pv_area
*stack
;
1687 struct cleanup
*back_to
;
1688 int framereg
, framesize
;
1689 CORE_ADDR unrecognized_pc
= 0;
1691 /* Search the prologue looking for instructions that set up the
1692 frame pointer, adjust the stack pointer, and save registers.
1694 Be careful, however, and if it doesn't look like a prologue,
1695 don't try to scan it. If, for instance, a frameless function
1696 begins with stmfd sp!, then we will tell ourselves there is
1697 a frame, which will confuse stack traceback, as well as "finish"
1698 and other operations that rely on a knowledge of the stack
1701 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1702 regs
[regno
] = pv_register (regno
, 0);
1703 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1704 back_to
= make_cleanup_free_pv_area (stack
);
1706 for (current_pc
= prologue_start
;
1707 current_pc
< prologue_end
;
1711 = read_memory_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1713 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1715 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1718 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1719 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1721 unsigned imm
= insn
& 0xff; /* immediate value */
1722 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1723 int rd
= bits (insn
, 12, 15);
1724 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1725 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1728 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1729 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1731 unsigned imm
= insn
& 0xff; /* immediate value */
1732 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1733 int rd
= bits (insn
, 12, 15);
1734 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1735 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1738 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd,
1741 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1743 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1744 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4,
1745 regs
[bits (insn
, 12, 15)]);
1748 else if ((insn
& 0xffff0000) == 0xe92d0000)
1749 /* stmfd sp!, {..., fp, ip, lr, pc}
1751 stmfd sp!, {a1, a2, a3, a4} */
1753 int mask
= insn
& 0xffff;
1755 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1758 /* Calculate offsets of saved registers. */
1759 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1760 if (mask
& (1 << regno
))
1763 = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1764 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1767 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1768 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1769 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1771 /* No need to add this to saved_regs -- it's just an arg reg. */
1774 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1775 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1776 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1778 /* No need to add this to saved_regs -- it's just an arg reg. */
1781 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn,
1783 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1785 /* No need to add this to saved_regs -- it's just arg regs. */
1788 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1790 unsigned imm
= insn
& 0xff; /* immediate value */
1791 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1792 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1793 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1795 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1797 unsigned imm
= insn
& 0xff; /* immediate value */
1798 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1799 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1800 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1802 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?,
1804 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1806 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1809 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1810 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1811 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1813 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1815 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1817 int n_saved_fp_regs
;
1818 unsigned int fp_start_reg
, fp_bound_reg
;
1820 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1823 if ((insn
& 0x800) == 0x800) /* N0 is set */
1825 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1826 n_saved_fp_regs
= 3;
1828 n_saved_fp_regs
= 1;
1832 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1833 n_saved_fp_regs
= 2;
1835 n_saved_fp_regs
= 4;
1838 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1839 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1840 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1842 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1843 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
1844 regs
[fp_start_reg
++]);
1847 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1849 /* Allow some special function calls when skipping the
1850 prologue; GCC generates these before storing arguments to
1852 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1854 if (skip_prologue_function (gdbarch
, dest
, 0))
1859 else if ((insn
& 0xf0000000) != 0xe0000000)
1860 break; /* Condition not true, exit early. */
1861 else if (arm_instruction_changes_pc (insn
))
1862 /* Don't scan past anything that might change control flow. */
1864 else if ((insn
& 0xfe500000) == 0xe8100000 /* ldm */
1865 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1866 /* Ignore block loads from the stack, potentially copying
1867 parameters from memory. */
1869 else if ((insn
& 0xfc500000) == 0xe4100000
1870 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1871 /* Similarly ignore single loads from the stack. */
1873 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1874 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1875 register instead of the stack. */
1879 /* The optimizer might shove anything into the prologue,
1880 so we just skip what we don't recognize. */
1881 unrecognized_pc
= current_pc
;
1886 if (unrecognized_pc
== 0)
1887 unrecognized_pc
= current_pc
;
1889 /* The frame size is just the distance from the frame register
1890 to the original stack pointer. */
1891 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1893 /* Frame pointer is fp. */
1894 framereg
= ARM_FP_REGNUM
;
1895 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1899 /* Try the stack pointer... this is a bit desperate. */
1900 framereg
= ARM_SP_REGNUM
;
1901 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1906 cache
->framereg
= framereg
;
1907 cache
->framesize
= framesize
;
1909 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1910 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1911 cache
->saved_regs
[regno
].addr
= offset
;
1915 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1916 paddress (gdbarch
, unrecognized_pc
));
1918 do_cleanups (back_to
);
1919 return unrecognized_pc
;
1923 arm_scan_prologue (struct frame_info
*this_frame
,
1924 struct arm_prologue_cache
*cache
)
1926 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1927 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1929 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
1930 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1931 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1932 pv_t regs
[ARM_FPS_REGNUM
];
1933 struct pv_area
*stack
;
1934 struct cleanup
*back_to
;
1937 /* Assume there is no frame until proven otherwise. */
1938 cache
->framereg
= ARM_SP_REGNUM
;
1939 cache
->framesize
= 0;
1941 /* Check for Thumb prologue. */
1942 if (arm_frame_is_thumb (this_frame
))
1944 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1948 /* Find the function prologue. If we can't find the function in
1949 the symbol table, peek in the stack frame to find the PC. */
1950 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1953 /* One way to find the end of the prologue (which works well
1954 for unoptimized code) is to do the following:
1956 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1959 prologue_end = prev_pc;
1960 else if (sal.end < prologue_end)
1961 prologue_end = sal.end;
1963 This mechanism is very accurate so long as the optimizer
1964 doesn't move any instructions from the function body into the
1965 prologue. If this happens, sal.end will be the last
1966 instruction in the first hunk of prologue code just before
1967 the first instruction that the scheduler has moved from
1968 the body to the prologue.
1970 In order to make sure that we scan all of the prologue
1971 instructions, we use a slightly less accurate mechanism which
1972 may scan more than necessary. To help compensate for this
1973 lack of accuracy, the prologue scanning loop below contains
1974 several clauses which'll cause the loop to terminate early if
1975 an implausible prologue instruction is encountered.
1981 is a suitable endpoint since it accounts for the largest
1982 possible prologue plus up to five instructions inserted by
1985 if (prologue_end
> prologue_start
+ 64)
1987 prologue_end
= prologue_start
+ 64; /* See above. */
1992 /* We have no symbol information. Our only option is to assume this
1993 function has a standard stack frame and the normal frame register.
1994 Then, we can find the value of our frame pointer on entrance to
1995 the callee (or at the present moment if this is the innermost frame).
1996 The value stored there should be the address of the stmfd + 8. */
1997 CORE_ADDR frame_loc
;
1998 LONGEST return_value
;
2000 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
2001 if (!safe_read_memory_integer (frame_loc
, 4, byte_order
, &return_value
))
2005 prologue_start
= gdbarch_addr_bits_remove
2006 (gdbarch
, return_value
) - 8;
2007 prologue_end
= prologue_start
+ 64; /* See above. */
2011 if (prev_pc
< prologue_end
)
2012 prologue_end
= prev_pc
;
2014 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
2017 static struct arm_prologue_cache
*
2018 arm_make_prologue_cache (struct frame_info
*this_frame
)
2021 struct arm_prologue_cache
*cache
;
2022 CORE_ADDR unwound_fp
;
2024 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2025 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2027 arm_scan_prologue (this_frame
, cache
);
2029 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
2030 if (unwound_fp
== 0)
2033 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
2035 /* Calculate actual addresses of saved registers using offsets
2036 determined by arm_scan_prologue. */
2037 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
2038 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
2039 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
2044 /* Our frame ID for a normal frame is the current function's starting PC
2045 and the caller's SP when we were called. */
2048 arm_prologue_this_id (struct frame_info
*this_frame
,
2050 struct frame_id
*this_id
)
2052 struct arm_prologue_cache
*cache
;
2056 if (*this_cache
== NULL
)
2057 *this_cache
= arm_make_prologue_cache (this_frame
);
2058 cache
= *this_cache
;
2060 /* This is meant to halt the backtrace at "_start". */
2061 pc
= get_frame_pc (this_frame
);
2062 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
2065 /* If we've hit a wall, stop. */
2066 if (cache
->prev_sp
== 0)
2069 /* Use function start address as part of the frame ID. If we cannot
2070 identify the start address (due to missing symbol information),
2071 fall back to just using the current PC. */
2072 func
= get_frame_func (this_frame
);
2076 id
= frame_id_build (cache
->prev_sp
, func
);
2080 static struct value
*
2081 arm_prologue_prev_register (struct frame_info
*this_frame
,
2085 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2086 struct arm_prologue_cache
*cache
;
2088 if (*this_cache
== NULL
)
2089 *this_cache
= arm_make_prologue_cache (this_frame
);
2090 cache
= *this_cache
;
2092 /* If we are asked to unwind the PC, then we need to return the LR
2093 instead. The prologue may save PC, but it will point into this
2094 frame's prologue, not the next frame's resume location. Also
2095 strip the saved T bit. A valid LR may have the low bit set, but
2096 a valid PC never does. */
2097 if (prev_regnum
== ARM_PC_REGNUM
)
2101 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2102 return frame_unwind_got_constant (this_frame
, prev_regnum
,
2103 arm_addr_bits_remove (gdbarch
, lr
));
2106 /* SP is generally not saved to the stack, but this frame is
2107 identified by the next frame's stack pointer at the time of the call.
2108 The value was already reconstructed into PREV_SP. */
2109 if (prev_regnum
== ARM_SP_REGNUM
)
2110 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
2112 /* The CPSR may have been changed by the call instruction and by the
2113 called function. The only bit we can reconstruct is the T bit,
2114 by checking the low bit of LR as of the call. This is a reliable
2115 indicator of Thumb-ness except for some ARM v4T pre-interworking
2116 Thumb code, which could get away with a clear low bit as long as
2117 the called function did not use bx. Guess that all other
2118 bits are unchanged; the condition flags are presumably lost,
2119 but the processor status is likely valid. */
2120 if (prev_regnum
== ARM_PS_REGNUM
)
2123 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
2125 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
2126 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2127 if (IS_THUMB_ADDR (lr
))
2131 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
2134 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
2138 struct frame_unwind arm_prologue_unwind
= {
2140 default_frame_unwind_stop_reason
,
2141 arm_prologue_this_id
,
2142 arm_prologue_prev_register
,
2144 default_frame_sniffer
2147 /* Maintain a list of ARM exception table entries per objfile, similar to the
2148 list of mapping symbols. We only cache entries for standard ARM-defined
2149 personality routines; the cache will contain only the frame unwinding
2150 instructions associated with the entry (not the descriptors). */
2152 static const struct objfile_data
*arm_exidx_data_key
;
2154 struct arm_exidx_entry
2159 typedef struct arm_exidx_entry arm_exidx_entry_s
;
2160 DEF_VEC_O(arm_exidx_entry_s
);
2162 struct arm_exidx_data
2164 VEC(arm_exidx_entry_s
) **section_maps
;
2168 arm_exidx_data_free (struct objfile
*objfile
, void *arg
)
2170 struct arm_exidx_data
*data
= arg
;
2173 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
2174 VEC_free (arm_exidx_entry_s
, data
->section_maps
[i
]);
2178 arm_compare_exidx_entries (const struct arm_exidx_entry
*lhs
,
2179 const struct arm_exidx_entry
*rhs
)
2181 return lhs
->addr
< rhs
->addr
;
2184 static struct obj_section
*
2185 arm_obj_section_from_vma (struct objfile
*objfile
, bfd_vma vma
)
2187 struct obj_section
*osect
;
2189 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
2190 if (bfd_get_section_flags (objfile
->obfd
,
2191 osect
->the_bfd_section
) & SEC_ALLOC
)
2193 bfd_vma start
, size
;
2194 start
= bfd_get_section_vma (objfile
->obfd
, osect
->the_bfd_section
);
2195 size
= bfd_get_section_size (osect
->the_bfd_section
);
2197 if (start
<= vma
&& vma
< start
+ size
)
2204 /* Parse contents of exception table and exception index sections
2205 of OBJFILE, and fill in the exception table entry cache.
2207 For each entry that refers to a standard ARM-defined personality
2208 routine, extract the frame unwinding instructions (from either
2209 the index or the table section). The unwinding instructions
2211 - extracting them from the rest of the table data
2212 - converting to host endianness
2213 - appending the implicit 0xb0 ("Finish") code
2215 The extracted and normalized instructions are stored for later
2216 retrieval by the arm_find_exidx_entry routine. */
2219 arm_exidx_new_objfile (struct objfile
*objfile
)
2221 struct cleanup
*cleanups
;
2222 struct arm_exidx_data
*data
;
2223 asection
*exidx
, *extab
;
2224 bfd_vma exidx_vma
= 0, extab_vma
= 0;
2225 bfd_size_type exidx_size
= 0, extab_size
= 0;
2226 gdb_byte
*exidx_data
= NULL
, *extab_data
= NULL
;
2229 /* If we've already touched this file, do nothing. */
2230 if (!objfile
|| objfile_data (objfile
, arm_exidx_data_key
) != NULL
)
2232 cleanups
= make_cleanup (null_cleanup
, NULL
);
2234 /* Read contents of exception table and index. */
2235 exidx
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.exidx");
2238 exidx_vma
= bfd_section_vma (objfile
->obfd
, exidx
);
2239 exidx_size
= bfd_get_section_size (exidx
);
2240 exidx_data
= xmalloc (exidx_size
);
2241 make_cleanup (xfree
, exidx_data
);
2243 if (!bfd_get_section_contents (objfile
->obfd
, exidx
,
2244 exidx_data
, 0, exidx_size
))
2246 do_cleanups (cleanups
);
2251 extab
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.extab");
2254 extab_vma
= bfd_section_vma (objfile
->obfd
, extab
);
2255 extab_size
= bfd_get_section_size (extab
);
2256 extab_data
= xmalloc (extab_size
);
2257 make_cleanup (xfree
, extab_data
);
2259 if (!bfd_get_section_contents (objfile
->obfd
, extab
,
2260 extab_data
, 0, extab_size
))
2262 do_cleanups (cleanups
);
2267 /* Allocate exception table data structure. */
2268 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
, struct arm_exidx_data
);
2269 set_objfile_data (objfile
, arm_exidx_data_key
, data
);
2270 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2271 objfile
->obfd
->section_count
,
2272 VEC(arm_exidx_entry_s
) *);
2274 /* Fill in exception table. */
2275 for (i
= 0; i
< exidx_size
/ 8; i
++)
2277 struct arm_exidx_entry new_exidx_entry
;
2278 bfd_vma idx
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8);
2279 bfd_vma val
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8 + 4);
2280 bfd_vma addr
= 0, word
= 0;
2281 int n_bytes
= 0, n_words
= 0;
2282 struct obj_section
*sec
;
2283 gdb_byte
*entry
= NULL
;
2285 /* Extract address of start of function. */
2286 idx
= ((idx
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2287 idx
+= exidx_vma
+ i
* 8;
2289 /* Find section containing function and compute section offset. */
2290 sec
= arm_obj_section_from_vma (objfile
, idx
);
2293 idx
-= bfd_get_section_vma (objfile
->obfd
, sec
->the_bfd_section
);
2295 /* Determine address of exception table entry. */
2298 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2300 else if ((val
& 0xff000000) == 0x80000000)
2302 /* Exception table entry embedded in .ARM.exidx
2303 -- must be short form. */
2307 else if (!(val
& 0x80000000))
2309 /* Exception table entry in .ARM.extab. */
2310 addr
= ((val
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2311 addr
+= exidx_vma
+ i
* 8 + 4;
2313 if (addr
>= extab_vma
&& addr
+ 4 <= extab_vma
+ extab_size
)
2315 word
= bfd_h_get_32 (objfile
->obfd
,
2316 extab_data
+ addr
- extab_vma
);
2319 if ((word
& 0xff000000) == 0x80000000)
2324 else if ((word
& 0xff000000) == 0x81000000
2325 || (word
& 0xff000000) == 0x82000000)
2329 n_words
= ((word
>> 16) & 0xff);
2331 else if (!(word
& 0x80000000))
2334 struct obj_section
*pers_sec
;
2335 int gnu_personality
= 0;
2337 /* Custom personality routine. */
2338 pers
= ((word
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2339 pers
= UNMAKE_THUMB_ADDR (pers
+ addr
- 4);
2341 /* Check whether we've got one of the variants of the
2342 GNU personality routines. */
2343 pers_sec
= arm_obj_section_from_vma (objfile
, pers
);
2346 static const char *personality
[] =
2348 "__gcc_personality_v0",
2349 "__gxx_personality_v0",
2350 "__gcj_personality_v0",
2351 "__gnu_objc_personality_v0",
2355 CORE_ADDR pc
= pers
+ obj_section_offset (pers_sec
);
2358 for (k
= 0; personality
[k
]; k
++)
2359 if (lookup_minimal_symbol_by_pc_name
2360 (pc
, personality
[k
], objfile
))
2362 gnu_personality
= 1;
2367 /* If so, the next word contains a word count in the high
2368 byte, followed by the same unwind instructions as the
2369 pre-defined forms. */
2371 && addr
+ 4 <= extab_vma
+ extab_size
)
2373 word
= bfd_h_get_32 (objfile
->obfd
,
2374 extab_data
+ addr
- extab_vma
);
2377 n_words
= ((word
>> 24) & 0xff);
2383 /* Sanity check address. */
2385 if (addr
< extab_vma
|| addr
+ 4 * n_words
> extab_vma
+ extab_size
)
2386 n_words
= n_bytes
= 0;
2388 /* The unwind instructions reside in WORD (only the N_BYTES least
2389 significant bytes are valid), followed by N_WORDS words in the
2390 extab section starting at ADDR. */
2391 if (n_bytes
|| n_words
)
2393 gdb_byte
*p
= entry
= obstack_alloc (&objfile
->objfile_obstack
,
2394 n_bytes
+ n_words
* 4 + 1);
2397 *p
++ = (gdb_byte
) ((word
>> (8 * n_bytes
)) & 0xff);
2401 word
= bfd_h_get_32 (objfile
->obfd
,
2402 extab_data
+ addr
- extab_vma
);
2405 *p
++ = (gdb_byte
) ((word
>> 24) & 0xff);
2406 *p
++ = (gdb_byte
) ((word
>> 16) & 0xff);
2407 *p
++ = (gdb_byte
) ((word
>> 8) & 0xff);
2408 *p
++ = (gdb_byte
) (word
& 0xff);
2411 /* Implied "Finish" to terminate the list. */
2415 /* Push entry onto vector. They are guaranteed to always
2416 appear in order of increasing addresses. */
2417 new_exidx_entry
.addr
= idx
;
2418 new_exidx_entry
.entry
= entry
;
2419 VEC_safe_push (arm_exidx_entry_s
,
2420 data
->section_maps
[sec
->the_bfd_section
->index
],
2424 do_cleanups (cleanups
);
2427 /* Search for the exception table entry covering MEMADDR. If one is found,
2428 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2429 set *START to the start of the region covered by this entry. */
2432 arm_find_exidx_entry (CORE_ADDR memaddr
, CORE_ADDR
*start
)
2434 struct obj_section
*sec
;
2436 sec
= find_pc_section (memaddr
);
2439 struct arm_exidx_data
*data
;
2440 VEC(arm_exidx_entry_s
) *map
;
2441 struct arm_exidx_entry map_key
= { memaddr
- obj_section_addr (sec
), 0 };
2444 data
= objfile_data (sec
->objfile
, arm_exidx_data_key
);
2447 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
2448 if (!VEC_empty (arm_exidx_entry_s
, map
))
2450 struct arm_exidx_entry
*map_sym
;
2452 idx
= VEC_lower_bound (arm_exidx_entry_s
, map
, &map_key
,
2453 arm_compare_exidx_entries
);
2455 /* VEC_lower_bound finds the earliest ordered insertion
2456 point. If the following symbol starts at this exact
2457 address, we use that; otherwise, the preceding
2458 exception table entry covers this address. */
2459 if (idx
< VEC_length (arm_exidx_entry_s
, map
))
2461 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
);
2462 if (map_sym
->addr
== map_key
.addr
)
2465 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2466 return map_sym
->entry
;
2472 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
- 1);
2474 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2475 return map_sym
->entry
;
2484 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2485 instruction list from the ARM exception table entry ENTRY, allocate and
2486 return a prologue cache structure describing how to unwind this frame.
2488 Return NULL if the unwinding instruction list contains a "spare",
2489 "reserved" or "refuse to unwind" instruction as defined in section
2490 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2491 for the ARM Architecture" document. */
2493 static struct arm_prologue_cache
*
2494 arm_exidx_fill_cache (struct frame_info
*this_frame
, gdb_byte
*entry
)
2499 struct arm_prologue_cache
*cache
;
2500 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2501 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2507 /* Whenever we reload SP, we actually have to retrieve its
2508 actual value in the current frame. */
2511 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2513 int reg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2514 vsp
= get_frame_register_unsigned (this_frame
, reg
);
2518 CORE_ADDR addr
= cache
->saved_regs
[ARM_SP_REGNUM
].addr
;
2519 vsp
= get_frame_memory_unsigned (this_frame
, addr
, 4);
2525 /* Decode next unwind instruction. */
2528 if ((insn
& 0xc0) == 0)
2530 int offset
= insn
& 0x3f;
2531 vsp
+= (offset
<< 2) + 4;
2533 else if ((insn
& 0xc0) == 0x40)
2535 int offset
= insn
& 0x3f;
2536 vsp
-= (offset
<< 2) + 4;
2538 else if ((insn
& 0xf0) == 0x80)
2540 int mask
= ((insn
& 0xf) << 8) | *entry
++;
2543 /* The special case of an all-zero mask identifies
2544 "Refuse to unwind". We return NULL to fall back
2545 to the prologue analyzer. */
2549 /* Pop registers r4..r15 under mask. */
2550 for (i
= 0; i
< 12; i
++)
2551 if (mask
& (1 << i
))
2553 cache
->saved_regs
[4 + i
].addr
= vsp
;
2557 /* Special-case popping SP -- we need to reload vsp. */
2558 if (mask
& (1 << (ARM_SP_REGNUM
- 4)))
2561 else if ((insn
& 0xf0) == 0x90)
2563 int reg
= insn
& 0xf;
2565 /* Reserved cases. */
2566 if (reg
== ARM_SP_REGNUM
|| reg
== ARM_PC_REGNUM
)
2569 /* Set SP from another register and mark VSP for reload. */
2570 cache
->saved_regs
[ARM_SP_REGNUM
] = cache
->saved_regs
[reg
];
2573 else if ((insn
& 0xf0) == 0xa0)
2575 int count
= insn
& 0x7;
2576 int pop_lr
= (insn
& 0x8) != 0;
2579 /* Pop r4..r[4+count]. */
2580 for (i
= 0; i
<= count
; i
++)
2582 cache
->saved_regs
[4 + i
].addr
= vsp
;
2586 /* If indicated by flag, pop LR as well. */
2589 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= vsp
;
2593 else if (insn
== 0xb0)
2595 /* We could only have updated PC by popping into it; if so, it
2596 will show up as address. Otherwise, copy LR into PC. */
2597 if (!trad_frame_addr_p (cache
->saved_regs
, ARM_PC_REGNUM
))
2598 cache
->saved_regs
[ARM_PC_REGNUM
]
2599 = cache
->saved_regs
[ARM_LR_REGNUM
];
2604 else if (insn
== 0xb1)
2606 int mask
= *entry
++;
2609 /* All-zero mask and mask >= 16 is "spare". */
2610 if (mask
== 0 || mask
>= 16)
2613 /* Pop r0..r3 under mask. */
2614 for (i
= 0; i
< 4; i
++)
2615 if (mask
& (1 << i
))
2617 cache
->saved_regs
[i
].addr
= vsp
;
2621 else if (insn
== 0xb2)
2623 ULONGEST offset
= 0;
2628 offset
|= (*entry
& 0x7f) << shift
;
2631 while (*entry
++ & 0x80);
2633 vsp
+= 0x204 + (offset
<< 2);
2635 else if (insn
== 0xb3)
2637 int start
= *entry
>> 4;
2638 int count
= (*entry
++) & 0xf;
2641 /* Only registers D0..D15 are valid here. */
2642 if (start
+ count
>= 16)
2645 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2646 for (i
= 0; i
<= count
; i
++)
2648 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2652 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2655 else if ((insn
& 0xf8) == 0xb8)
2657 int count
= insn
& 0x7;
2660 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2661 for (i
= 0; i
<= count
; i
++)
2663 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2667 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2670 else if (insn
== 0xc6)
2672 int start
= *entry
>> 4;
2673 int count
= (*entry
++) & 0xf;
2676 /* Only registers WR0..WR15 are valid. */
2677 if (start
+ count
>= 16)
2680 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2681 for (i
= 0; i
<= count
; i
++)
2683 cache
->saved_regs
[ARM_WR0_REGNUM
+ start
+ i
].addr
= vsp
;
2687 else if (insn
== 0xc7)
2689 int mask
= *entry
++;
2692 /* All-zero mask and mask >= 16 is "spare". */
2693 if (mask
== 0 || mask
>= 16)
2696 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2697 for (i
= 0; i
< 4; i
++)
2698 if (mask
& (1 << i
))
2700 cache
->saved_regs
[ARM_WCGR0_REGNUM
+ i
].addr
= vsp
;
2704 else if ((insn
& 0xf8) == 0xc0)
2706 int count
= insn
& 0x7;
2709 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2710 for (i
= 0; i
<= count
; i
++)
2712 cache
->saved_regs
[ARM_WR0_REGNUM
+ 10 + i
].addr
= vsp
;
2716 else if (insn
== 0xc8)
2718 int start
= *entry
>> 4;
2719 int count
= (*entry
++) & 0xf;
2722 /* Only registers D0..D31 are valid. */
2723 if (start
+ count
>= 16)
2726 /* Pop VFP double-precision registers
2727 D[16+start]..D[16+start+count]. */
2728 for (i
= 0; i
<= count
; i
++)
2730 cache
->saved_regs
[ARM_D0_REGNUM
+ 16 + start
+ i
].addr
= vsp
;
2734 else if (insn
== 0xc9)
2736 int start
= *entry
>> 4;
2737 int count
= (*entry
++) & 0xf;
2740 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2741 for (i
= 0; i
<= count
; i
++)
2743 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2747 else if ((insn
& 0xf8) == 0xd0)
2749 int count
= insn
& 0x7;
2752 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2753 for (i
= 0; i
<= count
; i
++)
2755 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2761 /* Everything else is "spare". */
2766 /* If we restore SP from a register, assume this was the frame register.
2767 Otherwise just fall back to SP as frame register. */
2768 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2769 cache
->framereg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2771 cache
->framereg
= ARM_SP_REGNUM
;
2773 /* Determine offset to previous frame. */
2775 = vsp
- get_frame_register_unsigned (this_frame
, cache
->framereg
);
2777 /* We already got the previous SP. */
2778 cache
->prev_sp
= vsp
;
2783 /* Unwinding via ARM exception table entries. Note that the sniffer
2784 already computes a filled-in prologue cache, which is then used
2785 with the same arm_prologue_this_id and arm_prologue_prev_register
2786 routines also used for prologue-parsing based unwinding. */
2789 arm_exidx_unwind_sniffer (const struct frame_unwind
*self
,
2790 struct frame_info
*this_frame
,
2791 void **this_prologue_cache
)
2793 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2794 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2795 CORE_ADDR addr_in_block
, exidx_region
, func_start
;
2796 struct arm_prologue_cache
*cache
;
2799 /* See if we have an ARM exception table entry covering this address. */
2800 addr_in_block
= get_frame_address_in_block (this_frame
);
2801 entry
= arm_find_exidx_entry (addr_in_block
, &exidx_region
);
2805 /* The ARM exception table does not describe unwind information
2806 for arbitrary PC values, but is guaranteed to be correct only
2807 at call sites. We have to decide here whether we want to use
2808 ARM exception table information for this frame, or fall back
2809 to using prologue parsing. (Note that if we have DWARF CFI,
2810 this sniffer isn't even called -- CFI is always preferred.)
2812 Before we make this decision, however, we check whether we
2813 actually have *symbol* information for the current frame.
2814 If not, prologue parsing would not work anyway, so we might
2815 as well use the exception table and hope for the best. */
2816 if (find_pc_partial_function (addr_in_block
, NULL
, &func_start
, NULL
))
2820 /* If the next frame is "normal", we are at a call site in this
2821 frame, so exception information is guaranteed to be valid. */
2822 if (get_next_frame (this_frame
)
2823 && get_frame_type (get_next_frame (this_frame
)) == NORMAL_FRAME
)
2826 /* We also assume exception information is valid if we're currently
2827 blocked in a system call. The system library is supposed to
2828 ensure this, so that e.g. pthread cancellation works. */
2829 if (arm_frame_is_thumb (this_frame
))
2833 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 2, 2,
2834 byte_order_for_code
, &insn
)
2835 && (insn
& 0xff00) == 0xdf00 /* svc */)
2842 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 4, 4,
2843 byte_order_for_code
, &insn
)
2844 && (insn
& 0x0f000000) == 0x0f000000 /* svc */)
2848 /* Bail out if we don't know that exception information is valid. */
2852 /* The ARM exception index does not mark the *end* of the region
2853 covered by the entry, and some functions will not have any entry.
2854 To correctly recognize the end of the covered region, the linker
2855 should have inserted dummy records with a CANTUNWIND marker.
2857 Unfortunately, current versions of GNU ld do not reliably do
2858 this, and thus we may have found an incorrect entry above.
2859 As a (temporary) sanity check, we only use the entry if it
2860 lies *within* the bounds of the function. Note that this check
2861 might reject perfectly valid entries that just happen to cover
2862 multiple functions; therefore this check ought to be removed
2863 once the linker is fixed. */
2864 if (func_start
> exidx_region
)
2868 /* Decode the list of unwinding instructions into a prologue cache.
2869 Note that this may fail due to e.g. a "refuse to unwind" code. */
2870 cache
= arm_exidx_fill_cache (this_frame
, entry
);
2874 *this_prologue_cache
= cache
;
2878 struct frame_unwind arm_exidx_unwind
= {
2880 default_frame_unwind_stop_reason
,
2881 arm_prologue_this_id
,
2882 arm_prologue_prev_register
,
2884 arm_exidx_unwind_sniffer
2887 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2888 trampoline, return the target PC. Otherwise return 0.
2890 void call0a (char c, short s, int i, long l) {}
2894 (*pointer_to_call0a) (c, s, i, l);
2897 Instead of calling a stub library function _call_via_xx (xx is
2898 the register name), GCC may inline the trampoline in the object
2899 file as below (register r2 has the address of call0a).
2902 .type main, %function
2911 The trampoline 'bx r2' doesn't belong to main. */
2914 arm_skip_bx_reg (struct frame_info
*frame
, CORE_ADDR pc
)
2916 /* The heuristics of recognizing such trampoline is that FRAME is
2917 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2918 if (arm_frame_is_thumb (frame
))
2922 if (target_read_memory (pc
, buf
, 2) == 0)
2924 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2925 enum bfd_endian byte_order_for_code
2926 = gdbarch_byte_order_for_code (gdbarch
);
2928 = extract_unsigned_integer (buf
, 2, byte_order_for_code
);
2930 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
2933 = get_frame_register_unsigned (frame
, bits (insn
, 3, 6));
2935 /* Clear the LSB so that gdb core sets step-resume
2936 breakpoint at the right address. */
2937 return UNMAKE_THUMB_ADDR (dest
);
2945 static struct arm_prologue_cache
*
2946 arm_make_stub_cache (struct frame_info
*this_frame
)
2948 struct arm_prologue_cache
*cache
;
2950 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2951 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2953 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2958 /* Our frame ID for a stub frame is the current SP and LR. */
2961 arm_stub_this_id (struct frame_info
*this_frame
,
2963 struct frame_id
*this_id
)
2965 struct arm_prologue_cache
*cache
;
2967 if (*this_cache
== NULL
)
2968 *this_cache
= arm_make_stub_cache (this_frame
);
2969 cache
= *this_cache
;
2971 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
2975 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
2976 struct frame_info
*this_frame
,
2977 void **this_prologue_cache
)
2979 CORE_ADDR addr_in_block
;
2981 CORE_ADDR pc
, start_addr
;
2984 addr_in_block
= get_frame_address_in_block (this_frame
);
2985 pc
= get_frame_pc (this_frame
);
2986 if (in_plt_section (addr_in_block
)
2987 /* We also use the stub winder if the target memory is unreadable
2988 to avoid having the prologue unwinder trying to read it. */
2989 || target_read_memory (pc
, dummy
, 4) != 0)
2992 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0
2993 && arm_skip_bx_reg (this_frame
, pc
) != 0)
2999 struct frame_unwind arm_stub_unwind
= {
3001 default_frame_unwind_stop_reason
,
3003 arm_prologue_prev_register
,
3005 arm_stub_unwind_sniffer
3008 /* Put here the code to store, into CACHE->saved_regs, the addresses
3009 of the saved registers of frame described by THIS_FRAME. CACHE is
3012 static struct arm_prologue_cache
*
3013 arm_m_exception_cache (struct frame_info
*this_frame
)
3015 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3016 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3017 struct arm_prologue_cache
*cache
;
3018 CORE_ADDR unwound_sp
;
3021 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
3022 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3024 unwound_sp
= get_frame_register_unsigned (this_frame
,
3027 /* The hardware saves eight 32-bit words, comprising xPSR,
3028 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
3029 "B1.5.6 Exception entry behavior" in
3030 "ARMv7-M Architecture Reference Manual". */
3031 cache
->saved_regs
[0].addr
= unwound_sp
;
3032 cache
->saved_regs
[1].addr
= unwound_sp
+ 4;
3033 cache
->saved_regs
[2].addr
= unwound_sp
+ 8;
3034 cache
->saved_regs
[3].addr
= unwound_sp
+ 12;
3035 cache
->saved_regs
[12].addr
= unwound_sp
+ 16;
3036 cache
->saved_regs
[14].addr
= unwound_sp
+ 20;
3037 cache
->saved_regs
[15].addr
= unwound_sp
+ 24;
3038 cache
->saved_regs
[ARM_PS_REGNUM
].addr
= unwound_sp
+ 28;
3040 /* If bit 9 of the saved xPSR is set, then there is a four-byte
3041 aligner between the top of the 32-byte stack frame and the
3042 previous context's stack pointer. */
3043 cache
->prev_sp
= unwound_sp
+ 32;
3044 if (safe_read_memory_integer (unwound_sp
+ 28, 4, byte_order
, &xpsr
)
3045 && (xpsr
& (1 << 9)) != 0)
3046 cache
->prev_sp
+= 4;
3051 /* Implementation of function hook 'this_id' in
3052 'struct frame_uwnind'. */
3055 arm_m_exception_this_id (struct frame_info
*this_frame
,
3057 struct frame_id
*this_id
)
3059 struct arm_prologue_cache
*cache
;
3061 if (*this_cache
== NULL
)
3062 *this_cache
= arm_m_exception_cache (this_frame
);
3063 cache
= *this_cache
;
3065 /* Our frame ID for a stub frame is the current SP and LR. */
3066 *this_id
= frame_id_build (cache
->prev_sp
,
3067 get_frame_pc (this_frame
));
3070 /* Implementation of function hook 'prev_register' in
3071 'struct frame_uwnind'. */
3073 static struct value
*
3074 arm_m_exception_prev_register (struct frame_info
*this_frame
,
3078 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3079 struct arm_prologue_cache
*cache
;
3081 if (*this_cache
== NULL
)
3082 *this_cache
= arm_m_exception_cache (this_frame
);
3083 cache
= *this_cache
;
3085 /* The value was already reconstructed into PREV_SP. */
3086 if (prev_regnum
== ARM_SP_REGNUM
)
3087 return frame_unwind_got_constant (this_frame
, prev_regnum
,
3090 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
3094 /* Implementation of function hook 'sniffer' in
3095 'struct frame_uwnind'. */
3098 arm_m_exception_unwind_sniffer (const struct frame_unwind
*self
,
3099 struct frame_info
*this_frame
,
3100 void **this_prologue_cache
)
3102 CORE_ADDR this_pc
= get_frame_pc (this_frame
);
3104 /* No need to check is_m; this sniffer is only registered for
3105 M-profile architectures. */
3107 /* Exception frames return to one of these magic PCs. Other values
3108 are not defined as of v7-M. See details in "B1.5.8 Exception
3109 return behavior" in "ARMv7-M Architecture Reference Manual". */
3110 if (this_pc
== 0xfffffff1 || this_pc
== 0xfffffff9
3111 || this_pc
== 0xfffffffd)
3117 /* Frame unwinder for M-profile exceptions. */
3119 struct frame_unwind arm_m_exception_unwind
=
3122 default_frame_unwind_stop_reason
,
3123 arm_m_exception_this_id
,
3124 arm_m_exception_prev_register
,
3126 arm_m_exception_unwind_sniffer
3130 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
3132 struct arm_prologue_cache
*cache
;
3134 if (*this_cache
== NULL
)
3135 *this_cache
= arm_make_prologue_cache (this_frame
);
3136 cache
= *this_cache
;
3138 return cache
->prev_sp
- cache
->framesize
;
3141 struct frame_base arm_normal_base
= {
3142 &arm_prologue_unwind
,
3143 arm_normal_frame_base
,
3144 arm_normal_frame_base
,
3145 arm_normal_frame_base
3148 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3149 dummy frame. The frame ID's base needs to match the TOS value
3150 saved by save_dummy_frame_tos() and returned from
3151 arm_push_dummy_call, and the PC needs to match the dummy frame's
3154 static struct frame_id
3155 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3157 return frame_id_build (get_frame_register_unsigned (this_frame
,
3159 get_frame_pc (this_frame
));
3162 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3163 be used to construct the previous frame's ID, after looking up the
3164 containing function). */
3167 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3170 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
3171 return arm_addr_bits_remove (gdbarch
, pc
);
3175 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3177 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
3180 static struct value
*
3181 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
3184 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
3186 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
3191 /* The PC is normally copied from the return column, which
3192 describes saves of LR. However, that version may have an
3193 extra bit set to indicate Thumb state. The bit is not
3195 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3196 return frame_unwind_got_constant (this_frame
, regnum
,
3197 arm_addr_bits_remove (gdbarch
, lr
));
3200 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3201 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
3202 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3203 if (IS_THUMB_ADDR (lr
))
3207 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
3210 internal_error (__FILE__
, __LINE__
,
3211 _("Unexpected register %d"), regnum
);
3216 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3217 struct dwarf2_frame_state_reg
*reg
,
3218 struct frame_info
*this_frame
)
3224 reg
->how
= DWARF2_FRAME_REG_FN
;
3225 reg
->loc
.fn
= arm_dwarf2_prev_register
;
3228 reg
->how
= DWARF2_FRAME_REG_CFA
;
3233 /* Return true if we are in the function's epilogue, i.e. after the
3234 instruction that destroyed the function's stack frame. */
3237 thumb_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3239 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3240 unsigned int insn
, insn2
;
3241 int found_return
= 0, found_stack_adjust
= 0;
3242 CORE_ADDR func_start
, func_end
;
3246 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3249 /* The epilogue is a sequence of instructions along the following lines:
3251 - add stack frame size to SP or FP
3252 - [if frame pointer used] restore SP from FP
3253 - restore registers from SP [may include PC]
3254 - a return-type instruction [if PC wasn't already restored]
3256 In a first pass, we scan forward from the current PC and verify the
3257 instructions we find as compatible with this sequence, ending in a
3260 However, this is not sufficient to distinguish indirect function calls
3261 within a function from indirect tail calls in the epilogue in some cases.
3262 Therefore, if we didn't already find any SP-changing instruction during
3263 forward scan, we add a backward scanning heuristic to ensure we actually
3264 are in the epilogue. */
3267 while (scan_pc
< func_end
&& !found_return
)
3269 if (target_read_memory (scan_pc
, buf
, 2))
3273 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3275 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3277 else if (insn
== 0x46f7) /* mov pc, lr */
3279 else if (thumb_instruction_restores_sp (insn
))
3281 if ((insn
& 0xff00) == 0xbd00) /* pop <registers, PC> */
3284 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instruction */
3286 if (target_read_memory (scan_pc
, buf
, 2))
3290 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3292 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3294 if (insn2
& 0x8000) /* <registers> include PC. */
3297 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3298 && (insn2
& 0x0fff) == 0x0b04)
3300 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
3303 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3304 && (insn2
& 0x0e00) == 0x0a00)
3316 /* Since any instruction in the epilogue sequence, with the possible
3317 exception of return itself, updates the stack pointer, we need to
3318 scan backwards for at most one instruction. Try either a 16-bit or
3319 a 32-bit instruction. This is just a heuristic, so we do not worry
3320 too much about false positives. */
3322 if (pc
- 4 < func_start
)
3324 if (target_read_memory (pc
- 4, buf
, 4))
3327 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3328 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
3330 if (thumb_instruction_restores_sp (insn2
))
3331 found_stack_adjust
= 1;
3332 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3333 found_stack_adjust
= 1;
3334 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3335 && (insn2
& 0x0fff) == 0x0b04)
3336 found_stack_adjust
= 1;
3337 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3338 && (insn2
& 0x0e00) == 0x0a00)
3339 found_stack_adjust
= 1;
3341 return found_stack_adjust
;
3344 /* Return true if we are in the function's epilogue, i.e. after the
3345 instruction that destroyed the function's stack frame. */
3348 arm_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3350 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3352 int found_return
, found_stack_adjust
;
3353 CORE_ADDR func_start
, func_end
;
3355 if (arm_pc_is_thumb (gdbarch
, pc
))
3356 return thumb_in_function_epilogue_p (gdbarch
, pc
);
3358 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3361 /* We are in the epilogue if the previous instruction was a stack
3362 adjustment and the next instruction is a possible return (bx, mov
3363 pc, or pop). We could have to scan backwards to find the stack
3364 adjustment, or forwards to find the return, but this is a decent
3365 approximation. First scan forwards. */
3368 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3369 if (bits (insn
, 28, 31) != INST_NV
)
3371 if ((insn
& 0x0ffffff0) == 0x012fff10)
3374 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
3377 else if ((insn
& 0x0fff0000) == 0x08bd0000
3378 && (insn
& 0x0000c000) != 0)
3379 /* POP (LDMIA), including PC or LR. */
3386 /* Scan backwards. This is just a heuristic, so do not worry about
3387 false positives from mode changes. */
3389 if (pc
< func_start
+ 4)
3392 found_stack_adjust
= 0;
3393 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
3394 if (bits (insn
, 28, 31) != INST_NV
)
3396 if ((insn
& 0x0df0f000) == 0x0080d000)
3397 /* ADD SP (register or immediate). */
3398 found_stack_adjust
= 1;
3399 else if ((insn
& 0x0df0f000) == 0x0040d000)
3400 /* SUB SP (register or immediate). */
3401 found_stack_adjust
= 1;
3402 else if ((insn
& 0x0ffffff0) == 0x01a0d000)
3404 found_stack_adjust
= 1;
3405 else if ((insn
& 0x0fff0000) == 0x08bd0000)
3407 found_stack_adjust
= 1;
3408 else if ((insn
& 0x0fff0000) == 0x049d0000)
3409 /* POP of a single register. */
3410 found_stack_adjust
= 1;
3413 if (found_stack_adjust
)
3420 /* When arguments must be pushed onto the stack, they go on in reverse
3421 order. The code below implements a FILO (stack) to do this. */
3426 struct stack_item
*prev
;
3430 static struct stack_item
*
3431 push_stack_item (struct stack_item
*prev
, const void *contents
, int len
)
3433 struct stack_item
*si
;
3434 si
= xmalloc (sizeof (struct stack_item
));
3435 si
->data
= xmalloc (len
);
3438 memcpy (si
->data
, contents
, len
);
3442 static struct stack_item
*
3443 pop_stack_item (struct stack_item
*si
)
3445 struct stack_item
*dead
= si
;
3453 /* Return the alignment (in bytes) of the given type. */
3456 arm_type_align (struct type
*t
)
3462 t
= check_typedef (t
);
3463 switch (TYPE_CODE (t
))
3466 /* Should never happen. */
3467 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
3471 case TYPE_CODE_ENUM
:
3475 case TYPE_CODE_RANGE
:
3477 case TYPE_CODE_CHAR
:
3478 case TYPE_CODE_BOOL
:
3479 return TYPE_LENGTH (t
);
3481 case TYPE_CODE_ARRAY
:
3482 case TYPE_CODE_COMPLEX
:
3483 /* TODO: What about vector types? */
3484 return arm_type_align (TYPE_TARGET_TYPE (t
));
3486 case TYPE_CODE_STRUCT
:
3487 case TYPE_CODE_UNION
:
3489 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
3491 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
3499 /* Possible base types for a candidate for passing and returning in
3502 enum arm_vfp_cprc_base_type
3511 /* The length of one element of base type B. */
3514 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
3518 case VFP_CPRC_SINGLE
:
3520 case VFP_CPRC_DOUBLE
:
3522 case VFP_CPRC_VEC64
:
3524 case VFP_CPRC_VEC128
:
3527 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3532 /* The character ('s', 'd' or 'q') for the type of VFP register used
3533 for passing base type B. */
3536 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
3540 case VFP_CPRC_SINGLE
:
3542 case VFP_CPRC_DOUBLE
:
3544 case VFP_CPRC_VEC64
:
3546 case VFP_CPRC_VEC128
:
3549 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3554 /* Determine whether T may be part of a candidate for passing and
3555 returning in VFP registers, ignoring the limit on the total number
3556 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3557 classification of the first valid component found; if it is not
3558 VFP_CPRC_UNKNOWN, all components must have the same classification
3559 as *BASE_TYPE. If it is found that T contains a type not permitted
3560 for passing and returning in VFP registers, a type differently
3561 classified from *BASE_TYPE, or two types differently classified
3562 from each other, return -1, otherwise return the total number of
3563 base-type elements found (possibly 0 in an empty structure or
3564 array). Vector types are not currently supported, matching the
3565 generic AAPCS support. */
3568 arm_vfp_cprc_sub_candidate (struct type
*t
,
3569 enum arm_vfp_cprc_base_type
*base_type
)
3571 t
= check_typedef (t
);
3572 switch (TYPE_CODE (t
))
3575 switch (TYPE_LENGTH (t
))
3578 if (*base_type
== VFP_CPRC_UNKNOWN
)
3579 *base_type
= VFP_CPRC_SINGLE
;
3580 else if (*base_type
!= VFP_CPRC_SINGLE
)
3585 if (*base_type
== VFP_CPRC_UNKNOWN
)
3586 *base_type
= VFP_CPRC_DOUBLE
;
3587 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3596 case TYPE_CODE_COMPLEX
:
3597 /* Arguments of complex T where T is one of the types float or
3598 double get treated as if they are implemented as:
3607 switch (TYPE_LENGTH (t
))
3610 if (*base_type
== VFP_CPRC_UNKNOWN
)
3611 *base_type
= VFP_CPRC_SINGLE
;
3612 else if (*base_type
!= VFP_CPRC_SINGLE
)
3617 if (*base_type
== VFP_CPRC_UNKNOWN
)
3618 *base_type
= VFP_CPRC_DOUBLE
;
3619 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3628 case TYPE_CODE_ARRAY
:
3632 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
), base_type
);
3635 if (TYPE_LENGTH (t
) == 0)
3637 gdb_assert (count
== 0);
3640 else if (count
== 0)
3642 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3643 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
3644 return TYPE_LENGTH (t
) / unitlen
;
3648 case TYPE_CODE_STRUCT
:
3653 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3655 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3657 if (sub_count
== -1)
3661 if (TYPE_LENGTH (t
) == 0)
3663 gdb_assert (count
== 0);
3666 else if (count
== 0)
3668 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3669 if (TYPE_LENGTH (t
) != unitlen
* count
)
3674 case TYPE_CODE_UNION
:
3679 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3681 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3683 if (sub_count
== -1)
3685 count
= (count
> sub_count
? count
: sub_count
);
3687 if (TYPE_LENGTH (t
) == 0)
3689 gdb_assert (count
== 0);
3692 else if (count
== 0)
3694 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3695 if (TYPE_LENGTH (t
) != unitlen
* count
)
3707 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3708 if passed to or returned from a non-variadic function with the VFP
3709 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3710 *BASE_TYPE to the base type for T and *COUNT to the number of
3711 elements of that base type before returning. */
3714 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
3717 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
3718 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
3719 if (c
<= 0 || c
> 4)
3726 /* Return 1 if the VFP ABI should be used for passing arguments to and
3727 returning values from a function of type FUNC_TYPE, 0
3731 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
3733 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3734 /* Variadic functions always use the base ABI. Assume that functions
3735 without debug info are not variadic. */
3736 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
3738 /* The VFP ABI is only supported as a variant of AAPCS. */
3739 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
3741 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
3744 /* We currently only support passing parameters in integer registers, which
3745 conforms with GCC's default model, and VFP argument passing following
3746 the VFP variant of AAPCS. Several other variants exist and
3747 we should probably support some of them based on the selected ABI. */
3750 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3751 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3752 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3753 CORE_ADDR struct_addr
)
3755 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3759 struct stack_item
*si
= NULL
;
3762 unsigned vfp_regs_free
= (1 << 16) - 1;
3764 /* Determine the type of this function and whether the VFP ABI
3766 ftype
= check_typedef (value_type (function
));
3767 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
3768 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
3769 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
3771 /* Set the return address. For the ARM, the return breakpoint is
3772 always at BP_ADDR. */
3773 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
3775 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
3777 /* Walk through the list of args and determine how large a temporary
3778 stack is required. Need to take care here as structs may be
3779 passed on the stack, and we have to push them. */
3782 argreg
= ARM_A1_REGNUM
;
3785 /* The struct_return pointer occupies the first parameter
3786 passing register. */
3790 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
3791 gdbarch_register_name (gdbarch
, argreg
),
3792 paddress (gdbarch
, struct_addr
));
3793 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
3797 for (argnum
= 0; argnum
< nargs
; argnum
++)
3800 struct type
*arg_type
;
3801 struct type
*target_type
;
3802 enum type_code typecode
;
3803 const bfd_byte
*val
;
3805 enum arm_vfp_cprc_base_type vfp_base_type
;
3807 int may_use_core_reg
= 1;
3809 arg_type
= check_typedef (value_type (args
[argnum
]));
3810 len
= TYPE_LENGTH (arg_type
);
3811 target_type
= TYPE_TARGET_TYPE (arg_type
);
3812 typecode
= TYPE_CODE (arg_type
);
3813 val
= value_contents (args
[argnum
]);
3815 align
= arm_type_align (arg_type
);
3816 /* Round alignment up to a whole number of words. */
3817 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
3818 /* Different ABIs have different maximum alignments. */
3819 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
3821 /* The APCS ABI only requires word alignment. */
3822 align
= INT_REGISTER_SIZE
;
3826 /* The AAPCS requires at most doubleword alignment. */
3827 if (align
> INT_REGISTER_SIZE
* 2)
3828 align
= INT_REGISTER_SIZE
* 2;
3832 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
3840 /* Because this is a CPRC it cannot go in a core register or
3841 cause a core register to be skipped for alignment.
3842 Either it goes in VFP registers and the rest of this loop
3843 iteration is skipped for this argument, or it goes on the
3844 stack (and the stack alignment code is correct for this
3846 may_use_core_reg
= 0;
3848 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
3849 shift
= unit_length
/ 4;
3850 mask
= (1 << (shift
* vfp_base_count
)) - 1;
3851 for (regno
= 0; regno
< 16; regno
+= shift
)
3852 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
3861 vfp_regs_free
&= ~(mask
<< regno
);
3862 reg_scaled
= regno
/ shift
;
3863 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
3864 for (i
= 0; i
< vfp_base_count
; i
++)
3868 if (reg_char
== 'q')
3869 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
3870 val
+ i
* unit_length
);
3873 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d",
3874 reg_char
, reg_scaled
+ i
);
3875 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3877 regcache_cooked_write (regcache
, regnum
,
3878 val
+ i
* unit_length
);
3885 /* This CPRC could not go in VFP registers, so all VFP
3886 registers are now marked as used. */
3891 /* Push stack padding for dowubleword alignment. */
3892 if (nstack
& (align
- 1))
3894 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3895 nstack
+= INT_REGISTER_SIZE
;
3898 /* Doubleword aligned quantities must go in even register pairs. */
3899 if (may_use_core_reg
3900 && argreg
<= ARM_LAST_ARG_REGNUM
3901 && align
> INT_REGISTER_SIZE
3905 /* If the argument is a pointer to a function, and it is a
3906 Thumb function, create a LOCAL copy of the value and set
3907 the THUMB bit in it. */
3908 if (TYPE_CODE_PTR
== typecode
3909 && target_type
!= NULL
3910 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
3912 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
3913 if (arm_pc_is_thumb (gdbarch
, regval
))
3915 bfd_byte
*copy
= alloca (len
);
3916 store_unsigned_integer (copy
, len
, byte_order
,
3917 MAKE_THUMB_ADDR (regval
));
3922 /* Copy the argument to general registers or the stack in
3923 register-sized pieces. Large arguments are split between
3924 registers and stack. */
3927 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
3929 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
3931 /* The argument is being passed in a general purpose
3934 = extract_unsigned_integer (val
, partial_len
, byte_order
);
3935 if (byte_order
== BFD_ENDIAN_BIG
)
3936 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
3938 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
3940 gdbarch_register_name
3942 phex (regval
, INT_REGISTER_SIZE
));
3943 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3948 /* Push the arguments onto the stack. */
3950 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
3952 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3953 nstack
+= INT_REGISTER_SIZE
;
3960 /* If we have an odd number of words to push, then decrement the stack
3961 by one word now, so first stack argument will be dword aligned. */
3968 write_memory (sp
, si
->data
, si
->len
);
3969 si
= pop_stack_item (si
);
3972 /* Finally, update teh SP register. */
3973 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
3979 /* Always align the frame to an 8-byte boundary. This is required on
3980 some platforms and harmless on the rest. */
3983 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3985 /* Align the stack to eight bytes. */
3986 return sp
& ~ (CORE_ADDR
) 7;
3990 print_fpu_flags (struct ui_file
*file
, int flags
)
3992 if (flags
& (1 << 0))
3993 fputs_filtered ("IVO ", file
);
3994 if (flags
& (1 << 1))
3995 fputs_filtered ("DVZ ", file
);
3996 if (flags
& (1 << 2))
3997 fputs_filtered ("OFL ", file
);
3998 if (flags
& (1 << 3))
3999 fputs_filtered ("UFL ", file
);
4000 if (flags
& (1 << 4))
4001 fputs_filtered ("INX ", file
);
4002 fputc_filtered ('\n', file
);
4005 /* Print interesting information about the floating point processor
4006 (if present) or emulator. */
4008 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4009 struct frame_info
*frame
, const char *args
)
4011 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
4014 type
= (status
>> 24) & 127;
4015 if (status
& (1 << 31))
4016 fprintf_filtered (file
, _("Hardware FPU type %d\n"), type
);
4018 fprintf_filtered (file
, _("Software FPU type %d\n"), type
);
4019 /* i18n: [floating point unit] mask */
4020 fputs_filtered (_("mask: "), file
);
4021 print_fpu_flags (file
, status
>> 16);
4022 /* i18n: [floating point unit] flags */
4023 fputs_filtered (_("flags: "), file
);
4024 print_fpu_flags (file
, status
);
4027 /* Construct the ARM extended floating point type. */
4028 static struct type
*
4029 arm_ext_type (struct gdbarch
*gdbarch
)
4031 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4033 if (!tdep
->arm_ext_type
)
4035 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
4036 floatformats_arm_ext
);
4038 return tdep
->arm_ext_type
;
4041 static struct type
*
4042 arm_neon_double_type (struct gdbarch
*gdbarch
)
4044 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4046 if (tdep
->neon_double_type
== NULL
)
4048 struct type
*t
, *elem
;
4050 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
4052 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4053 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
4054 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4055 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
4056 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4057 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
4058 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4059 append_composite_type_field (t
, "u64", elem
);
4060 elem
= builtin_type (gdbarch
)->builtin_float
;
4061 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
4062 elem
= builtin_type (gdbarch
)->builtin_double
;
4063 append_composite_type_field (t
, "f64", elem
);
4065 TYPE_VECTOR (t
) = 1;
4066 TYPE_NAME (t
) = "neon_d";
4067 tdep
->neon_double_type
= t
;
4070 return tdep
->neon_double_type
;
4073 /* FIXME: The vector types are not correctly ordered on big-endian
4074 targets. Just as s0 is the low bits of d0, d0[0] is also the low
4075 bits of d0 - regardless of what unit size is being held in d0. So
4076 the offset of the first uint8 in d0 is 7, but the offset of the
4077 first float is 4. This code works as-is for little-endian
4080 static struct type
*
4081 arm_neon_quad_type (struct gdbarch
*gdbarch
)
4083 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4085 if (tdep
->neon_quad_type
== NULL
)
4087 struct type
*t
, *elem
;
4089 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
4091 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4092 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
4093 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4094 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
4095 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4096 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
4097 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4098 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
4099 elem
= builtin_type (gdbarch
)->builtin_float
;
4100 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
4101 elem
= builtin_type (gdbarch
)->builtin_double
;
4102 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
4104 TYPE_VECTOR (t
) = 1;
4105 TYPE_NAME (t
) = "neon_q";
4106 tdep
->neon_quad_type
= t
;
4109 return tdep
->neon_quad_type
;
4112 /* Return the GDB type object for the "standard" data type of data in
4115 static struct type
*
4116 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
4118 int num_regs
= gdbarch_num_regs (gdbarch
);
4120 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
4121 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
4122 return builtin_type (gdbarch
)->builtin_float
;
4124 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
4125 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
4126 return arm_neon_quad_type (gdbarch
);
4128 /* If the target description has register information, we are only
4129 in this function so that we can override the types of
4130 double-precision registers for NEON. */
4131 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
4133 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
4135 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
4136 && TYPE_CODE (t
) == TYPE_CODE_FLT
4137 && gdbarch_tdep (gdbarch
)->have_neon
)
4138 return arm_neon_double_type (gdbarch
);
4143 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
4145 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
4146 return builtin_type (gdbarch
)->builtin_void
;
4148 return arm_ext_type (gdbarch
);
4150 else if (regnum
== ARM_SP_REGNUM
)
4151 return builtin_type (gdbarch
)->builtin_data_ptr
;
4152 else if (regnum
== ARM_PC_REGNUM
)
4153 return builtin_type (gdbarch
)->builtin_func_ptr
;
4154 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
4155 /* These registers are only supported on targets which supply
4156 an XML description. */
4157 return builtin_type (gdbarch
)->builtin_int0
;
4159 return builtin_type (gdbarch
)->builtin_uint32
;
4162 /* Map a DWARF register REGNUM onto the appropriate GDB register
4166 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
4168 /* Core integer regs. */
4169 if (reg
>= 0 && reg
<= 15)
4172 /* Legacy FPA encoding. These were once used in a way which
4173 overlapped with VFP register numbering, so their use is
4174 discouraged, but GDB doesn't support the ARM toolchain
4175 which used them for VFP. */
4176 if (reg
>= 16 && reg
<= 23)
4177 return ARM_F0_REGNUM
+ reg
- 16;
4179 /* New assignments for the FPA registers. */
4180 if (reg
>= 96 && reg
<= 103)
4181 return ARM_F0_REGNUM
+ reg
- 96;
4183 /* WMMX register assignments. */
4184 if (reg
>= 104 && reg
<= 111)
4185 return ARM_WCGR0_REGNUM
+ reg
- 104;
4187 if (reg
>= 112 && reg
<= 127)
4188 return ARM_WR0_REGNUM
+ reg
- 112;
4190 if (reg
>= 192 && reg
<= 199)
4191 return ARM_WC0_REGNUM
+ reg
- 192;
4193 /* VFP v2 registers. A double precision value is actually
4194 in d1 rather than s2, but the ABI only defines numbering
4195 for the single precision registers. This will "just work"
4196 in GDB for little endian targets (we'll read eight bytes,
4197 starting in s0 and then progressing to s1), but will be
4198 reversed on big endian targets with VFP. This won't
4199 be a problem for the new Neon quad registers; you're supposed
4200 to use DW_OP_piece for those. */
4201 if (reg
>= 64 && reg
<= 95)
4205 xsnprintf (name_buf
, sizeof (name_buf
), "s%d", reg
- 64);
4206 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4210 /* VFP v3 / Neon registers. This range is also used for VFP v2
4211 registers, except that it now describes d0 instead of s0. */
4212 if (reg
>= 256 && reg
<= 287)
4216 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", reg
- 256);
4217 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4224 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4226 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
4229 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
4231 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
4232 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
4234 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
4235 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
4237 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
4238 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
4240 if (reg
< NUM_GREGS
)
4241 return SIM_ARM_R0_REGNUM
+ reg
;
4244 if (reg
< NUM_FREGS
)
4245 return SIM_ARM_FP0_REGNUM
+ reg
;
4248 if (reg
< NUM_SREGS
)
4249 return SIM_ARM_FPS_REGNUM
+ reg
;
4252 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
4255 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4256 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4257 It is thought that this is is the floating-point register format on
4258 little-endian systems. */
4261 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
4262 void *dbl
, int endianess
)
4266 if (endianess
== BFD_ENDIAN_BIG
)
4267 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
4269 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4271 floatformat_from_doublest (fmt
, &d
, dbl
);
4275 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
4280 floatformat_to_doublest (fmt
, ptr
, &d
);
4281 if (endianess
== BFD_ENDIAN_BIG
)
4282 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
4284 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4289 condition_true (unsigned long cond
, unsigned long status_reg
)
4291 if (cond
== INST_AL
|| cond
== INST_NV
)
4297 return ((status_reg
& FLAG_Z
) != 0);
4299 return ((status_reg
& FLAG_Z
) == 0);
4301 return ((status_reg
& FLAG_C
) != 0);
4303 return ((status_reg
& FLAG_C
) == 0);
4305 return ((status_reg
& FLAG_N
) != 0);
4307 return ((status_reg
& FLAG_N
) == 0);
4309 return ((status_reg
& FLAG_V
) != 0);
4311 return ((status_reg
& FLAG_V
) == 0);
4313 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
4315 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
4317 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
4319 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
4321 return (((status_reg
& FLAG_Z
) == 0)
4322 && (((status_reg
& FLAG_N
) == 0)
4323 == ((status_reg
& FLAG_V
) == 0)));
4325 return (((status_reg
& FLAG_Z
) != 0)
4326 || (((status_reg
& FLAG_N
) == 0)
4327 != ((status_reg
& FLAG_V
) == 0)));
4332 static unsigned long
4333 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
4334 unsigned long pc_val
, unsigned long status_reg
)
4336 unsigned long res
, shift
;
4337 int rm
= bits (inst
, 0, 3);
4338 unsigned long shifttype
= bits (inst
, 5, 6);
4342 int rs
= bits (inst
, 8, 11);
4343 shift
= (rs
== 15 ? pc_val
+ 8
4344 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
4347 shift
= bits (inst
, 7, 11);
4349 res
= (rm
== ARM_PC_REGNUM
4350 ? (pc_val
+ (bit (inst
, 4) ? 12 : 8))
4351 : get_frame_register_unsigned (frame
, rm
));
4356 res
= shift
>= 32 ? 0 : res
<< shift
;
4360 res
= shift
>= 32 ? 0 : res
>> shift
;
4366 res
= ((res
& 0x80000000L
)
4367 ? ~((~res
) >> shift
) : res
>> shift
);
4370 case 3: /* ROR/RRX */
4373 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
4375 res
= (res
>> shift
) | (res
<< (32 - shift
));
4379 return res
& 0xffffffff;
4382 /* Return number of 1-bits in VAL. */
4385 bitcount (unsigned long val
)
4388 for (nbits
= 0; val
!= 0; nbits
++)
4389 val
&= val
- 1; /* Delete rightmost 1-bit in val. */
4393 /* Return the size in bytes of the complete Thumb instruction whose
4394 first halfword is INST1. */
4397 thumb_insn_size (unsigned short inst1
)
4399 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
4406 thumb_advance_itstate (unsigned int itstate
)
4408 /* Preserve IT[7:5], the first three bits of the condition. Shift
4409 the upcoming condition flags left by one bit. */
4410 itstate
= (itstate
& 0xe0) | ((itstate
<< 1) & 0x1f);
4412 /* If we have finished the IT block, clear the state. */
4413 if ((itstate
& 0x0f) == 0)
4419 /* Find the next PC after the current instruction executes. In some
4420 cases we can not statically determine the answer (see the IT state
4421 handling in this function); in that case, a breakpoint may be
4422 inserted in addition to the returned PC, which will be used to set
4423 another breakpoint by our caller. */
4426 thumb_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
)
4428 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4429 struct address_space
*aspace
= get_frame_address_space (frame
);
4430 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4431 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4432 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
4433 unsigned short inst1
;
4434 CORE_ADDR nextpc
= pc
+ 2; /* Default is next instruction. */
4435 unsigned long offset
;
4436 ULONGEST status
, itstate
;
4438 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4439 pc_val
= MAKE_THUMB_ADDR (pc_val
);
4441 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
4443 /* Thumb-2 conditional execution support. There are eight bits in
4444 the CPSR which describe conditional execution state. Once
4445 reconstructed (they're in a funny order), the low five bits
4446 describe the low bit of the condition for each instruction and
4447 how many instructions remain. The high three bits describe the
4448 base condition. One of the low four bits will be set if an IT
4449 block is active. These bits read as zero on earlier
4451 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
4452 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
4454 /* If-Then handling. On GNU/Linux, where this routine is used, we
4455 use an undefined instruction as a breakpoint. Unlike BKPT, IT
4456 can disable execution of the undefined instruction. So we might
4457 miss the breakpoint if we set it on a skipped conditional
4458 instruction. Because conditional instructions can change the
4459 flags, affecting the execution of further instructions, we may
4460 need to set two breakpoints. */
4462 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
!= NULL
)
4464 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4466 /* An IT instruction. Because this instruction does not
4467 modify the flags, we can accurately predict the next
4468 executed instruction. */
4469 itstate
= inst1
& 0x00ff;
4470 pc
+= thumb_insn_size (inst1
);
4472 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
4474 inst1
= read_memory_unsigned_integer (pc
, 2,
4475 byte_order_for_code
);
4476 pc
+= thumb_insn_size (inst1
);
4477 itstate
= thumb_advance_itstate (itstate
);
4480 return MAKE_THUMB_ADDR (pc
);
4482 else if (itstate
!= 0)
4484 /* We are in a conditional block. Check the condition. */
4485 if (! condition_true (itstate
>> 4, status
))
4487 /* Advance to the next executed instruction. */
4488 pc
+= thumb_insn_size (inst1
);
4489 itstate
= thumb_advance_itstate (itstate
);
4491 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
4493 inst1
= read_memory_unsigned_integer (pc
, 2,
4494 byte_order_for_code
);
4495 pc
+= thumb_insn_size (inst1
);
4496 itstate
= thumb_advance_itstate (itstate
);
4499 return MAKE_THUMB_ADDR (pc
);
4501 else if ((itstate
& 0x0f) == 0x08)
4503 /* This is the last instruction of the conditional
4504 block, and it is executed. We can handle it normally
4505 because the following instruction is not conditional,
4506 and we must handle it normally because it is
4507 permitted to branch. Fall through. */
4513 /* There are conditional instructions after this one.
4514 If this instruction modifies the flags, then we can
4515 not predict what the next executed instruction will
4516 be. Fortunately, this instruction is architecturally
4517 forbidden to branch; we know it will fall through.
4518 Start by skipping past it. */
4519 pc
+= thumb_insn_size (inst1
);
4520 itstate
= thumb_advance_itstate (itstate
);
4522 /* Set a breakpoint on the following instruction. */
4523 gdb_assert ((itstate
& 0x0f) != 0);
4524 arm_insert_single_step_breakpoint (gdbarch
, aspace
,
4525 MAKE_THUMB_ADDR (pc
));
4526 cond_negated
= (itstate
>> 4) & 1;
4528 /* Skip all following instructions with the same
4529 condition. If there is a later instruction in the IT
4530 block with the opposite condition, set the other
4531 breakpoint there. If not, then set a breakpoint on
4532 the instruction after the IT block. */
4535 inst1
= read_memory_unsigned_integer (pc
, 2,
4536 byte_order_for_code
);
4537 pc
+= thumb_insn_size (inst1
);
4538 itstate
= thumb_advance_itstate (itstate
);
4540 while (itstate
!= 0 && ((itstate
>> 4) & 1) == cond_negated
);
4542 return MAKE_THUMB_ADDR (pc
);
4546 else if (itstate
& 0x0f)
4548 /* We are in a conditional block. Check the condition. */
4549 int cond
= itstate
>> 4;
4551 if (! condition_true (cond
, status
))
4552 /* Advance to the next instruction. All the 32-bit
4553 instructions share a common prefix. */
4554 return MAKE_THUMB_ADDR (pc
+ thumb_insn_size (inst1
));
4556 /* Otherwise, handle the instruction normally. */
4559 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
4563 /* Fetch the saved PC from the stack. It's stored above
4564 all of the other registers. */
4565 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
4566 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
4567 nextpc
= read_memory_unsigned_integer (sp
+ offset
, 4, byte_order
);
4569 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
4571 unsigned long cond
= bits (inst1
, 8, 11);
4572 if (cond
== 0x0f) /* 0x0f = SWI */
4574 struct gdbarch_tdep
*tdep
;
4575 tdep
= gdbarch_tdep (gdbarch
);
4577 if (tdep
->syscall_next_pc
!= NULL
)
4578 nextpc
= tdep
->syscall_next_pc (frame
);
4581 else if (cond
!= 0x0f && condition_true (cond
, status
))
4582 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
4584 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
4586 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
4588 else if (thumb_insn_size (inst1
) == 4) /* 32-bit instruction */
4590 unsigned short inst2
;
4591 inst2
= read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
4593 /* Default to the next instruction. */
4595 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4597 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
4599 /* Branches and miscellaneous control instructions. */
4601 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
4604 int j1
, j2
, imm1
, imm2
;
4606 imm1
= sbits (inst1
, 0, 10);
4607 imm2
= bits (inst2
, 0, 10);
4608 j1
= bit (inst2
, 13);
4609 j2
= bit (inst2
, 11);
4611 offset
= ((imm1
<< 12) + (imm2
<< 1));
4612 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
4614 nextpc
= pc_val
+ offset
;
4615 /* For BLX make sure to clear the low bits. */
4616 if (bit (inst2
, 12) == 0)
4617 nextpc
= nextpc
& 0xfffffffc;
4619 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
4621 /* SUBS PC, LR, #imm8. */
4622 nextpc
= get_frame_register_unsigned (frame
, ARM_LR_REGNUM
);
4623 nextpc
-= inst2
& 0x00ff;
4625 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
4627 /* Conditional branch. */
4628 if (condition_true (bits (inst1
, 6, 9), status
))
4630 int sign
, j1
, j2
, imm1
, imm2
;
4632 sign
= sbits (inst1
, 10, 10);
4633 imm1
= bits (inst1
, 0, 5);
4634 imm2
= bits (inst2
, 0, 10);
4635 j1
= bit (inst2
, 13);
4636 j2
= bit (inst2
, 11);
4638 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
4639 offset
+= (imm1
<< 12) + (imm2
<< 1);
4641 nextpc
= pc_val
+ offset
;
4645 else if ((inst1
& 0xfe50) == 0xe810)
4647 /* Load multiple or RFE. */
4648 int rn
, offset
, load_pc
= 1;
4650 rn
= bits (inst1
, 0, 3);
4651 if (bit (inst1
, 7) && !bit (inst1
, 8))
4654 if (!bit (inst2
, 15))
4656 offset
= bitcount (inst2
) * 4 - 4;
4658 else if (!bit (inst1
, 7) && bit (inst1
, 8))
4661 if (!bit (inst2
, 15))
4665 else if (bit (inst1
, 7) && bit (inst1
, 8))
4670 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
4680 CORE_ADDR addr
= get_frame_register_unsigned (frame
, rn
);
4681 nextpc
= get_frame_memory_unsigned (frame
, addr
+ offset
, 4);
4684 else if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
4686 /* MOV PC or MOVS PC. */
4687 nextpc
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4688 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4690 else if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
4694 int rn
, load_pc
= 1;
4696 rn
= bits (inst1
, 0, 3);
4697 base
= get_frame_register_unsigned (frame
, rn
);
4698 if (rn
== ARM_PC_REGNUM
)
4700 base
= (base
+ 4) & ~(CORE_ADDR
) 0x3;
4702 base
+= bits (inst2
, 0, 11);
4704 base
-= bits (inst2
, 0, 11);
4706 else if (bit (inst1
, 7))
4707 base
+= bits (inst2
, 0, 11);
4708 else if (bit (inst2
, 11))
4710 if (bit (inst2
, 10))
4713 base
+= bits (inst2
, 0, 7);
4715 base
-= bits (inst2
, 0, 7);
4718 else if ((inst2
& 0x0fc0) == 0x0000)
4720 int shift
= bits (inst2
, 4, 5), rm
= bits (inst2
, 0, 3);
4721 base
+= get_frame_register_unsigned (frame
, rm
) << shift
;
4728 nextpc
= get_frame_memory_unsigned (frame
, base
, 4);
4730 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
4733 CORE_ADDR tbl_reg
, table
, offset
, length
;
4735 tbl_reg
= bits (inst1
, 0, 3);
4736 if (tbl_reg
== 0x0f)
4737 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
4739 table
= get_frame_register_unsigned (frame
, tbl_reg
);
4741 offset
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4742 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 1);
4743 nextpc
= pc_val
+ length
;
4745 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
4748 CORE_ADDR tbl_reg
, table
, offset
, length
;
4750 tbl_reg
= bits (inst1
, 0, 3);
4751 if (tbl_reg
== 0x0f)
4752 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
4754 table
= get_frame_register_unsigned (frame
, tbl_reg
);
4756 offset
= 2 * get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4757 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 2);
4758 nextpc
= pc_val
+ length
;
4761 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
4763 if (bits (inst1
, 3, 6) == 0x0f)
4764 nextpc
= UNMAKE_THUMB_ADDR (pc_val
);
4766 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
4768 else if ((inst1
& 0xff87) == 0x4687) /* mov pc, REG */
4770 if (bits (inst1
, 3, 6) == 0x0f)
4773 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
4775 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4777 else if ((inst1
& 0xf500) == 0xb100)
4780 int imm
= (bit (inst1
, 9) << 6) + (bits (inst1
, 3, 7) << 1);
4781 ULONGEST reg
= get_frame_register_unsigned (frame
, bits (inst1
, 0, 2));
4783 if (bit (inst1
, 11) && reg
!= 0)
4784 nextpc
= pc_val
+ imm
;
4785 else if (!bit (inst1
, 11) && reg
== 0)
4786 nextpc
= pc_val
+ imm
;
4791 /* Get the raw next address. PC is the current program counter, in
4792 FRAME, which is assumed to be executing in ARM mode.
4794 The value returned has the execution state of the next instruction
4795 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
4796 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
4800 arm_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
)
4802 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4803 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4804 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4805 unsigned long pc_val
;
4806 unsigned long this_instr
;
4807 unsigned long status
;
4810 pc_val
= (unsigned long) pc
;
4811 this_instr
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
4813 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
4814 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
4816 if (bits (this_instr
, 28, 31) == INST_NV
)
4817 switch (bits (this_instr
, 24, 27))
4822 /* Branch with Link and change to Thumb. */
4823 nextpc
= BranchDest (pc
, this_instr
);
4824 nextpc
|= bit (this_instr
, 24) << 1;
4825 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4831 /* Coprocessor register transfer. */
4832 if (bits (this_instr
, 12, 15) == 15)
4833 error (_("Invalid update to pc in instruction"));
4836 else if (condition_true (bits (this_instr
, 28, 31), status
))
4838 switch (bits (this_instr
, 24, 27))
4841 case 0x1: /* data processing */
4845 unsigned long operand1
, operand2
, result
= 0;
4849 if (bits (this_instr
, 12, 15) != 15)
4852 if (bits (this_instr
, 22, 25) == 0
4853 && bits (this_instr
, 4, 7) == 9) /* multiply */
4854 error (_("Invalid update to pc in instruction"));
4856 /* BX <reg>, BLX <reg> */
4857 if (bits (this_instr
, 4, 27) == 0x12fff1
4858 || bits (this_instr
, 4, 27) == 0x12fff3)
4860 rn
= bits (this_instr
, 0, 3);
4861 nextpc
= ((rn
== ARM_PC_REGNUM
)
4863 : get_frame_register_unsigned (frame
, rn
));
4868 /* Multiply into PC. */
4869 c
= (status
& FLAG_C
) ? 1 : 0;
4870 rn
= bits (this_instr
, 16, 19);
4871 operand1
= ((rn
== ARM_PC_REGNUM
)
4873 : get_frame_register_unsigned (frame
, rn
));
4875 if (bit (this_instr
, 25))
4877 unsigned long immval
= bits (this_instr
, 0, 7);
4878 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
4879 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
4882 else /* operand 2 is a shifted register. */
4883 operand2
= shifted_reg_val (frame
, this_instr
, c
,
4886 switch (bits (this_instr
, 21, 24))
4889 result
= operand1
& operand2
;
4893 result
= operand1
^ operand2
;
4897 result
= operand1
- operand2
;
4901 result
= operand2
- operand1
;
4905 result
= operand1
+ operand2
;
4909 result
= operand1
+ operand2
+ c
;
4913 result
= operand1
- operand2
+ c
;
4917 result
= operand2
- operand1
+ c
;
4923 case 0xb: /* tst, teq, cmp, cmn */
4924 result
= (unsigned long) nextpc
;
4928 result
= operand1
| operand2
;
4932 /* Always step into a function. */
4937 result
= operand1
& ~operand2
;
4945 /* In 26-bit APCS the bottom two bits of the result are
4946 ignored, and we always end up in ARM state. */
4948 nextpc
= arm_addr_bits_remove (gdbarch
, result
);
4956 case 0x5: /* data transfer */
4959 if (bit (this_instr
, 20))
4962 if (bits (this_instr
, 12, 15) == 15)
4968 if (bit (this_instr
, 22))
4969 error (_("Invalid update to pc in instruction"));
4971 /* byte write to PC */
4972 rn
= bits (this_instr
, 16, 19);
4973 base
= ((rn
== ARM_PC_REGNUM
)
4975 : get_frame_register_unsigned (frame
, rn
));
4977 if (bit (this_instr
, 24))
4980 int c
= (status
& FLAG_C
) ? 1 : 0;
4981 unsigned long offset
=
4982 (bit (this_instr
, 25)
4983 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
4984 : bits (this_instr
, 0, 11));
4986 if (bit (this_instr
, 23))
4992 (CORE_ADDR
) read_memory_unsigned_integer ((CORE_ADDR
) base
,
4999 case 0x9: /* block transfer */
5000 if (bit (this_instr
, 20))
5003 if (bit (this_instr
, 15))
5007 unsigned long rn_val
5008 = get_frame_register_unsigned (frame
,
5009 bits (this_instr
, 16, 19));
5011 if (bit (this_instr
, 23))
5014 unsigned long reglist
= bits (this_instr
, 0, 14);
5015 offset
= bitcount (reglist
) * 4;
5016 if (bit (this_instr
, 24)) /* pre */
5019 else if (bit (this_instr
, 24))
5023 (CORE_ADDR
) read_memory_unsigned_integer ((CORE_ADDR
)
5030 case 0xb: /* branch & link */
5031 case 0xa: /* branch */
5033 nextpc
= BranchDest (pc
, this_instr
);
5039 case 0xe: /* coproc ops */
5043 struct gdbarch_tdep
*tdep
;
5044 tdep
= gdbarch_tdep (gdbarch
);
5046 if (tdep
->syscall_next_pc
!= NULL
)
5047 nextpc
= tdep
->syscall_next_pc (frame
);
5053 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
5061 /* Determine next PC after current instruction executes. Will call either
5062 arm_get_next_pc_raw or thumb_get_next_pc_raw. Error out if infinite
5063 loop is detected. */
5066 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
5070 if (arm_frame_is_thumb (frame
))
5071 nextpc
= thumb_get_next_pc_raw (frame
, pc
);
5073 nextpc
= arm_get_next_pc_raw (frame
, pc
);
5078 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
5079 of the appropriate mode (as encoded in the PC value), even if this
5080 differs from what would be expected according to the symbol tables. */
5083 arm_insert_single_step_breakpoint (struct gdbarch
*gdbarch
,
5084 struct address_space
*aspace
,
5087 struct cleanup
*old_chain
5088 = make_cleanup_restore_integer (&arm_override_mode
);
5090 arm_override_mode
= IS_THUMB_ADDR (pc
);
5091 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
5093 insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
5095 do_cleanups (old_chain
);
5098 /* Checks for an atomic sequence of instructions beginning with a LDREX{,B,H,D}
5099 instruction and ending with a STREX{,B,H,D} instruction. If such a sequence
5100 is found, attempt to step through it. A breakpoint is placed at the end of
5104 thumb_deal_with_atomic_sequence_raw (struct frame_info
*frame
)
5106 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5107 struct address_space
*aspace
= get_frame_address_space (frame
);
5108 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5109 CORE_ADDR pc
= get_frame_pc (frame
);
5110 CORE_ADDR breaks
[2] = {-1, -1};
5112 unsigned short insn1
, insn2
;
5115 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
5116 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
5117 ULONGEST status
, itstate
;
5119 /* We currently do not support atomic sequences within an IT block. */
5120 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
5121 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
5125 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. */
5126 insn1
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5128 if (thumb_insn_size (insn1
) != 4)
5131 insn2
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5133 if (!((insn1
& 0xfff0) == 0xe850
5134 || ((insn1
& 0xfff0) == 0xe8d0 && (insn2
& 0x00c0) == 0x0040)))
5137 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5139 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
5141 insn1
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5144 if (thumb_insn_size (insn1
) != 4)
5146 /* Assume that there is at most one conditional branch in the
5147 atomic sequence. If a conditional branch is found, put a
5148 breakpoint in its destination address. */
5149 if ((insn1
& 0xf000) == 0xd000 && bits (insn1
, 8, 11) != 0x0f)
5151 if (last_breakpoint
> 0)
5152 return 0; /* More than one conditional branch found,
5153 fallback to the standard code. */
5155 breaks
[1] = loc
+ 2 + (sbits (insn1
, 0, 7) << 1);
5159 /* We do not support atomic sequences that use any *other*
5160 instructions but conditional branches to change the PC.
5161 Fall back to standard code to avoid losing control of
5163 else if (thumb_instruction_changes_pc (insn1
))
5168 insn2
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5171 /* Assume that there is at most one conditional branch in the
5172 atomic sequence. If a conditional branch is found, put a
5173 breakpoint in its destination address. */
5174 if ((insn1
& 0xf800) == 0xf000
5175 && (insn2
& 0xd000) == 0x8000
5176 && (insn1
& 0x0380) != 0x0380)
5178 int sign
, j1
, j2
, imm1
, imm2
;
5179 unsigned int offset
;
5181 sign
= sbits (insn1
, 10, 10);
5182 imm1
= bits (insn1
, 0, 5);
5183 imm2
= bits (insn2
, 0, 10);
5184 j1
= bit (insn2
, 13);
5185 j2
= bit (insn2
, 11);
5187 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
5188 offset
+= (imm1
<< 12) + (imm2
<< 1);
5190 if (last_breakpoint
> 0)
5191 return 0; /* More than one conditional branch found,
5192 fallback to the standard code. */
5194 breaks
[1] = loc
+ offset
;
5198 /* We do not support atomic sequences that use any *other*
5199 instructions but conditional branches to change the PC.
5200 Fall back to standard code to avoid losing control of
5202 else if (thumb2_instruction_changes_pc (insn1
, insn2
))
5205 /* If we find a strex{,b,h,d}, we're done. */
5206 if ((insn1
& 0xfff0) == 0xe840
5207 || ((insn1
& 0xfff0) == 0xe8c0 && (insn2
& 0x00c0) == 0x0040))
5212 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5213 if (insn_count
== atomic_sequence_length
)
5216 /* Insert a breakpoint right after the end of the atomic sequence. */
5219 /* Check for duplicated breakpoints. Check also for a breakpoint
5220 placed (branch instruction's destination) anywhere in sequence. */
5222 && (breaks
[1] == breaks
[0]
5223 || (breaks
[1] >= pc
&& breaks
[1] < loc
)))
5224 last_breakpoint
= 0;
5226 /* Effectively inserts the breakpoints. */
5227 for (index
= 0; index
<= last_breakpoint
; index
++)
5228 arm_insert_single_step_breakpoint (gdbarch
, aspace
,
5229 MAKE_THUMB_ADDR (breaks
[index
]));
5235 arm_deal_with_atomic_sequence_raw (struct frame_info
*frame
)
5237 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5238 struct address_space
*aspace
= get_frame_address_space (frame
);
5239 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5240 CORE_ADDR pc
= get_frame_pc (frame
);
5241 CORE_ADDR breaks
[2] = {-1, -1};
5246 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
5247 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
5249 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction.
5250 Note that we do not currently support conditionally executed atomic
5252 insn
= read_memory_unsigned_integer (loc
, 4, byte_order_for_code
);
5254 if ((insn
& 0xff9000f0) != 0xe1900090)
5257 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5259 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
5261 insn
= read_memory_unsigned_integer (loc
, 4, byte_order_for_code
);
5264 /* Assume that there is at most one conditional branch in the atomic
5265 sequence. If a conditional branch is found, put a breakpoint in
5266 its destination address. */
5267 if (bits (insn
, 24, 27) == 0xa)
5269 if (last_breakpoint
> 0)
5270 return 0; /* More than one conditional branch found, fallback
5271 to the standard single-step code. */
5273 breaks
[1] = BranchDest (loc
- 4, insn
);
5277 /* We do not support atomic sequences that use any *other* instructions
5278 but conditional branches to change the PC. Fall back to standard
5279 code to avoid losing control of execution. */
5280 else if (arm_instruction_changes_pc (insn
))
5283 /* If we find a strex{,b,h,d}, we're done. */
5284 if ((insn
& 0xff9000f0) == 0xe1800090)
5288 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5289 if (insn_count
== atomic_sequence_length
)
5292 /* Insert a breakpoint right after the end of the atomic sequence. */
5295 /* Check for duplicated breakpoints. Check also for a breakpoint
5296 placed (branch instruction's destination) anywhere in sequence. */
5298 && (breaks
[1] == breaks
[0]
5299 || (breaks
[1] >= pc
&& breaks
[1] < loc
)))
5300 last_breakpoint
= 0;
5302 /* Effectively inserts the breakpoints. */
5303 for (index
= 0; index
<= last_breakpoint
; index
++)
5304 arm_insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
5310 arm_deal_with_atomic_sequence (struct frame_info
*frame
)
5312 if (arm_frame_is_thumb (frame
))
5313 return thumb_deal_with_atomic_sequence_raw (frame
);
5315 return arm_deal_with_atomic_sequence_raw (frame
);
5318 /* single_step() is called just before we want to resume the inferior,
5319 if we want to single-step it but there is no hardware or kernel
5320 single-step support. We find the target of the coming instruction
5321 and breakpoint it. */
5324 arm_software_single_step (struct frame_info
*frame
)
5326 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5327 struct address_space
*aspace
= get_frame_address_space (frame
);
5330 if (arm_deal_with_atomic_sequence (frame
))
5333 next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
5334 arm_insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
5339 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
5340 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
5341 NULL if an error occurs. BUF is freed. */
5344 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
5345 int old_len
, int new_len
)
5348 int bytes_to_read
= new_len
- old_len
;
5350 new_buf
= xmalloc (new_len
);
5351 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
5353 if (target_read_memory (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
5361 /* An IT block is at most the 2-byte IT instruction followed by
5362 four 4-byte instructions. The furthest back we must search to
5363 find an IT block that affects the current instruction is thus
5364 2 + 3 * 4 == 14 bytes. */
5365 #define MAX_IT_BLOCK_PREFIX 14
5367 /* Use a quick scan if there are more than this many bytes of
5369 #define IT_SCAN_THRESHOLD 32
5371 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
5372 A breakpoint in an IT block may not be hit, depending on the
5375 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
5379 CORE_ADDR boundary
, func_start
;
5381 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
5382 int i
, any
, last_it
, last_it_count
;
5384 /* If we are using BKPT breakpoints, none of this is necessary. */
5385 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
5388 /* ARM mode does not have this problem. */
5389 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
5392 /* We are setting a breakpoint in Thumb code that could potentially
5393 contain an IT block. The first step is to find how much Thumb
5394 code there is; we do not need to read outside of known Thumb
5396 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
5398 /* Thumb-2 code must have mapping symbols to have a chance. */
5401 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
5403 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
5404 && func_start
> boundary
)
5405 boundary
= func_start
;
5407 /* Search for a candidate IT instruction. We have to do some fancy
5408 footwork to distinguish a real IT instruction from the second
5409 half of a 32-bit instruction, but there is no need for that if
5410 there's no candidate. */
5411 buf_len
= min (bpaddr
- boundary
, MAX_IT_BLOCK_PREFIX
);
5413 /* No room for an IT instruction. */
5416 buf
= xmalloc (buf_len
);
5417 if (target_read_memory (bpaddr
- buf_len
, buf
, buf_len
) != 0)
5420 for (i
= 0; i
< buf_len
; i
+= 2)
5422 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5423 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
5435 /* OK, the code bytes before this instruction contain at least one
5436 halfword which resembles an IT instruction. We know that it's
5437 Thumb code, but there are still two possibilities. Either the
5438 halfword really is an IT instruction, or it is the second half of
5439 a 32-bit Thumb instruction. The only way we can tell is to
5440 scan forwards from a known instruction boundary. */
5441 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
5445 /* There's a lot of code before this instruction. Start with an
5446 optimistic search; it's easy to recognize halfwords that can
5447 not be the start of a 32-bit instruction, and use that to
5448 lock on to the instruction boundaries. */
5449 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
5452 buf_len
= IT_SCAN_THRESHOLD
;
5455 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
5457 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5458 if (thumb_insn_size (inst1
) == 2)
5465 /* At this point, if DEFINITE, BUF[I] is the first place we
5466 are sure that we know the instruction boundaries, and it is far
5467 enough from BPADDR that we could not miss an IT instruction
5468 affecting BPADDR. If ! DEFINITE, give up - start from a
5472 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
,
5476 buf_len
= bpaddr
- boundary
;
5482 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
5485 buf_len
= bpaddr
- boundary
;
5489 /* Scan forwards. Find the last IT instruction before BPADDR. */
5494 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5496 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
5501 else if (inst1
& 0x0002)
5503 else if (inst1
& 0x0004)
5508 i
+= thumb_insn_size (inst1
);
5514 /* There wasn't really an IT instruction after all. */
5517 if (last_it_count
< 1)
5518 /* It was too far away. */
5521 /* This really is a trouble spot. Move the breakpoint to the IT
5523 return bpaddr
- buf_len
+ last_it
;
5526 /* ARM displaced stepping support.
5528 Generally ARM displaced stepping works as follows:
5530 1. When an instruction is to be single-stepped, it is first decoded by
5531 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
5532 Depending on the type of instruction, it is then copied to a scratch
5533 location, possibly in a modified form. The copy_* set of functions
5534 performs such modification, as necessary. A breakpoint is placed after
5535 the modified instruction in the scratch space to return control to GDB.
5536 Note in particular that instructions which modify the PC will no longer
5537 do so after modification.
5539 2. The instruction is single-stepped, by setting the PC to the scratch
5540 location address, and resuming. Control returns to GDB when the
5543 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
5544 function used for the current instruction. This function's job is to
5545 put the CPU/memory state back to what it would have been if the
5546 instruction had been executed unmodified in its original location. */
5548 /* NOP instruction (mov r0, r0). */
5549 #define ARM_NOP 0xe1a00000
5550 #define THUMB_NOP 0x4600
5552 /* Helper for register reads for displaced stepping. In particular, this
5553 returns the PC as it would be seen by the instruction at its original
5557 displaced_read_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5561 CORE_ADDR from
= dsc
->insn_addr
;
5563 if (regno
== ARM_PC_REGNUM
)
5565 /* Compute pipeline offset:
5566 - When executing an ARM instruction, PC reads as the address of the
5567 current instruction plus 8.
5568 - When executing a Thumb instruction, PC reads as the address of the
5569 current instruction plus 4. */
5576 if (debug_displaced
)
5577 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
5578 (unsigned long) from
);
5579 return (ULONGEST
) from
;
5583 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
5584 if (debug_displaced
)
5585 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
5586 regno
, (unsigned long) ret
);
5592 displaced_in_arm_mode (struct regcache
*regs
)
5595 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
5597 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
5599 return (ps
& t_bit
) == 0;
5602 /* Write to the PC as from a branch instruction. */
5605 branch_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5609 /* Note: If bits 0/1 are set, this branch would be unpredictable for
5610 architecture versions < 6. */
5611 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
5612 val
& ~(ULONGEST
) 0x3);
5614 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
5615 val
& ~(ULONGEST
) 0x1);
5618 /* Write to the PC as from a branch-exchange instruction. */
5621 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
5624 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
5626 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
5630 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
5631 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
5633 else if ((val
& 2) == 0)
5635 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
5636 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
5640 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
5641 mode, align dest to 4 bytes). */
5642 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
5643 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
5644 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
5648 /* Write to the PC as if from a load instruction. */
5651 load_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5654 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
5655 bx_write_pc (regs
, val
);
5657 branch_write_pc (regs
, dsc
, val
);
5660 /* Write to the PC as if from an ALU instruction. */
5663 alu_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5666 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && !dsc
->is_thumb
)
5667 bx_write_pc (regs
, val
);
5669 branch_write_pc (regs
, dsc
, val
);
5672 /* Helper for writing to registers for displaced stepping. Writing to the PC
5673 has a varying effects depending on the instruction which does the write:
5674 this is controlled by the WRITE_PC argument. */
5677 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5678 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
5680 if (regno
== ARM_PC_REGNUM
)
5682 if (debug_displaced
)
5683 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
5684 (unsigned long) val
);
5687 case BRANCH_WRITE_PC
:
5688 branch_write_pc (regs
, dsc
, val
);
5692 bx_write_pc (regs
, val
);
5696 load_write_pc (regs
, dsc
, val
);
5700 alu_write_pc (regs
, dsc
, val
);
5703 case CANNOT_WRITE_PC
:
5704 warning (_("Instruction wrote to PC in an unexpected way when "
5705 "single-stepping"));
5709 internal_error (__FILE__
, __LINE__
,
5710 _("Invalid argument to displaced_write_reg"));
5713 dsc
->wrote_to_pc
= 1;
5717 if (debug_displaced
)
5718 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
5719 regno
, (unsigned long) val
);
5720 regcache_cooked_write_unsigned (regs
, regno
, val
);
5724 /* This function is used to concisely determine if an instruction INSN
5725 references PC. Register fields of interest in INSN should have the
5726 corresponding fields of BITMASK set to 0b1111. The function
5727 returns return 1 if any of these fields in INSN reference the PC
5728 (also 0b1111, r15), else it returns 0. */
5731 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
5733 uint32_t lowbit
= 1;
5735 while (bitmask
!= 0)
5739 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
5745 mask
= lowbit
* 0xf;
5747 if ((insn
& mask
) == mask
)
5756 /* The simplest copy function. Many instructions have the same effect no
5757 matter what address they are executed at: in those cases, use this. */
5760 arm_copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
5761 const char *iname
, struct displaced_step_closure
*dsc
)
5763 if (debug_displaced
)
5764 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
5765 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
5768 dsc
->modinsn
[0] = insn
;
5774 thumb_copy_unmodified_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
5775 uint16_t insn2
, const char *iname
,
5776 struct displaced_step_closure
*dsc
)
5778 if (debug_displaced
)
5779 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x %.4x, "
5780 "opcode/class '%s' unmodified\n", insn1
, insn2
,
5783 dsc
->modinsn
[0] = insn1
;
5784 dsc
->modinsn
[1] = insn2
;
5790 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
5793 thumb_copy_unmodified_16bit (struct gdbarch
*gdbarch
, unsigned int insn
,
5795 struct displaced_step_closure
*dsc
)
5797 if (debug_displaced
)
5798 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x, "
5799 "opcode/class '%s' unmodified\n", insn
,
5802 dsc
->modinsn
[0] = insn
;
5807 /* Preload instructions with immediate offset. */
5810 cleanup_preload (struct gdbarch
*gdbarch
,
5811 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5813 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5814 if (!dsc
->u
.preload
.immed
)
5815 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5819 install_preload (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5820 struct displaced_step_closure
*dsc
, unsigned int rn
)
5823 /* Preload instructions:
5825 {pli/pld} [rn, #+/-imm]
5827 {pli/pld} [r0, #+/-imm]. */
5829 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5830 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5831 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5832 dsc
->u
.preload
.immed
= 1;
5834 dsc
->cleanup
= &cleanup_preload
;
5838 arm_copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5839 struct displaced_step_closure
*dsc
)
5841 unsigned int rn
= bits (insn
, 16, 19);
5843 if (!insn_references_pc (insn
, 0x000f0000ul
))
5844 return arm_copy_unmodified (gdbarch
, insn
, "preload", dsc
);
5846 if (debug_displaced
)
5847 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
5848 (unsigned long) insn
);
5850 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
5852 install_preload (gdbarch
, regs
, dsc
, rn
);
5858 thumb2_copy_preload (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
5859 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5861 unsigned int rn
= bits (insn1
, 0, 3);
5862 unsigned int u_bit
= bit (insn1
, 7);
5863 int imm12
= bits (insn2
, 0, 11);
5866 if (rn
!= ARM_PC_REGNUM
)
5867 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "preload", dsc
);
5869 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
5870 PLD (literal) Encoding T1. */
5871 if (debug_displaced
)
5872 fprintf_unfiltered (gdb_stdlog
,
5873 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
5874 (unsigned int) dsc
->insn_addr
, u_bit
? '+' : '-',
5880 /* Rewrite instruction {pli/pld} PC imm12 into:
5881 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
5885 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
5887 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5888 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5890 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
5892 displaced_write_reg (regs
, dsc
, 0, pc_val
, CANNOT_WRITE_PC
);
5893 displaced_write_reg (regs
, dsc
, 1, imm12
, CANNOT_WRITE_PC
);
5894 dsc
->u
.preload
.immed
= 0;
5896 /* {pli/pld} [r0, r1] */
5897 dsc
->modinsn
[0] = insn1
& 0xfff0;
5898 dsc
->modinsn
[1] = 0xf001;
5901 dsc
->cleanup
= &cleanup_preload
;
5905 /* Preload instructions with register offset. */
5908 install_preload_reg(struct gdbarch
*gdbarch
, struct regcache
*regs
,
5909 struct displaced_step_closure
*dsc
, unsigned int rn
,
5912 ULONGEST rn_val
, rm_val
;
5914 /* Preload register-offset instructions:
5916 {pli/pld} [rn, rm {, shift}]
5918 {pli/pld} [r0, r1 {, shift}]. */
5920 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5921 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5922 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5923 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5924 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5925 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
5926 dsc
->u
.preload
.immed
= 0;
5928 dsc
->cleanup
= &cleanup_preload
;
5932 arm_copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5933 struct regcache
*regs
,
5934 struct displaced_step_closure
*dsc
)
5936 unsigned int rn
= bits (insn
, 16, 19);
5937 unsigned int rm
= bits (insn
, 0, 3);
5940 if (!insn_references_pc (insn
, 0x000f000ful
))
5941 return arm_copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
5943 if (debug_displaced
)
5944 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
5945 (unsigned long) insn
);
5947 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
5949 install_preload_reg (gdbarch
, regs
, dsc
, rn
, rm
);
5953 /* Copy/cleanup coprocessor load and store instructions. */
5956 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
5957 struct regcache
*regs
,
5958 struct displaced_step_closure
*dsc
)
5960 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 0);
5962 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5964 if (dsc
->u
.ldst
.writeback
)
5965 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
5969 install_copro_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5970 struct displaced_step_closure
*dsc
,
5971 int writeback
, unsigned int rn
)
5975 /* Coprocessor load/store instructions:
5977 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
5979 {stc/stc2} [r0, #+/-imm].
5981 ldc/ldc2 are handled identically. */
5983 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5984 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5985 /* PC should be 4-byte aligned. */
5986 rn_val
= rn_val
& 0xfffffffc;
5987 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5989 dsc
->u
.ldst
.writeback
= writeback
;
5990 dsc
->u
.ldst
.rn
= rn
;
5992 dsc
->cleanup
= &cleanup_copro_load_store
;
5996 arm_copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
5997 struct regcache
*regs
,
5998 struct displaced_step_closure
*dsc
)
6000 unsigned int rn
= bits (insn
, 16, 19);
6002 if (!insn_references_pc (insn
, 0x000f0000ul
))
6003 return arm_copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
6005 if (debug_displaced
)
6006 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
6007 "load/store insn %.8lx\n", (unsigned long) insn
);
6009 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
6011 install_copro_load_store (gdbarch
, regs
, dsc
, bit (insn
, 25), rn
);
6017 thumb2_copy_copro_load_store (struct gdbarch
*gdbarch
, uint16_t insn1
,
6018 uint16_t insn2
, struct regcache
*regs
,
6019 struct displaced_step_closure
*dsc
)
6021 unsigned int rn
= bits (insn1
, 0, 3);
6023 if (rn
!= ARM_PC_REGNUM
)
6024 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6025 "copro load/store", dsc
);
6027 if (debug_displaced
)
6028 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
6029 "load/store insn %.4x%.4x\n", insn1
, insn2
);
6031 dsc
->modinsn
[0] = insn1
& 0xfff0;
6032 dsc
->modinsn
[1] = insn2
;
6035 /* This function is called for copying instruction LDC/LDC2/VLDR, which
6036 doesn't support writeback, so pass 0. */
6037 install_copro_load_store (gdbarch
, regs
, dsc
, 0, rn
);
6042 /* Clean up branch instructions (actually perform the branch, by setting
6046 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6047 struct displaced_step_closure
*dsc
)
6049 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6050 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
6051 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
6052 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
6057 if (dsc
->u
.branch
.link
)
6059 /* The value of LR should be the next insn of current one. In order
6060 not to confuse logic hanlding later insn `bx lr', if current insn mode
6061 is Thumb, the bit 0 of LR value should be set to 1. */
6062 ULONGEST next_insn_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
6065 next_insn_addr
|= 0x1;
6067 displaced_write_reg (regs
, dsc
, ARM_LR_REGNUM
, next_insn_addr
,
6071 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, dsc
->u
.branch
.dest
, write_pc
);
6074 /* Copy B/BL/BLX instructions with immediate destinations. */
6077 install_b_bl_blx (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6078 struct displaced_step_closure
*dsc
,
6079 unsigned int cond
, int exchange
, int link
, long offset
)
6081 /* Implement "BL<cond> <label>" as:
6083 Preparation: cond <- instruction condition
6084 Insn: mov r0, r0 (nop)
6085 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
6087 B<cond> similar, but don't set r14 in cleanup. */
6089 dsc
->u
.branch
.cond
= cond
;
6090 dsc
->u
.branch
.link
= link
;
6091 dsc
->u
.branch
.exchange
= exchange
;
6093 dsc
->u
.branch
.dest
= dsc
->insn_addr
;
6094 if (link
&& exchange
)
6095 /* For BLX, offset is computed from the Align (PC, 4). */
6096 dsc
->u
.branch
.dest
= dsc
->u
.branch
.dest
& 0xfffffffc;
6099 dsc
->u
.branch
.dest
+= 4 + offset
;
6101 dsc
->u
.branch
.dest
+= 8 + offset
;
6103 dsc
->cleanup
= &cleanup_branch
;
6106 arm_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
6107 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6109 unsigned int cond
= bits (insn
, 28, 31);
6110 int exchange
= (cond
== 0xf);
6111 int link
= exchange
|| bit (insn
, 24);
6114 if (debug_displaced
)
6115 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
6116 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
6117 (unsigned long) insn
);
6119 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
6120 then arrange the switch into Thumb mode. */
6121 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
6123 offset
= bits (insn
, 0, 23) << 2;
6125 if (bit (offset
, 25))
6126 offset
= offset
| ~0x3ffffff;
6128 dsc
->modinsn
[0] = ARM_NOP
;
6130 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
6135 thumb2_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint16_t insn1
,
6136 uint16_t insn2
, struct regcache
*regs
,
6137 struct displaced_step_closure
*dsc
)
6139 int link
= bit (insn2
, 14);
6140 int exchange
= link
&& !bit (insn2
, 12);
6143 int j1
= bit (insn2
, 13);
6144 int j2
= bit (insn2
, 11);
6145 int s
= sbits (insn1
, 10, 10);
6146 int i1
= !(j1
^ bit (insn1
, 10));
6147 int i2
= !(j2
^ bit (insn1
, 10));
6149 if (!link
&& !exchange
) /* B */
6151 offset
= (bits (insn2
, 0, 10) << 1);
6152 if (bit (insn2
, 12)) /* Encoding T4 */
6154 offset
|= (bits (insn1
, 0, 9) << 12)
6160 else /* Encoding T3 */
6162 offset
|= (bits (insn1
, 0, 5) << 12)
6166 cond
= bits (insn1
, 6, 9);
6171 offset
= (bits (insn1
, 0, 9) << 12);
6172 offset
|= ((i2
<< 22) | (i1
<< 23) | (s
<< 24));
6173 offset
|= exchange
?
6174 (bits (insn2
, 1, 10) << 2) : (bits (insn2
, 0, 10) << 1);
6177 if (debug_displaced
)
6178 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s insn "
6179 "%.4x %.4x with offset %.8lx\n",
6180 link
? (exchange
) ? "blx" : "bl" : "b",
6181 insn1
, insn2
, offset
);
6183 dsc
->modinsn
[0] = THUMB_NOP
;
6185 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
6189 /* Copy B Thumb instructions. */
6191 thumb_copy_b (struct gdbarch
*gdbarch
, unsigned short insn
,
6192 struct displaced_step_closure
*dsc
)
6194 unsigned int cond
= 0;
6196 unsigned short bit_12_15
= bits (insn
, 12, 15);
6197 CORE_ADDR from
= dsc
->insn_addr
;
6199 if (bit_12_15
== 0xd)
6201 /* offset = SignExtend (imm8:0, 32) */
6202 offset
= sbits ((insn
<< 1), 0, 8);
6203 cond
= bits (insn
, 8, 11);
6205 else if (bit_12_15
== 0xe) /* Encoding T2 */
6207 offset
= sbits ((insn
<< 1), 0, 11);
6211 if (debug_displaced
)
6212 fprintf_unfiltered (gdb_stdlog
,
6213 "displaced: copying b immediate insn %.4x "
6214 "with offset %d\n", insn
, offset
);
6216 dsc
->u
.branch
.cond
= cond
;
6217 dsc
->u
.branch
.link
= 0;
6218 dsc
->u
.branch
.exchange
= 0;
6219 dsc
->u
.branch
.dest
= from
+ 4 + offset
;
6221 dsc
->modinsn
[0] = THUMB_NOP
;
6223 dsc
->cleanup
= &cleanup_branch
;
6228 /* Copy BX/BLX with register-specified destinations. */
6231 install_bx_blx_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6232 struct displaced_step_closure
*dsc
, int link
,
6233 unsigned int cond
, unsigned int rm
)
6235 /* Implement {BX,BLX}<cond> <reg>" as:
6237 Preparation: cond <- instruction condition
6238 Insn: mov r0, r0 (nop)
6239 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
6241 Don't set r14 in cleanup for BX. */
6243 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, dsc
, rm
);
6245 dsc
->u
.branch
.cond
= cond
;
6246 dsc
->u
.branch
.link
= link
;
6248 dsc
->u
.branch
.exchange
= 1;
6250 dsc
->cleanup
= &cleanup_branch
;
6254 arm_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
6255 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6257 unsigned int cond
= bits (insn
, 28, 31);
6260 int link
= bit (insn
, 5);
6261 unsigned int rm
= bits (insn
, 0, 3);
6263 if (debug_displaced
)
6264 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx",
6265 (unsigned long) insn
);
6267 dsc
->modinsn
[0] = ARM_NOP
;
6269 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, cond
, rm
);
6274 thumb_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
6275 struct regcache
*regs
,
6276 struct displaced_step_closure
*dsc
)
6278 int link
= bit (insn
, 7);
6279 unsigned int rm
= bits (insn
, 3, 6);
6281 if (debug_displaced
)
6282 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x",
6283 (unsigned short) insn
);
6285 dsc
->modinsn
[0] = THUMB_NOP
;
6287 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, INST_AL
, rm
);
6293 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
6296 cleanup_alu_imm (struct gdbarch
*gdbarch
,
6297 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6299 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
6300 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6301 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6302 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6306 arm_copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
6307 struct displaced_step_closure
*dsc
)
6309 unsigned int rn
= bits (insn
, 16, 19);
6310 unsigned int rd
= bits (insn
, 12, 15);
6311 unsigned int op
= bits (insn
, 21, 24);
6312 int is_mov
= (op
== 0xd);
6313 ULONGEST rd_val
, rn_val
;
6315 if (!insn_references_pc (insn
, 0x000ff000ul
))
6316 return arm_copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
6318 if (debug_displaced
)
6319 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
6320 "%.8lx\n", is_mov
? "move" : "ALU",
6321 (unsigned long) insn
);
6323 /* Instruction is of form:
6325 <op><cond> rd, [rn,] #imm
6329 Preparation: tmp1, tmp2 <- r0, r1;
6331 Insn: <op><cond> r0, r1, #imm
6332 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6335 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6336 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6337 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6338 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6339 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6340 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6344 dsc
->modinsn
[0] = insn
& 0xfff00fff;
6346 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
6348 dsc
->cleanup
= &cleanup_alu_imm
;
6354 thumb2_copy_alu_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
6355 uint16_t insn2
, struct regcache
*regs
,
6356 struct displaced_step_closure
*dsc
)
6358 unsigned int op
= bits (insn1
, 5, 8);
6359 unsigned int rn
, rm
, rd
;
6360 ULONGEST rd_val
, rn_val
;
6362 rn
= bits (insn1
, 0, 3); /* Rn */
6363 rm
= bits (insn2
, 0, 3); /* Rm */
6364 rd
= bits (insn2
, 8, 11); /* Rd */
6366 /* This routine is only called for instruction MOV. */
6367 gdb_assert (op
== 0x2 && rn
== 0xf);
6369 if (rm
!= ARM_PC_REGNUM
&& rd
!= ARM_PC_REGNUM
)
6370 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ALU imm", dsc
);
6372 if (debug_displaced
)
6373 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x%.4x\n",
6374 "ALU", insn1
, insn2
);
6376 /* Instruction is of form:
6378 <op><cond> rd, [rn,] #imm
6382 Preparation: tmp1, tmp2 <- r0, r1;
6384 Insn: <op><cond> r0, r1, #imm
6385 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6388 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6389 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6390 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6391 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6392 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6393 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6396 dsc
->modinsn
[0] = insn1
;
6397 dsc
->modinsn
[1] = ((insn2
& 0xf0f0) | 0x1);
6400 dsc
->cleanup
= &cleanup_alu_imm
;
6405 /* Copy/cleanup arithmetic/logic insns with register RHS. */
6408 cleanup_alu_reg (struct gdbarch
*gdbarch
,
6409 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6414 rd_val
= displaced_read_reg (regs
, dsc
, 0);
6416 for (i
= 0; i
< 3; i
++)
6417 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
6419 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6423 install_alu_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6424 struct displaced_step_closure
*dsc
,
6425 unsigned int rd
, unsigned int rn
, unsigned int rm
)
6427 ULONGEST rd_val
, rn_val
, rm_val
;
6429 /* Instruction is of form:
6431 <op><cond> rd, [rn,] rm [, <shift>]
6435 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
6436 r0, r1, r2 <- rd, rn, rm
6437 Insn: <op><cond> r0, r1, r2 [, <shift>]
6438 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
6441 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6442 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6443 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6444 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6445 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6446 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6447 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6448 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6449 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
6452 dsc
->cleanup
= &cleanup_alu_reg
;
6456 arm_copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
6457 struct displaced_step_closure
*dsc
)
6459 unsigned int op
= bits (insn
, 21, 24);
6460 int is_mov
= (op
== 0xd);
6462 if (!insn_references_pc (insn
, 0x000ff00ful
))
6463 return arm_copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
6465 if (debug_displaced
)
6466 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
6467 is_mov
? "move" : "ALU", (unsigned long) insn
);
6470 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
6472 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
6474 install_alu_reg (gdbarch
, regs
, dsc
, bits (insn
, 12, 15), bits (insn
, 16, 19),
6480 thumb_copy_alu_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
6481 struct regcache
*regs
,
6482 struct displaced_step_closure
*dsc
)
6484 unsigned rn
, rm
, rd
;
6486 rd
= bits (insn
, 3, 6);
6487 rn
= (bit (insn
, 7) << 3) | bits (insn
, 0, 2);
6490 if (rd
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
6491 return thumb_copy_unmodified_16bit (gdbarch
, insn
, "ALU reg", dsc
);
6493 if (debug_displaced
)
6494 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x\n",
6495 "ALU", (unsigned short) insn
);
6497 dsc
->modinsn
[0] = ((insn
& 0xff00) | 0x08);
6499 install_alu_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
);
6504 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
6507 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
6508 struct regcache
*regs
,
6509 struct displaced_step_closure
*dsc
)
6511 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
6514 for (i
= 0; i
< 4; i
++)
6515 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
6517 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6521 install_alu_shifted_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6522 struct displaced_step_closure
*dsc
,
6523 unsigned int rd
, unsigned int rn
, unsigned int rm
,
6527 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
6529 /* Instruction is of form:
6531 <op><cond> rd, [rn,] rm, <shift> rs
6535 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
6536 r0, r1, r2, r3 <- rd, rn, rm, rs
6537 Insn: <op><cond> r0, r1, r2, <shift> r3
6539 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
6543 for (i
= 0; i
< 4; i
++)
6544 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6546 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6547 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6548 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6549 rs_val
= displaced_read_reg (regs
, dsc
, rs
);
6550 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6551 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6552 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
6553 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
6555 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
6559 arm_copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
6560 struct regcache
*regs
,
6561 struct displaced_step_closure
*dsc
)
6563 unsigned int op
= bits (insn
, 21, 24);
6564 int is_mov
= (op
== 0xd);
6565 unsigned int rd
, rn
, rm
, rs
;
6567 if (!insn_references_pc (insn
, 0x000fff0ful
))
6568 return arm_copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
6570 if (debug_displaced
)
6571 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
6572 "%.8lx\n", is_mov
? "move" : "ALU",
6573 (unsigned long) insn
);
6575 rn
= bits (insn
, 16, 19);
6576 rm
= bits (insn
, 0, 3);
6577 rs
= bits (insn
, 8, 11);
6578 rd
= bits (insn
, 12, 15);
6581 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
6583 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
6585 install_alu_shifted_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
, rs
);
6590 /* Clean up load instructions. */
6593 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6594 struct displaced_step_closure
*dsc
)
6596 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
6598 rt_val
= displaced_read_reg (regs
, dsc
, 0);
6599 if (dsc
->u
.ldst
.xfersize
== 8)
6600 rt_val2
= displaced_read_reg (regs
, dsc
, 1);
6601 rn_val
= displaced_read_reg (regs
, dsc
, 2);
6603 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6604 if (dsc
->u
.ldst
.xfersize
> 4)
6605 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6606 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
6607 if (!dsc
->u
.ldst
.immed
)
6608 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
6610 /* Handle register writeback. */
6611 if (dsc
->u
.ldst
.writeback
)
6612 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
6613 /* Put result in right place. */
6614 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
6615 if (dsc
->u
.ldst
.xfersize
== 8)
6616 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
6619 /* Clean up store instructions. */
6622 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6623 struct displaced_step_closure
*dsc
)
6625 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 2);
6627 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6628 if (dsc
->u
.ldst
.xfersize
> 4)
6629 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6630 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
6631 if (!dsc
->u
.ldst
.immed
)
6632 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
6633 if (!dsc
->u
.ldst
.restore_r4
)
6634 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
6637 if (dsc
->u
.ldst
.writeback
)
6638 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
6641 /* Copy "extra" load/store instructions. These are halfword/doubleword
6642 transfers, which have a different encoding to byte/word transfers. */
6645 arm_copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unpriveleged
,
6646 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6648 unsigned int op1
= bits (insn
, 20, 24);
6649 unsigned int op2
= bits (insn
, 5, 6);
6650 unsigned int rt
= bits (insn
, 12, 15);
6651 unsigned int rn
= bits (insn
, 16, 19);
6652 unsigned int rm
= bits (insn
, 0, 3);
6653 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
6654 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
6655 int immed
= (op1
& 0x4) != 0;
6657 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
6659 if (!insn_references_pc (insn
, 0x000ff00ful
))
6660 return arm_copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
6662 if (debug_displaced
)
6663 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
6664 "insn %.8lx\n", unpriveleged
? "unpriveleged " : "",
6665 (unsigned long) insn
);
6667 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
6670 internal_error (__FILE__
, __LINE__
,
6671 _("copy_extra_ld_st: instruction decode error"));
6673 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6674 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6675 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6677 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6679 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
6680 if (bytesize
[opcode
] == 8)
6681 rt_val2
= displaced_read_reg (regs
, dsc
, rt
+ 1);
6682 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6684 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6686 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
6687 if (bytesize
[opcode
] == 8)
6688 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
6689 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
6691 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
6694 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
6695 dsc
->u
.ldst
.rn
= rn
;
6696 dsc
->u
.ldst
.immed
= immed
;
6697 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
6698 dsc
->u
.ldst
.restore_r4
= 0;
6701 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
6703 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
6704 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
6706 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
6708 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
6709 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
6711 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
6716 /* Copy byte/half word/word loads and stores. */
6719 install_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6720 struct displaced_step_closure
*dsc
, int load
,
6721 int immed
, int writeback
, int size
, int usermode
,
6722 int rt
, int rm
, int rn
)
6724 ULONGEST rt_val
, rn_val
, rm_val
= 0;
6726 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6727 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6729 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6731 dsc
->tmp
[4] = displaced_read_reg (regs
, dsc
, 4);
6733 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
6734 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6736 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6738 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
6739 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
6741 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
6743 dsc
->u
.ldst
.xfersize
= size
;
6744 dsc
->u
.ldst
.rn
= rn
;
6745 dsc
->u
.ldst
.immed
= immed
;
6746 dsc
->u
.ldst
.writeback
= writeback
;
6748 /* To write PC we can do:
6750 Before this sequence of instructions:
6751 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
6752 r2 is the Rn value got from dispalced_read_reg.
6754 Insn1: push {pc} Write address of STR instruction + offset on stack
6755 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
6756 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
6757 = addr(Insn1) + offset - addr(Insn3) - 8
6759 Insn4: add r4, r4, #8 r4 = offset - 8
6760 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
6762 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
6764 Otherwise we don't know what value to write for PC, since the offset is
6765 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
6766 of this can be found in Section "Saving from r15" in
6767 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
6769 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
6774 thumb2_copy_load_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
6775 uint16_t insn2
, struct regcache
*regs
,
6776 struct displaced_step_closure
*dsc
, int size
)
6778 unsigned int u_bit
= bit (insn1
, 7);
6779 unsigned int rt
= bits (insn2
, 12, 15);
6780 int imm12
= bits (insn2
, 0, 11);
6783 if (debug_displaced
)
6784 fprintf_unfiltered (gdb_stdlog
,
6785 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
6786 (unsigned int) dsc
->insn_addr
, rt
, u_bit
? '+' : '-',
6792 /* Rewrite instruction LDR Rt imm12 into:
6794 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
6798 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
6801 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6802 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6803 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6805 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
6807 pc_val
= pc_val
& 0xfffffffc;
6809 displaced_write_reg (regs
, dsc
, 2, pc_val
, CANNOT_WRITE_PC
);
6810 displaced_write_reg (regs
, dsc
, 3, imm12
, CANNOT_WRITE_PC
);
6814 dsc
->u
.ldst
.xfersize
= size
;
6815 dsc
->u
.ldst
.immed
= 0;
6816 dsc
->u
.ldst
.writeback
= 0;
6817 dsc
->u
.ldst
.restore_r4
= 0;
6819 /* LDR R0, R2, R3 */
6820 dsc
->modinsn
[0] = 0xf852;
6821 dsc
->modinsn
[1] = 0x3;
6824 dsc
->cleanup
= &cleanup_load
;
6830 thumb2_copy_load_reg_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
6831 uint16_t insn2
, struct regcache
*regs
,
6832 struct displaced_step_closure
*dsc
,
6833 int writeback
, int immed
)
6835 unsigned int rt
= bits (insn2
, 12, 15);
6836 unsigned int rn
= bits (insn1
, 0, 3);
6837 unsigned int rm
= bits (insn2
, 0, 3); /* Only valid if !immed. */
6838 /* In LDR (register), there is also a register Rm, which is not allowed to
6839 be PC, so we don't have to check it. */
6841 if (rt
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
6842 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "load",
6845 if (debug_displaced
)
6846 fprintf_unfiltered (gdb_stdlog
,
6847 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
6848 rt
, rn
, insn1
, insn2
);
6850 install_load_store (gdbarch
, regs
, dsc
, 1, immed
, writeback
, 4,
6853 dsc
->u
.ldst
.restore_r4
= 0;
6856 /* ldr[b]<cond> rt, [rn, #imm], etc.
6858 ldr[b]<cond> r0, [r2, #imm]. */
6860 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
6861 dsc
->modinsn
[1] = insn2
& 0x0fff;
6864 /* ldr[b]<cond> rt, [rn, rm], etc.
6866 ldr[b]<cond> r0, [r2, r3]. */
6868 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
6869 dsc
->modinsn
[1] = (insn2
& 0x0ff0) | 0x3;
6879 arm_copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
6880 struct regcache
*regs
,
6881 struct displaced_step_closure
*dsc
,
6882 int load
, int size
, int usermode
)
6884 int immed
= !bit (insn
, 25);
6885 int writeback
= (bit (insn
, 24) == 0 || bit (insn
, 21) != 0);
6886 unsigned int rt
= bits (insn
, 12, 15);
6887 unsigned int rn
= bits (insn
, 16, 19);
6888 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
6890 if (!insn_references_pc (insn
, 0x000ff00ful
))
6891 return arm_copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
6893 if (debug_displaced
)
6894 fprintf_unfiltered (gdb_stdlog
,
6895 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
6896 load
? (size
== 1 ? "ldrb" : "ldr")
6897 : (size
== 1 ? "strb" : "str"), usermode
? "t" : "",
6899 (unsigned long) insn
);
6901 install_load_store (gdbarch
, regs
, dsc
, load
, immed
, writeback
, size
,
6902 usermode
, rt
, rm
, rn
);
6904 if (load
|| rt
!= ARM_PC_REGNUM
)
6906 dsc
->u
.ldst
.restore_r4
= 0;
6909 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
6911 {ldr,str}[b]<cond> r0, [r2, #imm]. */
6912 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
6914 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
6916 {ldr,str}[b]<cond> r0, [r2, r3]. */
6917 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
6921 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
6922 dsc
->u
.ldst
.restore_r4
= 1;
6923 dsc
->modinsn
[0] = 0xe92d8000; /* push {pc} */
6924 dsc
->modinsn
[1] = 0xe8bd0010; /* pop {r4} */
6925 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
6926 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
6927 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
6931 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
6933 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
6938 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
6943 /* Cleanup LDM instructions with fully-populated register list. This is an
6944 unfortunate corner case: it's impossible to implement correctly by modifying
6945 the instruction. The issue is as follows: we have an instruction,
6949 which we must rewrite to avoid loading PC. A possible solution would be to
6950 do the load in two halves, something like (with suitable cleanup
6954 ldm[id][ab] r8!, {r0-r7}
6956 ldm[id][ab] r8, {r7-r14}
6959 but at present there's no suitable place for <temp>, since the scratch space
6960 is overwritten before the cleanup routine is called. For now, we simply
6961 emulate the instruction. */
6964 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6965 struct displaced_step_closure
*dsc
)
6967 int inc
= dsc
->u
.block
.increment
;
6968 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
6969 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
6970 uint32_t regmask
= dsc
->u
.block
.regmask
;
6971 int regno
= inc
? 0 : 15;
6972 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
6973 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
6974 && (regmask
& 0x8000) != 0;
6975 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6976 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
6977 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6982 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
6983 sensible we can do here. Complain loudly. */
6984 if (exception_return
)
6985 error (_("Cannot single-step exception return"));
6987 /* We don't handle any stores here for now. */
6988 gdb_assert (dsc
->u
.block
.load
!= 0);
6990 if (debug_displaced
)
6991 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
6992 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
6993 dsc
->u
.block
.increment
? "inc" : "dec",
6994 dsc
->u
.block
.before
? "before" : "after");
7001 while (regno
<= ARM_PC_REGNUM
&& (regmask
& (1 << regno
)) == 0)
7004 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
7007 xfer_addr
+= bump_before
;
7009 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
7010 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
7012 xfer_addr
+= bump_after
;
7014 regmask
&= ~(1 << regno
);
7017 if (dsc
->u
.block
.writeback
)
7018 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
7022 /* Clean up an STM which included the PC in the register list. */
7025 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7026 struct displaced_step_closure
*dsc
)
7028 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
7029 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
7030 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
7031 CORE_ADDR stm_insn_addr
;
7034 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7036 /* If condition code fails, there's nothing else to do. */
7037 if (!store_executed
)
7040 if (dsc
->u
.block
.increment
)
7042 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
7044 if (dsc
->u
.block
.before
)
7049 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
7051 if (dsc
->u
.block
.before
)
7055 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
7056 stm_insn_addr
= dsc
->scratch_base
;
7057 offset
= pc_val
- stm_insn_addr
;
7059 if (debug_displaced
)
7060 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
7061 "STM instruction\n", offset
);
7063 /* Rewrite the stored PC to the proper value for the non-displaced original
7065 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
7066 dsc
->insn_addr
+ offset
);
7069 /* Clean up an LDM which includes the PC in the register list. We clumped all
7070 the registers in the transferred list into a contiguous range r0...rX (to
7071 avoid loading PC directly and losing control of the debugged program), so we
7072 must undo that here. */
7075 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
7076 struct regcache
*regs
,
7077 struct displaced_step_closure
*dsc
)
7079 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
7080 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
);
7081 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= ARM_PC_REGNUM
;
7082 unsigned int regs_loaded
= bitcount (mask
);
7083 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
7085 /* The method employed here will fail if the register list is fully populated
7086 (we need to avoid loading PC directly). */
7087 gdb_assert (num_to_shuffle
< 16);
7092 clobbered
= (1 << num_to_shuffle
) - 1;
7094 while (num_to_shuffle
> 0)
7096 if ((mask
& (1 << write_reg
)) != 0)
7098 unsigned int read_reg
= num_to_shuffle
- 1;
7100 if (read_reg
!= write_reg
)
7102 ULONGEST rval
= displaced_read_reg (regs
, dsc
, read_reg
);
7103 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
7104 if (debug_displaced
)
7105 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
7106 "loaded register r%d to r%d\n"), read_reg
,
7109 else if (debug_displaced
)
7110 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
7111 "r%d already in the right place\n"),
7114 clobbered
&= ~(1 << write_reg
);
7122 /* Restore any registers we scribbled over. */
7123 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
7125 if ((clobbered
& (1 << write_reg
)) != 0)
7127 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
7129 if (debug_displaced
)
7130 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
7131 "clobbered register r%d\n"), write_reg
);
7132 clobbered
&= ~(1 << write_reg
);
7136 /* Perform register writeback manually. */
7137 if (dsc
->u
.block
.writeback
)
7139 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
7141 if (dsc
->u
.block
.increment
)
7142 new_rn_val
+= regs_loaded
* 4;
7144 new_rn_val
-= regs_loaded
* 4;
7146 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
7151 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
7152 in user-level code (in particular exception return, ldm rn, {...pc}^). */
7155 arm_copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
,
7156 struct regcache
*regs
,
7157 struct displaced_step_closure
*dsc
)
7159 int load
= bit (insn
, 20);
7160 int user
= bit (insn
, 22);
7161 int increment
= bit (insn
, 23);
7162 int before
= bit (insn
, 24);
7163 int writeback
= bit (insn
, 21);
7164 int rn
= bits (insn
, 16, 19);
7166 /* Block transfers which don't mention PC can be run directly
7168 if (rn
!= ARM_PC_REGNUM
&& (insn
& 0x8000) == 0)
7169 return arm_copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
7171 if (rn
== ARM_PC_REGNUM
)
7173 warning (_("displaced: Unpredictable LDM or STM with "
7174 "base register r15"));
7175 return arm_copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
7178 if (debug_displaced
)
7179 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
7180 "%.8lx\n", (unsigned long) insn
);
7182 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
7183 dsc
->u
.block
.rn
= rn
;
7185 dsc
->u
.block
.load
= load
;
7186 dsc
->u
.block
.user
= user
;
7187 dsc
->u
.block
.increment
= increment
;
7188 dsc
->u
.block
.before
= before
;
7189 dsc
->u
.block
.writeback
= writeback
;
7190 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
7192 dsc
->u
.block
.regmask
= insn
& 0xffff;
7196 if ((insn
& 0xffff) == 0xffff)
7198 /* LDM with a fully-populated register list. This case is
7199 particularly tricky. Implement for now by fully emulating the
7200 instruction (which might not behave perfectly in all cases, but
7201 these instructions should be rare enough for that not to matter
7203 dsc
->modinsn
[0] = ARM_NOP
;
7205 dsc
->cleanup
= &cleanup_block_load_all
;
7209 /* LDM of a list of registers which includes PC. Implement by
7210 rewriting the list of registers to be transferred into a
7211 contiguous chunk r0...rX before doing the transfer, then shuffling
7212 registers into the correct places in the cleanup routine. */
7213 unsigned int regmask
= insn
& 0xffff;
7214 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
7215 unsigned int to
= 0, from
= 0, i
, new_rn
;
7217 for (i
= 0; i
< num_in_list
; i
++)
7218 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7220 /* Writeback makes things complicated. We need to avoid clobbering
7221 the base register with one of the registers in our modified
7222 register list, but just using a different register can't work in
7225 ldm r14!, {r0-r13,pc}
7227 which would need to be rewritten as:
7231 but that can't work, because there's no free register for N.
7233 Solve this by turning off the writeback bit, and emulating
7234 writeback manually in the cleanup routine. */
7239 new_regmask
= (1 << num_in_list
) - 1;
7241 if (debug_displaced
)
7242 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
7243 "{..., pc}: original reg list %.4x, modified "
7244 "list %.4x\n"), rn
, writeback
? "!" : "",
7245 (int) insn
& 0xffff, new_regmask
);
7247 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
7249 dsc
->cleanup
= &cleanup_block_load_pc
;
7254 /* STM of a list of registers which includes PC. Run the instruction
7255 as-is, but out of line: this will store the wrong value for the PC,
7256 so we must manually fix up the memory in the cleanup routine.
7257 Doing things this way has the advantage that we can auto-detect
7258 the offset of the PC write (which is architecture-dependent) in
7259 the cleanup routine. */
7260 dsc
->modinsn
[0] = insn
;
7262 dsc
->cleanup
= &cleanup_block_store_pc
;
7269 thumb2_copy_block_xfer (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
7270 struct regcache
*regs
,
7271 struct displaced_step_closure
*dsc
)
7273 int rn
= bits (insn1
, 0, 3);
7274 int load
= bit (insn1
, 4);
7275 int writeback
= bit (insn1
, 5);
7277 /* Block transfers which don't mention PC can be run directly
7279 if (rn
!= ARM_PC_REGNUM
&& (insn2
& 0x8000) == 0)
7280 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ldm/stm", dsc
);
7282 if (rn
== ARM_PC_REGNUM
)
7284 warning (_("displaced: Unpredictable LDM or STM with "
7285 "base register r15"));
7286 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7287 "unpredictable ldm/stm", dsc
);
7290 if (debug_displaced
)
7291 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
7292 "%.4x%.4x\n", insn1
, insn2
);
7294 /* Clear bit 13, since it should be always zero. */
7295 dsc
->u
.block
.regmask
= (insn2
& 0xdfff);
7296 dsc
->u
.block
.rn
= rn
;
7298 dsc
->u
.block
.load
= load
;
7299 dsc
->u
.block
.user
= 0;
7300 dsc
->u
.block
.increment
= bit (insn1
, 7);
7301 dsc
->u
.block
.before
= bit (insn1
, 8);
7302 dsc
->u
.block
.writeback
= writeback
;
7303 dsc
->u
.block
.cond
= INST_AL
;
7304 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
7308 if (dsc
->u
.block
.regmask
== 0xffff)
7310 /* This branch is impossible to happen. */
7315 unsigned int regmask
= dsc
->u
.block
.regmask
;
7316 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
7317 unsigned int to
= 0, from
= 0, i
, new_rn
;
7319 for (i
= 0; i
< num_in_list
; i
++)
7320 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7325 new_regmask
= (1 << num_in_list
) - 1;
7327 if (debug_displaced
)
7328 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
7329 "{..., pc}: original reg list %.4x, modified "
7330 "list %.4x\n"), rn
, writeback
? "!" : "",
7331 (int) dsc
->u
.block
.regmask
, new_regmask
);
7333 dsc
->modinsn
[0] = insn1
;
7334 dsc
->modinsn
[1] = (new_regmask
& 0xffff);
7337 dsc
->cleanup
= &cleanup_block_load_pc
;
7342 dsc
->modinsn
[0] = insn1
;
7343 dsc
->modinsn
[1] = insn2
;
7345 dsc
->cleanup
= &cleanup_block_store_pc
;
7350 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
7351 for Linux, where some SVC instructions must be treated specially. */
7354 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7355 struct displaced_step_closure
*dsc
)
7357 CORE_ADDR resume_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
7359 if (debug_displaced
)
7360 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
7361 "%.8lx\n", (unsigned long) resume_addr
);
7363 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
7367 /* Common copy routine for svc instruciton. */
7370 install_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7371 struct displaced_step_closure
*dsc
)
7373 /* Preparation: none.
7374 Insn: unmodified svc.
7375 Cleanup: pc <- insn_addr + insn_size. */
7377 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
7379 dsc
->wrote_to_pc
= 1;
7381 /* Allow OS-specific code to override SVC handling. */
7382 if (dsc
->u
.svc
.copy_svc_os
)
7383 return dsc
->u
.svc
.copy_svc_os (gdbarch
, regs
, dsc
);
7386 dsc
->cleanup
= &cleanup_svc
;
7392 arm_copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
,
7393 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7396 if (debug_displaced
)
7397 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
7398 (unsigned long) insn
);
7400 dsc
->modinsn
[0] = insn
;
7402 return install_svc (gdbarch
, regs
, dsc
);
7406 thumb_copy_svc (struct gdbarch
*gdbarch
, uint16_t insn
,
7407 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7410 if (debug_displaced
)
7411 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.4x\n",
7414 dsc
->modinsn
[0] = insn
;
7416 return install_svc (gdbarch
, regs
, dsc
);
7419 /* Copy undefined instructions. */
7422 arm_copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
7423 struct displaced_step_closure
*dsc
)
7425 if (debug_displaced
)
7426 fprintf_unfiltered (gdb_stdlog
,
7427 "displaced: copying undefined insn %.8lx\n",
7428 (unsigned long) insn
);
7430 dsc
->modinsn
[0] = insn
;
7436 thumb_32bit_copy_undef (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
7437 struct displaced_step_closure
*dsc
)
7440 if (debug_displaced
)
7441 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn "
7442 "%.4x %.4x\n", (unsigned short) insn1
,
7443 (unsigned short) insn2
);
7445 dsc
->modinsn
[0] = insn1
;
7446 dsc
->modinsn
[1] = insn2
;
7452 /* Copy unpredictable instructions. */
7455 arm_copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
7456 struct displaced_step_closure
*dsc
)
7458 if (debug_displaced
)
7459 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
7460 "%.8lx\n", (unsigned long) insn
);
7462 dsc
->modinsn
[0] = insn
;
7467 /* The decode_* functions are instruction decoding helpers. They mostly follow
7468 the presentation in the ARM ARM. */
7471 arm_decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
7472 struct regcache
*regs
,
7473 struct displaced_step_closure
*dsc
)
7475 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
7476 unsigned int rn
= bits (insn
, 16, 19);
7478 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
7479 return arm_copy_unmodified (gdbarch
, insn
, "cps", dsc
);
7480 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
7481 return arm_copy_unmodified (gdbarch
, insn
, "setend", dsc
);
7482 else if ((op1
& 0x60) == 0x20)
7483 return arm_copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
7484 else if ((op1
& 0x71) == 0x40)
7485 return arm_copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store",
7487 else if ((op1
& 0x77) == 0x41)
7488 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
7489 else if ((op1
& 0x77) == 0x45)
7490 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
7491 else if ((op1
& 0x77) == 0x51)
7494 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
7496 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7498 else if ((op1
& 0x77) == 0x55)
7499 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
7500 else if (op1
== 0x57)
7503 case 0x1: return arm_copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
7504 case 0x4: return arm_copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
7505 case 0x5: return arm_copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
7506 case 0x6: return arm_copy_unmodified (gdbarch
, insn
, "isb", dsc
);
7507 default: return arm_copy_unpred (gdbarch
, insn
, dsc
);
7509 else if ((op1
& 0x63) == 0x43)
7510 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7511 else if ((op2
& 0x1) == 0x0)
7512 switch (op1
& ~0x80)
7515 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
7517 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
7518 case 0x71: case 0x75:
7520 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
7521 case 0x63: case 0x67: case 0x73: case 0x77:
7522 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7524 return arm_copy_undef (gdbarch
, insn
, dsc
);
7527 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
7531 arm_decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
7532 struct regcache
*regs
,
7533 struct displaced_step_closure
*dsc
)
7535 if (bit (insn
, 27) == 0)
7536 return arm_decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
7537 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
7538 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
7541 return arm_copy_unmodified (gdbarch
, insn
, "srs", dsc
);
7544 return arm_copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
7546 case 0x4: case 0x5: case 0x6: case 0x7:
7547 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
7550 switch ((insn
& 0xe00000) >> 21)
7552 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
7554 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7557 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
7560 return arm_copy_undef (gdbarch
, insn
, dsc
);
7565 int rn_f
= (bits (insn
, 16, 19) == 0xf);
7566 switch ((insn
& 0xe00000) >> 21)
7569 /* ldc/ldc2 imm (undefined for rn == pc). */
7570 return rn_f
? arm_copy_undef (gdbarch
, insn
, dsc
)
7571 : arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7574 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
7576 case 0x4: case 0x5: case 0x6: case 0x7:
7577 /* ldc/ldc2 lit (undefined for rn != pc). */
7578 return rn_f
? arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
7579 : arm_copy_undef (gdbarch
, insn
, dsc
);
7582 return arm_copy_undef (gdbarch
, insn
, dsc
);
7587 return arm_copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
7590 if (bits (insn
, 16, 19) == 0xf)
7592 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7594 return arm_copy_undef (gdbarch
, insn
, dsc
);
7598 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
7600 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7604 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
7606 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7609 return arm_copy_undef (gdbarch
, insn
, dsc
);
7613 /* Decode miscellaneous instructions in dp/misc encoding space. */
7616 arm_decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
7617 struct regcache
*regs
,
7618 struct displaced_step_closure
*dsc
)
7620 unsigned int op2
= bits (insn
, 4, 6);
7621 unsigned int op
= bits (insn
, 21, 22);
7622 unsigned int op1
= bits (insn
, 16, 19);
7627 return arm_copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
7630 if (op
== 0x1) /* bx. */
7631 return arm_copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
7633 return arm_copy_unmodified (gdbarch
, insn
, "clz", dsc
);
7635 return arm_copy_undef (gdbarch
, insn
, dsc
);
7639 /* Not really supported. */
7640 return arm_copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
7642 return arm_copy_undef (gdbarch
, insn
, dsc
);
7646 return arm_copy_bx_blx_reg (gdbarch
, insn
,
7647 regs
, dsc
); /* blx register. */
7649 return arm_copy_undef (gdbarch
, insn
, dsc
);
7652 return arm_copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
7656 return arm_copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
7658 /* Not really supported. */
7659 return arm_copy_unmodified (gdbarch
, insn
, "smc", dsc
);
7662 return arm_copy_undef (gdbarch
, insn
, dsc
);
7667 arm_decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
,
7668 struct regcache
*regs
,
7669 struct displaced_step_closure
*dsc
)
7672 switch (bits (insn
, 20, 24))
7675 return arm_copy_unmodified (gdbarch
, insn
, "movw", dsc
);
7678 return arm_copy_unmodified (gdbarch
, insn
, "movt", dsc
);
7680 case 0x12: case 0x16:
7681 return arm_copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
7684 return arm_copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
7688 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
7690 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
7691 return arm_copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
7692 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
7693 return arm_copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
7694 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
7695 return arm_decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
7696 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
7697 return arm_copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
7698 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
7699 return arm_copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
7700 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
7701 return arm_copy_unmodified (gdbarch
, insn
, "synch", dsc
);
7702 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
7703 /* 2nd arg means "unpriveleged". */
7704 return arm_copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
7708 /* Should be unreachable. */
7713 arm_decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
7714 struct regcache
*regs
,
7715 struct displaced_step_closure
*dsc
)
7717 int a
= bit (insn
, 25), b
= bit (insn
, 4);
7718 uint32_t op1
= bits (insn
, 20, 24);
7719 int rn_f
= bits (insn
, 16, 19) == 0xf;
7721 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
7722 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
7723 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 0);
7724 else if ((!a
&& (op1
& 0x17) == 0x02)
7725 || (a
&& (op1
& 0x17) == 0x02 && !b
))
7726 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 1);
7727 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
7728 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
7729 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 0);
7730 else if ((!a
&& (op1
& 0x17) == 0x03)
7731 || (a
&& (op1
& 0x17) == 0x03 && !b
))
7732 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 1);
7733 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
7734 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
7735 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
7736 else if ((!a
&& (op1
& 0x17) == 0x06)
7737 || (a
&& (op1
& 0x17) == 0x06 && !b
))
7738 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
7739 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
7740 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
7741 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
7742 else if ((!a
&& (op1
& 0x17) == 0x07)
7743 || (a
&& (op1
& 0x17) == 0x07 && !b
))
7744 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
7746 /* Should be unreachable. */
7751 arm_decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
7752 struct displaced_step_closure
*dsc
)
7754 switch (bits (insn
, 20, 24))
7756 case 0x00: case 0x01: case 0x02: case 0x03:
7757 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
7759 case 0x04: case 0x05: case 0x06: case 0x07:
7760 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
7762 case 0x08: case 0x09: case 0x0a: case 0x0b:
7763 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
7764 return arm_copy_unmodified (gdbarch
, insn
,
7765 "decode/pack/unpack/saturate/reverse", dsc
);
7768 if (bits (insn
, 5, 7) == 0) /* op2. */
7770 if (bits (insn
, 12, 15) == 0xf)
7771 return arm_copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
7773 return arm_copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
7776 return arm_copy_undef (gdbarch
, insn
, dsc
);
7778 case 0x1a: case 0x1b:
7779 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
7780 return arm_copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
7782 return arm_copy_undef (gdbarch
, insn
, dsc
);
7784 case 0x1c: case 0x1d:
7785 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
7787 if (bits (insn
, 0, 3) == 0xf)
7788 return arm_copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
7790 return arm_copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
7793 return arm_copy_undef (gdbarch
, insn
, dsc
);
7795 case 0x1e: case 0x1f:
7796 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
7797 return arm_copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
7799 return arm_copy_undef (gdbarch
, insn
, dsc
);
7802 /* Should be unreachable. */
7807 arm_decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, int32_t insn
,
7808 struct regcache
*regs
,
7809 struct displaced_step_closure
*dsc
)
7812 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
7814 return arm_copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
7818 arm_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
7819 struct regcache
*regs
,
7820 struct displaced_step_closure
*dsc
)
7822 unsigned int opcode
= bits (insn
, 20, 24);
7826 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
7827 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
7829 case 0x08: case 0x0a: case 0x0c: case 0x0e:
7830 case 0x12: case 0x16:
7831 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
7833 case 0x09: case 0x0b: case 0x0d: case 0x0f:
7834 case 0x13: case 0x17:
7835 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
7837 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7838 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7839 /* Note: no writeback for these instructions. Bit 25 will always be
7840 zero though (via caller), so the following works OK. */
7841 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7844 /* Should be unreachable. */
7848 /* Decode shifted register instructions. */
7851 thumb2_decode_dp_shift_reg (struct gdbarch
*gdbarch
, uint16_t insn1
,
7852 uint16_t insn2
, struct regcache
*regs
,
7853 struct displaced_step_closure
*dsc
)
7855 /* PC is only allowed to be used in instruction MOV. */
7857 unsigned int op
= bits (insn1
, 5, 8);
7858 unsigned int rn
= bits (insn1
, 0, 3);
7860 if (op
== 0x2 && rn
== 0xf) /* MOV */
7861 return thumb2_copy_alu_imm (gdbarch
, insn1
, insn2
, regs
, dsc
);
7863 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7864 "dp (shift reg)", dsc
);
7868 /* Decode extension register load/store. Exactly the same as
7869 arm_decode_ext_reg_ld_st. */
7872 thumb2_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint16_t insn1
,
7873 uint16_t insn2
, struct regcache
*regs
,
7874 struct displaced_step_closure
*dsc
)
7876 unsigned int opcode
= bits (insn1
, 4, 8);
7880 case 0x04: case 0x05:
7881 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7882 "vfp/neon vmov", dsc
);
7884 case 0x08: case 0x0c: /* 01x00 */
7885 case 0x0a: case 0x0e: /* 01x10 */
7886 case 0x12: case 0x16: /* 10x10 */
7887 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7888 "vfp/neon vstm/vpush", dsc
);
7890 case 0x09: case 0x0d: /* 01x01 */
7891 case 0x0b: case 0x0f: /* 01x11 */
7892 case 0x13: case 0x17: /* 10x11 */
7893 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7894 "vfp/neon vldm/vpop", dsc
);
7896 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7897 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7899 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7900 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
, regs
, dsc
);
7903 /* Should be unreachable. */
7908 arm_decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
7909 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7911 unsigned int op1
= bits (insn
, 20, 25);
7912 int op
= bit (insn
, 4);
7913 unsigned int coproc
= bits (insn
, 8, 11);
7914 unsigned int rn
= bits (insn
, 16, 19);
7916 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
7917 return arm_decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
7918 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
7919 && (coproc
& 0xe) != 0xa)
7921 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7922 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
7923 && (coproc
& 0xe) != 0xa)
7924 /* ldc/ldc2 imm/lit. */
7925 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7926 else if ((op1
& 0x3e) == 0x00)
7927 return arm_copy_undef (gdbarch
, insn
, dsc
);
7928 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
7929 return arm_copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
7930 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
7931 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
7932 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
7933 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
7934 else if ((op1
& 0x30) == 0x20 && !op
)
7936 if ((coproc
& 0xe) == 0xa)
7937 return arm_copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
7939 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7941 else if ((op1
& 0x30) == 0x20 && op
)
7942 return arm_copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
7943 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
7944 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
7945 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
7946 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
7947 else if ((op1
& 0x30) == 0x30)
7948 return arm_copy_svc (gdbarch
, insn
, regs
, dsc
);
7950 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
7954 thumb2_decode_svc_copro (struct gdbarch
*gdbarch
, uint16_t insn1
,
7955 uint16_t insn2
, struct regcache
*regs
,
7956 struct displaced_step_closure
*dsc
)
7958 unsigned int coproc
= bits (insn2
, 8, 11);
7959 unsigned int op1
= bits (insn1
, 4, 9);
7960 unsigned int bit_5_8
= bits (insn1
, 5, 8);
7961 unsigned int bit_9
= bit (insn1
, 9);
7962 unsigned int bit_4
= bit (insn1
, 4);
7963 unsigned int rn
= bits (insn1
, 0, 3);
7968 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7969 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
7971 else if (bit_5_8
== 0) /* UNDEFINED. */
7972 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
7975 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
7976 if ((coproc
& 0xe) == 0xa)
7977 return thumb2_decode_ext_reg_ld_st (gdbarch
, insn1
, insn2
, regs
,
7979 else /* coproc is not 101x. */
7981 if (bit_4
== 0) /* STC/STC2. */
7982 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7984 else /* LDC/LDC2 {literal, immeidate}. */
7985 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
,
7991 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "coproc", dsc
);
7997 install_pc_relative (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7998 struct displaced_step_closure
*dsc
, int rd
)
8004 Preparation: Rd <- PC
8010 int val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
8011 displaced_write_reg (regs
, dsc
, rd
, val
, CANNOT_WRITE_PC
);
8015 thumb_copy_pc_relative_16bit (struct gdbarch
*gdbarch
, struct regcache
*regs
,
8016 struct displaced_step_closure
*dsc
,
8017 int rd
, unsigned int imm
)
8020 /* Encoding T2: ADDS Rd, #imm */
8021 dsc
->modinsn
[0] = (0x3000 | (rd
<< 8) | imm
);
8023 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
8029 thumb_decode_pc_relative_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
8030 struct regcache
*regs
,
8031 struct displaced_step_closure
*dsc
)
8033 unsigned int rd
= bits (insn
, 8, 10);
8034 unsigned int imm8
= bits (insn
, 0, 7);
8036 if (debug_displaced
)
8037 fprintf_unfiltered (gdb_stdlog
,
8038 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
8041 return thumb_copy_pc_relative_16bit (gdbarch
, regs
, dsc
, rd
, imm8
);
8045 thumb_copy_pc_relative_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
8046 uint16_t insn2
, struct regcache
*regs
,
8047 struct displaced_step_closure
*dsc
)
8049 unsigned int rd
= bits (insn2
, 8, 11);
8050 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
8051 extract raw immediate encoding rather than computing immediate. When
8052 generating ADD or SUB instruction, we can simply perform OR operation to
8053 set immediate into ADD. */
8054 unsigned int imm_3_8
= insn2
& 0x70ff;
8055 unsigned int imm_i
= insn1
& 0x0400; /* Clear all bits except bit 10. */
8057 if (debug_displaced
)
8058 fprintf_unfiltered (gdb_stdlog
,
8059 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
8060 rd
, imm_i
, imm_3_8
, insn1
, insn2
);
8062 if (bit (insn1
, 7)) /* Encoding T2 */
8064 /* Encoding T3: SUB Rd, Rd, #imm */
8065 dsc
->modinsn
[0] = (0xf1a0 | rd
| imm_i
);
8066 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
8068 else /* Encoding T3 */
8070 /* Encoding T3: ADD Rd, Rd, #imm */
8071 dsc
->modinsn
[0] = (0xf100 | rd
| imm_i
);
8072 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
8076 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
8082 thumb_copy_16bit_ldr_literal (struct gdbarch
*gdbarch
, unsigned short insn1
,
8083 struct regcache
*regs
,
8084 struct displaced_step_closure
*dsc
)
8086 unsigned int rt
= bits (insn1
, 8, 10);
8088 int imm8
= (bits (insn1
, 0, 7) << 2);
8089 CORE_ADDR from
= dsc
->insn_addr
;
8095 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
8097 Insn: LDR R0, [R2, R3];
8098 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
8100 if (debug_displaced
)
8101 fprintf_unfiltered (gdb_stdlog
,
8102 "displaced: copying thumb ldr r%d [pc #%d]\n"
8105 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
8106 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
8107 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
8108 pc
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
8109 /* The assembler calculates the required value of the offset from the
8110 Align(PC,4) value of this instruction to the label. */
8111 pc
= pc
& 0xfffffffc;
8113 displaced_write_reg (regs
, dsc
, 2, pc
, CANNOT_WRITE_PC
);
8114 displaced_write_reg (regs
, dsc
, 3, imm8
, CANNOT_WRITE_PC
);
8117 dsc
->u
.ldst
.xfersize
= 4;
8119 dsc
->u
.ldst
.immed
= 0;
8120 dsc
->u
.ldst
.writeback
= 0;
8121 dsc
->u
.ldst
.restore_r4
= 0;
8123 dsc
->modinsn
[0] = 0x58d0; /* ldr r0, [r2, r3]*/
8125 dsc
->cleanup
= &cleanup_load
;
8130 /* Copy Thumb cbnz/cbz insruction. */
8133 thumb_copy_cbnz_cbz (struct gdbarch
*gdbarch
, uint16_t insn1
,
8134 struct regcache
*regs
,
8135 struct displaced_step_closure
*dsc
)
8137 int non_zero
= bit (insn1
, 11);
8138 unsigned int imm5
= (bit (insn1
, 9) << 6) | (bits (insn1
, 3, 7) << 1);
8139 CORE_ADDR from
= dsc
->insn_addr
;
8140 int rn
= bits (insn1
, 0, 2);
8141 int rn_val
= displaced_read_reg (regs
, dsc
, rn
);
8143 dsc
->u
.branch
.cond
= (rn_val
&& non_zero
) || (!rn_val
&& !non_zero
);
8144 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
8145 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
8146 condition is false, let it be, cleanup_branch will do nothing. */
8147 if (dsc
->u
.branch
.cond
)
8149 dsc
->u
.branch
.cond
= INST_AL
;
8150 dsc
->u
.branch
.dest
= from
+ 4 + imm5
;
8153 dsc
->u
.branch
.dest
= from
+ 2;
8155 dsc
->u
.branch
.link
= 0;
8156 dsc
->u
.branch
.exchange
= 0;
8158 if (debug_displaced
)
8159 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s [r%d = 0x%x]"
8160 " insn %.4x to %.8lx\n", non_zero
? "cbnz" : "cbz",
8161 rn
, rn_val
, insn1
, dsc
->u
.branch
.dest
);
8163 dsc
->modinsn
[0] = THUMB_NOP
;
8165 dsc
->cleanup
= &cleanup_branch
;
8169 /* Copy Table Branch Byte/Halfword */
8171 thumb2_copy_table_branch (struct gdbarch
*gdbarch
, uint16_t insn1
,
8172 uint16_t insn2
, struct regcache
*regs
,
8173 struct displaced_step_closure
*dsc
)
8175 ULONGEST rn_val
, rm_val
;
8176 int is_tbh
= bit (insn2
, 4);
8177 CORE_ADDR halfwords
= 0;
8178 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8180 rn_val
= displaced_read_reg (regs
, dsc
, bits (insn1
, 0, 3));
8181 rm_val
= displaced_read_reg (regs
, dsc
, bits (insn2
, 0, 3));
8187 target_read_memory (rn_val
+ 2 * rm_val
, buf
, 2);
8188 halfwords
= extract_unsigned_integer (buf
, 2, byte_order
);
8194 target_read_memory (rn_val
+ rm_val
, buf
, 1);
8195 halfwords
= extract_unsigned_integer (buf
, 1, byte_order
);
8198 if (debug_displaced
)
8199 fprintf_unfiltered (gdb_stdlog
, "displaced: %s base 0x%x offset 0x%x"
8200 " offset 0x%x\n", is_tbh
? "tbh" : "tbb",
8201 (unsigned int) rn_val
, (unsigned int) rm_val
,
8202 (unsigned int) halfwords
);
8204 dsc
->u
.branch
.cond
= INST_AL
;
8205 dsc
->u
.branch
.link
= 0;
8206 dsc
->u
.branch
.exchange
= 0;
8207 dsc
->u
.branch
.dest
= dsc
->insn_addr
+ 4 + 2 * halfwords
;
8209 dsc
->cleanup
= &cleanup_branch
;
8215 cleanup_pop_pc_16bit_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
8216 struct displaced_step_closure
*dsc
)
8219 int val
= displaced_read_reg (regs
, dsc
, 7);
8220 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, val
, BX_WRITE_PC
);
8223 val
= displaced_read_reg (regs
, dsc
, 8);
8224 displaced_write_reg (regs
, dsc
, 7, val
, CANNOT_WRITE_PC
);
8227 displaced_write_reg (regs
, dsc
, 8, dsc
->tmp
[0], CANNOT_WRITE_PC
);
8232 thumb_copy_pop_pc_16bit (struct gdbarch
*gdbarch
, unsigned short insn1
,
8233 struct regcache
*regs
,
8234 struct displaced_step_closure
*dsc
)
8236 dsc
->u
.block
.regmask
= insn1
& 0x00ff;
8238 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
8241 (1) register list is full, that is, r0-r7 are used.
8242 Prepare: tmp[0] <- r8
8244 POP {r0, r1, ...., r6, r7}; remove PC from reglist
8245 MOV r8, r7; Move value of r7 to r8;
8246 POP {r7}; Store PC value into r7.
8248 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
8250 (2) register list is not full, supposing there are N registers in
8251 register list (except PC, 0 <= N <= 7).
8252 Prepare: for each i, 0 - N, tmp[i] <- ri.
8254 POP {r0, r1, ...., rN};
8256 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
8257 from tmp[] properly.
8259 if (debug_displaced
)
8260 fprintf_unfiltered (gdb_stdlog
,
8261 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
8262 dsc
->u
.block
.regmask
, insn1
);
8264 if (dsc
->u
.block
.regmask
== 0xff)
8266 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 8);
8268 dsc
->modinsn
[0] = (insn1
& 0xfeff); /* POP {r0,r1,...,r6, r7} */
8269 dsc
->modinsn
[1] = 0x46b8; /* MOV r8, r7 */
8270 dsc
->modinsn
[2] = 0xbc80; /* POP {r7} */
8273 dsc
->cleanup
= &cleanup_pop_pc_16bit_all
;
8277 unsigned int num_in_list
= bitcount (dsc
->u
.block
.regmask
);
8278 unsigned int new_regmask
, bit
= 1;
8279 unsigned int to
= 0, from
= 0, i
, new_rn
;
8281 for (i
= 0; i
< num_in_list
+ 1; i
++)
8282 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
8284 new_regmask
= (1 << (num_in_list
+ 1)) - 1;
8286 if (debug_displaced
)
8287 fprintf_unfiltered (gdb_stdlog
, _("displaced: POP "
8288 "{..., pc}: original reg list %.4x,"
8289 " modified list %.4x\n"),
8290 (int) dsc
->u
.block
.regmask
, new_regmask
);
8292 dsc
->u
.block
.regmask
|= 0x8000;
8293 dsc
->u
.block
.writeback
= 0;
8294 dsc
->u
.block
.cond
= INST_AL
;
8296 dsc
->modinsn
[0] = (insn1
& ~0x1ff) | (new_regmask
& 0xff);
8298 dsc
->cleanup
= &cleanup_block_load_pc
;
8305 thumb_process_displaced_16bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
8306 struct regcache
*regs
,
8307 struct displaced_step_closure
*dsc
)
8309 unsigned short op_bit_12_15
= bits (insn1
, 12, 15);
8310 unsigned short op_bit_10_11
= bits (insn1
, 10, 11);
8313 /* 16-bit thumb instructions. */
8314 switch (op_bit_12_15
)
8316 /* Shift (imme), add, subtract, move and compare. */
8317 case 0: case 1: case 2: case 3:
8318 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
8319 "shift/add/sub/mov/cmp",
8323 switch (op_bit_10_11
)
8325 case 0: /* Data-processing */
8326 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
8330 case 1: /* Special data instructions and branch and exchange. */
8332 unsigned short op
= bits (insn1
, 7, 9);
8333 if (op
== 6 || op
== 7) /* BX or BLX */
8334 err
= thumb_copy_bx_blx_reg (gdbarch
, insn1
, regs
, dsc
);
8335 else if (bits (insn1
, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
8336 err
= thumb_copy_alu_reg (gdbarch
, insn1
, regs
, dsc
);
8338 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "special data",
8342 default: /* LDR (literal) */
8343 err
= thumb_copy_16bit_ldr_literal (gdbarch
, insn1
, regs
, dsc
);
8346 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
8347 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldr/str", dsc
);
8350 if (op_bit_10_11
< 2) /* Generate PC-relative address */
8351 err
= thumb_decode_pc_relative_16bit (gdbarch
, insn1
, regs
, dsc
);
8352 else /* Generate SP-relative address */
8353 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "sp-relative", dsc
);
8355 case 11: /* Misc 16-bit instructions */
8357 switch (bits (insn1
, 8, 11))
8359 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
8360 err
= thumb_copy_cbnz_cbz (gdbarch
, insn1
, regs
, dsc
);
8362 case 12: case 13: /* POP */
8363 if (bit (insn1
, 8)) /* PC is in register list. */
8364 err
= thumb_copy_pop_pc_16bit (gdbarch
, insn1
, regs
, dsc
);
8366 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "pop", dsc
);
8368 case 15: /* If-Then, and hints */
8369 if (bits (insn1
, 0, 3))
8370 /* If-Then makes up to four following instructions conditional.
8371 IT instruction itself is not conditional, so handle it as a
8372 common unmodified instruction. */
8373 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "If-Then",
8376 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "hints", dsc
);
8379 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "misc", dsc
);
8384 if (op_bit_10_11
< 2) /* Store multiple registers */
8385 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "stm", dsc
);
8386 else /* Load multiple registers */
8387 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldm", dsc
);
8389 case 13: /* Conditional branch and supervisor call */
8390 if (bits (insn1
, 9, 11) != 7) /* conditional branch */
8391 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
8393 err
= thumb_copy_svc (gdbarch
, insn1
, regs
, dsc
);
8395 case 14: /* Unconditional branch */
8396 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
8403 internal_error (__FILE__
, __LINE__
,
8404 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
8408 decode_thumb_32bit_ld_mem_hints (struct gdbarch
*gdbarch
,
8409 uint16_t insn1
, uint16_t insn2
,
8410 struct regcache
*regs
,
8411 struct displaced_step_closure
*dsc
)
8413 int rt
= bits (insn2
, 12, 15);
8414 int rn
= bits (insn1
, 0, 3);
8415 int op1
= bits (insn1
, 7, 8);
8418 switch (bits (insn1
, 5, 6))
8420 case 0: /* Load byte and memory hints */
8421 if (rt
== 0xf) /* PLD/PLI */
8424 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
8425 return thumb2_copy_preload (gdbarch
, insn1
, insn2
, regs
, dsc
);
8427 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8432 if (rn
== 0xf) /* LDRB/LDRSB (literal) */
8433 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
8436 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8437 "ldrb{reg, immediate}/ldrbt",
8442 case 1: /* Load halfword and memory hints. */
8443 if (rt
== 0xf) /* PLD{W} and Unalloc memory hint. */
8444 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8445 "pld/unalloc memhint", dsc
);
8449 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
8452 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8456 case 2: /* Load word */
8458 int insn2_bit_8_11
= bits (insn2
, 8, 11);
8461 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
, 4);
8462 else if (op1
== 0x1) /* Encoding T3 */
8463 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
, dsc
,
8465 else /* op1 == 0x0 */
8467 if (insn2_bit_8_11
== 0xc || (insn2_bit_8_11
& 0x9) == 0x9)
8468 /* LDR (immediate) */
8469 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
8470 dsc
, bit (insn2
, 8), 1);
8471 else if (insn2_bit_8_11
== 0xe) /* LDRT */
8472 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8475 /* LDR (register) */
8476 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
8482 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
8489 thumb_process_displaced_32bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
8490 uint16_t insn2
, struct regcache
*regs
,
8491 struct displaced_step_closure
*dsc
)
8494 unsigned short op
= bit (insn2
, 15);
8495 unsigned int op1
= bits (insn1
, 11, 12);
8501 switch (bits (insn1
, 9, 10))
8506 /* Load/store {dual, execlusive}, table branch. */
8507 if (bits (insn1
, 7, 8) == 1 && bits (insn1
, 4, 5) == 1
8508 && bits (insn2
, 5, 7) == 0)
8509 err
= thumb2_copy_table_branch (gdbarch
, insn1
, insn2
, regs
,
8512 /* PC is not allowed to use in load/store {dual, exclusive}
8514 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8515 "load/store dual/ex", dsc
);
8517 else /* load/store multiple */
8519 switch (bits (insn1
, 7, 8))
8521 case 0: case 3: /* SRS, RFE */
8522 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8525 case 1: case 2: /* LDM/STM/PUSH/POP */
8526 err
= thumb2_copy_block_xfer (gdbarch
, insn1
, insn2
, regs
, dsc
);
8533 /* Data-processing (shift register). */
8534 err
= thumb2_decode_dp_shift_reg (gdbarch
, insn1
, insn2
, regs
,
8537 default: /* Coprocessor instructions. */
8538 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
8543 case 2: /* op1 = 2 */
8544 if (op
) /* Branch and misc control. */
8546 if (bit (insn2
, 14) /* BLX/BL */
8547 || bit (insn2
, 12) /* Unconditional branch */
8548 || (bits (insn1
, 7, 9) != 0x7)) /* Conditional branch */
8549 err
= thumb2_copy_b_bl_blx (gdbarch
, insn1
, insn2
, regs
, dsc
);
8551 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8556 if (bit (insn1
, 9)) /* Data processing (plain binary imm). */
8558 int op
= bits (insn1
, 4, 8);
8559 int rn
= bits (insn1
, 0, 3);
8560 if ((op
== 0 || op
== 0xa) && rn
== 0xf)
8561 err
= thumb_copy_pc_relative_32bit (gdbarch
, insn1
, insn2
,
8564 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8567 else /* Data processing (modified immeidate) */
8568 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8572 case 3: /* op1 = 3 */
8573 switch (bits (insn1
, 9, 10))
8577 err
= decode_thumb_32bit_ld_mem_hints (gdbarch
, insn1
, insn2
,
8579 else /* NEON Load/Store and Store single data item */
8580 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8581 "neon elt/struct load/store",
8584 case 1: /* op1 = 3, bits (9, 10) == 1 */
8585 switch (bits (insn1
, 7, 8))
8587 case 0: case 1: /* Data processing (register) */
8588 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8591 case 2: /* Multiply and absolute difference */
8592 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8593 "mul/mua/diff", dsc
);
8595 case 3: /* Long multiply and divide */
8596 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8601 default: /* Coprocessor instructions */
8602 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
8611 internal_error (__FILE__
, __LINE__
,
8612 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
8617 thumb_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8618 CORE_ADDR to
, struct regcache
*regs
,
8619 struct displaced_step_closure
*dsc
)
8621 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8623 = read_memory_unsigned_integer (from
, 2, byte_order_for_code
);
8625 if (debug_displaced
)
8626 fprintf_unfiltered (gdb_stdlog
, "displaced: process thumb insn %.4x "
8627 "at %.8lx\n", insn1
, (unsigned long) from
);
8630 dsc
->insn_size
= thumb_insn_size (insn1
);
8631 if (thumb_insn_size (insn1
) == 4)
8634 = read_memory_unsigned_integer (from
+ 2, 2, byte_order_for_code
);
8635 thumb_process_displaced_32bit_insn (gdbarch
, insn1
, insn2
, regs
, dsc
);
8638 thumb_process_displaced_16bit_insn (gdbarch
, insn1
, regs
, dsc
);
8642 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8643 CORE_ADDR to
, struct regcache
*regs
,
8644 struct displaced_step_closure
*dsc
)
8647 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8650 /* Most displaced instructions use a 1-instruction scratch space, so set this
8651 here and override below if/when necessary. */
8653 dsc
->insn_addr
= from
;
8654 dsc
->scratch_base
= to
;
8655 dsc
->cleanup
= NULL
;
8656 dsc
->wrote_to_pc
= 0;
8658 if (!displaced_in_arm_mode (regs
))
8659 return thumb_process_displaced_insn (gdbarch
, from
, to
, regs
, dsc
);
8663 insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
8664 if (debug_displaced
)
8665 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
8666 "at %.8lx\n", (unsigned long) insn
,
8667 (unsigned long) from
);
8669 if ((insn
& 0xf0000000) == 0xf0000000)
8670 err
= arm_decode_unconditional (gdbarch
, insn
, regs
, dsc
);
8671 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
8673 case 0x0: case 0x1: case 0x2: case 0x3:
8674 err
= arm_decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
8677 case 0x4: case 0x5: case 0x6:
8678 err
= arm_decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
8682 err
= arm_decode_media (gdbarch
, insn
, dsc
);
8685 case 0x8: case 0x9: case 0xa: case 0xb:
8686 err
= arm_decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
8689 case 0xc: case 0xd: case 0xe: case 0xf:
8690 err
= arm_decode_svc_copro (gdbarch
, insn
, to
, regs
, dsc
);
8695 internal_error (__FILE__
, __LINE__
,
8696 _("arm_process_displaced_insn: Instruction decode error"));
8699 /* Actually set up the scratch space for a displaced instruction. */
8702 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8703 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
8705 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8706 unsigned int i
, len
, offset
;
8707 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8708 int size
= dsc
->is_thumb
? 2 : 4;
8709 const gdb_byte
*bkp_insn
;
8712 /* Poke modified instruction(s). */
8713 for (i
= 0; i
< dsc
->numinsns
; i
++)
8715 if (debug_displaced
)
8717 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn ");
8719 fprintf_unfiltered (gdb_stdlog
, "%.8lx",
8722 fprintf_unfiltered (gdb_stdlog
, "%.4x",
8723 (unsigned short)dsc
->modinsn
[i
]);
8725 fprintf_unfiltered (gdb_stdlog
, " at %.8lx\n",
8726 (unsigned long) to
+ offset
);
8729 write_memory_unsigned_integer (to
+ offset
, size
,
8730 byte_order_for_code
,
8735 /* Choose the correct breakpoint instruction. */
8738 bkp_insn
= tdep
->thumb_breakpoint
;
8739 len
= tdep
->thumb_breakpoint_size
;
8743 bkp_insn
= tdep
->arm_breakpoint
;
8744 len
= tdep
->arm_breakpoint_size
;
8747 /* Put breakpoint afterwards. */
8748 write_memory (to
+ offset
, bkp_insn
, len
);
8750 if (debug_displaced
)
8751 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
8752 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
8755 /* Entry point for copying an instruction into scratch space for displaced
8758 struct displaced_step_closure
*
8759 arm_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
8760 CORE_ADDR from
, CORE_ADDR to
,
8761 struct regcache
*regs
)
8763 struct displaced_step_closure
*dsc
8764 = xmalloc (sizeof (struct displaced_step_closure
));
8765 arm_process_displaced_insn (gdbarch
, from
, to
, regs
, dsc
);
8766 arm_displaced_init_closure (gdbarch
, from
, to
, dsc
);
8771 /* Entry point for cleaning things up after a displaced instruction has been
8775 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
8776 struct displaced_step_closure
*dsc
,
8777 CORE_ADDR from
, CORE_ADDR to
,
8778 struct regcache
*regs
)
8781 dsc
->cleanup (gdbarch
, regs
, dsc
);
8783 if (!dsc
->wrote_to_pc
)
8784 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
8785 dsc
->insn_addr
+ dsc
->insn_size
);
8789 #include "bfd-in2.h"
8790 #include "libcoff.h"
8793 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
8795 struct gdbarch
*gdbarch
= info
->application_data
;
8797 if (arm_pc_is_thumb (gdbarch
, memaddr
))
8799 static asymbol
*asym
;
8800 static combined_entry_type ce
;
8801 static struct coff_symbol_struct csym
;
8802 static struct bfd fake_bfd
;
8803 static bfd_target fake_target
;
8805 if (csym
.native
== NULL
)
8807 /* Create a fake symbol vector containing a Thumb symbol.
8808 This is solely so that the code in print_insn_little_arm()
8809 and print_insn_big_arm() in opcodes/arm-dis.c will detect
8810 the presence of a Thumb symbol and switch to decoding
8811 Thumb instructions. */
8813 fake_target
.flavour
= bfd_target_coff_flavour
;
8814 fake_bfd
.xvec
= &fake_target
;
8815 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
8817 csym
.symbol
.the_bfd
= &fake_bfd
;
8818 csym
.symbol
.name
= "fake";
8819 asym
= (asymbol
*) & csym
;
8822 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
8823 info
->symbols
= &asym
;
8826 info
->symbols
= NULL
;
8828 if (info
->endian
== BFD_ENDIAN_BIG
)
8829 return print_insn_big_arm (memaddr
, info
);
8831 return print_insn_little_arm (memaddr
, info
);
8834 /* The following define instruction sequences that will cause ARM
8835 cpu's to take an undefined instruction trap. These are used to
8836 signal a breakpoint to GDB.
8838 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
8839 modes. A different instruction is required for each mode. The ARM
8840 cpu's can also be big or little endian. Thus four different
8841 instructions are needed to support all cases.
8843 Note: ARMv4 defines several new instructions that will take the
8844 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
8845 not in fact add the new instructions. The new undefined
8846 instructions in ARMv4 are all instructions that had no defined
8847 behaviour in earlier chips. There is no guarantee that they will
8848 raise an exception, but may be treated as NOP's. In practice, it
8849 may only safe to rely on instructions matching:
8851 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
8852 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
8853 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
8855 Even this may only true if the condition predicate is true. The
8856 following use a condition predicate of ALWAYS so it is always TRUE.
8858 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
8859 and NetBSD all use a software interrupt rather than an undefined
8860 instruction to force a trap. This can be handled by by the
8861 abi-specific code during establishment of the gdbarch vector. */
8863 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
8864 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
8865 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
8866 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
8868 static const gdb_byte arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
8869 static const gdb_byte arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
8870 static const gdb_byte arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
8871 static const gdb_byte arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
8873 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
8874 the program counter value to determine whether a 16-bit or 32-bit
8875 breakpoint should be used. It returns a pointer to a string of
8876 bytes that encode a breakpoint instruction, stores the length of
8877 the string to *lenptr, and adjusts the program counter (if
8878 necessary) to point to the actual memory location where the
8879 breakpoint should be inserted. */
8881 static const unsigned char *
8882 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
8884 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8885 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8887 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
8889 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
8891 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
8892 check whether we are replacing a 32-bit instruction. */
8893 if (tdep
->thumb2_breakpoint
!= NULL
)
8896 if (target_read_memory (*pcptr
, buf
, 2) == 0)
8898 unsigned short inst1
;
8899 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
8900 if (thumb_insn_size (inst1
) == 4)
8902 *lenptr
= tdep
->thumb2_breakpoint_size
;
8903 return tdep
->thumb2_breakpoint
;
8908 *lenptr
= tdep
->thumb_breakpoint_size
;
8909 return tdep
->thumb_breakpoint
;
8913 *lenptr
= tdep
->arm_breakpoint_size
;
8914 return tdep
->arm_breakpoint
;
8919 arm_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
8922 arm_breakpoint_from_pc (gdbarch
, pcptr
, kindptr
);
8924 if (arm_pc_is_thumb (gdbarch
, *pcptr
) && *kindptr
== 4)
8925 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
8926 that this is not confused with a 32-bit ARM breakpoint. */
8930 /* Extract from an array REGBUF containing the (raw) register state a
8931 function return value of type TYPE, and copy that, in virtual
8932 format, into VALBUF. */
8935 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
8938 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
8939 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8941 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
8943 switch (gdbarch_tdep (gdbarch
)->fp_model
)
8947 /* The value is in register F0 in internal format. We need to
8948 extract the raw value and then convert it to the desired
8950 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
8952 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
8953 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
8954 valbuf
, gdbarch_byte_order (gdbarch
));
8958 case ARM_FLOAT_SOFT_FPA
:
8959 case ARM_FLOAT_SOFT_VFP
:
8960 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8961 not using the VFP ABI code. */
8963 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
8964 if (TYPE_LENGTH (type
) > 4)
8965 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
8966 valbuf
+ INT_REGISTER_SIZE
);
8970 internal_error (__FILE__
, __LINE__
,
8971 _("arm_extract_return_value: "
8972 "Floating point model not supported"));
8976 else if (TYPE_CODE (type
) == TYPE_CODE_INT
8977 || TYPE_CODE (type
) == TYPE_CODE_CHAR
8978 || TYPE_CODE (type
) == TYPE_CODE_BOOL
8979 || TYPE_CODE (type
) == TYPE_CODE_PTR
8980 || TYPE_CODE (type
) == TYPE_CODE_REF
8981 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
8983 /* If the type is a plain integer, then the access is
8984 straight-forward. Otherwise we have to play around a bit
8986 int len
= TYPE_LENGTH (type
);
8987 int regno
= ARM_A1_REGNUM
;
8992 /* By using store_unsigned_integer we avoid having to do
8993 anything special for small big-endian values. */
8994 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
8995 store_unsigned_integer (valbuf
,
8996 (len
> INT_REGISTER_SIZE
8997 ? INT_REGISTER_SIZE
: len
),
8999 len
-= INT_REGISTER_SIZE
;
9000 valbuf
+= INT_REGISTER_SIZE
;
9005 /* For a structure or union the behaviour is as if the value had
9006 been stored to word-aligned memory and then loaded into
9007 registers with 32-bit load instruction(s). */
9008 int len
= TYPE_LENGTH (type
);
9009 int regno
= ARM_A1_REGNUM
;
9010 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
9014 regcache_cooked_read (regs
, regno
++, tmpbuf
);
9015 memcpy (valbuf
, tmpbuf
,
9016 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
9017 len
-= INT_REGISTER_SIZE
;
9018 valbuf
+= INT_REGISTER_SIZE
;
9024 /* Will a function return an aggregate type in memory or in a
9025 register? Return 0 if an aggregate type can be returned in a
9026 register, 1 if it must be returned in memory. */
9029 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
9032 enum type_code code
;
9034 CHECK_TYPEDEF (type
);
9036 /* In the ARM ABI, "integer" like aggregate types are returned in
9037 registers. For an aggregate type to be integer like, its size
9038 must be less than or equal to INT_REGISTER_SIZE and the
9039 offset of each addressable subfield must be zero. Note that bit
9040 fields are not addressable, and all addressable subfields of
9041 unions always start at offset zero.
9043 This function is based on the behaviour of GCC 2.95.1.
9044 See: gcc/arm.c: arm_return_in_memory() for details.
9046 Note: All versions of GCC before GCC 2.95.2 do not set up the
9047 parameters correctly for a function returning the following
9048 structure: struct { float f;}; This should be returned in memory,
9049 not a register. Richard Earnshaw sent me a patch, but I do not
9050 know of any way to detect if a function like the above has been
9051 compiled with the correct calling convention. */
9053 /* All aggregate types that won't fit in a register must be returned
9055 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
9060 /* The AAPCS says all aggregates not larger than a word are returned
9062 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
9065 /* The only aggregate types that can be returned in a register are
9066 structs and unions. Arrays must be returned in memory. */
9067 code
= TYPE_CODE (type
);
9068 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
9073 /* Assume all other aggregate types can be returned in a register.
9074 Run a check for structures, unions and arrays. */
9077 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
9080 /* Need to check if this struct/union is "integer" like. For
9081 this to be true, its size must be less than or equal to
9082 INT_REGISTER_SIZE and the offset of each addressable
9083 subfield must be zero. Note that bit fields are not
9084 addressable, and unions always start at offset zero. If any
9085 of the subfields is a floating point type, the struct/union
9086 cannot be an integer type. */
9088 /* For each field in the object, check:
9089 1) Is it FP? --> yes, nRc = 1;
9090 2) Is it addressable (bitpos != 0) and
9091 not packed (bitsize == 0)?
9095 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
9097 enum type_code field_type_code
;
9098 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
,
9101 /* Is it a floating point type field? */
9102 if (field_type_code
== TYPE_CODE_FLT
)
9108 /* If bitpos != 0, then we have to care about it. */
9109 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
9111 /* Bitfields are not addressable. If the field bitsize is
9112 zero, then the field is not packed. Hence it cannot be
9113 a bitfield or any other packed type. */
9114 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
9126 /* Write into appropriate registers a function return value of type
9127 TYPE, given in virtual format. */
9130 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
9131 const gdb_byte
*valbuf
)
9133 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
9134 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
9136 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
9138 gdb_byte buf
[MAX_REGISTER_SIZE
];
9140 switch (gdbarch_tdep (gdbarch
)->fp_model
)
9144 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
9145 gdbarch_byte_order (gdbarch
));
9146 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
9149 case ARM_FLOAT_SOFT_FPA
:
9150 case ARM_FLOAT_SOFT_VFP
:
9151 /* ARM_FLOAT_VFP can arise if this is a variadic function so
9152 not using the VFP ABI code. */
9154 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
9155 if (TYPE_LENGTH (type
) > 4)
9156 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
9157 valbuf
+ INT_REGISTER_SIZE
);
9161 internal_error (__FILE__
, __LINE__
,
9162 _("arm_store_return_value: Floating "
9163 "point model not supported"));
9167 else if (TYPE_CODE (type
) == TYPE_CODE_INT
9168 || TYPE_CODE (type
) == TYPE_CODE_CHAR
9169 || TYPE_CODE (type
) == TYPE_CODE_BOOL
9170 || TYPE_CODE (type
) == TYPE_CODE_PTR
9171 || TYPE_CODE (type
) == TYPE_CODE_REF
9172 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
9174 if (TYPE_LENGTH (type
) <= 4)
9176 /* Values of one word or less are zero/sign-extended and
9178 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
9179 LONGEST val
= unpack_long (type
, valbuf
);
9181 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
9182 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
9186 /* Integral values greater than one word are stored in consecutive
9187 registers starting with r0. This will always be a multiple of
9188 the regiser size. */
9189 int len
= TYPE_LENGTH (type
);
9190 int regno
= ARM_A1_REGNUM
;
9194 regcache_cooked_write (regs
, regno
++, valbuf
);
9195 len
-= INT_REGISTER_SIZE
;
9196 valbuf
+= INT_REGISTER_SIZE
;
9202 /* For a structure or union the behaviour is as if the value had
9203 been stored to word-aligned memory and then loaded into
9204 registers with 32-bit load instruction(s). */
9205 int len
= TYPE_LENGTH (type
);
9206 int regno
= ARM_A1_REGNUM
;
9207 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
9211 memcpy (tmpbuf
, valbuf
,
9212 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
9213 regcache_cooked_write (regs
, regno
++, tmpbuf
);
9214 len
-= INT_REGISTER_SIZE
;
9215 valbuf
+= INT_REGISTER_SIZE
;
9221 /* Handle function return values. */
9223 static enum return_value_convention
9224 arm_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
9225 struct type
*valtype
, struct regcache
*regcache
,
9226 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
9228 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9229 struct type
*func_type
= function
? value_type (function
) : NULL
;
9230 enum arm_vfp_cprc_base_type vfp_base_type
;
9233 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
9234 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
9236 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
9237 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
9239 for (i
= 0; i
< vfp_base_count
; i
++)
9241 if (reg_char
== 'q')
9244 arm_neon_quad_write (gdbarch
, regcache
, i
,
9245 writebuf
+ i
* unit_length
);
9248 arm_neon_quad_read (gdbarch
, regcache
, i
,
9249 readbuf
+ i
* unit_length
);
9256 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d", reg_char
, i
);
9257 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9260 regcache_cooked_write (regcache
, regnum
,
9261 writebuf
+ i
* unit_length
);
9263 regcache_cooked_read (regcache
, regnum
,
9264 readbuf
+ i
* unit_length
);
9267 return RETURN_VALUE_REGISTER_CONVENTION
;
9270 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
9271 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
9272 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
9274 if (tdep
->struct_return
== pcc_struct_return
9275 || arm_return_in_memory (gdbarch
, valtype
))
9276 return RETURN_VALUE_STRUCT_CONVENTION
;
9279 /* AAPCS returns complex types longer than a register in memory. */
9280 if (tdep
->arm_abi
!= ARM_ABI_APCS
9281 && TYPE_CODE (valtype
) == TYPE_CODE_COMPLEX
9282 && TYPE_LENGTH (valtype
) > INT_REGISTER_SIZE
)
9283 return RETURN_VALUE_STRUCT_CONVENTION
;
9286 arm_store_return_value (valtype
, regcache
, writebuf
);
9289 arm_extract_return_value (valtype
, regcache
, readbuf
);
9291 return RETURN_VALUE_REGISTER_CONVENTION
;
9296 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
9298 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
9299 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9300 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
9302 gdb_byte buf
[INT_REGISTER_SIZE
];
9304 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
9306 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
9310 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
9314 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
9315 return the target PC. Otherwise return 0. */
9318 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
9322 CORE_ADDR start_addr
;
9324 /* Find the starting address and name of the function containing the PC. */
9325 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
9327 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
9329 start_addr
= arm_skip_bx_reg (frame
, pc
);
9330 if (start_addr
!= 0)
9336 /* If PC is in a Thumb call or return stub, return the address of the
9337 target PC, which is in a register. The thunk functions are called
9338 _call_via_xx, where x is the register name. The possible names
9339 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
9340 functions, named __ARM_call_via_r[0-7]. */
9341 if (strncmp (name
, "_call_via_", 10) == 0
9342 || strncmp (name
, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0)
9344 /* Use the name suffix to determine which register contains the
9346 static char *table
[15] =
9347 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
9348 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
9351 int offset
= strlen (name
) - 2;
9353 for (regno
= 0; regno
<= 14; regno
++)
9354 if (strcmp (&name
[offset
], table
[regno
]) == 0)
9355 return get_frame_register_unsigned (frame
, regno
);
9358 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
9359 non-interworking calls to foo. We could decode the stubs
9360 to find the target but it's easier to use the symbol table. */
9361 namelen
= strlen (name
);
9362 if (name
[0] == '_' && name
[1] == '_'
9363 && ((namelen
> 2 + strlen ("_from_thumb")
9364 && strncmp (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb",
9365 strlen ("_from_thumb")) == 0)
9366 || (namelen
> 2 + strlen ("_from_arm")
9367 && strncmp (name
+ namelen
- strlen ("_from_arm"), "_from_arm",
9368 strlen ("_from_arm")) == 0)))
9371 int target_len
= namelen
- 2;
9372 struct bound_minimal_symbol minsym
;
9373 struct objfile
*objfile
;
9374 struct obj_section
*sec
;
9376 if (name
[namelen
- 1] == 'b')
9377 target_len
-= strlen ("_from_thumb");
9379 target_len
-= strlen ("_from_arm");
9381 target_name
= alloca (target_len
+ 1);
9382 memcpy (target_name
, name
+ 2, target_len
);
9383 target_name
[target_len
] = '\0';
9385 sec
= find_pc_section (pc
);
9386 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
9387 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
9388 if (minsym
.minsym
!= NULL
)
9389 return BMSYMBOL_VALUE_ADDRESS (minsym
);
9394 return 0; /* not a stub */
9398 set_arm_command (char *args
, int from_tty
)
9400 printf_unfiltered (_("\
9401 \"set arm\" must be followed by an apporpriate subcommand.\n"));
9402 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
9406 show_arm_command (char *args
, int from_tty
)
9408 cmd_show_list (showarmcmdlist
, from_tty
, "");
9412 arm_update_current_architecture (void)
9414 struct gdbarch_info info
;
9416 /* If the current architecture is not ARM, we have nothing to do. */
9417 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_arm
)
9420 /* Update the architecture. */
9421 gdbarch_info_init (&info
);
9423 if (!gdbarch_update_p (info
))
9424 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
9428 set_fp_model_sfunc (char *args
, int from_tty
,
9429 struct cmd_list_element
*c
)
9431 enum arm_float_model fp_model
;
9433 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
9434 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
9436 arm_fp_model
= fp_model
;
9440 if (fp_model
== ARM_FLOAT_LAST
)
9441 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
9444 arm_update_current_architecture ();
9448 show_fp_model (struct ui_file
*file
, int from_tty
,
9449 struct cmd_list_element
*c
, const char *value
)
9451 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
9453 if (arm_fp_model
== ARM_FLOAT_AUTO
9454 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
9455 fprintf_filtered (file
, _("\
9456 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
9457 fp_model_strings
[tdep
->fp_model
]);
9459 fprintf_filtered (file
, _("\
9460 The current ARM floating point model is \"%s\".\n"),
9461 fp_model_strings
[arm_fp_model
]);
9465 arm_set_abi (char *args
, int from_tty
,
9466 struct cmd_list_element
*c
)
9468 enum arm_abi_kind arm_abi
;
9470 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
9471 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
9473 arm_abi_global
= arm_abi
;
9477 if (arm_abi
== ARM_ABI_LAST
)
9478 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
9481 arm_update_current_architecture ();
9485 arm_show_abi (struct ui_file
*file
, int from_tty
,
9486 struct cmd_list_element
*c
, const char *value
)
9488 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
9490 if (arm_abi_global
== ARM_ABI_AUTO
9491 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
9492 fprintf_filtered (file
, _("\
9493 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
9494 arm_abi_strings
[tdep
->arm_abi
]);
9496 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
9501 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
9502 struct cmd_list_element
*c
, const char *value
)
9504 fprintf_filtered (file
,
9505 _("The current execution mode assumed "
9506 "(when symbols are unavailable) is \"%s\".\n"),
9507 arm_fallback_mode_string
);
9511 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
9512 struct cmd_list_element
*c
, const char *value
)
9514 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
9516 fprintf_filtered (file
,
9517 _("The current execution mode assumed "
9518 "(even when symbols are available) is \"%s\".\n"),
9519 arm_force_mode_string
);
9522 /* If the user changes the register disassembly style used for info
9523 register and other commands, we have to also switch the style used
9524 in opcodes for disassembly output. This function is run in the "set
9525 arm disassembly" command, and does that. */
9528 set_disassembly_style_sfunc (char *args
, int from_tty
,
9529 struct cmd_list_element
*c
)
9531 set_disassembly_style ();
9534 /* Return the ARM register name corresponding to register I. */
9536 arm_register_name (struct gdbarch
*gdbarch
, int i
)
9538 const int num_regs
= gdbarch_num_regs (gdbarch
);
9540 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
9541 && i
>= num_regs
&& i
< num_regs
+ 32)
9543 static const char *const vfp_pseudo_names
[] = {
9544 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
9545 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
9546 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
9547 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
9550 return vfp_pseudo_names
[i
- num_regs
];
9553 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
9554 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
9556 static const char *const neon_pseudo_names
[] = {
9557 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
9558 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
9561 return neon_pseudo_names
[i
- num_regs
- 32];
9564 if (i
>= ARRAY_SIZE (arm_register_names
))
9565 /* These registers are only supported on targets which supply
9566 an XML description. */
9569 return arm_register_names
[i
];
9573 set_disassembly_style (void)
9577 /* Find the style that the user wants. */
9578 for (current
= 0; current
< num_disassembly_options
; current
++)
9579 if (disassembly_style
== valid_disassembly_styles
[current
])
9581 gdb_assert (current
< num_disassembly_options
);
9583 /* Synchronize the disassembler. */
9584 set_arm_regname_option (current
);
9587 /* Test whether the coff symbol specific value corresponds to a Thumb
9591 coff_sym_is_thumb (int val
)
9593 return (val
== C_THUMBEXT
9594 || val
== C_THUMBSTAT
9595 || val
== C_THUMBEXTFUNC
9596 || val
== C_THUMBSTATFUNC
9597 || val
== C_THUMBLABEL
);
9600 /* arm_coff_make_msymbol_special()
9601 arm_elf_make_msymbol_special()
9603 These functions test whether the COFF or ELF symbol corresponds to
9604 an address in thumb code, and set a "special" bit in a minimal
9605 symbol to indicate that it does. */
9608 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
9610 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type
*)sym
)->internal_elf_sym
)
9611 == ST_BRANCH_TO_THUMB
)
9612 MSYMBOL_SET_SPECIAL (msym
);
9616 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
9618 if (coff_sym_is_thumb (val
))
9619 MSYMBOL_SET_SPECIAL (msym
);
9623 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
9625 struct arm_per_objfile
*data
= arg
;
9628 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
9629 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
9633 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
9636 const char *name
= bfd_asymbol_name (sym
);
9637 struct arm_per_objfile
*data
;
9638 VEC(arm_mapping_symbol_s
) **map_p
;
9639 struct arm_mapping_symbol new_map_sym
;
9641 gdb_assert (name
[0] == '$');
9642 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
9645 data
= objfile_data (objfile
, arm_objfile_data_key
);
9648 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
9649 struct arm_per_objfile
);
9650 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
9651 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
9652 objfile
->obfd
->section_count
,
9653 VEC(arm_mapping_symbol_s
) *);
9655 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
9657 new_map_sym
.value
= sym
->value
;
9658 new_map_sym
.type
= name
[1];
9660 /* Assume that most mapping symbols appear in order of increasing
9661 value. If they were randomly distributed, it would be faster to
9662 always push here and then sort at first use. */
9663 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
9665 struct arm_mapping_symbol
*prev_map_sym
;
9667 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
9668 if (prev_map_sym
->value
>= sym
->value
)
9671 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
9672 arm_compare_mapping_symbols
);
9673 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
9678 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
9682 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
9684 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
9685 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
9687 /* If necessary, set the T bit. */
9690 ULONGEST val
, t_bit
;
9691 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
9692 t_bit
= arm_psr_thumb_bit (gdbarch
);
9693 if (arm_pc_is_thumb (gdbarch
, pc
))
9694 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
9697 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
9702 /* Read the contents of a NEON quad register, by reading from two
9703 double registers. This is used to implement the quad pseudo
9704 registers, and for argument passing in case the quad registers are
9705 missing; vectors are passed in quad registers when using the VFP
9706 ABI, even if a NEON unit is not present. REGNUM is the index of
9707 the quad register, in [0, 15]. */
9709 static enum register_status
9710 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9711 int regnum
, gdb_byte
*buf
)
9714 gdb_byte reg_buf
[8];
9715 int offset
, double_regnum
;
9716 enum register_status status
;
9718 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
9719 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9722 /* d0 is always the least significant half of q0. */
9723 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9728 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9729 if (status
!= REG_VALID
)
9731 memcpy (buf
+ offset
, reg_buf
, 8);
9733 offset
= 8 - offset
;
9734 status
= regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
9735 if (status
!= REG_VALID
)
9737 memcpy (buf
+ offset
, reg_buf
, 8);
9742 static enum register_status
9743 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9744 int regnum
, gdb_byte
*buf
)
9746 const int num_regs
= gdbarch_num_regs (gdbarch
);
9748 gdb_byte reg_buf
[8];
9749 int offset
, double_regnum
;
9751 gdb_assert (regnum
>= num_regs
);
9754 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
9755 /* Quad-precision register. */
9756 return arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
9759 enum register_status status
;
9761 /* Single-precision register. */
9762 gdb_assert (regnum
< 32);
9764 /* s0 is always the least significant half of d0. */
9765 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9766 offset
= (regnum
& 1) ? 0 : 4;
9768 offset
= (regnum
& 1) ? 4 : 0;
9770 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
9771 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9774 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9775 if (status
== REG_VALID
)
9776 memcpy (buf
, reg_buf
+ offset
, 4);
9781 /* Store the contents of BUF to a NEON quad register, by writing to
9782 two double registers. This is used to implement the quad pseudo
9783 registers, and for argument passing in case the quad registers are
9784 missing; vectors are passed in quad registers when using the VFP
9785 ABI, even if a NEON unit is not present. REGNUM is the index
9786 of the quad register, in [0, 15]. */
9789 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9790 int regnum
, const gdb_byte
*buf
)
9793 int offset
, double_regnum
;
9795 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
9796 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9799 /* d0 is always the least significant half of q0. */
9800 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9805 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
9806 offset
= 8 - offset
;
9807 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
9811 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9812 int regnum
, const gdb_byte
*buf
)
9814 const int num_regs
= gdbarch_num_regs (gdbarch
);
9816 gdb_byte reg_buf
[8];
9817 int offset
, double_regnum
;
9819 gdb_assert (regnum
>= num_regs
);
9822 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
9823 /* Quad-precision register. */
9824 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
9827 /* Single-precision register. */
9828 gdb_assert (regnum
< 32);
9830 /* s0 is always the least significant half of d0. */
9831 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9832 offset
= (regnum
& 1) ? 0 : 4;
9834 offset
= (regnum
& 1) ? 4 : 0;
9836 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
9837 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9840 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9841 memcpy (reg_buf
+ offset
, buf
, 4);
9842 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
9846 static struct value
*
9847 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
9849 const int *reg_p
= baton
;
9850 return value_of_register (*reg_p
, frame
);
9853 static enum gdb_osabi
9854 arm_elf_osabi_sniffer (bfd
*abfd
)
9856 unsigned int elfosabi
;
9857 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
9859 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
9861 if (elfosabi
== ELFOSABI_ARM
)
9862 /* GNU tools use this value. Check note sections in this case,
9864 bfd_map_over_sections (abfd
,
9865 generic_elf_osabi_sniff_abi_tag_sections
,
9868 /* Anything else will be handled by the generic ELF sniffer. */
9873 arm_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
9874 struct reggroup
*group
)
9876 /* FPS register's type is INT, but belongs to float_reggroup. Beside
9877 this, FPS register belongs to save_regroup, restore_reggroup, and
9878 all_reggroup, of course. */
9879 if (regnum
== ARM_FPS_REGNUM
)
9880 return (group
== float_reggroup
9881 || group
== save_reggroup
9882 || group
== restore_reggroup
9883 || group
== all_reggroup
);
9885 return default_register_reggroup_p (gdbarch
, regnum
, group
);
9889 /* For backward-compatibility we allow two 'g' packet lengths with
9890 the remote protocol depending on whether FPA registers are
9891 supplied. M-profile targets do not have FPA registers, but some
9892 stubs already exist in the wild which use a 'g' packet which
9893 supplies them albeit with dummy values. The packet format which
9894 includes FPA registers should be considered deprecated for
9895 M-profile targets. */
9898 arm_register_g_packet_guesses (struct gdbarch
*gdbarch
)
9900 if (gdbarch_tdep (gdbarch
)->is_m
)
9902 /* If we know from the executable this is an M-profile target,
9903 cater for remote targets whose register set layout is the
9904 same as the FPA layout. */
9905 register_remote_g_packet_guess (gdbarch
,
9906 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
9907 (16 * INT_REGISTER_SIZE
)
9908 + (8 * FP_REGISTER_SIZE
)
9909 + (2 * INT_REGISTER_SIZE
),
9910 tdesc_arm_with_m_fpa_layout
);
9912 /* The regular M-profile layout. */
9913 register_remote_g_packet_guess (gdbarch
,
9914 /* r0-r12,sp,lr,pc; xpsr */
9915 (16 * INT_REGISTER_SIZE
)
9916 + INT_REGISTER_SIZE
,
9919 /* M-profile plus M4F VFP. */
9920 register_remote_g_packet_guess (gdbarch
,
9921 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
9922 (16 * INT_REGISTER_SIZE
)
9923 + (16 * VFP_REGISTER_SIZE
)
9924 + (2 * INT_REGISTER_SIZE
),
9925 tdesc_arm_with_m_vfp_d16
);
9928 /* Otherwise we don't have a useful guess. */
9932 /* Initialize the current architecture based on INFO. If possible,
9933 re-use an architecture from ARCHES, which is a list of
9934 architectures already created during this debugging session.
9936 Called e.g. at program startup, when reading a core file, and when
9937 reading a binary file. */
9939 static struct gdbarch
*
9940 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
9942 struct gdbarch_tdep
*tdep
;
9943 struct gdbarch
*gdbarch
;
9944 struct gdbarch_list
*best_arch
;
9945 enum arm_abi_kind arm_abi
= arm_abi_global
;
9946 enum arm_float_model fp_model
= arm_fp_model
;
9947 struct tdesc_arch_data
*tdesc_data
= NULL
;
9949 int have_vfp_registers
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
9951 int have_fpa_registers
= 1;
9952 const struct target_desc
*tdesc
= info
.target_desc
;
9954 /* If we have an object to base this architecture on, try to determine
9957 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
9959 int ei_osabi
, e_flags
;
9961 switch (bfd_get_flavour (info
.abfd
))
9963 case bfd_target_aout_flavour
:
9964 /* Assume it's an old APCS-style ABI. */
9965 arm_abi
= ARM_ABI_APCS
;
9968 case bfd_target_coff_flavour
:
9969 /* Assume it's an old APCS-style ABI. */
9971 arm_abi
= ARM_ABI_APCS
;
9974 case bfd_target_elf_flavour
:
9975 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
9976 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9978 if (ei_osabi
== ELFOSABI_ARM
)
9980 /* GNU tools used to use this value, but do not for EABI
9981 objects. There's nowhere to tag an EABI version
9982 anyway, so assume APCS. */
9983 arm_abi
= ARM_ABI_APCS
;
9985 else if (ei_osabi
== ELFOSABI_NONE
)
9987 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
9988 int attr_arch
, attr_profile
;
9992 case EF_ARM_EABI_UNKNOWN
:
9993 /* Assume GNU tools. */
9994 arm_abi
= ARM_ABI_APCS
;
9997 case EF_ARM_EABI_VER4
:
9998 case EF_ARM_EABI_VER5
:
9999 arm_abi
= ARM_ABI_AAPCS
;
10000 /* EABI binaries default to VFP float ordering.
10001 They may also contain build attributes that can
10002 be used to identify if the VFP argument-passing
10004 if (fp_model
== ARM_FLOAT_AUTO
)
10007 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
10012 /* "The user intended FP parameter/result
10013 passing to conform to AAPCS, base
10015 fp_model
= ARM_FLOAT_SOFT_VFP
;
10018 /* "The user intended FP parameter/result
10019 passing to conform to AAPCS, VFP
10021 fp_model
= ARM_FLOAT_VFP
;
10024 /* "The user intended FP parameter/result
10025 passing to conform to tool chain-specific
10026 conventions" - we don't know any such
10027 conventions, so leave it as "auto". */
10030 /* Attribute value not mentioned in the
10031 October 2008 ABI, so leave it as
10036 fp_model
= ARM_FLOAT_SOFT_VFP
;
10042 /* Leave it as "auto". */
10043 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
10048 /* Detect M-profile programs. This only works if the
10049 executable file includes build attributes; GCC does
10050 copy them to the executable, but e.g. RealView does
10052 attr_arch
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
10054 attr_profile
= bfd_elf_get_obj_attr_int (info
.abfd
,
10056 Tag_CPU_arch_profile
);
10057 /* GCC specifies the profile for v6-M; RealView only
10058 specifies the profile for architectures starting with
10059 V7 (as opposed to architectures with a tag
10060 numerically greater than TAG_CPU_ARCH_V7). */
10061 if (!tdesc_has_registers (tdesc
)
10062 && (attr_arch
== TAG_CPU_ARCH_V6_M
10063 || attr_arch
== TAG_CPU_ARCH_V6S_M
10064 || attr_profile
== 'M'))
10069 if (fp_model
== ARM_FLOAT_AUTO
)
10071 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
10073 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
10076 /* Leave it as "auto". Strictly speaking this case
10077 means FPA, but almost nobody uses that now, and
10078 many toolchains fail to set the appropriate bits
10079 for the floating-point model they use. */
10081 case EF_ARM_SOFT_FLOAT
:
10082 fp_model
= ARM_FLOAT_SOFT_FPA
;
10084 case EF_ARM_VFP_FLOAT
:
10085 fp_model
= ARM_FLOAT_VFP
;
10087 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
10088 fp_model
= ARM_FLOAT_SOFT_VFP
;
10093 if (e_flags
& EF_ARM_BE8
)
10094 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
10099 /* Leave it as "auto". */
10104 /* Check any target description for validity. */
10105 if (tdesc_has_registers (tdesc
))
10107 /* For most registers we require GDB's default names; but also allow
10108 the numeric names for sp / lr / pc, as a convenience. */
10109 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
10110 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
10111 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
10113 const struct tdesc_feature
*feature
;
10116 feature
= tdesc_find_feature (tdesc
,
10117 "org.gnu.gdb.arm.core");
10118 if (feature
== NULL
)
10120 feature
= tdesc_find_feature (tdesc
,
10121 "org.gnu.gdb.arm.m-profile");
10122 if (feature
== NULL
)
10128 tdesc_data
= tdesc_data_alloc ();
10131 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
10132 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
10133 arm_register_names
[i
]);
10134 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
10137 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
10140 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
10144 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10145 ARM_PS_REGNUM
, "xpsr");
10147 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10148 ARM_PS_REGNUM
, "cpsr");
10152 tdesc_data_cleanup (tdesc_data
);
10156 feature
= tdesc_find_feature (tdesc
,
10157 "org.gnu.gdb.arm.fpa");
10158 if (feature
!= NULL
)
10161 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
10162 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
10163 arm_register_names
[i
]);
10166 tdesc_data_cleanup (tdesc_data
);
10171 have_fpa_registers
= 0;
10173 feature
= tdesc_find_feature (tdesc
,
10174 "org.gnu.gdb.xscale.iwmmxt");
10175 if (feature
!= NULL
)
10177 static const char *const iwmmxt_names
[] = {
10178 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
10179 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
10180 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
10181 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
10185 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
10187 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
10188 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
10190 /* Check for the control registers, but do not fail if they
10192 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
10193 tdesc_numbered_register (feature
, tdesc_data
, i
,
10194 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
10196 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
10198 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
10199 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
10203 tdesc_data_cleanup (tdesc_data
);
10208 /* If we have a VFP unit, check whether the single precision registers
10209 are present. If not, then we will synthesize them as pseudo
10211 feature
= tdesc_find_feature (tdesc
,
10212 "org.gnu.gdb.arm.vfp");
10213 if (feature
!= NULL
)
10215 static const char *const vfp_double_names
[] = {
10216 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
10217 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
10218 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
10219 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
10222 /* Require the double precision registers. There must be either
10225 for (i
= 0; i
< 32; i
++)
10227 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10229 vfp_double_names
[i
]);
10233 if (!valid_p
&& i
== 16)
10236 /* Also require FPSCR. */
10237 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10238 ARM_FPSCR_REGNUM
, "fpscr");
10241 tdesc_data_cleanup (tdesc_data
);
10245 if (tdesc_unnumbered_register (feature
, "s0") == 0)
10246 have_vfp_pseudos
= 1;
10248 have_vfp_registers
= 1;
10250 /* If we have VFP, also check for NEON. The architecture allows
10251 NEON without VFP (integer vector operations only), but GDB
10252 does not support that. */
10253 feature
= tdesc_find_feature (tdesc
,
10254 "org.gnu.gdb.arm.neon");
10255 if (feature
!= NULL
)
10257 /* NEON requires 32 double-precision registers. */
10260 tdesc_data_cleanup (tdesc_data
);
10264 /* If there are quad registers defined by the stub, use
10265 their type; otherwise (normally) provide them with
10266 the default type. */
10267 if (tdesc_unnumbered_register (feature
, "q0") == 0)
10268 have_neon_pseudos
= 1;
10275 /* If there is already a candidate, use it. */
10276 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
10278 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
10280 if (arm_abi
!= ARM_ABI_AUTO
10281 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
10284 if (fp_model
!= ARM_FLOAT_AUTO
10285 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
10288 /* There are various other properties in tdep that we do not
10289 need to check here: those derived from a target description,
10290 since gdbarches with a different target description are
10291 automatically disqualified. */
10293 /* Do check is_m, though, since it might come from the binary. */
10294 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
10297 /* Found a match. */
10301 if (best_arch
!= NULL
)
10303 if (tdesc_data
!= NULL
)
10304 tdesc_data_cleanup (tdesc_data
);
10305 return best_arch
->gdbarch
;
10308 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
10309 gdbarch
= gdbarch_alloc (&info
, tdep
);
10311 /* Record additional information about the architecture we are defining.
10312 These are gdbarch discriminators, like the OSABI. */
10313 tdep
->arm_abi
= arm_abi
;
10314 tdep
->fp_model
= fp_model
;
10316 tdep
->have_fpa_registers
= have_fpa_registers
;
10317 tdep
->have_vfp_registers
= have_vfp_registers
;
10318 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
10319 tdep
->have_neon_pseudos
= have_neon_pseudos
;
10320 tdep
->have_neon
= have_neon
;
10322 arm_register_g_packet_guesses (gdbarch
);
10325 switch (info
.byte_order_for_code
)
10327 case BFD_ENDIAN_BIG
:
10328 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
10329 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
10330 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
10331 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
10335 case BFD_ENDIAN_LITTLE
:
10336 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
10337 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
10338 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
10339 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
10344 internal_error (__FILE__
, __LINE__
,
10345 _("arm_gdbarch_init: bad byte order for float format"));
10348 /* On ARM targets char defaults to unsigned. */
10349 set_gdbarch_char_signed (gdbarch
, 0);
10351 /* Note: for displaced stepping, this includes the breakpoint, and one word
10352 of additional scratch space. This setting isn't used for anything beside
10353 displaced stepping at present. */
10354 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
10356 /* This should be low enough for everything. */
10357 tdep
->lowest_pc
= 0x20;
10358 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
10360 /* The default, for both APCS and AAPCS, is to return small
10361 structures in registers. */
10362 tdep
->struct_return
= reg_struct_return
;
10364 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
10365 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
10367 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
10369 /* Frame handling. */
10370 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
10371 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
10372 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
10374 frame_base_set_default (gdbarch
, &arm_normal_base
);
10376 /* Address manipulation. */
10377 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
10379 /* Advance PC across function entry code. */
10380 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
10382 /* Detect whether PC is in function epilogue. */
10383 set_gdbarch_in_function_epilogue_p (gdbarch
, arm_in_function_epilogue_p
);
10385 /* Skip trampolines. */
10386 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
10388 /* The stack grows downward. */
10389 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
10391 /* Breakpoint manipulation. */
10392 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
10393 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
10394 arm_remote_breakpoint_from_pc
);
10396 /* Information about registers, etc. */
10397 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
10398 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
10399 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
10400 set_gdbarch_register_type (gdbarch
, arm_register_type
);
10401 set_gdbarch_register_reggroup_p (gdbarch
, arm_register_reggroup_p
);
10403 /* This "info float" is FPA-specific. Use the generic version if we
10404 do not have FPA. */
10405 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
10406 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
10408 /* Internal <-> external register number maps. */
10409 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
10410 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
10412 set_gdbarch_register_name (gdbarch
, arm_register_name
);
10414 /* Returning results. */
10415 set_gdbarch_return_value (gdbarch
, arm_return_value
);
10418 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
10420 /* Minsymbol frobbing. */
10421 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
10422 set_gdbarch_coff_make_msymbol_special (gdbarch
,
10423 arm_coff_make_msymbol_special
);
10424 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
10426 /* Thumb-2 IT block support. */
10427 set_gdbarch_adjust_breakpoint_address (gdbarch
,
10428 arm_adjust_breakpoint_address
);
10430 /* Virtual tables. */
10431 set_gdbarch_vbit_in_delta (gdbarch
, 1);
10433 /* Hook in the ABI-specific overrides, if they have been registered. */
10434 gdbarch_init_osabi (info
, gdbarch
);
10436 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
10438 /* Add some default predicates. */
10440 frame_unwind_append_unwinder (gdbarch
, &arm_m_exception_unwind
);
10441 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
10442 dwarf2_append_unwinders (gdbarch
);
10443 frame_unwind_append_unwinder (gdbarch
, &arm_exidx_unwind
);
10444 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
10446 /* Now we have tuned the configuration, set a few final things,
10447 based on what the OS ABI has told us. */
10449 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
10450 binaries are always marked. */
10451 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
10452 tdep
->arm_abi
= ARM_ABI_APCS
;
10454 /* Watchpoints are not steppable. */
10455 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
10457 /* We used to default to FPA for generic ARM, but almost nobody
10458 uses that now, and we now provide a way for the user to force
10459 the model. So default to the most useful variant. */
10460 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
10461 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
10463 if (tdep
->jb_pc
>= 0)
10464 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
10466 /* Floating point sizes and format. */
10467 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
10468 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
10470 set_gdbarch_double_format
10471 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
10472 set_gdbarch_long_double_format
10473 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
10477 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
10478 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
10481 if (have_vfp_pseudos
)
10483 /* NOTE: These are the only pseudo registers used by
10484 the ARM target at the moment. If more are added, a
10485 little more care in numbering will be needed. */
10487 int num_pseudos
= 32;
10488 if (have_neon_pseudos
)
10490 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
10491 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
10492 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
10497 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
10499 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
10501 /* Override tdesc_register_type to adjust the types of VFP
10502 registers for NEON. */
10503 set_gdbarch_register_type (gdbarch
, arm_register_type
);
10506 /* Add standard register aliases. We add aliases even for those
10507 nanes which are used by the current architecture - it's simpler,
10508 and does no harm, since nothing ever lists user registers. */
10509 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
10510 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
10511 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
10517 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
10519 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
10524 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
10525 (unsigned long) tdep
->lowest_pc
);
10528 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
10531 _initialize_arm_tdep (void)
10533 struct ui_file
*stb
;
10535 struct cmd_list_element
*new_set
, *new_show
;
10536 const char *setname
;
10537 const char *setdesc
;
10538 const char *const *regnames
;
10540 static char *helptext
;
10541 char regdesc
[1024], *rdptr
= regdesc
;
10542 size_t rest
= sizeof (regdesc
);
10544 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
10546 arm_objfile_data_key
10547 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
10549 /* Add ourselves to objfile event chain. */
10550 observer_attach_new_objfile (arm_exidx_new_objfile
);
10552 = register_objfile_data_with_cleanup (NULL
, arm_exidx_data_free
);
10554 /* Register an ELF OS ABI sniffer for ARM binaries. */
10555 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
10556 bfd_target_elf_flavour
,
10557 arm_elf_osabi_sniffer
);
10559 /* Initialize the standard target descriptions. */
10560 initialize_tdesc_arm_with_m ();
10561 initialize_tdesc_arm_with_m_fpa_layout ();
10562 initialize_tdesc_arm_with_m_vfp_d16 ();
10563 initialize_tdesc_arm_with_iwmmxt ();
10564 initialize_tdesc_arm_with_vfpv2 ();
10565 initialize_tdesc_arm_with_vfpv3 ();
10566 initialize_tdesc_arm_with_neon ();
10568 /* Get the number of possible sets of register names defined in opcodes. */
10569 num_disassembly_options
= get_arm_regname_num_options ();
10571 /* Add root prefix command for all "set arm"/"show arm" commands. */
10572 add_prefix_cmd ("arm", no_class
, set_arm_command
,
10573 _("Various ARM-specific commands."),
10574 &setarmcmdlist
, "set arm ", 0, &setlist
);
10576 add_prefix_cmd ("arm", no_class
, show_arm_command
,
10577 _("Various ARM-specific commands."),
10578 &showarmcmdlist
, "show arm ", 0, &showlist
);
10580 /* Sync the opcode insn printer with our register viewer. */
10581 parse_arm_disassembler_option ("reg-names-std");
10583 /* Initialize the array that will be passed to
10584 add_setshow_enum_cmd(). */
10585 valid_disassembly_styles
10586 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
10587 for (i
= 0; i
< num_disassembly_options
; i
++)
10589 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
10590 valid_disassembly_styles
[i
] = setname
;
10591 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
10594 /* When we find the default names, tell the disassembler to use
10596 if (!strcmp (setname
, "std"))
10598 disassembly_style
= setname
;
10599 set_arm_regname_option (i
);
10602 /* Mark the end of valid options. */
10603 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
10605 /* Create the help text. */
10606 stb
= mem_fileopen ();
10607 fprintf_unfiltered (stb
, "%s%s%s",
10608 _("The valid values are:\n"),
10610 _("The default is \"std\"."));
10611 helptext
= ui_file_xstrdup (stb
, NULL
);
10612 ui_file_delete (stb
);
10614 add_setshow_enum_cmd("disassembler", no_class
,
10615 valid_disassembly_styles
, &disassembly_style
,
10616 _("Set the disassembly style."),
10617 _("Show the disassembly style."),
10619 set_disassembly_style_sfunc
,
10620 NULL
, /* FIXME: i18n: The disassembly style is
10622 &setarmcmdlist
, &showarmcmdlist
);
10624 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
10625 _("Set usage of ARM 32-bit mode."),
10626 _("Show usage of ARM 32-bit mode."),
10627 _("When off, a 26-bit PC will be used."),
10629 NULL
, /* FIXME: i18n: Usage of ARM 32-bit
10631 &setarmcmdlist
, &showarmcmdlist
);
10633 /* Add a command to allow the user to force the FPU model. */
10634 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
10635 _("Set the floating point type."),
10636 _("Show the floating point type."),
10637 _("auto - Determine the FP typefrom the OS-ABI.\n\
10638 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
10639 fpa - FPA co-processor (GCC compiled).\n\
10640 softvfp - Software FP with pure-endian doubles.\n\
10641 vfp - VFP co-processor."),
10642 set_fp_model_sfunc
, show_fp_model
,
10643 &setarmcmdlist
, &showarmcmdlist
);
10645 /* Add a command to allow the user to force the ABI. */
10646 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
10648 _("Show the ABI."),
10649 NULL
, arm_set_abi
, arm_show_abi
,
10650 &setarmcmdlist
, &showarmcmdlist
);
10652 /* Add two commands to allow the user to force the assumed
10654 add_setshow_enum_cmd ("fallback-mode", class_support
,
10655 arm_mode_strings
, &arm_fallback_mode_string
,
10656 _("Set the mode assumed when symbols are unavailable."),
10657 _("Show the mode assumed when symbols are unavailable."),
10658 NULL
, NULL
, arm_show_fallback_mode
,
10659 &setarmcmdlist
, &showarmcmdlist
);
10660 add_setshow_enum_cmd ("force-mode", class_support
,
10661 arm_mode_strings
, &arm_force_mode_string
,
10662 _("Set the mode assumed even when symbols are available."),
10663 _("Show the mode assumed even when symbols are available."),
10664 NULL
, NULL
, arm_show_force_mode
,
10665 &setarmcmdlist
, &showarmcmdlist
);
10667 /* Debugging flag. */
10668 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
10669 _("Set ARM debugging."),
10670 _("Show ARM debugging."),
10671 _("When on, arm-specific debugging is enabled."),
10673 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
10674 &setdebuglist
, &showdebuglist
);
10677 /* ARM-reversible process record data structures. */
10679 #define ARM_INSN_SIZE_BYTES 4
10680 #define THUMB_INSN_SIZE_BYTES 2
10681 #define THUMB2_INSN_SIZE_BYTES 4
10684 /* Position of the bit within a 32-bit ARM instruction
10685 that defines whether the instruction is a load or store. */
10686 #define INSN_S_L_BIT_NUM 20
10688 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
10691 unsigned int reg_len = LENGTH; \
10694 REGS = XNEWVEC (uint32_t, reg_len); \
10695 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
10700 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
10703 unsigned int mem_len = LENGTH; \
10706 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
10707 memcpy(&MEMS->len, &RECORD_BUF[0], \
10708 sizeof(struct arm_mem_r) * LENGTH); \
10713 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
10714 #define INSN_RECORDED(ARM_RECORD) \
10715 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
10717 /* ARM memory record structure. */
10720 uint32_t len
; /* Record length. */
10721 uint32_t addr
; /* Memory address. */
10724 /* ARM instruction record contains opcode of current insn
10725 and execution state (before entry to decode_insn()),
10726 contains list of to-be-modified registers and
10727 memory blocks (on return from decode_insn()). */
10729 typedef struct insn_decode_record_t
10731 struct gdbarch
*gdbarch
;
10732 struct regcache
*regcache
;
10733 CORE_ADDR this_addr
; /* Address of the insn being decoded. */
10734 uint32_t arm_insn
; /* Should accommodate thumb. */
10735 uint32_t cond
; /* Condition code. */
10736 uint32_t opcode
; /* Insn opcode. */
10737 uint32_t decode
; /* Insn decode bits. */
10738 uint32_t mem_rec_count
; /* No of mem records. */
10739 uint32_t reg_rec_count
; /* No of reg records. */
10740 uint32_t *arm_regs
; /* Registers to be saved for this record. */
10741 struct arm_mem_r
*arm_mems
; /* Memory to be saved for this record. */
10742 } insn_decode_record
;
10745 /* Checks ARM SBZ and SBO mandatory fields. */
10748 sbo_sbz (uint32_t insn
, uint32_t bit_num
, uint32_t len
, uint32_t sbo
)
10750 uint32_t ones
= bits (insn
, bit_num
- 1, (bit_num
-1) + (len
- 1));
10769 enum arm_record_result
10771 ARM_RECORD_SUCCESS
= 0,
10772 ARM_RECORD_FAILURE
= 1
10779 } arm_record_strx_t
;
10790 arm_record_strx (insn_decode_record
*arm_insn_r
, uint32_t *record_buf
,
10791 uint32_t *record_buf_mem
, arm_record_strx_t str_type
)
10794 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10795 ULONGEST u_regval
[2]= {0};
10797 uint32_t reg_src1
= 0, reg_src2
= 0;
10798 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
10799 uint32_t opcode1
= 0;
10801 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10802 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10803 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
10806 if (14 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10808 /* 1) Handle misc store, immediate offset. */
10809 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
10810 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
10811 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10812 regcache_raw_read_unsigned (reg_cache
, reg_src1
,
10814 if (ARM_PC_REGNUM
== reg_src1
)
10816 /* If R15 was used as Rn, hence current PC+8. */
10817 u_regval
[0] = u_regval
[0] + 8;
10819 offset_8
= (immed_high
<< 4) | immed_low
;
10820 /* Calculate target store address. */
10821 if (14 == arm_insn_r
->opcode
)
10823 tgt_mem_addr
= u_regval
[0] + offset_8
;
10827 tgt_mem_addr
= u_regval
[0] - offset_8
;
10829 if (ARM_RECORD_STRH
== str_type
)
10831 record_buf_mem
[0] = 2;
10832 record_buf_mem
[1] = tgt_mem_addr
;
10833 arm_insn_r
->mem_rec_count
= 1;
10835 else if (ARM_RECORD_STRD
== str_type
)
10837 record_buf_mem
[0] = 4;
10838 record_buf_mem
[1] = tgt_mem_addr
;
10839 record_buf_mem
[2] = 4;
10840 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10841 arm_insn_r
->mem_rec_count
= 2;
10844 else if (12 == arm_insn_r
->opcode
|| 8 == arm_insn_r
->opcode
)
10846 /* 2) Store, register offset. */
10848 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10850 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10851 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10852 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10853 if (15 == reg_src2
)
10855 /* If R15 was used as Rn, hence current PC+8. */
10856 u_regval
[0] = u_regval
[0] + 8;
10858 /* Calculate target store address, Rn +/- Rm, register offset. */
10859 if (12 == arm_insn_r
->opcode
)
10861 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10865 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10867 if (ARM_RECORD_STRH
== str_type
)
10869 record_buf_mem
[0] = 2;
10870 record_buf_mem
[1] = tgt_mem_addr
;
10871 arm_insn_r
->mem_rec_count
= 1;
10873 else if (ARM_RECORD_STRD
== str_type
)
10875 record_buf_mem
[0] = 4;
10876 record_buf_mem
[1] = tgt_mem_addr
;
10877 record_buf_mem
[2] = 4;
10878 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10879 arm_insn_r
->mem_rec_count
= 2;
10882 else if (11 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10883 || 2 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
10885 /* 3) Store, immediate pre-indexed. */
10886 /* 5) Store, immediate post-indexed. */
10887 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
10888 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
10889 offset_8
= (immed_high
<< 4) | immed_low
;
10890 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10891 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10892 /* Calculate target store address, Rn +/- Rm, register offset. */
10893 if (15 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
10895 tgt_mem_addr
= u_regval
[0] + offset_8
;
10899 tgt_mem_addr
= u_regval
[0] - offset_8
;
10901 if (ARM_RECORD_STRH
== str_type
)
10903 record_buf_mem
[0] = 2;
10904 record_buf_mem
[1] = tgt_mem_addr
;
10905 arm_insn_r
->mem_rec_count
= 1;
10907 else if (ARM_RECORD_STRD
== str_type
)
10909 record_buf_mem
[0] = 4;
10910 record_buf_mem
[1] = tgt_mem_addr
;
10911 record_buf_mem
[2] = 4;
10912 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10913 arm_insn_r
->mem_rec_count
= 2;
10915 /* Record Rn also as it changes. */
10916 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
10917 arm_insn_r
->reg_rec_count
= 1;
10919 else if (9 == arm_insn_r
->opcode
|| 13 == arm_insn_r
->opcode
10920 || 0 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
10922 /* 4) Store, register pre-indexed. */
10923 /* 6) Store, register post -indexed. */
10924 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10925 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10926 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10927 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10928 /* Calculate target store address, Rn +/- Rm, register offset. */
10929 if (13 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
10931 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10935 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10937 if (ARM_RECORD_STRH
== str_type
)
10939 record_buf_mem
[0] = 2;
10940 record_buf_mem
[1] = tgt_mem_addr
;
10941 arm_insn_r
->mem_rec_count
= 1;
10943 else if (ARM_RECORD_STRD
== str_type
)
10945 record_buf_mem
[0] = 4;
10946 record_buf_mem
[1] = tgt_mem_addr
;
10947 record_buf_mem
[2] = 4;
10948 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10949 arm_insn_r
->mem_rec_count
= 2;
10951 /* Record Rn also as it changes. */
10952 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
10953 arm_insn_r
->reg_rec_count
= 1;
10958 /* Handling ARM extension space insns. */
10961 arm_record_extension_space (insn_decode_record
*arm_insn_r
)
10963 uint32_t ret
= 0; /* Return value: -1:record failure ; 0:success */
10964 uint32_t opcode1
= 0, opcode2
= 0, insn_op1
= 0;
10965 uint32_t record_buf
[8], record_buf_mem
[8];
10966 uint32_t reg_src1
= 0;
10967 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
10968 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10969 ULONGEST u_regval
= 0;
10971 gdb_assert (!INSN_RECORDED(arm_insn_r
));
10972 /* Handle unconditional insn extension space. */
10974 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 27);
10975 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10976 if (arm_insn_r
->cond
)
10978 /* PLD has no affect on architectural state, it just affects
10980 if (5 == ((opcode1
& 0xE0) >> 5))
10983 record_buf
[0] = ARM_PS_REGNUM
;
10984 record_buf
[1] = ARM_LR_REGNUM
;
10985 arm_insn_r
->reg_rec_count
= 2;
10987 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10991 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10992 if (3 == opcode1
&& bit (arm_insn_r
->arm_insn
, 4))
10995 /* Undefined instruction on ARM V5; need to handle if later
10996 versions define it. */
10999 opcode1
= bits (arm_insn_r
->arm_insn
, 24, 27);
11000 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
11001 insn_op1
= bits (arm_insn_r
->arm_insn
, 20, 23);
11003 /* Handle arithmetic insn extension space. */
11004 if (!opcode1
&& 9 == opcode2
&& 1 != arm_insn_r
->cond
11005 && !INSN_RECORDED(arm_insn_r
))
11007 /* Handle MLA(S) and MUL(S). */
11008 if (0 <= insn_op1
&& 3 >= insn_op1
)
11010 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11011 record_buf
[1] = ARM_PS_REGNUM
;
11012 arm_insn_r
->reg_rec_count
= 2;
11014 else if (4 <= insn_op1
&& 15 >= insn_op1
)
11016 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
11017 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
11018 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
11019 record_buf
[2] = ARM_PS_REGNUM
;
11020 arm_insn_r
->reg_rec_count
= 3;
11024 opcode1
= bits (arm_insn_r
->arm_insn
, 26, 27);
11025 opcode2
= bits (arm_insn_r
->arm_insn
, 23, 24);
11026 insn_op1
= bits (arm_insn_r
->arm_insn
, 21, 22);
11028 /* Handle control insn extension space. */
11030 if (!opcode1
&& 2 == opcode2
&& !bit (arm_insn_r
->arm_insn
, 20)
11031 && 1 != arm_insn_r
->cond
&& !INSN_RECORDED(arm_insn_r
))
11033 if (!bit (arm_insn_r
->arm_insn
,25))
11035 if (!bits (arm_insn_r
->arm_insn
, 4, 7))
11037 if ((0 == insn_op1
) || (2 == insn_op1
))
11040 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11041 arm_insn_r
->reg_rec_count
= 1;
11043 else if (1 == insn_op1
)
11045 /* CSPR is going to be changed. */
11046 record_buf
[0] = ARM_PS_REGNUM
;
11047 arm_insn_r
->reg_rec_count
= 1;
11049 else if (3 == insn_op1
)
11051 /* SPSR is going to be changed. */
11052 /* We need to get SPSR value, which is yet to be done. */
11053 printf_unfiltered (_("Process record does not support "
11054 "instruction 0x%0x at address %s.\n"),
11055 arm_insn_r
->arm_insn
,
11056 paddress (arm_insn_r
->gdbarch
,
11057 arm_insn_r
->this_addr
));
11061 else if (1 == bits (arm_insn_r
->arm_insn
, 4, 7))
11066 record_buf
[0] = ARM_PS_REGNUM
;
11067 arm_insn_r
->reg_rec_count
= 1;
11069 else if (3 == insn_op1
)
11072 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11073 arm_insn_r
->reg_rec_count
= 1;
11076 else if (3 == bits (arm_insn_r
->arm_insn
, 4, 7))
11079 record_buf
[0] = ARM_PS_REGNUM
;
11080 record_buf
[1] = ARM_LR_REGNUM
;
11081 arm_insn_r
->reg_rec_count
= 2;
11083 else if (5 == bits (arm_insn_r
->arm_insn
, 4, 7))
11085 /* QADD, QSUB, QDADD, QDSUB */
11086 record_buf
[0] = ARM_PS_REGNUM
;
11087 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
11088 arm_insn_r
->reg_rec_count
= 2;
11090 else if (7 == bits (arm_insn_r
->arm_insn
, 4, 7))
11093 record_buf
[0] = ARM_PS_REGNUM
;
11094 record_buf
[1] = ARM_LR_REGNUM
;
11095 arm_insn_r
->reg_rec_count
= 2;
11097 /* Save SPSR also;how? */
11098 printf_unfiltered (_("Process record does not support "
11099 "instruction 0x%0x at address %s.\n"),
11100 arm_insn_r
->arm_insn
,
11101 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11104 else if(8 == bits (arm_insn_r
->arm_insn
, 4, 7)
11105 || 10 == bits (arm_insn_r
->arm_insn
, 4, 7)
11106 || 12 == bits (arm_insn_r
->arm_insn
, 4, 7)
11107 || 14 == bits (arm_insn_r
->arm_insn
, 4, 7)
11110 if (0 == insn_op1
|| 1 == insn_op1
)
11112 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
11113 /* We dont do optimization for SMULW<y> where we
11115 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11116 record_buf
[1] = ARM_PS_REGNUM
;
11117 arm_insn_r
->reg_rec_count
= 2;
11119 else if (2 == insn_op1
)
11122 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11123 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11124 arm_insn_r
->reg_rec_count
= 2;
11126 else if (3 == insn_op1
)
11129 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11130 arm_insn_r
->reg_rec_count
= 1;
11136 /* MSR : immediate form. */
11139 /* CSPR is going to be changed. */
11140 record_buf
[0] = ARM_PS_REGNUM
;
11141 arm_insn_r
->reg_rec_count
= 1;
11143 else if (3 == insn_op1
)
11145 /* SPSR is going to be changed. */
11146 /* we need to get SPSR value, which is yet to be done */
11147 printf_unfiltered (_("Process record does not support "
11148 "instruction 0x%0x at address %s.\n"),
11149 arm_insn_r
->arm_insn
,
11150 paddress (arm_insn_r
->gdbarch
,
11151 arm_insn_r
->this_addr
));
11157 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
11158 opcode2
= bits (arm_insn_r
->arm_insn
, 20, 24);
11159 insn_op1
= bits (arm_insn_r
->arm_insn
, 5, 6);
11161 /* Handle load/store insn extension space. */
11163 if (!opcode1
&& bit (arm_insn_r
->arm_insn
, 7)
11164 && bit (arm_insn_r
->arm_insn
, 4) && 1 != arm_insn_r
->cond
11165 && !INSN_RECORDED(arm_insn_r
))
11170 /* These insn, changes register and memory as well. */
11171 /* SWP or SWPB insn. */
11172 /* Get memory address given by Rn. */
11173 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11174 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11175 /* SWP insn ?, swaps word. */
11176 if (8 == arm_insn_r
->opcode
)
11178 record_buf_mem
[0] = 4;
11182 /* SWPB insn, swaps only byte. */
11183 record_buf_mem
[0] = 1;
11185 record_buf_mem
[1] = u_regval
;
11186 arm_insn_r
->mem_rec_count
= 1;
11187 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11188 arm_insn_r
->reg_rec_count
= 1;
11190 else if (1 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
11193 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11196 else if (2 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
11199 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11200 record_buf
[1] = record_buf
[0] + 1;
11201 arm_insn_r
->reg_rec_count
= 2;
11203 else if (3 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
11206 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11209 else if (bit (arm_insn_r
->arm_insn
, 20) && insn_op1
<= 3)
11211 /* LDRH, LDRSB, LDRSH. */
11212 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11213 arm_insn_r
->reg_rec_count
= 1;
11218 opcode1
= bits (arm_insn_r
->arm_insn
, 23, 27);
11219 if (24 == opcode1
&& bit (arm_insn_r
->arm_insn
, 21)
11220 && !INSN_RECORDED(arm_insn_r
))
11223 /* Handle coprocessor insn extension space. */
11226 /* To be done for ARMv5 and later; as of now we return -1. */
11228 printf_unfiltered (_("Process record does not support instruction x%0x "
11229 "at address %s.\n"),arm_insn_r
->arm_insn
,
11230 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11233 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11234 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11239 /* Handling opcode 000 insns. */
11242 arm_record_data_proc_misc_ld_str (insn_decode_record
*arm_insn_r
)
11244 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11245 uint32_t record_buf
[8], record_buf_mem
[8];
11246 ULONGEST u_regval
[2] = {0};
11248 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
11249 uint32_t immed_high
= 0, immed_low
= 0, offset_8
= 0, tgt_mem_addr
= 0;
11250 uint32_t opcode1
= 0;
11252 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11253 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11254 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
11256 /* Data processing insn /multiply insn. */
11257 if (9 == arm_insn_r
->decode
11258 && ((4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
11259 || (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)))
11261 /* Handle multiply instructions. */
11262 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
11263 if (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)
11265 /* Handle MLA and MUL. */
11266 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
11267 record_buf
[1] = ARM_PS_REGNUM
;
11268 arm_insn_r
->reg_rec_count
= 2;
11270 else if (4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
11272 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
11273 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
11274 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
11275 record_buf
[2] = ARM_PS_REGNUM
;
11276 arm_insn_r
->reg_rec_count
= 3;
11279 else if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
11280 && (11 == arm_insn_r
->decode
|| 13 == arm_insn_r
->decode
))
11282 /* Handle misc load insns, as 20th bit (L = 1). */
11283 /* LDR insn has a capability to do branching, if
11284 MOV LR, PC is precceded by LDR insn having Rn as R15
11285 in that case, it emulates branch and link insn, and hence we
11286 need to save CSPR and PC as well. I am not sure this is right
11287 place; as opcode = 010 LDR insn make this happen, if R15 was
11289 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11290 if (15 != reg_dest
)
11292 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11293 arm_insn_r
->reg_rec_count
= 1;
11297 record_buf
[0] = reg_dest
;
11298 record_buf
[1] = ARM_PS_REGNUM
;
11299 arm_insn_r
->reg_rec_count
= 2;
11302 else if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
11303 && sbo_sbz (arm_insn_r
->arm_insn
, 5, 12, 0)
11304 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
11305 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21))
11307 /* Handle MSR insn. */
11308 if (9 == arm_insn_r
->opcode
)
11310 /* CSPR is going to be changed. */
11311 record_buf
[0] = ARM_PS_REGNUM
;
11312 arm_insn_r
->reg_rec_count
= 1;
11316 /* SPSR is going to be changed. */
11317 /* How to read SPSR value? */
11318 printf_unfiltered (_("Process record does not support instruction "
11319 "0x%0x at address %s.\n"),
11320 arm_insn_r
->arm_insn
,
11321 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11325 else if (9 == arm_insn_r
->decode
11326 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
11327 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11329 /* Handling SWP, SWPB. */
11330 /* These insn, changes register and memory as well. */
11331 /* SWP or SWPB insn. */
11333 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11334 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11335 /* SWP insn ?, swaps word. */
11336 if (8 == arm_insn_r
->opcode
)
11338 record_buf_mem
[0] = 4;
11342 /* SWPB insn, swaps only byte. */
11343 record_buf_mem
[0] = 1;
11345 record_buf_mem
[1] = u_regval
[0];
11346 arm_insn_r
->mem_rec_count
= 1;
11347 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11348 arm_insn_r
->reg_rec_count
= 1;
11350 else if (3 == arm_insn_r
->decode
&& 0x12 == opcode1
11351 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
11353 /* Handle BLX, branch and link/exchange. */
11354 if (9 == arm_insn_r
->opcode
)
11356 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
11357 and R14 stores the return address. */
11358 record_buf
[0] = ARM_PS_REGNUM
;
11359 record_buf
[1] = ARM_LR_REGNUM
;
11360 arm_insn_r
->reg_rec_count
= 2;
11363 else if (7 == arm_insn_r
->decode
&& 0x12 == opcode1
)
11365 /* Handle enhanced software breakpoint insn, BKPT. */
11366 /* CPSR is changed to be executed in ARM state, disabling normal
11367 interrupts, entering abort mode. */
11368 /* According to high vector configuration PC is set. */
11369 /* user hit breakpoint and type reverse, in
11370 that case, we need to go back with previous CPSR and
11371 Program Counter. */
11372 record_buf
[0] = ARM_PS_REGNUM
;
11373 record_buf
[1] = ARM_LR_REGNUM
;
11374 arm_insn_r
->reg_rec_count
= 2;
11376 /* Save SPSR also; how? */
11377 printf_unfiltered (_("Process record does not support instruction "
11378 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11379 paddress (arm_insn_r
->gdbarch
,
11380 arm_insn_r
->this_addr
));
11383 else if (11 == arm_insn_r
->decode
11384 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11386 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
11388 /* Handle str(x) insn */
11389 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11392 else if (1 == arm_insn_r
->decode
&& 0x12 == opcode1
11393 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
11395 /* Handle BX, branch and link/exchange. */
11396 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
11397 record_buf
[0] = ARM_PS_REGNUM
;
11398 arm_insn_r
->reg_rec_count
= 1;
11400 else if (1 == arm_insn_r
->decode
&& 0x16 == opcode1
11401 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 4, 1)
11402 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1))
11404 /* Count leading zeros: CLZ. */
11405 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11406 arm_insn_r
->reg_rec_count
= 1;
11408 else if (!bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
11409 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
11410 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1)
11411 && sbo_sbz (arm_insn_r
->arm_insn
, 1, 12, 0)
11414 /* Handle MRS insn. */
11415 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11416 arm_insn_r
->reg_rec_count
= 1;
11418 else if (arm_insn_r
->opcode
<= 15)
11420 /* Normal data processing insns. */
11421 /* Out of 11 shifter operands mode, all the insn modifies destination
11422 register, which is specified by 13-16 decode. */
11423 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11424 record_buf
[1] = ARM_PS_REGNUM
;
11425 arm_insn_r
->reg_rec_count
= 2;
11432 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11433 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11437 /* Handling opcode 001 insns. */
11440 arm_record_data_proc_imm (insn_decode_record
*arm_insn_r
)
11442 uint32_t record_buf
[8], record_buf_mem
[8];
11444 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11445 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11447 if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
11448 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21)
11449 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
11452 /* Handle MSR insn. */
11453 if (9 == arm_insn_r
->opcode
)
11455 /* CSPR is going to be changed. */
11456 record_buf
[0] = ARM_PS_REGNUM
;
11457 arm_insn_r
->reg_rec_count
= 1;
11461 /* SPSR is going to be changed. */
11464 else if (arm_insn_r
->opcode
<= 15)
11466 /* Normal data processing insns. */
11467 /* Out of 11 shifter operands mode, all the insn modifies destination
11468 register, which is specified by 13-16 decode. */
11469 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11470 record_buf
[1] = ARM_PS_REGNUM
;
11471 arm_insn_r
->reg_rec_count
= 2;
11478 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11479 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11483 /* Handle ARM mode instructions with opcode 010. */
11486 arm_record_ld_st_imm_offset (insn_decode_record
*arm_insn_r
)
11488 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11490 uint32_t reg_base
, reg_dest
;
11491 uint32_t offset_12
, tgt_mem_addr
;
11492 uint32_t record_buf
[8], record_buf_mem
[8];
11493 unsigned char wback
;
11496 /* Calculate wback. */
11497 wback
= (bit (arm_insn_r
->arm_insn
, 24) == 0)
11498 || (bit (arm_insn_r
->arm_insn
, 21) == 1);
11500 arm_insn_r
->reg_rec_count
= 0;
11501 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
11503 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11505 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
11508 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11509 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_dest
;
11511 /* The LDR instruction is capable of doing branching. If MOV LR, PC
11512 preceeds a LDR instruction having R15 as reg_base, it
11513 emulates a branch and link instruction, and hence we need to save
11514 CPSR and PC as well. */
11515 if (ARM_PC_REGNUM
== reg_dest
)
11516 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
11518 /* If wback is true, also save the base register, which is going to be
11521 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11525 /* STR (immediate), STRB (immediate), STRBT and STRT. */
11527 offset_12
= bits (arm_insn_r
->arm_insn
, 0, 11);
11528 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
11530 /* Handle bit U. */
11531 if (bit (arm_insn_r
->arm_insn
, 23))
11533 /* U == 1: Add the offset. */
11534 tgt_mem_addr
= (uint32_t) u_regval
+ offset_12
;
11538 /* U == 0: subtract the offset. */
11539 tgt_mem_addr
= (uint32_t) u_regval
- offset_12
;
11542 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
11544 if (bit (arm_insn_r
->arm_insn
, 22))
11546 /* STRB and STRBT: 1 byte. */
11547 record_buf_mem
[0] = 1;
11551 /* STR and STRT: 4 bytes. */
11552 record_buf_mem
[0] = 4;
11555 /* Handle bit P. */
11556 if (bit (arm_insn_r
->arm_insn
, 24))
11557 record_buf_mem
[1] = tgt_mem_addr
;
11559 record_buf_mem
[1] = (uint32_t) u_regval
;
11561 arm_insn_r
->mem_rec_count
= 1;
11563 /* If wback is true, also save the base register, which is going to be
11566 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11569 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11570 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11574 /* Handling opcode 011 insns. */
11577 arm_record_ld_st_reg_offset (insn_decode_record
*arm_insn_r
)
11579 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11581 uint32_t shift_imm
= 0;
11582 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
11583 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
11584 uint32_t record_buf
[8], record_buf_mem
[8];
11587 ULONGEST u_regval
[2];
11589 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11590 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11592 /* Handle enhanced store insns and LDRD DSP insn,
11593 order begins according to addressing modes for store insns
11597 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11599 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11600 /* LDR insn has a capability to do branching, if
11601 MOV LR, PC is precedded by LDR insn having Rn as R15
11602 in that case, it emulates branch and link insn, and hence we
11603 need to save CSPR and PC as well. */
11604 if (15 != reg_dest
)
11606 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11607 arm_insn_r
->reg_rec_count
= 1;
11611 record_buf
[0] = reg_dest
;
11612 record_buf
[1] = ARM_PS_REGNUM
;
11613 arm_insn_r
->reg_rec_count
= 2;
11618 if (! bits (arm_insn_r
->arm_insn
, 4, 11))
11620 /* Store insn, register offset and register pre-indexed,
11621 register post-indexed. */
11623 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
11625 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11626 regcache_raw_read_unsigned (reg_cache
, reg_src1
11628 regcache_raw_read_unsigned (reg_cache
, reg_src2
11630 if (15 == reg_src2
)
11632 /* If R15 was used as Rn, hence current PC+8. */
11633 /* Pre-indexed mode doesnt reach here ; illegal insn. */
11634 u_regval
[0] = u_regval
[0] + 8;
11636 /* Calculate target store address, Rn +/- Rm, register offset. */
11638 if (bit (arm_insn_r
->arm_insn
, 23))
11640 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
11644 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
11647 switch (arm_insn_r
->opcode
)
11661 record_buf_mem
[0] = 4;
11676 record_buf_mem
[0] = 1;
11680 gdb_assert_not_reached ("no decoding pattern found");
11683 record_buf_mem
[1] = tgt_mem_addr
;
11684 arm_insn_r
->mem_rec_count
= 1;
11686 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
11687 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
11688 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
11689 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
11690 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
11691 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
11694 /* Rn is going to be changed in pre-indexed mode and
11695 post-indexed mode as well. */
11696 record_buf
[0] = reg_src2
;
11697 arm_insn_r
->reg_rec_count
= 1;
11702 /* Store insn, scaled register offset; scaled pre-indexed. */
11703 offset_12
= bits (arm_insn_r
->arm_insn
, 5, 6);
11705 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
11707 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11708 /* Get shift_imm. */
11709 shift_imm
= bits (arm_insn_r
->arm_insn
, 7, 11);
11710 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11711 regcache_raw_read_signed (reg_cache
, reg_src1
, &s_word
);
11712 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11713 /* Offset_12 used as shift. */
11717 /* Offset_12 used as index. */
11718 offset_12
= u_regval
[0] << shift_imm
;
11722 offset_12
= (!shift_imm
)?0:u_regval
[0] >> shift_imm
;
11728 if (bit (u_regval
[0], 31))
11730 offset_12
= 0xFFFFFFFF;
11739 /* This is arithmetic shift. */
11740 offset_12
= s_word
>> shift_imm
;
11747 regcache_raw_read_unsigned (reg_cache
, ARM_PS_REGNUM
,
11749 /* Get C flag value and shift it by 31. */
11750 offset_12
= (((bit (u_regval
[1], 29)) << 31) \
11751 | (u_regval
[0]) >> 1);
11755 offset_12
= (u_regval
[0] >> shift_imm
) \
11757 (sizeof(uint32_t) - shift_imm
));
11762 gdb_assert_not_reached ("no decoding pattern found");
11766 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11768 if (bit (arm_insn_r
->arm_insn
, 23))
11770 tgt_mem_addr
= u_regval
[1] + offset_12
;
11774 tgt_mem_addr
= u_regval
[1] - offset_12
;
11777 switch (arm_insn_r
->opcode
)
11791 record_buf_mem
[0] = 4;
11806 record_buf_mem
[0] = 1;
11810 gdb_assert_not_reached ("no decoding pattern found");
11813 record_buf_mem
[1] = tgt_mem_addr
;
11814 arm_insn_r
->mem_rec_count
= 1;
11816 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
11817 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
11818 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
11819 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
11820 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
11821 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
11824 /* Rn is going to be changed in register scaled pre-indexed
11825 mode,and scaled post indexed mode. */
11826 record_buf
[0] = reg_src2
;
11827 arm_insn_r
->reg_rec_count
= 1;
11832 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11833 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11837 /* Handle ARM mode instructions with opcode 100. */
11840 arm_record_ld_st_multiple (insn_decode_record
*arm_insn_r
)
11842 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11843 uint32_t register_count
= 0, register_bits
;
11844 uint32_t reg_base
, addr_mode
;
11845 uint32_t record_buf
[24], record_buf_mem
[48];
11849 /* Fetch the list of registers. */
11850 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
11851 arm_insn_r
->reg_rec_count
= 0;
11853 /* Fetch the base register that contains the address we are loading data
11855 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
11857 /* Calculate wback. */
11858 wback
= (bit (arm_insn_r
->arm_insn
, 21) == 1);
11860 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11862 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
11864 /* Find out which registers are going to be loaded from memory. */
11865 while (register_bits
)
11867 if (register_bits
& 0x00000001)
11868 record_buf
[arm_insn_r
->reg_rec_count
++] = register_count
;
11869 register_bits
= register_bits
>> 1;
11874 /* If wback is true, also save the base register, which is going to be
11877 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11879 /* Save the CPSR register. */
11880 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
11884 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
11886 addr_mode
= bits (arm_insn_r
->arm_insn
, 23, 24);
11888 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
11890 /* Find out how many registers are going to be stored to memory. */
11891 while (register_bits
)
11893 if (register_bits
& 0x00000001)
11895 register_bits
= register_bits
>> 1;
11900 /* STMDA (STMED): Decrement after. */
11902 record_buf_mem
[1] = (uint32_t) u_regval
11903 - register_count
* INT_REGISTER_SIZE
+ 4;
11905 /* STM (STMIA, STMEA): Increment after. */
11907 record_buf_mem
[1] = (uint32_t) u_regval
;
11909 /* STMDB (STMFD): Decrement before. */
11911 record_buf_mem
[1] = (uint32_t) u_regval
11912 - register_count
* INT_REGISTER_SIZE
;
11914 /* STMIB (STMFA): Increment before. */
11916 record_buf_mem
[1] = (uint32_t) u_regval
+ INT_REGISTER_SIZE
;
11919 gdb_assert_not_reached ("no decoding pattern found");
11923 record_buf_mem
[0] = register_count
* INT_REGISTER_SIZE
;
11924 arm_insn_r
->mem_rec_count
= 1;
11926 /* If wback is true, also save the base register, which is going to be
11929 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11932 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11933 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11937 /* Handling opcode 101 insns. */
11940 arm_record_b_bl (insn_decode_record
*arm_insn_r
)
11942 uint32_t record_buf
[8];
11944 /* Handle B, BL, BLX(1) insns. */
11945 /* B simply branches so we do nothing here. */
11946 /* Note: BLX(1) doesnt fall here but instead it falls into
11947 extension space. */
11948 if (bit (arm_insn_r
->arm_insn
, 24))
11950 record_buf
[0] = ARM_LR_REGNUM
;
11951 arm_insn_r
->reg_rec_count
= 1;
11954 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11959 /* Handling opcode 110 insns. */
11962 arm_record_unsupported_insn (insn_decode_record
*arm_insn_r
)
11964 printf_unfiltered (_("Process record does not support instruction "
11965 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11966 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11971 /* Record handler for vector data transfer instructions. */
11974 arm_record_vdata_transfer_insn (insn_decode_record
*arm_insn_r
)
11976 uint32_t bits_a
, bit_c
, bit_l
, reg_t
, reg_v
;
11977 uint32_t record_buf
[4];
11979 const int num_regs
= gdbarch_num_regs (arm_insn_r
->gdbarch
);
11980 reg_t
= bits (arm_insn_r
->arm_insn
, 12, 15);
11981 reg_v
= bits (arm_insn_r
->arm_insn
, 21, 23);
11982 bits_a
= bits (arm_insn_r
->arm_insn
, 21, 23);
11983 bit_l
= bit (arm_insn_r
->arm_insn
, 20);
11984 bit_c
= bit (arm_insn_r
->arm_insn
, 8);
11986 /* Handle VMOV instruction. */
11987 if (bit_l
&& bit_c
)
11989 record_buf
[0] = reg_t
;
11990 arm_insn_r
->reg_rec_count
= 1;
11992 else if (bit_l
&& !bit_c
)
11994 /* Handle VMOV instruction. */
11995 if (bits_a
== 0x00)
11997 if (bit (arm_insn_r
->arm_insn
, 20))
11998 record_buf
[0] = reg_t
;
12000 record_buf
[0] = num_regs
+ (bit (arm_insn_r
->arm_insn
, 7) |
12003 arm_insn_r
->reg_rec_count
= 1;
12005 /* Handle VMRS instruction. */
12006 else if (bits_a
== 0x07)
12009 reg_t
= ARM_PS_REGNUM
;
12011 record_buf
[0] = reg_t
;
12012 arm_insn_r
->reg_rec_count
= 1;
12015 else if (!bit_l
&& !bit_c
)
12017 /* Handle VMOV instruction. */
12018 if (bits_a
== 0x00)
12020 if (bit (arm_insn_r
->arm_insn
, 20))
12021 record_buf
[0] = reg_t
;
12023 record_buf
[0] = num_regs
+ (bit (arm_insn_r
->arm_insn
, 7) |
12026 arm_insn_r
->reg_rec_count
= 1;
12028 /* Handle VMSR instruction. */
12029 else if (bits_a
== 0x07)
12031 record_buf
[0] = ARM_FPSCR_REGNUM
;
12032 arm_insn_r
->reg_rec_count
= 1;
12035 else if (!bit_l
&& bit_c
)
12037 /* Handle VMOV instruction. */
12038 if (!(bits_a
& 0x04))
12040 record_buf
[0] = (reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4))
12042 arm_insn_r
->reg_rec_count
= 1;
12044 /* Handle VDUP instruction. */
12047 if (bit (arm_insn_r
->arm_insn
, 21))
12049 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
12050 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
12051 record_buf
[1] = reg_v
+ ARM_D0_REGNUM
+ 1;
12052 arm_insn_r
->reg_rec_count
= 2;
12056 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
12057 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
12058 arm_insn_r
->reg_rec_count
= 1;
12063 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
12067 /* Record handler for extension register load/store instructions. */
12070 arm_record_exreg_ld_st_insn (insn_decode_record
*arm_insn_r
)
12072 uint32_t opcode
, single_reg
;
12073 uint8_t op_vldm_vstm
;
12074 uint32_t record_buf
[8], record_buf_mem
[128];
12075 ULONGEST u_regval
= 0;
12077 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
12078 const int num_regs
= gdbarch_num_regs (arm_insn_r
->gdbarch
);
12080 opcode
= bits (arm_insn_r
->arm_insn
, 20, 24);
12081 single_reg
= bit (arm_insn_r
->arm_insn
, 8);
12082 op_vldm_vstm
= opcode
& 0x1b;
12084 /* Handle VMOV instructions. */
12085 if ((opcode
& 0x1e) == 0x04)
12087 if (bit (arm_insn_r
->arm_insn
, 4))
12089 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
12090 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
12091 arm_insn_r
->reg_rec_count
= 2;
12095 uint8_t reg_m
= (bits (arm_insn_r
->arm_insn
, 0, 3) << 1)
12096 | bit (arm_insn_r
->arm_insn
, 5);
12100 record_buf
[0] = num_regs
+ reg_m
;
12101 record_buf
[1] = num_regs
+ reg_m
+ 1;
12102 arm_insn_r
->reg_rec_count
= 2;
12106 record_buf
[0] = reg_m
+ ARM_D0_REGNUM
;
12107 arm_insn_r
->reg_rec_count
= 1;
12111 /* Handle VSTM and VPUSH instructions. */
12112 else if (op_vldm_vstm
== 0x08 || op_vldm_vstm
== 0x0a
12113 || op_vldm_vstm
== 0x12)
12115 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
12116 uint32_t memory_index
= 0;
12118 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
12119 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12120 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
12121 imm_off32
= imm_off8
<< 24;
12122 memory_count
= imm_off8
;
12124 if (bit (arm_insn_r
->arm_insn
, 23))
12125 start_address
= u_regval
;
12127 start_address
= u_regval
- imm_off32
;
12129 if (bit (arm_insn_r
->arm_insn
, 21))
12131 record_buf
[0] = reg_rn
;
12132 arm_insn_r
->reg_rec_count
= 1;
12135 while (memory_count
> 0)
12139 record_buf_mem
[memory_index
] = start_address
;
12140 record_buf_mem
[memory_index
+ 1] = 4;
12141 start_address
= start_address
+ 4;
12142 memory_index
= memory_index
+ 2;
12146 record_buf_mem
[memory_index
] = start_address
;
12147 record_buf_mem
[memory_index
+ 1] = 4;
12148 record_buf_mem
[memory_index
+ 2] = start_address
+ 4;
12149 record_buf_mem
[memory_index
+ 3] = 4;
12150 start_address
= start_address
+ 8;
12151 memory_index
= memory_index
+ 4;
12155 arm_insn_r
->mem_rec_count
= (memory_index
>> 1);
12157 /* Handle VLDM instructions. */
12158 else if (op_vldm_vstm
== 0x09 || op_vldm_vstm
== 0x0b
12159 || op_vldm_vstm
== 0x13)
12161 uint32_t reg_count
, reg_vd
;
12162 uint32_t reg_index
= 0;
12164 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
12165 reg_count
= bits (arm_insn_r
->arm_insn
, 0, 7);
12168 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
12170 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
12172 if (bit (arm_insn_r
->arm_insn
, 21))
12173 record_buf
[reg_index
++] = bits (arm_insn_r
->arm_insn
, 16, 19);
12175 while (reg_count
> 0)
12178 record_buf
[reg_index
++] = num_regs
+ reg_vd
+ reg_count
- 1;
12180 record_buf
[reg_index
++] = ARM_D0_REGNUM
+ reg_vd
+ reg_count
- 1;
12184 arm_insn_r
->reg_rec_count
= reg_index
;
12186 /* VSTR Vector store register. */
12187 else if ((opcode
& 0x13) == 0x10)
12189 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
12190 uint32_t memory_index
= 0;
12192 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
12193 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12194 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
12195 imm_off32
= imm_off8
<< 24;
12196 memory_count
= imm_off8
;
12198 if (bit (arm_insn_r
->arm_insn
, 23))
12199 start_address
= u_regval
+ imm_off32
;
12201 start_address
= u_regval
- imm_off32
;
12205 record_buf_mem
[memory_index
] = start_address
;
12206 record_buf_mem
[memory_index
+ 1] = 4;
12207 arm_insn_r
->mem_rec_count
= 1;
12211 record_buf_mem
[memory_index
] = start_address
;
12212 record_buf_mem
[memory_index
+ 1] = 4;
12213 record_buf_mem
[memory_index
+ 2] = start_address
+ 4;
12214 record_buf_mem
[memory_index
+ 3] = 4;
12215 arm_insn_r
->mem_rec_count
= 2;
12218 /* VLDR Vector load register. */
12219 else if ((opcode
& 0x13) == 0x11)
12221 uint32_t reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
12225 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
12226 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
;
12230 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
12231 record_buf
[0] = num_regs
+ reg_vd
;
12233 arm_insn_r
->reg_rec_count
= 1;
12236 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
12237 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
12241 /* Record handler for arm/thumb mode VFP data processing instructions. */
12244 arm_record_vfp_data_proc_insn (insn_decode_record
*arm_insn_r
)
12246 uint32_t opc1
, opc2
, opc3
, dp_op_sz
, bit_d
, reg_vd
;
12247 uint32_t record_buf
[4];
12248 enum insn_types
{INSN_T0
, INSN_T1
, INSN_T2
, INSN_T3
, INSN_INV
};
12249 enum insn_types curr_insn_type
= INSN_INV
;
12251 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
12252 opc1
= bits (arm_insn_r
->arm_insn
, 20, 23);
12253 opc2
= bits (arm_insn_r
->arm_insn
, 16, 19);
12254 opc3
= bits (arm_insn_r
->arm_insn
, 6, 7);
12255 dp_op_sz
= bit (arm_insn_r
->arm_insn
, 8);
12256 bit_d
= bit (arm_insn_r
->arm_insn
, 22);
12257 opc1
= opc1
& 0x04;
12259 /* Handle VMLA, VMLS. */
12262 if (bit (arm_insn_r
->arm_insn
, 10))
12264 if (bit (arm_insn_r
->arm_insn
, 6))
12265 curr_insn_type
= INSN_T0
;
12267 curr_insn_type
= INSN_T1
;
12272 curr_insn_type
= INSN_T1
;
12274 curr_insn_type
= INSN_T2
;
12277 /* Handle VNMLA, VNMLS, VNMUL. */
12278 else if (opc1
== 0x01)
12281 curr_insn_type
= INSN_T1
;
12283 curr_insn_type
= INSN_T2
;
12286 else if (opc1
== 0x02 && !(opc3
& 0x01))
12288 if (bit (arm_insn_r
->arm_insn
, 10))
12290 if (bit (arm_insn_r
->arm_insn
, 6))
12291 curr_insn_type
= INSN_T0
;
12293 curr_insn_type
= INSN_T1
;
12298 curr_insn_type
= INSN_T1
;
12300 curr_insn_type
= INSN_T2
;
12303 /* Handle VADD, VSUB. */
12304 else if (opc1
== 0x03)
12306 if (!bit (arm_insn_r
->arm_insn
, 9))
12308 if (bit (arm_insn_r
->arm_insn
, 6))
12309 curr_insn_type
= INSN_T0
;
12311 curr_insn_type
= INSN_T1
;
12316 curr_insn_type
= INSN_T1
;
12318 curr_insn_type
= INSN_T2
;
12322 else if (opc1
== 0x0b)
12325 curr_insn_type
= INSN_T1
;
12327 curr_insn_type
= INSN_T2
;
12329 /* Handle all other vfp data processing instructions. */
12330 else if (opc1
== 0x0b)
12333 if (!(opc3
& 0x01) || (opc2
== 0x00 && opc3
== 0x01))
12335 if (bit (arm_insn_r
->arm_insn
, 4))
12337 if (bit (arm_insn_r
->arm_insn
, 6))
12338 curr_insn_type
= INSN_T0
;
12340 curr_insn_type
= INSN_T1
;
12345 curr_insn_type
= INSN_T1
;
12347 curr_insn_type
= INSN_T2
;
12350 /* Handle VNEG and VABS. */
12351 else if ((opc2
== 0x01 && opc3
== 0x01)
12352 || (opc2
== 0x00 && opc3
== 0x03))
12354 if (!bit (arm_insn_r
->arm_insn
, 11))
12356 if (bit (arm_insn_r
->arm_insn
, 6))
12357 curr_insn_type
= INSN_T0
;
12359 curr_insn_type
= INSN_T1
;
12364 curr_insn_type
= INSN_T1
;
12366 curr_insn_type
= INSN_T2
;
12369 /* Handle VSQRT. */
12370 else if (opc2
== 0x01 && opc3
== 0x03)
12373 curr_insn_type
= INSN_T1
;
12375 curr_insn_type
= INSN_T2
;
12378 else if (opc2
== 0x07 && opc3
== 0x03)
12381 curr_insn_type
= INSN_T1
;
12383 curr_insn_type
= INSN_T2
;
12385 else if (opc3
& 0x01)
12388 if ((opc2
== 0x08) || (opc2
& 0x0e) == 0x0c)
12390 if (!bit (arm_insn_r
->arm_insn
, 18))
12391 curr_insn_type
= INSN_T2
;
12395 curr_insn_type
= INSN_T1
;
12397 curr_insn_type
= INSN_T2
;
12401 else if ((opc2
& 0x0e) == 0x0a || (opc2
& 0x0e) == 0x0e)
12404 curr_insn_type
= INSN_T1
;
12406 curr_insn_type
= INSN_T2
;
12408 /* Handle VCVTB, VCVTT. */
12409 else if ((opc2
& 0x0e) == 0x02)
12410 curr_insn_type
= INSN_T2
;
12411 /* Handle VCMP, VCMPE. */
12412 else if ((opc2
& 0x0e) == 0x04)
12413 curr_insn_type
= INSN_T3
;
12417 switch (curr_insn_type
)
12420 reg_vd
= reg_vd
| (bit_d
<< 4);
12421 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
12422 record_buf
[1] = reg_vd
+ ARM_D0_REGNUM
+ 1;
12423 arm_insn_r
->reg_rec_count
= 2;
12427 reg_vd
= reg_vd
| (bit_d
<< 4);
12428 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
12429 arm_insn_r
->reg_rec_count
= 1;
12433 reg_vd
= (reg_vd
<< 1) | bit_d
;
12434 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
12435 arm_insn_r
->reg_rec_count
= 1;
12439 record_buf
[0] = ARM_FPSCR_REGNUM
;
12440 arm_insn_r
->reg_rec_count
= 1;
12444 gdb_assert_not_reached ("no decoding pattern found");
12448 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
12452 /* Handling opcode 110 insns. */
12455 arm_record_asimd_vfp_coproc (insn_decode_record
*arm_insn_r
)
12457 uint32_t op
, op1
, op1_sbit
, op1_ebit
, coproc
;
12459 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
12460 op1
= bits (arm_insn_r
->arm_insn
, 20, 25);
12461 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
12463 if ((coproc
& 0x0e) == 0x0a)
12465 /* Handle extension register ld/st instructions. */
12467 return arm_record_exreg_ld_st_insn (arm_insn_r
);
12469 /* 64-bit transfers between arm core and extension registers. */
12470 if ((op1
& 0x3e) == 0x04)
12471 return arm_record_exreg_ld_st_insn (arm_insn_r
);
12475 /* Handle coprocessor ld/st instructions. */
12480 return arm_record_unsupported_insn (arm_insn_r
);
12483 return arm_record_unsupported_insn (arm_insn_r
);
12486 /* Move to coprocessor from two arm core registers. */
12488 return arm_record_unsupported_insn (arm_insn_r
);
12490 /* Move to two arm core registers from coprocessor. */
12495 reg_t
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
12496 reg_t
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
12497 arm_insn_r
->reg_rec_count
= 2;
12499 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, reg_t
);
12503 return arm_record_unsupported_insn (arm_insn_r
);
12506 /* Handling opcode 111 insns. */
12509 arm_record_coproc_data_proc (insn_decode_record
*arm_insn_r
)
12511 uint32_t op
, op1_sbit
, op1_ebit
, coproc
;
12512 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arm_insn_r
->gdbarch
);
12513 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
12514 ULONGEST u_regval
= 0;
12516 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 24, 27);
12517 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
12518 op1_sbit
= bit (arm_insn_r
->arm_insn
, 24);
12519 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
12520 op
= bit (arm_insn_r
->arm_insn
, 4);
12522 /* Handle arm SWI/SVC system call instructions. */
12525 if (tdep
->arm_syscall_record
!= NULL
)
12527 ULONGEST svc_operand
, svc_number
;
12529 svc_operand
= (0x00ffffff & arm_insn_r
->arm_insn
);
12531 if (svc_operand
) /* OABI. */
12532 svc_number
= svc_operand
- 0x900000;
12534 regcache_raw_read_unsigned (reg_cache
, 7, &svc_number
);
12536 return tdep
->arm_syscall_record (reg_cache
, svc_number
);
12540 printf_unfiltered (_("no syscall record support\n"));
12545 if ((coproc
& 0x0e) == 0x0a)
12547 /* VFP data-processing instructions. */
12548 if (!op1_sbit
&& !op
)
12549 return arm_record_vfp_data_proc_insn (arm_insn_r
);
12551 /* Advanced SIMD, VFP instructions. */
12552 if (!op1_sbit
&& op
)
12553 return arm_record_vdata_transfer_insn (arm_insn_r
);
12557 /* Coprocessor data operations. */
12558 if (!op1_sbit
&& !op
)
12559 return arm_record_unsupported_insn (arm_insn_r
);
12561 /* Move to Coprocessor from ARM core register. */
12562 if (!op1_sbit
&& !op1_ebit
&& op
)
12563 return arm_record_unsupported_insn (arm_insn_r
);
12565 /* Move to arm core register from coprocessor. */
12566 if (!op1_sbit
&& op1_ebit
&& op
)
12568 uint32_t record_buf
[1];
12570 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
12571 if (record_buf
[0] == 15)
12572 record_buf
[0] = ARM_PS_REGNUM
;
12574 arm_insn_r
->reg_rec_count
= 1;
12575 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
,
12581 return arm_record_unsupported_insn (arm_insn_r
);
12584 /* Handling opcode 000 insns. */
12587 thumb_record_shift_add_sub (insn_decode_record
*thumb_insn_r
)
12589 uint32_t record_buf
[8];
12590 uint32_t reg_src1
= 0;
12592 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12594 record_buf
[0] = ARM_PS_REGNUM
;
12595 record_buf
[1] = reg_src1
;
12596 thumb_insn_r
->reg_rec_count
= 2;
12598 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12604 /* Handling opcode 001 insns. */
12607 thumb_record_add_sub_cmp_mov (insn_decode_record
*thumb_insn_r
)
12609 uint32_t record_buf
[8];
12610 uint32_t reg_src1
= 0;
12612 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12614 record_buf
[0] = ARM_PS_REGNUM
;
12615 record_buf
[1] = reg_src1
;
12616 thumb_insn_r
->reg_rec_count
= 2;
12618 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12623 /* Handling opcode 010 insns. */
12626 thumb_record_ld_st_reg_offset (insn_decode_record
*thumb_insn_r
)
12628 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12629 uint32_t record_buf
[8], record_buf_mem
[8];
12631 uint32_t reg_src1
= 0, reg_src2
= 0;
12632 uint32_t opcode1
= 0, opcode2
= 0, opcode3
= 0;
12634 ULONGEST u_regval
[2] = {0};
12636 opcode1
= bits (thumb_insn_r
->arm_insn
, 10, 12);
12638 if (bit (thumb_insn_r
->arm_insn
, 12))
12640 /* Handle load/store register offset. */
12641 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 10);
12642 if (opcode2
>= 12 && opcode2
<= 15)
12644 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
12645 reg_src1
= bits (thumb_insn_r
->arm_insn
,0, 2);
12646 record_buf
[0] = reg_src1
;
12647 thumb_insn_r
->reg_rec_count
= 1;
12649 else if (opcode2
>= 8 && opcode2
<= 10)
12651 /* STR(2), STRB(2), STRH(2) . */
12652 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12653 reg_src2
= bits (thumb_insn_r
->arm_insn
, 6, 8);
12654 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
12655 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
12657 record_buf_mem
[0] = 4; /* STR (2). */
12658 else if (10 == opcode2
)
12659 record_buf_mem
[0] = 1; /* STRB (2). */
12660 else if (9 == opcode2
)
12661 record_buf_mem
[0] = 2; /* STRH (2). */
12662 record_buf_mem
[1] = u_regval
[0] + u_regval
[1];
12663 thumb_insn_r
->mem_rec_count
= 1;
12666 else if (bit (thumb_insn_r
->arm_insn
, 11))
12668 /* Handle load from literal pool. */
12670 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12671 record_buf
[0] = reg_src1
;
12672 thumb_insn_r
->reg_rec_count
= 1;
12676 opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 9);
12677 opcode3
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12678 if ((3 == opcode2
) && (!opcode3
))
12680 /* Branch with exchange. */
12681 record_buf
[0] = ARM_PS_REGNUM
;
12682 thumb_insn_r
->reg_rec_count
= 1;
12686 /* Format 8; special data processing insns. */
12687 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12688 record_buf
[0] = ARM_PS_REGNUM
;
12689 record_buf
[1] = reg_src1
;
12690 thumb_insn_r
->reg_rec_count
= 2;
12695 /* Format 5; data processing insns. */
12696 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12697 if (bit (thumb_insn_r
->arm_insn
, 7))
12699 reg_src1
= reg_src1
+ 8;
12701 record_buf
[0] = ARM_PS_REGNUM
;
12702 record_buf
[1] = reg_src1
;
12703 thumb_insn_r
->reg_rec_count
= 2;
12706 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12707 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12713 /* Handling opcode 001 insns. */
12716 thumb_record_ld_st_imm_offset (insn_decode_record
*thumb_insn_r
)
12718 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12719 uint32_t record_buf
[8], record_buf_mem
[8];
12721 uint32_t reg_src1
= 0;
12722 uint32_t opcode
= 0, immed_5
= 0;
12724 ULONGEST u_regval
= 0;
12726 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12731 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12732 record_buf
[0] = reg_src1
;
12733 thumb_insn_r
->reg_rec_count
= 1;
12738 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12739 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
12740 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12741 record_buf_mem
[0] = 4;
12742 record_buf_mem
[1] = u_regval
+ (immed_5
* 4);
12743 thumb_insn_r
->mem_rec_count
= 1;
12746 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12747 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12753 /* Handling opcode 100 insns. */
12756 thumb_record_ld_st_stack (insn_decode_record
*thumb_insn_r
)
12758 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12759 uint32_t record_buf
[8], record_buf_mem
[8];
12761 uint32_t reg_src1
= 0;
12762 uint32_t opcode
= 0, immed_8
= 0, immed_5
= 0;
12764 ULONGEST u_regval
= 0;
12766 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12771 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12772 record_buf
[0] = reg_src1
;
12773 thumb_insn_r
->reg_rec_count
= 1;
12775 else if (1 == opcode
)
12778 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12779 record_buf
[0] = reg_src1
;
12780 thumb_insn_r
->reg_rec_count
= 1;
12782 else if (2 == opcode
)
12785 immed_8
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12786 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
12787 record_buf_mem
[0] = 4;
12788 record_buf_mem
[1] = u_regval
+ (immed_8
* 4);
12789 thumb_insn_r
->mem_rec_count
= 1;
12791 else if (0 == opcode
)
12794 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
12795 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12796 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12797 record_buf_mem
[0] = 2;
12798 record_buf_mem
[1] = u_regval
+ (immed_5
* 2);
12799 thumb_insn_r
->mem_rec_count
= 1;
12802 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12803 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12809 /* Handling opcode 101 insns. */
12812 thumb_record_misc (insn_decode_record
*thumb_insn_r
)
12814 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12816 uint32_t opcode
= 0, opcode1
= 0, opcode2
= 0;
12817 uint32_t register_bits
= 0, register_count
= 0;
12818 uint32_t register_list
[8] = {0}, index
= 0, start_address
= 0;
12819 uint32_t record_buf
[24], record_buf_mem
[48];
12822 ULONGEST u_regval
= 0;
12824 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12825 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12826 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 12);
12831 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12832 while (register_bits
)
12834 if (register_bits
& 0x00000001)
12835 record_buf
[index
++] = register_count
;
12836 register_bits
= register_bits
>> 1;
12839 record_buf
[index
++] = ARM_PS_REGNUM
;
12840 record_buf
[index
++] = ARM_SP_REGNUM
;
12841 thumb_insn_r
->reg_rec_count
= index
;
12843 else if (10 == opcode2
)
12846 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12847 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
12848 while (register_bits
)
12850 if (register_bits
& 0x00000001)
12852 register_bits
= register_bits
>> 1;
12854 start_address
= u_regval
- \
12855 (4 * (bit (thumb_insn_r
->arm_insn
, 8) + register_count
));
12856 thumb_insn_r
->mem_rec_count
= register_count
;
12857 while (register_count
)
12859 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12860 record_buf_mem
[(register_count
* 2) - 2] = 4;
12861 start_address
= start_address
+ 4;
12864 record_buf
[0] = ARM_SP_REGNUM
;
12865 thumb_insn_r
->reg_rec_count
= 1;
12867 else if (0x1E == opcode1
)
12870 /* Handle enhanced software breakpoint insn, BKPT. */
12871 /* CPSR is changed to be executed in ARM state, disabling normal
12872 interrupts, entering abort mode. */
12873 /* According to high vector configuration PC is set. */
12874 /* User hits breakpoint and type reverse, in that case, we need to go back with
12875 previous CPSR and Program Counter. */
12876 record_buf
[0] = ARM_PS_REGNUM
;
12877 record_buf
[1] = ARM_LR_REGNUM
;
12878 thumb_insn_r
->reg_rec_count
= 2;
12879 /* We need to save SPSR value, which is not yet done. */
12880 printf_unfiltered (_("Process record does not support instruction "
12881 "0x%0x at address %s.\n"),
12882 thumb_insn_r
->arm_insn
,
12883 paddress (thumb_insn_r
->gdbarch
,
12884 thumb_insn_r
->this_addr
));
12887 else if ((0 == opcode
) || (1 == opcode
))
12889 /* ADD(5), ADD(6). */
12890 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12891 record_buf
[0] = reg_src1
;
12892 thumb_insn_r
->reg_rec_count
= 1;
12894 else if (2 == opcode
)
12896 /* ADD(7), SUB(4). */
12897 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12898 record_buf
[0] = ARM_SP_REGNUM
;
12899 thumb_insn_r
->reg_rec_count
= 1;
12902 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12903 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12909 /* Handling opcode 110 insns. */
12912 thumb_record_ldm_stm_swi (insn_decode_record
*thumb_insn_r
)
12914 struct gdbarch_tdep
*tdep
= gdbarch_tdep (thumb_insn_r
->gdbarch
);
12915 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12917 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
12918 uint32_t reg_src1
= 0;
12919 uint32_t opcode1
= 0, opcode2
= 0, register_bits
= 0, register_count
= 0;
12920 uint32_t register_list
[8] = {0}, index
= 0, start_address
= 0;
12921 uint32_t record_buf
[24], record_buf_mem
[48];
12923 ULONGEST u_regval
= 0;
12925 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12926 opcode2
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12932 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12934 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12935 while (register_bits
)
12937 if (register_bits
& 0x00000001)
12938 record_buf
[index
++] = register_count
;
12939 register_bits
= register_bits
>> 1;
12942 record_buf
[index
++] = reg_src1
;
12943 thumb_insn_r
->reg_rec_count
= index
;
12945 else if (0 == opcode2
)
12947 /* It handles both STMIA. */
12948 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12950 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12951 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12952 while (register_bits
)
12954 if (register_bits
& 0x00000001)
12956 register_bits
= register_bits
>> 1;
12958 start_address
= u_regval
;
12959 thumb_insn_r
->mem_rec_count
= register_count
;
12960 while (register_count
)
12962 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12963 record_buf_mem
[(register_count
* 2) - 2] = 4;
12964 start_address
= start_address
+ 4;
12968 else if (0x1F == opcode1
)
12970 /* Handle arm syscall insn. */
12971 if (tdep
->arm_syscall_record
!= NULL
)
12973 regcache_raw_read_unsigned (reg_cache
, 7, &u_regval
);
12974 ret
= tdep
->arm_syscall_record (reg_cache
, u_regval
);
12978 printf_unfiltered (_("no syscall record support\n"));
12983 /* B (1), conditional branch is automatically taken care in process_record,
12984 as PC is saved there. */
12986 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12987 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12993 /* Handling opcode 111 insns. */
12996 thumb_record_branch (insn_decode_record
*thumb_insn_r
)
12998 uint32_t record_buf
[8];
12999 uint32_t bits_h
= 0;
13001 bits_h
= bits (thumb_insn_r
->arm_insn
, 11, 12);
13003 if (2 == bits_h
|| 3 == bits_h
)
13006 record_buf
[0] = ARM_LR_REGNUM
;
13007 thumb_insn_r
->reg_rec_count
= 1;
13009 else if (1 == bits_h
)
13012 record_buf
[0] = ARM_PS_REGNUM
;
13013 record_buf
[1] = ARM_LR_REGNUM
;
13014 thumb_insn_r
->reg_rec_count
= 2;
13017 /* B(2) is automatically taken care in process_record, as PC is
13020 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
13025 /* Handler for thumb2 load/store multiple instructions. */
13028 thumb2_record_ld_st_multiple (insn_decode_record
*thumb2_insn_r
)
13030 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13032 uint32_t reg_rn
, op
;
13033 uint32_t register_bits
= 0, register_count
= 0;
13034 uint32_t index
= 0, start_address
= 0;
13035 uint32_t record_buf
[24], record_buf_mem
[48];
13037 ULONGEST u_regval
= 0;
13039 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13040 op
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
13042 if (0 == op
|| 3 == op
)
13044 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
13046 /* Handle RFE instruction. */
13047 record_buf
[0] = ARM_PS_REGNUM
;
13048 thumb2_insn_r
->reg_rec_count
= 1;
13052 /* Handle SRS instruction after reading banked SP. */
13053 return arm_record_unsupported_insn (thumb2_insn_r
);
13056 else if (1 == op
|| 2 == op
)
13058 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
13060 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
13061 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
13062 while (register_bits
)
13064 if (register_bits
& 0x00000001)
13065 record_buf
[index
++] = register_count
;
13068 register_bits
= register_bits
>> 1;
13070 record_buf
[index
++] = reg_rn
;
13071 record_buf
[index
++] = ARM_PS_REGNUM
;
13072 thumb2_insn_r
->reg_rec_count
= index
;
13076 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
13077 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
13078 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
13079 while (register_bits
)
13081 if (register_bits
& 0x00000001)
13084 register_bits
= register_bits
>> 1;
13089 /* Start address calculation for LDMDB/LDMEA. */
13090 start_address
= u_regval
;
13094 /* Start address calculation for LDMDB/LDMEA. */
13095 start_address
= u_regval
- register_count
* 4;
13098 thumb2_insn_r
->mem_rec_count
= register_count
;
13099 while (register_count
)
13101 record_buf_mem
[register_count
* 2 - 1] = start_address
;
13102 record_buf_mem
[register_count
* 2 - 2] = 4;
13103 start_address
= start_address
+ 4;
13106 record_buf
[0] = reg_rn
;
13107 record_buf
[1] = ARM_PS_REGNUM
;
13108 thumb2_insn_r
->reg_rec_count
= 2;
13112 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13114 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13116 return ARM_RECORD_SUCCESS
;
13119 /* Handler for thumb2 load/store (dual/exclusive) and table branch
13123 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record
*thumb2_insn_r
)
13125 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13127 uint32_t reg_rd
, reg_rn
, offset_imm
;
13128 uint32_t reg_dest1
, reg_dest2
;
13129 uint32_t address
, offset_addr
;
13130 uint32_t record_buf
[8], record_buf_mem
[8];
13131 uint32_t op1
, op2
, op3
;
13134 ULONGEST u_regval
[2];
13136 op1
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
13137 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 21);
13138 op3
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
13140 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
13142 if(!(1 == op1
&& 1 == op2
&& (0 == op3
|| 1 == op3
)))
13144 reg_dest1
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
13145 record_buf
[0] = reg_dest1
;
13146 record_buf
[1] = ARM_PS_REGNUM
;
13147 thumb2_insn_r
->reg_rec_count
= 2;
13150 if (3 == op2
|| (op1
& 2) || (1 == op1
&& 1 == op2
&& 7 == op3
))
13152 reg_dest2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13153 record_buf
[2] = reg_dest2
;
13154 thumb2_insn_r
->reg_rec_count
= 3;
13159 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13160 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
13162 if (0 == op1
&& 0 == op2
)
13164 /* Handle STREX. */
13165 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
13166 address
= u_regval
[0] + (offset_imm
* 4);
13167 record_buf_mem
[0] = 4;
13168 record_buf_mem
[1] = address
;
13169 thumb2_insn_r
->mem_rec_count
= 1;
13170 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
13171 record_buf
[0] = reg_rd
;
13172 thumb2_insn_r
->reg_rec_count
= 1;
13174 else if (1 == op1
&& 0 == op2
)
13176 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
13177 record_buf
[0] = reg_rd
;
13178 thumb2_insn_r
->reg_rec_count
= 1;
13179 address
= u_regval
[0];
13180 record_buf_mem
[1] = address
;
13184 /* Handle STREXB. */
13185 record_buf_mem
[0] = 1;
13186 thumb2_insn_r
->mem_rec_count
= 1;
13190 /* Handle STREXH. */
13191 record_buf_mem
[0] = 2 ;
13192 thumb2_insn_r
->mem_rec_count
= 1;
13196 /* Handle STREXD. */
13197 address
= u_regval
[0];
13198 record_buf_mem
[0] = 4;
13199 record_buf_mem
[2] = 4;
13200 record_buf_mem
[3] = address
+ 4;
13201 thumb2_insn_r
->mem_rec_count
= 2;
13206 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
13208 if (bit (thumb2_insn_r
->arm_insn
, 24))
13210 if (bit (thumb2_insn_r
->arm_insn
, 23))
13211 offset_addr
= u_regval
[0] + (offset_imm
* 4);
13213 offset_addr
= u_regval
[0] - (offset_imm
* 4);
13215 address
= offset_addr
;
13218 address
= u_regval
[0];
13220 record_buf_mem
[0] = 4;
13221 record_buf_mem
[1] = address
;
13222 record_buf_mem
[2] = 4;
13223 record_buf_mem
[3] = address
+ 4;
13224 thumb2_insn_r
->mem_rec_count
= 2;
13225 record_buf
[0] = reg_rn
;
13226 thumb2_insn_r
->reg_rec_count
= 1;
13230 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13232 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13234 return ARM_RECORD_SUCCESS
;
13237 /* Handler for thumb2 data processing (shift register and modified immediate)
13241 thumb2_record_data_proc_sreg_mimm (insn_decode_record
*thumb2_insn_r
)
13243 uint32_t reg_rd
, op
;
13244 uint32_t record_buf
[8];
13246 op
= bits (thumb2_insn_r
->arm_insn
, 21, 24);
13247 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13249 if ((0 == op
|| 4 == op
|| 8 == op
|| 13 == op
) && 15 == reg_rd
)
13251 record_buf
[0] = ARM_PS_REGNUM
;
13252 thumb2_insn_r
->reg_rec_count
= 1;
13256 record_buf
[0] = reg_rd
;
13257 record_buf
[1] = ARM_PS_REGNUM
;
13258 thumb2_insn_r
->reg_rec_count
= 2;
13261 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13263 return ARM_RECORD_SUCCESS
;
13266 /* Generic handler for thumb2 instructions which effect destination and PS
13270 thumb2_record_ps_dest_generic (insn_decode_record
*thumb2_insn_r
)
13273 uint32_t record_buf
[8];
13275 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13277 record_buf
[0] = reg_rd
;
13278 record_buf
[1] = ARM_PS_REGNUM
;
13279 thumb2_insn_r
->reg_rec_count
= 2;
13281 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13283 return ARM_RECORD_SUCCESS
;
13286 /* Handler for thumb2 branch and miscellaneous control instructions. */
13289 thumb2_record_branch_misc_cntrl (insn_decode_record
*thumb2_insn_r
)
13291 uint32_t op
, op1
, op2
;
13292 uint32_t record_buf
[8];
13294 op
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
13295 op1
= bits (thumb2_insn_r
->arm_insn
, 12, 14);
13296 op2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13298 /* Handle MSR insn. */
13299 if (!(op1
& 0x2) && 0x38 == op
)
13303 /* CPSR is going to be changed. */
13304 record_buf
[0] = ARM_PS_REGNUM
;
13305 thumb2_insn_r
->reg_rec_count
= 1;
13309 arm_record_unsupported_insn(thumb2_insn_r
);
13313 else if (4 == (op1
& 0x5) || 5 == (op1
& 0x5))
13316 record_buf
[0] = ARM_PS_REGNUM
;
13317 record_buf
[1] = ARM_LR_REGNUM
;
13318 thumb2_insn_r
->reg_rec_count
= 2;
13321 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13323 return ARM_RECORD_SUCCESS
;
13326 /* Handler for thumb2 store single data item instructions. */
13329 thumb2_record_str_single_data (insn_decode_record
*thumb2_insn_r
)
13331 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13333 uint32_t reg_rn
, reg_rm
, offset_imm
, shift_imm
;
13334 uint32_t address
, offset_addr
;
13335 uint32_t record_buf
[8], record_buf_mem
[8];
13338 ULONGEST u_regval
[2];
13340 op1
= bits (thumb2_insn_r
->arm_insn
, 21, 23);
13341 op2
= bits (thumb2_insn_r
->arm_insn
, 6, 11);
13342 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13343 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
13345 if (bit (thumb2_insn_r
->arm_insn
, 23))
13348 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 11);
13349 offset_addr
= u_regval
[0] + offset_imm
;
13350 address
= offset_addr
;
13355 if ((0 == op1
|| 1 == op1
|| 2 == op1
) && !(op2
& 0x20))
13357 /* Handle STRB (register). */
13358 reg_rm
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
13359 regcache_raw_read_unsigned (reg_cache
, reg_rm
, &u_regval
[1]);
13360 shift_imm
= bits (thumb2_insn_r
->arm_insn
, 4, 5);
13361 offset_addr
= u_regval
[1] << shift_imm
;
13362 address
= u_regval
[0] + offset_addr
;
13366 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
13367 if (bit (thumb2_insn_r
->arm_insn
, 10))
13369 if (bit (thumb2_insn_r
->arm_insn
, 9))
13370 offset_addr
= u_regval
[0] + offset_imm
;
13372 offset_addr
= u_regval
[0] - offset_imm
;
13374 address
= offset_addr
;
13377 address
= u_regval
[0];
13383 /* Store byte instructions. */
13386 record_buf_mem
[0] = 1;
13388 /* Store half word instructions. */
13391 record_buf_mem
[0] = 2;
13393 /* Store word instructions. */
13396 record_buf_mem
[0] = 4;
13400 gdb_assert_not_reached ("no decoding pattern found");
13404 record_buf_mem
[1] = address
;
13405 thumb2_insn_r
->mem_rec_count
= 1;
13406 record_buf
[0] = reg_rn
;
13407 thumb2_insn_r
->reg_rec_count
= 1;
13409 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13411 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13413 return ARM_RECORD_SUCCESS
;
13416 /* Handler for thumb2 load memory hints instructions. */
13419 thumb2_record_ld_mem_hints (insn_decode_record
*thumb2_insn_r
)
13421 uint32_t record_buf
[8];
13422 uint32_t reg_rt
, reg_rn
;
13424 reg_rt
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
13425 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13427 if (ARM_PC_REGNUM
!= reg_rt
)
13429 record_buf
[0] = reg_rt
;
13430 record_buf
[1] = reg_rn
;
13431 record_buf
[2] = ARM_PS_REGNUM
;
13432 thumb2_insn_r
->reg_rec_count
= 3;
13434 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13436 return ARM_RECORD_SUCCESS
;
13439 return ARM_RECORD_FAILURE
;
13442 /* Handler for thumb2 load word instructions. */
13445 thumb2_record_ld_word (insn_decode_record
*thumb2_insn_r
)
13447 uint32_t opcode1
= 0, opcode2
= 0;
13448 uint32_t record_buf
[8];
13450 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
13451 record_buf
[1] = ARM_PS_REGNUM
;
13452 thumb2_insn_r
->reg_rec_count
= 2;
13454 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13456 return ARM_RECORD_SUCCESS
;
13459 /* Handler for thumb2 long multiply, long multiply accumulate, and
13460 divide instructions. */
13463 thumb2_record_lmul_lmla_div (insn_decode_record
*thumb2_insn_r
)
13465 uint32_t opcode1
= 0, opcode2
= 0;
13466 uint32_t record_buf
[8];
13467 uint32_t reg_src1
= 0;
13469 opcode1
= bits (thumb2_insn_r
->arm_insn
, 20, 22);
13470 opcode2
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
13472 if (0 == opcode1
|| 2 == opcode1
|| (opcode1
>= 4 && opcode1
<= 6))
13474 /* Handle SMULL, UMULL, SMULAL. */
13475 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
13476 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
13477 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
13478 record_buf
[2] = ARM_PS_REGNUM
;
13479 thumb2_insn_r
->reg_rec_count
= 3;
13481 else if (1 == opcode1
|| 3 == opcode2
)
13483 /* Handle SDIV and UDIV. */
13484 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
13485 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
13486 record_buf
[2] = ARM_PS_REGNUM
;
13487 thumb2_insn_r
->reg_rec_count
= 3;
13490 return ARM_RECORD_FAILURE
;
13492 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13494 return ARM_RECORD_SUCCESS
;
13497 /* Record handler for thumb32 coprocessor instructions. */
13500 thumb2_record_coproc_insn (insn_decode_record
*thumb2_insn_r
)
13502 if (bit (thumb2_insn_r
->arm_insn
, 25))
13503 return arm_record_coproc_data_proc (thumb2_insn_r
);
13505 return arm_record_asimd_vfp_coproc (thumb2_insn_r
);
13508 /* Record handler for advance SIMD structure load/store instructions. */
13511 thumb2_record_asimd_struct_ld_st (insn_decode_record
*thumb2_insn_r
)
13513 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13514 uint32_t l_bit
, a_bit
, b_bits
;
13515 uint32_t record_buf
[128], record_buf_mem
[128];
13516 uint32_t reg_rn
, reg_vd
, address
, f_esize
, f_elem
;
13517 uint32_t index_r
= 0, index_e
= 0, bf_regs
= 0, index_m
= 0, loop_t
= 0;
13520 l_bit
= bit (thumb2_insn_r
->arm_insn
, 21);
13521 a_bit
= bit (thumb2_insn_r
->arm_insn
, 23);
13522 b_bits
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13523 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13524 reg_vd
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
13525 reg_vd
= (bit (thumb2_insn_r
->arm_insn
, 22) << 4) | reg_vd
;
13526 f_ebytes
= (1 << bits (thumb2_insn_r
->arm_insn
, 6, 7));
13527 f_esize
= 8 * f_ebytes
;
13528 f_elem
= 8 / f_ebytes
;
13532 ULONGEST u_regval
= 0;
13533 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
13534 address
= u_regval
;
13539 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
13541 if (b_bits
== 0x07)
13543 else if (b_bits
== 0x0a)
13545 else if (b_bits
== 0x06)
13547 else if (b_bits
== 0x02)
13552 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
13554 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13556 record_buf_mem
[index_m
++] = f_ebytes
;
13557 record_buf_mem
[index_m
++] = address
;
13558 address
= address
+ f_ebytes
;
13559 thumb2_insn_r
->mem_rec_count
+= 1;
13564 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
13566 if (b_bits
== 0x09 || b_bits
== 0x08)
13568 else if (b_bits
== 0x03)
13573 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
13574 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13576 for (loop_t
= 0; loop_t
< 2; loop_t
++)
13578 record_buf_mem
[index_m
++] = f_ebytes
;
13579 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
13580 thumb2_insn_r
->mem_rec_count
+= 1;
13582 address
= address
+ (2 * f_ebytes
);
13586 else if ((b_bits
& 0x0e) == 0x04)
13588 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13590 for (loop_t
= 0; loop_t
< 3; loop_t
++)
13592 record_buf_mem
[index_m
++] = f_ebytes
;
13593 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
13594 thumb2_insn_r
->mem_rec_count
+= 1;
13596 address
= address
+ (3 * f_ebytes
);
13600 else if (!(b_bits
& 0x0e))
13602 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13604 for (loop_t
= 0; loop_t
< 4; loop_t
++)
13606 record_buf_mem
[index_m
++] = f_ebytes
;
13607 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
13608 thumb2_insn_r
->mem_rec_count
+= 1;
13610 address
= address
+ (4 * f_ebytes
);
13616 uint8_t bft_size
= bits (thumb2_insn_r
->arm_insn
, 10, 11);
13618 if (bft_size
== 0x00)
13620 else if (bft_size
== 0x01)
13622 else if (bft_size
== 0x02)
13628 if (!(b_bits
& 0x0b) || b_bits
== 0x08)
13629 thumb2_insn_r
->mem_rec_count
= 1;
13631 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09)
13632 thumb2_insn_r
->mem_rec_count
= 2;
13634 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a)
13635 thumb2_insn_r
->mem_rec_count
= 3;
13637 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b)
13638 thumb2_insn_r
->mem_rec_count
= 4;
13640 for (index_m
= 0; index_m
< thumb2_insn_r
->mem_rec_count
; index_m
++)
13642 record_buf_mem
[index_m
] = f_ebytes
;
13643 record_buf_mem
[index_m
] = address
+ (index_m
* f_ebytes
);
13652 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
13653 thumb2_insn_r
->reg_rec_count
= 1;
13655 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
13656 thumb2_insn_r
->reg_rec_count
= 2;
13658 else if ((b_bits
& 0x0e) == 0x04)
13659 thumb2_insn_r
->reg_rec_count
= 3;
13661 else if (!(b_bits
& 0x0e))
13662 thumb2_insn_r
->reg_rec_count
= 4;
13667 if (!(b_bits
& 0x0b) || b_bits
== 0x08 || b_bits
== 0x0c)
13668 thumb2_insn_r
->reg_rec_count
= 1;
13670 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09 || b_bits
== 0x0d)
13671 thumb2_insn_r
->reg_rec_count
= 2;
13673 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a || b_bits
== 0x0e)
13674 thumb2_insn_r
->reg_rec_count
= 3;
13676 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b || b_bits
== 0x0f)
13677 thumb2_insn_r
->reg_rec_count
= 4;
13679 for (index_r
= 0; index_r
< thumb2_insn_r
->reg_rec_count
; index_r
++)
13680 record_buf
[index_r
] = reg_vd
+ ARM_D0_REGNUM
+ index_r
;
13684 if (bits (thumb2_insn_r
->arm_insn
, 0, 3) != 15)
13686 record_buf
[index_r
] = reg_rn
;
13687 thumb2_insn_r
->reg_rec_count
+= 1;
13690 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13692 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13697 /* Decodes thumb2 instruction type and invokes its record handler. */
13699 static unsigned int
13700 thumb2_record_decode_insn_handler (insn_decode_record
*thumb2_insn_r
)
13702 uint32_t op
, op1
, op2
;
13704 op
= bit (thumb2_insn_r
->arm_insn
, 15);
13705 op1
= bits (thumb2_insn_r
->arm_insn
, 27, 28);
13706 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
13710 if (!(op2
& 0x64 ))
13712 /* Load/store multiple instruction. */
13713 return thumb2_record_ld_st_multiple (thumb2_insn_r
);
13715 else if (!((op2
& 0x64) ^ 0x04))
13717 /* Load/store (dual/exclusive) and table branch instruction. */
13718 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r
);
13720 else if (!((op2
& 0x20) ^ 0x20))
13722 /* Data-processing (shifted register). */
13723 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
13725 else if (op2
& 0x40)
13727 /* Co-processor instructions. */
13728 return thumb2_record_coproc_insn (thumb2_insn_r
);
13731 else if (op1
== 0x02)
13735 /* Branches and miscellaneous control instructions. */
13736 return thumb2_record_branch_misc_cntrl (thumb2_insn_r
);
13738 else if (op2
& 0x20)
13740 /* Data-processing (plain binary immediate) instruction. */
13741 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
13745 /* Data-processing (modified immediate). */
13746 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
13749 else if (op1
== 0x03)
13751 if (!(op2
& 0x71 ))
13753 /* Store single data item. */
13754 return thumb2_record_str_single_data (thumb2_insn_r
);
13756 else if (!((op2
& 0x71) ^ 0x10))
13758 /* Advanced SIMD or structure load/store instructions. */
13759 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r
);
13761 else if (!((op2
& 0x67) ^ 0x01))
13763 /* Load byte, memory hints instruction. */
13764 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
13766 else if (!((op2
& 0x67) ^ 0x03))
13768 /* Load halfword, memory hints instruction. */
13769 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
13771 else if (!((op2
& 0x67) ^ 0x05))
13773 /* Load word instruction. */
13774 return thumb2_record_ld_word (thumb2_insn_r
);
13776 else if (!((op2
& 0x70) ^ 0x20))
13778 /* Data-processing (register) instruction. */
13779 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
13781 else if (!((op2
& 0x78) ^ 0x30))
13783 /* Multiply, multiply accumulate, abs diff instruction. */
13784 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
13786 else if (!((op2
& 0x78) ^ 0x38))
13788 /* Long multiply, long multiply accumulate, and divide. */
13789 return thumb2_record_lmul_lmla_div (thumb2_insn_r
);
13791 else if (op2
& 0x40)
13793 /* Co-processor instructions. */
13794 return thumb2_record_coproc_insn (thumb2_insn_r
);
13801 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
13802 and positive val on fauilure. */
13805 extract_arm_insn (insn_decode_record
*insn_record
, uint32_t insn_size
)
13807 gdb_byte buf
[insn_size
];
13809 memset (&buf
[0], 0, insn_size
);
13811 if (target_read_memory (insn_record
->this_addr
, &buf
[0], insn_size
))
13813 insn_record
->arm_insn
= (uint32_t) extract_unsigned_integer (&buf
[0],
13815 gdbarch_byte_order (insn_record
->gdbarch
));
13819 typedef int (*sti_arm_hdl_fp_t
) (insn_decode_record
*);
13821 /* Decode arm/thumb insn depending on condition cods and opcodes; and
13825 decode_insn (insn_decode_record
*arm_record
, record_type_t record_type
,
13826 uint32_t insn_size
)
13829 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */
13830 static const sti_arm_hdl_fp_t
const arm_handle_insn
[8] =
13832 arm_record_data_proc_misc_ld_str
, /* 000. */
13833 arm_record_data_proc_imm
, /* 001. */
13834 arm_record_ld_st_imm_offset
, /* 010. */
13835 arm_record_ld_st_reg_offset
, /* 011. */
13836 arm_record_ld_st_multiple
, /* 100. */
13837 arm_record_b_bl
, /* 101. */
13838 arm_record_asimd_vfp_coproc
, /* 110. */
13839 arm_record_coproc_data_proc
/* 111. */
13842 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */
13843 static const sti_arm_hdl_fp_t
const thumb_handle_insn
[8] =
13845 thumb_record_shift_add_sub
, /* 000. */
13846 thumb_record_add_sub_cmp_mov
, /* 001. */
13847 thumb_record_ld_st_reg_offset
, /* 010. */
13848 thumb_record_ld_st_imm_offset
, /* 011. */
13849 thumb_record_ld_st_stack
, /* 100. */
13850 thumb_record_misc
, /* 101. */
13851 thumb_record_ldm_stm_swi
, /* 110. */
13852 thumb_record_branch
/* 111. */
13855 uint32_t ret
= 0; /* return value: negative:failure 0:success. */
13856 uint32_t insn_id
= 0;
13858 if (extract_arm_insn (arm_record
, insn_size
))
13862 printf_unfiltered (_("Process record: error reading memory at "
13863 "addr %s len = %d.\n"),
13864 paddress (arm_record
->gdbarch
, arm_record
->this_addr
), insn_size
);
13868 else if (ARM_RECORD
== record_type
)
13870 arm_record
->cond
= bits (arm_record
->arm_insn
, 28, 31);
13871 insn_id
= bits (arm_record
->arm_insn
, 25, 27);
13872 ret
= arm_record_extension_space (arm_record
);
13873 /* If this insn has fallen into extension space
13874 then we need not decode it anymore. */
13875 if (ret
!= -1 && !INSN_RECORDED(arm_record
))
13877 ret
= arm_handle_insn
[insn_id
] (arm_record
);
13880 else if (THUMB_RECORD
== record_type
)
13882 /* As thumb does not have condition codes, we set negative. */
13883 arm_record
->cond
= -1;
13884 insn_id
= bits (arm_record
->arm_insn
, 13, 15);
13885 ret
= thumb_handle_insn
[insn_id
] (arm_record
);
13887 else if (THUMB2_RECORD
== record_type
)
13889 /* As thumb does not have condition codes, we set negative. */
13890 arm_record
->cond
= -1;
13892 /* Swap first half of 32bit thumb instruction with second half. */
13893 arm_record
->arm_insn
13894 = (arm_record
->arm_insn
>> 16) | (arm_record
->arm_insn
<< 16);
13896 insn_id
= thumb2_record_decode_insn_handler (arm_record
);
13898 if (insn_id
!= ARM_RECORD_SUCCESS
)
13900 arm_record_unsupported_insn (arm_record
);
13906 /* Throw assertion. */
13907 gdb_assert_not_reached ("not a valid instruction, could not decode");
13914 /* Cleans up local record registers and memory allocations. */
13917 deallocate_reg_mem (insn_decode_record
*record
)
13919 xfree (record
->arm_regs
);
13920 xfree (record
->arm_mems
);
13924 /* Parse the current instruction and record the values of the registers and
13925 memory that will be changed in current instruction to record_arch_list".
13926 Return -1 if something is wrong. */
13929 arm_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
13930 CORE_ADDR insn_addr
)
13933 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
13934 uint32_t no_of_rec
= 0;
13935 uint32_t ret
= 0; /* return value: -1:record failure ; 0:success */
13936 ULONGEST t_bit
= 0, insn_id
= 0;
13938 ULONGEST u_regval
= 0;
13940 insn_decode_record arm_record
;
13942 memset (&arm_record
, 0, sizeof (insn_decode_record
));
13943 arm_record
.regcache
= regcache
;
13944 arm_record
.this_addr
= insn_addr
;
13945 arm_record
.gdbarch
= gdbarch
;
13948 if (record_debug
> 1)
13950 fprintf_unfiltered (gdb_stdlog
, "Process record: arm_process_record "
13952 paddress (gdbarch
, arm_record
.this_addr
));
13955 if (extract_arm_insn (&arm_record
, 2))
13959 printf_unfiltered (_("Process record: error reading memory at "
13960 "addr %s len = %d.\n"),
13961 paddress (arm_record
.gdbarch
,
13962 arm_record
.this_addr
), 2);
13967 /* Check the insn, whether it is thumb or arm one. */
13969 t_bit
= arm_psr_thumb_bit (arm_record
.gdbarch
);
13970 regcache_raw_read_unsigned (arm_record
.regcache
, ARM_PS_REGNUM
, &u_regval
);
13973 if (!(u_regval
& t_bit
))
13975 /* We are decoding arm insn. */
13976 ret
= decode_insn (&arm_record
, ARM_RECORD
, ARM_INSN_SIZE_BYTES
);
13980 insn_id
= bits (arm_record
.arm_insn
, 11, 15);
13981 /* is it thumb2 insn? */
13982 if ((0x1D == insn_id
) || (0x1E == insn_id
) || (0x1F == insn_id
))
13984 ret
= decode_insn (&arm_record
, THUMB2_RECORD
,
13985 THUMB2_INSN_SIZE_BYTES
);
13989 /* We are decoding thumb insn. */
13990 ret
= decode_insn (&arm_record
, THUMB_RECORD
, THUMB_INSN_SIZE_BYTES
);
13996 /* Record registers. */
13997 record_full_arch_list_add_reg (arm_record
.regcache
, ARM_PC_REGNUM
);
13998 if (arm_record
.arm_regs
)
14000 for (no_of_rec
= 0; no_of_rec
< arm_record
.reg_rec_count
; no_of_rec
++)
14002 if (record_full_arch_list_add_reg
14003 (arm_record
.regcache
, arm_record
.arm_regs
[no_of_rec
]))
14007 /* Record memories. */
14008 if (arm_record
.arm_mems
)
14010 for (no_of_rec
= 0; no_of_rec
< arm_record
.mem_rec_count
; no_of_rec
++)
14012 if (record_full_arch_list_add_mem
14013 ((CORE_ADDR
)arm_record
.arm_mems
[no_of_rec
].addr
,
14014 arm_record
.arm_mems
[no_of_rec
].len
))
14019 if (record_full_arch_list_add_end ())
14024 deallocate_reg_mem (&arm_record
);