1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "coff/internal.h" /* Internal format of COFF symbols in BFD */
31 extern void _initialize_arm_tdep (void);
34 The following macros are actually wrong. Neither arm nor thumb can
35 or should set the lsb on addr.
36 The thumb addresses are mod 2, so (addr & 2) would be a good heuristic
37 to use when checking for thumb (see arm_pc_is_thumb() below).
38 Unfortunately, something else depends on these (incorrect) macros, so
39 fixing them actually breaks gdb. I didn't have time to investigate. Z.R.
41 /* Thumb function addresses are odd (bit 0 is set). Here are some
42 macros to test, set, or clear bit 0 of addresses. */
43 #define IS_THUMB_ADDR(addr) ((addr) & 1)
44 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
45 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
47 /* Default register names as specified by APCS. */
48 static char * atpcs_register_names
[] =
49 {"a1", "a2", "a3", "a4", /* 0 1 2 3 */
50 "v1", "v2", "v3", "v4", /* 4 5 6 7 */
51 "v5", "v6", "v7", "v8", /* 8 9 10 11 */
52 "IP", "SP", "LR", "PC", /* 12 13 14 15 */
53 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
54 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
55 "FPS", "PS" }; /* 24 25 */
57 /* Alternate set of registers names used by GCC. */
58 static char * additional_register_names
[] =
59 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
60 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
61 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
62 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
63 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
64 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
65 "fps", "ps" }; /* 24 25 */
67 /* This is the variable that is set with "set disassembly-flavor".
68 By default use the APCS registers names. */
69 char ** arm_register_names
= atpcs_register_names
;
71 /* Valid register name flavours. */
72 static char apcs_flavor
[] = "apcs";
73 static char r_prefix_flavor
[] = "r-prefix";
74 static char * valid_flavors
[] =
81 /* Disassembly flavor to use. */
82 static char *disassembly_flavor
= apcs_flavor
;
84 /* This is used to keep the bfd arch_info in sync with the disassembly
86 static void set_disassembly_flavor_sfunc(char *, int,
87 struct cmd_list_element
*);
88 static void set_disassembly_flavor (void);
90 static void convert_from_extended (void *ptr
, void *dbl
);
92 /* Define other aspects of the stack frame. We keep the offsets of
93 all saved registers, 'cause we need 'em a lot! We also keep the
94 current size of the stack frame, and the offset of the frame
95 pointer from the stack pointer (for frameless functions, and when
96 we're still in the prologue of a function with a frame) */
98 struct frame_extra_info
100 struct frame_saved_regs fsr
;
106 #define SWAP_TARGET_AND_HOST(buffer,len) \
109 if (TARGET_BYTE_ORDER != HOST_BYTE_ORDER) \
112 char *p = (char *)(buffer); \
113 char *q = ((char *)(buffer)) + len - 1; \
114 for (; p < q; p++, q--) \
124 /* Will a function return an aggregate type in memory or in a
125 register? Return 0 if an aggregate type can be returned in a
126 register, 1 if it must be returned in memory. */
129 arm_use_struct_convention (int gcc_p
, struct type
*type
)
132 register enum type_code code
;
134 /* In the ARM ABI, "integer" like aggregate types are returned in
135 registers. For an aggregate type to be integer like, its size
136 must be less than or equal to REGISTER_SIZE and the offset of
137 each addressable subfield must be zero. Note that bit fields are
138 not addressable, and all addressable subfields of unions always
139 start at offset zero.
141 This function is based on the behaviour of GCC 2.95.1.
142 See: gcc/arm.c: arm_return_in_memory() for details.
144 Note: All versions of GCC before GCC 2.95.2 do not set up the
145 parameters correctly for a function returning the following
146 structure: struct { float f;}; This should be returned in memory,
147 not a register. Richard Earnshaw sent me a patch, but I do not
148 know of any way to detect if a function like the above has been
149 compiled with the correct calling convention. */
151 /* All aggregate types that won't fit in a register must be returned
153 if (TYPE_LENGTH (type
) > REGISTER_SIZE
)
158 /* The only aggregate types that can be returned in a register are
159 structs and unions. Arrays must be returned in memory. */
160 code
= TYPE_CODE (type
);
161 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
166 /* Assume all other aggregate types can be returned in a register.
167 Run a check for structures, unions and arrays. */
170 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
173 /* Need to check if this struct/union is "integer" like. For
174 this to be true, its size must be less than or equal to
175 REGISTER_SIZE and the offset of each addressable subfield
176 must be zero. Note that bit fields are not addressable, and
177 unions always start at offset zero. If any of the subfields
178 is a floating point type, the struct/union cannot be an
181 /* For each field in the object, check:
182 1) Is it FP? --> yes, nRc = 1;
183 2) Is it addressable (bitpos != 0) and
184 not packed (bitsize == 0)?
188 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
190 enum type_code field_type_code
;
191 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
193 /* Is it a floating point type field? */
194 if (field_type_code
== TYPE_CODE_FLT
)
200 /* If bitpos != 0, then we have to care about it. */
201 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
203 /* Bitfields are not addressable. If the field bitsize is
204 zero, then the field is not packed. Hence it cannot be
205 a bitfield or any other packed type. */
206 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
219 arm_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*thisframe
)
221 return (chain
!= 0 && (FRAME_SAVED_PC (thisframe
) >= LOWEST_PC
));
224 /* Set to true if the 32-bit mode is in use. */
228 /* Flag set by arm_fix_call_dummy that tells whether the target
229 function is a Thumb function. This flag is checked by
230 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
231 its use in valops.c) to pass the function address as an additional
234 static int target_is_thumb
;
236 /* Flag set by arm_fix_call_dummy that tells whether the calling
237 function is a Thumb function. This flag is checked by
238 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
240 static int caller_is_thumb
;
242 /* Determine if the program counter specified in MEMADDR is in a Thumb
246 arm_pc_is_thumb (bfd_vma memaddr
)
248 struct minimal_symbol
*sym
;
250 /* If bit 0 of the address is set, assume this is a Thumb address. */
251 if (IS_THUMB_ADDR (memaddr
))
254 /* Thumb functions have a "special" bit set in minimal symbols. */
255 sym
= lookup_minimal_symbol_by_pc (memaddr
);
258 return (MSYMBOL_IS_SPECIAL (sym
));
266 /* Determine if the program counter specified in MEMADDR is in a call
267 dummy being called from a Thumb function. */
270 arm_pc_is_thumb_dummy (bfd_vma memaddr
)
272 CORE_ADDR sp
= read_sp ();
274 /* FIXME: Until we switch for the new call dummy macros, this heuristic
275 is the best we can do. We are trying to determine if the pc is on
276 the stack, which (hopefully) will only happen in a call dummy.
277 We hope the current stack pointer is not so far alway from the dummy
278 frame location (true if we have not pushed large data structures or
279 gone too many levels deep) and that our 1024 is not enough to consider
280 code regions as part of the stack (true for most practical purposes) */
281 if (PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 1024))
282 return caller_is_thumb
;
288 arm_addr_bits_remove (CORE_ADDR val
)
290 if (arm_pc_is_thumb (val
))
291 return (val
& (arm_apcs_32
? 0xfffffffe : 0x03fffffe));
293 return (val
& (arm_apcs_32
? 0xfffffffc : 0x03fffffc));
297 arm_saved_pc_after_call (struct frame_info
*frame
)
299 return ADDR_BITS_REMOVE (read_register (LR_REGNUM
));
303 arm_frameless_function_invocation (struct frame_info
*fi
)
305 CORE_ADDR func_start
, after_prologue
;
308 func_start
= (get_pc_function_start ((fi
)->pc
) + FUNCTION_START_OFFSET
);
309 after_prologue
= SKIP_PROLOGUE (func_start
);
311 /* There are some frameless functions whose first two instructions
312 follow the standard APCS form, in which case after_prologue will
313 be func_start + 8. */
315 frameless
= (after_prologue
< func_start
+ 12);
319 /* A typical Thumb prologue looks like this:
323 Sometimes the latter instruction may be replaced by:
331 or, on tpcs, like this:
338 There is always one instruction of three classes:
343 When we have found at least one of each class we are done with the prolog.
344 Note that the "sub sp, #NN" before the push does not count.
348 thumb_skip_prologue (CORE_ADDR pc
)
350 CORE_ADDR current_pc
;
351 int findmask
= 0; /* findmask:
352 bit 0 - push { rlist }
353 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
354 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
357 for (current_pc
= pc
; current_pc
< pc
+ 40; current_pc
+= 2)
359 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
361 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
363 findmask
|= 1; /* push found */
365 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
367 if ((findmask
& 1) == 0) /* before push ? */
370 findmask
|= 4; /* add/sub sp found */
372 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
374 findmask
|= 2; /* setting of r7 found */
376 else if (insn
== 0x466f) /* mov r7, sp */
378 findmask
|= 2; /* setting of r7 found */
381 continue; /* something in the prolog that we don't care about or some
382 instruction from outside the prolog scheduled here for optimization */
388 /* The APCS (ARM Procedure Call Standard) defines the following
392 [stmfd sp!, {a1,a2,a3,a4}]
393 stmfd sp!, {...,fp,ip,lr,pc}
394 [stfe f7, [sp, #-12]!]
395 [stfe f6, [sp, #-12]!]
396 [stfe f5, [sp, #-12]!]
397 [stfe f4, [sp, #-12]!]
398 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
401 arm_skip_prologue (CORE_ADDR pc
)
405 CORE_ADDR func_addr
, func_end
;
406 struct symtab_and_line sal
;
408 /* See what the symbol table says. */
410 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
412 sal
= find_pc_line (func_addr
, 0);
413 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
417 /* Check if this is Thumb code. */
418 if (arm_pc_is_thumb (pc
))
419 return thumb_skip_prologue (pc
);
421 /* Can't find the prologue end in the symbol table, try it the hard way
422 by disassembling the instructions. */
424 inst
= read_memory_integer (skip_pc
, 4);
425 if (inst
!= 0xe1a0c00d) /* mov ip, sp */
429 inst
= read_memory_integer (skip_pc
, 4);
430 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
433 inst
= read_memory_integer (skip_pc
, 4);
436 if ((inst
& 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */
440 inst
= read_memory_integer (skip_pc
, 4);
442 /* Any insns after this point may float into the code, if it makes
443 for better instruction scheduling, so we skip them only if we
444 find them, but still consdier the function to be frame-ful. */
446 /* We may have either one sfmfd instruction here, or several stfe
447 insns, depending on the version of floating point code we
449 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
452 inst
= read_memory_integer (skip_pc
, 4);
456 while ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
459 inst
= read_memory_integer (skip_pc
, 4);
463 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
469 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
470 This function decodes a Thumb function prologue to determine:
471 1) the size of the stack frame
472 2) which registers are saved on it
473 3) the offsets of saved regs
474 4) the offset from the stack pointer to the frame pointer
475 This information is stored in the "extra" fields of the frame_info.
477 A typical Thumb function prologue would create this stack frame
478 (offsets relative to FP)
479 old SP -> 24 stack parameters
482 R7 -> 0 local variables (16 bytes)
483 SP -> -12 additional stack space (12 bytes)
484 The frame size would thus be 36 bytes, and the frame offset would be
485 12 bytes. The frame register is R7.
487 The comments for thumb_skip_prolog() describe the algorithm we use to detect
488 the end of the prolog */
492 thumb_scan_prologue (struct frame_info
*fi
)
494 CORE_ADDR prologue_start
;
495 CORE_ADDR prologue_end
;
496 CORE_ADDR current_pc
;
497 int saved_reg
[16]; /* which register has been copied to register n? */
498 int findmask
= 0; /* findmask:
499 bit 0 - push { rlist }
500 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
501 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
505 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
507 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
509 if (sal
.line
== 0) /* no line info, use current PC */
510 prologue_end
= fi
->pc
;
511 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
512 prologue_end
= sal
.end
; /* (probably means no prologue) */
515 prologue_end
= prologue_start
+ 40; /* We're in the boondocks: allow for */
516 /* 16 pushes, an add, and "mv fp,sp" */
518 prologue_end
= min (prologue_end
, fi
->pc
);
520 /* Initialize the saved register map. When register H is copied to
521 register L, we will put H in saved_reg[L]. */
522 for (i
= 0; i
< 16; i
++)
525 /* Search the prologue looking for instructions that set up the
526 frame pointer, adjust the stack pointer, and save registers.
527 Do this until all basic prolog instructions are found. */
530 for (current_pc
= prologue_start
;
531 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
538 insn
= read_memory_unsigned_integer (current_pc
, 2);
540 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
543 findmask
|= 1; /* push found */
544 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
545 whether to save LR (R14). */
546 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
548 /* Calculate offsets of saved R0-R7 and LR. */
549 for (regno
= LR_REGNUM
; regno
>= 0; regno
--)
550 if (mask
& (1 << regno
))
553 fi
->fsr
.regs
[saved_reg
[regno
]] = -(fi
->framesize
);
554 saved_reg
[regno
] = regno
; /* reset saved register map */
557 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
559 if ((findmask
& 1) == 0) /* before push ? */
562 findmask
|= 4; /* add/sub sp found */
564 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
565 if (insn
& 0x80) /* is it signed? (==subtracting) */
567 fi
->frameoffset
+= offset
;
570 fi
->framesize
-= offset
;
572 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
574 findmask
|= 2; /* setting of r7 found */
575 fi
->framereg
= THUMB_FP_REGNUM
;
576 fi
->frameoffset
= (insn
& 0xff) << 2; /* get scaled offset */
578 else if (insn
== 0x466f) /* mov r7, sp */
580 findmask
|= 2; /* setting of r7 found */
581 fi
->framereg
= THUMB_FP_REGNUM
;
583 saved_reg
[THUMB_FP_REGNUM
] = SP_REGNUM
;
585 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
587 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
588 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
589 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
592 continue; /* something in the prolog that we don't care about or some
593 instruction from outside the prolog scheduled here for optimization */
597 /* Check if prologue for this frame's PC has already been scanned. If
598 it has, copy the relevant information about that prologue and
599 return non-zero. Otherwise do not copy anything and return zero.
601 The information saved in the cache includes:
602 * the frame register number;
603 * the size of the stack frame;
604 * the offsets of saved regs (relative to the old SP); and
605 * the offset from the stack pointer to the frame pointer
607 The cache contains only one entry, since this is adequate for the
608 typical sequence of prologue scan requests we get. When performing
609 a backtrace, GDB will usually ask to scan the same function twice
610 in a row (once to get the frame chain, and once to fill in the
611 extra frame information). */
613 static struct frame_info prologue_cache
;
616 check_prologue_cache (struct frame_info
*fi
)
620 if (fi
->pc
== prologue_cache
.pc
)
622 fi
->framereg
= prologue_cache
.framereg
;
623 fi
->framesize
= prologue_cache
.framesize
;
624 fi
->frameoffset
= prologue_cache
.frameoffset
;
625 for (i
= 0; i
<= NUM_REGS
; i
++)
626 fi
->fsr
.regs
[i
] = prologue_cache
.fsr
.regs
[i
];
634 /* Copy the prologue information from fi to the prologue cache. */
637 save_prologue_cache (struct frame_info
*fi
)
641 prologue_cache
.pc
= fi
->pc
;
642 prologue_cache
.framereg
= fi
->framereg
;
643 prologue_cache
.framesize
= fi
->framesize
;
644 prologue_cache
.frameoffset
= fi
->frameoffset
;
646 for (i
= 0; i
<= NUM_REGS
; i
++)
647 prologue_cache
.fsr
.regs
[i
] = fi
->fsr
.regs
[i
];
651 /* This function decodes an ARM function prologue to determine:
652 1) the size of the stack frame
653 2) which registers are saved on it
654 3) the offsets of saved regs
655 4) the offset from the stack pointer to the frame pointer
656 This information is stored in the "extra" fields of the frame_info.
658 There are two basic forms for the ARM prologue. The fixed argument
659 function call will look like:
662 stmfd sp!, {fp, ip, lr, pc}
666 Which would create this stack frame (offsets relative to FP):
667 IP -> 4 (caller's stack)
668 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
669 -4 LR (return address in caller)
670 -8 IP (copy of caller's SP)
672 SP -> -28 Local variables
674 The frame size would thus be 32 bytes, and the frame offset would be
675 28 bytes. The stmfd call can also save any of the vN registers it
676 plans to use, which increases the frame size accordingly.
678 Note: The stored PC is 8 off of the STMFD instruction that stored it
679 because the ARM Store instructions always store PC + 8 when you read
682 A variable argument function call will look like:
685 stmfd sp!, {a1, a2, a3, a4}
686 stmfd sp!, {fp, ip, lr, pc}
689 Which would create this stack frame (offsets relative to FP):
690 IP -> 20 (caller's stack)
695 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
696 -4 LR (return address in caller)
697 -8 IP (copy of caller's SP)
699 SP -> -28 Local variables
701 The frame size would thus be 48 bytes, and the frame offset would be
704 There is another potential complication, which is that the optimizer
705 will try to separate the store of fp in the "stmfd" instruction from
706 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
707 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
709 Also, note, the original version of the ARM toolchain claimed that there
712 instruction at the end of the prologue. I have never seen GCC produce
713 this, and the ARM docs don't mention it. We still test for it below in
719 arm_scan_prologue (struct frame_info
*fi
)
721 int regno
, sp_offset
, fp_offset
;
722 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
724 /* Check if this function is already in the cache of frame information. */
725 if (check_prologue_cache (fi
))
728 /* Assume there is no frame until proven otherwise. */
729 fi
->framereg
= SP_REGNUM
;
733 /* Check for Thumb prologue. */
734 if (arm_pc_is_thumb (fi
->pc
))
736 thumb_scan_prologue (fi
);
737 save_prologue_cache (fi
);
741 /* Find the function prologue. If we can't find the function in
742 the symbol table, peek in the stack frame to find the PC. */
743 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
745 /* Assume the prologue is everything between the first instruction
746 in the function and the first source line. */
747 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
749 if (sal
.line
== 0) /* no line info, use current PC */
750 prologue_end
= fi
->pc
;
751 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
752 prologue_end
= sal
.end
; /* (probably means no prologue) */
756 /* Get address of the stmfd in the prologue of the callee; the saved
757 PC is the address of the stmfd + 8. */
758 prologue_start
= ADDR_BITS_REMOVE (read_memory_integer (fi
->frame
, 4))
760 prologue_end
= prologue_start
+ 64; /* This is all the insn's
761 that could be in the prologue,
762 plus room for 5 insn's inserted
766 /* Now search the prologue looking for instructions that set up the
767 frame pointer, adjust the stack pointer, and save registers.
769 Be careful, however, and if it doesn't look like a prologue,
770 don't try to scan it. If, for instance, a frameless function
771 begins with stmfd sp!, then we will tell ourselves there is
772 a frame, which will confuse stack traceback, as well ad"finish"
773 and other operations that rely on a knowledge of the stack
776 In the APCS, the prologue should start with "mov ip, sp" so
777 if we don't see this as the first insn, we will stop. */
779 sp_offset
= fp_offset
= 0;
781 if (read_memory_unsigned_integer (prologue_start
, 4)
782 == 0xe1a0c00d) /* mov ip, sp */
784 for (current_pc
= prologue_start
+ 4; current_pc
< prologue_end
;
787 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
789 if ((insn
& 0xffff0000) == 0xe92d0000)
790 /* stmfd sp!, {..., fp, ip, lr, pc}
792 stmfd sp!, {a1, a2, a3, a4} */
794 int mask
= insn
& 0xffff;
796 /* Calculate offsets of saved registers. */
797 for (regno
= PC_REGNUM
; regno
>= 0; regno
--)
798 if (mask
& (1 << regno
))
801 fi
->fsr
.regs
[regno
] = sp_offset
;
804 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
806 unsigned imm
= insn
& 0xff; /* immediate value */
807 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
808 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
810 fi
->framereg
= FP_REGNUM
;
812 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
814 unsigned imm
= insn
& 0xff; /* immediate value */
815 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
816 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
819 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
822 regno
= F0_REGNUM
+ ((insn
>> 12) & 0x07);
823 fi
->fsr
.regs
[regno
] = sp_offset
;
825 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
828 unsigned int fp_start_reg
, fp_bound_reg
;
830 if ((insn
& 0x800) == 0x800) /* N0 is set */
832 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
839 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
845 fp_start_reg
= F0_REGNUM
+ ((insn
>> 12) & 0x7);
846 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
847 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
850 fi
->fsr
.regs
[fp_start_reg
++] = sp_offset
;
854 /* The optimizer might shove anything into the prologue,
855 so we just skip what we don't recognize. */
860 /* The frame size is just the negative of the offset (from the original SP)
861 of the last thing thing we pushed on the stack. The frame offset is
862 [new FP] - [new SP]. */
863 fi
->framesize
= -sp_offset
;
864 fi
->frameoffset
= fp_offset
- sp_offset
;
866 save_prologue_cache (fi
);
869 /* Find REGNUM on the stack. Otherwise, it's in an active register.
870 One thing we might want to do here is to check REGNUM against the
871 clobber mask, and somehow flag it as invalid if it isn't saved on
872 the stack somewhere. This would provide a graceful failure mode
873 when trying to get the value of caller-saves registers for an inner
877 arm_find_callers_reg (struct frame_info
*fi
, int regnum
)
879 for (; fi
; fi
= fi
->next
)
881 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
882 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
883 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
886 if (fi
->fsr
.regs
[regnum
] != 0)
887 return read_memory_integer (fi
->fsr
.regs
[regnum
],
888 REGISTER_RAW_SIZE (regnum
));
889 return read_register (regnum
);
892 /* Function: frame_chain
893 Given a GDB frame, determine the address of the calling function's frame.
894 This will be used to create a new GDB frame struct, and then
895 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
896 For ARM, we save the frame size when we initialize the frame_info.
898 The original definition of this function was a macro in tm-arm.h:
899 { In the case of the ARM, the frame's nominal address is the FP value,
900 and 12 bytes before comes the saved previous FP value as a 4-byte word. }
902 #define FRAME_CHAIN(thisframe) \
903 ((thisframe)->pc >= LOWEST_PC ? \
904 read_memory_integer ((thisframe)->frame - 12, 4) :\
910 arm_frame_chain (struct frame_info
*fi
)
912 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
913 CORE_ADDR fn_start
, callers_pc
, fp
;
915 /* is this a dummy frame? */
916 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
917 return fi
->frame
; /* dummy frame same as caller's frame */
919 /* is caller-of-this a dummy frame? */
920 callers_pc
= FRAME_SAVED_PC (fi
); /* find out who called us: */
921 fp
= arm_find_callers_reg (fi
, FP_REGNUM
);
922 if (PC_IN_CALL_DUMMY (callers_pc
, fp
, fp
))
923 return fp
; /* dummy frame's frame may bear no relation to ours */
925 if (find_pc_partial_function (fi
->pc
, 0, &fn_start
, 0))
926 if (fn_start
== entry_point_address ())
927 return 0; /* in _start fn, don't chain further */
929 CORE_ADDR caller_pc
, fn_start
;
930 struct frame_info caller_fi
;
931 int framereg
= fi
->framereg
;
933 if (fi
->pc
< LOWEST_PC
)
936 /* If the caller is the startup code, we're at the end of the chain. */
937 caller_pc
= FRAME_SAVED_PC (fi
);
938 if (find_pc_partial_function (caller_pc
, 0, &fn_start
, 0))
939 if (fn_start
== entry_point_address ())
942 /* If the caller is Thumb and the caller is ARM, or vice versa,
943 the frame register of the caller is different from ours.
944 So we must scan the prologue of the caller to determine its
945 frame register number. */
946 if (arm_pc_is_thumb (caller_pc
) != arm_pc_is_thumb (fi
->pc
))
948 memset (&caller_fi
, 0, sizeof (caller_fi
));
949 caller_fi
.pc
= caller_pc
;
950 arm_scan_prologue (&caller_fi
);
951 framereg
= caller_fi
.framereg
;
954 /* If the caller used a frame register, return its value.
955 Otherwise, return the caller's stack pointer. */
956 if (framereg
== FP_REGNUM
|| framereg
== THUMB_FP_REGNUM
)
957 return arm_find_callers_reg (fi
, framereg
);
959 return fi
->frame
+ fi
->framesize
;
962 /* This function actually figures out the frame address for a given pc
963 and sp. This is tricky because we sometimes don't use an explicit
964 frame pointer, and the previous stack pointer isn't necessarily
965 recorded on the stack. The only reliable way to get this info is
966 to examine the prologue. FROMLEAF is a little confusing, it means
967 this is the next frame up the chain AFTER a frameless function. If
968 this is true, then the frame value for this frame is still in the
972 arm_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
977 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
979 memset (fi
->fsr
.regs
, '\000', sizeof fi
->fsr
.regs
);
981 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
982 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
984 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
985 by assuming it's always FP. */
986 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
, SP_REGNUM
);
994 arm_scan_prologue (fi
);
997 /* this is the innermost frame? */
998 fi
->frame
= read_register (fi
->framereg
);
999 else if (fi
->framereg
== FP_REGNUM
|| fi
->framereg
== THUMB_FP_REGNUM
)
1001 /* not the innermost frame */
1002 /* If we have an FP, the callee saved it. */
1003 if (fi
->next
->fsr
.regs
[fi
->framereg
] != 0)
1005 read_memory_integer (fi
->next
->fsr
.regs
[fi
->framereg
], 4);
1007 /* If we were called by a frameless fn. then our frame is
1008 still in the frame pointer register on the board... */
1009 fi
->frame
= read_fp ();
1012 /* Calculate actual addresses of saved registers using offsets
1013 determined by arm_scan_prologue. */
1014 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1015 if (fi
->fsr
.regs
[reg
] != 0)
1016 fi
->fsr
.regs
[reg
] += fi
->frame
+ fi
->framesize
- fi
->frameoffset
;
1021 /* Find the caller of this frame. We do this by seeing if LR_REGNUM
1022 is saved in the stack anywhere, otherwise we get it from the
1025 The old definition of this function was a macro:
1026 #define FRAME_SAVED_PC(FRAME) \
1027 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1030 arm_frame_saved_pc (struct frame_info
*fi
)
1032 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1033 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1034 return generic_read_register_dummy (fi
->pc
, fi
->frame
, PC_REGNUM
);
1038 CORE_ADDR pc
= arm_find_callers_reg (fi
, LR_REGNUM
);
1039 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1043 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1044 Examine the Program Status Register to decide which state we're in. */
1047 arm_target_read_fp (void)
1049 if (read_register (PS_REGNUM
) & 0x20) /* Bit 5 is Thumb state bit */
1050 return read_register (THUMB_FP_REGNUM
); /* R7 if Thumb */
1052 return read_register (FP_REGNUM
); /* R11 if ARM */
1055 /* Calculate the frame offsets of the saved registers (ARM version). */
1058 arm_frame_find_saved_regs (struct frame_info
*fi
,
1059 struct frame_saved_regs
*regaddr
)
1061 memcpy (regaddr
, &fi
->fsr
, sizeof (struct frame_saved_regs
));
1065 arm_push_dummy_frame (void)
1067 CORE_ADDR old_sp
= read_register (SP_REGNUM
);
1068 CORE_ADDR sp
= old_sp
;
1069 CORE_ADDR fp
, prologue_start
;
1072 /* Push the two dummy prologue instructions in reverse order,
1073 so that they'll be in the correct low-to-high order in memory. */
1074 /* sub fp, ip, #4 */
1075 sp
= push_word (sp
, 0xe24cb004);
1076 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1077 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
1079 /* Push a pointer to the dummy prologue + 12, because when stm
1080 instruction stores the PC, it stores the address of the stm
1081 instruction itself plus 12. */
1082 fp
= sp
= push_word (sp
, prologue_start
+ 12);
1083 sp
= push_word (sp
, read_register (PC_REGNUM
)); /* FIXME: was PS_REGNUM */
1084 sp
= push_word (sp
, old_sp
);
1085 sp
= push_word (sp
, read_register (FP_REGNUM
));
1087 for (regnum
= 10; regnum
>= 0; regnum
--)
1088 sp
= push_word (sp
, read_register (regnum
));
1090 write_register (FP_REGNUM
, fp
);
1091 write_register (THUMB_FP_REGNUM
, fp
);
1092 write_register (SP_REGNUM
, sp
);
1095 /* Fix up the call dummy, based on whether the processor is currently
1096 in Thumb or ARM mode, and whether the target function is Thumb or
1097 ARM. There are three different situations requiring three
1100 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1101 been copied into the dummy parameter to this function.
1102 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1103 "mov pc,r4" instruction patched to be a "bx r4" instead.
1104 * Thumb calling anything: uses the Thumb dummy defined below, which
1105 works for calling both ARM and Thumb functions.
1107 All three call dummies expect to receive the target function
1108 address in R4, with the low bit set if it's a Thumb function. */
1111 arm_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
1112 value_ptr
*args
, struct type
*type
, int gcc_p
)
1114 static short thumb_dummy
[4] =
1116 0xf000, 0xf801, /* bl label */
1117 0xdf18, /* swi 24 */
1118 0x4720, /* label: bx r4 */
1120 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
1122 /* Set flag indicating whether the current PC is in a Thumb function. */
1123 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
1125 /* If the target function is Thumb, set the low bit of the function
1126 address. And if the CPU is currently in ARM mode, patch the
1127 second instruction of call dummy to use a BX instruction to
1128 switch to Thumb mode. */
1129 target_is_thumb
= arm_pc_is_thumb (fun
);
1130 if (target_is_thumb
)
1133 if (!caller_is_thumb
)
1134 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
1137 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1138 instead of the ARM one that's already been copied. This will
1139 work for both Thumb and ARM target functions. */
1140 if (caller_is_thumb
)
1144 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
1146 for (i
= 0; i
< len
; i
++)
1148 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1149 p
+= sizeof (thumb_dummy
[0]);
1153 /* Put the target address in r4; the call dummy will copy this to
1155 write_register (4, fun
);
1158 /* Return the offset in the call dummy of the instruction that needs
1159 to have a breakpoint placed on it. This is the offset of the 'swi
1160 24' instruction, which is no longer actually used, but simply acts
1161 as a place-holder now.
1163 This implements the CALL_DUMMY_BREAK_OFFSET macro. */
1166 arm_call_dummy_breakpoint_offset (void)
1168 if (caller_is_thumb
)
1176 This function does not support passing parameters using the FPA
1177 variant of the APCS. It passes any floating point arguments in the
1178 general registers and/or on the stack. */
1181 arm_push_arguments (int nargs
, value_ptr
* args
, CORE_ADDR sp
,
1182 int struct_return
, CORE_ADDR struct_addr
)
1185 int argnum
, argreg
, nstack_size
;
1187 /* Walk through the list of args and determine how large a temporary
1188 stack is required. Need to take care here as structs may be
1189 passed on the stack, and we have to to push them. */
1190 nstack_size
= -4 * REGISTER_SIZE
; /* Some arguments go into A1-A4. */
1191 if (struct_return
) /* The struct address goes in A1. */
1192 nstack_size
+= REGISTER_SIZE
;
1194 /* Walk through the arguments and add their size to nstack_size. */
1195 for (argnum
= 0; argnum
< nargs
; argnum
++)
1198 struct type
*arg_type
;
1200 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1201 len
= TYPE_LENGTH (arg_type
);
1203 /* ANSI C code passes float arguments as integers, K&R code
1204 passes float arguments as doubles. Correct for this here. */
1205 if (TYPE_CODE_FLT
== TYPE_CODE (arg_type
) && REGISTER_SIZE
== len
)
1206 nstack_size
+= FP_REGISTER_VIRTUAL_SIZE
;
1211 /* Allocate room on the stack, and initialize our stack frame
1214 if (nstack_size
> 0)
1220 /* Initialize the integer argument register pointer. */
1223 /* The struct_return pointer occupies the first parameter passing
1226 write_register (argreg
++, struct_addr
);
1228 /* Process arguments from left to right. Store as many as allowed
1229 in the parameter passing registers (A1-A4), and save the rest on
1230 the temporary stack. */
1231 for (argnum
= 0; argnum
< nargs
; argnum
++)
1237 enum type_code typecode
;
1238 struct type
*arg_type
, *target_type
;
1240 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1241 target_type
= TYPE_TARGET_TYPE (arg_type
);
1242 len
= TYPE_LENGTH (arg_type
);
1243 typecode
= TYPE_CODE (arg_type
);
1244 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
1246 /* ANSI C code passes float arguments as integers, K&R code
1247 passes float arguments as doubles. The .stabs record for
1248 for ANSI prototype floating point arguments records the
1249 type as FP_INTEGER, while a K&R style (no prototype)
1250 .stabs records the type as FP_FLOAT. In this latter case
1251 the compiler converts the float arguments to double before
1252 calling the function. */
1253 if (TYPE_CODE_FLT
== typecode
&& REGISTER_SIZE
== len
)
1257 char * bufo
= (char *) &d
;
1258 char * bufd
= (char *) &dbl_arg
;
1260 len
= sizeof (double);
1262 SWAP_TARGET_AND_HOST (&f
, sizeof (float)); /* adjust endianess */
1264 /* We must revert the longwords so they get loaded into the
1265 the right registers. */
1266 memcpy (bufd
, bufo
+ len
/ 2, len
/ 2);
1267 SWAP_TARGET_AND_HOST (bufd
, len
/ 2); /* adjust endianess */
1268 memcpy (bufd
+ len
/ 2, bufo
, len
/ 2);
1269 SWAP_TARGET_AND_HOST (bufd
+ len
/ 2, len
/ 2); /* adjust endianess */
1270 val
= (char *) &dbl_arg
;
1273 /* I don't know why this code was disable. The only logical use
1274 for a function pointer is to call that function, so setting
1275 the mode bit is perfectly fine. FN */
1276 /* If the argument is a pointer to a function, and it is a Thumb
1277 function, set the low bit of the pointer. */
1278 if (TYPE_CODE_PTR
== typecode
1279 && NULL
!= target_type
1280 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1282 CORE_ADDR regval
= extract_address (val
, len
);
1283 if (arm_pc_is_thumb (regval
))
1284 store_address (val
, len
, MAKE_THUMB_ADDR (regval
));
1287 /* Copy the argument to general registers or the stack in
1288 register-sized pieces. Large arguments are split between
1289 registers and stack. */
1292 int partial_len
= len
< REGISTER_SIZE
? len
: REGISTER_SIZE
;
1294 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1296 /* It's an argument being passed in a general register. */
1297 regval
= extract_address (val
, partial_len
);
1298 write_register (argreg
++, regval
);
1302 /* Push the arguments onto the stack. */
1303 write_memory ((CORE_ADDR
) fp
, val
, REGISTER_SIZE
);
1304 fp
+= REGISTER_SIZE
;
1312 /* Return adjusted stack pointer. */
1317 arm_pop_frame (void)
1320 struct frame_info
*frame
= get_current_frame ();
1322 if (!PC_IN_CALL_DUMMY(frame
->pc
, frame
->frame
, read_fp()))
1326 old_SP
= read_register (frame
->framereg
);
1327 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1328 if (frame
->fsr
.regs
[regnum
] != 0)
1329 write_register (regnum
,
1330 read_memory_integer (frame
->fsr
.regs
[regnum
], 4));
1332 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
1333 write_register (SP_REGNUM
, old_SP
);
1339 sp
= read_register (FP_REGNUM
);
1340 sp
-= sizeof(CORE_ADDR
); /* we don't care about this first word */
1342 write_register (PC_REGNUM
, read_memory_integer (sp
, 4));
1343 sp
-= sizeof(CORE_ADDR
);
1344 write_register (SP_REGNUM
, read_memory_integer (sp
, 4));
1345 sp
-= sizeof(CORE_ADDR
);
1346 write_register (FP_REGNUM
, read_memory_integer (sp
, 4));
1347 sp
-= sizeof(CORE_ADDR
);
1349 for (regnum
= 10; regnum
>= 0; regnum
--)
1351 write_register (regnum
, read_memory_integer (sp
, 4));
1352 sp
-= sizeof(CORE_ADDR
);
1356 flush_cached_frames ();
1360 print_fpu_flags (int flags
)
1362 if (flags
& (1 << 0))
1363 fputs ("IVO ", stdout
);
1364 if (flags
& (1 << 1))
1365 fputs ("DVZ ", stdout
);
1366 if (flags
& (1 << 2))
1367 fputs ("OFL ", stdout
);
1368 if (flags
& (1 << 3))
1369 fputs ("UFL ", stdout
);
1370 if (flags
& (1 << 4))
1371 fputs ("INX ", stdout
);
1376 arm_float_info (void)
1378 register unsigned long status
= read_register (FPS_REGNUM
);
1381 type
= (status
>> 24) & 127;
1382 printf ("%s FPU type %d\n",
1383 (status
& (1 << 31)) ? "Hardware" : "Software",
1385 fputs ("mask: ", stdout
);
1386 print_fpu_flags (status
>> 16);
1387 fputs ("flags: ", stdout
);
1388 print_fpu_flags (status
);
1391 /* If the disassembly mode is APCS, we have to also switch the
1392 bfd mach_type. This function is run in the set disassembly_flavor
1393 command, and does that. */
1396 set_disassembly_flavor_sfunc (char *args
, int from_tty
,
1397 struct cmd_list_element
*c
)
1399 set_disassembly_flavor ();
1403 set_disassembly_flavor (void)
1405 if (disassembly_flavor
== apcs_flavor
)
1407 parse_arm_disassembler_option ("reg-names-atpcs");
1408 arm_register_names
= atpcs_register_names
;
1410 else if (disassembly_flavor
== r_prefix_flavor
)
1412 parse_arm_disassembler_option ("reg-names-std");
1413 arm_register_names
= additional_register_names
;
1417 /* arm_othernames implements the "othernames" command. This is kind
1418 of hacky, and I prefer the set-show disassembly-flavor which is
1419 also used for the x86 gdb. I will keep this around, however, in
1420 case anyone is actually using it. */
1423 arm_othernames (char *names
, int n
)
1425 if (disassembly_flavor
== r_prefix_flavor
)
1427 disassembly_flavor
= apcs_flavor
;
1428 set_disassembly_flavor ();
1432 disassembly_flavor
= r_prefix_flavor
;
1433 set_disassembly_flavor ();
1438 /* FIXME: The generated assembler works but sucks. Instead of using
1439 r0, r1 it pushes them on the stack, then loads them into r3, r4 and
1440 uses those registers. I must be missing something. ScottB */
1443 convert_from_extended (void *ptr
, void *dbl
)
1449 : "r" (ptr
), "r" (dbl
));
1453 convert_to_extended (void *dbl
, void *ptr
)
1459 : "r" (dbl
), "r" (ptr
));
1463 convert_from_extended (void *ptr
, void *dbl
)
1465 *(double *) dbl
= *(double *) ptr
;
1469 convert_to_extended (void *dbl
, void *ptr
)
1471 *(double *) ptr
= *(double *) dbl
;
1475 /* Nonzero if register N requires conversion from raw format to
1479 arm_register_convertible (unsigned int regnum
)
1481 return ((regnum
- F0_REGNUM
) < 8);
1484 /* Convert data from raw format for register REGNUM in buffer FROM to
1485 virtual format with type TYPE in buffer TO. */
1488 arm_register_convert_to_virtual (unsigned int regnum
, struct type
*type
,
1489 void *from
, void *to
)
1493 convert_from_extended (from
, &val
);
1494 store_floating (to
, TYPE_LENGTH (type
), val
);
1497 /* Convert data from virtual format with type TYPE in buffer FROM to
1498 raw format for register REGNUM in buffer TO. */
1501 arm_register_convert_to_raw (unsigned int regnum
, struct type
*type
,
1502 void *from
, void *to
)
1504 double val
= extract_floating (from
, TYPE_LENGTH (type
));
1506 convert_to_extended (&val
, to
);
1510 condition_true (unsigned long cond
, unsigned long status_reg
)
1512 if (cond
== INST_AL
|| cond
== INST_NV
)
1518 return ((status_reg
& FLAG_Z
) != 0);
1520 return ((status_reg
& FLAG_Z
) == 0);
1522 return ((status_reg
& FLAG_C
) != 0);
1524 return ((status_reg
& FLAG_C
) == 0);
1526 return ((status_reg
& FLAG_N
) != 0);
1528 return ((status_reg
& FLAG_N
) == 0);
1530 return ((status_reg
& FLAG_V
) != 0);
1532 return ((status_reg
& FLAG_V
) == 0);
1534 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1536 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1538 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1540 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1542 return (((status_reg
& FLAG_Z
) == 0) &&
1543 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1545 return (((status_reg
& FLAG_Z
) != 0) ||
1546 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1551 #define submask(x) ((1L << ((x) + 1)) - 1)
1552 #define bit(obj,st) (((obj) >> (st)) & 1)
1553 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1554 #define sbits(obj,st,fn) \
1555 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1556 #define BranchDest(addr,instr) \
1557 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1560 static unsigned long
1561 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1562 unsigned long status_reg
)
1564 unsigned long res
, shift
;
1565 int rm
= bits (inst
, 0, 3);
1566 unsigned long shifttype
= bits (inst
, 5, 6);
1570 int rs
= bits (inst
, 8, 11);
1571 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1574 shift
= bits (inst
, 7, 11);
1577 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1578 + (bit (inst
, 4) ? 12 : 8))
1579 : read_register (rm
));
1584 res
= shift
>= 32 ? 0 : res
<< shift
;
1588 res
= shift
>= 32 ? 0 : res
>> shift
;
1594 res
= ((res
& 0x80000000L
)
1595 ? ~((~res
) >> shift
) : res
>> shift
);
1598 case 3: /* ROR/RRX */
1601 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1603 res
= (res
>> shift
) | (res
<< (32 - shift
));
1607 return res
& 0xffffffff;
1610 /* Return number of 1-bits in VAL. */
1613 bitcount (unsigned long val
)
1616 for (nbits
= 0; val
!= 0; nbits
++)
1617 val
&= val
- 1; /* delete rightmost 1-bit in val */
1622 thumb_get_next_pc (CORE_ADDR pc
)
1624 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1625 unsigned short inst1
= read_memory_integer (pc
, 2);
1626 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1627 unsigned long offset
;
1629 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1633 /* Fetch the saved PC from the stack. It's stored above
1634 all of the other registers. */
1635 offset
= bitcount (bits (inst1
, 0, 7)) * REGISTER_SIZE
;
1636 sp
= read_register (SP_REGNUM
);
1637 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1638 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1640 error ("Infinite loop detected");
1642 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1644 unsigned long status
= read_register (PS_REGNUM
);
1645 unsigned long cond
= bits (inst1
, 8, 11);
1646 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1647 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1649 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1651 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1653 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1655 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1656 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1657 nextpc
= pc_val
+ offset
;
1664 arm_get_next_pc (CORE_ADDR pc
)
1666 unsigned long pc_val
;
1667 unsigned long this_instr
;
1668 unsigned long status
;
1671 if (arm_pc_is_thumb (pc
))
1672 return thumb_get_next_pc (pc
);
1674 pc_val
= (unsigned long) pc
;
1675 this_instr
= read_memory_integer (pc
, 4);
1676 status
= read_register (PS_REGNUM
);
1677 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1679 if (condition_true (bits (this_instr
, 28, 31), status
))
1681 switch (bits (this_instr
, 24, 27))
1684 case 0x1: /* data processing */
1688 unsigned long operand1
, operand2
, result
= 0;
1692 if (bits (this_instr
, 12, 15) != 15)
1695 if (bits (this_instr
, 22, 25) == 0
1696 && bits (this_instr
, 4, 7) == 9) /* multiply */
1697 error ("Illegal update to pc in instruction");
1699 /* Multiply into PC */
1700 c
= (status
& FLAG_C
) ? 1 : 0;
1701 rn
= bits (this_instr
, 16, 19);
1702 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1704 if (bit (this_instr
, 25))
1706 unsigned long immval
= bits (this_instr
, 0, 7);
1707 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1708 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1711 else /* operand 2 is a shifted register */
1712 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1714 switch (bits (this_instr
, 21, 24))
1717 result
= operand1
& operand2
;
1721 result
= operand1
^ operand2
;
1725 result
= operand1
- operand2
;
1729 result
= operand2
- operand1
;
1733 result
= operand1
+ operand2
;
1737 result
= operand1
+ operand2
+ c
;
1741 result
= operand1
- operand2
+ c
;
1745 result
= operand2
- operand1
+ c
;
1751 case 0xb: /* tst, teq, cmp, cmn */
1752 result
= (unsigned long) nextpc
;
1756 result
= operand1
| operand2
;
1760 /* Always step into a function. */
1765 result
= operand1
& ~operand2
;
1772 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1775 error ("Infinite loop detected");
1780 case 0x5: /* data transfer */
1783 if (bit (this_instr
, 20))
1786 if (bits (this_instr
, 12, 15) == 15)
1792 if (bit (this_instr
, 22))
1793 error ("Illegal update to pc in instruction");
1795 /* byte write to PC */
1796 rn
= bits (this_instr
, 16, 19);
1797 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1798 if (bit (this_instr
, 24))
1801 int c
= (status
& FLAG_C
) ? 1 : 0;
1802 unsigned long offset
=
1803 (bit (this_instr
, 25)
1804 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1805 : bits (this_instr
, 0, 11));
1807 if (bit (this_instr
, 23))
1812 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1815 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1818 error ("Infinite loop detected");
1824 case 0x9: /* block transfer */
1825 if (bit (this_instr
, 20))
1828 if (bit (this_instr
, 15))
1833 if (bit (this_instr
, 23))
1836 unsigned long reglist
= bits (this_instr
, 0, 14);
1837 offset
= bitcount (reglist
) * 4;
1838 if (bit (this_instr
, 24)) /* pre */
1841 else if (bit (this_instr
, 24))
1845 unsigned long rn_val
=
1846 read_register (bits (this_instr
, 16, 19));
1848 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1852 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1854 error ("Infinite loop detected");
1859 case 0xb: /* branch & link */
1860 case 0xa: /* branch */
1862 nextpc
= BranchDest (pc
, this_instr
);
1864 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1866 error ("Infinite loop detected");
1872 case 0xe: /* coproc ops */
1877 fprintf (stderr
, "Bad bit-field extraction\n");
1885 #include "bfd-in2.h"
1886 #include "libcoff.h"
1889 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
1891 if (arm_pc_is_thumb (memaddr
))
1893 static asymbol
*asym
;
1894 static combined_entry_type ce
;
1895 static struct coff_symbol_struct csym
;
1896 static struct _bfd fake_bfd
;
1897 static bfd_target fake_target
;
1899 if (csym
.native
== NULL
)
1901 /* Create a fake symbol vector containing a Thumb symbol. This is
1902 solely so that the code in print_insn_little_arm() and
1903 print_insn_big_arm() in opcodes/arm-dis.c will detect the presence
1904 of a Thumb symbol and switch to decoding Thumb instructions. */
1906 fake_target
.flavour
= bfd_target_coff_flavour
;
1907 fake_bfd
.xvec
= &fake_target
;
1908 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
1910 csym
.symbol
.the_bfd
= &fake_bfd
;
1911 csym
.symbol
.name
= "fake";
1912 asym
= (asymbol
*) & csym
;
1915 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
1916 info
->symbols
= &asym
;
1919 info
->symbols
= NULL
;
1921 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1922 return print_insn_big_arm (memaddr
, info
);
1924 return print_insn_little_arm (memaddr
, info
);
1927 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the
1928 program counter value to determine whether a 16-bit or 32-bit
1929 breakpoint should be used. It returns a pointer to a string of
1930 bytes that encode a breakpoint instruction, stores the length of
1931 the string to *lenptr, and adjusts the program counter (if
1932 necessary) to point to the actual memory location where the
1933 breakpoint should be inserted. */
1936 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1938 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
1940 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1942 static char thumb_breakpoint
[] = THUMB_BE_BREAKPOINT
;
1943 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1944 *lenptr
= sizeof (thumb_breakpoint
);
1945 return thumb_breakpoint
;
1949 static char thumb_breakpoint
[] = THUMB_LE_BREAKPOINT
;
1950 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1951 *lenptr
= sizeof (thumb_breakpoint
);
1952 return thumb_breakpoint
;
1957 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1959 static char arm_breakpoint
[] = ARM_BE_BREAKPOINT
;
1960 *lenptr
= sizeof (arm_breakpoint
);
1961 return arm_breakpoint
;
1965 static char arm_breakpoint
[] = ARM_LE_BREAKPOINT
;
1966 *lenptr
= sizeof (arm_breakpoint
);
1967 return arm_breakpoint
;
1972 /* Extract from an array REGBUF containing the (raw) register state a
1973 function return value of type TYPE, and copy that, in virtual
1974 format, into VALBUF. */
1977 arm_extract_return_value (struct type
*type
,
1978 char regbuf
[REGISTER_BYTES
],
1981 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
1982 convert_from_extended (®buf
[REGISTER_BYTE (F0_REGNUM
)], valbuf
);
1984 memcpy (valbuf
, ®buf
[REGISTER_BYTE (A1_REGNUM
)], TYPE_LENGTH (type
));
1987 /* Return non-zero if the PC is inside a thumb call thunk. */
1990 arm_in_call_stub (CORE_ADDR pc
, char *name
)
1992 CORE_ADDR start_addr
;
1994 /* Find the starting address of the function containing the PC. If
1995 the caller didn't give us a name, look it up at the same time. */
1996 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
1999 return strncmp (name
, "_call_via_r", 11) == 0;
2002 /* If PC is in a Thumb call or return stub, return the address of the
2003 target PC, which is in a register. The thunk functions are called
2004 _called_via_xx, where x is the register name. The possible names
2005 are r0-r9, sl, fp, ip, sp, and lr. */
2008 arm_skip_stub (CORE_ADDR pc
)
2011 CORE_ADDR start_addr
;
2013 /* Find the starting address and name of the function containing the PC. */
2014 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2017 /* Call thunks always start with "_call_via_". */
2018 if (strncmp (name
, "_call_via_", 10) == 0)
2020 /* Use the name suffix to determine which register contains the
2022 static char *table
[15] =
2023 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2024 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2028 for (regno
= 0; regno
<= 14; regno
++)
2029 if (strcmp (&name
[10], table
[regno
]) == 0)
2030 return read_register (regno
);
2033 return 0; /* not a stub */
2037 _initialize_arm_tdep (void)
2039 struct cmd_list_element
*new_cmd
;
2041 tm_print_insn
= gdb_print_insn_arm
;
2043 /* Sync the opcode insn printer with our register viewer: */
2044 parse_arm_disassembler_option ("reg-names-atpcs");
2046 /* Add the deprecated "othernames" command */
2048 add_com ("othernames", class_obscure
, arm_othernames
,
2049 "Switch to the other set of register names.");
2051 /* Add the disassembly-flavor command */
2053 new_cmd
= add_set_enum_cmd ("disassembly-flavor", no_class
,
2055 (char *) &disassembly_flavor
,
2056 "Set the disassembly flavor, \
2057 the valid values are \"apcs\" and \"r-prefix\", \
2058 and the default value is \"apcs\".",
2060 new_cmd
->function
.sfunc
= set_disassembly_flavor_sfunc
;
2061 add_show_from_set (new_cmd
, &showlist
);
2063 /* ??? Maybe this should be a boolean. */
2064 add_show_from_set (add_set_cmd ("apcs32", no_class
,
2065 var_zinteger
, (char *) &arm_apcs_32
,
2066 "Set usage of ARM 32-bit mode.\n", &setlist
),
2071 /* Test whether the coff symbol specific value corresponds to a Thumb
2075 coff_sym_is_thumb (int val
)
2077 return (val
== C_THUMBEXT
||
2078 val
== C_THUMBSTAT
||
2079 val
== C_THUMBEXTFUNC
||
2080 val
== C_THUMBSTATFUNC
||
2081 val
== C_THUMBLABEL
);