1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2015 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
31 #include "reggroups.h"
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "gdb/sim-arm.h"
52 #include "coff/internal.h"
58 #include "record-full.h"
60 #include "features/arm-with-m.c"
61 #include "features/arm-with-m-fpa-layout.c"
62 #include "features/arm-with-m-vfp-d16.c"
63 #include "features/arm-with-iwmmxt.c"
64 #include "features/arm-with-vfpv2.c"
65 #include "features/arm-with-vfpv3.c"
66 #include "features/arm-with-neon.c"
70 /* Macros for setting and testing a bit in a minimal symbol that marks
71 it as Thumb function. The MSB of the minimal symbol's "info" field
72 is used for this purpose.
74 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
75 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
77 #define MSYMBOL_SET_SPECIAL(msym) \
78 MSYMBOL_TARGET_FLAG_1 (msym) = 1
80 #define MSYMBOL_IS_SPECIAL(msym) \
81 MSYMBOL_TARGET_FLAG_1 (msym)
83 /* Per-objfile data used for mapping symbols. */
84 static const struct objfile_data
*arm_objfile_data_key
;
86 struct arm_mapping_symbol
91 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
92 DEF_VEC_O(arm_mapping_symbol_s
);
94 struct arm_per_objfile
96 VEC(arm_mapping_symbol_s
) **section_maps
;
99 /* The list of available "set arm ..." and "show arm ..." commands. */
100 static struct cmd_list_element
*setarmcmdlist
= NULL
;
101 static struct cmd_list_element
*showarmcmdlist
= NULL
;
103 /* The type of floating-point to use. Keep this in sync with enum
104 arm_float_model, and the help string in _initialize_arm_tdep. */
105 static const char *const fp_model_strings
[] =
115 /* A variable that can be configured by the user. */
116 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
117 static const char *current_fp_model
= "auto";
119 /* The ABI to use. Keep this in sync with arm_abi_kind. */
120 static const char *const arm_abi_strings
[] =
128 /* A variable that can be configured by the user. */
129 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
130 static const char *arm_abi_string
= "auto";
132 /* The execution mode to assume. */
133 static const char *const arm_mode_strings
[] =
141 static const char *arm_fallback_mode_string
= "auto";
142 static const char *arm_force_mode_string
= "auto";
144 /* Internal override of the execution mode. -1 means no override,
145 0 means override to ARM mode, 1 means override to Thumb mode.
146 The effect is the same as if arm_force_mode has been set by the
147 user (except the internal override has precedence over a user's
148 arm_force_mode override). */
149 static int arm_override_mode
= -1;
151 /* Number of different reg name sets (options). */
152 static int num_disassembly_options
;
154 /* The standard register names, and all the valid aliases for them. Note
155 that `fp', `sp' and `pc' are not added in this alias list, because they
156 have been added as builtin user registers in
157 std-regs.c:_initialize_frame_reg. */
162 } arm_register_aliases
[] = {
163 /* Basic register numbers. */
180 /* Synonyms (argument and variable registers). */
193 /* Other platform-specific names for r9. */
199 /* Names used by GCC (not listed in the ARM EABI). */
201 /* A special name from the older ATPCS. */
205 static const char *const arm_register_names
[] =
206 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
207 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
208 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
209 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
210 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
211 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
212 "fps", "cpsr" }; /* 24 25 */
214 /* Valid register name styles. */
215 static const char **valid_disassembly_styles
;
217 /* Disassembly style to use. Default to "std" register names. */
218 static const char *disassembly_style
;
220 /* This is used to keep the bfd arch_info in sync with the disassembly
222 static void set_disassembly_style_sfunc(char *, int,
223 struct cmd_list_element
*);
224 static void set_disassembly_style (void);
226 static void convert_from_extended (const struct floatformat
*, const void *,
228 static void convert_to_extended (const struct floatformat
*, void *,
231 static enum register_status
arm_neon_quad_read (struct gdbarch
*gdbarch
,
232 struct regcache
*regcache
,
233 int regnum
, gdb_byte
*buf
);
234 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
235 struct regcache
*regcache
,
236 int regnum
, const gdb_byte
*buf
);
238 static int thumb_insn_size (unsigned short inst1
);
240 struct arm_prologue_cache
242 /* The stack pointer at the time this frame was created; i.e. the
243 caller's stack pointer when this function was called. It is used
244 to identify this frame. */
247 /* The frame base for this frame is just prev_sp - frame size.
248 FRAMESIZE is the distance from the frame pointer to the
249 initial stack pointer. */
253 /* The register used to hold the frame pointer for this frame. */
256 /* Saved register offsets. */
257 struct trad_frame_saved_reg
*saved_regs
;
260 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
261 CORE_ADDR prologue_start
,
262 CORE_ADDR prologue_end
,
263 struct arm_prologue_cache
*cache
);
265 /* Architecture version for displaced stepping. This effects the behaviour of
266 certain instructions, and really should not be hard-wired. */
268 #define DISPLACED_STEPPING_ARCH_VERSION 5
270 /* Addresses for calling Thumb functions have the bit 0 set.
271 Here are some macros to test, set, or clear bit 0 of addresses. */
272 #define IS_THUMB_ADDR(addr) ((addr) & 1)
273 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
274 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
276 /* Set to true if the 32-bit mode is in use. */
280 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
283 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
285 if (gdbarch_tdep (gdbarch
)->is_m
)
291 /* Determine if FRAME is executing in Thumb mode. */
294 arm_frame_is_thumb (struct frame_info
*frame
)
297 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
299 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
300 directly (from a signal frame or dummy frame) or by interpreting
301 the saved LR (from a prologue or DWARF frame). So consult it and
302 trust the unwinders. */
303 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
305 return (cpsr
& t_bit
) != 0;
308 /* Callback for VEC_lower_bound. */
311 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
312 const struct arm_mapping_symbol
*rhs
)
314 return lhs
->value
< rhs
->value
;
317 /* Search for the mapping symbol covering MEMADDR. If one is found,
318 return its type. Otherwise, return 0. If START is non-NULL,
319 set *START to the location of the mapping symbol. */
322 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
324 struct obj_section
*sec
;
326 /* If there are mapping symbols, consult them. */
327 sec
= find_pc_section (memaddr
);
330 struct arm_per_objfile
*data
;
331 VEC(arm_mapping_symbol_s
) *map
;
332 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
336 data
= objfile_data (sec
->objfile
, arm_objfile_data_key
);
339 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
340 if (!VEC_empty (arm_mapping_symbol_s
, map
))
342 struct arm_mapping_symbol
*map_sym
;
344 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
345 arm_compare_mapping_symbols
);
347 /* VEC_lower_bound finds the earliest ordered insertion
348 point. If the following symbol starts at this exact
349 address, we use that; otherwise, the preceding
350 mapping symbol covers this address. */
351 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
353 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
354 if (map_sym
->value
== map_key
.value
)
357 *start
= map_sym
->value
+ obj_section_addr (sec
);
358 return map_sym
->type
;
364 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
366 *start
= map_sym
->value
+ obj_section_addr (sec
);
367 return map_sym
->type
;
376 /* Determine if the program counter specified in MEMADDR is in a Thumb
377 function. This function should be called for addresses unrelated to
378 any executing frame; otherwise, prefer arm_frame_is_thumb. */
381 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
383 struct bound_minimal_symbol sym
;
385 struct displaced_step_closure
* dsc
386 = get_displaced_step_closure_by_addr(memaddr
);
388 /* If checking the mode of displaced instruction in copy area, the mode
389 should be determined by instruction on the original address. */
393 fprintf_unfiltered (gdb_stdlog
,
394 "displaced: check mode of %.8lx instead of %.8lx\n",
395 (unsigned long) dsc
->insn_addr
,
396 (unsigned long) memaddr
);
397 memaddr
= dsc
->insn_addr
;
400 /* If bit 0 of the address is set, assume this is a Thumb address. */
401 if (IS_THUMB_ADDR (memaddr
))
404 /* Respect internal mode override if active. */
405 if (arm_override_mode
!= -1)
406 return arm_override_mode
;
408 /* If the user wants to override the symbol table, let him. */
409 if (strcmp (arm_force_mode_string
, "arm") == 0)
411 if (strcmp (arm_force_mode_string
, "thumb") == 0)
414 /* ARM v6-M and v7-M are always in Thumb mode. */
415 if (gdbarch_tdep (gdbarch
)->is_m
)
418 /* If there are mapping symbols, consult them. */
419 type
= arm_find_mapping_symbol (memaddr
, NULL
);
423 /* Thumb functions have a "special" bit set in minimal symbols. */
424 sym
= lookup_minimal_symbol_by_pc (memaddr
);
426 return (MSYMBOL_IS_SPECIAL (sym
.minsym
));
428 /* If the user wants to override the fallback mode, let them. */
429 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
431 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
434 /* If we couldn't find any symbol, but we're talking to a running
435 target, then trust the current value of $cpsr. This lets
436 "display/i $pc" always show the correct mode (though if there is
437 a symbol table we will not reach here, so it still may not be
438 displayed in the mode it will be executed). */
439 if (target_has_registers
)
440 return arm_frame_is_thumb (get_current_frame ());
442 /* Otherwise we're out of luck; we assume ARM. */
446 /* Remove useless bits from addresses in a running program. */
448 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
450 /* On M-profile devices, do not strip the low bit from EXC_RETURN
451 (the magic exception return address). */
452 if (gdbarch_tdep (gdbarch
)->is_m
453 && (val
& 0xfffffff0) == 0xfffffff0)
457 return UNMAKE_THUMB_ADDR (val
);
459 return (val
& 0x03fffffc);
462 /* Return 1 if PC is the start of a compiler helper function which
463 can be safely ignored during prologue skipping. IS_THUMB is true
464 if the function is known to be a Thumb function due to the way it
467 skip_prologue_function (struct gdbarch
*gdbarch
, CORE_ADDR pc
, int is_thumb
)
469 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
470 struct bound_minimal_symbol msym
;
472 msym
= lookup_minimal_symbol_by_pc (pc
);
473 if (msym
.minsym
!= NULL
474 && BMSYMBOL_VALUE_ADDRESS (msym
) == pc
475 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
)
477 const char *name
= MSYMBOL_LINKAGE_NAME (msym
.minsym
);
479 /* The GNU linker's Thumb call stub to foo is named
481 if (strstr (name
, "_from_thumb") != NULL
)
484 /* On soft-float targets, __truncdfsf2 is called to convert promoted
485 arguments to their argument types in non-prototyped
487 if (startswith (name
, "__truncdfsf2"))
489 if (startswith (name
, "__aeabi_d2f"))
492 /* Internal functions related to thread-local storage. */
493 if (startswith (name
, "__tls_get_addr"))
495 if (startswith (name
, "__aeabi_read_tp"))
500 /* If we run against a stripped glibc, we may be unable to identify
501 special functions by name. Check for one important case,
502 __aeabi_read_tp, by comparing the *code* against the default
503 implementation (this is hand-written ARM assembler in glibc). */
506 && read_memory_unsigned_integer (pc
, 4, byte_order_for_code
)
507 == 0xe3e00a0f /* mov r0, #0xffff0fff */
508 && read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
)
509 == 0xe240f01f) /* sub pc, r0, #31 */
516 /* Support routines for instruction parsing. */
517 #define submask(x) ((1L << ((x) + 1)) - 1)
518 #define bit(obj,st) (((obj) >> (st)) & 1)
519 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
520 #define sbits(obj,st,fn) \
521 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
522 #define BranchDest(addr,instr) \
523 ((CORE_ADDR) (((unsigned long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
525 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
526 the first 16-bit of instruction, and INSN2 is the second 16-bit of
528 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
529 ((bits ((insn1), 0, 3) << 12) \
530 | (bits ((insn1), 10, 10) << 11) \
531 | (bits ((insn2), 12, 14) << 8) \
532 | bits ((insn2), 0, 7))
534 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
535 the 32-bit instruction. */
536 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
537 ((bits ((insn), 16, 19) << 12) \
538 | bits ((insn), 0, 11))
540 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
543 thumb_expand_immediate (unsigned int imm
)
545 unsigned int count
= imm
>> 7;
553 return (imm
& 0xff) | ((imm
& 0xff) << 16);
555 return ((imm
& 0xff) << 8) | ((imm
& 0xff) << 24);
557 return (imm
& 0xff) | ((imm
& 0xff) << 8)
558 | ((imm
& 0xff) << 16) | ((imm
& 0xff) << 24);
561 return (0x80 | (imm
& 0x7f)) << (32 - count
);
564 /* Return 1 if the 16-bit Thumb instruction INST might change
565 control flow, 0 otherwise. */
568 thumb_instruction_changes_pc (unsigned short inst
)
570 if ((inst
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
573 if ((inst
& 0xf000) == 0xd000) /* conditional branch */
576 if ((inst
& 0xf800) == 0xe000) /* unconditional branch */
579 if ((inst
& 0xff00) == 0x4700) /* bx REG, blx REG */
582 if ((inst
& 0xff87) == 0x4687) /* mov pc, REG */
585 if ((inst
& 0xf500) == 0xb100) /* CBNZ or CBZ. */
591 /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
592 might change control flow, 0 otherwise. */
595 thumb2_instruction_changes_pc (unsigned short inst1
, unsigned short inst2
)
597 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
599 /* Branches and miscellaneous control instructions. */
601 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
606 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
608 /* SUBS PC, LR, #imm8. */
611 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
613 /* Conditional branch. */
620 if ((inst1
& 0xfe50) == 0xe810)
622 /* Load multiple or RFE. */
624 if (bit (inst1
, 7) && !bit (inst1
, 8))
630 else if (!bit (inst1
, 7) && bit (inst1
, 8))
636 else if (bit (inst1
, 7) && bit (inst1
, 8))
641 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
650 if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
652 /* MOV PC or MOVS PC. */
656 if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
659 if (bits (inst1
, 0, 3) == 15)
665 if ((inst2
& 0x0fc0) == 0x0000)
671 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
677 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
686 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
687 epilogue, 0 otherwise. */
690 thumb_instruction_restores_sp (unsigned short insn
)
692 return (insn
== 0x46bd /* mov sp, r7 */
693 || (insn
& 0xff80) == 0xb000 /* add sp, imm */
694 || (insn
& 0xfe00) == 0xbc00); /* pop <registers> */
697 /* Analyze a Thumb prologue, looking for a recognizable stack frame
698 and frame pointer. Scan until we encounter a store that could
699 clobber the stack frame unexpectedly, or an unknown instruction.
700 Return the last address which is definitely safe to skip for an
701 initial breakpoint. */
704 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
705 CORE_ADDR start
, CORE_ADDR limit
,
706 struct arm_prologue_cache
*cache
)
708 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
709 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
712 struct pv_area
*stack
;
713 struct cleanup
*back_to
;
715 CORE_ADDR unrecognized_pc
= 0;
717 for (i
= 0; i
< 16; i
++)
718 regs
[i
] = pv_register (i
, 0);
719 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
720 back_to
= make_cleanup_free_pv_area (stack
);
722 while (start
< limit
)
726 insn
= read_memory_unsigned_integer (start
, 2, byte_order_for_code
);
728 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
733 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
736 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
737 whether to save LR (R14). */
738 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
740 /* Calculate offsets of saved R0-R7 and LR. */
741 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
742 if (mask
& (1 << regno
))
744 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
746 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
749 else if ((insn
& 0xff80) == 0xb080) /* sub sp, #imm */
751 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
752 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
755 else if (thumb_instruction_restores_sp (insn
))
757 /* Don't scan past the epilogue. */
760 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
761 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
763 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
764 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
765 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
767 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
768 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
769 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
771 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
772 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
773 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
774 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
775 regs
[bits (insn
, 6, 8)]);
776 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
777 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
779 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
780 int rm
= bits (insn
, 3, 6);
781 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
783 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
785 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
786 int src_reg
= (insn
& 0x78) >> 3;
787 regs
[dst_reg
] = regs
[src_reg
];
789 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
791 /* Handle stores to the stack. Normally pushes are used,
792 but with GCC -mtpcs-frame, there may be other stores
793 in the prologue to create the frame. */
794 int regno
= (insn
>> 8) & 0x7;
797 offset
= (insn
& 0xff) << 2;
798 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
800 if (pv_area_store_would_trash (stack
, addr
))
803 pv_area_store (stack
, addr
, 4, regs
[regno
]);
805 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
807 int rd
= bits (insn
, 0, 2);
808 int rn
= bits (insn
, 3, 5);
811 offset
= bits (insn
, 6, 10) << 2;
812 addr
= pv_add_constant (regs
[rn
], offset
);
814 if (pv_area_store_would_trash (stack
, addr
))
817 pv_area_store (stack
, addr
, 4, regs
[rd
]);
819 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
820 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
821 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
822 /* Ignore stores of argument registers to the stack. */
824 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
825 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
826 /* Ignore block loads from the stack, potentially copying
827 parameters from memory. */
829 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
830 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
831 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
832 /* Similarly ignore single loads from the stack. */
834 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
835 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
836 /* Skip register copies, i.e. saves to another register
837 instead of the stack. */
839 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
840 /* Recognize constant loads; even with small stacks these are necessary
842 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
843 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
845 /* Constant pool loads, for the same reason. */
846 unsigned int constant
;
849 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
850 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
851 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
853 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instructions. */
855 unsigned short inst2
;
857 inst2
= read_memory_unsigned_integer (start
+ 2, 2,
858 byte_order_for_code
);
860 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
862 /* BL, BLX. Allow some special function calls when
863 skipping the prologue; GCC generates these before
864 storing arguments to the stack. */
866 int j1
, j2
, imm1
, imm2
;
868 imm1
= sbits (insn
, 0, 10);
869 imm2
= bits (inst2
, 0, 10);
870 j1
= bit (inst2
, 13);
871 j2
= bit (inst2
, 11);
873 offset
= ((imm1
<< 12) + (imm2
<< 1));
874 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
876 nextpc
= start
+ 4 + offset
;
877 /* For BLX make sure to clear the low bits. */
878 if (bit (inst2
, 12) == 0)
879 nextpc
= nextpc
& 0xfffffffc;
881 if (!skip_prologue_function (gdbarch
, nextpc
,
882 bit (inst2
, 12) != 0))
886 else if ((insn
& 0xffd0) == 0xe900 /* stmdb Rn{!},
888 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
890 pv_t addr
= regs
[bits (insn
, 0, 3)];
893 if (pv_area_store_would_trash (stack
, addr
))
896 /* Calculate offsets of saved registers. */
897 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
898 if (inst2
& (1 << regno
))
900 addr
= pv_add_constant (addr
, -4);
901 pv_area_store (stack
, addr
, 4, regs
[regno
]);
905 regs
[bits (insn
, 0, 3)] = addr
;
908 else if ((insn
& 0xff50) == 0xe940 /* strd Rt, Rt2,
910 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
912 int regno1
= bits (inst2
, 12, 15);
913 int regno2
= bits (inst2
, 8, 11);
914 pv_t addr
= regs
[bits (insn
, 0, 3)];
916 offset
= inst2
& 0xff;
918 addr
= pv_add_constant (addr
, offset
);
920 addr
= pv_add_constant (addr
, -offset
);
922 if (pv_area_store_would_trash (stack
, addr
))
925 pv_area_store (stack
, addr
, 4, regs
[regno1
]);
926 pv_area_store (stack
, pv_add_constant (addr
, 4),
930 regs
[bits (insn
, 0, 3)] = addr
;
933 else if ((insn
& 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
934 && (inst2
& 0x0c00) == 0x0c00
935 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
937 int regno
= bits (inst2
, 12, 15);
938 pv_t addr
= regs
[bits (insn
, 0, 3)];
940 offset
= inst2
& 0xff;
942 addr
= pv_add_constant (addr
, offset
);
944 addr
= pv_add_constant (addr
, -offset
);
946 if (pv_area_store_would_trash (stack
, addr
))
949 pv_area_store (stack
, addr
, 4, regs
[regno
]);
952 regs
[bits (insn
, 0, 3)] = addr
;
955 else if ((insn
& 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
956 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
958 int regno
= bits (inst2
, 12, 15);
961 offset
= inst2
& 0xfff;
962 addr
= pv_add_constant (regs
[bits (insn
, 0, 3)], offset
);
964 if (pv_area_store_would_trash (stack
, addr
))
967 pv_area_store (stack
, addr
, 4, regs
[regno
]);
970 else if ((insn
& 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
971 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
972 /* Ignore stores of argument registers to the stack. */
975 else if ((insn
& 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
976 && (inst2
& 0x0d00) == 0x0c00
977 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
978 /* Ignore stores of argument registers to the stack. */
981 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!],
983 && (inst2
& 0x8000) == 0x0000
984 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
985 /* Ignore block loads from the stack, potentially copying
986 parameters from memory. */
989 else if ((insn
& 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
991 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
992 /* Similarly ignore dual loads from the stack. */
995 else if ((insn
& 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
996 && (inst2
& 0x0d00) == 0x0c00
997 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
998 /* Similarly ignore single loads from the stack. */
1001 else if ((insn
& 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
1002 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
1003 /* Similarly ignore single loads from the stack. */
1006 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
1007 && (inst2
& 0x8000) == 0x0000)
1009 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1010 | (bits (inst2
, 12, 14) << 8)
1011 | bits (inst2
, 0, 7));
1013 regs
[bits (inst2
, 8, 11)]
1014 = pv_add_constant (regs
[bits (insn
, 0, 3)],
1015 thumb_expand_immediate (imm
));
1018 else if ((insn
& 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
1019 && (inst2
& 0x8000) == 0x0000)
1021 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1022 | (bits (inst2
, 12, 14) << 8)
1023 | bits (inst2
, 0, 7));
1025 regs
[bits (inst2
, 8, 11)]
1026 = pv_add_constant (regs
[bits (insn
, 0, 3)], imm
);
1029 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
1030 && (inst2
& 0x8000) == 0x0000)
1032 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1033 | (bits (inst2
, 12, 14) << 8)
1034 | bits (inst2
, 0, 7));
1036 regs
[bits (inst2
, 8, 11)]
1037 = pv_add_constant (regs
[bits (insn
, 0, 3)],
1038 - (CORE_ADDR
) thumb_expand_immediate (imm
));
1041 else if ((insn
& 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
1042 && (inst2
& 0x8000) == 0x0000)
1044 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1045 | (bits (inst2
, 12, 14) << 8)
1046 | bits (inst2
, 0, 7));
1048 regs
[bits (inst2
, 8, 11)]
1049 = pv_add_constant (regs
[bits (insn
, 0, 3)], - (CORE_ADDR
) imm
);
1052 else if ((insn
& 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1054 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1055 | (bits (inst2
, 12, 14) << 8)
1056 | bits (inst2
, 0, 7));
1058 regs
[bits (inst2
, 8, 11)]
1059 = pv_constant (thumb_expand_immediate (imm
));
1062 else if ((insn
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1065 = EXTRACT_MOVW_MOVT_IMM_T (insn
, inst2
);
1067 regs
[bits (inst2
, 8, 11)] = pv_constant (imm
);
1070 else if (insn
== 0xea5f /* mov.w Rd,Rm */
1071 && (inst2
& 0xf0f0) == 0)
1073 int dst_reg
= (inst2
& 0x0f00) >> 8;
1074 int src_reg
= inst2
& 0xf;
1075 regs
[dst_reg
] = regs
[src_reg
];
1078 else if ((insn
& 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1080 /* Constant pool loads. */
1081 unsigned int constant
;
1084 offset
= bits (inst2
, 0, 11);
1086 loc
= start
+ 4 + offset
;
1088 loc
= start
+ 4 - offset
;
1090 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1091 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1094 else if ((insn
& 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1096 /* Constant pool loads. */
1097 unsigned int constant
;
1100 offset
= bits (inst2
, 0, 7) << 2;
1102 loc
= start
+ 4 + offset
;
1104 loc
= start
+ 4 - offset
;
1106 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1107 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1109 constant
= read_memory_unsigned_integer (loc
+ 4, 4, byte_order
);
1110 regs
[bits (inst2
, 8, 11)] = pv_constant (constant
);
1113 else if (thumb2_instruction_changes_pc (insn
, inst2
))
1115 /* Don't scan past anything that might change control flow. */
1120 /* The optimizer might shove anything into the prologue,
1121 so we just skip what we don't recognize. */
1122 unrecognized_pc
= start
;
1127 else if (thumb_instruction_changes_pc (insn
))
1129 /* Don't scan past anything that might change control flow. */
1134 /* The optimizer might shove anything into the prologue,
1135 so we just skip what we don't recognize. */
1136 unrecognized_pc
= start
;
1143 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1144 paddress (gdbarch
, start
));
1146 if (unrecognized_pc
== 0)
1147 unrecognized_pc
= start
;
1151 do_cleanups (back_to
);
1152 return unrecognized_pc
;
1155 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1157 /* Frame pointer is fp. Frame size is constant. */
1158 cache
->framereg
= ARM_FP_REGNUM
;
1159 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1161 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
1163 /* Frame pointer is r7. Frame size is constant. */
1164 cache
->framereg
= THUMB_FP_REGNUM
;
1165 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
1169 /* Try the stack pointer... this is a bit desperate. */
1170 cache
->framereg
= ARM_SP_REGNUM
;
1171 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1174 for (i
= 0; i
< 16; i
++)
1175 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
1176 cache
->saved_regs
[i
].addr
= offset
;
1178 do_cleanups (back_to
);
1179 return unrecognized_pc
;
1183 /* Try to analyze the instructions starting from PC, which load symbol
1184 __stack_chk_guard. Return the address of instruction after loading this
1185 symbol, set the dest register number to *BASEREG, and set the size of
1186 instructions for loading symbol in OFFSET. Return 0 if instructions are
1190 arm_analyze_load_stack_chk_guard(CORE_ADDR pc
, struct gdbarch
*gdbarch
,
1191 unsigned int *destreg
, int *offset
)
1193 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1194 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1195 unsigned int low
, high
, address
;
1200 unsigned short insn1
1201 = read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
1203 if ((insn1
& 0xf800) == 0x4800) /* ldr Rd, #immed */
1205 *destreg
= bits (insn1
, 8, 10);
1207 address
= (pc
& 0xfffffffc) + 4 + (bits (insn1
, 0, 7) << 2);
1208 address
= read_memory_unsigned_integer (address
, 4,
1209 byte_order_for_code
);
1211 else if ((insn1
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1213 unsigned short insn2
1214 = read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1216 low
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1219 = read_memory_unsigned_integer (pc
+ 4, 2, byte_order_for_code
);
1221 = read_memory_unsigned_integer (pc
+ 6, 2, byte_order_for_code
);
1223 /* movt Rd, #const */
1224 if ((insn1
& 0xfbc0) == 0xf2c0)
1226 high
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1227 *destreg
= bits (insn2
, 8, 11);
1229 address
= (high
<< 16 | low
);
1236 = read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
1238 if ((insn
& 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1240 address
= bits (insn
, 0, 11) + pc
+ 8;
1241 address
= read_memory_unsigned_integer (address
, 4,
1242 byte_order_for_code
);
1244 *destreg
= bits (insn
, 12, 15);
1247 else if ((insn
& 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1249 low
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1252 = read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
);
1254 if ((insn
& 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1256 high
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1257 *destreg
= bits (insn
, 12, 15);
1259 address
= (high
<< 16 | low
);
1267 /* Try to skip a sequence of instructions used for stack protector. If PC
1268 points to the first instruction of this sequence, return the address of
1269 first instruction after this sequence, otherwise, return original PC.
1271 On arm, this sequence of instructions is composed of mainly three steps,
1272 Step 1: load symbol __stack_chk_guard,
1273 Step 2: load from address of __stack_chk_guard,
1274 Step 3: store it to somewhere else.
1276 Usually, instructions on step 2 and step 3 are the same on various ARM
1277 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1278 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1279 instructions in step 1 vary from different ARM architectures. On ARMv7,
1282 movw Rn, #:lower16:__stack_chk_guard
1283 movt Rn, #:upper16:__stack_chk_guard
1290 .word __stack_chk_guard
1292 Since ldr/str is a very popular instruction, we can't use them as
1293 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1294 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1295 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1298 arm_skip_stack_protector(CORE_ADDR pc
, struct gdbarch
*gdbarch
)
1300 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1301 unsigned int basereg
;
1302 struct bound_minimal_symbol stack_chk_guard
;
1304 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1307 /* Try to parse the instructions in Step 1. */
1308 addr
= arm_analyze_load_stack_chk_guard (pc
, gdbarch
,
1313 stack_chk_guard
= lookup_minimal_symbol_by_pc (addr
);
1314 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1315 Otherwise, this sequence cannot be for stack protector. */
1316 if (stack_chk_guard
.minsym
== NULL
1317 || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard
.minsym
), "__stack_chk_guard"))
1322 unsigned int destreg
;
1324 = read_memory_unsigned_integer (pc
+ offset
, 2, byte_order_for_code
);
1326 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1327 if ((insn
& 0xf800) != 0x6800)
1329 if (bits (insn
, 3, 5) != basereg
)
1331 destreg
= bits (insn
, 0, 2);
1333 insn
= read_memory_unsigned_integer (pc
+ offset
+ 2, 2,
1334 byte_order_for_code
);
1335 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1336 if ((insn
& 0xf800) != 0x6000)
1338 if (destreg
!= bits (insn
, 0, 2))
1343 unsigned int destreg
;
1345 = read_memory_unsigned_integer (pc
+ offset
, 4, byte_order_for_code
);
1347 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1348 if ((insn
& 0x0e500000) != 0x04100000)
1350 if (bits (insn
, 16, 19) != basereg
)
1352 destreg
= bits (insn
, 12, 15);
1353 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1354 insn
= read_memory_unsigned_integer (pc
+ offset
+ 4,
1355 4, byte_order_for_code
);
1356 if ((insn
& 0x0e500000) != 0x04000000)
1358 if (bits (insn
, 12, 15) != destreg
)
1361 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1364 return pc
+ offset
+ 4;
1366 return pc
+ offset
+ 8;
1369 /* Advance the PC across any function entry prologue instructions to
1370 reach some "real" code.
1372 The APCS (ARM Procedure Call Standard) defines the following
1376 [stmfd sp!, {a1,a2,a3,a4}]
1377 stmfd sp!, {...,fp,ip,lr,pc}
1378 [stfe f7, [sp, #-12]!]
1379 [stfe f6, [sp, #-12]!]
1380 [stfe f5, [sp, #-12]!]
1381 [stfe f4, [sp, #-12]!]
1382 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1385 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1387 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1389 CORE_ADDR func_addr
, limit_pc
;
1391 /* See if we can determine the end of the prologue via the symbol table.
1392 If so, then return either PC, or the PC after the prologue, whichever
1394 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1396 CORE_ADDR post_prologue_pc
1397 = skip_prologue_using_sal (gdbarch
, func_addr
);
1398 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1400 if (post_prologue_pc
)
1402 = arm_skip_stack_protector (post_prologue_pc
, gdbarch
);
1405 /* GCC always emits a line note before the prologue and another
1406 one after, even if the two are at the same address or on the
1407 same line. Take advantage of this so that we do not need to
1408 know every instruction that might appear in the prologue. We
1409 will have producer information for most binaries; if it is
1410 missing (e.g. for -gstabs), assuming the GNU tools. */
1411 if (post_prologue_pc
1413 || COMPUNIT_PRODUCER (cust
) == NULL
1414 || startswith (COMPUNIT_PRODUCER (cust
), "GNU ")
1415 || startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
1416 return post_prologue_pc
;
1418 if (post_prologue_pc
!= 0)
1420 CORE_ADDR analyzed_limit
;
1422 /* For non-GCC compilers, make sure the entire line is an
1423 acceptable prologue; GDB will round this function's
1424 return value up to the end of the following line so we
1425 can not skip just part of a line (and we do not want to).
1427 RealView does not treat the prologue specially, but does
1428 associate prologue code with the opening brace; so this
1429 lets us skip the first line if we think it is the opening
1431 if (arm_pc_is_thumb (gdbarch
, func_addr
))
1432 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
1433 post_prologue_pc
, NULL
);
1435 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
1436 post_prologue_pc
, NULL
);
1438 if (analyzed_limit
!= post_prologue_pc
)
1441 return post_prologue_pc
;
1445 /* Can't determine prologue from the symbol table, need to examine
1448 /* Find an upper limit on the function prologue using the debug
1449 information. If the debug information could not be used to provide
1450 that bound, then use an arbitrary large number as the upper bound. */
1451 /* Like arm_scan_prologue, stop no later than pc + 64. */
1452 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1454 limit_pc
= pc
+ 64; /* Magic. */
1457 /* Check if this is Thumb code. */
1458 if (arm_pc_is_thumb (gdbarch
, pc
))
1459 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1461 return arm_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1465 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1466 This function decodes a Thumb function prologue to determine:
1467 1) the size of the stack frame
1468 2) which registers are saved on it
1469 3) the offsets of saved regs
1470 4) the offset from the stack pointer to the frame pointer
1472 A typical Thumb function prologue would create this stack frame
1473 (offsets relative to FP)
1474 old SP -> 24 stack parameters
1477 R7 -> 0 local variables (16 bytes)
1478 SP -> -12 additional stack space (12 bytes)
1479 The frame size would thus be 36 bytes, and the frame offset would be
1480 12 bytes. The frame register is R7.
1482 The comments for thumb_skip_prolog() describe the algorithm we use
1483 to detect the end of the prolog. */
1487 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
1488 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
1490 CORE_ADDR prologue_start
;
1491 CORE_ADDR prologue_end
;
1493 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1496 /* See comment in arm_scan_prologue for an explanation of
1498 if (prologue_end
> prologue_start
+ 64)
1500 prologue_end
= prologue_start
+ 64;
1504 /* We're in the boondocks: we have no idea where the start of the
1508 prologue_end
= min (prologue_end
, prev_pc
);
1510 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1513 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
1516 arm_instruction_changes_pc (uint32_t this_instr
)
1518 if (bits (this_instr
, 28, 31) == INST_NV
)
1519 /* Unconditional instructions. */
1520 switch (bits (this_instr
, 24, 27))
1524 /* Branch with Link and change to Thumb. */
1529 /* Coprocessor register transfer. */
1530 if (bits (this_instr
, 12, 15) == 15)
1531 error (_("Invalid update to pc in instruction"));
1537 switch (bits (this_instr
, 25, 27))
1540 if (bits (this_instr
, 23, 24) == 2 && bit (this_instr
, 20) == 0)
1542 /* Multiplies and extra load/stores. */
1543 if (bit (this_instr
, 4) == 1 && bit (this_instr
, 7) == 1)
1544 /* Neither multiplies nor extension load/stores are allowed
1548 /* Otherwise, miscellaneous instructions. */
1550 /* BX <reg>, BXJ <reg>, BLX <reg> */
1551 if (bits (this_instr
, 4, 27) == 0x12fff1
1552 || bits (this_instr
, 4, 27) == 0x12fff2
1553 || bits (this_instr
, 4, 27) == 0x12fff3)
1556 /* Other miscellaneous instructions are unpredictable if they
1560 /* Data processing instruction. Fall through. */
1563 if (bits (this_instr
, 12, 15) == 15)
1570 /* Media instructions and architecturally undefined instructions. */
1571 if (bits (this_instr
, 25, 27) == 3 && bit (this_instr
, 4) == 1)
1575 if (bit (this_instr
, 20) == 0)
1579 if (bits (this_instr
, 12, 15) == ARM_PC_REGNUM
)
1585 /* Load/store multiple. */
1586 if (bit (this_instr
, 20) == 1 && bit (this_instr
, 15) == 1)
1592 /* Branch and branch with link. */
1597 /* Coprocessor transfers or SWIs can not affect PC. */
1601 internal_error (__FILE__
, __LINE__
, _("bad value in switch"));
1605 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1609 arm_instruction_restores_sp (unsigned int insn
)
1611 if (bits (insn
, 28, 31) != INST_NV
)
1613 if ((insn
& 0x0df0f000) == 0x0080d000
1614 /* ADD SP (register or immediate). */
1615 || (insn
& 0x0df0f000) == 0x0040d000
1616 /* SUB SP (register or immediate). */
1617 || (insn
& 0x0ffffff0) == 0x01a0d000
1619 || (insn
& 0x0fff0000) == 0x08bd0000
1621 || (insn
& 0x0fff0000) == 0x049d0000)
1622 /* POP of a single register. */
1629 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1630 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1631 fill it in. Return the first address not recognized as a prologue
1634 We recognize all the instructions typically found in ARM prologues,
1635 plus harmless instructions which can be skipped (either for analysis
1636 purposes, or a more restrictive set that can be skipped when finding
1637 the end of the prologue). */
1640 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1641 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1642 struct arm_prologue_cache
*cache
)
1644 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1645 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1647 CORE_ADDR offset
, current_pc
;
1648 pv_t regs
[ARM_FPS_REGNUM
];
1649 struct pv_area
*stack
;
1650 struct cleanup
*back_to
;
1651 CORE_ADDR unrecognized_pc
= 0;
1653 /* Search the prologue looking for instructions that set up the
1654 frame pointer, adjust the stack pointer, and save registers.
1656 Be careful, however, and if it doesn't look like a prologue,
1657 don't try to scan it. If, for instance, a frameless function
1658 begins with stmfd sp!, then we will tell ourselves there is
1659 a frame, which will confuse stack traceback, as well as "finish"
1660 and other operations that rely on a knowledge of the stack
1663 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1664 regs
[regno
] = pv_register (regno
, 0);
1665 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1666 back_to
= make_cleanup_free_pv_area (stack
);
1668 for (current_pc
= prologue_start
;
1669 current_pc
< prologue_end
;
1673 = read_memory_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1675 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1677 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1680 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1681 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1683 unsigned imm
= insn
& 0xff; /* immediate value */
1684 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1685 int rd
= bits (insn
, 12, 15);
1686 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1687 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1690 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1691 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1693 unsigned imm
= insn
& 0xff; /* immediate value */
1694 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1695 int rd
= bits (insn
, 12, 15);
1696 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1697 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1700 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd,
1703 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1705 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1706 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4,
1707 regs
[bits (insn
, 12, 15)]);
1710 else if ((insn
& 0xffff0000) == 0xe92d0000)
1711 /* stmfd sp!, {..., fp, ip, lr, pc}
1713 stmfd sp!, {a1, a2, a3, a4} */
1715 int mask
= insn
& 0xffff;
1717 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1720 /* Calculate offsets of saved registers. */
1721 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1722 if (mask
& (1 << regno
))
1725 = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1726 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1729 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1730 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1731 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1733 /* No need to add this to saved_regs -- it's just an arg reg. */
1736 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1737 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1738 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1740 /* No need to add this to saved_regs -- it's just an arg reg. */
1743 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn,
1745 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1747 /* No need to add this to saved_regs -- it's just arg regs. */
1750 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1752 unsigned imm
= insn
& 0xff; /* immediate value */
1753 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1754 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1755 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1757 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1759 unsigned imm
= insn
& 0xff; /* immediate value */
1760 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1761 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1762 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1764 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?,
1766 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1768 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1771 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1772 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1773 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1775 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1777 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1779 int n_saved_fp_regs
;
1780 unsigned int fp_start_reg
, fp_bound_reg
;
1782 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1785 if ((insn
& 0x800) == 0x800) /* N0 is set */
1787 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1788 n_saved_fp_regs
= 3;
1790 n_saved_fp_regs
= 1;
1794 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1795 n_saved_fp_regs
= 2;
1797 n_saved_fp_regs
= 4;
1800 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1801 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1802 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1804 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1805 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
1806 regs
[fp_start_reg
++]);
1809 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1811 /* Allow some special function calls when skipping the
1812 prologue; GCC generates these before storing arguments to
1814 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1816 if (skip_prologue_function (gdbarch
, dest
, 0))
1821 else if ((insn
& 0xf0000000) != 0xe0000000)
1822 break; /* Condition not true, exit early. */
1823 else if (arm_instruction_changes_pc (insn
))
1824 /* Don't scan past anything that might change control flow. */
1826 else if (arm_instruction_restores_sp (insn
))
1828 /* Don't scan past the epilogue. */
1831 else if ((insn
& 0xfe500000) == 0xe8100000 /* ldm */
1832 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1833 /* Ignore block loads from the stack, potentially copying
1834 parameters from memory. */
1836 else if ((insn
& 0xfc500000) == 0xe4100000
1837 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1838 /* Similarly ignore single loads from the stack. */
1840 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1841 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1842 register instead of the stack. */
1846 /* The optimizer might shove anything into the prologue, if
1847 we build up cache (cache != NULL) from scanning prologue,
1848 we just skip what we don't recognize and scan further to
1849 make cache as complete as possible. However, if we skip
1850 prologue, we'll stop immediately on unrecognized
1852 unrecognized_pc
= current_pc
;
1860 if (unrecognized_pc
== 0)
1861 unrecognized_pc
= current_pc
;
1865 int framereg
, framesize
;
1867 /* The frame size is just the distance from the frame register
1868 to the original stack pointer. */
1869 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1871 /* Frame pointer is fp. */
1872 framereg
= ARM_FP_REGNUM
;
1873 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1877 /* Try the stack pointer... this is a bit desperate. */
1878 framereg
= ARM_SP_REGNUM
;
1879 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1882 cache
->framereg
= framereg
;
1883 cache
->framesize
= framesize
;
1885 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1886 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1887 cache
->saved_regs
[regno
].addr
= offset
;
1891 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1892 paddress (gdbarch
, unrecognized_pc
));
1894 do_cleanups (back_to
);
1895 return unrecognized_pc
;
1899 arm_scan_prologue (struct frame_info
*this_frame
,
1900 struct arm_prologue_cache
*cache
)
1902 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1903 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1905 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
1906 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1907 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1908 pv_t regs
[ARM_FPS_REGNUM
];
1909 struct pv_area
*stack
;
1910 struct cleanup
*back_to
;
1913 /* Assume there is no frame until proven otherwise. */
1914 cache
->framereg
= ARM_SP_REGNUM
;
1915 cache
->framesize
= 0;
1917 /* Check for Thumb prologue. */
1918 if (arm_frame_is_thumb (this_frame
))
1920 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1924 /* Find the function prologue. If we can't find the function in
1925 the symbol table, peek in the stack frame to find the PC. */
1926 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1929 /* One way to find the end of the prologue (which works well
1930 for unoptimized code) is to do the following:
1932 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1935 prologue_end = prev_pc;
1936 else if (sal.end < prologue_end)
1937 prologue_end = sal.end;
1939 This mechanism is very accurate so long as the optimizer
1940 doesn't move any instructions from the function body into the
1941 prologue. If this happens, sal.end will be the last
1942 instruction in the first hunk of prologue code just before
1943 the first instruction that the scheduler has moved from
1944 the body to the prologue.
1946 In order to make sure that we scan all of the prologue
1947 instructions, we use a slightly less accurate mechanism which
1948 may scan more than necessary. To help compensate for this
1949 lack of accuracy, the prologue scanning loop below contains
1950 several clauses which'll cause the loop to terminate early if
1951 an implausible prologue instruction is encountered.
1957 is a suitable endpoint since it accounts for the largest
1958 possible prologue plus up to five instructions inserted by
1961 if (prologue_end
> prologue_start
+ 64)
1963 prologue_end
= prologue_start
+ 64; /* See above. */
1968 /* We have no symbol information. Our only option is to assume this
1969 function has a standard stack frame and the normal frame register.
1970 Then, we can find the value of our frame pointer on entrance to
1971 the callee (or at the present moment if this is the innermost frame).
1972 The value stored there should be the address of the stmfd + 8. */
1973 CORE_ADDR frame_loc
;
1974 LONGEST return_value
;
1976 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
1977 if (!safe_read_memory_integer (frame_loc
, 4, byte_order
, &return_value
))
1981 prologue_start
= gdbarch_addr_bits_remove
1982 (gdbarch
, return_value
) - 8;
1983 prologue_end
= prologue_start
+ 64; /* See above. */
1987 if (prev_pc
< prologue_end
)
1988 prologue_end
= prev_pc
;
1990 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1993 static struct arm_prologue_cache
*
1994 arm_make_prologue_cache (struct frame_info
*this_frame
)
1997 struct arm_prologue_cache
*cache
;
1998 CORE_ADDR unwound_fp
;
2000 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2001 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2003 arm_scan_prologue (this_frame
, cache
);
2005 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
2006 if (unwound_fp
== 0)
2009 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
2011 /* Calculate actual addresses of saved registers using offsets
2012 determined by arm_scan_prologue. */
2013 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
2014 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
2015 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
2020 /* Implementation of the stop_reason hook for arm_prologue frames. */
2022 static enum unwind_stop_reason
2023 arm_prologue_unwind_stop_reason (struct frame_info
*this_frame
,
2026 struct arm_prologue_cache
*cache
;
2029 if (*this_cache
== NULL
)
2030 *this_cache
= arm_make_prologue_cache (this_frame
);
2031 cache
= *this_cache
;
2033 /* This is meant to halt the backtrace at "_start". */
2034 pc
= get_frame_pc (this_frame
);
2035 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
2036 return UNWIND_OUTERMOST
;
2038 /* If we've hit a wall, stop. */
2039 if (cache
->prev_sp
== 0)
2040 return UNWIND_OUTERMOST
;
2042 return UNWIND_NO_REASON
;
2045 /* Our frame ID for a normal frame is the current function's starting PC
2046 and the caller's SP when we were called. */
2049 arm_prologue_this_id (struct frame_info
*this_frame
,
2051 struct frame_id
*this_id
)
2053 struct arm_prologue_cache
*cache
;
2057 if (*this_cache
== NULL
)
2058 *this_cache
= arm_make_prologue_cache (this_frame
);
2059 cache
= *this_cache
;
2061 /* Use function start address as part of the frame ID. If we cannot
2062 identify the start address (due to missing symbol information),
2063 fall back to just using the current PC. */
2064 pc
= get_frame_pc (this_frame
);
2065 func
= get_frame_func (this_frame
);
2069 id
= frame_id_build (cache
->prev_sp
, func
);
2073 static struct value
*
2074 arm_prologue_prev_register (struct frame_info
*this_frame
,
2078 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2079 struct arm_prologue_cache
*cache
;
2081 if (*this_cache
== NULL
)
2082 *this_cache
= arm_make_prologue_cache (this_frame
);
2083 cache
= *this_cache
;
2085 /* If we are asked to unwind the PC, then we need to return the LR
2086 instead. The prologue may save PC, but it will point into this
2087 frame's prologue, not the next frame's resume location. Also
2088 strip the saved T bit. A valid LR may have the low bit set, but
2089 a valid PC never does. */
2090 if (prev_regnum
== ARM_PC_REGNUM
)
2094 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2095 return frame_unwind_got_constant (this_frame
, prev_regnum
,
2096 arm_addr_bits_remove (gdbarch
, lr
));
2099 /* SP is generally not saved to the stack, but this frame is
2100 identified by the next frame's stack pointer at the time of the call.
2101 The value was already reconstructed into PREV_SP. */
2102 if (prev_regnum
== ARM_SP_REGNUM
)
2103 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
2105 /* The CPSR may have been changed by the call instruction and by the
2106 called function. The only bit we can reconstruct is the T bit,
2107 by checking the low bit of LR as of the call. This is a reliable
2108 indicator of Thumb-ness except for some ARM v4T pre-interworking
2109 Thumb code, which could get away with a clear low bit as long as
2110 the called function did not use bx. Guess that all other
2111 bits are unchanged; the condition flags are presumably lost,
2112 but the processor status is likely valid. */
2113 if (prev_regnum
== ARM_PS_REGNUM
)
2116 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
2118 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
2119 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2120 if (IS_THUMB_ADDR (lr
))
2124 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
2127 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
2131 struct frame_unwind arm_prologue_unwind
= {
2133 arm_prologue_unwind_stop_reason
,
2134 arm_prologue_this_id
,
2135 arm_prologue_prev_register
,
2137 default_frame_sniffer
2140 /* Maintain a list of ARM exception table entries per objfile, similar to the
2141 list of mapping symbols. We only cache entries for standard ARM-defined
2142 personality routines; the cache will contain only the frame unwinding
2143 instructions associated with the entry (not the descriptors). */
2145 static const struct objfile_data
*arm_exidx_data_key
;
2147 struct arm_exidx_entry
2152 typedef struct arm_exidx_entry arm_exidx_entry_s
;
2153 DEF_VEC_O(arm_exidx_entry_s
);
2155 struct arm_exidx_data
2157 VEC(arm_exidx_entry_s
) **section_maps
;
2161 arm_exidx_data_free (struct objfile
*objfile
, void *arg
)
2163 struct arm_exidx_data
*data
= arg
;
2166 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
2167 VEC_free (arm_exidx_entry_s
, data
->section_maps
[i
]);
2171 arm_compare_exidx_entries (const struct arm_exidx_entry
*lhs
,
2172 const struct arm_exidx_entry
*rhs
)
2174 return lhs
->addr
< rhs
->addr
;
2177 static struct obj_section
*
2178 arm_obj_section_from_vma (struct objfile
*objfile
, bfd_vma vma
)
2180 struct obj_section
*osect
;
2182 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
2183 if (bfd_get_section_flags (objfile
->obfd
,
2184 osect
->the_bfd_section
) & SEC_ALLOC
)
2186 bfd_vma start
, size
;
2187 start
= bfd_get_section_vma (objfile
->obfd
, osect
->the_bfd_section
);
2188 size
= bfd_get_section_size (osect
->the_bfd_section
);
2190 if (start
<= vma
&& vma
< start
+ size
)
2197 /* Parse contents of exception table and exception index sections
2198 of OBJFILE, and fill in the exception table entry cache.
2200 For each entry that refers to a standard ARM-defined personality
2201 routine, extract the frame unwinding instructions (from either
2202 the index or the table section). The unwinding instructions
2204 - extracting them from the rest of the table data
2205 - converting to host endianness
2206 - appending the implicit 0xb0 ("Finish") code
2208 The extracted and normalized instructions are stored for later
2209 retrieval by the arm_find_exidx_entry routine. */
2212 arm_exidx_new_objfile (struct objfile
*objfile
)
2214 struct cleanup
*cleanups
;
2215 struct arm_exidx_data
*data
;
2216 asection
*exidx
, *extab
;
2217 bfd_vma exidx_vma
= 0, extab_vma
= 0;
2218 bfd_size_type exidx_size
= 0, extab_size
= 0;
2219 gdb_byte
*exidx_data
= NULL
, *extab_data
= NULL
;
2222 /* If we've already touched this file, do nothing. */
2223 if (!objfile
|| objfile_data (objfile
, arm_exidx_data_key
) != NULL
)
2225 cleanups
= make_cleanup (null_cleanup
, NULL
);
2227 /* Read contents of exception table and index. */
2228 exidx
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.exidx");
2231 exidx_vma
= bfd_section_vma (objfile
->obfd
, exidx
);
2232 exidx_size
= bfd_get_section_size (exidx
);
2233 exidx_data
= xmalloc (exidx_size
);
2234 make_cleanup (xfree
, exidx_data
);
2236 if (!bfd_get_section_contents (objfile
->obfd
, exidx
,
2237 exidx_data
, 0, exidx_size
))
2239 do_cleanups (cleanups
);
2244 extab
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.extab");
2247 extab_vma
= bfd_section_vma (objfile
->obfd
, extab
);
2248 extab_size
= bfd_get_section_size (extab
);
2249 extab_data
= xmalloc (extab_size
);
2250 make_cleanup (xfree
, extab_data
);
2252 if (!bfd_get_section_contents (objfile
->obfd
, extab
,
2253 extab_data
, 0, extab_size
))
2255 do_cleanups (cleanups
);
2260 /* Allocate exception table data structure. */
2261 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
, struct arm_exidx_data
);
2262 set_objfile_data (objfile
, arm_exidx_data_key
, data
);
2263 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2264 objfile
->obfd
->section_count
,
2265 VEC(arm_exidx_entry_s
) *);
2267 /* Fill in exception table. */
2268 for (i
= 0; i
< exidx_size
/ 8; i
++)
2270 struct arm_exidx_entry new_exidx_entry
;
2271 bfd_vma idx
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8);
2272 bfd_vma val
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8 + 4);
2273 bfd_vma addr
= 0, word
= 0;
2274 int n_bytes
= 0, n_words
= 0;
2275 struct obj_section
*sec
;
2276 gdb_byte
*entry
= NULL
;
2278 /* Extract address of start of function. */
2279 idx
= ((idx
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2280 idx
+= exidx_vma
+ i
* 8;
2282 /* Find section containing function and compute section offset. */
2283 sec
= arm_obj_section_from_vma (objfile
, idx
);
2286 idx
-= bfd_get_section_vma (objfile
->obfd
, sec
->the_bfd_section
);
2288 /* Determine address of exception table entry. */
2291 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2293 else if ((val
& 0xff000000) == 0x80000000)
2295 /* Exception table entry embedded in .ARM.exidx
2296 -- must be short form. */
2300 else if (!(val
& 0x80000000))
2302 /* Exception table entry in .ARM.extab. */
2303 addr
= ((val
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2304 addr
+= exidx_vma
+ i
* 8 + 4;
2306 if (addr
>= extab_vma
&& addr
+ 4 <= extab_vma
+ extab_size
)
2308 word
= bfd_h_get_32 (objfile
->obfd
,
2309 extab_data
+ addr
- extab_vma
);
2312 if ((word
& 0xff000000) == 0x80000000)
2317 else if ((word
& 0xff000000) == 0x81000000
2318 || (word
& 0xff000000) == 0x82000000)
2322 n_words
= ((word
>> 16) & 0xff);
2324 else if (!(word
& 0x80000000))
2327 struct obj_section
*pers_sec
;
2328 int gnu_personality
= 0;
2330 /* Custom personality routine. */
2331 pers
= ((word
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2332 pers
= UNMAKE_THUMB_ADDR (pers
+ addr
- 4);
2334 /* Check whether we've got one of the variants of the
2335 GNU personality routines. */
2336 pers_sec
= arm_obj_section_from_vma (objfile
, pers
);
2339 static const char *personality
[] =
2341 "__gcc_personality_v0",
2342 "__gxx_personality_v0",
2343 "__gcj_personality_v0",
2344 "__gnu_objc_personality_v0",
2348 CORE_ADDR pc
= pers
+ obj_section_offset (pers_sec
);
2351 for (k
= 0; personality
[k
]; k
++)
2352 if (lookup_minimal_symbol_by_pc_name
2353 (pc
, personality
[k
], objfile
))
2355 gnu_personality
= 1;
2360 /* If so, the next word contains a word count in the high
2361 byte, followed by the same unwind instructions as the
2362 pre-defined forms. */
2364 && addr
+ 4 <= extab_vma
+ extab_size
)
2366 word
= bfd_h_get_32 (objfile
->obfd
,
2367 extab_data
+ addr
- extab_vma
);
2370 n_words
= ((word
>> 24) & 0xff);
2376 /* Sanity check address. */
2378 if (addr
< extab_vma
|| addr
+ 4 * n_words
> extab_vma
+ extab_size
)
2379 n_words
= n_bytes
= 0;
2381 /* The unwind instructions reside in WORD (only the N_BYTES least
2382 significant bytes are valid), followed by N_WORDS words in the
2383 extab section starting at ADDR. */
2384 if (n_bytes
|| n_words
)
2386 gdb_byte
*p
= entry
= obstack_alloc (&objfile
->objfile_obstack
,
2387 n_bytes
+ n_words
* 4 + 1);
2390 *p
++ = (gdb_byte
) ((word
>> (8 * n_bytes
)) & 0xff);
2394 word
= bfd_h_get_32 (objfile
->obfd
,
2395 extab_data
+ addr
- extab_vma
);
2398 *p
++ = (gdb_byte
) ((word
>> 24) & 0xff);
2399 *p
++ = (gdb_byte
) ((word
>> 16) & 0xff);
2400 *p
++ = (gdb_byte
) ((word
>> 8) & 0xff);
2401 *p
++ = (gdb_byte
) (word
& 0xff);
2404 /* Implied "Finish" to terminate the list. */
2408 /* Push entry onto vector. They are guaranteed to always
2409 appear in order of increasing addresses. */
2410 new_exidx_entry
.addr
= idx
;
2411 new_exidx_entry
.entry
= entry
;
2412 VEC_safe_push (arm_exidx_entry_s
,
2413 data
->section_maps
[sec
->the_bfd_section
->index
],
2417 do_cleanups (cleanups
);
2420 /* Search for the exception table entry covering MEMADDR. If one is found,
2421 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2422 set *START to the start of the region covered by this entry. */
2425 arm_find_exidx_entry (CORE_ADDR memaddr
, CORE_ADDR
*start
)
2427 struct obj_section
*sec
;
2429 sec
= find_pc_section (memaddr
);
2432 struct arm_exidx_data
*data
;
2433 VEC(arm_exidx_entry_s
) *map
;
2434 struct arm_exidx_entry map_key
= { memaddr
- obj_section_addr (sec
), 0 };
2437 data
= objfile_data (sec
->objfile
, arm_exidx_data_key
);
2440 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
2441 if (!VEC_empty (arm_exidx_entry_s
, map
))
2443 struct arm_exidx_entry
*map_sym
;
2445 idx
= VEC_lower_bound (arm_exidx_entry_s
, map
, &map_key
,
2446 arm_compare_exidx_entries
);
2448 /* VEC_lower_bound finds the earliest ordered insertion
2449 point. If the following symbol starts at this exact
2450 address, we use that; otherwise, the preceding
2451 exception table entry covers this address. */
2452 if (idx
< VEC_length (arm_exidx_entry_s
, map
))
2454 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
);
2455 if (map_sym
->addr
== map_key
.addr
)
2458 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2459 return map_sym
->entry
;
2465 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
- 1);
2467 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2468 return map_sym
->entry
;
2477 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2478 instruction list from the ARM exception table entry ENTRY, allocate and
2479 return a prologue cache structure describing how to unwind this frame.
2481 Return NULL if the unwinding instruction list contains a "spare",
2482 "reserved" or "refuse to unwind" instruction as defined in section
2483 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2484 for the ARM Architecture" document. */
2486 static struct arm_prologue_cache
*
2487 arm_exidx_fill_cache (struct frame_info
*this_frame
, gdb_byte
*entry
)
2492 struct arm_prologue_cache
*cache
;
2493 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2494 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2500 /* Whenever we reload SP, we actually have to retrieve its
2501 actual value in the current frame. */
2504 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2506 int reg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2507 vsp
= get_frame_register_unsigned (this_frame
, reg
);
2511 CORE_ADDR addr
= cache
->saved_regs
[ARM_SP_REGNUM
].addr
;
2512 vsp
= get_frame_memory_unsigned (this_frame
, addr
, 4);
2518 /* Decode next unwind instruction. */
2521 if ((insn
& 0xc0) == 0)
2523 int offset
= insn
& 0x3f;
2524 vsp
+= (offset
<< 2) + 4;
2526 else if ((insn
& 0xc0) == 0x40)
2528 int offset
= insn
& 0x3f;
2529 vsp
-= (offset
<< 2) + 4;
2531 else if ((insn
& 0xf0) == 0x80)
2533 int mask
= ((insn
& 0xf) << 8) | *entry
++;
2536 /* The special case of an all-zero mask identifies
2537 "Refuse to unwind". We return NULL to fall back
2538 to the prologue analyzer. */
2542 /* Pop registers r4..r15 under mask. */
2543 for (i
= 0; i
< 12; i
++)
2544 if (mask
& (1 << i
))
2546 cache
->saved_regs
[4 + i
].addr
= vsp
;
2550 /* Special-case popping SP -- we need to reload vsp. */
2551 if (mask
& (1 << (ARM_SP_REGNUM
- 4)))
2554 else if ((insn
& 0xf0) == 0x90)
2556 int reg
= insn
& 0xf;
2558 /* Reserved cases. */
2559 if (reg
== ARM_SP_REGNUM
|| reg
== ARM_PC_REGNUM
)
2562 /* Set SP from another register and mark VSP for reload. */
2563 cache
->saved_regs
[ARM_SP_REGNUM
] = cache
->saved_regs
[reg
];
2566 else if ((insn
& 0xf0) == 0xa0)
2568 int count
= insn
& 0x7;
2569 int pop_lr
= (insn
& 0x8) != 0;
2572 /* Pop r4..r[4+count]. */
2573 for (i
= 0; i
<= count
; i
++)
2575 cache
->saved_regs
[4 + i
].addr
= vsp
;
2579 /* If indicated by flag, pop LR as well. */
2582 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= vsp
;
2586 else if (insn
== 0xb0)
2588 /* We could only have updated PC by popping into it; if so, it
2589 will show up as address. Otherwise, copy LR into PC. */
2590 if (!trad_frame_addr_p (cache
->saved_regs
, ARM_PC_REGNUM
))
2591 cache
->saved_regs
[ARM_PC_REGNUM
]
2592 = cache
->saved_regs
[ARM_LR_REGNUM
];
2597 else if (insn
== 0xb1)
2599 int mask
= *entry
++;
2602 /* All-zero mask and mask >= 16 is "spare". */
2603 if (mask
== 0 || mask
>= 16)
2606 /* Pop r0..r3 under mask. */
2607 for (i
= 0; i
< 4; i
++)
2608 if (mask
& (1 << i
))
2610 cache
->saved_regs
[i
].addr
= vsp
;
2614 else if (insn
== 0xb2)
2616 ULONGEST offset
= 0;
2621 offset
|= (*entry
& 0x7f) << shift
;
2624 while (*entry
++ & 0x80);
2626 vsp
+= 0x204 + (offset
<< 2);
2628 else if (insn
== 0xb3)
2630 int start
= *entry
>> 4;
2631 int count
= (*entry
++) & 0xf;
2634 /* Only registers D0..D15 are valid here. */
2635 if (start
+ count
>= 16)
2638 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2639 for (i
= 0; i
<= count
; i
++)
2641 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2645 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2648 else if ((insn
& 0xf8) == 0xb8)
2650 int count
= insn
& 0x7;
2653 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2654 for (i
= 0; i
<= count
; i
++)
2656 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2660 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2663 else if (insn
== 0xc6)
2665 int start
= *entry
>> 4;
2666 int count
= (*entry
++) & 0xf;
2669 /* Only registers WR0..WR15 are valid. */
2670 if (start
+ count
>= 16)
2673 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2674 for (i
= 0; i
<= count
; i
++)
2676 cache
->saved_regs
[ARM_WR0_REGNUM
+ start
+ i
].addr
= vsp
;
2680 else if (insn
== 0xc7)
2682 int mask
= *entry
++;
2685 /* All-zero mask and mask >= 16 is "spare". */
2686 if (mask
== 0 || mask
>= 16)
2689 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2690 for (i
= 0; i
< 4; i
++)
2691 if (mask
& (1 << i
))
2693 cache
->saved_regs
[ARM_WCGR0_REGNUM
+ i
].addr
= vsp
;
2697 else if ((insn
& 0xf8) == 0xc0)
2699 int count
= insn
& 0x7;
2702 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2703 for (i
= 0; i
<= count
; i
++)
2705 cache
->saved_regs
[ARM_WR0_REGNUM
+ 10 + i
].addr
= vsp
;
2709 else if (insn
== 0xc8)
2711 int start
= *entry
>> 4;
2712 int count
= (*entry
++) & 0xf;
2715 /* Only registers D0..D31 are valid. */
2716 if (start
+ count
>= 16)
2719 /* Pop VFP double-precision registers
2720 D[16+start]..D[16+start+count]. */
2721 for (i
= 0; i
<= count
; i
++)
2723 cache
->saved_regs
[ARM_D0_REGNUM
+ 16 + start
+ i
].addr
= vsp
;
2727 else if (insn
== 0xc9)
2729 int start
= *entry
>> 4;
2730 int count
= (*entry
++) & 0xf;
2733 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2734 for (i
= 0; i
<= count
; i
++)
2736 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2740 else if ((insn
& 0xf8) == 0xd0)
2742 int count
= insn
& 0x7;
2745 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2746 for (i
= 0; i
<= count
; i
++)
2748 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2754 /* Everything else is "spare". */
2759 /* If we restore SP from a register, assume this was the frame register.
2760 Otherwise just fall back to SP as frame register. */
2761 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2762 cache
->framereg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2764 cache
->framereg
= ARM_SP_REGNUM
;
2766 /* Determine offset to previous frame. */
2768 = vsp
- get_frame_register_unsigned (this_frame
, cache
->framereg
);
2770 /* We already got the previous SP. */
2771 cache
->prev_sp
= vsp
;
2776 /* Unwinding via ARM exception table entries. Note that the sniffer
2777 already computes a filled-in prologue cache, which is then used
2778 with the same arm_prologue_this_id and arm_prologue_prev_register
2779 routines also used for prologue-parsing based unwinding. */
2782 arm_exidx_unwind_sniffer (const struct frame_unwind
*self
,
2783 struct frame_info
*this_frame
,
2784 void **this_prologue_cache
)
2786 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2787 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2788 CORE_ADDR addr_in_block
, exidx_region
, func_start
;
2789 struct arm_prologue_cache
*cache
;
2792 /* See if we have an ARM exception table entry covering this address. */
2793 addr_in_block
= get_frame_address_in_block (this_frame
);
2794 entry
= arm_find_exidx_entry (addr_in_block
, &exidx_region
);
2798 /* The ARM exception table does not describe unwind information
2799 for arbitrary PC values, but is guaranteed to be correct only
2800 at call sites. We have to decide here whether we want to use
2801 ARM exception table information for this frame, or fall back
2802 to using prologue parsing. (Note that if we have DWARF CFI,
2803 this sniffer isn't even called -- CFI is always preferred.)
2805 Before we make this decision, however, we check whether we
2806 actually have *symbol* information for the current frame.
2807 If not, prologue parsing would not work anyway, so we might
2808 as well use the exception table and hope for the best. */
2809 if (find_pc_partial_function (addr_in_block
, NULL
, &func_start
, NULL
))
2813 /* If the next frame is "normal", we are at a call site in this
2814 frame, so exception information is guaranteed to be valid. */
2815 if (get_next_frame (this_frame
)
2816 && get_frame_type (get_next_frame (this_frame
)) == NORMAL_FRAME
)
2819 /* We also assume exception information is valid if we're currently
2820 blocked in a system call. The system library is supposed to
2821 ensure this, so that e.g. pthread cancellation works. */
2822 if (arm_frame_is_thumb (this_frame
))
2826 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 2, 2,
2827 byte_order_for_code
, &insn
)
2828 && (insn
& 0xff00) == 0xdf00 /* svc */)
2835 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 4, 4,
2836 byte_order_for_code
, &insn
)
2837 && (insn
& 0x0f000000) == 0x0f000000 /* svc */)
2841 /* Bail out if we don't know that exception information is valid. */
2845 /* The ARM exception index does not mark the *end* of the region
2846 covered by the entry, and some functions will not have any entry.
2847 To correctly recognize the end of the covered region, the linker
2848 should have inserted dummy records with a CANTUNWIND marker.
2850 Unfortunately, current versions of GNU ld do not reliably do
2851 this, and thus we may have found an incorrect entry above.
2852 As a (temporary) sanity check, we only use the entry if it
2853 lies *within* the bounds of the function. Note that this check
2854 might reject perfectly valid entries that just happen to cover
2855 multiple functions; therefore this check ought to be removed
2856 once the linker is fixed. */
2857 if (func_start
> exidx_region
)
2861 /* Decode the list of unwinding instructions into a prologue cache.
2862 Note that this may fail due to e.g. a "refuse to unwind" code. */
2863 cache
= arm_exidx_fill_cache (this_frame
, entry
);
2867 *this_prologue_cache
= cache
;
2871 struct frame_unwind arm_exidx_unwind
= {
2873 default_frame_unwind_stop_reason
,
2874 arm_prologue_this_id
,
2875 arm_prologue_prev_register
,
2877 arm_exidx_unwind_sniffer
2880 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2881 trampoline, return the target PC. Otherwise return 0.
2883 void call0a (char c, short s, int i, long l) {}
2887 (*pointer_to_call0a) (c, s, i, l);
2890 Instead of calling a stub library function _call_via_xx (xx is
2891 the register name), GCC may inline the trampoline in the object
2892 file as below (register r2 has the address of call0a).
2895 .type main, %function
2904 The trampoline 'bx r2' doesn't belong to main. */
2907 arm_skip_bx_reg (struct frame_info
*frame
, CORE_ADDR pc
)
2909 /* The heuristics of recognizing such trampoline is that FRAME is
2910 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2911 if (arm_frame_is_thumb (frame
))
2915 if (target_read_memory (pc
, buf
, 2) == 0)
2917 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2918 enum bfd_endian byte_order_for_code
2919 = gdbarch_byte_order_for_code (gdbarch
);
2921 = extract_unsigned_integer (buf
, 2, byte_order_for_code
);
2923 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
2926 = get_frame_register_unsigned (frame
, bits (insn
, 3, 6));
2928 /* Clear the LSB so that gdb core sets step-resume
2929 breakpoint at the right address. */
2930 return UNMAKE_THUMB_ADDR (dest
);
2938 static struct arm_prologue_cache
*
2939 arm_make_stub_cache (struct frame_info
*this_frame
)
2941 struct arm_prologue_cache
*cache
;
2943 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2944 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2946 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2951 /* Our frame ID for a stub frame is the current SP and LR. */
2954 arm_stub_this_id (struct frame_info
*this_frame
,
2956 struct frame_id
*this_id
)
2958 struct arm_prologue_cache
*cache
;
2960 if (*this_cache
== NULL
)
2961 *this_cache
= arm_make_stub_cache (this_frame
);
2962 cache
= *this_cache
;
2964 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
2968 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
2969 struct frame_info
*this_frame
,
2970 void **this_prologue_cache
)
2972 CORE_ADDR addr_in_block
;
2974 CORE_ADDR pc
, start_addr
;
2977 addr_in_block
= get_frame_address_in_block (this_frame
);
2978 pc
= get_frame_pc (this_frame
);
2979 if (in_plt_section (addr_in_block
)
2980 /* We also use the stub winder if the target memory is unreadable
2981 to avoid having the prologue unwinder trying to read it. */
2982 || target_read_memory (pc
, dummy
, 4) != 0)
2985 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0
2986 && arm_skip_bx_reg (this_frame
, pc
) != 0)
2992 struct frame_unwind arm_stub_unwind
= {
2994 default_frame_unwind_stop_reason
,
2996 arm_prologue_prev_register
,
2998 arm_stub_unwind_sniffer
3001 /* Put here the code to store, into CACHE->saved_regs, the addresses
3002 of the saved registers of frame described by THIS_FRAME. CACHE is
3005 static struct arm_prologue_cache
*
3006 arm_m_exception_cache (struct frame_info
*this_frame
)
3008 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3009 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3010 struct arm_prologue_cache
*cache
;
3011 CORE_ADDR unwound_sp
;
3014 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
3015 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3017 unwound_sp
= get_frame_register_unsigned (this_frame
,
3020 /* The hardware saves eight 32-bit words, comprising xPSR,
3021 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
3022 "B1.5.6 Exception entry behavior" in
3023 "ARMv7-M Architecture Reference Manual". */
3024 cache
->saved_regs
[0].addr
= unwound_sp
;
3025 cache
->saved_regs
[1].addr
= unwound_sp
+ 4;
3026 cache
->saved_regs
[2].addr
= unwound_sp
+ 8;
3027 cache
->saved_regs
[3].addr
= unwound_sp
+ 12;
3028 cache
->saved_regs
[12].addr
= unwound_sp
+ 16;
3029 cache
->saved_regs
[14].addr
= unwound_sp
+ 20;
3030 cache
->saved_regs
[15].addr
= unwound_sp
+ 24;
3031 cache
->saved_regs
[ARM_PS_REGNUM
].addr
= unwound_sp
+ 28;
3033 /* If bit 9 of the saved xPSR is set, then there is a four-byte
3034 aligner between the top of the 32-byte stack frame and the
3035 previous context's stack pointer. */
3036 cache
->prev_sp
= unwound_sp
+ 32;
3037 if (safe_read_memory_integer (unwound_sp
+ 28, 4, byte_order
, &xpsr
)
3038 && (xpsr
& (1 << 9)) != 0)
3039 cache
->prev_sp
+= 4;
3044 /* Implementation of function hook 'this_id' in
3045 'struct frame_uwnind'. */
3048 arm_m_exception_this_id (struct frame_info
*this_frame
,
3050 struct frame_id
*this_id
)
3052 struct arm_prologue_cache
*cache
;
3054 if (*this_cache
== NULL
)
3055 *this_cache
= arm_m_exception_cache (this_frame
);
3056 cache
= *this_cache
;
3058 /* Our frame ID for a stub frame is the current SP and LR. */
3059 *this_id
= frame_id_build (cache
->prev_sp
,
3060 get_frame_pc (this_frame
));
3063 /* Implementation of function hook 'prev_register' in
3064 'struct frame_uwnind'. */
3066 static struct value
*
3067 arm_m_exception_prev_register (struct frame_info
*this_frame
,
3071 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3072 struct arm_prologue_cache
*cache
;
3074 if (*this_cache
== NULL
)
3075 *this_cache
= arm_m_exception_cache (this_frame
);
3076 cache
= *this_cache
;
3078 /* The value was already reconstructed into PREV_SP. */
3079 if (prev_regnum
== ARM_SP_REGNUM
)
3080 return frame_unwind_got_constant (this_frame
, prev_regnum
,
3083 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
3087 /* Implementation of function hook 'sniffer' in
3088 'struct frame_uwnind'. */
3091 arm_m_exception_unwind_sniffer (const struct frame_unwind
*self
,
3092 struct frame_info
*this_frame
,
3093 void **this_prologue_cache
)
3095 CORE_ADDR this_pc
= get_frame_pc (this_frame
);
3097 /* No need to check is_m; this sniffer is only registered for
3098 M-profile architectures. */
3100 /* Exception frames return to one of these magic PCs. Other values
3101 are not defined as of v7-M. See details in "B1.5.8 Exception
3102 return behavior" in "ARMv7-M Architecture Reference Manual". */
3103 if (this_pc
== 0xfffffff1 || this_pc
== 0xfffffff9
3104 || this_pc
== 0xfffffffd)
3110 /* Frame unwinder for M-profile exceptions. */
3112 struct frame_unwind arm_m_exception_unwind
=
3115 default_frame_unwind_stop_reason
,
3116 arm_m_exception_this_id
,
3117 arm_m_exception_prev_register
,
3119 arm_m_exception_unwind_sniffer
3123 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
3125 struct arm_prologue_cache
*cache
;
3127 if (*this_cache
== NULL
)
3128 *this_cache
= arm_make_prologue_cache (this_frame
);
3129 cache
= *this_cache
;
3131 return cache
->prev_sp
- cache
->framesize
;
3134 struct frame_base arm_normal_base
= {
3135 &arm_prologue_unwind
,
3136 arm_normal_frame_base
,
3137 arm_normal_frame_base
,
3138 arm_normal_frame_base
3141 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3142 dummy frame. The frame ID's base needs to match the TOS value
3143 saved by save_dummy_frame_tos() and returned from
3144 arm_push_dummy_call, and the PC needs to match the dummy frame's
3147 static struct frame_id
3148 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3150 return frame_id_build (get_frame_register_unsigned (this_frame
,
3152 get_frame_pc (this_frame
));
3155 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3156 be used to construct the previous frame's ID, after looking up the
3157 containing function). */
3160 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3163 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
3164 return arm_addr_bits_remove (gdbarch
, pc
);
3168 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3170 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
3173 static struct value
*
3174 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
3177 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
3179 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
3184 /* The PC is normally copied from the return column, which
3185 describes saves of LR. However, that version may have an
3186 extra bit set to indicate Thumb state. The bit is not
3188 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3189 return frame_unwind_got_constant (this_frame
, regnum
,
3190 arm_addr_bits_remove (gdbarch
, lr
));
3193 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3194 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
3195 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3196 if (IS_THUMB_ADDR (lr
))
3200 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
3203 internal_error (__FILE__
, __LINE__
,
3204 _("Unexpected register %d"), regnum
);
3209 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3210 struct dwarf2_frame_state_reg
*reg
,
3211 struct frame_info
*this_frame
)
3217 reg
->how
= DWARF2_FRAME_REG_FN
;
3218 reg
->loc
.fn
= arm_dwarf2_prev_register
;
3221 reg
->how
= DWARF2_FRAME_REG_CFA
;
3226 /* Return true if we are in the function's epilogue, i.e. after the
3227 instruction that destroyed the function's stack frame. */
3230 thumb_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3232 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3233 unsigned int insn
, insn2
;
3234 int found_return
= 0, found_stack_adjust
= 0;
3235 CORE_ADDR func_start
, func_end
;
3239 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3242 /* The epilogue is a sequence of instructions along the following lines:
3244 - add stack frame size to SP or FP
3245 - [if frame pointer used] restore SP from FP
3246 - restore registers from SP [may include PC]
3247 - a return-type instruction [if PC wasn't already restored]
3249 In a first pass, we scan forward from the current PC and verify the
3250 instructions we find as compatible with this sequence, ending in a
3253 However, this is not sufficient to distinguish indirect function calls
3254 within a function from indirect tail calls in the epilogue in some cases.
3255 Therefore, if we didn't already find any SP-changing instruction during
3256 forward scan, we add a backward scanning heuristic to ensure we actually
3257 are in the epilogue. */
3260 while (scan_pc
< func_end
&& !found_return
)
3262 if (target_read_memory (scan_pc
, buf
, 2))
3266 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3268 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3270 else if (insn
== 0x46f7) /* mov pc, lr */
3272 else if (thumb_instruction_restores_sp (insn
))
3274 if ((insn
& 0xff00) == 0xbd00) /* pop <registers, PC> */
3277 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instruction */
3279 if (target_read_memory (scan_pc
, buf
, 2))
3283 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3285 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3287 if (insn2
& 0x8000) /* <registers> include PC. */
3290 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3291 && (insn2
& 0x0fff) == 0x0b04)
3293 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
3296 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3297 && (insn2
& 0x0e00) == 0x0a00)
3309 /* Since any instruction in the epilogue sequence, with the possible
3310 exception of return itself, updates the stack pointer, we need to
3311 scan backwards for at most one instruction. Try either a 16-bit or
3312 a 32-bit instruction. This is just a heuristic, so we do not worry
3313 too much about false positives. */
3315 if (pc
- 4 < func_start
)
3317 if (target_read_memory (pc
- 4, buf
, 4))
3320 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3321 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
3323 if (thumb_instruction_restores_sp (insn2
))
3324 found_stack_adjust
= 1;
3325 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3326 found_stack_adjust
= 1;
3327 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3328 && (insn2
& 0x0fff) == 0x0b04)
3329 found_stack_adjust
= 1;
3330 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3331 && (insn2
& 0x0e00) == 0x0a00)
3332 found_stack_adjust
= 1;
3334 return found_stack_adjust
;
3337 /* Return true if we are in the function's epilogue, i.e. after the
3338 instruction that destroyed the function's stack frame. */
3341 arm_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3343 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3346 CORE_ADDR func_start
, func_end
;
3348 if (arm_pc_is_thumb (gdbarch
, pc
))
3349 return thumb_in_function_epilogue_p (gdbarch
, pc
);
3351 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3354 /* We are in the epilogue if the previous instruction was a stack
3355 adjustment and the next instruction is a possible return (bx, mov
3356 pc, or pop). We could have to scan backwards to find the stack
3357 adjustment, or forwards to find the return, but this is a decent
3358 approximation. First scan forwards. */
3361 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3362 if (bits (insn
, 28, 31) != INST_NV
)
3364 if ((insn
& 0x0ffffff0) == 0x012fff10)
3367 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
3370 else if ((insn
& 0x0fff0000) == 0x08bd0000
3371 && (insn
& 0x0000c000) != 0)
3372 /* POP (LDMIA), including PC or LR. */
3379 /* Scan backwards. This is just a heuristic, so do not worry about
3380 false positives from mode changes. */
3382 if (pc
< func_start
+ 4)
3385 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
3386 if (arm_instruction_restores_sp (insn
))
3393 /* When arguments must be pushed onto the stack, they go on in reverse
3394 order. The code below implements a FILO (stack) to do this. */
3399 struct stack_item
*prev
;
3403 static struct stack_item
*
3404 push_stack_item (struct stack_item
*prev
, const void *contents
, int len
)
3406 struct stack_item
*si
;
3407 si
= xmalloc (sizeof (struct stack_item
));
3408 si
->data
= xmalloc (len
);
3411 memcpy (si
->data
, contents
, len
);
3415 static struct stack_item
*
3416 pop_stack_item (struct stack_item
*si
)
3418 struct stack_item
*dead
= si
;
3426 /* Return the alignment (in bytes) of the given type. */
3429 arm_type_align (struct type
*t
)
3435 t
= check_typedef (t
);
3436 switch (TYPE_CODE (t
))
3439 /* Should never happen. */
3440 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
3444 case TYPE_CODE_ENUM
:
3448 case TYPE_CODE_RANGE
:
3450 case TYPE_CODE_CHAR
:
3451 case TYPE_CODE_BOOL
:
3452 return TYPE_LENGTH (t
);
3454 case TYPE_CODE_ARRAY
:
3455 case TYPE_CODE_COMPLEX
:
3456 /* TODO: What about vector types? */
3457 return arm_type_align (TYPE_TARGET_TYPE (t
));
3459 case TYPE_CODE_STRUCT
:
3460 case TYPE_CODE_UNION
:
3462 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
3464 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
3472 /* Possible base types for a candidate for passing and returning in
3475 enum arm_vfp_cprc_base_type
3484 /* The length of one element of base type B. */
3487 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
3491 case VFP_CPRC_SINGLE
:
3493 case VFP_CPRC_DOUBLE
:
3495 case VFP_CPRC_VEC64
:
3497 case VFP_CPRC_VEC128
:
3500 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3505 /* The character ('s', 'd' or 'q') for the type of VFP register used
3506 for passing base type B. */
3509 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
3513 case VFP_CPRC_SINGLE
:
3515 case VFP_CPRC_DOUBLE
:
3517 case VFP_CPRC_VEC64
:
3519 case VFP_CPRC_VEC128
:
3522 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3527 /* Determine whether T may be part of a candidate for passing and
3528 returning in VFP registers, ignoring the limit on the total number
3529 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3530 classification of the first valid component found; if it is not
3531 VFP_CPRC_UNKNOWN, all components must have the same classification
3532 as *BASE_TYPE. If it is found that T contains a type not permitted
3533 for passing and returning in VFP registers, a type differently
3534 classified from *BASE_TYPE, or two types differently classified
3535 from each other, return -1, otherwise return the total number of
3536 base-type elements found (possibly 0 in an empty structure or
3537 array). Vector types are not currently supported, matching the
3538 generic AAPCS support. */
3541 arm_vfp_cprc_sub_candidate (struct type
*t
,
3542 enum arm_vfp_cprc_base_type
*base_type
)
3544 t
= check_typedef (t
);
3545 switch (TYPE_CODE (t
))
3548 switch (TYPE_LENGTH (t
))
3551 if (*base_type
== VFP_CPRC_UNKNOWN
)
3552 *base_type
= VFP_CPRC_SINGLE
;
3553 else if (*base_type
!= VFP_CPRC_SINGLE
)
3558 if (*base_type
== VFP_CPRC_UNKNOWN
)
3559 *base_type
= VFP_CPRC_DOUBLE
;
3560 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3569 case TYPE_CODE_COMPLEX
:
3570 /* Arguments of complex T where T is one of the types float or
3571 double get treated as if they are implemented as:
3580 switch (TYPE_LENGTH (t
))
3583 if (*base_type
== VFP_CPRC_UNKNOWN
)
3584 *base_type
= VFP_CPRC_SINGLE
;
3585 else if (*base_type
!= VFP_CPRC_SINGLE
)
3590 if (*base_type
== VFP_CPRC_UNKNOWN
)
3591 *base_type
= VFP_CPRC_DOUBLE
;
3592 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3601 case TYPE_CODE_ARRAY
:
3605 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
), base_type
);
3608 if (TYPE_LENGTH (t
) == 0)
3610 gdb_assert (count
== 0);
3613 else if (count
== 0)
3615 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3616 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
3617 return TYPE_LENGTH (t
) / unitlen
;
3621 case TYPE_CODE_STRUCT
:
3626 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3628 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3630 if (sub_count
== -1)
3634 if (TYPE_LENGTH (t
) == 0)
3636 gdb_assert (count
== 0);
3639 else if (count
== 0)
3641 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3642 if (TYPE_LENGTH (t
) != unitlen
* count
)
3647 case TYPE_CODE_UNION
:
3652 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3654 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3656 if (sub_count
== -1)
3658 count
= (count
> sub_count
? count
: sub_count
);
3660 if (TYPE_LENGTH (t
) == 0)
3662 gdb_assert (count
== 0);
3665 else if (count
== 0)
3667 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3668 if (TYPE_LENGTH (t
) != unitlen
* count
)
3680 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3681 if passed to or returned from a non-variadic function with the VFP
3682 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3683 *BASE_TYPE to the base type for T and *COUNT to the number of
3684 elements of that base type before returning. */
3687 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
3690 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
3691 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
3692 if (c
<= 0 || c
> 4)
3699 /* Return 1 if the VFP ABI should be used for passing arguments to and
3700 returning values from a function of type FUNC_TYPE, 0
3704 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
3706 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3707 /* Variadic functions always use the base ABI. Assume that functions
3708 without debug info are not variadic. */
3709 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
3711 /* The VFP ABI is only supported as a variant of AAPCS. */
3712 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
3714 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
3717 /* We currently only support passing parameters in integer registers, which
3718 conforms with GCC's default model, and VFP argument passing following
3719 the VFP variant of AAPCS. Several other variants exist and
3720 we should probably support some of them based on the selected ABI. */
3723 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3724 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3725 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3726 CORE_ADDR struct_addr
)
3728 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3732 struct stack_item
*si
= NULL
;
3735 unsigned vfp_regs_free
= (1 << 16) - 1;
3737 /* Determine the type of this function and whether the VFP ABI
3739 ftype
= check_typedef (value_type (function
));
3740 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
3741 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
3742 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
3744 /* Set the return address. For the ARM, the return breakpoint is
3745 always at BP_ADDR. */
3746 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
3748 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
3750 /* Walk through the list of args and determine how large a temporary
3751 stack is required. Need to take care here as structs may be
3752 passed on the stack, and we have to push them. */
3755 argreg
= ARM_A1_REGNUM
;
3758 /* The struct_return pointer occupies the first parameter
3759 passing register. */
3763 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
3764 gdbarch_register_name (gdbarch
, argreg
),
3765 paddress (gdbarch
, struct_addr
));
3766 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
3770 for (argnum
= 0; argnum
< nargs
; argnum
++)
3773 struct type
*arg_type
;
3774 struct type
*target_type
;
3775 enum type_code typecode
;
3776 const bfd_byte
*val
;
3778 enum arm_vfp_cprc_base_type vfp_base_type
;
3780 int may_use_core_reg
= 1;
3782 arg_type
= check_typedef (value_type (args
[argnum
]));
3783 len
= TYPE_LENGTH (arg_type
);
3784 target_type
= TYPE_TARGET_TYPE (arg_type
);
3785 typecode
= TYPE_CODE (arg_type
);
3786 val
= value_contents (args
[argnum
]);
3788 align
= arm_type_align (arg_type
);
3789 /* Round alignment up to a whole number of words. */
3790 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
3791 /* Different ABIs have different maximum alignments. */
3792 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
3794 /* The APCS ABI only requires word alignment. */
3795 align
= INT_REGISTER_SIZE
;
3799 /* The AAPCS requires at most doubleword alignment. */
3800 if (align
> INT_REGISTER_SIZE
* 2)
3801 align
= INT_REGISTER_SIZE
* 2;
3805 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
3813 /* Because this is a CPRC it cannot go in a core register or
3814 cause a core register to be skipped for alignment.
3815 Either it goes in VFP registers and the rest of this loop
3816 iteration is skipped for this argument, or it goes on the
3817 stack (and the stack alignment code is correct for this
3819 may_use_core_reg
= 0;
3821 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
3822 shift
= unit_length
/ 4;
3823 mask
= (1 << (shift
* vfp_base_count
)) - 1;
3824 for (regno
= 0; regno
< 16; regno
+= shift
)
3825 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
3834 vfp_regs_free
&= ~(mask
<< regno
);
3835 reg_scaled
= regno
/ shift
;
3836 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
3837 for (i
= 0; i
< vfp_base_count
; i
++)
3841 if (reg_char
== 'q')
3842 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
3843 val
+ i
* unit_length
);
3846 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d",
3847 reg_char
, reg_scaled
+ i
);
3848 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3850 regcache_cooked_write (regcache
, regnum
,
3851 val
+ i
* unit_length
);
3858 /* This CPRC could not go in VFP registers, so all VFP
3859 registers are now marked as used. */
3864 /* Push stack padding for dowubleword alignment. */
3865 if (nstack
& (align
- 1))
3867 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3868 nstack
+= INT_REGISTER_SIZE
;
3871 /* Doubleword aligned quantities must go in even register pairs. */
3872 if (may_use_core_reg
3873 && argreg
<= ARM_LAST_ARG_REGNUM
3874 && align
> INT_REGISTER_SIZE
3878 /* If the argument is a pointer to a function, and it is a
3879 Thumb function, create a LOCAL copy of the value and set
3880 the THUMB bit in it. */
3881 if (TYPE_CODE_PTR
== typecode
3882 && target_type
!= NULL
3883 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
3885 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
3886 if (arm_pc_is_thumb (gdbarch
, regval
))
3888 bfd_byte
*copy
= alloca (len
);
3889 store_unsigned_integer (copy
, len
, byte_order
,
3890 MAKE_THUMB_ADDR (regval
));
3895 /* Copy the argument to general registers or the stack in
3896 register-sized pieces. Large arguments are split between
3897 registers and stack. */
3900 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
3902 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
3904 /* The argument is being passed in a general purpose
3907 = extract_unsigned_integer (val
, partial_len
, byte_order
);
3908 if (byte_order
== BFD_ENDIAN_BIG
)
3909 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
3911 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
3913 gdbarch_register_name
3915 phex (regval
, INT_REGISTER_SIZE
));
3916 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3921 /* Push the arguments onto the stack. */
3923 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
3925 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3926 nstack
+= INT_REGISTER_SIZE
;
3933 /* If we have an odd number of words to push, then decrement the stack
3934 by one word now, so first stack argument will be dword aligned. */
3941 write_memory (sp
, si
->data
, si
->len
);
3942 si
= pop_stack_item (si
);
3945 /* Finally, update teh SP register. */
3946 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
3952 /* Always align the frame to an 8-byte boundary. This is required on
3953 some platforms and harmless on the rest. */
3956 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3958 /* Align the stack to eight bytes. */
3959 return sp
& ~ (CORE_ADDR
) 7;
3963 print_fpu_flags (struct ui_file
*file
, int flags
)
3965 if (flags
& (1 << 0))
3966 fputs_filtered ("IVO ", file
);
3967 if (flags
& (1 << 1))
3968 fputs_filtered ("DVZ ", file
);
3969 if (flags
& (1 << 2))
3970 fputs_filtered ("OFL ", file
);
3971 if (flags
& (1 << 3))
3972 fputs_filtered ("UFL ", file
);
3973 if (flags
& (1 << 4))
3974 fputs_filtered ("INX ", file
);
3975 fputc_filtered ('\n', file
);
3978 /* Print interesting information about the floating point processor
3979 (if present) or emulator. */
3981 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
3982 struct frame_info
*frame
, const char *args
)
3984 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
3987 type
= (status
>> 24) & 127;
3988 if (status
& (1 << 31))
3989 fprintf_filtered (file
, _("Hardware FPU type %d\n"), type
);
3991 fprintf_filtered (file
, _("Software FPU type %d\n"), type
);
3992 /* i18n: [floating point unit] mask */
3993 fputs_filtered (_("mask: "), file
);
3994 print_fpu_flags (file
, status
>> 16);
3995 /* i18n: [floating point unit] flags */
3996 fputs_filtered (_("flags: "), file
);
3997 print_fpu_flags (file
, status
);
4000 /* Construct the ARM extended floating point type. */
4001 static struct type
*
4002 arm_ext_type (struct gdbarch
*gdbarch
)
4004 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4006 if (!tdep
->arm_ext_type
)
4008 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
4009 floatformats_arm_ext
);
4011 return tdep
->arm_ext_type
;
4014 static struct type
*
4015 arm_neon_double_type (struct gdbarch
*gdbarch
)
4017 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4019 if (tdep
->neon_double_type
== NULL
)
4021 struct type
*t
, *elem
;
4023 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
4025 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4026 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
4027 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4028 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
4029 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4030 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
4031 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4032 append_composite_type_field (t
, "u64", elem
);
4033 elem
= builtin_type (gdbarch
)->builtin_float
;
4034 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
4035 elem
= builtin_type (gdbarch
)->builtin_double
;
4036 append_composite_type_field (t
, "f64", elem
);
4038 TYPE_VECTOR (t
) = 1;
4039 TYPE_NAME (t
) = "neon_d";
4040 tdep
->neon_double_type
= t
;
4043 return tdep
->neon_double_type
;
4046 /* FIXME: The vector types are not correctly ordered on big-endian
4047 targets. Just as s0 is the low bits of d0, d0[0] is also the low
4048 bits of d0 - regardless of what unit size is being held in d0. So
4049 the offset of the first uint8 in d0 is 7, but the offset of the
4050 first float is 4. This code works as-is for little-endian
4053 static struct type
*
4054 arm_neon_quad_type (struct gdbarch
*gdbarch
)
4056 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4058 if (tdep
->neon_quad_type
== NULL
)
4060 struct type
*t
, *elem
;
4062 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
4064 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4065 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
4066 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4067 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
4068 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4069 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
4070 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4071 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
4072 elem
= builtin_type (gdbarch
)->builtin_float
;
4073 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
4074 elem
= builtin_type (gdbarch
)->builtin_double
;
4075 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
4077 TYPE_VECTOR (t
) = 1;
4078 TYPE_NAME (t
) = "neon_q";
4079 tdep
->neon_quad_type
= t
;
4082 return tdep
->neon_quad_type
;
4085 /* Return the GDB type object for the "standard" data type of data in
4088 static struct type
*
4089 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
4091 int num_regs
= gdbarch_num_regs (gdbarch
);
4093 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
4094 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
4095 return builtin_type (gdbarch
)->builtin_float
;
4097 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
4098 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
4099 return arm_neon_quad_type (gdbarch
);
4101 /* If the target description has register information, we are only
4102 in this function so that we can override the types of
4103 double-precision registers for NEON. */
4104 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
4106 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
4108 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
4109 && TYPE_CODE (t
) == TYPE_CODE_FLT
4110 && gdbarch_tdep (gdbarch
)->have_neon
)
4111 return arm_neon_double_type (gdbarch
);
4116 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
4118 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
4119 return builtin_type (gdbarch
)->builtin_void
;
4121 return arm_ext_type (gdbarch
);
4123 else if (regnum
== ARM_SP_REGNUM
)
4124 return builtin_type (gdbarch
)->builtin_data_ptr
;
4125 else if (regnum
== ARM_PC_REGNUM
)
4126 return builtin_type (gdbarch
)->builtin_func_ptr
;
4127 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
4128 /* These registers are only supported on targets which supply
4129 an XML description. */
4130 return builtin_type (gdbarch
)->builtin_int0
;
4132 return builtin_type (gdbarch
)->builtin_uint32
;
4135 /* Map a DWARF register REGNUM onto the appropriate GDB register
4139 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
4141 /* Core integer regs. */
4142 if (reg
>= 0 && reg
<= 15)
4145 /* Legacy FPA encoding. These were once used in a way which
4146 overlapped with VFP register numbering, so their use is
4147 discouraged, but GDB doesn't support the ARM toolchain
4148 which used them for VFP. */
4149 if (reg
>= 16 && reg
<= 23)
4150 return ARM_F0_REGNUM
+ reg
- 16;
4152 /* New assignments for the FPA registers. */
4153 if (reg
>= 96 && reg
<= 103)
4154 return ARM_F0_REGNUM
+ reg
- 96;
4156 /* WMMX register assignments. */
4157 if (reg
>= 104 && reg
<= 111)
4158 return ARM_WCGR0_REGNUM
+ reg
- 104;
4160 if (reg
>= 112 && reg
<= 127)
4161 return ARM_WR0_REGNUM
+ reg
- 112;
4163 if (reg
>= 192 && reg
<= 199)
4164 return ARM_WC0_REGNUM
+ reg
- 192;
4166 /* VFP v2 registers. A double precision value is actually
4167 in d1 rather than s2, but the ABI only defines numbering
4168 for the single precision registers. This will "just work"
4169 in GDB for little endian targets (we'll read eight bytes,
4170 starting in s0 and then progressing to s1), but will be
4171 reversed on big endian targets with VFP. This won't
4172 be a problem for the new Neon quad registers; you're supposed
4173 to use DW_OP_piece for those. */
4174 if (reg
>= 64 && reg
<= 95)
4178 xsnprintf (name_buf
, sizeof (name_buf
), "s%d", reg
- 64);
4179 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4183 /* VFP v3 / Neon registers. This range is also used for VFP v2
4184 registers, except that it now describes d0 instead of s0. */
4185 if (reg
>= 256 && reg
<= 287)
4189 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", reg
- 256);
4190 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4197 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4199 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
4202 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
4204 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
4205 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
4207 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
4208 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
4210 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
4211 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
4213 if (reg
< NUM_GREGS
)
4214 return SIM_ARM_R0_REGNUM
+ reg
;
4217 if (reg
< NUM_FREGS
)
4218 return SIM_ARM_FP0_REGNUM
+ reg
;
4221 if (reg
< NUM_SREGS
)
4222 return SIM_ARM_FPS_REGNUM
+ reg
;
4225 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
4228 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4229 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4230 It is thought that this is is the floating-point register format on
4231 little-endian systems. */
4234 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
4235 void *dbl
, int endianess
)
4239 if (endianess
== BFD_ENDIAN_BIG
)
4240 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
4242 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4244 floatformat_from_doublest (fmt
, &d
, dbl
);
4248 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
4253 floatformat_to_doublest (fmt
, ptr
, &d
);
4254 if (endianess
== BFD_ENDIAN_BIG
)
4255 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
4257 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4262 condition_true (unsigned long cond
, unsigned long status_reg
)
4264 if (cond
== INST_AL
|| cond
== INST_NV
)
4270 return ((status_reg
& FLAG_Z
) != 0);
4272 return ((status_reg
& FLAG_Z
) == 0);
4274 return ((status_reg
& FLAG_C
) != 0);
4276 return ((status_reg
& FLAG_C
) == 0);
4278 return ((status_reg
& FLAG_N
) != 0);
4280 return ((status_reg
& FLAG_N
) == 0);
4282 return ((status_reg
& FLAG_V
) != 0);
4284 return ((status_reg
& FLAG_V
) == 0);
4286 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
4288 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
4290 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
4292 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
4294 return (((status_reg
& FLAG_Z
) == 0)
4295 && (((status_reg
& FLAG_N
) == 0)
4296 == ((status_reg
& FLAG_V
) == 0)));
4298 return (((status_reg
& FLAG_Z
) != 0)
4299 || (((status_reg
& FLAG_N
) == 0)
4300 != ((status_reg
& FLAG_V
) == 0)));
4305 static unsigned long
4306 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
4307 unsigned long pc_val
, unsigned long status_reg
)
4309 unsigned long res
, shift
;
4310 int rm
= bits (inst
, 0, 3);
4311 unsigned long shifttype
= bits (inst
, 5, 6);
4315 int rs
= bits (inst
, 8, 11);
4316 shift
= (rs
== 15 ? pc_val
+ 8
4317 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
4320 shift
= bits (inst
, 7, 11);
4322 res
= (rm
== ARM_PC_REGNUM
4323 ? (pc_val
+ (bit (inst
, 4) ? 12 : 8))
4324 : get_frame_register_unsigned (frame
, rm
));
4329 res
= shift
>= 32 ? 0 : res
<< shift
;
4333 res
= shift
>= 32 ? 0 : res
>> shift
;
4339 res
= ((res
& 0x80000000L
)
4340 ? ~((~res
) >> shift
) : res
>> shift
);
4343 case 3: /* ROR/RRX */
4346 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
4348 res
= (res
>> shift
) | (res
<< (32 - shift
));
4352 return res
& 0xffffffff;
4355 /* Return number of 1-bits in VAL. */
4358 bitcount (unsigned long val
)
4361 for (nbits
= 0; val
!= 0; nbits
++)
4362 val
&= val
- 1; /* Delete rightmost 1-bit in val. */
4366 /* Return the size in bytes of the complete Thumb instruction whose
4367 first halfword is INST1. */
4370 thumb_insn_size (unsigned short inst1
)
4372 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
4379 thumb_advance_itstate (unsigned int itstate
)
4381 /* Preserve IT[7:5], the first three bits of the condition. Shift
4382 the upcoming condition flags left by one bit. */
4383 itstate
= (itstate
& 0xe0) | ((itstate
<< 1) & 0x1f);
4385 /* If we have finished the IT block, clear the state. */
4386 if ((itstate
& 0x0f) == 0)
4392 /* Find the next PC after the current instruction executes. In some
4393 cases we can not statically determine the answer (see the IT state
4394 handling in this function); in that case, a breakpoint may be
4395 inserted in addition to the returned PC, which will be used to set
4396 another breakpoint by our caller. */
4399 thumb_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
)
4401 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4402 struct address_space
*aspace
= get_frame_address_space (frame
);
4403 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4404 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4405 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
4406 unsigned short inst1
;
4407 CORE_ADDR nextpc
= pc
+ 2; /* Default is next instruction. */
4408 unsigned long offset
;
4409 ULONGEST status
, itstate
;
4411 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4412 pc_val
= MAKE_THUMB_ADDR (pc_val
);
4414 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
4416 /* Thumb-2 conditional execution support. There are eight bits in
4417 the CPSR which describe conditional execution state. Once
4418 reconstructed (they're in a funny order), the low five bits
4419 describe the low bit of the condition for each instruction and
4420 how many instructions remain. The high three bits describe the
4421 base condition. One of the low four bits will be set if an IT
4422 block is active. These bits read as zero on earlier
4424 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
4425 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
4427 /* If-Then handling. On GNU/Linux, where this routine is used, we
4428 use an undefined instruction as a breakpoint. Unlike BKPT, IT
4429 can disable execution of the undefined instruction. So we might
4430 miss the breakpoint if we set it on a skipped conditional
4431 instruction. Because conditional instructions can change the
4432 flags, affecting the execution of further instructions, we may
4433 need to set two breakpoints. */
4435 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
!= NULL
)
4437 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4439 /* An IT instruction. Because this instruction does not
4440 modify the flags, we can accurately predict the next
4441 executed instruction. */
4442 itstate
= inst1
& 0x00ff;
4443 pc
+= thumb_insn_size (inst1
);
4445 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
4447 inst1
= read_memory_unsigned_integer (pc
, 2,
4448 byte_order_for_code
);
4449 pc
+= thumb_insn_size (inst1
);
4450 itstate
= thumb_advance_itstate (itstate
);
4453 return MAKE_THUMB_ADDR (pc
);
4455 else if (itstate
!= 0)
4457 /* We are in a conditional block. Check the condition. */
4458 if (! condition_true (itstate
>> 4, status
))
4460 /* Advance to the next executed instruction. */
4461 pc
+= thumb_insn_size (inst1
);
4462 itstate
= thumb_advance_itstate (itstate
);
4464 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
4466 inst1
= read_memory_unsigned_integer (pc
, 2,
4467 byte_order_for_code
);
4468 pc
+= thumb_insn_size (inst1
);
4469 itstate
= thumb_advance_itstate (itstate
);
4472 return MAKE_THUMB_ADDR (pc
);
4474 else if ((itstate
& 0x0f) == 0x08)
4476 /* This is the last instruction of the conditional
4477 block, and it is executed. We can handle it normally
4478 because the following instruction is not conditional,
4479 and we must handle it normally because it is
4480 permitted to branch. Fall through. */
4486 /* There are conditional instructions after this one.
4487 If this instruction modifies the flags, then we can
4488 not predict what the next executed instruction will
4489 be. Fortunately, this instruction is architecturally
4490 forbidden to branch; we know it will fall through.
4491 Start by skipping past it. */
4492 pc
+= thumb_insn_size (inst1
);
4493 itstate
= thumb_advance_itstate (itstate
);
4495 /* Set a breakpoint on the following instruction. */
4496 gdb_assert ((itstate
& 0x0f) != 0);
4497 arm_insert_single_step_breakpoint (gdbarch
, aspace
,
4498 MAKE_THUMB_ADDR (pc
));
4499 cond_negated
= (itstate
>> 4) & 1;
4501 /* Skip all following instructions with the same
4502 condition. If there is a later instruction in the IT
4503 block with the opposite condition, set the other
4504 breakpoint there. If not, then set a breakpoint on
4505 the instruction after the IT block. */
4508 inst1
= read_memory_unsigned_integer (pc
, 2,
4509 byte_order_for_code
);
4510 pc
+= thumb_insn_size (inst1
);
4511 itstate
= thumb_advance_itstate (itstate
);
4513 while (itstate
!= 0 && ((itstate
>> 4) & 1) == cond_negated
);
4515 return MAKE_THUMB_ADDR (pc
);
4519 else if (itstate
& 0x0f)
4521 /* We are in a conditional block. Check the condition. */
4522 int cond
= itstate
>> 4;
4524 if (! condition_true (cond
, status
))
4525 /* Advance to the next instruction. All the 32-bit
4526 instructions share a common prefix. */
4527 return MAKE_THUMB_ADDR (pc
+ thumb_insn_size (inst1
));
4529 /* Otherwise, handle the instruction normally. */
4532 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
4536 /* Fetch the saved PC from the stack. It's stored above
4537 all of the other registers. */
4538 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
4539 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
4540 nextpc
= read_memory_unsigned_integer (sp
+ offset
, 4, byte_order
);
4542 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
4544 unsigned long cond
= bits (inst1
, 8, 11);
4545 if (cond
== 0x0f) /* 0x0f = SWI */
4547 struct gdbarch_tdep
*tdep
;
4548 tdep
= gdbarch_tdep (gdbarch
);
4550 if (tdep
->syscall_next_pc
!= NULL
)
4551 nextpc
= tdep
->syscall_next_pc (frame
);
4554 else if (cond
!= 0x0f && condition_true (cond
, status
))
4555 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
4557 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
4559 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
4561 else if (thumb_insn_size (inst1
) == 4) /* 32-bit instruction */
4563 unsigned short inst2
;
4564 inst2
= read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
4566 /* Default to the next instruction. */
4568 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4570 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
4572 /* Branches and miscellaneous control instructions. */
4574 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
4577 int j1
, j2
, imm1
, imm2
;
4579 imm1
= sbits (inst1
, 0, 10);
4580 imm2
= bits (inst2
, 0, 10);
4581 j1
= bit (inst2
, 13);
4582 j2
= bit (inst2
, 11);
4584 offset
= ((imm1
<< 12) + (imm2
<< 1));
4585 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
4587 nextpc
= pc_val
+ offset
;
4588 /* For BLX make sure to clear the low bits. */
4589 if (bit (inst2
, 12) == 0)
4590 nextpc
= nextpc
& 0xfffffffc;
4592 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
4594 /* SUBS PC, LR, #imm8. */
4595 nextpc
= get_frame_register_unsigned (frame
, ARM_LR_REGNUM
);
4596 nextpc
-= inst2
& 0x00ff;
4598 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
4600 /* Conditional branch. */
4601 if (condition_true (bits (inst1
, 6, 9), status
))
4603 int sign
, j1
, j2
, imm1
, imm2
;
4605 sign
= sbits (inst1
, 10, 10);
4606 imm1
= bits (inst1
, 0, 5);
4607 imm2
= bits (inst2
, 0, 10);
4608 j1
= bit (inst2
, 13);
4609 j2
= bit (inst2
, 11);
4611 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
4612 offset
+= (imm1
<< 12) + (imm2
<< 1);
4614 nextpc
= pc_val
+ offset
;
4618 else if ((inst1
& 0xfe50) == 0xe810)
4620 /* Load multiple or RFE. */
4621 int rn
, offset
, load_pc
= 1;
4623 rn
= bits (inst1
, 0, 3);
4624 if (bit (inst1
, 7) && !bit (inst1
, 8))
4627 if (!bit (inst2
, 15))
4629 offset
= bitcount (inst2
) * 4 - 4;
4631 else if (!bit (inst1
, 7) && bit (inst1
, 8))
4634 if (!bit (inst2
, 15))
4638 else if (bit (inst1
, 7) && bit (inst1
, 8))
4643 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
4653 CORE_ADDR addr
= get_frame_register_unsigned (frame
, rn
);
4654 nextpc
= get_frame_memory_unsigned (frame
, addr
+ offset
, 4);
4657 else if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
4659 /* MOV PC or MOVS PC. */
4660 nextpc
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4661 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4663 else if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
4667 int rn
, load_pc
= 1;
4669 rn
= bits (inst1
, 0, 3);
4670 base
= get_frame_register_unsigned (frame
, rn
);
4671 if (rn
== ARM_PC_REGNUM
)
4673 base
= (base
+ 4) & ~(CORE_ADDR
) 0x3;
4675 base
+= bits (inst2
, 0, 11);
4677 base
-= bits (inst2
, 0, 11);
4679 else if (bit (inst1
, 7))
4680 base
+= bits (inst2
, 0, 11);
4681 else if (bit (inst2
, 11))
4683 if (bit (inst2
, 10))
4686 base
+= bits (inst2
, 0, 7);
4688 base
-= bits (inst2
, 0, 7);
4691 else if ((inst2
& 0x0fc0) == 0x0000)
4693 int shift
= bits (inst2
, 4, 5), rm
= bits (inst2
, 0, 3);
4694 base
+= get_frame_register_unsigned (frame
, rm
) << shift
;
4701 nextpc
= get_frame_memory_unsigned (frame
, base
, 4);
4703 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
4706 CORE_ADDR tbl_reg
, table
, offset
, length
;
4708 tbl_reg
= bits (inst1
, 0, 3);
4709 if (tbl_reg
== 0x0f)
4710 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
4712 table
= get_frame_register_unsigned (frame
, tbl_reg
);
4714 offset
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4715 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 1);
4716 nextpc
= pc_val
+ length
;
4718 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
4721 CORE_ADDR tbl_reg
, table
, offset
, length
;
4723 tbl_reg
= bits (inst1
, 0, 3);
4724 if (tbl_reg
== 0x0f)
4725 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
4727 table
= get_frame_register_unsigned (frame
, tbl_reg
);
4729 offset
= 2 * get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4730 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 2);
4731 nextpc
= pc_val
+ length
;
4734 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
4736 if (bits (inst1
, 3, 6) == 0x0f)
4737 nextpc
= UNMAKE_THUMB_ADDR (pc_val
);
4739 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
4741 else if ((inst1
& 0xff87) == 0x4687) /* mov pc, REG */
4743 if (bits (inst1
, 3, 6) == 0x0f)
4746 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
4748 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4750 else if ((inst1
& 0xf500) == 0xb100)
4753 int imm
= (bit (inst1
, 9) << 6) + (bits (inst1
, 3, 7) << 1);
4754 ULONGEST reg
= get_frame_register_unsigned (frame
, bits (inst1
, 0, 2));
4756 if (bit (inst1
, 11) && reg
!= 0)
4757 nextpc
= pc_val
+ imm
;
4758 else if (!bit (inst1
, 11) && reg
== 0)
4759 nextpc
= pc_val
+ imm
;
4764 /* Get the raw next address. PC is the current program counter, in
4765 FRAME, which is assumed to be executing in ARM mode.
4767 The value returned has the execution state of the next instruction
4768 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
4769 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
4773 arm_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
)
4775 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4776 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4777 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4778 unsigned long pc_val
;
4779 unsigned long this_instr
;
4780 unsigned long status
;
4783 pc_val
= (unsigned long) pc
;
4784 this_instr
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
4786 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
4787 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
4789 if (bits (this_instr
, 28, 31) == INST_NV
)
4790 switch (bits (this_instr
, 24, 27))
4795 /* Branch with Link and change to Thumb. */
4796 nextpc
= BranchDest (pc
, this_instr
);
4797 nextpc
|= bit (this_instr
, 24) << 1;
4798 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4804 /* Coprocessor register transfer. */
4805 if (bits (this_instr
, 12, 15) == 15)
4806 error (_("Invalid update to pc in instruction"));
4809 else if (condition_true (bits (this_instr
, 28, 31), status
))
4811 switch (bits (this_instr
, 24, 27))
4814 case 0x1: /* data processing */
4818 unsigned long operand1
, operand2
, result
= 0;
4822 if (bits (this_instr
, 12, 15) != 15)
4825 if (bits (this_instr
, 22, 25) == 0
4826 && bits (this_instr
, 4, 7) == 9) /* multiply */
4827 error (_("Invalid update to pc in instruction"));
4829 /* BX <reg>, BLX <reg> */
4830 if (bits (this_instr
, 4, 27) == 0x12fff1
4831 || bits (this_instr
, 4, 27) == 0x12fff3)
4833 rn
= bits (this_instr
, 0, 3);
4834 nextpc
= ((rn
== ARM_PC_REGNUM
)
4836 : get_frame_register_unsigned (frame
, rn
));
4841 /* Multiply into PC. */
4842 c
= (status
& FLAG_C
) ? 1 : 0;
4843 rn
= bits (this_instr
, 16, 19);
4844 operand1
= ((rn
== ARM_PC_REGNUM
)
4846 : get_frame_register_unsigned (frame
, rn
));
4848 if (bit (this_instr
, 25))
4850 unsigned long immval
= bits (this_instr
, 0, 7);
4851 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
4852 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
4855 else /* operand 2 is a shifted register. */
4856 operand2
= shifted_reg_val (frame
, this_instr
, c
,
4859 switch (bits (this_instr
, 21, 24))
4862 result
= operand1
& operand2
;
4866 result
= operand1
^ operand2
;
4870 result
= operand1
- operand2
;
4874 result
= operand2
- operand1
;
4878 result
= operand1
+ operand2
;
4882 result
= operand1
+ operand2
+ c
;
4886 result
= operand1
- operand2
+ c
;
4890 result
= operand2
- operand1
+ c
;
4896 case 0xb: /* tst, teq, cmp, cmn */
4897 result
= (unsigned long) nextpc
;
4901 result
= operand1
| operand2
;
4905 /* Always step into a function. */
4910 result
= operand1
& ~operand2
;
4918 /* In 26-bit APCS the bottom two bits of the result are
4919 ignored, and we always end up in ARM state. */
4921 nextpc
= arm_addr_bits_remove (gdbarch
, result
);
4929 case 0x5: /* data transfer */
4932 if (bit (this_instr
, 20))
4935 if (bits (this_instr
, 12, 15) == 15)
4941 if (bit (this_instr
, 22))
4942 error (_("Invalid update to pc in instruction"));
4944 /* byte write to PC */
4945 rn
= bits (this_instr
, 16, 19);
4946 base
= ((rn
== ARM_PC_REGNUM
)
4948 : get_frame_register_unsigned (frame
, rn
));
4950 if (bit (this_instr
, 24))
4953 int c
= (status
& FLAG_C
) ? 1 : 0;
4954 unsigned long offset
=
4955 (bit (this_instr
, 25)
4956 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
4957 : bits (this_instr
, 0, 11));
4959 if (bit (this_instr
, 23))
4965 (CORE_ADDR
) read_memory_unsigned_integer ((CORE_ADDR
) base
,
4972 case 0x9: /* block transfer */
4973 if (bit (this_instr
, 20))
4976 if (bit (this_instr
, 15))
4980 unsigned long rn_val
4981 = get_frame_register_unsigned (frame
,
4982 bits (this_instr
, 16, 19));
4984 if (bit (this_instr
, 23))
4987 unsigned long reglist
= bits (this_instr
, 0, 14);
4988 offset
= bitcount (reglist
) * 4;
4989 if (bit (this_instr
, 24)) /* pre */
4992 else if (bit (this_instr
, 24))
4996 (CORE_ADDR
) read_memory_unsigned_integer ((CORE_ADDR
)
5003 case 0xb: /* branch & link */
5004 case 0xa: /* branch */
5006 nextpc
= BranchDest (pc
, this_instr
);
5012 case 0xe: /* coproc ops */
5016 struct gdbarch_tdep
*tdep
;
5017 tdep
= gdbarch_tdep (gdbarch
);
5019 if (tdep
->syscall_next_pc
!= NULL
)
5020 nextpc
= tdep
->syscall_next_pc (frame
);
5026 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
5034 /* Determine next PC after current instruction executes. Will call either
5035 arm_get_next_pc_raw or thumb_get_next_pc_raw. Error out if infinite
5036 loop is detected. */
5039 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
5043 if (arm_frame_is_thumb (frame
))
5044 nextpc
= thumb_get_next_pc_raw (frame
, pc
);
5046 nextpc
= arm_get_next_pc_raw (frame
, pc
);
5051 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
5052 of the appropriate mode (as encoded in the PC value), even if this
5053 differs from what would be expected according to the symbol tables. */
5056 arm_insert_single_step_breakpoint (struct gdbarch
*gdbarch
,
5057 struct address_space
*aspace
,
5060 struct cleanup
*old_chain
5061 = make_cleanup_restore_integer (&arm_override_mode
);
5063 arm_override_mode
= IS_THUMB_ADDR (pc
);
5064 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
5066 insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
5068 do_cleanups (old_chain
);
5071 /* Checks for an atomic sequence of instructions beginning with a LDREX{,B,H,D}
5072 instruction and ending with a STREX{,B,H,D} instruction. If such a sequence
5073 is found, attempt to step through it. A breakpoint is placed at the end of
5077 thumb_deal_with_atomic_sequence_raw (struct frame_info
*frame
)
5079 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5080 struct address_space
*aspace
= get_frame_address_space (frame
);
5081 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5082 CORE_ADDR pc
= get_frame_pc (frame
);
5083 CORE_ADDR breaks
[2] = {-1, -1};
5085 unsigned short insn1
, insn2
;
5088 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
5089 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
5090 ULONGEST status
, itstate
;
5092 /* We currently do not support atomic sequences within an IT block. */
5093 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
5094 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
5098 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. */
5099 insn1
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5101 if (thumb_insn_size (insn1
) != 4)
5104 insn2
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5106 if (!((insn1
& 0xfff0) == 0xe850
5107 || ((insn1
& 0xfff0) == 0xe8d0 && (insn2
& 0x00c0) == 0x0040)))
5110 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5112 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
5114 insn1
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5117 if (thumb_insn_size (insn1
) != 4)
5119 /* Assume that there is at most one conditional branch in the
5120 atomic sequence. If a conditional branch is found, put a
5121 breakpoint in its destination address. */
5122 if ((insn1
& 0xf000) == 0xd000 && bits (insn1
, 8, 11) != 0x0f)
5124 if (last_breakpoint
> 0)
5125 return 0; /* More than one conditional branch found,
5126 fallback to the standard code. */
5128 breaks
[1] = loc
+ 2 + (sbits (insn1
, 0, 7) << 1);
5132 /* We do not support atomic sequences that use any *other*
5133 instructions but conditional branches to change the PC.
5134 Fall back to standard code to avoid losing control of
5136 else if (thumb_instruction_changes_pc (insn1
))
5141 insn2
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5144 /* Assume that there is at most one conditional branch in the
5145 atomic sequence. If a conditional branch is found, put a
5146 breakpoint in its destination address. */
5147 if ((insn1
& 0xf800) == 0xf000
5148 && (insn2
& 0xd000) == 0x8000
5149 && (insn1
& 0x0380) != 0x0380)
5151 int sign
, j1
, j2
, imm1
, imm2
;
5152 unsigned int offset
;
5154 sign
= sbits (insn1
, 10, 10);
5155 imm1
= bits (insn1
, 0, 5);
5156 imm2
= bits (insn2
, 0, 10);
5157 j1
= bit (insn2
, 13);
5158 j2
= bit (insn2
, 11);
5160 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
5161 offset
+= (imm1
<< 12) + (imm2
<< 1);
5163 if (last_breakpoint
> 0)
5164 return 0; /* More than one conditional branch found,
5165 fallback to the standard code. */
5167 breaks
[1] = loc
+ offset
;
5171 /* We do not support atomic sequences that use any *other*
5172 instructions but conditional branches to change the PC.
5173 Fall back to standard code to avoid losing control of
5175 else if (thumb2_instruction_changes_pc (insn1
, insn2
))
5178 /* If we find a strex{,b,h,d}, we're done. */
5179 if ((insn1
& 0xfff0) == 0xe840
5180 || ((insn1
& 0xfff0) == 0xe8c0 && (insn2
& 0x00c0) == 0x0040))
5185 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5186 if (insn_count
== atomic_sequence_length
)
5189 /* Insert a breakpoint right after the end of the atomic sequence. */
5192 /* Check for duplicated breakpoints. Check also for a breakpoint
5193 placed (branch instruction's destination) anywhere in sequence. */
5195 && (breaks
[1] == breaks
[0]
5196 || (breaks
[1] >= pc
&& breaks
[1] < loc
)))
5197 last_breakpoint
= 0;
5199 /* Effectively inserts the breakpoints. */
5200 for (index
= 0; index
<= last_breakpoint
; index
++)
5201 arm_insert_single_step_breakpoint (gdbarch
, aspace
,
5202 MAKE_THUMB_ADDR (breaks
[index
]));
5208 arm_deal_with_atomic_sequence_raw (struct frame_info
*frame
)
5210 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5211 struct address_space
*aspace
= get_frame_address_space (frame
);
5212 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5213 CORE_ADDR pc
= get_frame_pc (frame
);
5214 CORE_ADDR breaks
[2] = {-1, -1};
5219 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
5220 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
5222 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction.
5223 Note that we do not currently support conditionally executed atomic
5225 insn
= read_memory_unsigned_integer (loc
, 4, byte_order_for_code
);
5227 if ((insn
& 0xff9000f0) != 0xe1900090)
5230 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5232 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
5234 insn
= read_memory_unsigned_integer (loc
, 4, byte_order_for_code
);
5237 /* Assume that there is at most one conditional branch in the atomic
5238 sequence. If a conditional branch is found, put a breakpoint in
5239 its destination address. */
5240 if (bits (insn
, 24, 27) == 0xa)
5242 if (last_breakpoint
> 0)
5243 return 0; /* More than one conditional branch found, fallback
5244 to the standard single-step code. */
5246 breaks
[1] = BranchDest (loc
- 4, insn
);
5250 /* We do not support atomic sequences that use any *other* instructions
5251 but conditional branches to change the PC. Fall back to standard
5252 code to avoid losing control of execution. */
5253 else if (arm_instruction_changes_pc (insn
))
5256 /* If we find a strex{,b,h,d}, we're done. */
5257 if ((insn
& 0xff9000f0) == 0xe1800090)
5261 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5262 if (insn_count
== atomic_sequence_length
)
5265 /* Insert a breakpoint right after the end of the atomic sequence. */
5268 /* Check for duplicated breakpoints. Check also for a breakpoint
5269 placed (branch instruction's destination) anywhere in sequence. */
5271 && (breaks
[1] == breaks
[0]
5272 || (breaks
[1] >= pc
&& breaks
[1] < loc
)))
5273 last_breakpoint
= 0;
5275 /* Effectively inserts the breakpoints. */
5276 for (index
= 0; index
<= last_breakpoint
; index
++)
5277 arm_insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
5283 arm_deal_with_atomic_sequence (struct frame_info
*frame
)
5285 if (arm_frame_is_thumb (frame
))
5286 return thumb_deal_with_atomic_sequence_raw (frame
);
5288 return arm_deal_with_atomic_sequence_raw (frame
);
5291 /* single_step() is called just before we want to resume the inferior,
5292 if we want to single-step it but there is no hardware or kernel
5293 single-step support. We find the target of the coming instruction
5294 and breakpoint it. */
5297 arm_software_single_step (struct frame_info
*frame
)
5299 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5300 struct address_space
*aspace
= get_frame_address_space (frame
);
5303 if (arm_deal_with_atomic_sequence (frame
))
5306 next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
5307 arm_insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
5312 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
5313 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
5314 NULL if an error occurs. BUF is freed. */
5317 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
5318 int old_len
, int new_len
)
5321 int bytes_to_read
= new_len
- old_len
;
5323 new_buf
= xmalloc (new_len
);
5324 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
5326 if (target_read_memory (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
5334 /* An IT block is at most the 2-byte IT instruction followed by
5335 four 4-byte instructions. The furthest back we must search to
5336 find an IT block that affects the current instruction is thus
5337 2 + 3 * 4 == 14 bytes. */
5338 #define MAX_IT_BLOCK_PREFIX 14
5340 /* Use a quick scan if there are more than this many bytes of
5342 #define IT_SCAN_THRESHOLD 32
5344 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
5345 A breakpoint in an IT block may not be hit, depending on the
5348 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
5352 CORE_ADDR boundary
, func_start
;
5354 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
5355 int i
, any
, last_it
, last_it_count
;
5357 /* If we are using BKPT breakpoints, none of this is necessary. */
5358 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
5361 /* ARM mode does not have this problem. */
5362 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
5365 /* We are setting a breakpoint in Thumb code that could potentially
5366 contain an IT block. The first step is to find how much Thumb
5367 code there is; we do not need to read outside of known Thumb
5369 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
5371 /* Thumb-2 code must have mapping symbols to have a chance. */
5374 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
5376 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
5377 && func_start
> boundary
)
5378 boundary
= func_start
;
5380 /* Search for a candidate IT instruction. We have to do some fancy
5381 footwork to distinguish a real IT instruction from the second
5382 half of a 32-bit instruction, but there is no need for that if
5383 there's no candidate. */
5384 buf_len
= min (bpaddr
- boundary
, MAX_IT_BLOCK_PREFIX
);
5386 /* No room for an IT instruction. */
5389 buf
= xmalloc (buf_len
);
5390 if (target_read_memory (bpaddr
- buf_len
, buf
, buf_len
) != 0)
5393 for (i
= 0; i
< buf_len
; i
+= 2)
5395 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5396 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
5408 /* OK, the code bytes before this instruction contain at least one
5409 halfword which resembles an IT instruction. We know that it's
5410 Thumb code, but there are still two possibilities. Either the
5411 halfword really is an IT instruction, or it is the second half of
5412 a 32-bit Thumb instruction. The only way we can tell is to
5413 scan forwards from a known instruction boundary. */
5414 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
5418 /* There's a lot of code before this instruction. Start with an
5419 optimistic search; it's easy to recognize halfwords that can
5420 not be the start of a 32-bit instruction, and use that to
5421 lock on to the instruction boundaries. */
5422 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
5425 buf_len
= IT_SCAN_THRESHOLD
;
5428 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
5430 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5431 if (thumb_insn_size (inst1
) == 2)
5438 /* At this point, if DEFINITE, BUF[I] is the first place we
5439 are sure that we know the instruction boundaries, and it is far
5440 enough from BPADDR that we could not miss an IT instruction
5441 affecting BPADDR. If ! DEFINITE, give up - start from a
5445 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
,
5449 buf_len
= bpaddr
- boundary
;
5455 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
5458 buf_len
= bpaddr
- boundary
;
5462 /* Scan forwards. Find the last IT instruction before BPADDR. */
5467 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5469 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
5474 else if (inst1
& 0x0002)
5476 else if (inst1
& 0x0004)
5481 i
+= thumb_insn_size (inst1
);
5487 /* There wasn't really an IT instruction after all. */
5490 if (last_it_count
< 1)
5491 /* It was too far away. */
5494 /* This really is a trouble spot. Move the breakpoint to the IT
5496 return bpaddr
- buf_len
+ last_it
;
5499 /* ARM displaced stepping support.
5501 Generally ARM displaced stepping works as follows:
5503 1. When an instruction is to be single-stepped, it is first decoded by
5504 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
5505 Depending on the type of instruction, it is then copied to a scratch
5506 location, possibly in a modified form. The copy_* set of functions
5507 performs such modification, as necessary. A breakpoint is placed after
5508 the modified instruction in the scratch space to return control to GDB.
5509 Note in particular that instructions which modify the PC will no longer
5510 do so after modification.
5512 2. The instruction is single-stepped, by setting the PC to the scratch
5513 location address, and resuming. Control returns to GDB when the
5516 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
5517 function used for the current instruction. This function's job is to
5518 put the CPU/memory state back to what it would have been if the
5519 instruction had been executed unmodified in its original location. */
5521 /* NOP instruction (mov r0, r0). */
5522 #define ARM_NOP 0xe1a00000
5523 #define THUMB_NOP 0x4600
5525 /* Helper for register reads for displaced stepping. In particular, this
5526 returns the PC as it would be seen by the instruction at its original
5530 displaced_read_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5534 CORE_ADDR from
= dsc
->insn_addr
;
5536 if (regno
== ARM_PC_REGNUM
)
5538 /* Compute pipeline offset:
5539 - When executing an ARM instruction, PC reads as the address of the
5540 current instruction plus 8.
5541 - When executing a Thumb instruction, PC reads as the address of the
5542 current instruction plus 4. */
5549 if (debug_displaced
)
5550 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
5551 (unsigned long) from
);
5552 return (ULONGEST
) from
;
5556 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
5557 if (debug_displaced
)
5558 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
5559 regno
, (unsigned long) ret
);
5565 displaced_in_arm_mode (struct regcache
*regs
)
5568 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
5570 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
5572 return (ps
& t_bit
) == 0;
5575 /* Write to the PC as from a branch instruction. */
5578 branch_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5582 /* Note: If bits 0/1 are set, this branch would be unpredictable for
5583 architecture versions < 6. */
5584 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
5585 val
& ~(ULONGEST
) 0x3);
5587 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
5588 val
& ~(ULONGEST
) 0x1);
5591 /* Write to the PC as from a branch-exchange instruction. */
5594 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
5597 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
5599 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
5603 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
5604 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
5606 else if ((val
& 2) == 0)
5608 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
5609 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
5613 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
5614 mode, align dest to 4 bytes). */
5615 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
5616 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
5617 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
5621 /* Write to the PC as if from a load instruction. */
5624 load_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5627 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
5628 bx_write_pc (regs
, val
);
5630 branch_write_pc (regs
, dsc
, val
);
5633 /* Write to the PC as if from an ALU instruction. */
5636 alu_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5639 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && !dsc
->is_thumb
)
5640 bx_write_pc (regs
, val
);
5642 branch_write_pc (regs
, dsc
, val
);
5645 /* Helper for writing to registers for displaced stepping. Writing to the PC
5646 has a varying effects depending on the instruction which does the write:
5647 this is controlled by the WRITE_PC argument. */
5650 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5651 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
5653 if (regno
== ARM_PC_REGNUM
)
5655 if (debug_displaced
)
5656 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
5657 (unsigned long) val
);
5660 case BRANCH_WRITE_PC
:
5661 branch_write_pc (regs
, dsc
, val
);
5665 bx_write_pc (regs
, val
);
5669 load_write_pc (regs
, dsc
, val
);
5673 alu_write_pc (regs
, dsc
, val
);
5676 case CANNOT_WRITE_PC
:
5677 warning (_("Instruction wrote to PC in an unexpected way when "
5678 "single-stepping"));
5682 internal_error (__FILE__
, __LINE__
,
5683 _("Invalid argument to displaced_write_reg"));
5686 dsc
->wrote_to_pc
= 1;
5690 if (debug_displaced
)
5691 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
5692 regno
, (unsigned long) val
);
5693 regcache_cooked_write_unsigned (regs
, regno
, val
);
5697 /* This function is used to concisely determine if an instruction INSN
5698 references PC. Register fields of interest in INSN should have the
5699 corresponding fields of BITMASK set to 0b1111. The function
5700 returns return 1 if any of these fields in INSN reference the PC
5701 (also 0b1111, r15), else it returns 0. */
5704 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
5706 uint32_t lowbit
= 1;
5708 while (bitmask
!= 0)
5712 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
5718 mask
= lowbit
* 0xf;
5720 if ((insn
& mask
) == mask
)
5729 /* The simplest copy function. Many instructions have the same effect no
5730 matter what address they are executed at: in those cases, use this. */
5733 arm_copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
5734 const char *iname
, struct displaced_step_closure
*dsc
)
5736 if (debug_displaced
)
5737 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
5738 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
5741 dsc
->modinsn
[0] = insn
;
5747 thumb_copy_unmodified_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
5748 uint16_t insn2
, const char *iname
,
5749 struct displaced_step_closure
*dsc
)
5751 if (debug_displaced
)
5752 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x %.4x, "
5753 "opcode/class '%s' unmodified\n", insn1
, insn2
,
5756 dsc
->modinsn
[0] = insn1
;
5757 dsc
->modinsn
[1] = insn2
;
5763 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
5766 thumb_copy_unmodified_16bit (struct gdbarch
*gdbarch
, unsigned int insn
,
5768 struct displaced_step_closure
*dsc
)
5770 if (debug_displaced
)
5771 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x, "
5772 "opcode/class '%s' unmodified\n", insn
,
5775 dsc
->modinsn
[0] = insn
;
5780 /* Preload instructions with immediate offset. */
5783 cleanup_preload (struct gdbarch
*gdbarch
,
5784 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5786 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5787 if (!dsc
->u
.preload
.immed
)
5788 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5792 install_preload (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5793 struct displaced_step_closure
*dsc
, unsigned int rn
)
5796 /* Preload instructions:
5798 {pli/pld} [rn, #+/-imm]
5800 {pli/pld} [r0, #+/-imm]. */
5802 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5803 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5804 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5805 dsc
->u
.preload
.immed
= 1;
5807 dsc
->cleanup
= &cleanup_preload
;
5811 arm_copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5812 struct displaced_step_closure
*dsc
)
5814 unsigned int rn
= bits (insn
, 16, 19);
5816 if (!insn_references_pc (insn
, 0x000f0000ul
))
5817 return arm_copy_unmodified (gdbarch
, insn
, "preload", dsc
);
5819 if (debug_displaced
)
5820 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
5821 (unsigned long) insn
);
5823 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
5825 install_preload (gdbarch
, regs
, dsc
, rn
);
5831 thumb2_copy_preload (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
5832 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5834 unsigned int rn
= bits (insn1
, 0, 3);
5835 unsigned int u_bit
= bit (insn1
, 7);
5836 int imm12
= bits (insn2
, 0, 11);
5839 if (rn
!= ARM_PC_REGNUM
)
5840 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "preload", dsc
);
5842 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
5843 PLD (literal) Encoding T1. */
5844 if (debug_displaced
)
5845 fprintf_unfiltered (gdb_stdlog
,
5846 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
5847 (unsigned int) dsc
->insn_addr
, u_bit
? '+' : '-',
5853 /* Rewrite instruction {pli/pld} PC imm12 into:
5854 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
5858 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
5860 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5861 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5863 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
5865 displaced_write_reg (regs
, dsc
, 0, pc_val
, CANNOT_WRITE_PC
);
5866 displaced_write_reg (regs
, dsc
, 1, imm12
, CANNOT_WRITE_PC
);
5867 dsc
->u
.preload
.immed
= 0;
5869 /* {pli/pld} [r0, r1] */
5870 dsc
->modinsn
[0] = insn1
& 0xfff0;
5871 dsc
->modinsn
[1] = 0xf001;
5874 dsc
->cleanup
= &cleanup_preload
;
5878 /* Preload instructions with register offset. */
5881 install_preload_reg(struct gdbarch
*gdbarch
, struct regcache
*regs
,
5882 struct displaced_step_closure
*dsc
, unsigned int rn
,
5885 ULONGEST rn_val
, rm_val
;
5887 /* Preload register-offset instructions:
5889 {pli/pld} [rn, rm {, shift}]
5891 {pli/pld} [r0, r1 {, shift}]. */
5893 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5894 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5895 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5896 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5897 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5898 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
5899 dsc
->u
.preload
.immed
= 0;
5901 dsc
->cleanup
= &cleanup_preload
;
5905 arm_copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5906 struct regcache
*regs
,
5907 struct displaced_step_closure
*dsc
)
5909 unsigned int rn
= bits (insn
, 16, 19);
5910 unsigned int rm
= bits (insn
, 0, 3);
5913 if (!insn_references_pc (insn
, 0x000f000ful
))
5914 return arm_copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
5916 if (debug_displaced
)
5917 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
5918 (unsigned long) insn
);
5920 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
5922 install_preload_reg (gdbarch
, regs
, dsc
, rn
, rm
);
5926 /* Copy/cleanup coprocessor load and store instructions. */
5929 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
5930 struct regcache
*regs
,
5931 struct displaced_step_closure
*dsc
)
5933 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 0);
5935 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5937 if (dsc
->u
.ldst
.writeback
)
5938 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
5942 install_copro_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5943 struct displaced_step_closure
*dsc
,
5944 int writeback
, unsigned int rn
)
5948 /* Coprocessor load/store instructions:
5950 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
5952 {stc/stc2} [r0, #+/-imm].
5954 ldc/ldc2 are handled identically. */
5956 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5957 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5958 /* PC should be 4-byte aligned. */
5959 rn_val
= rn_val
& 0xfffffffc;
5960 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5962 dsc
->u
.ldst
.writeback
= writeback
;
5963 dsc
->u
.ldst
.rn
= rn
;
5965 dsc
->cleanup
= &cleanup_copro_load_store
;
5969 arm_copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
5970 struct regcache
*regs
,
5971 struct displaced_step_closure
*dsc
)
5973 unsigned int rn
= bits (insn
, 16, 19);
5975 if (!insn_references_pc (insn
, 0x000f0000ul
))
5976 return arm_copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
5978 if (debug_displaced
)
5979 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
5980 "load/store insn %.8lx\n", (unsigned long) insn
);
5982 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
5984 install_copro_load_store (gdbarch
, regs
, dsc
, bit (insn
, 25), rn
);
5990 thumb2_copy_copro_load_store (struct gdbarch
*gdbarch
, uint16_t insn1
,
5991 uint16_t insn2
, struct regcache
*regs
,
5992 struct displaced_step_closure
*dsc
)
5994 unsigned int rn
= bits (insn1
, 0, 3);
5996 if (rn
!= ARM_PC_REGNUM
)
5997 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
5998 "copro load/store", dsc
);
6000 if (debug_displaced
)
6001 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
6002 "load/store insn %.4x%.4x\n", insn1
, insn2
);
6004 dsc
->modinsn
[0] = insn1
& 0xfff0;
6005 dsc
->modinsn
[1] = insn2
;
6008 /* This function is called for copying instruction LDC/LDC2/VLDR, which
6009 doesn't support writeback, so pass 0. */
6010 install_copro_load_store (gdbarch
, regs
, dsc
, 0, rn
);
6015 /* Clean up branch instructions (actually perform the branch, by setting
6019 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6020 struct displaced_step_closure
*dsc
)
6022 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6023 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
6024 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
6025 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
6030 if (dsc
->u
.branch
.link
)
6032 /* The value of LR should be the next insn of current one. In order
6033 not to confuse logic hanlding later insn `bx lr', if current insn mode
6034 is Thumb, the bit 0 of LR value should be set to 1. */
6035 ULONGEST next_insn_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
6038 next_insn_addr
|= 0x1;
6040 displaced_write_reg (regs
, dsc
, ARM_LR_REGNUM
, next_insn_addr
,
6044 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, dsc
->u
.branch
.dest
, write_pc
);
6047 /* Copy B/BL/BLX instructions with immediate destinations. */
6050 install_b_bl_blx (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6051 struct displaced_step_closure
*dsc
,
6052 unsigned int cond
, int exchange
, int link
, long offset
)
6054 /* Implement "BL<cond> <label>" as:
6056 Preparation: cond <- instruction condition
6057 Insn: mov r0, r0 (nop)
6058 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
6060 B<cond> similar, but don't set r14 in cleanup. */
6062 dsc
->u
.branch
.cond
= cond
;
6063 dsc
->u
.branch
.link
= link
;
6064 dsc
->u
.branch
.exchange
= exchange
;
6066 dsc
->u
.branch
.dest
= dsc
->insn_addr
;
6067 if (link
&& exchange
)
6068 /* For BLX, offset is computed from the Align (PC, 4). */
6069 dsc
->u
.branch
.dest
= dsc
->u
.branch
.dest
& 0xfffffffc;
6072 dsc
->u
.branch
.dest
+= 4 + offset
;
6074 dsc
->u
.branch
.dest
+= 8 + offset
;
6076 dsc
->cleanup
= &cleanup_branch
;
6079 arm_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
6080 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6082 unsigned int cond
= bits (insn
, 28, 31);
6083 int exchange
= (cond
== 0xf);
6084 int link
= exchange
|| bit (insn
, 24);
6087 if (debug_displaced
)
6088 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
6089 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
6090 (unsigned long) insn
);
6092 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
6093 then arrange the switch into Thumb mode. */
6094 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
6096 offset
= bits (insn
, 0, 23) << 2;
6098 if (bit (offset
, 25))
6099 offset
= offset
| ~0x3ffffff;
6101 dsc
->modinsn
[0] = ARM_NOP
;
6103 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
6108 thumb2_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint16_t insn1
,
6109 uint16_t insn2
, struct regcache
*regs
,
6110 struct displaced_step_closure
*dsc
)
6112 int link
= bit (insn2
, 14);
6113 int exchange
= link
&& !bit (insn2
, 12);
6116 int j1
= bit (insn2
, 13);
6117 int j2
= bit (insn2
, 11);
6118 int s
= sbits (insn1
, 10, 10);
6119 int i1
= !(j1
^ bit (insn1
, 10));
6120 int i2
= !(j2
^ bit (insn1
, 10));
6122 if (!link
&& !exchange
) /* B */
6124 offset
= (bits (insn2
, 0, 10) << 1);
6125 if (bit (insn2
, 12)) /* Encoding T4 */
6127 offset
|= (bits (insn1
, 0, 9) << 12)
6133 else /* Encoding T3 */
6135 offset
|= (bits (insn1
, 0, 5) << 12)
6139 cond
= bits (insn1
, 6, 9);
6144 offset
= (bits (insn1
, 0, 9) << 12);
6145 offset
|= ((i2
<< 22) | (i1
<< 23) | (s
<< 24));
6146 offset
|= exchange
?
6147 (bits (insn2
, 1, 10) << 2) : (bits (insn2
, 0, 10) << 1);
6150 if (debug_displaced
)
6151 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s insn "
6152 "%.4x %.4x with offset %.8lx\n",
6153 link
? (exchange
) ? "blx" : "bl" : "b",
6154 insn1
, insn2
, offset
);
6156 dsc
->modinsn
[0] = THUMB_NOP
;
6158 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
6162 /* Copy B Thumb instructions. */
6164 thumb_copy_b (struct gdbarch
*gdbarch
, unsigned short insn
,
6165 struct displaced_step_closure
*dsc
)
6167 unsigned int cond
= 0;
6169 unsigned short bit_12_15
= bits (insn
, 12, 15);
6170 CORE_ADDR from
= dsc
->insn_addr
;
6172 if (bit_12_15
== 0xd)
6174 /* offset = SignExtend (imm8:0, 32) */
6175 offset
= sbits ((insn
<< 1), 0, 8);
6176 cond
= bits (insn
, 8, 11);
6178 else if (bit_12_15
== 0xe) /* Encoding T2 */
6180 offset
= sbits ((insn
<< 1), 0, 11);
6184 if (debug_displaced
)
6185 fprintf_unfiltered (gdb_stdlog
,
6186 "displaced: copying b immediate insn %.4x "
6187 "with offset %d\n", insn
, offset
);
6189 dsc
->u
.branch
.cond
= cond
;
6190 dsc
->u
.branch
.link
= 0;
6191 dsc
->u
.branch
.exchange
= 0;
6192 dsc
->u
.branch
.dest
= from
+ 4 + offset
;
6194 dsc
->modinsn
[0] = THUMB_NOP
;
6196 dsc
->cleanup
= &cleanup_branch
;
6201 /* Copy BX/BLX with register-specified destinations. */
6204 install_bx_blx_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6205 struct displaced_step_closure
*dsc
, int link
,
6206 unsigned int cond
, unsigned int rm
)
6208 /* Implement {BX,BLX}<cond> <reg>" as:
6210 Preparation: cond <- instruction condition
6211 Insn: mov r0, r0 (nop)
6212 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
6214 Don't set r14 in cleanup for BX. */
6216 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, dsc
, rm
);
6218 dsc
->u
.branch
.cond
= cond
;
6219 dsc
->u
.branch
.link
= link
;
6221 dsc
->u
.branch
.exchange
= 1;
6223 dsc
->cleanup
= &cleanup_branch
;
6227 arm_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
6228 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6230 unsigned int cond
= bits (insn
, 28, 31);
6233 int link
= bit (insn
, 5);
6234 unsigned int rm
= bits (insn
, 0, 3);
6236 if (debug_displaced
)
6237 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx",
6238 (unsigned long) insn
);
6240 dsc
->modinsn
[0] = ARM_NOP
;
6242 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, cond
, rm
);
6247 thumb_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
6248 struct regcache
*regs
,
6249 struct displaced_step_closure
*dsc
)
6251 int link
= bit (insn
, 7);
6252 unsigned int rm
= bits (insn
, 3, 6);
6254 if (debug_displaced
)
6255 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x",
6256 (unsigned short) insn
);
6258 dsc
->modinsn
[0] = THUMB_NOP
;
6260 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, INST_AL
, rm
);
6266 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
6269 cleanup_alu_imm (struct gdbarch
*gdbarch
,
6270 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6272 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
6273 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6274 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6275 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6279 arm_copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
6280 struct displaced_step_closure
*dsc
)
6282 unsigned int rn
= bits (insn
, 16, 19);
6283 unsigned int rd
= bits (insn
, 12, 15);
6284 unsigned int op
= bits (insn
, 21, 24);
6285 int is_mov
= (op
== 0xd);
6286 ULONGEST rd_val
, rn_val
;
6288 if (!insn_references_pc (insn
, 0x000ff000ul
))
6289 return arm_copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
6291 if (debug_displaced
)
6292 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
6293 "%.8lx\n", is_mov
? "move" : "ALU",
6294 (unsigned long) insn
);
6296 /* Instruction is of form:
6298 <op><cond> rd, [rn,] #imm
6302 Preparation: tmp1, tmp2 <- r0, r1;
6304 Insn: <op><cond> r0, r1, #imm
6305 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6308 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6309 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6310 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6311 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6312 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6313 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6317 dsc
->modinsn
[0] = insn
& 0xfff00fff;
6319 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
6321 dsc
->cleanup
= &cleanup_alu_imm
;
6327 thumb2_copy_alu_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
6328 uint16_t insn2
, struct regcache
*regs
,
6329 struct displaced_step_closure
*dsc
)
6331 unsigned int op
= bits (insn1
, 5, 8);
6332 unsigned int rn
, rm
, rd
;
6333 ULONGEST rd_val
, rn_val
;
6335 rn
= bits (insn1
, 0, 3); /* Rn */
6336 rm
= bits (insn2
, 0, 3); /* Rm */
6337 rd
= bits (insn2
, 8, 11); /* Rd */
6339 /* This routine is only called for instruction MOV. */
6340 gdb_assert (op
== 0x2 && rn
== 0xf);
6342 if (rm
!= ARM_PC_REGNUM
&& rd
!= ARM_PC_REGNUM
)
6343 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ALU imm", dsc
);
6345 if (debug_displaced
)
6346 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x%.4x\n",
6347 "ALU", insn1
, insn2
);
6349 /* Instruction is of form:
6351 <op><cond> rd, [rn,] #imm
6355 Preparation: tmp1, tmp2 <- r0, r1;
6357 Insn: <op><cond> r0, r1, #imm
6358 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6361 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6362 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6363 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6364 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6365 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6366 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6369 dsc
->modinsn
[0] = insn1
;
6370 dsc
->modinsn
[1] = ((insn2
& 0xf0f0) | 0x1);
6373 dsc
->cleanup
= &cleanup_alu_imm
;
6378 /* Copy/cleanup arithmetic/logic insns with register RHS. */
6381 cleanup_alu_reg (struct gdbarch
*gdbarch
,
6382 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6387 rd_val
= displaced_read_reg (regs
, dsc
, 0);
6389 for (i
= 0; i
< 3; i
++)
6390 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
6392 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6396 install_alu_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6397 struct displaced_step_closure
*dsc
,
6398 unsigned int rd
, unsigned int rn
, unsigned int rm
)
6400 ULONGEST rd_val
, rn_val
, rm_val
;
6402 /* Instruction is of form:
6404 <op><cond> rd, [rn,] rm [, <shift>]
6408 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
6409 r0, r1, r2 <- rd, rn, rm
6410 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
6411 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
6414 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6415 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6416 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6417 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6418 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6419 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6420 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6421 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6422 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
6425 dsc
->cleanup
= &cleanup_alu_reg
;
6429 arm_copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
6430 struct displaced_step_closure
*dsc
)
6432 unsigned int op
= bits (insn
, 21, 24);
6433 int is_mov
= (op
== 0xd);
6435 if (!insn_references_pc (insn
, 0x000ff00ful
))
6436 return arm_copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
6438 if (debug_displaced
)
6439 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
6440 is_mov
? "move" : "ALU", (unsigned long) insn
);
6443 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
6445 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
6447 install_alu_reg (gdbarch
, regs
, dsc
, bits (insn
, 12, 15), bits (insn
, 16, 19),
6453 thumb_copy_alu_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
6454 struct regcache
*regs
,
6455 struct displaced_step_closure
*dsc
)
6459 rm
= bits (insn
, 3, 6);
6460 rd
= (bit (insn
, 7) << 3) | bits (insn
, 0, 2);
6462 if (rd
!= ARM_PC_REGNUM
&& rm
!= ARM_PC_REGNUM
)
6463 return thumb_copy_unmodified_16bit (gdbarch
, insn
, "ALU reg", dsc
);
6465 if (debug_displaced
)
6466 fprintf_unfiltered (gdb_stdlog
, "displaced: copying ALU reg insn %.4x\n",
6467 (unsigned short) insn
);
6469 dsc
->modinsn
[0] = ((insn
& 0xff00) | 0x10);
6471 install_alu_reg (gdbarch
, regs
, dsc
, rd
, rd
, rm
);
6476 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
6479 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
6480 struct regcache
*regs
,
6481 struct displaced_step_closure
*dsc
)
6483 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
6486 for (i
= 0; i
< 4; i
++)
6487 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
6489 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6493 install_alu_shifted_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6494 struct displaced_step_closure
*dsc
,
6495 unsigned int rd
, unsigned int rn
, unsigned int rm
,
6499 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
6501 /* Instruction is of form:
6503 <op><cond> rd, [rn,] rm, <shift> rs
6507 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
6508 r0, r1, r2, r3 <- rd, rn, rm, rs
6509 Insn: <op><cond> r0, r1, r2, <shift> r3
6511 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
6515 for (i
= 0; i
< 4; i
++)
6516 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6518 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6519 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6520 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6521 rs_val
= displaced_read_reg (regs
, dsc
, rs
);
6522 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6523 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6524 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
6525 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
6527 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
6531 arm_copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
6532 struct regcache
*regs
,
6533 struct displaced_step_closure
*dsc
)
6535 unsigned int op
= bits (insn
, 21, 24);
6536 int is_mov
= (op
== 0xd);
6537 unsigned int rd
, rn
, rm
, rs
;
6539 if (!insn_references_pc (insn
, 0x000fff0ful
))
6540 return arm_copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
6542 if (debug_displaced
)
6543 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
6544 "%.8lx\n", is_mov
? "move" : "ALU",
6545 (unsigned long) insn
);
6547 rn
= bits (insn
, 16, 19);
6548 rm
= bits (insn
, 0, 3);
6549 rs
= bits (insn
, 8, 11);
6550 rd
= bits (insn
, 12, 15);
6553 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
6555 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
6557 install_alu_shifted_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
, rs
);
6562 /* Clean up load instructions. */
6565 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6566 struct displaced_step_closure
*dsc
)
6568 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
6570 rt_val
= displaced_read_reg (regs
, dsc
, 0);
6571 if (dsc
->u
.ldst
.xfersize
== 8)
6572 rt_val2
= displaced_read_reg (regs
, dsc
, 1);
6573 rn_val
= displaced_read_reg (regs
, dsc
, 2);
6575 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6576 if (dsc
->u
.ldst
.xfersize
> 4)
6577 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6578 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
6579 if (!dsc
->u
.ldst
.immed
)
6580 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
6582 /* Handle register writeback. */
6583 if (dsc
->u
.ldst
.writeback
)
6584 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
6585 /* Put result in right place. */
6586 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
6587 if (dsc
->u
.ldst
.xfersize
== 8)
6588 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
6591 /* Clean up store instructions. */
6594 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6595 struct displaced_step_closure
*dsc
)
6597 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 2);
6599 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6600 if (dsc
->u
.ldst
.xfersize
> 4)
6601 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6602 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
6603 if (!dsc
->u
.ldst
.immed
)
6604 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
6605 if (!dsc
->u
.ldst
.restore_r4
)
6606 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
6609 if (dsc
->u
.ldst
.writeback
)
6610 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
6613 /* Copy "extra" load/store instructions. These are halfword/doubleword
6614 transfers, which have a different encoding to byte/word transfers. */
6617 arm_copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unpriveleged
,
6618 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6620 unsigned int op1
= bits (insn
, 20, 24);
6621 unsigned int op2
= bits (insn
, 5, 6);
6622 unsigned int rt
= bits (insn
, 12, 15);
6623 unsigned int rn
= bits (insn
, 16, 19);
6624 unsigned int rm
= bits (insn
, 0, 3);
6625 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
6626 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
6627 int immed
= (op1
& 0x4) != 0;
6629 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
6631 if (!insn_references_pc (insn
, 0x000ff00ful
))
6632 return arm_copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
6634 if (debug_displaced
)
6635 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
6636 "insn %.8lx\n", unpriveleged
? "unpriveleged " : "",
6637 (unsigned long) insn
);
6639 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
6642 internal_error (__FILE__
, __LINE__
,
6643 _("copy_extra_ld_st: instruction decode error"));
6645 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6646 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6647 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6649 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6651 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
6652 if (bytesize
[opcode
] == 8)
6653 rt_val2
= displaced_read_reg (regs
, dsc
, rt
+ 1);
6654 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6656 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6658 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
6659 if (bytesize
[opcode
] == 8)
6660 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
6661 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
6663 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
6666 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
6667 dsc
->u
.ldst
.rn
= rn
;
6668 dsc
->u
.ldst
.immed
= immed
;
6669 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
6670 dsc
->u
.ldst
.restore_r4
= 0;
6673 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
6675 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
6676 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
6678 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
6680 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
6681 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
6683 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
6688 /* Copy byte/half word/word loads and stores. */
6691 install_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6692 struct displaced_step_closure
*dsc
, int load
,
6693 int immed
, int writeback
, int size
, int usermode
,
6694 int rt
, int rm
, int rn
)
6696 ULONGEST rt_val
, rn_val
, rm_val
= 0;
6698 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6699 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6701 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6703 dsc
->tmp
[4] = displaced_read_reg (regs
, dsc
, 4);
6705 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
6706 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6708 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6710 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
6711 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
6713 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
6715 dsc
->u
.ldst
.xfersize
= size
;
6716 dsc
->u
.ldst
.rn
= rn
;
6717 dsc
->u
.ldst
.immed
= immed
;
6718 dsc
->u
.ldst
.writeback
= writeback
;
6720 /* To write PC we can do:
6722 Before this sequence of instructions:
6723 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
6724 r2 is the Rn value got from dispalced_read_reg.
6726 Insn1: push {pc} Write address of STR instruction + offset on stack
6727 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
6728 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
6729 = addr(Insn1) + offset - addr(Insn3) - 8
6731 Insn4: add r4, r4, #8 r4 = offset - 8
6732 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
6734 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
6736 Otherwise we don't know what value to write for PC, since the offset is
6737 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
6738 of this can be found in Section "Saving from r15" in
6739 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
6741 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
6746 thumb2_copy_load_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
6747 uint16_t insn2
, struct regcache
*regs
,
6748 struct displaced_step_closure
*dsc
, int size
)
6750 unsigned int u_bit
= bit (insn1
, 7);
6751 unsigned int rt
= bits (insn2
, 12, 15);
6752 int imm12
= bits (insn2
, 0, 11);
6755 if (debug_displaced
)
6756 fprintf_unfiltered (gdb_stdlog
,
6757 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
6758 (unsigned int) dsc
->insn_addr
, rt
, u_bit
? '+' : '-',
6764 /* Rewrite instruction LDR Rt imm12 into:
6766 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
6770 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
6773 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6774 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6775 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6777 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
6779 pc_val
= pc_val
& 0xfffffffc;
6781 displaced_write_reg (regs
, dsc
, 2, pc_val
, CANNOT_WRITE_PC
);
6782 displaced_write_reg (regs
, dsc
, 3, imm12
, CANNOT_WRITE_PC
);
6786 dsc
->u
.ldst
.xfersize
= size
;
6787 dsc
->u
.ldst
.immed
= 0;
6788 dsc
->u
.ldst
.writeback
= 0;
6789 dsc
->u
.ldst
.restore_r4
= 0;
6791 /* LDR R0, R2, R3 */
6792 dsc
->modinsn
[0] = 0xf852;
6793 dsc
->modinsn
[1] = 0x3;
6796 dsc
->cleanup
= &cleanup_load
;
6802 thumb2_copy_load_reg_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
6803 uint16_t insn2
, struct regcache
*regs
,
6804 struct displaced_step_closure
*dsc
,
6805 int writeback
, int immed
)
6807 unsigned int rt
= bits (insn2
, 12, 15);
6808 unsigned int rn
= bits (insn1
, 0, 3);
6809 unsigned int rm
= bits (insn2
, 0, 3); /* Only valid if !immed. */
6810 /* In LDR (register), there is also a register Rm, which is not allowed to
6811 be PC, so we don't have to check it. */
6813 if (rt
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
6814 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "load",
6817 if (debug_displaced
)
6818 fprintf_unfiltered (gdb_stdlog
,
6819 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
6820 rt
, rn
, insn1
, insn2
);
6822 install_load_store (gdbarch
, regs
, dsc
, 1, immed
, writeback
, 4,
6825 dsc
->u
.ldst
.restore_r4
= 0;
6828 /* ldr[b]<cond> rt, [rn, #imm], etc.
6830 ldr[b]<cond> r0, [r2, #imm]. */
6832 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
6833 dsc
->modinsn
[1] = insn2
& 0x0fff;
6836 /* ldr[b]<cond> rt, [rn, rm], etc.
6838 ldr[b]<cond> r0, [r2, r3]. */
6840 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
6841 dsc
->modinsn
[1] = (insn2
& 0x0ff0) | 0x3;
6851 arm_copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
6852 struct regcache
*regs
,
6853 struct displaced_step_closure
*dsc
,
6854 int load
, int size
, int usermode
)
6856 int immed
= !bit (insn
, 25);
6857 int writeback
= (bit (insn
, 24) == 0 || bit (insn
, 21) != 0);
6858 unsigned int rt
= bits (insn
, 12, 15);
6859 unsigned int rn
= bits (insn
, 16, 19);
6860 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
6862 if (!insn_references_pc (insn
, 0x000ff00ful
))
6863 return arm_copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
6865 if (debug_displaced
)
6866 fprintf_unfiltered (gdb_stdlog
,
6867 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
6868 load
? (size
== 1 ? "ldrb" : "ldr")
6869 : (size
== 1 ? "strb" : "str"), usermode
? "t" : "",
6871 (unsigned long) insn
);
6873 install_load_store (gdbarch
, regs
, dsc
, load
, immed
, writeback
, size
,
6874 usermode
, rt
, rm
, rn
);
6876 if (load
|| rt
!= ARM_PC_REGNUM
)
6878 dsc
->u
.ldst
.restore_r4
= 0;
6881 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
6883 {ldr,str}[b]<cond> r0, [r2, #imm]. */
6884 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
6886 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
6888 {ldr,str}[b]<cond> r0, [r2, r3]. */
6889 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
6893 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
6894 dsc
->u
.ldst
.restore_r4
= 1;
6895 dsc
->modinsn
[0] = 0xe92d8000; /* push {pc} */
6896 dsc
->modinsn
[1] = 0xe8bd0010; /* pop {r4} */
6897 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
6898 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
6899 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
6903 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
6905 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
6910 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
6915 /* Cleanup LDM instructions with fully-populated register list. This is an
6916 unfortunate corner case: it's impossible to implement correctly by modifying
6917 the instruction. The issue is as follows: we have an instruction,
6921 which we must rewrite to avoid loading PC. A possible solution would be to
6922 do the load in two halves, something like (with suitable cleanup
6926 ldm[id][ab] r8!, {r0-r7}
6928 ldm[id][ab] r8, {r7-r14}
6931 but at present there's no suitable place for <temp>, since the scratch space
6932 is overwritten before the cleanup routine is called. For now, we simply
6933 emulate the instruction. */
6936 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6937 struct displaced_step_closure
*dsc
)
6939 int inc
= dsc
->u
.block
.increment
;
6940 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
6941 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
6942 uint32_t regmask
= dsc
->u
.block
.regmask
;
6943 int regno
= inc
? 0 : 15;
6944 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
6945 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
6946 && (regmask
& 0x8000) != 0;
6947 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6948 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
6949 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6954 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
6955 sensible we can do here. Complain loudly. */
6956 if (exception_return
)
6957 error (_("Cannot single-step exception return"));
6959 /* We don't handle any stores here for now. */
6960 gdb_assert (dsc
->u
.block
.load
!= 0);
6962 if (debug_displaced
)
6963 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
6964 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
6965 dsc
->u
.block
.increment
? "inc" : "dec",
6966 dsc
->u
.block
.before
? "before" : "after");
6973 while (regno
<= ARM_PC_REGNUM
&& (regmask
& (1 << regno
)) == 0)
6976 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
6979 xfer_addr
+= bump_before
;
6981 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
6982 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
6984 xfer_addr
+= bump_after
;
6986 regmask
&= ~(1 << regno
);
6989 if (dsc
->u
.block
.writeback
)
6990 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
6994 /* Clean up an STM which included the PC in the register list. */
6997 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6998 struct displaced_step_closure
*dsc
)
7000 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
7001 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
7002 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
7003 CORE_ADDR stm_insn_addr
;
7006 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7008 /* If condition code fails, there's nothing else to do. */
7009 if (!store_executed
)
7012 if (dsc
->u
.block
.increment
)
7014 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
7016 if (dsc
->u
.block
.before
)
7021 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
7023 if (dsc
->u
.block
.before
)
7027 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
7028 stm_insn_addr
= dsc
->scratch_base
;
7029 offset
= pc_val
- stm_insn_addr
;
7031 if (debug_displaced
)
7032 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
7033 "STM instruction\n", offset
);
7035 /* Rewrite the stored PC to the proper value for the non-displaced original
7037 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
7038 dsc
->insn_addr
+ offset
);
7041 /* Clean up an LDM which includes the PC in the register list. We clumped all
7042 the registers in the transferred list into a contiguous range r0...rX (to
7043 avoid loading PC directly and losing control of the debugged program), so we
7044 must undo that here. */
7047 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
7048 struct regcache
*regs
,
7049 struct displaced_step_closure
*dsc
)
7051 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
7052 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
);
7053 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= ARM_PC_REGNUM
;
7054 unsigned int regs_loaded
= bitcount (mask
);
7055 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
7057 /* The method employed here will fail if the register list is fully populated
7058 (we need to avoid loading PC directly). */
7059 gdb_assert (num_to_shuffle
< 16);
7064 clobbered
= (1 << num_to_shuffle
) - 1;
7066 while (num_to_shuffle
> 0)
7068 if ((mask
& (1 << write_reg
)) != 0)
7070 unsigned int read_reg
= num_to_shuffle
- 1;
7072 if (read_reg
!= write_reg
)
7074 ULONGEST rval
= displaced_read_reg (regs
, dsc
, read_reg
);
7075 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
7076 if (debug_displaced
)
7077 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
7078 "loaded register r%d to r%d\n"), read_reg
,
7081 else if (debug_displaced
)
7082 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
7083 "r%d already in the right place\n"),
7086 clobbered
&= ~(1 << write_reg
);
7094 /* Restore any registers we scribbled over. */
7095 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
7097 if ((clobbered
& (1 << write_reg
)) != 0)
7099 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
7101 if (debug_displaced
)
7102 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
7103 "clobbered register r%d\n"), write_reg
);
7104 clobbered
&= ~(1 << write_reg
);
7108 /* Perform register writeback manually. */
7109 if (dsc
->u
.block
.writeback
)
7111 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
7113 if (dsc
->u
.block
.increment
)
7114 new_rn_val
+= regs_loaded
* 4;
7116 new_rn_val
-= regs_loaded
* 4;
7118 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
7123 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
7124 in user-level code (in particular exception return, ldm rn, {...pc}^). */
7127 arm_copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
,
7128 struct regcache
*regs
,
7129 struct displaced_step_closure
*dsc
)
7131 int load
= bit (insn
, 20);
7132 int user
= bit (insn
, 22);
7133 int increment
= bit (insn
, 23);
7134 int before
= bit (insn
, 24);
7135 int writeback
= bit (insn
, 21);
7136 int rn
= bits (insn
, 16, 19);
7138 /* Block transfers which don't mention PC can be run directly
7140 if (rn
!= ARM_PC_REGNUM
&& (insn
& 0x8000) == 0)
7141 return arm_copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
7143 if (rn
== ARM_PC_REGNUM
)
7145 warning (_("displaced: Unpredictable LDM or STM with "
7146 "base register r15"));
7147 return arm_copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
7150 if (debug_displaced
)
7151 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
7152 "%.8lx\n", (unsigned long) insn
);
7154 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
7155 dsc
->u
.block
.rn
= rn
;
7157 dsc
->u
.block
.load
= load
;
7158 dsc
->u
.block
.user
= user
;
7159 dsc
->u
.block
.increment
= increment
;
7160 dsc
->u
.block
.before
= before
;
7161 dsc
->u
.block
.writeback
= writeback
;
7162 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
7164 dsc
->u
.block
.regmask
= insn
& 0xffff;
7168 if ((insn
& 0xffff) == 0xffff)
7170 /* LDM with a fully-populated register list. This case is
7171 particularly tricky. Implement for now by fully emulating the
7172 instruction (which might not behave perfectly in all cases, but
7173 these instructions should be rare enough for that not to matter
7175 dsc
->modinsn
[0] = ARM_NOP
;
7177 dsc
->cleanup
= &cleanup_block_load_all
;
7181 /* LDM of a list of registers which includes PC. Implement by
7182 rewriting the list of registers to be transferred into a
7183 contiguous chunk r0...rX before doing the transfer, then shuffling
7184 registers into the correct places in the cleanup routine. */
7185 unsigned int regmask
= insn
& 0xffff;
7186 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
7187 unsigned int to
= 0, from
= 0, i
, new_rn
;
7189 for (i
= 0; i
< num_in_list
; i
++)
7190 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7192 /* Writeback makes things complicated. We need to avoid clobbering
7193 the base register with one of the registers in our modified
7194 register list, but just using a different register can't work in
7197 ldm r14!, {r0-r13,pc}
7199 which would need to be rewritten as:
7203 but that can't work, because there's no free register for N.
7205 Solve this by turning off the writeback bit, and emulating
7206 writeback manually in the cleanup routine. */
7211 new_regmask
= (1 << num_in_list
) - 1;
7213 if (debug_displaced
)
7214 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
7215 "{..., pc}: original reg list %.4x, modified "
7216 "list %.4x\n"), rn
, writeback
? "!" : "",
7217 (int) insn
& 0xffff, new_regmask
);
7219 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
7221 dsc
->cleanup
= &cleanup_block_load_pc
;
7226 /* STM of a list of registers which includes PC. Run the instruction
7227 as-is, but out of line: this will store the wrong value for the PC,
7228 so we must manually fix up the memory in the cleanup routine.
7229 Doing things this way has the advantage that we can auto-detect
7230 the offset of the PC write (which is architecture-dependent) in
7231 the cleanup routine. */
7232 dsc
->modinsn
[0] = insn
;
7234 dsc
->cleanup
= &cleanup_block_store_pc
;
7241 thumb2_copy_block_xfer (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
7242 struct regcache
*regs
,
7243 struct displaced_step_closure
*dsc
)
7245 int rn
= bits (insn1
, 0, 3);
7246 int load
= bit (insn1
, 4);
7247 int writeback
= bit (insn1
, 5);
7249 /* Block transfers which don't mention PC can be run directly
7251 if (rn
!= ARM_PC_REGNUM
&& (insn2
& 0x8000) == 0)
7252 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ldm/stm", dsc
);
7254 if (rn
== ARM_PC_REGNUM
)
7256 warning (_("displaced: Unpredictable LDM or STM with "
7257 "base register r15"));
7258 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7259 "unpredictable ldm/stm", dsc
);
7262 if (debug_displaced
)
7263 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
7264 "%.4x%.4x\n", insn1
, insn2
);
7266 /* Clear bit 13, since it should be always zero. */
7267 dsc
->u
.block
.regmask
= (insn2
& 0xdfff);
7268 dsc
->u
.block
.rn
= rn
;
7270 dsc
->u
.block
.load
= load
;
7271 dsc
->u
.block
.user
= 0;
7272 dsc
->u
.block
.increment
= bit (insn1
, 7);
7273 dsc
->u
.block
.before
= bit (insn1
, 8);
7274 dsc
->u
.block
.writeback
= writeback
;
7275 dsc
->u
.block
.cond
= INST_AL
;
7276 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
7280 if (dsc
->u
.block
.regmask
== 0xffff)
7282 /* This branch is impossible to happen. */
7287 unsigned int regmask
= dsc
->u
.block
.regmask
;
7288 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
7289 unsigned int to
= 0, from
= 0, i
, new_rn
;
7291 for (i
= 0; i
< num_in_list
; i
++)
7292 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7297 new_regmask
= (1 << num_in_list
) - 1;
7299 if (debug_displaced
)
7300 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
7301 "{..., pc}: original reg list %.4x, modified "
7302 "list %.4x\n"), rn
, writeback
? "!" : "",
7303 (int) dsc
->u
.block
.regmask
, new_regmask
);
7305 dsc
->modinsn
[0] = insn1
;
7306 dsc
->modinsn
[1] = (new_regmask
& 0xffff);
7309 dsc
->cleanup
= &cleanup_block_load_pc
;
7314 dsc
->modinsn
[0] = insn1
;
7315 dsc
->modinsn
[1] = insn2
;
7317 dsc
->cleanup
= &cleanup_block_store_pc
;
7322 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
7323 for Linux, where some SVC instructions must be treated specially. */
7326 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7327 struct displaced_step_closure
*dsc
)
7329 CORE_ADDR resume_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
7331 if (debug_displaced
)
7332 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
7333 "%.8lx\n", (unsigned long) resume_addr
);
7335 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
7339 /* Common copy routine for svc instruciton. */
7342 install_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7343 struct displaced_step_closure
*dsc
)
7345 /* Preparation: none.
7346 Insn: unmodified svc.
7347 Cleanup: pc <- insn_addr + insn_size. */
7349 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
7351 dsc
->wrote_to_pc
= 1;
7353 /* Allow OS-specific code to override SVC handling. */
7354 if (dsc
->u
.svc
.copy_svc_os
)
7355 return dsc
->u
.svc
.copy_svc_os (gdbarch
, regs
, dsc
);
7358 dsc
->cleanup
= &cleanup_svc
;
7364 arm_copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
,
7365 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7368 if (debug_displaced
)
7369 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
7370 (unsigned long) insn
);
7372 dsc
->modinsn
[0] = insn
;
7374 return install_svc (gdbarch
, regs
, dsc
);
7378 thumb_copy_svc (struct gdbarch
*gdbarch
, uint16_t insn
,
7379 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7382 if (debug_displaced
)
7383 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.4x\n",
7386 dsc
->modinsn
[0] = insn
;
7388 return install_svc (gdbarch
, regs
, dsc
);
7391 /* Copy undefined instructions. */
7394 arm_copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
7395 struct displaced_step_closure
*dsc
)
7397 if (debug_displaced
)
7398 fprintf_unfiltered (gdb_stdlog
,
7399 "displaced: copying undefined insn %.8lx\n",
7400 (unsigned long) insn
);
7402 dsc
->modinsn
[0] = insn
;
7408 thumb_32bit_copy_undef (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
7409 struct displaced_step_closure
*dsc
)
7412 if (debug_displaced
)
7413 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn "
7414 "%.4x %.4x\n", (unsigned short) insn1
,
7415 (unsigned short) insn2
);
7417 dsc
->modinsn
[0] = insn1
;
7418 dsc
->modinsn
[1] = insn2
;
7424 /* Copy unpredictable instructions. */
7427 arm_copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
7428 struct displaced_step_closure
*dsc
)
7430 if (debug_displaced
)
7431 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
7432 "%.8lx\n", (unsigned long) insn
);
7434 dsc
->modinsn
[0] = insn
;
7439 /* The decode_* functions are instruction decoding helpers. They mostly follow
7440 the presentation in the ARM ARM. */
7443 arm_decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
7444 struct regcache
*regs
,
7445 struct displaced_step_closure
*dsc
)
7447 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
7448 unsigned int rn
= bits (insn
, 16, 19);
7450 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
7451 return arm_copy_unmodified (gdbarch
, insn
, "cps", dsc
);
7452 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
7453 return arm_copy_unmodified (gdbarch
, insn
, "setend", dsc
);
7454 else if ((op1
& 0x60) == 0x20)
7455 return arm_copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
7456 else if ((op1
& 0x71) == 0x40)
7457 return arm_copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store",
7459 else if ((op1
& 0x77) == 0x41)
7460 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
7461 else if ((op1
& 0x77) == 0x45)
7462 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
7463 else if ((op1
& 0x77) == 0x51)
7466 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
7468 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7470 else if ((op1
& 0x77) == 0x55)
7471 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
7472 else if (op1
== 0x57)
7475 case 0x1: return arm_copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
7476 case 0x4: return arm_copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
7477 case 0x5: return arm_copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
7478 case 0x6: return arm_copy_unmodified (gdbarch
, insn
, "isb", dsc
);
7479 default: return arm_copy_unpred (gdbarch
, insn
, dsc
);
7481 else if ((op1
& 0x63) == 0x43)
7482 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7483 else if ((op2
& 0x1) == 0x0)
7484 switch (op1
& ~0x80)
7487 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
7489 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
7490 case 0x71: case 0x75:
7492 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
7493 case 0x63: case 0x67: case 0x73: case 0x77:
7494 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7496 return arm_copy_undef (gdbarch
, insn
, dsc
);
7499 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
7503 arm_decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
7504 struct regcache
*regs
,
7505 struct displaced_step_closure
*dsc
)
7507 if (bit (insn
, 27) == 0)
7508 return arm_decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
7509 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
7510 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
7513 return arm_copy_unmodified (gdbarch
, insn
, "srs", dsc
);
7516 return arm_copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
7518 case 0x4: case 0x5: case 0x6: case 0x7:
7519 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
7522 switch ((insn
& 0xe00000) >> 21)
7524 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
7526 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7529 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
7532 return arm_copy_undef (gdbarch
, insn
, dsc
);
7537 int rn_f
= (bits (insn
, 16, 19) == 0xf);
7538 switch ((insn
& 0xe00000) >> 21)
7541 /* ldc/ldc2 imm (undefined for rn == pc). */
7542 return rn_f
? arm_copy_undef (gdbarch
, insn
, dsc
)
7543 : arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7546 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
7548 case 0x4: case 0x5: case 0x6: case 0x7:
7549 /* ldc/ldc2 lit (undefined for rn != pc). */
7550 return rn_f
? arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
7551 : arm_copy_undef (gdbarch
, insn
, dsc
);
7554 return arm_copy_undef (gdbarch
, insn
, dsc
);
7559 return arm_copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
7562 if (bits (insn
, 16, 19) == 0xf)
7564 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7566 return arm_copy_undef (gdbarch
, insn
, dsc
);
7570 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
7572 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7576 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
7578 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7581 return arm_copy_undef (gdbarch
, insn
, dsc
);
7585 /* Decode miscellaneous instructions in dp/misc encoding space. */
7588 arm_decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
7589 struct regcache
*regs
,
7590 struct displaced_step_closure
*dsc
)
7592 unsigned int op2
= bits (insn
, 4, 6);
7593 unsigned int op
= bits (insn
, 21, 22);
7594 unsigned int op1
= bits (insn
, 16, 19);
7599 return arm_copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
7602 if (op
== 0x1) /* bx. */
7603 return arm_copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
7605 return arm_copy_unmodified (gdbarch
, insn
, "clz", dsc
);
7607 return arm_copy_undef (gdbarch
, insn
, dsc
);
7611 /* Not really supported. */
7612 return arm_copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
7614 return arm_copy_undef (gdbarch
, insn
, dsc
);
7618 return arm_copy_bx_blx_reg (gdbarch
, insn
,
7619 regs
, dsc
); /* blx register. */
7621 return arm_copy_undef (gdbarch
, insn
, dsc
);
7624 return arm_copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
7628 return arm_copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
7630 /* Not really supported. */
7631 return arm_copy_unmodified (gdbarch
, insn
, "smc", dsc
);
7634 return arm_copy_undef (gdbarch
, insn
, dsc
);
7639 arm_decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
,
7640 struct regcache
*regs
,
7641 struct displaced_step_closure
*dsc
)
7644 switch (bits (insn
, 20, 24))
7647 return arm_copy_unmodified (gdbarch
, insn
, "movw", dsc
);
7650 return arm_copy_unmodified (gdbarch
, insn
, "movt", dsc
);
7652 case 0x12: case 0x16:
7653 return arm_copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
7656 return arm_copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
7660 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
7662 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
7663 return arm_copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
7664 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
7665 return arm_copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
7666 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
7667 return arm_decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
7668 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
7669 return arm_copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
7670 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
7671 return arm_copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
7672 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
7673 return arm_copy_unmodified (gdbarch
, insn
, "synch", dsc
);
7674 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
7675 /* 2nd arg means "unpriveleged". */
7676 return arm_copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
7680 /* Should be unreachable. */
7685 arm_decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
7686 struct regcache
*regs
,
7687 struct displaced_step_closure
*dsc
)
7689 int a
= bit (insn
, 25), b
= bit (insn
, 4);
7690 uint32_t op1
= bits (insn
, 20, 24);
7691 int rn_f
= bits (insn
, 16, 19) == 0xf;
7693 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
7694 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
7695 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 0);
7696 else if ((!a
&& (op1
& 0x17) == 0x02)
7697 || (a
&& (op1
& 0x17) == 0x02 && !b
))
7698 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 1);
7699 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
7700 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
7701 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 0);
7702 else if ((!a
&& (op1
& 0x17) == 0x03)
7703 || (a
&& (op1
& 0x17) == 0x03 && !b
))
7704 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 1);
7705 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
7706 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
7707 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
7708 else if ((!a
&& (op1
& 0x17) == 0x06)
7709 || (a
&& (op1
& 0x17) == 0x06 && !b
))
7710 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
7711 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
7712 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
7713 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
7714 else if ((!a
&& (op1
& 0x17) == 0x07)
7715 || (a
&& (op1
& 0x17) == 0x07 && !b
))
7716 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
7718 /* Should be unreachable. */
7723 arm_decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
7724 struct displaced_step_closure
*dsc
)
7726 switch (bits (insn
, 20, 24))
7728 case 0x00: case 0x01: case 0x02: case 0x03:
7729 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
7731 case 0x04: case 0x05: case 0x06: case 0x07:
7732 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
7734 case 0x08: case 0x09: case 0x0a: case 0x0b:
7735 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
7736 return arm_copy_unmodified (gdbarch
, insn
,
7737 "decode/pack/unpack/saturate/reverse", dsc
);
7740 if (bits (insn
, 5, 7) == 0) /* op2. */
7742 if (bits (insn
, 12, 15) == 0xf)
7743 return arm_copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
7745 return arm_copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
7748 return arm_copy_undef (gdbarch
, insn
, dsc
);
7750 case 0x1a: case 0x1b:
7751 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
7752 return arm_copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
7754 return arm_copy_undef (gdbarch
, insn
, dsc
);
7756 case 0x1c: case 0x1d:
7757 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
7759 if (bits (insn
, 0, 3) == 0xf)
7760 return arm_copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
7762 return arm_copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
7765 return arm_copy_undef (gdbarch
, insn
, dsc
);
7767 case 0x1e: case 0x1f:
7768 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
7769 return arm_copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
7771 return arm_copy_undef (gdbarch
, insn
, dsc
);
7774 /* Should be unreachable. */
7779 arm_decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, int32_t insn
,
7780 struct regcache
*regs
,
7781 struct displaced_step_closure
*dsc
)
7784 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
7786 return arm_copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
7790 arm_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
7791 struct regcache
*regs
,
7792 struct displaced_step_closure
*dsc
)
7794 unsigned int opcode
= bits (insn
, 20, 24);
7798 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
7799 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
7801 case 0x08: case 0x0a: case 0x0c: case 0x0e:
7802 case 0x12: case 0x16:
7803 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
7805 case 0x09: case 0x0b: case 0x0d: case 0x0f:
7806 case 0x13: case 0x17:
7807 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
7809 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7810 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7811 /* Note: no writeback for these instructions. Bit 25 will always be
7812 zero though (via caller), so the following works OK. */
7813 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7816 /* Should be unreachable. */
7820 /* Decode shifted register instructions. */
7823 thumb2_decode_dp_shift_reg (struct gdbarch
*gdbarch
, uint16_t insn1
,
7824 uint16_t insn2
, struct regcache
*regs
,
7825 struct displaced_step_closure
*dsc
)
7827 /* PC is only allowed to be used in instruction MOV. */
7829 unsigned int op
= bits (insn1
, 5, 8);
7830 unsigned int rn
= bits (insn1
, 0, 3);
7832 if (op
== 0x2 && rn
== 0xf) /* MOV */
7833 return thumb2_copy_alu_imm (gdbarch
, insn1
, insn2
, regs
, dsc
);
7835 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7836 "dp (shift reg)", dsc
);
7840 /* Decode extension register load/store. Exactly the same as
7841 arm_decode_ext_reg_ld_st. */
7844 thumb2_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint16_t insn1
,
7845 uint16_t insn2
, struct regcache
*regs
,
7846 struct displaced_step_closure
*dsc
)
7848 unsigned int opcode
= bits (insn1
, 4, 8);
7852 case 0x04: case 0x05:
7853 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7854 "vfp/neon vmov", dsc
);
7856 case 0x08: case 0x0c: /* 01x00 */
7857 case 0x0a: case 0x0e: /* 01x10 */
7858 case 0x12: case 0x16: /* 10x10 */
7859 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7860 "vfp/neon vstm/vpush", dsc
);
7862 case 0x09: case 0x0d: /* 01x01 */
7863 case 0x0b: case 0x0f: /* 01x11 */
7864 case 0x13: case 0x17: /* 10x11 */
7865 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7866 "vfp/neon vldm/vpop", dsc
);
7868 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7869 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7871 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7872 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
, regs
, dsc
);
7875 /* Should be unreachable. */
7880 arm_decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
7881 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7883 unsigned int op1
= bits (insn
, 20, 25);
7884 int op
= bit (insn
, 4);
7885 unsigned int coproc
= bits (insn
, 8, 11);
7886 unsigned int rn
= bits (insn
, 16, 19);
7888 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
7889 return arm_decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
7890 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
7891 && (coproc
& 0xe) != 0xa)
7893 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7894 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
7895 && (coproc
& 0xe) != 0xa)
7896 /* ldc/ldc2 imm/lit. */
7897 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7898 else if ((op1
& 0x3e) == 0x00)
7899 return arm_copy_undef (gdbarch
, insn
, dsc
);
7900 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
7901 return arm_copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
7902 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
7903 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
7904 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
7905 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
7906 else if ((op1
& 0x30) == 0x20 && !op
)
7908 if ((coproc
& 0xe) == 0xa)
7909 return arm_copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
7911 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7913 else if ((op1
& 0x30) == 0x20 && op
)
7914 return arm_copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
7915 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
7916 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
7917 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
7918 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
7919 else if ((op1
& 0x30) == 0x30)
7920 return arm_copy_svc (gdbarch
, insn
, regs
, dsc
);
7922 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
7926 thumb2_decode_svc_copro (struct gdbarch
*gdbarch
, uint16_t insn1
,
7927 uint16_t insn2
, struct regcache
*regs
,
7928 struct displaced_step_closure
*dsc
)
7930 unsigned int coproc
= bits (insn2
, 8, 11);
7931 unsigned int op1
= bits (insn1
, 4, 9);
7932 unsigned int bit_5_8
= bits (insn1
, 5, 8);
7933 unsigned int bit_9
= bit (insn1
, 9);
7934 unsigned int bit_4
= bit (insn1
, 4);
7935 unsigned int rn
= bits (insn1
, 0, 3);
7940 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7941 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
7943 else if (bit_5_8
== 0) /* UNDEFINED. */
7944 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
7947 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
7948 if ((coproc
& 0xe) == 0xa)
7949 return thumb2_decode_ext_reg_ld_st (gdbarch
, insn1
, insn2
, regs
,
7951 else /* coproc is not 101x. */
7953 if (bit_4
== 0) /* STC/STC2. */
7954 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7956 else /* LDC/LDC2 {literal, immeidate}. */
7957 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
,
7963 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "coproc", dsc
);
7969 install_pc_relative (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7970 struct displaced_step_closure
*dsc
, int rd
)
7976 Preparation: Rd <- PC
7982 int val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
7983 displaced_write_reg (regs
, dsc
, rd
, val
, CANNOT_WRITE_PC
);
7987 thumb_copy_pc_relative_16bit (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7988 struct displaced_step_closure
*dsc
,
7989 int rd
, unsigned int imm
)
7992 /* Encoding T2: ADDS Rd, #imm */
7993 dsc
->modinsn
[0] = (0x3000 | (rd
<< 8) | imm
);
7995 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
8001 thumb_decode_pc_relative_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
8002 struct regcache
*regs
,
8003 struct displaced_step_closure
*dsc
)
8005 unsigned int rd
= bits (insn
, 8, 10);
8006 unsigned int imm8
= bits (insn
, 0, 7);
8008 if (debug_displaced
)
8009 fprintf_unfiltered (gdb_stdlog
,
8010 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
8013 return thumb_copy_pc_relative_16bit (gdbarch
, regs
, dsc
, rd
, imm8
);
8017 thumb_copy_pc_relative_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
8018 uint16_t insn2
, struct regcache
*regs
,
8019 struct displaced_step_closure
*dsc
)
8021 unsigned int rd
= bits (insn2
, 8, 11);
8022 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
8023 extract raw immediate encoding rather than computing immediate. When
8024 generating ADD or SUB instruction, we can simply perform OR operation to
8025 set immediate into ADD. */
8026 unsigned int imm_3_8
= insn2
& 0x70ff;
8027 unsigned int imm_i
= insn1
& 0x0400; /* Clear all bits except bit 10. */
8029 if (debug_displaced
)
8030 fprintf_unfiltered (gdb_stdlog
,
8031 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
8032 rd
, imm_i
, imm_3_8
, insn1
, insn2
);
8034 if (bit (insn1
, 7)) /* Encoding T2 */
8036 /* Encoding T3: SUB Rd, Rd, #imm */
8037 dsc
->modinsn
[0] = (0xf1a0 | rd
| imm_i
);
8038 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
8040 else /* Encoding T3 */
8042 /* Encoding T3: ADD Rd, Rd, #imm */
8043 dsc
->modinsn
[0] = (0xf100 | rd
| imm_i
);
8044 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
8048 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
8054 thumb_copy_16bit_ldr_literal (struct gdbarch
*gdbarch
, unsigned short insn1
,
8055 struct regcache
*regs
,
8056 struct displaced_step_closure
*dsc
)
8058 unsigned int rt
= bits (insn1
, 8, 10);
8060 int imm8
= (bits (insn1
, 0, 7) << 2);
8061 CORE_ADDR from
= dsc
->insn_addr
;
8067 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
8069 Insn: LDR R0, [R2, R3];
8070 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
8072 if (debug_displaced
)
8073 fprintf_unfiltered (gdb_stdlog
,
8074 "displaced: copying thumb ldr r%d [pc #%d]\n"
8077 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
8078 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
8079 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
8080 pc
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
8081 /* The assembler calculates the required value of the offset from the
8082 Align(PC,4) value of this instruction to the label. */
8083 pc
= pc
& 0xfffffffc;
8085 displaced_write_reg (regs
, dsc
, 2, pc
, CANNOT_WRITE_PC
);
8086 displaced_write_reg (regs
, dsc
, 3, imm8
, CANNOT_WRITE_PC
);
8089 dsc
->u
.ldst
.xfersize
= 4;
8091 dsc
->u
.ldst
.immed
= 0;
8092 dsc
->u
.ldst
.writeback
= 0;
8093 dsc
->u
.ldst
.restore_r4
= 0;
8095 dsc
->modinsn
[0] = 0x58d0; /* ldr r0, [r2, r3]*/
8097 dsc
->cleanup
= &cleanup_load
;
8102 /* Copy Thumb cbnz/cbz insruction. */
8105 thumb_copy_cbnz_cbz (struct gdbarch
*gdbarch
, uint16_t insn1
,
8106 struct regcache
*regs
,
8107 struct displaced_step_closure
*dsc
)
8109 int non_zero
= bit (insn1
, 11);
8110 unsigned int imm5
= (bit (insn1
, 9) << 6) | (bits (insn1
, 3, 7) << 1);
8111 CORE_ADDR from
= dsc
->insn_addr
;
8112 int rn
= bits (insn1
, 0, 2);
8113 int rn_val
= displaced_read_reg (regs
, dsc
, rn
);
8115 dsc
->u
.branch
.cond
= (rn_val
&& non_zero
) || (!rn_val
&& !non_zero
);
8116 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
8117 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
8118 condition is false, let it be, cleanup_branch will do nothing. */
8119 if (dsc
->u
.branch
.cond
)
8121 dsc
->u
.branch
.cond
= INST_AL
;
8122 dsc
->u
.branch
.dest
= from
+ 4 + imm5
;
8125 dsc
->u
.branch
.dest
= from
+ 2;
8127 dsc
->u
.branch
.link
= 0;
8128 dsc
->u
.branch
.exchange
= 0;
8130 if (debug_displaced
)
8131 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s [r%d = 0x%x]"
8132 " insn %.4x to %.8lx\n", non_zero
? "cbnz" : "cbz",
8133 rn
, rn_val
, insn1
, dsc
->u
.branch
.dest
);
8135 dsc
->modinsn
[0] = THUMB_NOP
;
8137 dsc
->cleanup
= &cleanup_branch
;
8141 /* Copy Table Branch Byte/Halfword */
8143 thumb2_copy_table_branch (struct gdbarch
*gdbarch
, uint16_t insn1
,
8144 uint16_t insn2
, struct regcache
*regs
,
8145 struct displaced_step_closure
*dsc
)
8147 ULONGEST rn_val
, rm_val
;
8148 int is_tbh
= bit (insn2
, 4);
8149 CORE_ADDR halfwords
= 0;
8150 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8152 rn_val
= displaced_read_reg (regs
, dsc
, bits (insn1
, 0, 3));
8153 rm_val
= displaced_read_reg (regs
, dsc
, bits (insn2
, 0, 3));
8159 target_read_memory (rn_val
+ 2 * rm_val
, buf
, 2);
8160 halfwords
= extract_unsigned_integer (buf
, 2, byte_order
);
8166 target_read_memory (rn_val
+ rm_val
, buf
, 1);
8167 halfwords
= extract_unsigned_integer (buf
, 1, byte_order
);
8170 if (debug_displaced
)
8171 fprintf_unfiltered (gdb_stdlog
, "displaced: %s base 0x%x offset 0x%x"
8172 " offset 0x%x\n", is_tbh
? "tbh" : "tbb",
8173 (unsigned int) rn_val
, (unsigned int) rm_val
,
8174 (unsigned int) halfwords
);
8176 dsc
->u
.branch
.cond
= INST_AL
;
8177 dsc
->u
.branch
.link
= 0;
8178 dsc
->u
.branch
.exchange
= 0;
8179 dsc
->u
.branch
.dest
= dsc
->insn_addr
+ 4 + 2 * halfwords
;
8181 dsc
->cleanup
= &cleanup_branch
;
8187 cleanup_pop_pc_16bit_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
8188 struct displaced_step_closure
*dsc
)
8191 int val
= displaced_read_reg (regs
, dsc
, 7);
8192 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, val
, BX_WRITE_PC
);
8195 val
= displaced_read_reg (regs
, dsc
, 8);
8196 displaced_write_reg (regs
, dsc
, 7, val
, CANNOT_WRITE_PC
);
8199 displaced_write_reg (regs
, dsc
, 8, dsc
->tmp
[0], CANNOT_WRITE_PC
);
8204 thumb_copy_pop_pc_16bit (struct gdbarch
*gdbarch
, unsigned short insn1
,
8205 struct regcache
*regs
,
8206 struct displaced_step_closure
*dsc
)
8208 dsc
->u
.block
.regmask
= insn1
& 0x00ff;
8210 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
8213 (1) register list is full, that is, r0-r7 are used.
8214 Prepare: tmp[0] <- r8
8216 POP {r0, r1, ...., r6, r7}; remove PC from reglist
8217 MOV r8, r7; Move value of r7 to r8;
8218 POP {r7}; Store PC value into r7.
8220 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
8222 (2) register list is not full, supposing there are N registers in
8223 register list (except PC, 0 <= N <= 7).
8224 Prepare: for each i, 0 - N, tmp[i] <- ri.
8226 POP {r0, r1, ...., rN};
8228 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
8229 from tmp[] properly.
8231 if (debug_displaced
)
8232 fprintf_unfiltered (gdb_stdlog
,
8233 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
8234 dsc
->u
.block
.regmask
, insn1
);
8236 if (dsc
->u
.block
.regmask
== 0xff)
8238 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 8);
8240 dsc
->modinsn
[0] = (insn1
& 0xfeff); /* POP {r0,r1,...,r6, r7} */
8241 dsc
->modinsn
[1] = 0x46b8; /* MOV r8, r7 */
8242 dsc
->modinsn
[2] = 0xbc80; /* POP {r7} */
8245 dsc
->cleanup
= &cleanup_pop_pc_16bit_all
;
8249 unsigned int num_in_list
= bitcount (dsc
->u
.block
.regmask
);
8250 unsigned int new_regmask
, bit
= 1;
8251 unsigned int to
= 0, from
= 0, i
, new_rn
;
8253 for (i
= 0; i
< num_in_list
+ 1; i
++)
8254 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
8256 new_regmask
= (1 << (num_in_list
+ 1)) - 1;
8258 if (debug_displaced
)
8259 fprintf_unfiltered (gdb_stdlog
, _("displaced: POP "
8260 "{..., pc}: original reg list %.4x,"
8261 " modified list %.4x\n"),
8262 (int) dsc
->u
.block
.regmask
, new_regmask
);
8264 dsc
->u
.block
.regmask
|= 0x8000;
8265 dsc
->u
.block
.writeback
= 0;
8266 dsc
->u
.block
.cond
= INST_AL
;
8268 dsc
->modinsn
[0] = (insn1
& ~0x1ff) | (new_regmask
& 0xff);
8270 dsc
->cleanup
= &cleanup_block_load_pc
;
8277 thumb_process_displaced_16bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
8278 struct regcache
*regs
,
8279 struct displaced_step_closure
*dsc
)
8281 unsigned short op_bit_12_15
= bits (insn1
, 12, 15);
8282 unsigned short op_bit_10_11
= bits (insn1
, 10, 11);
8285 /* 16-bit thumb instructions. */
8286 switch (op_bit_12_15
)
8288 /* Shift (imme), add, subtract, move and compare. */
8289 case 0: case 1: case 2: case 3:
8290 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
8291 "shift/add/sub/mov/cmp",
8295 switch (op_bit_10_11
)
8297 case 0: /* Data-processing */
8298 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
8302 case 1: /* Special data instructions and branch and exchange. */
8304 unsigned short op
= bits (insn1
, 7, 9);
8305 if (op
== 6 || op
== 7) /* BX or BLX */
8306 err
= thumb_copy_bx_blx_reg (gdbarch
, insn1
, regs
, dsc
);
8307 else if (bits (insn1
, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
8308 err
= thumb_copy_alu_reg (gdbarch
, insn1
, regs
, dsc
);
8310 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "special data",
8314 default: /* LDR (literal) */
8315 err
= thumb_copy_16bit_ldr_literal (gdbarch
, insn1
, regs
, dsc
);
8318 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
8319 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldr/str", dsc
);
8322 if (op_bit_10_11
< 2) /* Generate PC-relative address */
8323 err
= thumb_decode_pc_relative_16bit (gdbarch
, insn1
, regs
, dsc
);
8324 else /* Generate SP-relative address */
8325 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "sp-relative", dsc
);
8327 case 11: /* Misc 16-bit instructions */
8329 switch (bits (insn1
, 8, 11))
8331 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
8332 err
= thumb_copy_cbnz_cbz (gdbarch
, insn1
, regs
, dsc
);
8334 case 12: case 13: /* POP */
8335 if (bit (insn1
, 8)) /* PC is in register list. */
8336 err
= thumb_copy_pop_pc_16bit (gdbarch
, insn1
, regs
, dsc
);
8338 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "pop", dsc
);
8340 case 15: /* If-Then, and hints */
8341 if (bits (insn1
, 0, 3))
8342 /* If-Then makes up to four following instructions conditional.
8343 IT instruction itself is not conditional, so handle it as a
8344 common unmodified instruction. */
8345 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "If-Then",
8348 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "hints", dsc
);
8351 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "misc", dsc
);
8356 if (op_bit_10_11
< 2) /* Store multiple registers */
8357 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "stm", dsc
);
8358 else /* Load multiple registers */
8359 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldm", dsc
);
8361 case 13: /* Conditional branch and supervisor call */
8362 if (bits (insn1
, 9, 11) != 7) /* conditional branch */
8363 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
8365 err
= thumb_copy_svc (gdbarch
, insn1
, regs
, dsc
);
8367 case 14: /* Unconditional branch */
8368 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
8375 internal_error (__FILE__
, __LINE__
,
8376 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
8380 decode_thumb_32bit_ld_mem_hints (struct gdbarch
*gdbarch
,
8381 uint16_t insn1
, uint16_t insn2
,
8382 struct regcache
*regs
,
8383 struct displaced_step_closure
*dsc
)
8385 int rt
= bits (insn2
, 12, 15);
8386 int rn
= bits (insn1
, 0, 3);
8387 int op1
= bits (insn1
, 7, 8);
8390 switch (bits (insn1
, 5, 6))
8392 case 0: /* Load byte and memory hints */
8393 if (rt
== 0xf) /* PLD/PLI */
8396 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
8397 return thumb2_copy_preload (gdbarch
, insn1
, insn2
, regs
, dsc
);
8399 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8404 if (rn
== 0xf) /* LDRB/LDRSB (literal) */
8405 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
8408 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8409 "ldrb{reg, immediate}/ldrbt",
8414 case 1: /* Load halfword and memory hints. */
8415 if (rt
== 0xf) /* PLD{W} and Unalloc memory hint. */
8416 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8417 "pld/unalloc memhint", dsc
);
8421 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
8424 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8428 case 2: /* Load word */
8430 int insn2_bit_8_11
= bits (insn2
, 8, 11);
8433 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
, 4);
8434 else if (op1
== 0x1) /* Encoding T3 */
8435 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
, dsc
,
8437 else /* op1 == 0x0 */
8439 if (insn2_bit_8_11
== 0xc || (insn2_bit_8_11
& 0x9) == 0x9)
8440 /* LDR (immediate) */
8441 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
8442 dsc
, bit (insn2
, 8), 1);
8443 else if (insn2_bit_8_11
== 0xe) /* LDRT */
8444 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8447 /* LDR (register) */
8448 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
8454 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
8461 thumb_process_displaced_32bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
8462 uint16_t insn2
, struct regcache
*regs
,
8463 struct displaced_step_closure
*dsc
)
8466 unsigned short op
= bit (insn2
, 15);
8467 unsigned int op1
= bits (insn1
, 11, 12);
8473 switch (bits (insn1
, 9, 10))
8478 /* Load/store {dual, execlusive}, table branch. */
8479 if (bits (insn1
, 7, 8) == 1 && bits (insn1
, 4, 5) == 1
8480 && bits (insn2
, 5, 7) == 0)
8481 err
= thumb2_copy_table_branch (gdbarch
, insn1
, insn2
, regs
,
8484 /* PC is not allowed to use in load/store {dual, exclusive}
8486 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8487 "load/store dual/ex", dsc
);
8489 else /* load/store multiple */
8491 switch (bits (insn1
, 7, 8))
8493 case 0: case 3: /* SRS, RFE */
8494 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8497 case 1: case 2: /* LDM/STM/PUSH/POP */
8498 err
= thumb2_copy_block_xfer (gdbarch
, insn1
, insn2
, regs
, dsc
);
8505 /* Data-processing (shift register). */
8506 err
= thumb2_decode_dp_shift_reg (gdbarch
, insn1
, insn2
, regs
,
8509 default: /* Coprocessor instructions. */
8510 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
8515 case 2: /* op1 = 2 */
8516 if (op
) /* Branch and misc control. */
8518 if (bit (insn2
, 14) /* BLX/BL */
8519 || bit (insn2
, 12) /* Unconditional branch */
8520 || (bits (insn1
, 7, 9) != 0x7)) /* Conditional branch */
8521 err
= thumb2_copy_b_bl_blx (gdbarch
, insn1
, insn2
, regs
, dsc
);
8523 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8528 if (bit (insn1
, 9)) /* Data processing (plain binary imm). */
8530 int op
= bits (insn1
, 4, 8);
8531 int rn
= bits (insn1
, 0, 3);
8532 if ((op
== 0 || op
== 0xa) && rn
== 0xf)
8533 err
= thumb_copy_pc_relative_32bit (gdbarch
, insn1
, insn2
,
8536 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8539 else /* Data processing (modified immeidate) */
8540 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8544 case 3: /* op1 = 3 */
8545 switch (bits (insn1
, 9, 10))
8549 err
= decode_thumb_32bit_ld_mem_hints (gdbarch
, insn1
, insn2
,
8551 else /* NEON Load/Store and Store single data item */
8552 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8553 "neon elt/struct load/store",
8556 case 1: /* op1 = 3, bits (9, 10) == 1 */
8557 switch (bits (insn1
, 7, 8))
8559 case 0: case 1: /* Data processing (register) */
8560 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8563 case 2: /* Multiply and absolute difference */
8564 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8565 "mul/mua/diff", dsc
);
8567 case 3: /* Long multiply and divide */
8568 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8573 default: /* Coprocessor instructions */
8574 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
8583 internal_error (__FILE__
, __LINE__
,
8584 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
8589 thumb_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8590 CORE_ADDR to
, struct regcache
*regs
,
8591 struct displaced_step_closure
*dsc
)
8593 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8595 = read_memory_unsigned_integer (from
, 2, byte_order_for_code
);
8597 if (debug_displaced
)
8598 fprintf_unfiltered (gdb_stdlog
, "displaced: process thumb insn %.4x "
8599 "at %.8lx\n", insn1
, (unsigned long) from
);
8602 dsc
->insn_size
= thumb_insn_size (insn1
);
8603 if (thumb_insn_size (insn1
) == 4)
8606 = read_memory_unsigned_integer (from
+ 2, 2, byte_order_for_code
);
8607 thumb_process_displaced_32bit_insn (gdbarch
, insn1
, insn2
, regs
, dsc
);
8610 thumb_process_displaced_16bit_insn (gdbarch
, insn1
, regs
, dsc
);
8614 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8615 CORE_ADDR to
, struct regcache
*regs
,
8616 struct displaced_step_closure
*dsc
)
8619 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8622 /* Most displaced instructions use a 1-instruction scratch space, so set this
8623 here and override below if/when necessary. */
8625 dsc
->insn_addr
= from
;
8626 dsc
->scratch_base
= to
;
8627 dsc
->cleanup
= NULL
;
8628 dsc
->wrote_to_pc
= 0;
8630 if (!displaced_in_arm_mode (regs
))
8631 return thumb_process_displaced_insn (gdbarch
, from
, to
, regs
, dsc
);
8635 insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
8636 if (debug_displaced
)
8637 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
8638 "at %.8lx\n", (unsigned long) insn
,
8639 (unsigned long) from
);
8641 if ((insn
& 0xf0000000) == 0xf0000000)
8642 err
= arm_decode_unconditional (gdbarch
, insn
, regs
, dsc
);
8643 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
8645 case 0x0: case 0x1: case 0x2: case 0x3:
8646 err
= arm_decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
8649 case 0x4: case 0x5: case 0x6:
8650 err
= arm_decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
8654 err
= arm_decode_media (gdbarch
, insn
, dsc
);
8657 case 0x8: case 0x9: case 0xa: case 0xb:
8658 err
= arm_decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
8661 case 0xc: case 0xd: case 0xe: case 0xf:
8662 err
= arm_decode_svc_copro (gdbarch
, insn
, to
, regs
, dsc
);
8667 internal_error (__FILE__
, __LINE__
,
8668 _("arm_process_displaced_insn: Instruction decode error"));
8671 /* Actually set up the scratch space for a displaced instruction. */
8674 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8675 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
8677 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8678 unsigned int i
, len
, offset
;
8679 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8680 int size
= dsc
->is_thumb
? 2 : 4;
8681 const gdb_byte
*bkp_insn
;
8684 /* Poke modified instruction(s). */
8685 for (i
= 0; i
< dsc
->numinsns
; i
++)
8687 if (debug_displaced
)
8689 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn ");
8691 fprintf_unfiltered (gdb_stdlog
, "%.8lx",
8694 fprintf_unfiltered (gdb_stdlog
, "%.4x",
8695 (unsigned short)dsc
->modinsn
[i
]);
8697 fprintf_unfiltered (gdb_stdlog
, " at %.8lx\n",
8698 (unsigned long) to
+ offset
);
8701 write_memory_unsigned_integer (to
+ offset
, size
,
8702 byte_order_for_code
,
8707 /* Choose the correct breakpoint instruction. */
8710 bkp_insn
= tdep
->thumb_breakpoint
;
8711 len
= tdep
->thumb_breakpoint_size
;
8715 bkp_insn
= tdep
->arm_breakpoint
;
8716 len
= tdep
->arm_breakpoint_size
;
8719 /* Put breakpoint afterwards. */
8720 write_memory (to
+ offset
, bkp_insn
, len
);
8722 if (debug_displaced
)
8723 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
8724 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
8727 /* Entry point for copying an instruction into scratch space for displaced
8730 struct displaced_step_closure
*
8731 arm_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
8732 CORE_ADDR from
, CORE_ADDR to
,
8733 struct regcache
*regs
)
8735 struct displaced_step_closure
*dsc
8736 = xmalloc (sizeof (struct displaced_step_closure
));
8737 arm_process_displaced_insn (gdbarch
, from
, to
, regs
, dsc
);
8738 arm_displaced_init_closure (gdbarch
, from
, to
, dsc
);
8743 /* Entry point for cleaning things up after a displaced instruction has been
8747 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
8748 struct displaced_step_closure
*dsc
,
8749 CORE_ADDR from
, CORE_ADDR to
,
8750 struct regcache
*regs
)
8753 dsc
->cleanup (gdbarch
, regs
, dsc
);
8755 if (!dsc
->wrote_to_pc
)
8756 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
8757 dsc
->insn_addr
+ dsc
->insn_size
);
8761 #include "bfd-in2.h"
8762 #include "libcoff.h"
8765 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
8767 struct gdbarch
*gdbarch
= info
->application_data
;
8769 if (arm_pc_is_thumb (gdbarch
, memaddr
))
8771 static asymbol
*asym
;
8772 static combined_entry_type ce
;
8773 static struct coff_symbol_struct csym
;
8774 static struct bfd fake_bfd
;
8775 static bfd_target fake_target
;
8777 if (csym
.native
== NULL
)
8779 /* Create a fake symbol vector containing a Thumb symbol.
8780 This is solely so that the code in print_insn_little_arm()
8781 and print_insn_big_arm() in opcodes/arm-dis.c will detect
8782 the presence of a Thumb symbol and switch to decoding
8783 Thumb instructions. */
8785 fake_target
.flavour
= bfd_target_coff_flavour
;
8786 fake_bfd
.xvec
= &fake_target
;
8787 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
8789 csym
.symbol
.the_bfd
= &fake_bfd
;
8790 csym
.symbol
.name
= "fake";
8791 asym
= (asymbol
*) & csym
;
8794 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
8795 info
->symbols
= &asym
;
8798 info
->symbols
= NULL
;
8800 if (info
->endian
== BFD_ENDIAN_BIG
)
8801 return print_insn_big_arm (memaddr
, info
);
8803 return print_insn_little_arm (memaddr
, info
);
8806 /* The following define instruction sequences that will cause ARM
8807 cpu's to take an undefined instruction trap. These are used to
8808 signal a breakpoint to GDB.
8810 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
8811 modes. A different instruction is required for each mode. The ARM
8812 cpu's can also be big or little endian. Thus four different
8813 instructions are needed to support all cases.
8815 Note: ARMv4 defines several new instructions that will take the
8816 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
8817 not in fact add the new instructions. The new undefined
8818 instructions in ARMv4 are all instructions that had no defined
8819 behaviour in earlier chips. There is no guarantee that they will
8820 raise an exception, but may be treated as NOP's. In practice, it
8821 may only safe to rely on instructions matching:
8823 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
8824 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
8825 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
8827 Even this may only true if the condition predicate is true. The
8828 following use a condition predicate of ALWAYS so it is always TRUE.
8830 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
8831 and NetBSD all use a software interrupt rather than an undefined
8832 instruction to force a trap. This can be handled by by the
8833 abi-specific code during establishment of the gdbarch vector. */
8835 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
8836 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
8837 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
8838 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
8840 static const gdb_byte arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
8841 static const gdb_byte arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
8842 static const gdb_byte arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
8843 static const gdb_byte arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
8845 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
8846 the program counter value to determine whether a 16-bit or 32-bit
8847 breakpoint should be used. It returns a pointer to a string of
8848 bytes that encode a breakpoint instruction, stores the length of
8849 the string to *lenptr, and adjusts the program counter (if
8850 necessary) to point to the actual memory location where the
8851 breakpoint should be inserted. */
8853 static const unsigned char *
8854 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
8856 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8857 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8859 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
8861 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
8863 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
8864 check whether we are replacing a 32-bit instruction. */
8865 if (tdep
->thumb2_breakpoint
!= NULL
)
8868 if (target_read_memory (*pcptr
, buf
, 2) == 0)
8870 unsigned short inst1
;
8871 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
8872 if (thumb_insn_size (inst1
) == 4)
8874 *lenptr
= tdep
->thumb2_breakpoint_size
;
8875 return tdep
->thumb2_breakpoint
;
8880 *lenptr
= tdep
->thumb_breakpoint_size
;
8881 return tdep
->thumb_breakpoint
;
8885 *lenptr
= tdep
->arm_breakpoint_size
;
8886 return tdep
->arm_breakpoint
;
8891 arm_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
8894 arm_breakpoint_from_pc (gdbarch
, pcptr
, kindptr
);
8896 if (arm_pc_is_thumb (gdbarch
, *pcptr
) && *kindptr
== 4)
8897 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
8898 that this is not confused with a 32-bit ARM breakpoint. */
8902 /* Extract from an array REGBUF containing the (raw) register state a
8903 function return value of type TYPE, and copy that, in virtual
8904 format, into VALBUF. */
8907 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
8910 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
8911 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8913 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
8915 switch (gdbarch_tdep (gdbarch
)->fp_model
)
8919 /* The value is in register F0 in internal format. We need to
8920 extract the raw value and then convert it to the desired
8922 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
8924 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
8925 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
8926 valbuf
, gdbarch_byte_order (gdbarch
));
8930 case ARM_FLOAT_SOFT_FPA
:
8931 case ARM_FLOAT_SOFT_VFP
:
8932 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8933 not using the VFP ABI code. */
8935 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
8936 if (TYPE_LENGTH (type
) > 4)
8937 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
8938 valbuf
+ INT_REGISTER_SIZE
);
8942 internal_error (__FILE__
, __LINE__
,
8943 _("arm_extract_return_value: "
8944 "Floating point model not supported"));
8948 else if (TYPE_CODE (type
) == TYPE_CODE_INT
8949 || TYPE_CODE (type
) == TYPE_CODE_CHAR
8950 || TYPE_CODE (type
) == TYPE_CODE_BOOL
8951 || TYPE_CODE (type
) == TYPE_CODE_PTR
8952 || TYPE_CODE (type
) == TYPE_CODE_REF
8953 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
8955 /* If the type is a plain integer, then the access is
8956 straight-forward. Otherwise we have to play around a bit
8958 int len
= TYPE_LENGTH (type
);
8959 int regno
= ARM_A1_REGNUM
;
8964 /* By using store_unsigned_integer we avoid having to do
8965 anything special for small big-endian values. */
8966 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
8967 store_unsigned_integer (valbuf
,
8968 (len
> INT_REGISTER_SIZE
8969 ? INT_REGISTER_SIZE
: len
),
8971 len
-= INT_REGISTER_SIZE
;
8972 valbuf
+= INT_REGISTER_SIZE
;
8977 /* For a structure or union the behaviour is as if the value had
8978 been stored to word-aligned memory and then loaded into
8979 registers with 32-bit load instruction(s). */
8980 int len
= TYPE_LENGTH (type
);
8981 int regno
= ARM_A1_REGNUM
;
8982 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8986 regcache_cooked_read (regs
, regno
++, tmpbuf
);
8987 memcpy (valbuf
, tmpbuf
,
8988 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
8989 len
-= INT_REGISTER_SIZE
;
8990 valbuf
+= INT_REGISTER_SIZE
;
8996 /* Will a function return an aggregate type in memory or in a
8997 register? Return 0 if an aggregate type can be returned in a
8998 register, 1 if it must be returned in memory. */
9001 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
9004 enum type_code code
;
9006 CHECK_TYPEDEF (type
);
9008 /* In the ARM ABI, "integer" like aggregate types are returned in
9009 registers. For an aggregate type to be integer like, its size
9010 must be less than or equal to INT_REGISTER_SIZE and the
9011 offset of each addressable subfield must be zero. Note that bit
9012 fields are not addressable, and all addressable subfields of
9013 unions always start at offset zero.
9015 This function is based on the behaviour of GCC 2.95.1.
9016 See: gcc/arm.c: arm_return_in_memory() for details.
9018 Note: All versions of GCC before GCC 2.95.2 do not set up the
9019 parameters correctly for a function returning the following
9020 structure: struct { float f;}; This should be returned in memory,
9021 not a register. Richard Earnshaw sent me a patch, but I do not
9022 know of any way to detect if a function like the above has been
9023 compiled with the correct calling convention. */
9025 /* All aggregate types that won't fit in a register must be returned
9027 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
9032 /* The AAPCS says all aggregates not larger than a word are returned
9034 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
9037 /* The only aggregate types that can be returned in a register are
9038 structs and unions. Arrays must be returned in memory. */
9039 code
= TYPE_CODE (type
);
9040 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
9045 /* Assume all other aggregate types can be returned in a register.
9046 Run a check for structures, unions and arrays. */
9049 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
9052 /* Need to check if this struct/union is "integer" like. For
9053 this to be true, its size must be less than or equal to
9054 INT_REGISTER_SIZE and the offset of each addressable
9055 subfield must be zero. Note that bit fields are not
9056 addressable, and unions always start at offset zero. If any
9057 of the subfields is a floating point type, the struct/union
9058 cannot be an integer type. */
9060 /* For each field in the object, check:
9061 1) Is it FP? --> yes, nRc = 1;
9062 2) Is it addressable (bitpos != 0) and
9063 not packed (bitsize == 0)?
9067 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
9069 enum type_code field_type_code
;
9070 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
,
9073 /* Is it a floating point type field? */
9074 if (field_type_code
== TYPE_CODE_FLT
)
9080 /* If bitpos != 0, then we have to care about it. */
9081 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
9083 /* Bitfields are not addressable. If the field bitsize is
9084 zero, then the field is not packed. Hence it cannot be
9085 a bitfield or any other packed type. */
9086 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
9098 /* Write into appropriate registers a function return value of type
9099 TYPE, given in virtual format. */
9102 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
9103 const gdb_byte
*valbuf
)
9105 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
9106 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
9108 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
9110 gdb_byte buf
[MAX_REGISTER_SIZE
];
9112 switch (gdbarch_tdep (gdbarch
)->fp_model
)
9116 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
9117 gdbarch_byte_order (gdbarch
));
9118 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
9121 case ARM_FLOAT_SOFT_FPA
:
9122 case ARM_FLOAT_SOFT_VFP
:
9123 /* ARM_FLOAT_VFP can arise if this is a variadic function so
9124 not using the VFP ABI code. */
9126 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
9127 if (TYPE_LENGTH (type
) > 4)
9128 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
9129 valbuf
+ INT_REGISTER_SIZE
);
9133 internal_error (__FILE__
, __LINE__
,
9134 _("arm_store_return_value: Floating "
9135 "point model not supported"));
9139 else if (TYPE_CODE (type
) == TYPE_CODE_INT
9140 || TYPE_CODE (type
) == TYPE_CODE_CHAR
9141 || TYPE_CODE (type
) == TYPE_CODE_BOOL
9142 || TYPE_CODE (type
) == TYPE_CODE_PTR
9143 || TYPE_CODE (type
) == TYPE_CODE_REF
9144 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
9146 if (TYPE_LENGTH (type
) <= 4)
9148 /* Values of one word or less are zero/sign-extended and
9150 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
9151 LONGEST val
= unpack_long (type
, valbuf
);
9153 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
9154 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
9158 /* Integral values greater than one word are stored in consecutive
9159 registers starting with r0. This will always be a multiple of
9160 the regiser size. */
9161 int len
= TYPE_LENGTH (type
);
9162 int regno
= ARM_A1_REGNUM
;
9166 regcache_cooked_write (regs
, regno
++, valbuf
);
9167 len
-= INT_REGISTER_SIZE
;
9168 valbuf
+= INT_REGISTER_SIZE
;
9174 /* For a structure or union the behaviour is as if the value had
9175 been stored to word-aligned memory and then loaded into
9176 registers with 32-bit load instruction(s). */
9177 int len
= TYPE_LENGTH (type
);
9178 int regno
= ARM_A1_REGNUM
;
9179 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
9183 memcpy (tmpbuf
, valbuf
,
9184 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
9185 regcache_cooked_write (regs
, regno
++, tmpbuf
);
9186 len
-= INT_REGISTER_SIZE
;
9187 valbuf
+= INT_REGISTER_SIZE
;
9193 /* Handle function return values. */
9195 static enum return_value_convention
9196 arm_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
9197 struct type
*valtype
, struct regcache
*regcache
,
9198 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
9200 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9201 struct type
*func_type
= function
? value_type (function
) : NULL
;
9202 enum arm_vfp_cprc_base_type vfp_base_type
;
9205 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
9206 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
9208 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
9209 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
9211 for (i
= 0; i
< vfp_base_count
; i
++)
9213 if (reg_char
== 'q')
9216 arm_neon_quad_write (gdbarch
, regcache
, i
,
9217 writebuf
+ i
* unit_length
);
9220 arm_neon_quad_read (gdbarch
, regcache
, i
,
9221 readbuf
+ i
* unit_length
);
9228 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d", reg_char
, i
);
9229 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9232 regcache_cooked_write (regcache
, regnum
,
9233 writebuf
+ i
* unit_length
);
9235 regcache_cooked_read (regcache
, regnum
,
9236 readbuf
+ i
* unit_length
);
9239 return RETURN_VALUE_REGISTER_CONVENTION
;
9242 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
9243 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
9244 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
9246 if (tdep
->struct_return
== pcc_struct_return
9247 || arm_return_in_memory (gdbarch
, valtype
))
9248 return RETURN_VALUE_STRUCT_CONVENTION
;
9251 /* AAPCS returns complex types longer than a register in memory. */
9252 if (tdep
->arm_abi
!= ARM_ABI_APCS
9253 && TYPE_CODE (valtype
) == TYPE_CODE_COMPLEX
9254 && TYPE_LENGTH (valtype
) > INT_REGISTER_SIZE
)
9255 return RETURN_VALUE_STRUCT_CONVENTION
;
9258 arm_store_return_value (valtype
, regcache
, writebuf
);
9261 arm_extract_return_value (valtype
, regcache
, readbuf
);
9263 return RETURN_VALUE_REGISTER_CONVENTION
;
9268 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
9270 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
9271 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9272 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
9274 gdb_byte buf
[INT_REGISTER_SIZE
];
9276 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
9278 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
9282 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
9286 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
9287 return the target PC. Otherwise return 0. */
9290 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
9294 CORE_ADDR start_addr
;
9296 /* Find the starting address and name of the function containing the PC. */
9297 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
9299 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
9301 start_addr
= arm_skip_bx_reg (frame
, pc
);
9302 if (start_addr
!= 0)
9308 /* If PC is in a Thumb call or return stub, return the address of the
9309 target PC, which is in a register. The thunk functions are called
9310 _call_via_xx, where x is the register name. The possible names
9311 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
9312 functions, named __ARM_call_via_r[0-7]. */
9313 if (startswith (name
, "_call_via_")
9314 || startswith (name
, "__ARM_call_via_"))
9316 /* Use the name suffix to determine which register contains the
9318 static char *table
[15] =
9319 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
9320 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
9323 int offset
= strlen (name
) - 2;
9325 for (regno
= 0; regno
<= 14; regno
++)
9326 if (strcmp (&name
[offset
], table
[regno
]) == 0)
9327 return get_frame_register_unsigned (frame
, regno
);
9330 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
9331 non-interworking calls to foo. We could decode the stubs
9332 to find the target but it's easier to use the symbol table. */
9333 namelen
= strlen (name
);
9334 if (name
[0] == '_' && name
[1] == '_'
9335 && ((namelen
> 2 + strlen ("_from_thumb")
9336 && startswith (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb"))
9337 || (namelen
> 2 + strlen ("_from_arm")
9338 && startswith (name
+ namelen
- strlen ("_from_arm"), "_from_arm"))))
9341 int target_len
= namelen
- 2;
9342 struct bound_minimal_symbol minsym
;
9343 struct objfile
*objfile
;
9344 struct obj_section
*sec
;
9346 if (name
[namelen
- 1] == 'b')
9347 target_len
-= strlen ("_from_thumb");
9349 target_len
-= strlen ("_from_arm");
9351 target_name
= alloca (target_len
+ 1);
9352 memcpy (target_name
, name
+ 2, target_len
);
9353 target_name
[target_len
] = '\0';
9355 sec
= find_pc_section (pc
);
9356 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
9357 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
9358 if (minsym
.minsym
!= NULL
)
9359 return BMSYMBOL_VALUE_ADDRESS (minsym
);
9364 return 0; /* not a stub */
9368 set_arm_command (char *args
, int from_tty
)
9370 printf_unfiltered (_("\
9371 \"set arm\" must be followed by an apporpriate subcommand.\n"));
9372 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
9376 show_arm_command (char *args
, int from_tty
)
9378 cmd_show_list (showarmcmdlist
, from_tty
, "");
9382 arm_update_current_architecture (void)
9384 struct gdbarch_info info
;
9386 /* If the current architecture is not ARM, we have nothing to do. */
9387 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_arm
)
9390 /* Update the architecture. */
9391 gdbarch_info_init (&info
);
9393 if (!gdbarch_update_p (info
))
9394 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
9398 set_fp_model_sfunc (char *args
, int from_tty
,
9399 struct cmd_list_element
*c
)
9403 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
9404 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
9406 arm_fp_model
= fp_model
;
9410 if (fp_model
== ARM_FLOAT_LAST
)
9411 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
9414 arm_update_current_architecture ();
9418 show_fp_model (struct ui_file
*file
, int from_tty
,
9419 struct cmd_list_element
*c
, const char *value
)
9421 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
9423 if (arm_fp_model
== ARM_FLOAT_AUTO
9424 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
9425 fprintf_filtered (file
, _("\
9426 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
9427 fp_model_strings
[tdep
->fp_model
]);
9429 fprintf_filtered (file
, _("\
9430 The current ARM floating point model is \"%s\".\n"),
9431 fp_model_strings
[arm_fp_model
]);
9435 arm_set_abi (char *args
, int from_tty
,
9436 struct cmd_list_element
*c
)
9440 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
9441 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
9443 arm_abi_global
= arm_abi
;
9447 if (arm_abi
== ARM_ABI_LAST
)
9448 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
9451 arm_update_current_architecture ();
9455 arm_show_abi (struct ui_file
*file
, int from_tty
,
9456 struct cmd_list_element
*c
, const char *value
)
9458 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
9460 if (arm_abi_global
== ARM_ABI_AUTO
9461 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
9462 fprintf_filtered (file
, _("\
9463 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
9464 arm_abi_strings
[tdep
->arm_abi
]);
9466 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
9471 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
9472 struct cmd_list_element
*c
, const char *value
)
9474 fprintf_filtered (file
,
9475 _("The current execution mode assumed "
9476 "(when symbols are unavailable) is \"%s\".\n"),
9477 arm_fallback_mode_string
);
9481 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
9482 struct cmd_list_element
*c
, const char *value
)
9484 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
9486 fprintf_filtered (file
,
9487 _("The current execution mode assumed "
9488 "(even when symbols are available) is \"%s\".\n"),
9489 arm_force_mode_string
);
9492 /* If the user changes the register disassembly style used for info
9493 register and other commands, we have to also switch the style used
9494 in opcodes for disassembly output. This function is run in the "set
9495 arm disassembly" command, and does that. */
9498 set_disassembly_style_sfunc (char *args
, int from_tty
,
9499 struct cmd_list_element
*c
)
9501 set_disassembly_style ();
9504 /* Return the ARM register name corresponding to register I. */
9506 arm_register_name (struct gdbarch
*gdbarch
, int i
)
9508 const int num_regs
= gdbarch_num_regs (gdbarch
);
9510 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
9511 && i
>= num_regs
&& i
< num_regs
+ 32)
9513 static const char *const vfp_pseudo_names
[] = {
9514 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
9515 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
9516 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
9517 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
9520 return vfp_pseudo_names
[i
- num_regs
];
9523 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
9524 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
9526 static const char *const neon_pseudo_names
[] = {
9527 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
9528 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
9531 return neon_pseudo_names
[i
- num_regs
- 32];
9534 if (i
>= ARRAY_SIZE (arm_register_names
))
9535 /* These registers are only supported on targets which supply
9536 an XML description. */
9539 return arm_register_names
[i
];
9543 set_disassembly_style (void)
9547 /* Find the style that the user wants. */
9548 for (current
= 0; current
< num_disassembly_options
; current
++)
9549 if (disassembly_style
== valid_disassembly_styles
[current
])
9551 gdb_assert (current
< num_disassembly_options
);
9553 /* Synchronize the disassembler. */
9554 set_arm_regname_option (current
);
9557 /* Test whether the coff symbol specific value corresponds to a Thumb
9561 coff_sym_is_thumb (int val
)
9563 return (val
== C_THUMBEXT
9564 || val
== C_THUMBSTAT
9565 || val
== C_THUMBEXTFUNC
9566 || val
== C_THUMBSTATFUNC
9567 || val
== C_THUMBLABEL
);
9570 /* arm_coff_make_msymbol_special()
9571 arm_elf_make_msymbol_special()
9573 These functions test whether the COFF or ELF symbol corresponds to
9574 an address in thumb code, and set a "special" bit in a minimal
9575 symbol to indicate that it does. */
9578 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
9580 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type
*)sym
)->internal_elf_sym
)
9581 == ST_BRANCH_TO_THUMB
)
9582 MSYMBOL_SET_SPECIAL (msym
);
9586 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
9588 if (coff_sym_is_thumb (val
))
9589 MSYMBOL_SET_SPECIAL (msym
);
9593 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
9595 struct arm_per_objfile
*data
= arg
;
9598 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
9599 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
9603 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
9606 const char *name
= bfd_asymbol_name (sym
);
9607 struct arm_per_objfile
*data
;
9608 VEC(arm_mapping_symbol_s
) **map_p
;
9609 struct arm_mapping_symbol new_map_sym
;
9611 gdb_assert (name
[0] == '$');
9612 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
9615 data
= objfile_data (objfile
, arm_objfile_data_key
);
9618 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
9619 struct arm_per_objfile
);
9620 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
9621 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
9622 objfile
->obfd
->section_count
,
9623 VEC(arm_mapping_symbol_s
) *);
9625 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
9627 new_map_sym
.value
= sym
->value
;
9628 new_map_sym
.type
= name
[1];
9630 /* Assume that most mapping symbols appear in order of increasing
9631 value. If they were randomly distributed, it would be faster to
9632 always push here and then sort at first use. */
9633 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
9635 struct arm_mapping_symbol
*prev_map_sym
;
9637 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
9638 if (prev_map_sym
->value
>= sym
->value
)
9641 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
9642 arm_compare_mapping_symbols
);
9643 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
9648 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
9652 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
9654 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
9655 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
9657 /* If necessary, set the T bit. */
9660 ULONGEST val
, t_bit
;
9661 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
9662 t_bit
= arm_psr_thumb_bit (gdbarch
);
9663 if (arm_pc_is_thumb (gdbarch
, pc
))
9664 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
9667 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
9672 /* Read the contents of a NEON quad register, by reading from two
9673 double registers. This is used to implement the quad pseudo
9674 registers, and for argument passing in case the quad registers are
9675 missing; vectors are passed in quad registers when using the VFP
9676 ABI, even if a NEON unit is not present. REGNUM is the index of
9677 the quad register, in [0, 15]. */
9679 static enum register_status
9680 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9681 int regnum
, gdb_byte
*buf
)
9684 gdb_byte reg_buf
[8];
9685 int offset
, double_regnum
;
9686 enum register_status status
;
9688 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
9689 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9692 /* d0 is always the least significant half of q0. */
9693 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9698 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9699 if (status
!= REG_VALID
)
9701 memcpy (buf
+ offset
, reg_buf
, 8);
9703 offset
= 8 - offset
;
9704 status
= regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
9705 if (status
!= REG_VALID
)
9707 memcpy (buf
+ offset
, reg_buf
, 8);
9712 static enum register_status
9713 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9714 int regnum
, gdb_byte
*buf
)
9716 const int num_regs
= gdbarch_num_regs (gdbarch
);
9718 gdb_byte reg_buf
[8];
9719 int offset
, double_regnum
;
9721 gdb_assert (regnum
>= num_regs
);
9724 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
9725 /* Quad-precision register. */
9726 return arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
9729 enum register_status status
;
9731 /* Single-precision register. */
9732 gdb_assert (regnum
< 32);
9734 /* s0 is always the least significant half of d0. */
9735 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9736 offset
= (regnum
& 1) ? 0 : 4;
9738 offset
= (regnum
& 1) ? 4 : 0;
9740 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
9741 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9744 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9745 if (status
== REG_VALID
)
9746 memcpy (buf
, reg_buf
+ offset
, 4);
9751 /* Store the contents of BUF to a NEON quad register, by writing to
9752 two double registers. This is used to implement the quad pseudo
9753 registers, and for argument passing in case the quad registers are
9754 missing; vectors are passed in quad registers when using the VFP
9755 ABI, even if a NEON unit is not present. REGNUM is the index
9756 of the quad register, in [0, 15]. */
9759 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9760 int regnum
, const gdb_byte
*buf
)
9763 int offset
, double_regnum
;
9765 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
9766 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9769 /* d0 is always the least significant half of q0. */
9770 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9775 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
9776 offset
= 8 - offset
;
9777 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
9781 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9782 int regnum
, const gdb_byte
*buf
)
9784 const int num_regs
= gdbarch_num_regs (gdbarch
);
9786 gdb_byte reg_buf
[8];
9787 int offset
, double_regnum
;
9789 gdb_assert (regnum
>= num_regs
);
9792 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
9793 /* Quad-precision register. */
9794 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
9797 /* Single-precision register. */
9798 gdb_assert (regnum
< 32);
9800 /* s0 is always the least significant half of d0. */
9801 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9802 offset
= (regnum
& 1) ? 0 : 4;
9804 offset
= (regnum
& 1) ? 4 : 0;
9806 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
9807 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9810 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9811 memcpy (reg_buf
+ offset
, buf
, 4);
9812 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
9816 static struct value
*
9817 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
9819 const int *reg_p
= baton
;
9820 return value_of_register (*reg_p
, frame
);
9823 static enum gdb_osabi
9824 arm_elf_osabi_sniffer (bfd
*abfd
)
9826 unsigned int elfosabi
;
9827 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
9829 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
9831 if (elfosabi
== ELFOSABI_ARM
)
9832 /* GNU tools use this value. Check note sections in this case,
9834 bfd_map_over_sections (abfd
,
9835 generic_elf_osabi_sniff_abi_tag_sections
,
9838 /* Anything else will be handled by the generic ELF sniffer. */
9843 arm_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
9844 struct reggroup
*group
)
9846 /* FPS register's type is INT, but belongs to float_reggroup. Beside
9847 this, FPS register belongs to save_regroup, restore_reggroup, and
9848 all_reggroup, of course. */
9849 if (regnum
== ARM_FPS_REGNUM
)
9850 return (group
== float_reggroup
9851 || group
== save_reggroup
9852 || group
== restore_reggroup
9853 || group
== all_reggroup
);
9855 return default_register_reggroup_p (gdbarch
, regnum
, group
);
9859 /* For backward-compatibility we allow two 'g' packet lengths with
9860 the remote protocol depending on whether FPA registers are
9861 supplied. M-profile targets do not have FPA registers, but some
9862 stubs already exist in the wild which use a 'g' packet which
9863 supplies them albeit with dummy values. The packet format which
9864 includes FPA registers should be considered deprecated for
9865 M-profile targets. */
9868 arm_register_g_packet_guesses (struct gdbarch
*gdbarch
)
9870 if (gdbarch_tdep (gdbarch
)->is_m
)
9872 /* If we know from the executable this is an M-profile target,
9873 cater for remote targets whose register set layout is the
9874 same as the FPA layout. */
9875 register_remote_g_packet_guess (gdbarch
,
9876 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
9877 (16 * INT_REGISTER_SIZE
)
9878 + (8 * FP_REGISTER_SIZE
)
9879 + (2 * INT_REGISTER_SIZE
),
9880 tdesc_arm_with_m_fpa_layout
);
9882 /* The regular M-profile layout. */
9883 register_remote_g_packet_guess (gdbarch
,
9884 /* r0-r12,sp,lr,pc; xpsr */
9885 (16 * INT_REGISTER_SIZE
)
9886 + INT_REGISTER_SIZE
,
9889 /* M-profile plus M4F VFP. */
9890 register_remote_g_packet_guess (gdbarch
,
9891 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
9892 (16 * INT_REGISTER_SIZE
)
9893 + (16 * VFP_REGISTER_SIZE
)
9894 + (2 * INT_REGISTER_SIZE
),
9895 tdesc_arm_with_m_vfp_d16
);
9898 /* Otherwise we don't have a useful guess. */
9902 /* Initialize the current architecture based on INFO. If possible,
9903 re-use an architecture from ARCHES, which is a list of
9904 architectures already created during this debugging session.
9906 Called e.g. at program startup, when reading a core file, and when
9907 reading a binary file. */
9909 static struct gdbarch
*
9910 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
9912 struct gdbarch_tdep
*tdep
;
9913 struct gdbarch
*gdbarch
;
9914 struct gdbarch_list
*best_arch
;
9915 enum arm_abi_kind arm_abi
= arm_abi_global
;
9916 enum arm_float_model fp_model
= arm_fp_model
;
9917 struct tdesc_arch_data
*tdesc_data
= NULL
;
9919 int have_vfp_registers
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
9921 int have_fpa_registers
= 1;
9922 const struct target_desc
*tdesc
= info
.target_desc
;
9924 /* If we have an object to base this architecture on, try to determine
9927 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
9929 int ei_osabi
, e_flags
;
9931 switch (bfd_get_flavour (info
.abfd
))
9933 case bfd_target_aout_flavour
:
9934 /* Assume it's an old APCS-style ABI. */
9935 arm_abi
= ARM_ABI_APCS
;
9938 case bfd_target_coff_flavour
:
9939 /* Assume it's an old APCS-style ABI. */
9941 arm_abi
= ARM_ABI_APCS
;
9944 case bfd_target_elf_flavour
:
9945 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
9946 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9948 if (ei_osabi
== ELFOSABI_ARM
)
9950 /* GNU tools used to use this value, but do not for EABI
9951 objects. There's nowhere to tag an EABI version
9952 anyway, so assume APCS. */
9953 arm_abi
= ARM_ABI_APCS
;
9955 else if (ei_osabi
== ELFOSABI_NONE
)
9957 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
9958 int attr_arch
, attr_profile
;
9962 case EF_ARM_EABI_UNKNOWN
:
9963 /* Assume GNU tools. */
9964 arm_abi
= ARM_ABI_APCS
;
9967 case EF_ARM_EABI_VER4
:
9968 case EF_ARM_EABI_VER5
:
9969 arm_abi
= ARM_ABI_AAPCS
;
9970 /* EABI binaries default to VFP float ordering.
9971 They may also contain build attributes that can
9972 be used to identify if the VFP argument-passing
9974 if (fp_model
== ARM_FLOAT_AUTO
)
9977 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
9981 case AEABI_VFP_args_base
:
9982 /* "The user intended FP parameter/result
9983 passing to conform to AAPCS, base
9985 fp_model
= ARM_FLOAT_SOFT_VFP
;
9987 case AEABI_VFP_args_vfp
:
9988 /* "The user intended FP parameter/result
9989 passing to conform to AAPCS, VFP
9991 fp_model
= ARM_FLOAT_VFP
;
9993 case AEABI_VFP_args_toolchain
:
9994 /* "The user intended FP parameter/result
9995 passing to conform to tool chain-specific
9996 conventions" - we don't know any such
9997 conventions, so leave it as "auto". */
9999 case AEABI_VFP_args_compatible
:
10000 /* "Code is compatible with both the base
10001 and VFP variants; the user did not permit
10002 non-variadic functions to pass FP
10003 parameters/results" - leave it as
10007 /* Attribute value not mentioned in the
10008 November 2012 ABI, so leave it as
10013 fp_model
= ARM_FLOAT_SOFT_VFP
;
10019 /* Leave it as "auto". */
10020 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
10025 /* Detect M-profile programs. This only works if the
10026 executable file includes build attributes; GCC does
10027 copy them to the executable, but e.g. RealView does
10029 attr_arch
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
10031 attr_profile
= bfd_elf_get_obj_attr_int (info
.abfd
,
10033 Tag_CPU_arch_profile
);
10034 /* GCC specifies the profile for v6-M; RealView only
10035 specifies the profile for architectures starting with
10036 V7 (as opposed to architectures with a tag
10037 numerically greater than TAG_CPU_ARCH_V7). */
10038 if (!tdesc_has_registers (tdesc
)
10039 && (attr_arch
== TAG_CPU_ARCH_V6_M
10040 || attr_arch
== TAG_CPU_ARCH_V6S_M
10041 || attr_profile
== 'M'))
10046 if (fp_model
== ARM_FLOAT_AUTO
)
10048 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
10050 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
10053 /* Leave it as "auto". Strictly speaking this case
10054 means FPA, but almost nobody uses that now, and
10055 many toolchains fail to set the appropriate bits
10056 for the floating-point model they use. */
10058 case EF_ARM_SOFT_FLOAT
:
10059 fp_model
= ARM_FLOAT_SOFT_FPA
;
10061 case EF_ARM_VFP_FLOAT
:
10062 fp_model
= ARM_FLOAT_VFP
;
10064 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
10065 fp_model
= ARM_FLOAT_SOFT_VFP
;
10070 if (e_flags
& EF_ARM_BE8
)
10071 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
10076 /* Leave it as "auto". */
10081 /* Check any target description for validity. */
10082 if (tdesc_has_registers (tdesc
))
10084 /* For most registers we require GDB's default names; but also allow
10085 the numeric names for sp / lr / pc, as a convenience. */
10086 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
10087 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
10088 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
10090 const struct tdesc_feature
*feature
;
10093 feature
= tdesc_find_feature (tdesc
,
10094 "org.gnu.gdb.arm.core");
10095 if (feature
== NULL
)
10097 feature
= tdesc_find_feature (tdesc
,
10098 "org.gnu.gdb.arm.m-profile");
10099 if (feature
== NULL
)
10105 tdesc_data
= tdesc_data_alloc ();
10108 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
10109 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
10110 arm_register_names
[i
]);
10111 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
10114 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
10117 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
10121 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10122 ARM_PS_REGNUM
, "xpsr");
10124 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10125 ARM_PS_REGNUM
, "cpsr");
10129 tdesc_data_cleanup (tdesc_data
);
10133 feature
= tdesc_find_feature (tdesc
,
10134 "org.gnu.gdb.arm.fpa");
10135 if (feature
!= NULL
)
10138 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
10139 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
10140 arm_register_names
[i
]);
10143 tdesc_data_cleanup (tdesc_data
);
10148 have_fpa_registers
= 0;
10150 feature
= tdesc_find_feature (tdesc
,
10151 "org.gnu.gdb.xscale.iwmmxt");
10152 if (feature
!= NULL
)
10154 static const char *const iwmmxt_names
[] = {
10155 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
10156 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
10157 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
10158 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
10162 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
10164 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
10165 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
10167 /* Check for the control registers, but do not fail if they
10169 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
10170 tdesc_numbered_register (feature
, tdesc_data
, i
,
10171 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
10173 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
10175 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
10176 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
10180 tdesc_data_cleanup (tdesc_data
);
10185 /* If we have a VFP unit, check whether the single precision registers
10186 are present. If not, then we will synthesize them as pseudo
10188 feature
= tdesc_find_feature (tdesc
,
10189 "org.gnu.gdb.arm.vfp");
10190 if (feature
!= NULL
)
10192 static const char *const vfp_double_names
[] = {
10193 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
10194 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
10195 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
10196 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
10199 /* Require the double precision registers. There must be either
10202 for (i
= 0; i
< 32; i
++)
10204 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10206 vfp_double_names
[i
]);
10210 if (!valid_p
&& i
== 16)
10213 /* Also require FPSCR. */
10214 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10215 ARM_FPSCR_REGNUM
, "fpscr");
10218 tdesc_data_cleanup (tdesc_data
);
10222 if (tdesc_unnumbered_register (feature
, "s0") == 0)
10223 have_vfp_pseudos
= 1;
10225 have_vfp_registers
= 1;
10227 /* If we have VFP, also check for NEON. The architecture allows
10228 NEON without VFP (integer vector operations only), but GDB
10229 does not support that. */
10230 feature
= tdesc_find_feature (tdesc
,
10231 "org.gnu.gdb.arm.neon");
10232 if (feature
!= NULL
)
10234 /* NEON requires 32 double-precision registers. */
10237 tdesc_data_cleanup (tdesc_data
);
10241 /* If there are quad registers defined by the stub, use
10242 their type; otherwise (normally) provide them with
10243 the default type. */
10244 if (tdesc_unnumbered_register (feature
, "q0") == 0)
10245 have_neon_pseudos
= 1;
10252 /* If there is already a candidate, use it. */
10253 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
10255 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
10257 if (arm_abi
!= ARM_ABI_AUTO
10258 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
10261 if (fp_model
!= ARM_FLOAT_AUTO
10262 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
10265 /* There are various other properties in tdep that we do not
10266 need to check here: those derived from a target description,
10267 since gdbarches with a different target description are
10268 automatically disqualified. */
10270 /* Do check is_m, though, since it might come from the binary. */
10271 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
10274 /* Found a match. */
10278 if (best_arch
!= NULL
)
10280 if (tdesc_data
!= NULL
)
10281 tdesc_data_cleanup (tdesc_data
);
10282 return best_arch
->gdbarch
;
10285 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
10286 gdbarch
= gdbarch_alloc (&info
, tdep
);
10288 /* Record additional information about the architecture we are defining.
10289 These are gdbarch discriminators, like the OSABI. */
10290 tdep
->arm_abi
= arm_abi
;
10291 tdep
->fp_model
= fp_model
;
10293 tdep
->have_fpa_registers
= have_fpa_registers
;
10294 tdep
->have_vfp_registers
= have_vfp_registers
;
10295 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
10296 tdep
->have_neon_pseudos
= have_neon_pseudos
;
10297 tdep
->have_neon
= have_neon
;
10299 arm_register_g_packet_guesses (gdbarch
);
10302 switch (info
.byte_order_for_code
)
10304 case BFD_ENDIAN_BIG
:
10305 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
10306 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
10307 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
10308 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
10312 case BFD_ENDIAN_LITTLE
:
10313 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
10314 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
10315 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
10316 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
10321 internal_error (__FILE__
, __LINE__
,
10322 _("arm_gdbarch_init: bad byte order for float format"));
10325 /* On ARM targets char defaults to unsigned. */
10326 set_gdbarch_char_signed (gdbarch
, 0);
10328 /* Note: for displaced stepping, this includes the breakpoint, and one word
10329 of additional scratch space. This setting isn't used for anything beside
10330 displaced stepping at present. */
10331 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
10333 /* This should be low enough for everything. */
10334 tdep
->lowest_pc
= 0x20;
10335 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
10337 /* The default, for both APCS and AAPCS, is to return small
10338 structures in registers. */
10339 tdep
->struct_return
= reg_struct_return
;
10341 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
10342 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
10344 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
10346 /* Frame handling. */
10347 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
10348 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
10349 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
10351 frame_base_set_default (gdbarch
, &arm_normal_base
);
10353 /* Address manipulation. */
10354 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
10356 /* Advance PC across function entry code. */
10357 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
10359 /* Detect whether PC is in function epilogue. */
10360 set_gdbarch_in_function_epilogue_p (gdbarch
, arm_in_function_epilogue_p
);
10362 /* Skip trampolines. */
10363 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
10365 /* The stack grows downward. */
10366 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
10368 /* Breakpoint manipulation. */
10369 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
10370 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
10371 arm_remote_breakpoint_from_pc
);
10373 /* Information about registers, etc. */
10374 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
10375 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
10376 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
10377 set_gdbarch_register_type (gdbarch
, arm_register_type
);
10378 set_gdbarch_register_reggroup_p (gdbarch
, arm_register_reggroup_p
);
10380 /* This "info float" is FPA-specific. Use the generic version if we
10381 do not have FPA. */
10382 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
10383 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
10385 /* Internal <-> external register number maps. */
10386 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
10387 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
10389 set_gdbarch_register_name (gdbarch
, arm_register_name
);
10391 /* Returning results. */
10392 set_gdbarch_return_value (gdbarch
, arm_return_value
);
10395 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
10397 /* Minsymbol frobbing. */
10398 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
10399 set_gdbarch_coff_make_msymbol_special (gdbarch
,
10400 arm_coff_make_msymbol_special
);
10401 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
10403 /* Thumb-2 IT block support. */
10404 set_gdbarch_adjust_breakpoint_address (gdbarch
,
10405 arm_adjust_breakpoint_address
);
10407 /* Virtual tables. */
10408 set_gdbarch_vbit_in_delta (gdbarch
, 1);
10410 /* Hook in the ABI-specific overrides, if they have been registered. */
10411 gdbarch_init_osabi (info
, gdbarch
);
10413 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
10415 /* Add some default predicates. */
10417 frame_unwind_append_unwinder (gdbarch
, &arm_m_exception_unwind
);
10418 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
10419 dwarf2_append_unwinders (gdbarch
);
10420 frame_unwind_append_unwinder (gdbarch
, &arm_exidx_unwind
);
10421 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
10423 /* Now we have tuned the configuration, set a few final things,
10424 based on what the OS ABI has told us. */
10426 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
10427 binaries are always marked. */
10428 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
10429 tdep
->arm_abi
= ARM_ABI_APCS
;
10431 /* Watchpoints are not steppable. */
10432 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
10434 /* We used to default to FPA for generic ARM, but almost nobody
10435 uses that now, and we now provide a way for the user to force
10436 the model. So default to the most useful variant. */
10437 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
10438 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
10440 if (tdep
->jb_pc
>= 0)
10441 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
10443 /* Floating point sizes and format. */
10444 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
10445 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
10447 set_gdbarch_double_format
10448 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
10449 set_gdbarch_long_double_format
10450 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
10454 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
10455 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
10458 if (have_vfp_pseudos
)
10460 /* NOTE: These are the only pseudo registers used by
10461 the ARM target at the moment. If more are added, a
10462 little more care in numbering will be needed. */
10464 int num_pseudos
= 32;
10465 if (have_neon_pseudos
)
10467 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
10468 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
10469 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
10474 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
10476 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
10478 /* Override tdesc_register_type to adjust the types of VFP
10479 registers for NEON. */
10480 set_gdbarch_register_type (gdbarch
, arm_register_type
);
10483 /* Add standard register aliases. We add aliases even for those
10484 nanes which are used by the current architecture - it's simpler,
10485 and does no harm, since nothing ever lists user registers. */
10486 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
10487 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
10488 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
10494 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
10496 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
10501 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
10502 (unsigned long) tdep
->lowest_pc
);
10505 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
10508 _initialize_arm_tdep (void)
10510 struct ui_file
*stb
;
10512 struct cmd_list_element
*new_set
, *new_show
;
10513 const char *setname
;
10514 const char *setdesc
;
10515 const char *const *regnames
;
10517 static char *helptext
;
10518 char regdesc
[1024], *rdptr
= regdesc
;
10519 size_t rest
= sizeof (regdesc
);
10521 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
10523 arm_objfile_data_key
10524 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
10526 /* Add ourselves to objfile event chain. */
10527 observer_attach_new_objfile (arm_exidx_new_objfile
);
10529 = register_objfile_data_with_cleanup (NULL
, arm_exidx_data_free
);
10531 /* Register an ELF OS ABI sniffer for ARM binaries. */
10532 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
10533 bfd_target_elf_flavour
,
10534 arm_elf_osabi_sniffer
);
10536 /* Initialize the standard target descriptions. */
10537 initialize_tdesc_arm_with_m ();
10538 initialize_tdesc_arm_with_m_fpa_layout ();
10539 initialize_tdesc_arm_with_m_vfp_d16 ();
10540 initialize_tdesc_arm_with_iwmmxt ();
10541 initialize_tdesc_arm_with_vfpv2 ();
10542 initialize_tdesc_arm_with_vfpv3 ();
10543 initialize_tdesc_arm_with_neon ();
10545 /* Get the number of possible sets of register names defined in opcodes. */
10546 num_disassembly_options
= get_arm_regname_num_options ();
10548 /* Add root prefix command for all "set arm"/"show arm" commands. */
10549 add_prefix_cmd ("arm", no_class
, set_arm_command
,
10550 _("Various ARM-specific commands."),
10551 &setarmcmdlist
, "set arm ", 0, &setlist
);
10553 add_prefix_cmd ("arm", no_class
, show_arm_command
,
10554 _("Various ARM-specific commands."),
10555 &showarmcmdlist
, "show arm ", 0, &showlist
);
10557 /* Sync the opcode insn printer with our register viewer. */
10558 parse_arm_disassembler_option ("reg-names-std");
10560 /* Initialize the array that will be passed to
10561 add_setshow_enum_cmd(). */
10562 valid_disassembly_styles
10563 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
10564 for (i
= 0; i
< num_disassembly_options
; i
++)
10566 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
10567 valid_disassembly_styles
[i
] = setname
;
10568 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
10571 /* When we find the default names, tell the disassembler to use
10573 if (!strcmp (setname
, "std"))
10575 disassembly_style
= setname
;
10576 set_arm_regname_option (i
);
10579 /* Mark the end of valid options. */
10580 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
10582 /* Create the help text. */
10583 stb
= mem_fileopen ();
10584 fprintf_unfiltered (stb
, "%s%s%s",
10585 _("The valid values are:\n"),
10587 _("The default is \"std\"."));
10588 helptext
= ui_file_xstrdup (stb
, NULL
);
10589 ui_file_delete (stb
);
10591 add_setshow_enum_cmd("disassembler", no_class
,
10592 valid_disassembly_styles
, &disassembly_style
,
10593 _("Set the disassembly style."),
10594 _("Show the disassembly style."),
10596 set_disassembly_style_sfunc
,
10597 NULL
, /* FIXME: i18n: The disassembly style is
10599 &setarmcmdlist
, &showarmcmdlist
);
10601 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
10602 _("Set usage of ARM 32-bit mode."),
10603 _("Show usage of ARM 32-bit mode."),
10604 _("When off, a 26-bit PC will be used."),
10606 NULL
, /* FIXME: i18n: Usage of ARM 32-bit
10608 &setarmcmdlist
, &showarmcmdlist
);
10610 /* Add a command to allow the user to force the FPU model. */
10611 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
10612 _("Set the floating point type."),
10613 _("Show the floating point type."),
10614 _("auto - Determine the FP typefrom the OS-ABI.\n\
10615 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
10616 fpa - FPA co-processor (GCC compiled).\n\
10617 softvfp - Software FP with pure-endian doubles.\n\
10618 vfp - VFP co-processor."),
10619 set_fp_model_sfunc
, show_fp_model
,
10620 &setarmcmdlist
, &showarmcmdlist
);
10622 /* Add a command to allow the user to force the ABI. */
10623 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
10625 _("Show the ABI."),
10626 NULL
, arm_set_abi
, arm_show_abi
,
10627 &setarmcmdlist
, &showarmcmdlist
);
10629 /* Add two commands to allow the user to force the assumed
10631 add_setshow_enum_cmd ("fallback-mode", class_support
,
10632 arm_mode_strings
, &arm_fallback_mode_string
,
10633 _("Set the mode assumed when symbols are unavailable."),
10634 _("Show the mode assumed when symbols are unavailable."),
10635 NULL
, NULL
, arm_show_fallback_mode
,
10636 &setarmcmdlist
, &showarmcmdlist
);
10637 add_setshow_enum_cmd ("force-mode", class_support
,
10638 arm_mode_strings
, &arm_force_mode_string
,
10639 _("Set the mode assumed even when symbols are available."),
10640 _("Show the mode assumed even when symbols are available."),
10641 NULL
, NULL
, arm_show_force_mode
,
10642 &setarmcmdlist
, &showarmcmdlist
);
10644 /* Debugging flag. */
10645 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
10646 _("Set ARM debugging."),
10647 _("Show ARM debugging."),
10648 _("When on, arm-specific debugging is enabled."),
10650 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
10651 &setdebuglist
, &showdebuglist
);
10654 /* ARM-reversible process record data structures. */
10656 #define ARM_INSN_SIZE_BYTES 4
10657 #define THUMB_INSN_SIZE_BYTES 2
10658 #define THUMB2_INSN_SIZE_BYTES 4
10661 /* Position of the bit within a 32-bit ARM instruction
10662 that defines whether the instruction is a load or store. */
10663 #define INSN_S_L_BIT_NUM 20
10665 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
10668 unsigned int reg_len = LENGTH; \
10671 REGS = XNEWVEC (uint32_t, reg_len); \
10672 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
10677 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
10680 unsigned int mem_len = LENGTH; \
10683 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
10684 memcpy(&MEMS->len, &RECORD_BUF[0], \
10685 sizeof(struct arm_mem_r) * LENGTH); \
10690 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
10691 #define INSN_RECORDED(ARM_RECORD) \
10692 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
10694 /* ARM memory record structure. */
10697 uint32_t len
; /* Record length. */
10698 uint32_t addr
; /* Memory address. */
10701 /* ARM instruction record contains opcode of current insn
10702 and execution state (before entry to decode_insn()),
10703 contains list of to-be-modified registers and
10704 memory blocks (on return from decode_insn()). */
10706 typedef struct insn_decode_record_t
10708 struct gdbarch
*gdbarch
;
10709 struct regcache
*regcache
;
10710 CORE_ADDR this_addr
; /* Address of the insn being decoded. */
10711 uint32_t arm_insn
; /* Should accommodate thumb. */
10712 uint32_t cond
; /* Condition code. */
10713 uint32_t opcode
; /* Insn opcode. */
10714 uint32_t decode
; /* Insn decode bits. */
10715 uint32_t mem_rec_count
; /* No of mem records. */
10716 uint32_t reg_rec_count
; /* No of reg records. */
10717 uint32_t *arm_regs
; /* Registers to be saved for this record. */
10718 struct arm_mem_r
*arm_mems
; /* Memory to be saved for this record. */
10719 } insn_decode_record
;
10722 /* Checks ARM SBZ and SBO mandatory fields. */
10725 sbo_sbz (uint32_t insn
, uint32_t bit_num
, uint32_t len
, uint32_t sbo
)
10727 uint32_t ones
= bits (insn
, bit_num
- 1, (bit_num
-1) + (len
- 1));
10746 enum arm_record_result
10748 ARM_RECORD_SUCCESS
= 0,
10749 ARM_RECORD_FAILURE
= 1
10756 } arm_record_strx_t
;
10767 arm_record_strx (insn_decode_record
*arm_insn_r
, uint32_t *record_buf
,
10768 uint32_t *record_buf_mem
, arm_record_strx_t str_type
)
10771 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10772 ULONGEST u_regval
[2]= {0};
10774 uint32_t reg_src1
= 0, reg_src2
= 0;
10775 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
10776 uint32_t opcode1
= 0;
10778 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10779 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10780 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
10783 if (14 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10785 /* 1) Handle misc store, immediate offset. */
10786 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
10787 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
10788 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10789 regcache_raw_read_unsigned (reg_cache
, reg_src1
,
10791 if (ARM_PC_REGNUM
== reg_src1
)
10793 /* If R15 was used as Rn, hence current PC+8. */
10794 u_regval
[0] = u_regval
[0] + 8;
10796 offset_8
= (immed_high
<< 4) | immed_low
;
10797 /* Calculate target store address. */
10798 if (14 == arm_insn_r
->opcode
)
10800 tgt_mem_addr
= u_regval
[0] + offset_8
;
10804 tgt_mem_addr
= u_regval
[0] - offset_8
;
10806 if (ARM_RECORD_STRH
== str_type
)
10808 record_buf_mem
[0] = 2;
10809 record_buf_mem
[1] = tgt_mem_addr
;
10810 arm_insn_r
->mem_rec_count
= 1;
10812 else if (ARM_RECORD_STRD
== str_type
)
10814 record_buf_mem
[0] = 4;
10815 record_buf_mem
[1] = tgt_mem_addr
;
10816 record_buf_mem
[2] = 4;
10817 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10818 arm_insn_r
->mem_rec_count
= 2;
10821 else if (12 == arm_insn_r
->opcode
|| 8 == arm_insn_r
->opcode
)
10823 /* 2) Store, register offset. */
10825 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10827 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10828 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10829 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10830 if (15 == reg_src2
)
10832 /* If R15 was used as Rn, hence current PC+8. */
10833 u_regval
[0] = u_regval
[0] + 8;
10835 /* Calculate target store address, Rn +/- Rm, register offset. */
10836 if (12 == arm_insn_r
->opcode
)
10838 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10842 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10844 if (ARM_RECORD_STRH
== str_type
)
10846 record_buf_mem
[0] = 2;
10847 record_buf_mem
[1] = tgt_mem_addr
;
10848 arm_insn_r
->mem_rec_count
= 1;
10850 else if (ARM_RECORD_STRD
== str_type
)
10852 record_buf_mem
[0] = 4;
10853 record_buf_mem
[1] = tgt_mem_addr
;
10854 record_buf_mem
[2] = 4;
10855 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10856 arm_insn_r
->mem_rec_count
= 2;
10859 else if (11 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10860 || 2 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
10862 /* 3) Store, immediate pre-indexed. */
10863 /* 5) Store, immediate post-indexed. */
10864 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
10865 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
10866 offset_8
= (immed_high
<< 4) | immed_low
;
10867 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10868 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10869 /* Calculate target store address, Rn +/- Rm, register offset. */
10870 if (15 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
10872 tgt_mem_addr
= u_regval
[0] + offset_8
;
10876 tgt_mem_addr
= u_regval
[0] - offset_8
;
10878 if (ARM_RECORD_STRH
== str_type
)
10880 record_buf_mem
[0] = 2;
10881 record_buf_mem
[1] = tgt_mem_addr
;
10882 arm_insn_r
->mem_rec_count
= 1;
10884 else if (ARM_RECORD_STRD
== str_type
)
10886 record_buf_mem
[0] = 4;
10887 record_buf_mem
[1] = tgt_mem_addr
;
10888 record_buf_mem
[2] = 4;
10889 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10890 arm_insn_r
->mem_rec_count
= 2;
10892 /* Record Rn also as it changes. */
10893 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
10894 arm_insn_r
->reg_rec_count
= 1;
10896 else if (9 == arm_insn_r
->opcode
|| 13 == arm_insn_r
->opcode
10897 || 0 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
10899 /* 4) Store, register pre-indexed. */
10900 /* 6) Store, register post -indexed. */
10901 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10902 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10903 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10904 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10905 /* Calculate target store address, Rn +/- Rm, register offset. */
10906 if (13 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
10908 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10912 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10914 if (ARM_RECORD_STRH
== str_type
)
10916 record_buf_mem
[0] = 2;
10917 record_buf_mem
[1] = tgt_mem_addr
;
10918 arm_insn_r
->mem_rec_count
= 1;
10920 else if (ARM_RECORD_STRD
== str_type
)
10922 record_buf_mem
[0] = 4;
10923 record_buf_mem
[1] = tgt_mem_addr
;
10924 record_buf_mem
[2] = 4;
10925 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10926 arm_insn_r
->mem_rec_count
= 2;
10928 /* Record Rn also as it changes. */
10929 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
10930 arm_insn_r
->reg_rec_count
= 1;
10935 /* Handling ARM extension space insns. */
10938 arm_record_extension_space (insn_decode_record
*arm_insn_r
)
10940 uint32_t ret
= 0; /* Return value: -1:record failure ; 0:success */
10941 uint32_t opcode1
= 0, opcode2
= 0, insn_op1
= 0;
10942 uint32_t record_buf
[8], record_buf_mem
[8];
10943 uint32_t reg_src1
= 0;
10944 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
10945 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10946 ULONGEST u_regval
= 0;
10948 gdb_assert (!INSN_RECORDED(arm_insn_r
));
10949 /* Handle unconditional insn extension space. */
10951 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 27);
10952 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10953 if (arm_insn_r
->cond
)
10955 /* PLD has no affect on architectural state, it just affects
10957 if (5 == ((opcode1
& 0xE0) >> 5))
10960 record_buf
[0] = ARM_PS_REGNUM
;
10961 record_buf
[1] = ARM_LR_REGNUM
;
10962 arm_insn_r
->reg_rec_count
= 2;
10964 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10968 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10969 if (3 == opcode1
&& bit (arm_insn_r
->arm_insn
, 4))
10972 /* Undefined instruction on ARM V5; need to handle if later
10973 versions define it. */
10976 opcode1
= bits (arm_insn_r
->arm_insn
, 24, 27);
10977 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10978 insn_op1
= bits (arm_insn_r
->arm_insn
, 20, 23);
10980 /* Handle arithmetic insn extension space. */
10981 if (!opcode1
&& 9 == opcode2
&& 1 != arm_insn_r
->cond
10982 && !INSN_RECORDED(arm_insn_r
))
10984 /* Handle MLA(S) and MUL(S). */
10985 if (0 <= insn_op1
&& 3 >= insn_op1
)
10987 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10988 record_buf
[1] = ARM_PS_REGNUM
;
10989 arm_insn_r
->reg_rec_count
= 2;
10991 else if (4 <= insn_op1
&& 15 >= insn_op1
)
10993 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
10994 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10995 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10996 record_buf
[2] = ARM_PS_REGNUM
;
10997 arm_insn_r
->reg_rec_count
= 3;
11001 opcode1
= bits (arm_insn_r
->arm_insn
, 26, 27);
11002 opcode2
= bits (arm_insn_r
->arm_insn
, 23, 24);
11003 insn_op1
= bits (arm_insn_r
->arm_insn
, 21, 22);
11005 /* Handle control insn extension space. */
11007 if (!opcode1
&& 2 == opcode2
&& !bit (arm_insn_r
->arm_insn
, 20)
11008 && 1 != arm_insn_r
->cond
&& !INSN_RECORDED(arm_insn_r
))
11010 if (!bit (arm_insn_r
->arm_insn
,25))
11012 if (!bits (arm_insn_r
->arm_insn
, 4, 7))
11014 if ((0 == insn_op1
) || (2 == insn_op1
))
11017 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11018 arm_insn_r
->reg_rec_count
= 1;
11020 else if (1 == insn_op1
)
11022 /* CSPR is going to be changed. */
11023 record_buf
[0] = ARM_PS_REGNUM
;
11024 arm_insn_r
->reg_rec_count
= 1;
11026 else if (3 == insn_op1
)
11028 /* SPSR is going to be changed. */
11029 /* We need to get SPSR value, which is yet to be done. */
11030 printf_unfiltered (_("Process record does not support "
11031 "instruction 0x%0x at address %s.\n"),
11032 arm_insn_r
->arm_insn
,
11033 paddress (arm_insn_r
->gdbarch
,
11034 arm_insn_r
->this_addr
));
11038 else if (1 == bits (arm_insn_r
->arm_insn
, 4, 7))
11043 record_buf
[0] = ARM_PS_REGNUM
;
11044 arm_insn_r
->reg_rec_count
= 1;
11046 else if (3 == insn_op1
)
11049 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11050 arm_insn_r
->reg_rec_count
= 1;
11053 else if (3 == bits (arm_insn_r
->arm_insn
, 4, 7))
11056 record_buf
[0] = ARM_PS_REGNUM
;
11057 record_buf
[1] = ARM_LR_REGNUM
;
11058 arm_insn_r
->reg_rec_count
= 2;
11060 else if (5 == bits (arm_insn_r
->arm_insn
, 4, 7))
11062 /* QADD, QSUB, QDADD, QDSUB */
11063 record_buf
[0] = ARM_PS_REGNUM
;
11064 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
11065 arm_insn_r
->reg_rec_count
= 2;
11067 else if (7 == bits (arm_insn_r
->arm_insn
, 4, 7))
11070 record_buf
[0] = ARM_PS_REGNUM
;
11071 record_buf
[1] = ARM_LR_REGNUM
;
11072 arm_insn_r
->reg_rec_count
= 2;
11074 /* Save SPSR also;how? */
11075 printf_unfiltered (_("Process record does not support "
11076 "instruction 0x%0x at address %s.\n"),
11077 arm_insn_r
->arm_insn
,
11078 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11081 else if(8 == bits (arm_insn_r
->arm_insn
, 4, 7)
11082 || 10 == bits (arm_insn_r
->arm_insn
, 4, 7)
11083 || 12 == bits (arm_insn_r
->arm_insn
, 4, 7)
11084 || 14 == bits (arm_insn_r
->arm_insn
, 4, 7)
11087 if (0 == insn_op1
|| 1 == insn_op1
)
11089 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
11090 /* We dont do optimization for SMULW<y> where we
11092 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11093 record_buf
[1] = ARM_PS_REGNUM
;
11094 arm_insn_r
->reg_rec_count
= 2;
11096 else if (2 == insn_op1
)
11099 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11100 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11101 arm_insn_r
->reg_rec_count
= 2;
11103 else if (3 == insn_op1
)
11106 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11107 arm_insn_r
->reg_rec_count
= 1;
11113 /* MSR : immediate form. */
11116 /* CSPR is going to be changed. */
11117 record_buf
[0] = ARM_PS_REGNUM
;
11118 arm_insn_r
->reg_rec_count
= 1;
11120 else if (3 == insn_op1
)
11122 /* SPSR is going to be changed. */
11123 /* we need to get SPSR value, which is yet to be done */
11124 printf_unfiltered (_("Process record does not support "
11125 "instruction 0x%0x at address %s.\n"),
11126 arm_insn_r
->arm_insn
,
11127 paddress (arm_insn_r
->gdbarch
,
11128 arm_insn_r
->this_addr
));
11134 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
11135 opcode2
= bits (arm_insn_r
->arm_insn
, 20, 24);
11136 insn_op1
= bits (arm_insn_r
->arm_insn
, 5, 6);
11138 /* Handle load/store insn extension space. */
11140 if (!opcode1
&& bit (arm_insn_r
->arm_insn
, 7)
11141 && bit (arm_insn_r
->arm_insn
, 4) && 1 != arm_insn_r
->cond
11142 && !INSN_RECORDED(arm_insn_r
))
11147 /* These insn, changes register and memory as well. */
11148 /* SWP or SWPB insn. */
11149 /* Get memory address given by Rn. */
11150 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11151 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11152 /* SWP insn ?, swaps word. */
11153 if (8 == arm_insn_r
->opcode
)
11155 record_buf_mem
[0] = 4;
11159 /* SWPB insn, swaps only byte. */
11160 record_buf_mem
[0] = 1;
11162 record_buf_mem
[1] = u_regval
;
11163 arm_insn_r
->mem_rec_count
= 1;
11164 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11165 arm_insn_r
->reg_rec_count
= 1;
11167 else if (1 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
11170 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11173 else if (2 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
11176 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11177 record_buf
[1] = record_buf
[0] + 1;
11178 arm_insn_r
->reg_rec_count
= 2;
11180 else if (3 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
11183 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11186 else if (bit (arm_insn_r
->arm_insn
, 20) && insn_op1
<= 3)
11188 /* LDRH, LDRSB, LDRSH. */
11189 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11190 arm_insn_r
->reg_rec_count
= 1;
11195 opcode1
= bits (arm_insn_r
->arm_insn
, 23, 27);
11196 if (24 == opcode1
&& bit (arm_insn_r
->arm_insn
, 21)
11197 && !INSN_RECORDED(arm_insn_r
))
11200 /* Handle coprocessor insn extension space. */
11203 /* To be done for ARMv5 and later; as of now we return -1. */
11205 printf_unfiltered (_("Process record does not support instruction x%0x "
11206 "at address %s.\n"),arm_insn_r
->arm_insn
,
11207 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11210 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11211 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11216 /* Handling opcode 000 insns. */
11219 arm_record_data_proc_misc_ld_str (insn_decode_record
*arm_insn_r
)
11221 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11222 uint32_t record_buf
[8], record_buf_mem
[8];
11223 ULONGEST u_regval
[2] = {0};
11225 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
11226 uint32_t immed_high
= 0, immed_low
= 0, offset_8
= 0, tgt_mem_addr
= 0;
11227 uint32_t opcode1
= 0;
11229 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11230 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11231 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
11233 /* Data processing insn /multiply insn. */
11234 if (9 == arm_insn_r
->decode
11235 && ((4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
11236 || (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)))
11238 /* Handle multiply instructions. */
11239 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
11240 if (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)
11242 /* Handle MLA and MUL. */
11243 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
11244 record_buf
[1] = ARM_PS_REGNUM
;
11245 arm_insn_r
->reg_rec_count
= 2;
11247 else if (4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
11249 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
11250 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
11251 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
11252 record_buf
[2] = ARM_PS_REGNUM
;
11253 arm_insn_r
->reg_rec_count
= 3;
11256 else if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
11257 && (11 == arm_insn_r
->decode
|| 13 == arm_insn_r
->decode
))
11259 /* Handle misc load insns, as 20th bit (L = 1). */
11260 /* LDR insn has a capability to do branching, if
11261 MOV LR, PC is precceded by LDR insn having Rn as R15
11262 in that case, it emulates branch and link insn, and hence we
11263 need to save CSPR and PC as well. I am not sure this is right
11264 place; as opcode = 010 LDR insn make this happen, if R15 was
11266 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11267 if (15 != reg_dest
)
11269 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11270 arm_insn_r
->reg_rec_count
= 1;
11274 record_buf
[0] = reg_dest
;
11275 record_buf
[1] = ARM_PS_REGNUM
;
11276 arm_insn_r
->reg_rec_count
= 2;
11279 else if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
11280 && sbo_sbz (arm_insn_r
->arm_insn
, 5, 12, 0)
11281 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
11282 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21))
11284 /* Handle MSR insn. */
11285 if (9 == arm_insn_r
->opcode
)
11287 /* CSPR is going to be changed. */
11288 record_buf
[0] = ARM_PS_REGNUM
;
11289 arm_insn_r
->reg_rec_count
= 1;
11293 /* SPSR is going to be changed. */
11294 /* How to read SPSR value? */
11295 printf_unfiltered (_("Process record does not support instruction "
11296 "0x%0x at address %s.\n"),
11297 arm_insn_r
->arm_insn
,
11298 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11302 else if (9 == arm_insn_r
->decode
11303 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
11304 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11306 /* Handling SWP, SWPB. */
11307 /* These insn, changes register and memory as well. */
11308 /* SWP or SWPB insn. */
11310 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11311 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11312 /* SWP insn ?, swaps word. */
11313 if (8 == arm_insn_r
->opcode
)
11315 record_buf_mem
[0] = 4;
11319 /* SWPB insn, swaps only byte. */
11320 record_buf_mem
[0] = 1;
11322 record_buf_mem
[1] = u_regval
[0];
11323 arm_insn_r
->mem_rec_count
= 1;
11324 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11325 arm_insn_r
->reg_rec_count
= 1;
11327 else if (3 == arm_insn_r
->decode
&& 0x12 == opcode1
11328 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
11330 /* Handle BLX, branch and link/exchange. */
11331 if (9 == arm_insn_r
->opcode
)
11333 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
11334 and R14 stores the return address. */
11335 record_buf
[0] = ARM_PS_REGNUM
;
11336 record_buf
[1] = ARM_LR_REGNUM
;
11337 arm_insn_r
->reg_rec_count
= 2;
11340 else if (7 == arm_insn_r
->decode
&& 0x12 == opcode1
)
11342 /* Handle enhanced software breakpoint insn, BKPT. */
11343 /* CPSR is changed to be executed in ARM state, disabling normal
11344 interrupts, entering abort mode. */
11345 /* According to high vector configuration PC is set. */
11346 /* user hit breakpoint and type reverse, in
11347 that case, we need to go back with previous CPSR and
11348 Program Counter. */
11349 record_buf
[0] = ARM_PS_REGNUM
;
11350 record_buf
[1] = ARM_LR_REGNUM
;
11351 arm_insn_r
->reg_rec_count
= 2;
11353 /* Save SPSR also; how? */
11354 printf_unfiltered (_("Process record does not support instruction "
11355 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11356 paddress (arm_insn_r
->gdbarch
,
11357 arm_insn_r
->this_addr
));
11360 else if (11 == arm_insn_r
->decode
11361 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11363 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
11365 /* Handle str(x) insn */
11366 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11369 else if (1 == arm_insn_r
->decode
&& 0x12 == opcode1
11370 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
11372 /* Handle BX, branch and link/exchange. */
11373 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
11374 record_buf
[0] = ARM_PS_REGNUM
;
11375 arm_insn_r
->reg_rec_count
= 1;
11377 else if (1 == arm_insn_r
->decode
&& 0x16 == opcode1
11378 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 4, 1)
11379 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1))
11381 /* Count leading zeros: CLZ. */
11382 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11383 arm_insn_r
->reg_rec_count
= 1;
11385 else if (!bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
11386 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
11387 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1)
11388 && sbo_sbz (arm_insn_r
->arm_insn
, 1, 12, 0)
11391 /* Handle MRS insn. */
11392 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11393 arm_insn_r
->reg_rec_count
= 1;
11395 else if (arm_insn_r
->opcode
<= 15)
11397 /* Normal data processing insns. */
11398 /* Out of 11 shifter operands mode, all the insn modifies destination
11399 register, which is specified by 13-16 decode. */
11400 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11401 record_buf
[1] = ARM_PS_REGNUM
;
11402 arm_insn_r
->reg_rec_count
= 2;
11409 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11410 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11414 /* Handling opcode 001 insns. */
11417 arm_record_data_proc_imm (insn_decode_record
*arm_insn_r
)
11419 uint32_t record_buf
[8], record_buf_mem
[8];
11421 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11422 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11424 if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
11425 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21)
11426 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
11429 /* Handle MSR insn. */
11430 if (9 == arm_insn_r
->opcode
)
11432 /* CSPR is going to be changed. */
11433 record_buf
[0] = ARM_PS_REGNUM
;
11434 arm_insn_r
->reg_rec_count
= 1;
11438 /* SPSR is going to be changed. */
11441 else if (arm_insn_r
->opcode
<= 15)
11443 /* Normal data processing insns. */
11444 /* Out of 11 shifter operands mode, all the insn modifies destination
11445 register, which is specified by 13-16 decode. */
11446 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11447 record_buf
[1] = ARM_PS_REGNUM
;
11448 arm_insn_r
->reg_rec_count
= 2;
11455 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11456 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11460 /* Handle ARM mode instructions with opcode 010. */
11463 arm_record_ld_st_imm_offset (insn_decode_record
*arm_insn_r
)
11465 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11467 uint32_t reg_base
, reg_dest
;
11468 uint32_t offset_12
, tgt_mem_addr
;
11469 uint32_t record_buf
[8], record_buf_mem
[8];
11470 unsigned char wback
;
11473 /* Calculate wback. */
11474 wback
= (bit (arm_insn_r
->arm_insn
, 24) == 0)
11475 || (bit (arm_insn_r
->arm_insn
, 21) == 1);
11477 arm_insn_r
->reg_rec_count
= 0;
11478 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
11480 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11482 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
11485 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11486 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_dest
;
11488 /* The LDR instruction is capable of doing branching. If MOV LR, PC
11489 preceeds a LDR instruction having R15 as reg_base, it
11490 emulates a branch and link instruction, and hence we need to save
11491 CPSR and PC as well. */
11492 if (ARM_PC_REGNUM
== reg_dest
)
11493 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
11495 /* If wback is true, also save the base register, which is going to be
11498 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11502 /* STR (immediate), STRB (immediate), STRBT and STRT. */
11504 offset_12
= bits (arm_insn_r
->arm_insn
, 0, 11);
11505 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
11507 /* Handle bit U. */
11508 if (bit (arm_insn_r
->arm_insn
, 23))
11510 /* U == 1: Add the offset. */
11511 tgt_mem_addr
= (uint32_t) u_regval
+ offset_12
;
11515 /* U == 0: subtract the offset. */
11516 tgt_mem_addr
= (uint32_t) u_regval
- offset_12
;
11519 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
11521 if (bit (arm_insn_r
->arm_insn
, 22))
11523 /* STRB and STRBT: 1 byte. */
11524 record_buf_mem
[0] = 1;
11528 /* STR and STRT: 4 bytes. */
11529 record_buf_mem
[0] = 4;
11532 /* Handle bit P. */
11533 if (bit (arm_insn_r
->arm_insn
, 24))
11534 record_buf_mem
[1] = tgt_mem_addr
;
11536 record_buf_mem
[1] = (uint32_t) u_regval
;
11538 arm_insn_r
->mem_rec_count
= 1;
11540 /* If wback is true, also save the base register, which is going to be
11543 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11546 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11547 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11551 /* Handling opcode 011 insns. */
11554 arm_record_ld_st_reg_offset (insn_decode_record
*arm_insn_r
)
11556 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11558 uint32_t shift_imm
= 0;
11559 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
11560 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
11561 uint32_t record_buf
[8], record_buf_mem
[8];
11564 ULONGEST u_regval
[2];
11566 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11567 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11569 /* Handle enhanced store insns and LDRD DSP insn,
11570 order begins according to addressing modes for store insns
11574 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11576 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11577 /* LDR insn has a capability to do branching, if
11578 MOV LR, PC is precedded by LDR insn having Rn as R15
11579 in that case, it emulates branch and link insn, and hence we
11580 need to save CSPR and PC as well. */
11581 if (15 != reg_dest
)
11583 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11584 arm_insn_r
->reg_rec_count
= 1;
11588 record_buf
[0] = reg_dest
;
11589 record_buf
[1] = ARM_PS_REGNUM
;
11590 arm_insn_r
->reg_rec_count
= 2;
11595 if (! bits (arm_insn_r
->arm_insn
, 4, 11))
11597 /* Store insn, register offset and register pre-indexed,
11598 register post-indexed. */
11600 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
11602 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11603 regcache_raw_read_unsigned (reg_cache
, reg_src1
11605 regcache_raw_read_unsigned (reg_cache
, reg_src2
11607 if (15 == reg_src2
)
11609 /* If R15 was used as Rn, hence current PC+8. */
11610 /* Pre-indexed mode doesnt reach here ; illegal insn. */
11611 u_regval
[0] = u_regval
[0] + 8;
11613 /* Calculate target store address, Rn +/- Rm, register offset. */
11615 if (bit (arm_insn_r
->arm_insn
, 23))
11617 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
11621 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
11624 switch (arm_insn_r
->opcode
)
11638 record_buf_mem
[0] = 4;
11653 record_buf_mem
[0] = 1;
11657 gdb_assert_not_reached ("no decoding pattern found");
11660 record_buf_mem
[1] = tgt_mem_addr
;
11661 arm_insn_r
->mem_rec_count
= 1;
11663 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
11664 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
11665 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
11666 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
11667 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
11668 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
11671 /* Rn is going to be changed in pre-indexed mode and
11672 post-indexed mode as well. */
11673 record_buf
[0] = reg_src2
;
11674 arm_insn_r
->reg_rec_count
= 1;
11679 /* Store insn, scaled register offset; scaled pre-indexed. */
11680 offset_12
= bits (arm_insn_r
->arm_insn
, 5, 6);
11682 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
11684 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11685 /* Get shift_imm. */
11686 shift_imm
= bits (arm_insn_r
->arm_insn
, 7, 11);
11687 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11688 regcache_raw_read_signed (reg_cache
, reg_src1
, &s_word
);
11689 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11690 /* Offset_12 used as shift. */
11694 /* Offset_12 used as index. */
11695 offset_12
= u_regval
[0] << shift_imm
;
11699 offset_12
= (!shift_imm
)?0:u_regval
[0] >> shift_imm
;
11705 if (bit (u_regval
[0], 31))
11707 offset_12
= 0xFFFFFFFF;
11716 /* This is arithmetic shift. */
11717 offset_12
= s_word
>> shift_imm
;
11724 regcache_raw_read_unsigned (reg_cache
, ARM_PS_REGNUM
,
11726 /* Get C flag value and shift it by 31. */
11727 offset_12
= (((bit (u_regval
[1], 29)) << 31) \
11728 | (u_regval
[0]) >> 1);
11732 offset_12
= (u_regval
[0] >> shift_imm
) \
11734 (sizeof(uint32_t) - shift_imm
));
11739 gdb_assert_not_reached ("no decoding pattern found");
11743 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11745 if (bit (arm_insn_r
->arm_insn
, 23))
11747 tgt_mem_addr
= u_regval
[1] + offset_12
;
11751 tgt_mem_addr
= u_regval
[1] - offset_12
;
11754 switch (arm_insn_r
->opcode
)
11768 record_buf_mem
[0] = 4;
11783 record_buf_mem
[0] = 1;
11787 gdb_assert_not_reached ("no decoding pattern found");
11790 record_buf_mem
[1] = tgt_mem_addr
;
11791 arm_insn_r
->mem_rec_count
= 1;
11793 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
11794 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
11795 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
11796 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
11797 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
11798 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
11801 /* Rn is going to be changed in register scaled pre-indexed
11802 mode,and scaled post indexed mode. */
11803 record_buf
[0] = reg_src2
;
11804 arm_insn_r
->reg_rec_count
= 1;
11809 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11810 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11814 /* Handle ARM mode instructions with opcode 100. */
11817 arm_record_ld_st_multiple (insn_decode_record
*arm_insn_r
)
11819 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11820 uint32_t register_count
= 0, register_bits
;
11821 uint32_t reg_base
, addr_mode
;
11822 uint32_t record_buf
[24], record_buf_mem
[48];
11826 /* Fetch the list of registers. */
11827 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
11828 arm_insn_r
->reg_rec_count
= 0;
11830 /* Fetch the base register that contains the address we are loading data
11832 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
11834 /* Calculate wback. */
11835 wback
= (bit (arm_insn_r
->arm_insn
, 21) == 1);
11837 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11839 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
11841 /* Find out which registers are going to be loaded from memory. */
11842 while (register_bits
)
11844 if (register_bits
& 0x00000001)
11845 record_buf
[arm_insn_r
->reg_rec_count
++] = register_count
;
11846 register_bits
= register_bits
>> 1;
11851 /* If wback is true, also save the base register, which is going to be
11854 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11856 /* Save the CPSR register. */
11857 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
11861 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
11863 addr_mode
= bits (arm_insn_r
->arm_insn
, 23, 24);
11865 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
11867 /* Find out how many registers are going to be stored to memory. */
11868 while (register_bits
)
11870 if (register_bits
& 0x00000001)
11872 register_bits
= register_bits
>> 1;
11877 /* STMDA (STMED): Decrement after. */
11879 record_buf_mem
[1] = (uint32_t) u_regval
11880 - register_count
* INT_REGISTER_SIZE
+ 4;
11882 /* STM (STMIA, STMEA): Increment after. */
11884 record_buf_mem
[1] = (uint32_t) u_regval
;
11886 /* STMDB (STMFD): Decrement before. */
11888 record_buf_mem
[1] = (uint32_t) u_regval
11889 - register_count
* INT_REGISTER_SIZE
;
11891 /* STMIB (STMFA): Increment before. */
11893 record_buf_mem
[1] = (uint32_t) u_regval
+ INT_REGISTER_SIZE
;
11896 gdb_assert_not_reached ("no decoding pattern found");
11900 record_buf_mem
[0] = register_count
* INT_REGISTER_SIZE
;
11901 arm_insn_r
->mem_rec_count
= 1;
11903 /* If wback is true, also save the base register, which is going to be
11906 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11909 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11910 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11914 /* Handling opcode 101 insns. */
11917 arm_record_b_bl (insn_decode_record
*arm_insn_r
)
11919 uint32_t record_buf
[8];
11921 /* Handle B, BL, BLX(1) insns. */
11922 /* B simply branches so we do nothing here. */
11923 /* Note: BLX(1) doesnt fall here but instead it falls into
11924 extension space. */
11925 if (bit (arm_insn_r
->arm_insn
, 24))
11927 record_buf
[0] = ARM_LR_REGNUM
;
11928 arm_insn_r
->reg_rec_count
= 1;
11931 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11936 /* Handling opcode 110 insns. */
11939 arm_record_unsupported_insn (insn_decode_record
*arm_insn_r
)
11941 printf_unfiltered (_("Process record does not support instruction "
11942 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11943 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11948 /* Record handler for vector data transfer instructions. */
11951 arm_record_vdata_transfer_insn (insn_decode_record
*arm_insn_r
)
11953 uint32_t bits_a
, bit_c
, bit_l
, reg_t
, reg_v
;
11954 uint32_t record_buf
[4];
11956 const int num_regs
= gdbarch_num_regs (arm_insn_r
->gdbarch
);
11957 reg_t
= bits (arm_insn_r
->arm_insn
, 12, 15);
11958 reg_v
= bits (arm_insn_r
->arm_insn
, 21, 23);
11959 bits_a
= bits (arm_insn_r
->arm_insn
, 21, 23);
11960 bit_l
= bit (arm_insn_r
->arm_insn
, 20);
11961 bit_c
= bit (arm_insn_r
->arm_insn
, 8);
11963 /* Handle VMOV instruction. */
11964 if (bit_l
&& bit_c
)
11966 record_buf
[0] = reg_t
;
11967 arm_insn_r
->reg_rec_count
= 1;
11969 else if (bit_l
&& !bit_c
)
11971 /* Handle VMOV instruction. */
11972 if (bits_a
== 0x00)
11974 if (bit (arm_insn_r
->arm_insn
, 20))
11975 record_buf
[0] = reg_t
;
11977 record_buf
[0] = num_regs
+ (bit (arm_insn_r
->arm_insn
, 7) |
11980 arm_insn_r
->reg_rec_count
= 1;
11982 /* Handle VMRS instruction. */
11983 else if (bits_a
== 0x07)
11986 reg_t
= ARM_PS_REGNUM
;
11988 record_buf
[0] = reg_t
;
11989 arm_insn_r
->reg_rec_count
= 1;
11992 else if (!bit_l
&& !bit_c
)
11994 /* Handle VMOV instruction. */
11995 if (bits_a
== 0x00)
11997 if (bit (arm_insn_r
->arm_insn
, 20))
11998 record_buf
[0] = reg_t
;
12000 record_buf
[0] = num_regs
+ (bit (arm_insn_r
->arm_insn
, 7) |
12003 arm_insn_r
->reg_rec_count
= 1;
12005 /* Handle VMSR instruction. */
12006 else if (bits_a
== 0x07)
12008 record_buf
[0] = ARM_FPSCR_REGNUM
;
12009 arm_insn_r
->reg_rec_count
= 1;
12012 else if (!bit_l
&& bit_c
)
12014 /* Handle VMOV instruction. */
12015 if (!(bits_a
& 0x04))
12017 record_buf
[0] = (reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4))
12019 arm_insn_r
->reg_rec_count
= 1;
12021 /* Handle VDUP instruction. */
12024 if (bit (arm_insn_r
->arm_insn
, 21))
12026 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
12027 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
12028 record_buf
[1] = reg_v
+ ARM_D0_REGNUM
+ 1;
12029 arm_insn_r
->reg_rec_count
= 2;
12033 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
12034 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
12035 arm_insn_r
->reg_rec_count
= 1;
12040 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
12044 /* Record handler for extension register load/store instructions. */
12047 arm_record_exreg_ld_st_insn (insn_decode_record
*arm_insn_r
)
12049 uint32_t opcode
, single_reg
;
12050 uint8_t op_vldm_vstm
;
12051 uint32_t record_buf
[8], record_buf_mem
[128];
12052 ULONGEST u_regval
= 0;
12054 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
12055 const int num_regs
= gdbarch_num_regs (arm_insn_r
->gdbarch
);
12057 opcode
= bits (arm_insn_r
->arm_insn
, 20, 24);
12058 single_reg
= bit (arm_insn_r
->arm_insn
, 8);
12059 op_vldm_vstm
= opcode
& 0x1b;
12061 /* Handle VMOV instructions. */
12062 if ((opcode
& 0x1e) == 0x04)
12064 if (bit (arm_insn_r
->arm_insn
, 4))
12066 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
12067 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
12068 arm_insn_r
->reg_rec_count
= 2;
12072 uint8_t reg_m
= (bits (arm_insn_r
->arm_insn
, 0, 3) << 1)
12073 | bit (arm_insn_r
->arm_insn
, 5);
12077 record_buf
[0] = num_regs
+ reg_m
;
12078 record_buf
[1] = num_regs
+ reg_m
+ 1;
12079 arm_insn_r
->reg_rec_count
= 2;
12083 record_buf
[0] = reg_m
+ ARM_D0_REGNUM
;
12084 arm_insn_r
->reg_rec_count
= 1;
12088 /* Handle VSTM and VPUSH instructions. */
12089 else if (op_vldm_vstm
== 0x08 || op_vldm_vstm
== 0x0a
12090 || op_vldm_vstm
== 0x12)
12092 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
12093 uint32_t memory_index
= 0;
12095 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
12096 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12097 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
12098 imm_off32
= imm_off8
<< 24;
12099 memory_count
= imm_off8
;
12101 if (bit (arm_insn_r
->arm_insn
, 23))
12102 start_address
= u_regval
;
12104 start_address
= u_regval
- imm_off32
;
12106 if (bit (arm_insn_r
->arm_insn
, 21))
12108 record_buf
[0] = reg_rn
;
12109 arm_insn_r
->reg_rec_count
= 1;
12112 while (memory_count
> 0)
12116 record_buf_mem
[memory_index
] = start_address
;
12117 record_buf_mem
[memory_index
+ 1] = 4;
12118 start_address
= start_address
+ 4;
12119 memory_index
= memory_index
+ 2;
12123 record_buf_mem
[memory_index
] = start_address
;
12124 record_buf_mem
[memory_index
+ 1] = 4;
12125 record_buf_mem
[memory_index
+ 2] = start_address
+ 4;
12126 record_buf_mem
[memory_index
+ 3] = 4;
12127 start_address
= start_address
+ 8;
12128 memory_index
= memory_index
+ 4;
12132 arm_insn_r
->mem_rec_count
= (memory_index
>> 1);
12134 /* Handle VLDM instructions. */
12135 else if (op_vldm_vstm
== 0x09 || op_vldm_vstm
== 0x0b
12136 || op_vldm_vstm
== 0x13)
12138 uint32_t reg_count
, reg_vd
;
12139 uint32_t reg_index
= 0;
12141 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
12142 reg_count
= bits (arm_insn_r
->arm_insn
, 0, 7);
12145 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
12147 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
12149 if (bit (arm_insn_r
->arm_insn
, 21))
12150 record_buf
[reg_index
++] = bits (arm_insn_r
->arm_insn
, 16, 19);
12152 while (reg_count
> 0)
12155 record_buf
[reg_index
++] = num_regs
+ reg_vd
+ reg_count
- 1;
12157 record_buf
[reg_index
++] = ARM_D0_REGNUM
+ reg_vd
+ reg_count
- 1;
12161 arm_insn_r
->reg_rec_count
= reg_index
;
12163 /* VSTR Vector store register. */
12164 else if ((opcode
& 0x13) == 0x10)
12166 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
12167 uint32_t memory_index
= 0;
12169 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
12170 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12171 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
12172 imm_off32
= imm_off8
<< 24;
12173 memory_count
= imm_off8
;
12175 if (bit (arm_insn_r
->arm_insn
, 23))
12176 start_address
= u_regval
+ imm_off32
;
12178 start_address
= u_regval
- imm_off32
;
12182 record_buf_mem
[memory_index
] = start_address
;
12183 record_buf_mem
[memory_index
+ 1] = 4;
12184 arm_insn_r
->mem_rec_count
= 1;
12188 record_buf_mem
[memory_index
] = start_address
;
12189 record_buf_mem
[memory_index
+ 1] = 4;
12190 record_buf_mem
[memory_index
+ 2] = start_address
+ 4;
12191 record_buf_mem
[memory_index
+ 3] = 4;
12192 arm_insn_r
->mem_rec_count
= 2;
12195 /* VLDR Vector load register. */
12196 else if ((opcode
& 0x13) == 0x11)
12198 uint32_t reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
12202 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
12203 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
;
12207 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
12208 record_buf
[0] = num_regs
+ reg_vd
;
12210 arm_insn_r
->reg_rec_count
= 1;
12213 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
12214 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
12218 /* Record handler for arm/thumb mode VFP data processing instructions. */
12221 arm_record_vfp_data_proc_insn (insn_decode_record
*arm_insn_r
)
12223 uint32_t opc1
, opc2
, opc3
, dp_op_sz
, bit_d
, reg_vd
;
12224 uint32_t record_buf
[4];
12225 enum insn_types
{INSN_T0
, INSN_T1
, INSN_T2
, INSN_T3
, INSN_INV
};
12226 enum insn_types curr_insn_type
= INSN_INV
;
12228 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
12229 opc1
= bits (arm_insn_r
->arm_insn
, 20, 23);
12230 opc2
= bits (arm_insn_r
->arm_insn
, 16, 19);
12231 opc3
= bits (arm_insn_r
->arm_insn
, 6, 7);
12232 dp_op_sz
= bit (arm_insn_r
->arm_insn
, 8);
12233 bit_d
= bit (arm_insn_r
->arm_insn
, 22);
12234 opc1
= opc1
& 0x04;
12236 /* Handle VMLA, VMLS. */
12239 if (bit (arm_insn_r
->arm_insn
, 10))
12241 if (bit (arm_insn_r
->arm_insn
, 6))
12242 curr_insn_type
= INSN_T0
;
12244 curr_insn_type
= INSN_T1
;
12249 curr_insn_type
= INSN_T1
;
12251 curr_insn_type
= INSN_T2
;
12254 /* Handle VNMLA, VNMLS, VNMUL. */
12255 else if (opc1
== 0x01)
12258 curr_insn_type
= INSN_T1
;
12260 curr_insn_type
= INSN_T2
;
12263 else if (opc1
== 0x02 && !(opc3
& 0x01))
12265 if (bit (arm_insn_r
->arm_insn
, 10))
12267 if (bit (arm_insn_r
->arm_insn
, 6))
12268 curr_insn_type
= INSN_T0
;
12270 curr_insn_type
= INSN_T1
;
12275 curr_insn_type
= INSN_T1
;
12277 curr_insn_type
= INSN_T2
;
12280 /* Handle VADD, VSUB. */
12281 else if (opc1
== 0x03)
12283 if (!bit (arm_insn_r
->arm_insn
, 9))
12285 if (bit (arm_insn_r
->arm_insn
, 6))
12286 curr_insn_type
= INSN_T0
;
12288 curr_insn_type
= INSN_T1
;
12293 curr_insn_type
= INSN_T1
;
12295 curr_insn_type
= INSN_T2
;
12299 else if (opc1
== 0x0b)
12302 curr_insn_type
= INSN_T1
;
12304 curr_insn_type
= INSN_T2
;
12306 /* Handle all other vfp data processing instructions. */
12307 else if (opc1
== 0x0b)
12310 if (!(opc3
& 0x01) || (opc2
== 0x00 && opc3
== 0x01))
12312 if (bit (arm_insn_r
->arm_insn
, 4))
12314 if (bit (arm_insn_r
->arm_insn
, 6))
12315 curr_insn_type
= INSN_T0
;
12317 curr_insn_type
= INSN_T1
;
12322 curr_insn_type
= INSN_T1
;
12324 curr_insn_type
= INSN_T2
;
12327 /* Handle VNEG and VABS. */
12328 else if ((opc2
== 0x01 && opc3
== 0x01)
12329 || (opc2
== 0x00 && opc3
== 0x03))
12331 if (!bit (arm_insn_r
->arm_insn
, 11))
12333 if (bit (arm_insn_r
->arm_insn
, 6))
12334 curr_insn_type
= INSN_T0
;
12336 curr_insn_type
= INSN_T1
;
12341 curr_insn_type
= INSN_T1
;
12343 curr_insn_type
= INSN_T2
;
12346 /* Handle VSQRT. */
12347 else if (opc2
== 0x01 && opc3
== 0x03)
12350 curr_insn_type
= INSN_T1
;
12352 curr_insn_type
= INSN_T2
;
12355 else if (opc2
== 0x07 && opc3
== 0x03)
12358 curr_insn_type
= INSN_T1
;
12360 curr_insn_type
= INSN_T2
;
12362 else if (opc3
& 0x01)
12365 if ((opc2
== 0x08) || (opc2
& 0x0e) == 0x0c)
12367 if (!bit (arm_insn_r
->arm_insn
, 18))
12368 curr_insn_type
= INSN_T2
;
12372 curr_insn_type
= INSN_T1
;
12374 curr_insn_type
= INSN_T2
;
12378 else if ((opc2
& 0x0e) == 0x0a || (opc2
& 0x0e) == 0x0e)
12381 curr_insn_type
= INSN_T1
;
12383 curr_insn_type
= INSN_T2
;
12385 /* Handle VCVTB, VCVTT. */
12386 else if ((opc2
& 0x0e) == 0x02)
12387 curr_insn_type
= INSN_T2
;
12388 /* Handle VCMP, VCMPE. */
12389 else if ((opc2
& 0x0e) == 0x04)
12390 curr_insn_type
= INSN_T3
;
12394 switch (curr_insn_type
)
12397 reg_vd
= reg_vd
| (bit_d
<< 4);
12398 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
12399 record_buf
[1] = reg_vd
+ ARM_D0_REGNUM
+ 1;
12400 arm_insn_r
->reg_rec_count
= 2;
12404 reg_vd
= reg_vd
| (bit_d
<< 4);
12405 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
12406 arm_insn_r
->reg_rec_count
= 1;
12410 reg_vd
= (reg_vd
<< 1) | bit_d
;
12411 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
12412 arm_insn_r
->reg_rec_count
= 1;
12416 record_buf
[0] = ARM_FPSCR_REGNUM
;
12417 arm_insn_r
->reg_rec_count
= 1;
12421 gdb_assert_not_reached ("no decoding pattern found");
12425 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
12429 /* Handling opcode 110 insns. */
12432 arm_record_asimd_vfp_coproc (insn_decode_record
*arm_insn_r
)
12434 uint32_t op
, op1
, op1_sbit
, op1_ebit
, coproc
;
12436 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
12437 op1
= bits (arm_insn_r
->arm_insn
, 20, 25);
12438 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
12440 if ((coproc
& 0x0e) == 0x0a)
12442 /* Handle extension register ld/st instructions. */
12444 return arm_record_exreg_ld_st_insn (arm_insn_r
);
12446 /* 64-bit transfers between arm core and extension registers. */
12447 if ((op1
& 0x3e) == 0x04)
12448 return arm_record_exreg_ld_st_insn (arm_insn_r
);
12452 /* Handle coprocessor ld/st instructions. */
12457 return arm_record_unsupported_insn (arm_insn_r
);
12460 return arm_record_unsupported_insn (arm_insn_r
);
12463 /* Move to coprocessor from two arm core registers. */
12465 return arm_record_unsupported_insn (arm_insn_r
);
12467 /* Move to two arm core registers from coprocessor. */
12472 reg_t
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
12473 reg_t
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
12474 arm_insn_r
->reg_rec_count
= 2;
12476 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, reg_t
);
12480 return arm_record_unsupported_insn (arm_insn_r
);
12483 /* Handling opcode 111 insns. */
12486 arm_record_coproc_data_proc (insn_decode_record
*arm_insn_r
)
12488 uint32_t op
, op1_sbit
, op1_ebit
, coproc
;
12489 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arm_insn_r
->gdbarch
);
12490 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
12491 ULONGEST u_regval
= 0;
12493 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 24, 27);
12494 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
12495 op1_sbit
= bit (arm_insn_r
->arm_insn
, 24);
12496 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
12497 op
= bit (arm_insn_r
->arm_insn
, 4);
12499 /* Handle arm SWI/SVC system call instructions. */
12502 if (tdep
->arm_syscall_record
!= NULL
)
12504 ULONGEST svc_operand
, svc_number
;
12506 svc_operand
= (0x00ffffff & arm_insn_r
->arm_insn
);
12508 if (svc_operand
) /* OABI. */
12509 svc_number
= svc_operand
- 0x900000;
12511 regcache_raw_read_unsigned (reg_cache
, 7, &svc_number
);
12513 return tdep
->arm_syscall_record (reg_cache
, svc_number
);
12517 printf_unfiltered (_("no syscall record support\n"));
12522 if ((coproc
& 0x0e) == 0x0a)
12524 /* VFP data-processing instructions. */
12525 if (!op1_sbit
&& !op
)
12526 return arm_record_vfp_data_proc_insn (arm_insn_r
);
12528 /* Advanced SIMD, VFP instructions. */
12529 if (!op1_sbit
&& op
)
12530 return arm_record_vdata_transfer_insn (arm_insn_r
);
12534 /* Coprocessor data operations. */
12535 if (!op1_sbit
&& !op
)
12536 return arm_record_unsupported_insn (arm_insn_r
);
12538 /* Move to Coprocessor from ARM core register. */
12539 if (!op1_sbit
&& !op1_ebit
&& op
)
12540 return arm_record_unsupported_insn (arm_insn_r
);
12542 /* Move to arm core register from coprocessor. */
12543 if (!op1_sbit
&& op1_ebit
&& op
)
12545 uint32_t record_buf
[1];
12547 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
12548 if (record_buf
[0] == 15)
12549 record_buf
[0] = ARM_PS_REGNUM
;
12551 arm_insn_r
->reg_rec_count
= 1;
12552 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
,
12558 return arm_record_unsupported_insn (arm_insn_r
);
12561 /* Handling opcode 000 insns. */
12564 thumb_record_shift_add_sub (insn_decode_record
*thumb_insn_r
)
12566 uint32_t record_buf
[8];
12567 uint32_t reg_src1
= 0;
12569 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12571 record_buf
[0] = ARM_PS_REGNUM
;
12572 record_buf
[1] = reg_src1
;
12573 thumb_insn_r
->reg_rec_count
= 2;
12575 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12581 /* Handling opcode 001 insns. */
12584 thumb_record_add_sub_cmp_mov (insn_decode_record
*thumb_insn_r
)
12586 uint32_t record_buf
[8];
12587 uint32_t reg_src1
= 0;
12589 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12591 record_buf
[0] = ARM_PS_REGNUM
;
12592 record_buf
[1] = reg_src1
;
12593 thumb_insn_r
->reg_rec_count
= 2;
12595 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12600 /* Handling opcode 010 insns. */
12603 thumb_record_ld_st_reg_offset (insn_decode_record
*thumb_insn_r
)
12605 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12606 uint32_t record_buf
[8], record_buf_mem
[8];
12608 uint32_t reg_src1
= 0, reg_src2
= 0;
12609 uint32_t opcode1
= 0, opcode2
= 0, opcode3
= 0;
12611 ULONGEST u_regval
[2] = {0};
12613 opcode1
= bits (thumb_insn_r
->arm_insn
, 10, 12);
12615 if (bit (thumb_insn_r
->arm_insn
, 12))
12617 /* Handle load/store register offset. */
12618 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 10);
12619 if (opcode2
>= 12 && opcode2
<= 15)
12621 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
12622 reg_src1
= bits (thumb_insn_r
->arm_insn
,0, 2);
12623 record_buf
[0] = reg_src1
;
12624 thumb_insn_r
->reg_rec_count
= 1;
12626 else if (opcode2
>= 8 && opcode2
<= 10)
12628 /* STR(2), STRB(2), STRH(2) . */
12629 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12630 reg_src2
= bits (thumb_insn_r
->arm_insn
, 6, 8);
12631 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
12632 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
12634 record_buf_mem
[0] = 4; /* STR (2). */
12635 else if (10 == opcode2
)
12636 record_buf_mem
[0] = 1; /* STRB (2). */
12637 else if (9 == opcode2
)
12638 record_buf_mem
[0] = 2; /* STRH (2). */
12639 record_buf_mem
[1] = u_regval
[0] + u_regval
[1];
12640 thumb_insn_r
->mem_rec_count
= 1;
12643 else if (bit (thumb_insn_r
->arm_insn
, 11))
12645 /* Handle load from literal pool. */
12647 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12648 record_buf
[0] = reg_src1
;
12649 thumb_insn_r
->reg_rec_count
= 1;
12653 opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 9);
12654 opcode3
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12655 if ((3 == opcode2
) && (!opcode3
))
12657 /* Branch with exchange. */
12658 record_buf
[0] = ARM_PS_REGNUM
;
12659 thumb_insn_r
->reg_rec_count
= 1;
12663 /* Format 8; special data processing insns. */
12664 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12665 record_buf
[0] = ARM_PS_REGNUM
;
12666 record_buf
[1] = reg_src1
;
12667 thumb_insn_r
->reg_rec_count
= 2;
12672 /* Format 5; data processing insns. */
12673 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12674 if (bit (thumb_insn_r
->arm_insn
, 7))
12676 reg_src1
= reg_src1
+ 8;
12678 record_buf
[0] = ARM_PS_REGNUM
;
12679 record_buf
[1] = reg_src1
;
12680 thumb_insn_r
->reg_rec_count
= 2;
12683 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12684 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12690 /* Handling opcode 001 insns. */
12693 thumb_record_ld_st_imm_offset (insn_decode_record
*thumb_insn_r
)
12695 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12696 uint32_t record_buf
[8], record_buf_mem
[8];
12698 uint32_t reg_src1
= 0;
12699 uint32_t opcode
= 0, immed_5
= 0;
12701 ULONGEST u_regval
= 0;
12703 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12708 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12709 record_buf
[0] = reg_src1
;
12710 thumb_insn_r
->reg_rec_count
= 1;
12715 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12716 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
12717 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12718 record_buf_mem
[0] = 4;
12719 record_buf_mem
[1] = u_regval
+ (immed_5
* 4);
12720 thumb_insn_r
->mem_rec_count
= 1;
12723 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12724 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12730 /* Handling opcode 100 insns. */
12733 thumb_record_ld_st_stack (insn_decode_record
*thumb_insn_r
)
12735 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12736 uint32_t record_buf
[8], record_buf_mem
[8];
12738 uint32_t reg_src1
= 0;
12739 uint32_t opcode
= 0, immed_8
= 0, immed_5
= 0;
12741 ULONGEST u_regval
= 0;
12743 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12748 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12749 record_buf
[0] = reg_src1
;
12750 thumb_insn_r
->reg_rec_count
= 1;
12752 else if (1 == opcode
)
12755 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12756 record_buf
[0] = reg_src1
;
12757 thumb_insn_r
->reg_rec_count
= 1;
12759 else if (2 == opcode
)
12762 immed_8
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12763 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
12764 record_buf_mem
[0] = 4;
12765 record_buf_mem
[1] = u_regval
+ (immed_8
* 4);
12766 thumb_insn_r
->mem_rec_count
= 1;
12768 else if (0 == opcode
)
12771 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
12772 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12773 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12774 record_buf_mem
[0] = 2;
12775 record_buf_mem
[1] = u_regval
+ (immed_5
* 2);
12776 thumb_insn_r
->mem_rec_count
= 1;
12779 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12780 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12786 /* Handling opcode 101 insns. */
12789 thumb_record_misc (insn_decode_record
*thumb_insn_r
)
12791 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12793 uint32_t opcode
= 0, opcode1
= 0, opcode2
= 0;
12794 uint32_t register_bits
= 0, register_count
= 0;
12795 uint32_t register_list
[8] = {0}, index
= 0, start_address
= 0;
12796 uint32_t record_buf
[24], record_buf_mem
[48];
12799 ULONGEST u_regval
= 0;
12801 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12802 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12803 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 12);
12808 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12809 while (register_bits
)
12811 if (register_bits
& 0x00000001)
12812 record_buf
[index
++] = register_count
;
12813 register_bits
= register_bits
>> 1;
12816 record_buf
[index
++] = ARM_PS_REGNUM
;
12817 record_buf
[index
++] = ARM_SP_REGNUM
;
12818 thumb_insn_r
->reg_rec_count
= index
;
12820 else if (10 == opcode2
)
12823 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12824 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
12825 while (register_bits
)
12827 if (register_bits
& 0x00000001)
12829 register_bits
= register_bits
>> 1;
12831 start_address
= u_regval
- \
12832 (4 * (bit (thumb_insn_r
->arm_insn
, 8) + register_count
));
12833 thumb_insn_r
->mem_rec_count
= register_count
;
12834 while (register_count
)
12836 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12837 record_buf_mem
[(register_count
* 2) - 2] = 4;
12838 start_address
= start_address
+ 4;
12841 record_buf
[0] = ARM_SP_REGNUM
;
12842 thumb_insn_r
->reg_rec_count
= 1;
12844 else if (0x1E == opcode1
)
12847 /* Handle enhanced software breakpoint insn, BKPT. */
12848 /* CPSR is changed to be executed in ARM state, disabling normal
12849 interrupts, entering abort mode. */
12850 /* According to high vector configuration PC is set. */
12851 /* User hits breakpoint and type reverse, in that case, we need to go back with
12852 previous CPSR and Program Counter. */
12853 record_buf
[0] = ARM_PS_REGNUM
;
12854 record_buf
[1] = ARM_LR_REGNUM
;
12855 thumb_insn_r
->reg_rec_count
= 2;
12856 /* We need to save SPSR value, which is not yet done. */
12857 printf_unfiltered (_("Process record does not support instruction "
12858 "0x%0x at address %s.\n"),
12859 thumb_insn_r
->arm_insn
,
12860 paddress (thumb_insn_r
->gdbarch
,
12861 thumb_insn_r
->this_addr
));
12864 else if ((0 == opcode
) || (1 == opcode
))
12866 /* ADD(5), ADD(6). */
12867 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12868 record_buf
[0] = reg_src1
;
12869 thumb_insn_r
->reg_rec_count
= 1;
12871 else if (2 == opcode
)
12873 /* ADD(7), SUB(4). */
12874 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12875 record_buf
[0] = ARM_SP_REGNUM
;
12876 thumb_insn_r
->reg_rec_count
= 1;
12879 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12880 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12886 /* Handling opcode 110 insns. */
12889 thumb_record_ldm_stm_swi (insn_decode_record
*thumb_insn_r
)
12891 struct gdbarch_tdep
*tdep
= gdbarch_tdep (thumb_insn_r
->gdbarch
);
12892 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12894 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
12895 uint32_t reg_src1
= 0;
12896 uint32_t opcode1
= 0, opcode2
= 0, register_bits
= 0, register_count
= 0;
12897 uint32_t register_list
[8] = {0}, index
= 0, start_address
= 0;
12898 uint32_t record_buf
[24], record_buf_mem
[48];
12900 ULONGEST u_regval
= 0;
12902 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12903 opcode2
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12909 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12911 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12912 while (register_bits
)
12914 if (register_bits
& 0x00000001)
12915 record_buf
[index
++] = register_count
;
12916 register_bits
= register_bits
>> 1;
12919 record_buf
[index
++] = reg_src1
;
12920 thumb_insn_r
->reg_rec_count
= index
;
12922 else if (0 == opcode2
)
12924 /* It handles both STMIA. */
12925 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12927 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12928 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12929 while (register_bits
)
12931 if (register_bits
& 0x00000001)
12933 register_bits
= register_bits
>> 1;
12935 start_address
= u_regval
;
12936 thumb_insn_r
->mem_rec_count
= register_count
;
12937 while (register_count
)
12939 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12940 record_buf_mem
[(register_count
* 2) - 2] = 4;
12941 start_address
= start_address
+ 4;
12945 else if (0x1F == opcode1
)
12947 /* Handle arm syscall insn. */
12948 if (tdep
->arm_syscall_record
!= NULL
)
12950 regcache_raw_read_unsigned (reg_cache
, 7, &u_regval
);
12951 ret
= tdep
->arm_syscall_record (reg_cache
, u_regval
);
12955 printf_unfiltered (_("no syscall record support\n"));
12960 /* B (1), conditional branch is automatically taken care in process_record,
12961 as PC is saved there. */
12963 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12964 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12970 /* Handling opcode 111 insns. */
12973 thumb_record_branch (insn_decode_record
*thumb_insn_r
)
12975 uint32_t record_buf
[8];
12976 uint32_t bits_h
= 0;
12978 bits_h
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12980 if (2 == bits_h
|| 3 == bits_h
)
12983 record_buf
[0] = ARM_LR_REGNUM
;
12984 thumb_insn_r
->reg_rec_count
= 1;
12986 else if (1 == bits_h
)
12989 record_buf
[0] = ARM_PS_REGNUM
;
12990 record_buf
[1] = ARM_LR_REGNUM
;
12991 thumb_insn_r
->reg_rec_count
= 2;
12994 /* B(2) is automatically taken care in process_record, as PC is
12997 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
13002 /* Handler for thumb2 load/store multiple instructions. */
13005 thumb2_record_ld_st_multiple (insn_decode_record
*thumb2_insn_r
)
13007 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13009 uint32_t reg_rn
, op
;
13010 uint32_t register_bits
= 0, register_count
= 0;
13011 uint32_t index
= 0, start_address
= 0;
13012 uint32_t record_buf
[24], record_buf_mem
[48];
13014 ULONGEST u_regval
= 0;
13016 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13017 op
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
13019 if (0 == op
|| 3 == op
)
13021 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
13023 /* Handle RFE instruction. */
13024 record_buf
[0] = ARM_PS_REGNUM
;
13025 thumb2_insn_r
->reg_rec_count
= 1;
13029 /* Handle SRS instruction after reading banked SP. */
13030 return arm_record_unsupported_insn (thumb2_insn_r
);
13033 else if (1 == op
|| 2 == op
)
13035 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
13037 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
13038 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
13039 while (register_bits
)
13041 if (register_bits
& 0x00000001)
13042 record_buf
[index
++] = register_count
;
13045 register_bits
= register_bits
>> 1;
13047 record_buf
[index
++] = reg_rn
;
13048 record_buf
[index
++] = ARM_PS_REGNUM
;
13049 thumb2_insn_r
->reg_rec_count
= index
;
13053 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
13054 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
13055 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
13056 while (register_bits
)
13058 if (register_bits
& 0x00000001)
13061 register_bits
= register_bits
>> 1;
13066 /* Start address calculation for LDMDB/LDMEA. */
13067 start_address
= u_regval
;
13071 /* Start address calculation for LDMDB/LDMEA. */
13072 start_address
= u_regval
- register_count
* 4;
13075 thumb2_insn_r
->mem_rec_count
= register_count
;
13076 while (register_count
)
13078 record_buf_mem
[register_count
* 2 - 1] = start_address
;
13079 record_buf_mem
[register_count
* 2 - 2] = 4;
13080 start_address
= start_address
+ 4;
13083 record_buf
[0] = reg_rn
;
13084 record_buf
[1] = ARM_PS_REGNUM
;
13085 thumb2_insn_r
->reg_rec_count
= 2;
13089 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13091 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13093 return ARM_RECORD_SUCCESS
;
13096 /* Handler for thumb2 load/store (dual/exclusive) and table branch
13100 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record
*thumb2_insn_r
)
13102 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13104 uint32_t reg_rd
, reg_rn
, offset_imm
;
13105 uint32_t reg_dest1
, reg_dest2
;
13106 uint32_t address
, offset_addr
;
13107 uint32_t record_buf
[8], record_buf_mem
[8];
13108 uint32_t op1
, op2
, op3
;
13111 ULONGEST u_regval
[2];
13113 op1
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
13114 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 21);
13115 op3
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
13117 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
13119 if(!(1 == op1
&& 1 == op2
&& (0 == op3
|| 1 == op3
)))
13121 reg_dest1
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
13122 record_buf
[0] = reg_dest1
;
13123 record_buf
[1] = ARM_PS_REGNUM
;
13124 thumb2_insn_r
->reg_rec_count
= 2;
13127 if (3 == op2
|| (op1
& 2) || (1 == op1
&& 1 == op2
&& 7 == op3
))
13129 reg_dest2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13130 record_buf
[2] = reg_dest2
;
13131 thumb2_insn_r
->reg_rec_count
= 3;
13136 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13137 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
13139 if (0 == op1
&& 0 == op2
)
13141 /* Handle STREX. */
13142 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
13143 address
= u_regval
[0] + (offset_imm
* 4);
13144 record_buf_mem
[0] = 4;
13145 record_buf_mem
[1] = address
;
13146 thumb2_insn_r
->mem_rec_count
= 1;
13147 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
13148 record_buf
[0] = reg_rd
;
13149 thumb2_insn_r
->reg_rec_count
= 1;
13151 else if (1 == op1
&& 0 == op2
)
13153 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
13154 record_buf
[0] = reg_rd
;
13155 thumb2_insn_r
->reg_rec_count
= 1;
13156 address
= u_regval
[0];
13157 record_buf_mem
[1] = address
;
13161 /* Handle STREXB. */
13162 record_buf_mem
[0] = 1;
13163 thumb2_insn_r
->mem_rec_count
= 1;
13167 /* Handle STREXH. */
13168 record_buf_mem
[0] = 2 ;
13169 thumb2_insn_r
->mem_rec_count
= 1;
13173 /* Handle STREXD. */
13174 address
= u_regval
[0];
13175 record_buf_mem
[0] = 4;
13176 record_buf_mem
[2] = 4;
13177 record_buf_mem
[3] = address
+ 4;
13178 thumb2_insn_r
->mem_rec_count
= 2;
13183 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
13185 if (bit (thumb2_insn_r
->arm_insn
, 24))
13187 if (bit (thumb2_insn_r
->arm_insn
, 23))
13188 offset_addr
= u_regval
[0] + (offset_imm
* 4);
13190 offset_addr
= u_regval
[0] - (offset_imm
* 4);
13192 address
= offset_addr
;
13195 address
= u_regval
[0];
13197 record_buf_mem
[0] = 4;
13198 record_buf_mem
[1] = address
;
13199 record_buf_mem
[2] = 4;
13200 record_buf_mem
[3] = address
+ 4;
13201 thumb2_insn_r
->mem_rec_count
= 2;
13202 record_buf
[0] = reg_rn
;
13203 thumb2_insn_r
->reg_rec_count
= 1;
13207 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13209 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13211 return ARM_RECORD_SUCCESS
;
13214 /* Handler for thumb2 data processing (shift register and modified immediate)
13218 thumb2_record_data_proc_sreg_mimm (insn_decode_record
*thumb2_insn_r
)
13220 uint32_t reg_rd
, op
;
13221 uint32_t record_buf
[8];
13223 op
= bits (thumb2_insn_r
->arm_insn
, 21, 24);
13224 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13226 if ((0 == op
|| 4 == op
|| 8 == op
|| 13 == op
) && 15 == reg_rd
)
13228 record_buf
[0] = ARM_PS_REGNUM
;
13229 thumb2_insn_r
->reg_rec_count
= 1;
13233 record_buf
[0] = reg_rd
;
13234 record_buf
[1] = ARM_PS_REGNUM
;
13235 thumb2_insn_r
->reg_rec_count
= 2;
13238 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13240 return ARM_RECORD_SUCCESS
;
13243 /* Generic handler for thumb2 instructions which effect destination and PS
13247 thumb2_record_ps_dest_generic (insn_decode_record
*thumb2_insn_r
)
13250 uint32_t record_buf
[8];
13252 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13254 record_buf
[0] = reg_rd
;
13255 record_buf
[1] = ARM_PS_REGNUM
;
13256 thumb2_insn_r
->reg_rec_count
= 2;
13258 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13260 return ARM_RECORD_SUCCESS
;
13263 /* Handler for thumb2 branch and miscellaneous control instructions. */
13266 thumb2_record_branch_misc_cntrl (insn_decode_record
*thumb2_insn_r
)
13268 uint32_t op
, op1
, op2
;
13269 uint32_t record_buf
[8];
13271 op
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
13272 op1
= bits (thumb2_insn_r
->arm_insn
, 12, 14);
13273 op2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13275 /* Handle MSR insn. */
13276 if (!(op1
& 0x2) && 0x38 == op
)
13280 /* CPSR is going to be changed. */
13281 record_buf
[0] = ARM_PS_REGNUM
;
13282 thumb2_insn_r
->reg_rec_count
= 1;
13286 arm_record_unsupported_insn(thumb2_insn_r
);
13290 else if (4 == (op1
& 0x5) || 5 == (op1
& 0x5))
13293 record_buf
[0] = ARM_PS_REGNUM
;
13294 record_buf
[1] = ARM_LR_REGNUM
;
13295 thumb2_insn_r
->reg_rec_count
= 2;
13298 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13300 return ARM_RECORD_SUCCESS
;
13303 /* Handler for thumb2 store single data item instructions. */
13306 thumb2_record_str_single_data (insn_decode_record
*thumb2_insn_r
)
13308 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13310 uint32_t reg_rn
, reg_rm
, offset_imm
, shift_imm
;
13311 uint32_t address
, offset_addr
;
13312 uint32_t record_buf
[8], record_buf_mem
[8];
13315 ULONGEST u_regval
[2];
13317 op1
= bits (thumb2_insn_r
->arm_insn
, 21, 23);
13318 op2
= bits (thumb2_insn_r
->arm_insn
, 6, 11);
13319 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13320 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
13322 if (bit (thumb2_insn_r
->arm_insn
, 23))
13325 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 11);
13326 offset_addr
= u_regval
[0] + offset_imm
;
13327 address
= offset_addr
;
13332 if ((0 == op1
|| 1 == op1
|| 2 == op1
) && !(op2
& 0x20))
13334 /* Handle STRB (register). */
13335 reg_rm
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
13336 regcache_raw_read_unsigned (reg_cache
, reg_rm
, &u_regval
[1]);
13337 shift_imm
= bits (thumb2_insn_r
->arm_insn
, 4, 5);
13338 offset_addr
= u_regval
[1] << shift_imm
;
13339 address
= u_regval
[0] + offset_addr
;
13343 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
13344 if (bit (thumb2_insn_r
->arm_insn
, 10))
13346 if (bit (thumb2_insn_r
->arm_insn
, 9))
13347 offset_addr
= u_regval
[0] + offset_imm
;
13349 offset_addr
= u_regval
[0] - offset_imm
;
13351 address
= offset_addr
;
13354 address
= u_regval
[0];
13360 /* Store byte instructions. */
13363 record_buf_mem
[0] = 1;
13365 /* Store half word instructions. */
13368 record_buf_mem
[0] = 2;
13370 /* Store word instructions. */
13373 record_buf_mem
[0] = 4;
13377 gdb_assert_not_reached ("no decoding pattern found");
13381 record_buf_mem
[1] = address
;
13382 thumb2_insn_r
->mem_rec_count
= 1;
13383 record_buf
[0] = reg_rn
;
13384 thumb2_insn_r
->reg_rec_count
= 1;
13386 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13388 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13390 return ARM_RECORD_SUCCESS
;
13393 /* Handler for thumb2 load memory hints instructions. */
13396 thumb2_record_ld_mem_hints (insn_decode_record
*thumb2_insn_r
)
13398 uint32_t record_buf
[8];
13399 uint32_t reg_rt
, reg_rn
;
13401 reg_rt
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
13402 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13404 if (ARM_PC_REGNUM
!= reg_rt
)
13406 record_buf
[0] = reg_rt
;
13407 record_buf
[1] = reg_rn
;
13408 record_buf
[2] = ARM_PS_REGNUM
;
13409 thumb2_insn_r
->reg_rec_count
= 3;
13411 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13413 return ARM_RECORD_SUCCESS
;
13416 return ARM_RECORD_FAILURE
;
13419 /* Handler for thumb2 load word instructions. */
13422 thumb2_record_ld_word (insn_decode_record
*thumb2_insn_r
)
13424 uint32_t opcode1
= 0, opcode2
= 0;
13425 uint32_t record_buf
[8];
13427 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
13428 record_buf
[1] = ARM_PS_REGNUM
;
13429 thumb2_insn_r
->reg_rec_count
= 2;
13431 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13433 return ARM_RECORD_SUCCESS
;
13436 /* Handler for thumb2 long multiply, long multiply accumulate, and
13437 divide instructions. */
13440 thumb2_record_lmul_lmla_div (insn_decode_record
*thumb2_insn_r
)
13442 uint32_t opcode1
= 0, opcode2
= 0;
13443 uint32_t record_buf
[8];
13444 uint32_t reg_src1
= 0;
13446 opcode1
= bits (thumb2_insn_r
->arm_insn
, 20, 22);
13447 opcode2
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
13449 if (0 == opcode1
|| 2 == opcode1
|| (opcode1
>= 4 && opcode1
<= 6))
13451 /* Handle SMULL, UMULL, SMULAL. */
13452 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
13453 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
13454 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
13455 record_buf
[2] = ARM_PS_REGNUM
;
13456 thumb2_insn_r
->reg_rec_count
= 3;
13458 else if (1 == opcode1
|| 3 == opcode2
)
13460 /* Handle SDIV and UDIV. */
13461 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
13462 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
13463 record_buf
[2] = ARM_PS_REGNUM
;
13464 thumb2_insn_r
->reg_rec_count
= 3;
13467 return ARM_RECORD_FAILURE
;
13469 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13471 return ARM_RECORD_SUCCESS
;
13474 /* Record handler for thumb32 coprocessor instructions. */
13477 thumb2_record_coproc_insn (insn_decode_record
*thumb2_insn_r
)
13479 if (bit (thumb2_insn_r
->arm_insn
, 25))
13480 return arm_record_coproc_data_proc (thumb2_insn_r
);
13482 return arm_record_asimd_vfp_coproc (thumb2_insn_r
);
13485 /* Record handler for advance SIMD structure load/store instructions. */
13488 thumb2_record_asimd_struct_ld_st (insn_decode_record
*thumb2_insn_r
)
13490 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13491 uint32_t l_bit
, a_bit
, b_bits
;
13492 uint32_t record_buf
[128], record_buf_mem
[128];
13493 uint32_t reg_rn
, reg_vd
, address
, f_esize
, f_elem
;
13494 uint32_t index_r
= 0, index_e
= 0, bf_regs
= 0, index_m
= 0, loop_t
= 0;
13497 l_bit
= bit (thumb2_insn_r
->arm_insn
, 21);
13498 a_bit
= bit (thumb2_insn_r
->arm_insn
, 23);
13499 b_bits
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13500 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13501 reg_vd
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
13502 reg_vd
= (bit (thumb2_insn_r
->arm_insn
, 22) << 4) | reg_vd
;
13503 f_ebytes
= (1 << bits (thumb2_insn_r
->arm_insn
, 6, 7));
13504 f_esize
= 8 * f_ebytes
;
13505 f_elem
= 8 / f_ebytes
;
13509 ULONGEST u_regval
= 0;
13510 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
13511 address
= u_regval
;
13516 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
13518 if (b_bits
== 0x07)
13520 else if (b_bits
== 0x0a)
13522 else if (b_bits
== 0x06)
13524 else if (b_bits
== 0x02)
13529 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
13531 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13533 record_buf_mem
[index_m
++] = f_ebytes
;
13534 record_buf_mem
[index_m
++] = address
;
13535 address
= address
+ f_ebytes
;
13536 thumb2_insn_r
->mem_rec_count
+= 1;
13541 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
13543 if (b_bits
== 0x09 || b_bits
== 0x08)
13545 else if (b_bits
== 0x03)
13550 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
13551 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13553 for (loop_t
= 0; loop_t
< 2; loop_t
++)
13555 record_buf_mem
[index_m
++] = f_ebytes
;
13556 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
13557 thumb2_insn_r
->mem_rec_count
+= 1;
13559 address
= address
+ (2 * f_ebytes
);
13563 else if ((b_bits
& 0x0e) == 0x04)
13565 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13567 for (loop_t
= 0; loop_t
< 3; loop_t
++)
13569 record_buf_mem
[index_m
++] = f_ebytes
;
13570 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
13571 thumb2_insn_r
->mem_rec_count
+= 1;
13573 address
= address
+ (3 * f_ebytes
);
13577 else if (!(b_bits
& 0x0e))
13579 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13581 for (loop_t
= 0; loop_t
< 4; loop_t
++)
13583 record_buf_mem
[index_m
++] = f_ebytes
;
13584 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
13585 thumb2_insn_r
->mem_rec_count
+= 1;
13587 address
= address
+ (4 * f_ebytes
);
13593 uint8_t bft_size
= bits (thumb2_insn_r
->arm_insn
, 10, 11);
13595 if (bft_size
== 0x00)
13597 else if (bft_size
== 0x01)
13599 else if (bft_size
== 0x02)
13605 if (!(b_bits
& 0x0b) || b_bits
== 0x08)
13606 thumb2_insn_r
->mem_rec_count
= 1;
13608 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09)
13609 thumb2_insn_r
->mem_rec_count
= 2;
13611 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a)
13612 thumb2_insn_r
->mem_rec_count
= 3;
13614 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b)
13615 thumb2_insn_r
->mem_rec_count
= 4;
13617 for (index_m
= 0; index_m
< thumb2_insn_r
->mem_rec_count
; index_m
++)
13619 record_buf_mem
[index_m
] = f_ebytes
;
13620 record_buf_mem
[index_m
] = address
+ (index_m
* f_ebytes
);
13629 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
13630 thumb2_insn_r
->reg_rec_count
= 1;
13632 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
13633 thumb2_insn_r
->reg_rec_count
= 2;
13635 else if ((b_bits
& 0x0e) == 0x04)
13636 thumb2_insn_r
->reg_rec_count
= 3;
13638 else if (!(b_bits
& 0x0e))
13639 thumb2_insn_r
->reg_rec_count
= 4;
13644 if (!(b_bits
& 0x0b) || b_bits
== 0x08 || b_bits
== 0x0c)
13645 thumb2_insn_r
->reg_rec_count
= 1;
13647 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09 || b_bits
== 0x0d)
13648 thumb2_insn_r
->reg_rec_count
= 2;
13650 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a || b_bits
== 0x0e)
13651 thumb2_insn_r
->reg_rec_count
= 3;
13653 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b || b_bits
== 0x0f)
13654 thumb2_insn_r
->reg_rec_count
= 4;
13656 for (index_r
= 0; index_r
< thumb2_insn_r
->reg_rec_count
; index_r
++)
13657 record_buf
[index_r
] = reg_vd
+ ARM_D0_REGNUM
+ index_r
;
13661 if (bits (thumb2_insn_r
->arm_insn
, 0, 3) != 15)
13663 record_buf
[index_r
] = reg_rn
;
13664 thumb2_insn_r
->reg_rec_count
+= 1;
13667 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13669 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13674 /* Decodes thumb2 instruction type and invokes its record handler. */
13676 static unsigned int
13677 thumb2_record_decode_insn_handler (insn_decode_record
*thumb2_insn_r
)
13679 uint32_t op
, op1
, op2
;
13681 op
= bit (thumb2_insn_r
->arm_insn
, 15);
13682 op1
= bits (thumb2_insn_r
->arm_insn
, 27, 28);
13683 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
13687 if (!(op2
& 0x64 ))
13689 /* Load/store multiple instruction. */
13690 return thumb2_record_ld_st_multiple (thumb2_insn_r
);
13692 else if (!((op2
& 0x64) ^ 0x04))
13694 /* Load/store (dual/exclusive) and table branch instruction. */
13695 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r
);
13697 else if (!((op2
& 0x20) ^ 0x20))
13699 /* Data-processing (shifted register). */
13700 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
13702 else if (op2
& 0x40)
13704 /* Co-processor instructions. */
13705 return thumb2_record_coproc_insn (thumb2_insn_r
);
13708 else if (op1
== 0x02)
13712 /* Branches and miscellaneous control instructions. */
13713 return thumb2_record_branch_misc_cntrl (thumb2_insn_r
);
13715 else if (op2
& 0x20)
13717 /* Data-processing (plain binary immediate) instruction. */
13718 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
13722 /* Data-processing (modified immediate). */
13723 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
13726 else if (op1
== 0x03)
13728 if (!(op2
& 0x71 ))
13730 /* Store single data item. */
13731 return thumb2_record_str_single_data (thumb2_insn_r
);
13733 else if (!((op2
& 0x71) ^ 0x10))
13735 /* Advanced SIMD or structure load/store instructions. */
13736 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r
);
13738 else if (!((op2
& 0x67) ^ 0x01))
13740 /* Load byte, memory hints instruction. */
13741 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
13743 else if (!((op2
& 0x67) ^ 0x03))
13745 /* Load halfword, memory hints instruction. */
13746 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
13748 else if (!((op2
& 0x67) ^ 0x05))
13750 /* Load word instruction. */
13751 return thumb2_record_ld_word (thumb2_insn_r
);
13753 else if (!((op2
& 0x70) ^ 0x20))
13755 /* Data-processing (register) instruction. */
13756 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
13758 else if (!((op2
& 0x78) ^ 0x30))
13760 /* Multiply, multiply accumulate, abs diff instruction. */
13761 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
13763 else if (!((op2
& 0x78) ^ 0x38))
13765 /* Long multiply, long multiply accumulate, and divide. */
13766 return thumb2_record_lmul_lmla_div (thumb2_insn_r
);
13768 else if (op2
& 0x40)
13770 /* Co-processor instructions. */
13771 return thumb2_record_coproc_insn (thumb2_insn_r
);
13778 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
13779 and positive val on fauilure. */
13782 extract_arm_insn (insn_decode_record
*insn_record
, uint32_t insn_size
)
13784 gdb_byte buf
[insn_size
];
13786 memset (&buf
[0], 0, insn_size
);
13788 if (target_read_memory (insn_record
->this_addr
, &buf
[0], insn_size
))
13790 insn_record
->arm_insn
= (uint32_t) extract_unsigned_integer (&buf
[0],
13792 gdbarch_byte_order_for_code (insn_record
->gdbarch
));
13796 typedef int (*sti_arm_hdl_fp_t
) (insn_decode_record
*);
13798 /* Decode arm/thumb insn depending on condition cods and opcodes; and
13802 decode_insn (insn_decode_record
*arm_record
, record_type_t record_type
,
13803 uint32_t insn_size
)
13806 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */
13807 static const sti_arm_hdl_fp_t arm_handle_insn
[8] =
13809 arm_record_data_proc_misc_ld_str
, /* 000. */
13810 arm_record_data_proc_imm
, /* 001. */
13811 arm_record_ld_st_imm_offset
, /* 010. */
13812 arm_record_ld_st_reg_offset
, /* 011. */
13813 arm_record_ld_st_multiple
, /* 100. */
13814 arm_record_b_bl
, /* 101. */
13815 arm_record_asimd_vfp_coproc
, /* 110. */
13816 arm_record_coproc_data_proc
/* 111. */
13819 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */
13820 static const sti_arm_hdl_fp_t thumb_handle_insn
[8] =
13822 thumb_record_shift_add_sub
, /* 000. */
13823 thumb_record_add_sub_cmp_mov
, /* 001. */
13824 thumb_record_ld_st_reg_offset
, /* 010. */
13825 thumb_record_ld_st_imm_offset
, /* 011. */
13826 thumb_record_ld_st_stack
, /* 100. */
13827 thumb_record_misc
, /* 101. */
13828 thumb_record_ldm_stm_swi
, /* 110. */
13829 thumb_record_branch
/* 111. */
13832 uint32_t ret
= 0; /* return value: negative:failure 0:success. */
13833 uint32_t insn_id
= 0;
13835 if (extract_arm_insn (arm_record
, insn_size
))
13839 printf_unfiltered (_("Process record: error reading memory at "
13840 "addr %s len = %d.\n"),
13841 paddress (arm_record
->gdbarch
, arm_record
->this_addr
), insn_size
);
13845 else if (ARM_RECORD
== record_type
)
13847 arm_record
->cond
= bits (arm_record
->arm_insn
, 28, 31);
13848 insn_id
= bits (arm_record
->arm_insn
, 25, 27);
13849 ret
= arm_record_extension_space (arm_record
);
13850 /* If this insn has fallen into extension space
13851 then we need not decode it anymore. */
13852 if (ret
!= -1 && !INSN_RECORDED(arm_record
))
13854 ret
= arm_handle_insn
[insn_id
] (arm_record
);
13857 else if (THUMB_RECORD
== record_type
)
13859 /* As thumb does not have condition codes, we set negative. */
13860 arm_record
->cond
= -1;
13861 insn_id
= bits (arm_record
->arm_insn
, 13, 15);
13862 ret
= thumb_handle_insn
[insn_id
] (arm_record
);
13864 else if (THUMB2_RECORD
== record_type
)
13866 /* As thumb does not have condition codes, we set negative. */
13867 arm_record
->cond
= -1;
13869 /* Swap first half of 32bit thumb instruction with second half. */
13870 arm_record
->arm_insn
13871 = (arm_record
->arm_insn
>> 16) | (arm_record
->arm_insn
<< 16);
13873 insn_id
= thumb2_record_decode_insn_handler (arm_record
);
13875 if (insn_id
!= ARM_RECORD_SUCCESS
)
13877 arm_record_unsupported_insn (arm_record
);
13883 /* Throw assertion. */
13884 gdb_assert_not_reached ("not a valid instruction, could not decode");
13891 /* Cleans up local record registers and memory allocations. */
13894 deallocate_reg_mem (insn_decode_record
*record
)
13896 xfree (record
->arm_regs
);
13897 xfree (record
->arm_mems
);
13901 /* Parse the current instruction and record the values of the registers and
13902 memory that will be changed in current instruction to record_arch_list".
13903 Return -1 if something is wrong. */
13906 arm_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
13907 CORE_ADDR insn_addr
)
13910 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
13911 uint32_t no_of_rec
= 0;
13912 uint32_t ret
= 0; /* return value: -1:record failure ; 0:success */
13913 ULONGEST t_bit
= 0, insn_id
= 0;
13915 ULONGEST u_regval
= 0;
13917 insn_decode_record arm_record
;
13919 memset (&arm_record
, 0, sizeof (insn_decode_record
));
13920 arm_record
.regcache
= regcache
;
13921 arm_record
.this_addr
= insn_addr
;
13922 arm_record
.gdbarch
= gdbarch
;
13925 if (record_debug
> 1)
13927 fprintf_unfiltered (gdb_stdlog
, "Process record: arm_process_record "
13929 paddress (gdbarch
, arm_record
.this_addr
));
13932 if (extract_arm_insn (&arm_record
, 2))
13936 printf_unfiltered (_("Process record: error reading memory at "
13937 "addr %s len = %d.\n"),
13938 paddress (arm_record
.gdbarch
,
13939 arm_record
.this_addr
), 2);
13944 /* Check the insn, whether it is thumb or arm one. */
13946 t_bit
= arm_psr_thumb_bit (arm_record
.gdbarch
);
13947 regcache_raw_read_unsigned (arm_record
.regcache
, ARM_PS_REGNUM
, &u_regval
);
13950 if (!(u_regval
& t_bit
))
13952 /* We are decoding arm insn. */
13953 ret
= decode_insn (&arm_record
, ARM_RECORD
, ARM_INSN_SIZE_BYTES
);
13957 insn_id
= bits (arm_record
.arm_insn
, 11, 15);
13958 /* is it thumb2 insn? */
13959 if ((0x1D == insn_id
) || (0x1E == insn_id
) || (0x1F == insn_id
))
13961 ret
= decode_insn (&arm_record
, THUMB2_RECORD
,
13962 THUMB2_INSN_SIZE_BYTES
);
13966 /* We are decoding thumb insn. */
13967 ret
= decode_insn (&arm_record
, THUMB_RECORD
, THUMB_INSN_SIZE_BYTES
);
13973 /* Record registers. */
13974 record_full_arch_list_add_reg (arm_record
.regcache
, ARM_PC_REGNUM
);
13975 if (arm_record
.arm_regs
)
13977 for (no_of_rec
= 0; no_of_rec
< arm_record
.reg_rec_count
; no_of_rec
++)
13979 if (record_full_arch_list_add_reg
13980 (arm_record
.regcache
, arm_record
.arm_regs
[no_of_rec
]))
13984 /* Record memories. */
13985 if (arm_record
.arm_mems
)
13987 for (no_of_rec
= 0; no_of_rec
< arm_record
.mem_rec_count
; no_of_rec
++)
13989 if (record_full_arch_list_add_mem
13990 ((CORE_ADDR
)arm_record
.arm_mems
[no_of_rec
].addr
,
13991 arm_record
.arm_mems
[no_of_rec
].len
))
13996 if (record_full_arch_list_add_end ())
14001 deallocate_reg_mem (&arm_record
);