1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
31 #include "reggroups.h"
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "arch/arm-get-next-pcs.h"
51 #include "gdb/sim-arm.h"
54 #include "coff/internal.h"
60 #include "record-full.h"
63 #include "features/arm/arm-with-m.c"
64 #include "features/arm/arm-with-m-fpa-layout.c"
65 #include "features/arm/arm-with-m-vfp-d16.c"
66 #include "features/arm/arm-with-iwmmxt.c"
67 #include "features/arm/arm-with-vfpv2.c"
68 #include "features/arm/arm-with-vfpv3.c"
69 #include "features/arm/arm-with-neon.c"
73 /* Macros for setting and testing a bit in a minimal symbol that marks
74 it as Thumb function. The MSB of the minimal symbol's "info" field
75 is used for this purpose.
77 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
78 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
80 #define MSYMBOL_SET_SPECIAL(msym) \
81 MSYMBOL_TARGET_FLAG_1 (msym) = 1
83 #define MSYMBOL_IS_SPECIAL(msym) \
84 MSYMBOL_TARGET_FLAG_1 (msym)
86 /* Per-objfile data used for mapping symbols. */
87 static const struct objfile_data
*arm_objfile_data_key
;
89 struct arm_mapping_symbol
94 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
95 DEF_VEC_O(arm_mapping_symbol_s
);
97 struct arm_per_objfile
99 VEC(arm_mapping_symbol_s
) **section_maps
;
102 /* The list of available "set arm ..." and "show arm ..." commands. */
103 static struct cmd_list_element
*setarmcmdlist
= NULL
;
104 static struct cmd_list_element
*showarmcmdlist
= NULL
;
106 /* The type of floating-point to use. Keep this in sync with enum
107 arm_float_model, and the help string in _initialize_arm_tdep. */
108 static const char *const fp_model_strings
[] =
118 /* A variable that can be configured by the user. */
119 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
120 static const char *current_fp_model
= "auto";
122 /* The ABI to use. Keep this in sync with arm_abi_kind. */
123 static const char *const arm_abi_strings
[] =
131 /* A variable that can be configured by the user. */
132 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
133 static const char *arm_abi_string
= "auto";
135 /* The execution mode to assume. */
136 static const char *const arm_mode_strings
[] =
144 static const char *arm_fallback_mode_string
= "auto";
145 static const char *arm_force_mode_string
= "auto";
147 /* Number of different reg name sets (options). */
148 static int num_disassembly_options
;
150 /* The standard register names, and all the valid aliases for them. Note
151 that `fp', `sp' and `pc' are not added in this alias list, because they
152 have been added as builtin user registers in
153 std-regs.c:_initialize_frame_reg. */
158 } arm_register_aliases
[] = {
159 /* Basic register numbers. */
176 /* Synonyms (argument and variable registers). */
189 /* Other platform-specific names for r9. */
195 /* Names used by GCC (not listed in the ARM EABI). */
197 /* A special name from the older ATPCS. */
201 static const char *const arm_register_names
[] =
202 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
203 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
204 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
205 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
206 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
207 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
208 "fps", "cpsr" }; /* 24 25 */
210 /* Valid register name styles. */
211 static const char **valid_disassembly_styles
;
213 /* Disassembly style to use. Default to "std" register names. */
214 static const char *disassembly_style
;
216 /* This is used to keep the bfd arch_info in sync with the disassembly
218 static void set_disassembly_style_sfunc(char *, int,
219 struct cmd_list_element
*);
220 static void set_disassembly_style (void);
222 static void convert_from_extended (const struct floatformat
*, const void *,
224 static void convert_to_extended (const struct floatformat
*, void *,
227 static enum register_status
arm_neon_quad_read (struct gdbarch
*gdbarch
,
228 struct regcache
*regcache
,
229 int regnum
, gdb_byte
*buf
);
230 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
231 struct regcache
*regcache
,
232 int regnum
, const gdb_byte
*buf
);
235 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
);
238 /* get_next_pcs operations. */
239 static struct arm_get_next_pcs_ops arm_get_next_pcs_ops
= {
240 arm_get_next_pcs_read_memory_unsigned_integer
,
241 arm_get_next_pcs_syscall_next_pc
,
242 arm_get_next_pcs_addr_bits_remove
,
243 arm_get_next_pcs_is_thumb
,
247 struct arm_prologue_cache
249 /* The stack pointer at the time this frame was created; i.e. the
250 caller's stack pointer when this function was called. It is used
251 to identify this frame. */
254 /* The frame base for this frame is just prev_sp - frame size.
255 FRAMESIZE is the distance from the frame pointer to the
256 initial stack pointer. */
260 /* The register used to hold the frame pointer for this frame. */
263 /* Saved register offsets. */
264 struct trad_frame_saved_reg
*saved_regs
;
267 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
268 CORE_ADDR prologue_start
,
269 CORE_ADDR prologue_end
,
270 struct arm_prologue_cache
*cache
);
272 /* Architecture version for displaced stepping. This effects the behaviour of
273 certain instructions, and really should not be hard-wired. */
275 #define DISPLACED_STEPPING_ARCH_VERSION 5
277 /* Set to true if the 32-bit mode is in use. */
281 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
284 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
286 if (gdbarch_tdep (gdbarch
)->is_m
)
292 /* Determine if the processor is currently executing in Thumb mode. */
295 arm_is_thumb (struct regcache
*regcache
)
298 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regcache
));
300 cpsr
= regcache_raw_get_unsigned (regcache
, ARM_PS_REGNUM
);
302 return (cpsr
& t_bit
) != 0;
305 /* Determine if FRAME is executing in Thumb mode. */
308 arm_frame_is_thumb (struct frame_info
*frame
)
311 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
313 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
314 directly (from a signal frame or dummy frame) or by interpreting
315 the saved LR (from a prologue or DWARF frame). So consult it and
316 trust the unwinders. */
317 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
319 return (cpsr
& t_bit
) != 0;
322 /* Callback for VEC_lower_bound. */
325 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
326 const struct arm_mapping_symbol
*rhs
)
328 return lhs
->value
< rhs
->value
;
331 /* Search for the mapping symbol covering MEMADDR. If one is found,
332 return its type. Otherwise, return 0. If START is non-NULL,
333 set *START to the location of the mapping symbol. */
336 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
338 struct obj_section
*sec
;
340 /* If there are mapping symbols, consult them. */
341 sec
= find_pc_section (memaddr
);
344 struct arm_per_objfile
*data
;
345 VEC(arm_mapping_symbol_s
) *map
;
346 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
350 data
= (struct arm_per_objfile
*) objfile_data (sec
->objfile
,
351 arm_objfile_data_key
);
354 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
355 if (!VEC_empty (arm_mapping_symbol_s
, map
))
357 struct arm_mapping_symbol
*map_sym
;
359 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
360 arm_compare_mapping_symbols
);
362 /* VEC_lower_bound finds the earliest ordered insertion
363 point. If the following symbol starts at this exact
364 address, we use that; otherwise, the preceding
365 mapping symbol covers this address. */
366 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
368 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
369 if (map_sym
->value
== map_key
.value
)
372 *start
= map_sym
->value
+ obj_section_addr (sec
);
373 return map_sym
->type
;
379 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
381 *start
= map_sym
->value
+ obj_section_addr (sec
);
382 return map_sym
->type
;
391 /* Determine if the program counter specified in MEMADDR is in a Thumb
392 function. This function should be called for addresses unrelated to
393 any executing frame; otherwise, prefer arm_frame_is_thumb. */
396 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
398 struct bound_minimal_symbol sym
;
400 struct displaced_step_closure
* dsc
401 = get_displaced_step_closure_by_addr(memaddr
);
403 /* If checking the mode of displaced instruction in copy area, the mode
404 should be determined by instruction on the original address. */
408 fprintf_unfiltered (gdb_stdlog
,
409 "displaced: check mode of %.8lx instead of %.8lx\n",
410 (unsigned long) dsc
->insn_addr
,
411 (unsigned long) memaddr
);
412 memaddr
= dsc
->insn_addr
;
415 /* If bit 0 of the address is set, assume this is a Thumb address. */
416 if (IS_THUMB_ADDR (memaddr
))
419 /* If the user wants to override the symbol table, let him. */
420 if (strcmp (arm_force_mode_string
, "arm") == 0)
422 if (strcmp (arm_force_mode_string
, "thumb") == 0)
425 /* ARM v6-M and v7-M are always in Thumb mode. */
426 if (gdbarch_tdep (gdbarch
)->is_m
)
429 /* If there are mapping symbols, consult them. */
430 type
= arm_find_mapping_symbol (memaddr
, NULL
);
434 /* Thumb functions have a "special" bit set in minimal symbols. */
435 sym
= lookup_minimal_symbol_by_pc (memaddr
);
437 return (MSYMBOL_IS_SPECIAL (sym
.minsym
));
439 /* If the user wants to override the fallback mode, let them. */
440 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
442 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
445 /* If we couldn't find any symbol, but we're talking to a running
446 target, then trust the current value of $cpsr. This lets
447 "display/i $pc" always show the correct mode (though if there is
448 a symbol table we will not reach here, so it still may not be
449 displayed in the mode it will be executed). */
450 if (target_has_registers
)
451 return arm_frame_is_thumb (get_current_frame ());
453 /* Otherwise we're out of luck; we assume ARM. */
457 /* Determine if the address specified equals any of these magic return
458 values, called EXC_RETURN, defined by the ARM v6-M and v7-M
461 From ARMv6-M Reference Manual B1.5.8
462 Table B1-5 Exception return behavior
464 EXC_RETURN Return To Return Stack
465 0xFFFFFFF1 Handler mode Main
466 0xFFFFFFF9 Thread mode Main
467 0xFFFFFFFD Thread mode Process
469 From ARMv7-M Reference Manual B1.5.8
470 Table B1-8 EXC_RETURN definition of exception return behavior, no FP
472 EXC_RETURN Return To Return Stack
473 0xFFFFFFF1 Handler mode Main
474 0xFFFFFFF9 Thread mode Main
475 0xFFFFFFFD Thread mode Process
477 Table B1-9 EXC_RETURN definition of exception return behavior, with
480 EXC_RETURN Return To Return Stack Frame Type
481 0xFFFFFFE1 Handler mode Main Extended
482 0xFFFFFFE9 Thread mode Main Extended
483 0xFFFFFFED Thread mode Process Extended
484 0xFFFFFFF1 Handler mode Main Basic
485 0xFFFFFFF9 Thread mode Main Basic
486 0xFFFFFFFD Thread mode Process Basic
488 For more details see "B1.5.8 Exception return behavior"
489 in both ARMv6-M and ARMv7-M Architecture Reference Manuals. */
492 arm_m_addr_is_magic (CORE_ADDR addr
)
496 /* Values from Tables in B1.5.8 the EXC_RETURN definitions of
497 the exception return behavior. */
504 /* Address is magic. */
508 /* Address is not magic. */
513 /* Remove useless bits from addresses in a running program. */
515 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
517 /* On M-profile devices, do not strip the low bit from EXC_RETURN
518 (the magic exception return address). */
519 if (gdbarch_tdep (gdbarch
)->is_m
520 && arm_m_addr_is_magic (val
))
524 return UNMAKE_THUMB_ADDR (val
);
526 return (val
& 0x03fffffc);
529 /* Return 1 if PC is the start of a compiler helper function which
530 can be safely ignored during prologue skipping. IS_THUMB is true
531 if the function is known to be a Thumb function due to the way it
534 skip_prologue_function (struct gdbarch
*gdbarch
, CORE_ADDR pc
, int is_thumb
)
536 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
537 struct bound_minimal_symbol msym
;
539 msym
= lookup_minimal_symbol_by_pc (pc
);
540 if (msym
.minsym
!= NULL
541 && BMSYMBOL_VALUE_ADDRESS (msym
) == pc
542 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
)
544 const char *name
= MSYMBOL_LINKAGE_NAME (msym
.minsym
);
546 /* The GNU linker's Thumb call stub to foo is named
548 if (strstr (name
, "_from_thumb") != NULL
)
551 /* On soft-float targets, __truncdfsf2 is called to convert promoted
552 arguments to their argument types in non-prototyped
554 if (startswith (name
, "__truncdfsf2"))
556 if (startswith (name
, "__aeabi_d2f"))
559 /* Internal functions related to thread-local storage. */
560 if (startswith (name
, "__tls_get_addr"))
562 if (startswith (name
, "__aeabi_read_tp"))
567 /* If we run against a stripped glibc, we may be unable to identify
568 special functions by name. Check for one important case,
569 __aeabi_read_tp, by comparing the *code* against the default
570 implementation (this is hand-written ARM assembler in glibc). */
573 && read_code_unsigned_integer (pc
, 4, byte_order_for_code
)
574 == 0xe3e00a0f /* mov r0, #0xffff0fff */
575 && read_code_unsigned_integer (pc
+ 4, 4, byte_order_for_code
)
576 == 0xe240f01f) /* sub pc, r0, #31 */
583 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
584 the first 16-bit of instruction, and INSN2 is the second 16-bit of
586 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
587 ((bits ((insn1), 0, 3) << 12) \
588 | (bits ((insn1), 10, 10) << 11) \
589 | (bits ((insn2), 12, 14) << 8) \
590 | bits ((insn2), 0, 7))
592 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
593 the 32-bit instruction. */
594 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
595 ((bits ((insn), 16, 19) << 12) \
596 | bits ((insn), 0, 11))
598 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
601 thumb_expand_immediate (unsigned int imm
)
603 unsigned int count
= imm
>> 7;
611 return (imm
& 0xff) | ((imm
& 0xff) << 16);
613 return ((imm
& 0xff) << 8) | ((imm
& 0xff) << 24);
615 return (imm
& 0xff) | ((imm
& 0xff) << 8)
616 | ((imm
& 0xff) << 16) | ((imm
& 0xff) << 24);
619 return (0x80 | (imm
& 0x7f)) << (32 - count
);
622 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
623 epilogue, 0 otherwise. */
626 thumb_instruction_restores_sp (unsigned short insn
)
628 return (insn
== 0x46bd /* mov sp, r7 */
629 || (insn
& 0xff80) == 0xb000 /* add sp, imm */
630 || (insn
& 0xfe00) == 0xbc00); /* pop <registers> */
633 /* Analyze a Thumb prologue, looking for a recognizable stack frame
634 and frame pointer. Scan until we encounter a store that could
635 clobber the stack frame unexpectedly, or an unknown instruction.
636 Return the last address which is definitely safe to skip for an
637 initial breakpoint. */
640 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
641 CORE_ADDR start
, CORE_ADDR limit
,
642 struct arm_prologue_cache
*cache
)
644 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
645 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
648 struct pv_area
*stack
;
649 struct cleanup
*back_to
;
651 CORE_ADDR unrecognized_pc
= 0;
653 for (i
= 0; i
< 16; i
++)
654 regs
[i
] = pv_register (i
, 0);
655 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
656 back_to
= make_cleanup_free_pv_area (stack
);
658 while (start
< limit
)
662 insn
= read_code_unsigned_integer (start
, 2, byte_order_for_code
);
664 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
669 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
672 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
673 whether to save LR (R14). */
674 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
676 /* Calculate offsets of saved R0-R7 and LR. */
677 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
678 if (mask
& (1 << regno
))
680 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
682 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
685 else if ((insn
& 0xff80) == 0xb080) /* sub sp, #imm */
687 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
688 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
691 else if (thumb_instruction_restores_sp (insn
))
693 /* Don't scan past the epilogue. */
696 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
697 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
699 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
700 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
701 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
703 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
704 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
705 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
707 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
708 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
709 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
710 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
711 regs
[bits (insn
, 6, 8)]);
712 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
713 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
715 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
716 int rm
= bits (insn
, 3, 6);
717 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
719 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
721 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
722 int src_reg
= (insn
& 0x78) >> 3;
723 regs
[dst_reg
] = regs
[src_reg
];
725 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
727 /* Handle stores to the stack. Normally pushes are used,
728 but with GCC -mtpcs-frame, there may be other stores
729 in the prologue to create the frame. */
730 int regno
= (insn
>> 8) & 0x7;
733 offset
= (insn
& 0xff) << 2;
734 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
736 if (pv_area_store_would_trash (stack
, addr
))
739 pv_area_store (stack
, addr
, 4, regs
[regno
]);
741 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
743 int rd
= bits (insn
, 0, 2);
744 int rn
= bits (insn
, 3, 5);
747 offset
= bits (insn
, 6, 10) << 2;
748 addr
= pv_add_constant (regs
[rn
], offset
);
750 if (pv_area_store_would_trash (stack
, addr
))
753 pv_area_store (stack
, addr
, 4, regs
[rd
]);
755 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
756 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
757 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
758 /* Ignore stores of argument registers to the stack. */
760 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
761 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
762 /* Ignore block loads from the stack, potentially copying
763 parameters from memory. */
765 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
766 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
767 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
768 /* Similarly ignore single loads from the stack. */
770 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
771 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
772 /* Skip register copies, i.e. saves to another register
773 instead of the stack. */
775 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
776 /* Recognize constant loads; even with small stacks these are necessary
778 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
779 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
781 /* Constant pool loads, for the same reason. */
782 unsigned int constant
;
785 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
786 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
787 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
789 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instructions. */
791 unsigned short inst2
;
793 inst2
= read_code_unsigned_integer (start
+ 2, 2,
794 byte_order_for_code
);
796 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
798 /* BL, BLX. Allow some special function calls when
799 skipping the prologue; GCC generates these before
800 storing arguments to the stack. */
802 int j1
, j2
, imm1
, imm2
;
804 imm1
= sbits (insn
, 0, 10);
805 imm2
= bits (inst2
, 0, 10);
806 j1
= bit (inst2
, 13);
807 j2
= bit (inst2
, 11);
809 offset
= ((imm1
<< 12) + (imm2
<< 1));
810 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
812 nextpc
= start
+ 4 + offset
;
813 /* For BLX make sure to clear the low bits. */
814 if (bit (inst2
, 12) == 0)
815 nextpc
= nextpc
& 0xfffffffc;
817 if (!skip_prologue_function (gdbarch
, nextpc
,
818 bit (inst2
, 12) != 0))
822 else if ((insn
& 0xffd0) == 0xe900 /* stmdb Rn{!},
824 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
826 pv_t addr
= regs
[bits (insn
, 0, 3)];
829 if (pv_area_store_would_trash (stack
, addr
))
832 /* Calculate offsets of saved registers. */
833 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
834 if (inst2
& (1 << regno
))
836 addr
= pv_add_constant (addr
, -4);
837 pv_area_store (stack
, addr
, 4, regs
[regno
]);
841 regs
[bits (insn
, 0, 3)] = addr
;
844 else if ((insn
& 0xff50) == 0xe940 /* strd Rt, Rt2,
846 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
848 int regno1
= bits (inst2
, 12, 15);
849 int regno2
= bits (inst2
, 8, 11);
850 pv_t addr
= regs
[bits (insn
, 0, 3)];
852 offset
= inst2
& 0xff;
854 addr
= pv_add_constant (addr
, offset
);
856 addr
= pv_add_constant (addr
, -offset
);
858 if (pv_area_store_would_trash (stack
, addr
))
861 pv_area_store (stack
, addr
, 4, regs
[regno1
]);
862 pv_area_store (stack
, pv_add_constant (addr
, 4),
866 regs
[bits (insn
, 0, 3)] = addr
;
869 else if ((insn
& 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
870 && (inst2
& 0x0c00) == 0x0c00
871 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
873 int regno
= bits (inst2
, 12, 15);
874 pv_t addr
= regs
[bits (insn
, 0, 3)];
876 offset
= inst2
& 0xff;
878 addr
= pv_add_constant (addr
, offset
);
880 addr
= pv_add_constant (addr
, -offset
);
882 if (pv_area_store_would_trash (stack
, addr
))
885 pv_area_store (stack
, addr
, 4, regs
[regno
]);
888 regs
[bits (insn
, 0, 3)] = addr
;
891 else if ((insn
& 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
892 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
894 int regno
= bits (inst2
, 12, 15);
897 offset
= inst2
& 0xfff;
898 addr
= pv_add_constant (regs
[bits (insn
, 0, 3)], offset
);
900 if (pv_area_store_would_trash (stack
, addr
))
903 pv_area_store (stack
, addr
, 4, regs
[regno
]);
906 else if ((insn
& 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
907 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
908 /* Ignore stores of argument registers to the stack. */
911 else if ((insn
& 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
912 && (inst2
& 0x0d00) == 0x0c00
913 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
914 /* Ignore stores of argument registers to the stack. */
917 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!],
919 && (inst2
& 0x8000) == 0x0000
920 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
921 /* Ignore block loads from the stack, potentially copying
922 parameters from memory. */
925 else if ((insn
& 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
927 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
928 /* Similarly ignore dual loads from the stack. */
931 else if ((insn
& 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
932 && (inst2
& 0x0d00) == 0x0c00
933 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
934 /* Similarly ignore single loads from the stack. */
937 else if ((insn
& 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
938 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
939 /* Similarly ignore single loads from the stack. */
942 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
943 && (inst2
& 0x8000) == 0x0000)
945 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
946 | (bits (inst2
, 12, 14) << 8)
947 | bits (inst2
, 0, 7));
949 regs
[bits (inst2
, 8, 11)]
950 = pv_add_constant (regs
[bits (insn
, 0, 3)],
951 thumb_expand_immediate (imm
));
954 else if ((insn
& 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
955 && (inst2
& 0x8000) == 0x0000)
957 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
958 | (bits (inst2
, 12, 14) << 8)
959 | bits (inst2
, 0, 7));
961 regs
[bits (inst2
, 8, 11)]
962 = pv_add_constant (regs
[bits (insn
, 0, 3)], imm
);
965 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
966 && (inst2
& 0x8000) == 0x0000)
968 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
969 | (bits (inst2
, 12, 14) << 8)
970 | bits (inst2
, 0, 7));
972 regs
[bits (inst2
, 8, 11)]
973 = pv_add_constant (regs
[bits (insn
, 0, 3)],
974 - (CORE_ADDR
) thumb_expand_immediate (imm
));
977 else if ((insn
& 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
978 && (inst2
& 0x8000) == 0x0000)
980 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
981 | (bits (inst2
, 12, 14) << 8)
982 | bits (inst2
, 0, 7));
984 regs
[bits (inst2
, 8, 11)]
985 = pv_add_constant (regs
[bits (insn
, 0, 3)], - (CORE_ADDR
) imm
);
988 else if ((insn
& 0xfbff) == 0xf04f) /* mov.w Rd, #const */
990 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
991 | (bits (inst2
, 12, 14) << 8)
992 | bits (inst2
, 0, 7));
994 regs
[bits (inst2
, 8, 11)]
995 = pv_constant (thumb_expand_immediate (imm
));
998 else if ((insn
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1001 = EXTRACT_MOVW_MOVT_IMM_T (insn
, inst2
);
1003 regs
[bits (inst2
, 8, 11)] = pv_constant (imm
);
1006 else if (insn
== 0xea5f /* mov.w Rd,Rm */
1007 && (inst2
& 0xf0f0) == 0)
1009 int dst_reg
= (inst2
& 0x0f00) >> 8;
1010 int src_reg
= inst2
& 0xf;
1011 regs
[dst_reg
] = regs
[src_reg
];
1014 else if ((insn
& 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1016 /* Constant pool loads. */
1017 unsigned int constant
;
1020 offset
= bits (inst2
, 0, 11);
1022 loc
= start
+ 4 + offset
;
1024 loc
= start
+ 4 - offset
;
1026 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1027 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1030 else if ((insn
& 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1032 /* Constant pool loads. */
1033 unsigned int constant
;
1036 offset
= bits (inst2
, 0, 7) << 2;
1038 loc
= start
+ 4 + offset
;
1040 loc
= start
+ 4 - offset
;
1042 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1043 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1045 constant
= read_memory_unsigned_integer (loc
+ 4, 4, byte_order
);
1046 regs
[bits (inst2
, 8, 11)] = pv_constant (constant
);
1049 else if (thumb2_instruction_changes_pc (insn
, inst2
))
1051 /* Don't scan past anything that might change control flow. */
1056 /* The optimizer might shove anything into the prologue,
1057 so we just skip what we don't recognize. */
1058 unrecognized_pc
= start
;
1063 else if (thumb_instruction_changes_pc (insn
))
1065 /* Don't scan past anything that might change control flow. */
1070 /* The optimizer might shove anything into the prologue,
1071 so we just skip what we don't recognize. */
1072 unrecognized_pc
= start
;
1079 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1080 paddress (gdbarch
, start
));
1082 if (unrecognized_pc
== 0)
1083 unrecognized_pc
= start
;
1087 do_cleanups (back_to
);
1088 return unrecognized_pc
;
1091 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1093 /* Frame pointer is fp. Frame size is constant. */
1094 cache
->framereg
= ARM_FP_REGNUM
;
1095 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1097 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
1099 /* Frame pointer is r7. Frame size is constant. */
1100 cache
->framereg
= THUMB_FP_REGNUM
;
1101 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
1105 /* Try the stack pointer... this is a bit desperate. */
1106 cache
->framereg
= ARM_SP_REGNUM
;
1107 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1110 for (i
= 0; i
< 16; i
++)
1111 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
1112 cache
->saved_regs
[i
].addr
= offset
;
1114 do_cleanups (back_to
);
1115 return unrecognized_pc
;
1119 /* Try to analyze the instructions starting from PC, which load symbol
1120 __stack_chk_guard. Return the address of instruction after loading this
1121 symbol, set the dest register number to *BASEREG, and set the size of
1122 instructions for loading symbol in OFFSET. Return 0 if instructions are
1126 arm_analyze_load_stack_chk_guard(CORE_ADDR pc
, struct gdbarch
*gdbarch
,
1127 unsigned int *destreg
, int *offset
)
1129 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1130 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1131 unsigned int low
, high
, address
;
1136 unsigned short insn1
1137 = read_code_unsigned_integer (pc
, 2, byte_order_for_code
);
1139 if ((insn1
& 0xf800) == 0x4800) /* ldr Rd, #immed */
1141 *destreg
= bits (insn1
, 8, 10);
1143 address
= (pc
& 0xfffffffc) + 4 + (bits (insn1
, 0, 7) << 2);
1144 address
= read_memory_unsigned_integer (address
, 4,
1145 byte_order_for_code
);
1147 else if ((insn1
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1149 unsigned short insn2
1150 = read_code_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1152 low
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1155 = read_code_unsigned_integer (pc
+ 4, 2, byte_order_for_code
);
1157 = read_code_unsigned_integer (pc
+ 6, 2, byte_order_for_code
);
1159 /* movt Rd, #const */
1160 if ((insn1
& 0xfbc0) == 0xf2c0)
1162 high
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1163 *destreg
= bits (insn2
, 8, 11);
1165 address
= (high
<< 16 | low
);
1172 = read_code_unsigned_integer (pc
, 4, byte_order_for_code
);
1174 if ((insn
& 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1176 address
= bits (insn
, 0, 11) + pc
+ 8;
1177 address
= read_memory_unsigned_integer (address
, 4,
1178 byte_order_for_code
);
1180 *destreg
= bits (insn
, 12, 15);
1183 else if ((insn
& 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1185 low
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1188 = read_code_unsigned_integer (pc
+ 4, 4, byte_order_for_code
);
1190 if ((insn
& 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1192 high
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1193 *destreg
= bits (insn
, 12, 15);
1195 address
= (high
<< 16 | low
);
1203 /* Try to skip a sequence of instructions used for stack protector. If PC
1204 points to the first instruction of this sequence, return the address of
1205 first instruction after this sequence, otherwise, return original PC.
1207 On arm, this sequence of instructions is composed of mainly three steps,
1208 Step 1: load symbol __stack_chk_guard,
1209 Step 2: load from address of __stack_chk_guard,
1210 Step 3: store it to somewhere else.
1212 Usually, instructions on step 2 and step 3 are the same on various ARM
1213 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1214 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1215 instructions in step 1 vary from different ARM architectures. On ARMv7,
1218 movw Rn, #:lower16:__stack_chk_guard
1219 movt Rn, #:upper16:__stack_chk_guard
1226 .word __stack_chk_guard
1228 Since ldr/str is a very popular instruction, we can't use them as
1229 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1230 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1231 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1234 arm_skip_stack_protector(CORE_ADDR pc
, struct gdbarch
*gdbarch
)
1236 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1237 unsigned int basereg
;
1238 struct bound_minimal_symbol stack_chk_guard
;
1240 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1243 /* Try to parse the instructions in Step 1. */
1244 addr
= arm_analyze_load_stack_chk_guard (pc
, gdbarch
,
1249 stack_chk_guard
= lookup_minimal_symbol_by_pc (addr
);
1250 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1251 Otherwise, this sequence cannot be for stack protector. */
1252 if (stack_chk_guard
.minsym
== NULL
1253 || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard
.minsym
), "__stack_chk_guard"))
1258 unsigned int destreg
;
1260 = read_code_unsigned_integer (pc
+ offset
, 2, byte_order_for_code
);
1262 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1263 if ((insn
& 0xf800) != 0x6800)
1265 if (bits (insn
, 3, 5) != basereg
)
1267 destreg
= bits (insn
, 0, 2);
1269 insn
= read_code_unsigned_integer (pc
+ offset
+ 2, 2,
1270 byte_order_for_code
);
1271 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1272 if ((insn
& 0xf800) != 0x6000)
1274 if (destreg
!= bits (insn
, 0, 2))
1279 unsigned int destreg
;
1281 = read_code_unsigned_integer (pc
+ offset
, 4, byte_order_for_code
);
1283 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1284 if ((insn
& 0x0e500000) != 0x04100000)
1286 if (bits (insn
, 16, 19) != basereg
)
1288 destreg
= bits (insn
, 12, 15);
1289 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1290 insn
= read_code_unsigned_integer (pc
+ offset
+ 4,
1291 4, byte_order_for_code
);
1292 if ((insn
& 0x0e500000) != 0x04000000)
1294 if (bits (insn
, 12, 15) != destreg
)
1297 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1300 return pc
+ offset
+ 4;
1302 return pc
+ offset
+ 8;
1305 /* Advance the PC across any function entry prologue instructions to
1306 reach some "real" code.
1308 The APCS (ARM Procedure Call Standard) defines the following
1312 [stmfd sp!, {a1,a2,a3,a4}]
1313 stmfd sp!, {...,fp,ip,lr,pc}
1314 [stfe f7, [sp, #-12]!]
1315 [stfe f6, [sp, #-12]!]
1316 [stfe f5, [sp, #-12]!]
1317 [stfe f4, [sp, #-12]!]
1318 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1321 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1323 CORE_ADDR func_addr
, limit_pc
;
1325 /* See if we can determine the end of the prologue via the symbol table.
1326 If so, then return either PC, or the PC after the prologue, whichever
1328 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1330 CORE_ADDR post_prologue_pc
1331 = skip_prologue_using_sal (gdbarch
, func_addr
);
1332 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1334 if (post_prologue_pc
)
1336 = arm_skip_stack_protector (post_prologue_pc
, gdbarch
);
1339 /* GCC always emits a line note before the prologue and another
1340 one after, even if the two are at the same address or on the
1341 same line. Take advantage of this so that we do not need to
1342 know every instruction that might appear in the prologue. We
1343 will have producer information for most binaries; if it is
1344 missing (e.g. for -gstabs), assuming the GNU tools. */
1345 if (post_prologue_pc
1347 || COMPUNIT_PRODUCER (cust
) == NULL
1348 || startswith (COMPUNIT_PRODUCER (cust
), "GNU ")
1349 || startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
1350 return post_prologue_pc
;
1352 if (post_prologue_pc
!= 0)
1354 CORE_ADDR analyzed_limit
;
1356 /* For non-GCC compilers, make sure the entire line is an
1357 acceptable prologue; GDB will round this function's
1358 return value up to the end of the following line so we
1359 can not skip just part of a line (and we do not want to).
1361 RealView does not treat the prologue specially, but does
1362 associate prologue code with the opening brace; so this
1363 lets us skip the first line if we think it is the opening
1365 if (arm_pc_is_thumb (gdbarch
, func_addr
))
1366 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
1367 post_prologue_pc
, NULL
);
1369 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
1370 post_prologue_pc
, NULL
);
1372 if (analyzed_limit
!= post_prologue_pc
)
1375 return post_prologue_pc
;
1379 /* Can't determine prologue from the symbol table, need to examine
1382 /* Find an upper limit on the function prologue using the debug
1383 information. If the debug information could not be used to provide
1384 that bound, then use an arbitrary large number as the upper bound. */
1385 /* Like arm_scan_prologue, stop no later than pc + 64. */
1386 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1388 limit_pc
= pc
+ 64; /* Magic. */
1391 /* Check if this is Thumb code. */
1392 if (arm_pc_is_thumb (gdbarch
, pc
))
1393 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1395 return arm_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1399 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1400 This function decodes a Thumb function prologue to determine:
1401 1) the size of the stack frame
1402 2) which registers are saved on it
1403 3) the offsets of saved regs
1404 4) the offset from the stack pointer to the frame pointer
1406 A typical Thumb function prologue would create this stack frame
1407 (offsets relative to FP)
1408 old SP -> 24 stack parameters
1411 R7 -> 0 local variables (16 bytes)
1412 SP -> -12 additional stack space (12 bytes)
1413 The frame size would thus be 36 bytes, and the frame offset would be
1414 12 bytes. The frame register is R7.
1416 The comments for thumb_skip_prolog() describe the algorithm we use
1417 to detect the end of the prolog. */
1421 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
1422 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
1424 CORE_ADDR prologue_start
;
1425 CORE_ADDR prologue_end
;
1427 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1430 /* See comment in arm_scan_prologue for an explanation of
1432 if (prologue_end
> prologue_start
+ 64)
1434 prologue_end
= prologue_start
+ 64;
1438 /* We're in the boondocks: we have no idea where the start of the
1442 prologue_end
= std::min (prologue_end
, prev_pc
);
1444 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1447 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1451 arm_instruction_restores_sp (unsigned int insn
)
1453 if (bits (insn
, 28, 31) != INST_NV
)
1455 if ((insn
& 0x0df0f000) == 0x0080d000
1456 /* ADD SP (register or immediate). */
1457 || (insn
& 0x0df0f000) == 0x0040d000
1458 /* SUB SP (register or immediate). */
1459 || (insn
& 0x0ffffff0) == 0x01a0d000
1461 || (insn
& 0x0fff0000) == 0x08bd0000
1463 || (insn
& 0x0fff0000) == 0x049d0000)
1464 /* POP of a single register. */
1471 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1472 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1473 fill it in. Return the first address not recognized as a prologue
1476 We recognize all the instructions typically found in ARM prologues,
1477 plus harmless instructions which can be skipped (either for analysis
1478 purposes, or a more restrictive set that can be skipped when finding
1479 the end of the prologue). */
1482 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1483 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1484 struct arm_prologue_cache
*cache
)
1486 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1488 CORE_ADDR offset
, current_pc
;
1489 pv_t regs
[ARM_FPS_REGNUM
];
1490 struct pv_area
*stack
;
1491 struct cleanup
*back_to
;
1492 CORE_ADDR unrecognized_pc
= 0;
1494 /* Search the prologue looking for instructions that set up the
1495 frame pointer, adjust the stack pointer, and save registers.
1497 Be careful, however, and if it doesn't look like a prologue,
1498 don't try to scan it. If, for instance, a frameless function
1499 begins with stmfd sp!, then we will tell ourselves there is
1500 a frame, which will confuse stack traceback, as well as "finish"
1501 and other operations that rely on a knowledge of the stack
1504 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1505 regs
[regno
] = pv_register (regno
, 0);
1506 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1507 back_to
= make_cleanup_free_pv_area (stack
);
1509 for (current_pc
= prologue_start
;
1510 current_pc
< prologue_end
;
1514 = read_code_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1516 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1518 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1521 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1522 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1524 unsigned imm
= insn
& 0xff; /* immediate value */
1525 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1526 int rd
= bits (insn
, 12, 15);
1527 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1528 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1531 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1532 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1534 unsigned imm
= insn
& 0xff; /* immediate value */
1535 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1536 int rd
= bits (insn
, 12, 15);
1537 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1538 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1541 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd,
1544 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1546 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1547 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4,
1548 regs
[bits (insn
, 12, 15)]);
1551 else if ((insn
& 0xffff0000) == 0xe92d0000)
1552 /* stmfd sp!, {..., fp, ip, lr, pc}
1554 stmfd sp!, {a1, a2, a3, a4} */
1556 int mask
= insn
& 0xffff;
1558 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1561 /* Calculate offsets of saved registers. */
1562 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1563 if (mask
& (1 << regno
))
1566 = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1567 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1570 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1571 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1572 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1574 /* No need to add this to saved_regs -- it's just an arg reg. */
1577 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1578 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1579 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1581 /* No need to add this to saved_regs -- it's just an arg reg. */
1584 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn,
1586 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1588 /* No need to add this to saved_regs -- it's just arg regs. */
1591 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1593 unsigned imm
= insn
& 0xff; /* immediate value */
1594 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1595 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1596 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1598 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1600 unsigned imm
= insn
& 0xff; /* immediate value */
1601 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1602 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1603 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1605 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?,
1607 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1609 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1612 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1613 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1614 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1616 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1618 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1620 int n_saved_fp_regs
;
1621 unsigned int fp_start_reg
, fp_bound_reg
;
1623 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1626 if ((insn
& 0x800) == 0x800) /* N0 is set */
1628 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1629 n_saved_fp_regs
= 3;
1631 n_saved_fp_regs
= 1;
1635 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1636 n_saved_fp_regs
= 2;
1638 n_saved_fp_regs
= 4;
1641 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1642 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1643 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1645 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1646 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
1647 regs
[fp_start_reg
++]);
1650 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1652 /* Allow some special function calls when skipping the
1653 prologue; GCC generates these before storing arguments to
1655 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1657 if (skip_prologue_function (gdbarch
, dest
, 0))
1662 else if ((insn
& 0xf0000000) != 0xe0000000)
1663 break; /* Condition not true, exit early. */
1664 else if (arm_instruction_changes_pc (insn
))
1665 /* Don't scan past anything that might change control flow. */
1667 else if (arm_instruction_restores_sp (insn
))
1669 /* Don't scan past the epilogue. */
1672 else if ((insn
& 0xfe500000) == 0xe8100000 /* ldm */
1673 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1674 /* Ignore block loads from the stack, potentially copying
1675 parameters from memory. */
1677 else if ((insn
& 0xfc500000) == 0xe4100000
1678 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1679 /* Similarly ignore single loads from the stack. */
1681 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1682 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1683 register instead of the stack. */
1687 /* The optimizer might shove anything into the prologue, if
1688 we build up cache (cache != NULL) from scanning prologue,
1689 we just skip what we don't recognize and scan further to
1690 make cache as complete as possible. However, if we skip
1691 prologue, we'll stop immediately on unrecognized
1693 unrecognized_pc
= current_pc
;
1701 if (unrecognized_pc
== 0)
1702 unrecognized_pc
= current_pc
;
1706 int framereg
, framesize
;
1708 /* The frame size is just the distance from the frame register
1709 to the original stack pointer. */
1710 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1712 /* Frame pointer is fp. */
1713 framereg
= ARM_FP_REGNUM
;
1714 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1718 /* Try the stack pointer... this is a bit desperate. */
1719 framereg
= ARM_SP_REGNUM
;
1720 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1723 cache
->framereg
= framereg
;
1724 cache
->framesize
= framesize
;
1726 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1727 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1728 cache
->saved_regs
[regno
].addr
= offset
;
1732 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1733 paddress (gdbarch
, unrecognized_pc
));
1735 do_cleanups (back_to
);
1736 return unrecognized_pc
;
1740 arm_scan_prologue (struct frame_info
*this_frame
,
1741 struct arm_prologue_cache
*cache
)
1743 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1744 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1745 CORE_ADDR prologue_start
, prologue_end
;
1746 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1747 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1749 /* Assume there is no frame until proven otherwise. */
1750 cache
->framereg
= ARM_SP_REGNUM
;
1751 cache
->framesize
= 0;
1753 /* Check for Thumb prologue. */
1754 if (arm_frame_is_thumb (this_frame
))
1756 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1760 /* Find the function prologue. If we can't find the function in
1761 the symbol table, peek in the stack frame to find the PC. */
1762 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1765 /* One way to find the end of the prologue (which works well
1766 for unoptimized code) is to do the following:
1768 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1771 prologue_end = prev_pc;
1772 else if (sal.end < prologue_end)
1773 prologue_end = sal.end;
1775 This mechanism is very accurate so long as the optimizer
1776 doesn't move any instructions from the function body into the
1777 prologue. If this happens, sal.end will be the last
1778 instruction in the first hunk of prologue code just before
1779 the first instruction that the scheduler has moved from
1780 the body to the prologue.
1782 In order to make sure that we scan all of the prologue
1783 instructions, we use a slightly less accurate mechanism which
1784 may scan more than necessary. To help compensate for this
1785 lack of accuracy, the prologue scanning loop below contains
1786 several clauses which'll cause the loop to terminate early if
1787 an implausible prologue instruction is encountered.
1793 is a suitable endpoint since it accounts for the largest
1794 possible prologue plus up to five instructions inserted by
1797 if (prologue_end
> prologue_start
+ 64)
1799 prologue_end
= prologue_start
+ 64; /* See above. */
1804 /* We have no symbol information. Our only option is to assume this
1805 function has a standard stack frame and the normal frame register.
1806 Then, we can find the value of our frame pointer on entrance to
1807 the callee (or at the present moment if this is the innermost frame).
1808 The value stored there should be the address of the stmfd + 8. */
1809 CORE_ADDR frame_loc
;
1810 ULONGEST return_value
;
1812 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
1813 if (!safe_read_memory_unsigned_integer (frame_loc
, 4, byte_order
,
1818 prologue_start
= gdbarch_addr_bits_remove
1819 (gdbarch
, return_value
) - 8;
1820 prologue_end
= prologue_start
+ 64; /* See above. */
1824 if (prev_pc
< prologue_end
)
1825 prologue_end
= prev_pc
;
1827 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1830 static struct arm_prologue_cache
*
1831 arm_make_prologue_cache (struct frame_info
*this_frame
)
1834 struct arm_prologue_cache
*cache
;
1835 CORE_ADDR unwound_fp
;
1837 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1838 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1840 arm_scan_prologue (this_frame
, cache
);
1842 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
1843 if (unwound_fp
== 0)
1846 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
1848 /* Calculate actual addresses of saved registers using offsets
1849 determined by arm_scan_prologue. */
1850 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
1851 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
1852 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
1857 /* Implementation of the stop_reason hook for arm_prologue frames. */
1859 static enum unwind_stop_reason
1860 arm_prologue_unwind_stop_reason (struct frame_info
*this_frame
,
1863 struct arm_prologue_cache
*cache
;
1866 if (*this_cache
== NULL
)
1867 *this_cache
= arm_make_prologue_cache (this_frame
);
1868 cache
= (struct arm_prologue_cache
*) *this_cache
;
1870 /* This is meant to halt the backtrace at "_start". */
1871 pc
= get_frame_pc (this_frame
);
1872 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1873 return UNWIND_OUTERMOST
;
1875 /* If we've hit a wall, stop. */
1876 if (cache
->prev_sp
== 0)
1877 return UNWIND_OUTERMOST
;
1879 return UNWIND_NO_REASON
;
1882 /* Our frame ID for a normal frame is the current function's starting PC
1883 and the caller's SP when we were called. */
1886 arm_prologue_this_id (struct frame_info
*this_frame
,
1888 struct frame_id
*this_id
)
1890 struct arm_prologue_cache
*cache
;
1894 if (*this_cache
== NULL
)
1895 *this_cache
= arm_make_prologue_cache (this_frame
);
1896 cache
= (struct arm_prologue_cache
*) *this_cache
;
1898 /* Use function start address as part of the frame ID. If we cannot
1899 identify the start address (due to missing symbol information),
1900 fall back to just using the current PC. */
1901 pc
= get_frame_pc (this_frame
);
1902 func
= get_frame_func (this_frame
);
1906 id
= frame_id_build (cache
->prev_sp
, func
);
1910 static struct value
*
1911 arm_prologue_prev_register (struct frame_info
*this_frame
,
1915 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1916 struct arm_prologue_cache
*cache
;
1918 if (*this_cache
== NULL
)
1919 *this_cache
= arm_make_prologue_cache (this_frame
);
1920 cache
= (struct arm_prologue_cache
*) *this_cache
;
1922 /* If we are asked to unwind the PC, then we need to return the LR
1923 instead. The prologue may save PC, but it will point into this
1924 frame's prologue, not the next frame's resume location. Also
1925 strip the saved T bit. A valid LR may have the low bit set, but
1926 a valid PC never does. */
1927 if (prev_regnum
== ARM_PC_REGNUM
)
1931 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1932 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1933 arm_addr_bits_remove (gdbarch
, lr
));
1936 /* SP is generally not saved to the stack, but this frame is
1937 identified by the next frame's stack pointer at the time of the call.
1938 The value was already reconstructed into PREV_SP. */
1939 if (prev_regnum
== ARM_SP_REGNUM
)
1940 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1942 /* The CPSR may have been changed by the call instruction and by the
1943 called function. The only bit we can reconstruct is the T bit,
1944 by checking the low bit of LR as of the call. This is a reliable
1945 indicator of Thumb-ness except for some ARM v4T pre-interworking
1946 Thumb code, which could get away with a clear low bit as long as
1947 the called function did not use bx. Guess that all other
1948 bits are unchanged; the condition flags are presumably lost,
1949 but the processor status is likely valid. */
1950 if (prev_regnum
== ARM_PS_REGNUM
)
1953 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
1955 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1956 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1957 if (IS_THUMB_ADDR (lr
))
1961 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1964 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1968 struct frame_unwind arm_prologue_unwind
= {
1970 arm_prologue_unwind_stop_reason
,
1971 arm_prologue_this_id
,
1972 arm_prologue_prev_register
,
1974 default_frame_sniffer
1977 /* Maintain a list of ARM exception table entries per objfile, similar to the
1978 list of mapping symbols. We only cache entries for standard ARM-defined
1979 personality routines; the cache will contain only the frame unwinding
1980 instructions associated with the entry (not the descriptors). */
1982 static const struct objfile_data
*arm_exidx_data_key
;
1984 struct arm_exidx_entry
1989 typedef struct arm_exidx_entry arm_exidx_entry_s
;
1990 DEF_VEC_O(arm_exidx_entry_s
);
1992 struct arm_exidx_data
1994 VEC(arm_exidx_entry_s
) **section_maps
;
1998 arm_exidx_data_free (struct objfile
*objfile
, void *arg
)
2000 struct arm_exidx_data
*data
= (struct arm_exidx_data
*) arg
;
2003 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
2004 VEC_free (arm_exidx_entry_s
, data
->section_maps
[i
]);
2008 arm_compare_exidx_entries (const struct arm_exidx_entry
*lhs
,
2009 const struct arm_exidx_entry
*rhs
)
2011 return lhs
->addr
< rhs
->addr
;
2014 static struct obj_section
*
2015 arm_obj_section_from_vma (struct objfile
*objfile
, bfd_vma vma
)
2017 struct obj_section
*osect
;
2019 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
2020 if (bfd_get_section_flags (objfile
->obfd
,
2021 osect
->the_bfd_section
) & SEC_ALLOC
)
2023 bfd_vma start
, size
;
2024 start
= bfd_get_section_vma (objfile
->obfd
, osect
->the_bfd_section
);
2025 size
= bfd_get_section_size (osect
->the_bfd_section
);
2027 if (start
<= vma
&& vma
< start
+ size
)
2034 /* Parse contents of exception table and exception index sections
2035 of OBJFILE, and fill in the exception table entry cache.
2037 For each entry that refers to a standard ARM-defined personality
2038 routine, extract the frame unwinding instructions (from either
2039 the index or the table section). The unwinding instructions
2041 - extracting them from the rest of the table data
2042 - converting to host endianness
2043 - appending the implicit 0xb0 ("Finish") code
2045 The extracted and normalized instructions are stored for later
2046 retrieval by the arm_find_exidx_entry routine. */
2049 arm_exidx_new_objfile (struct objfile
*objfile
)
2051 struct cleanup
*cleanups
;
2052 struct arm_exidx_data
*data
;
2053 asection
*exidx
, *extab
;
2054 bfd_vma exidx_vma
= 0, extab_vma
= 0;
2055 bfd_size_type exidx_size
= 0, extab_size
= 0;
2056 gdb_byte
*exidx_data
= NULL
, *extab_data
= NULL
;
2059 /* If we've already touched this file, do nothing. */
2060 if (!objfile
|| objfile_data (objfile
, arm_exidx_data_key
) != NULL
)
2062 cleanups
= make_cleanup (null_cleanup
, NULL
);
2064 /* Read contents of exception table and index. */
2065 exidx
= bfd_get_section_by_name (objfile
->obfd
, ELF_STRING_ARM_unwind
);
2068 exidx_vma
= bfd_section_vma (objfile
->obfd
, exidx
);
2069 exidx_size
= bfd_get_section_size (exidx
);
2070 exidx_data
= (gdb_byte
*) xmalloc (exidx_size
);
2071 make_cleanup (xfree
, exidx_data
);
2073 if (!bfd_get_section_contents (objfile
->obfd
, exidx
,
2074 exidx_data
, 0, exidx_size
))
2076 do_cleanups (cleanups
);
2081 extab
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.extab");
2084 extab_vma
= bfd_section_vma (objfile
->obfd
, extab
);
2085 extab_size
= bfd_get_section_size (extab
);
2086 extab_data
= (gdb_byte
*) xmalloc (extab_size
);
2087 make_cleanup (xfree
, extab_data
);
2089 if (!bfd_get_section_contents (objfile
->obfd
, extab
,
2090 extab_data
, 0, extab_size
))
2092 do_cleanups (cleanups
);
2097 /* Allocate exception table data structure. */
2098 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
, struct arm_exidx_data
);
2099 set_objfile_data (objfile
, arm_exidx_data_key
, data
);
2100 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2101 objfile
->obfd
->section_count
,
2102 VEC(arm_exidx_entry_s
) *);
2104 /* Fill in exception table. */
2105 for (i
= 0; i
< exidx_size
/ 8; i
++)
2107 struct arm_exidx_entry new_exidx_entry
;
2108 bfd_vma idx
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8);
2109 bfd_vma val
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8 + 4);
2110 bfd_vma addr
= 0, word
= 0;
2111 int n_bytes
= 0, n_words
= 0;
2112 struct obj_section
*sec
;
2113 gdb_byte
*entry
= NULL
;
2115 /* Extract address of start of function. */
2116 idx
= ((idx
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2117 idx
+= exidx_vma
+ i
* 8;
2119 /* Find section containing function and compute section offset. */
2120 sec
= arm_obj_section_from_vma (objfile
, idx
);
2123 idx
-= bfd_get_section_vma (objfile
->obfd
, sec
->the_bfd_section
);
2125 /* Determine address of exception table entry. */
2128 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2130 else if ((val
& 0xff000000) == 0x80000000)
2132 /* Exception table entry embedded in .ARM.exidx
2133 -- must be short form. */
2137 else if (!(val
& 0x80000000))
2139 /* Exception table entry in .ARM.extab. */
2140 addr
= ((val
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2141 addr
+= exidx_vma
+ i
* 8 + 4;
2143 if (addr
>= extab_vma
&& addr
+ 4 <= extab_vma
+ extab_size
)
2145 word
= bfd_h_get_32 (objfile
->obfd
,
2146 extab_data
+ addr
- extab_vma
);
2149 if ((word
& 0xff000000) == 0x80000000)
2154 else if ((word
& 0xff000000) == 0x81000000
2155 || (word
& 0xff000000) == 0x82000000)
2159 n_words
= ((word
>> 16) & 0xff);
2161 else if (!(word
& 0x80000000))
2164 struct obj_section
*pers_sec
;
2165 int gnu_personality
= 0;
2167 /* Custom personality routine. */
2168 pers
= ((word
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2169 pers
= UNMAKE_THUMB_ADDR (pers
+ addr
- 4);
2171 /* Check whether we've got one of the variants of the
2172 GNU personality routines. */
2173 pers_sec
= arm_obj_section_from_vma (objfile
, pers
);
2176 static const char *personality
[] =
2178 "__gcc_personality_v0",
2179 "__gxx_personality_v0",
2180 "__gcj_personality_v0",
2181 "__gnu_objc_personality_v0",
2185 CORE_ADDR pc
= pers
+ obj_section_offset (pers_sec
);
2188 for (k
= 0; personality
[k
]; k
++)
2189 if (lookup_minimal_symbol_by_pc_name
2190 (pc
, personality
[k
], objfile
))
2192 gnu_personality
= 1;
2197 /* If so, the next word contains a word count in the high
2198 byte, followed by the same unwind instructions as the
2199 pre-defined forms. */
2201 && addr
+ 4 <= extab_vma
+ extab_size
)
2203 word
= bfd_h_get_32 (objfile
->obfd
,
2204 extab_data
+ addr
- extab_vma
);
2207 n_words
= ((word
>> 24) & 0xff);
2213 /* Sanity check address. */
2215 if (addr
< extab_vma
|| addr
+ 4 * n_words
> extab_vma
+ extab_size
)
2216 n_words
= n_bytes
= 0;
2218 /* The unwind instructions reside in WORD (only the N_BYTES least
2219 significant bytes are valid), followed by N_WORDS words in the
2220 extab section starting at ADDR. */
2221 if (n_bytes
|| n_words
)
2224 = (gdb_byte
*) obstack_alloc (&objfile
->objfile_obstack
,
2225 n_bytes
+ n_words
* 4 + 1);
2228 *p
++ = (gdb_byte
) ((word
>> (8 * n_bytes
)) & 0xff);
2232 word
= bfd_h_get_32 (objfile
->obfd
,
2233 extab_data
+ addr
- extab_vma
);
2236 *p
++ = (gdb_byte
) ((word
>> 24) & 0xff);
2237 *p
++ = (gdb_byte
) ((word
>> 16) & 0xff);
2238 *p
++ = (gdb_byte
) ((word
>> 8) & 0xff);
2239 *p
++ = (gdb_byte
) (word
& 0xff);
2242 /* Implied "Finish" to terminate the list. */
2246 /* Push entry onto vector. They are guaranteed to always
2247 appear in order of increasing addresses. */
2248 new_exidx_entry
.addr
= idx
;
2249 new_exidx_entry
.entry
= entry
;
2250 VEC_safe_push (arm_exidx_entry_s
,
2251 data
->section_maps
[sec
->the_bfd_section
->index
],
2255 do_cleanups (cleanups
);
2258 /* Search for the exception table entry covering MEMADDR. If one is found,
2259 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2260 set *START to the start of the region covered by this entry. */
2263 arm_find_exidx_entry (CORE_ADDR memaddr
, CORE_ADDR
*start
)
2265 struct obj_section
*sec
;
2267 sec
= find_pc_section (memaddr
);
2270 struct arm_exidx_data
*data
;
2271 VEC(arm_exidx_entry_s
) *map
;
2272 struct arm_exidx_entry map_key
= { memaddr
- obj_section_addr (sec
), 0 };
2275 data
= ((struct arm_exidx_data
*)
2276 objfile_data (sec
->objfile
, arm_exidx_data_key
));
2279 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
2280 if (!VEC_empty (arm_exidx_entry_s
, map
))
2282 struct arm_exidx_entry
*map_sym
;
2284 idx
= VEC_lower_bound (arm_exidx_entry_s
, map
, &map_key
,
2285 arm_compare_exidx_entries
);
2287 /* VEC_lower_bound finds the earliest ordered insertion
2288 point. If the following symbol starts at this exact
2289 address, we use that; otherwise, the preceding
2290 exception table entry covers this address. */
2291 if (idx
< VEC_length (arm_exidx_entry_s
, map
))
2293 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
);
2294 if (map_sym
->addr
== map_key
.addr
)
2297 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2298 return map_sym
->entry
;
2304 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
- 1);
2306 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2307 return map_sym
->entry
;
2316 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2317 instruction list from the ARM exception table entry ENTRY, allocate and
2318 return a prologue cache structure describing how to unwind this frame.
2320 Return NULL if the unwinding instruction list contains a "spare",
2321 "reserved" or "refuse to unwind" instruction as defined in section
2322 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2323 for the ARM Architecture" document. */
2325 static struct arm_prologue_cache
*
2326 arm_exidx_fill_cache (struct frame_info
*this_frame
, gdb_byte
*entry
)
2331 struct arm_prologue_cache
*cache
;
2332 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2333 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2339 /* Whenever we reload SP, we actually have to retrieve its
2340 actual value in the current frame. */
2343 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2345 int reg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2346 vsp
= get_frame_register_unsigned (this_frame
, reg
);
2350 CORE_ADDR addr
= cache
->saved_regs
[ARM_SP_REGNUM
].addr
;
2351 vsp
= get_frame_memory_unsigned (this_frame
, addr
, 4);
2357 /* Decode next unwind instruction. */
2360 if ((insn
& 0xc0) == 0)
2362 int offset
= insn
& 0x3f;
2363 vsp
+= (offset
<< 2) + 4;
2365 else if ((insn
& 0xc0) == 0x40)
2367 int offset
= insn
& 0x3f;
2368 vsp
-= (offset
<< 2) + 4;
2370 else if ((insn
& 0xf0) == 0x80)
2372 int mask
= ((insn
& 0xf) << 8) | *entry
++;
2375 /* The special case of an all-zero mask identifies
2376 "Refuse to unwind". We return NULL to fall back
2377 to the prologue analyzer. */
2381 /* Pop registers r4..r15 under mask. */
2382 for (i
= 0; i
< 12; i
++)
2383 if (mask
& (1 << i
))
2385 cache
->saved_regs
[4 + i
].addr
= vsp
;
2389 /* Special-case popping SP -- we need to reload vsp. */
2390 if (mask
& (1 << (ARM_SP_REGNUM
- 4)))
2393 else if ((insn
& 0xf0) == 0x90)
2395 int reg
= insn
& 0xf;
2397 /* Reserved cases. */
2398 if (reg
== ARM_SP_REGNUM
|| reg
== ARM_PC_REGNUM
)
2401 /* Set SP from another register and mark VSP for reload. */
2402 cache
->saved_regs
[ARM_SP_REGNUM
] = cache
->saved_regs
[reg
];
2405 else if ((insn
& 0xf0) == 0xa0)
2407 int count
= insn
& 0x7;
2408 int pop_lr
= (insn
& 0x8) != 0;
2411 /* Pop r4..r[4+count]. */
2412 for (i
= 0; i
<= count
; i
++)
2414 cache
->saved_regs
[4 + i
].addr
= vsp
;
2418 /* If indicated by flag, pop LR as well. */
2421 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= vsp
;
2425 else if (insn
== 0xb0)
2427 /* We could only have updated PC by popping into it; if so, it
2428 will show up as address. Otherwise, copy LR into PC. */
2429 if (!trad_frame_addr_p (cache
->saved_regs
, ARM_PC_REGNUM
))
2430 cache
->saved_regs
[ARM_PC_REGNUM
]
2431 = cache
->saved_regs
[ARM_LR_REGNUM
];
2436 else if (insn
== 0xb1)
2438 int mask
= *entry
++;
2441 /* All-zero mask and mask >= 16 is "spare". */
2442 if (mask
== 0 || mask
>= 16)
2445 /* Pop r0..r3 under mask. */
2446 for (i
= 0; i
< 4; i
++)
2447 if (mask
& (1 << i
))
2449 cache
->saved_regs
[i
].addr
= vsp
;
2453 else if (insn
== 0xb2)
2455 ULONGEST offset
= 0;
2460 offset
|= (*entry
& 0x7f) << shift
;
2463 while (*entry
++ & 0x80);
2465 vsp
+= 0x204 + (offset
<< 2);
2467 else if (insn
== 0xb3)
2469 int start
= *entry
>> 4;
2470 int count
= (*entry
++) & 0xf;
2473 /* Only registers D0..D15 are valid here. */
2474 if (start
+ count
>= 16)
2477 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2478 for (i
= 0; i
<= count
; i
++)
2480 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2484 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2487 else if ((insn
& 0xf8) == 0xb8)
2489 int count
= insn
& 0x7;
2492 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2493 for (i
= 0; i
<= count
; i
++)
2495 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2499 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2502 else if (insn
== 0xc6)
2504 int start
= *entry
>> 4;
2505 int count
= (*entry
++) & 0xf;
2508 /* Only registers WR0..WR15 are valid. */
2509 if (start
+ count
>= 16)
2512 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2513 for (i
= 0; i
<= count
; i
++)
2515 cache
->saved_regs
[ARM_WR0_REGNUM
+ start
+ i
].addr
= vsp
;
2519 else if (insn
== 0xc7)
2521 int mask
= *entry
++;
2524 /* All-zero mask and mask >= 16 is "spare". */
2525 if (mask
== 0 || mask
>= 16)
2528 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2529 for (i
= 0; i
< 4; i
++)
2530 if (mask
& (1 << i
))
2532 cache
->saved_regs
[ARM_WCGR0_REGNUM
+ i
].addr
= vsp
;
2536 else if ((insn
& 0xf8) == 0xc0)
2538 int count
= insn
& 0x7;
2541 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2542 for (i
= 0; i
<= count
; i
++)
2544 cache
->saved_regs
[ARM_WR0_REGNUM
+ 10 + i
].addr
= vsp
;
2548 else if (insn
== 0xc8)
2550 int start
= *entry
>> 4;
2551 int count
= (*entry
++) & 0xf;
2554 /* Only registers D0..D31 are valid. */
2555 if (start
+ count
>= 16)
2558 /* Pop VFP double-precision registers
2559 D[16+start]..D[16+start+count]. */
2560 for (i
= 0; i
<= count
; i
++)
2562 cache
->saved_regs
[ARM_D0_REGNUM
+ 16 + start
+ i
].addr
= vsp
;
2566 else if (insn
== 0xc9)
2568 int start
= *entry
>> 4;
2569 int count
= (*entry
++) & 0xf;
2572 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2573 for (i
= 0; i
<= count
; i
++)
2575 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2579 else if ((insn
& 0xf8) == 0xd0)
2581 int count
= insn
& 0x7;
2584 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2585 for (i
= 0; i
<= count
; i
++)
2587 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2593 /* Everything else is "spare". */
2598 /* If we restore SP from a register, assume this was the frame register.
2599 Otherwise just fall back to SP as frame register. */
2600 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2601 cache
->framereg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2603 cache
->framereg
= ARM_SP_REGNUM
;
2605 /* Determine offset to previous frame. */
2607 = vsp
- get_frame_register_unsigned (this_frame
, cache
->framereg
);
2609 /* We already got the previous SP. */
2610 cache
->prev_sp
= vsp
;
2615 /* Unwinding via ARM exception table entries. Note that the sniffer
2616 already computes a filled-in prologue cache, which is then used
2617 with the same arm_prologue_this_id and arm_prologue_prev_register
2618 routines also used for prologue-parsing based unwinding. */
2621 arm_exidx_unwind_sniffer (const struct frame_unwind
*self
,
2622 struct frame_info
*this_frame
,
2623 void **this_prologue_cache
)
2625 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2626 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2627 CORE_ADDR addr_in_block
, exidx_region
, func_start
;
2628 struct arm_prologue_cache
*cache
;
2631 /* See if we have an ARM exception table entry covering this address. */
2632 addr_in_block
= get_frame_address_in_block (this_frame
);
2633 entry
= arm_find_exidx_entry (addr_in_block
, &exidx_region
);
2637 /* The ARM exception table does not describe unwind information
2638 for arbitrary PC values, but is guaranteed to be correct only
2639 at call sites. We have to decide here whether we want to use
2640 ARM exception table information for this frame, or fall back
2641 to using prologue parsing. (Note that if we have DWARF CFI,
2642 this sniffer isn't even called -- CFI is always preferred.)
2644 Before we make this decision, however, we check whether we
2645 actually have *symbol* information for the current frame.
2646 If not, prologue parsing would not work anyway, so we might
2647 as well use the exception table and hope for the best. */
2648 if (find_pc_partial_function (addr_in_block
, NULL
, &func_start
, NULL
))
2652 /* If the next frame is "normal", we are at a call site in this
2653 frame, so exception information is guaranteed to be valid. */
2654 if (get_next_frame (this_frame
)
2655 && get_frame_type (get_next_frame (this_frame
)) == NORMAL_FRAME
)
2658 /* We also assume exception information is valid if we're currently
2659 blocked in a system call. The system library is supposed to
2660 ensure this, so that e.g. pthread cancellation works. */
2661 if (arm_frame_is_thumb (this_frame
))
2665 if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame
) - 2,
2666 2, byte_order_for_code
, &insn
)
2667 && (insn
& 0xff00) == 0xdf00 /* svc */)
2674 if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame
) - 4,
2675 4, byte_order_for_code
, &insn
)
2676 && (insn
& 0x0f000000) == 0x0f000000 /* svc */)
2680 /* Bail out if we don't know that exception information is valid. */
2684 /* The ARM exception index does not mark the *end* of the region
2685 covered by the entry, and some functions will not have any entry.
2686 To correctly recognize the end of the covered region, the linker
2687 should have inserted dummy records with a CANTUNWIND marker.
2689 Unfortunately, current versions of GNU ld do not reliably do
2690 this, and thus we may have found an incorrect entry above.
2691 As a (temporary) sanity check, we only use the entry if it
2692 lies *within* the bounds of the function. Note that this check
2693 might reject perfectly valid entries that just happen to cover
2694 multiple functions; therefore this check ought to be removed
2695 once the linker is fixed. */
2696 if (func_start
> exidx_region
)
2700 /* Decode the list of unwinding instructions into a prologue cache.
2701 Note that this may fail due to e.g. a "refuse to unwind" code. */
2702 cache
= arm_exidx_fill_cache (this_frame
, entry
);
2706 *this_prologue_cache
= cache
;
2710 struct frame_unwind arm_exidx_unwind
= {
2712 default_frame_unwind_stop_reason
,
2713 arm_prologue_this_id
,
2714 arm_prologue_prev_register
,
2716 arm_exidx_unwind_sniffer
2719 static struct arm_prologue_cache
*
2720 arm_make_epilogue_frame_cache (struct frame_info
*this_frame
)
2722 struct arm_prologue_cache
*cache
;
2725 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2726 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2728 /* Still rely on the offset calculated from prologue. */
2729 arm_scan_prologue (this_frame
, cache
);
2731 /* Since we are in epilogue, the SP has been restored. */
2732 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2734 /* Calculate actual addresses of saved registers using offsets
2735 determined by arm_scan_prologue. */
2736 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
2737 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
2738 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
2743 /* Implementation of function hook 'this_id' in
2744 'struct frame_uwnind' for epilogue unwinder. */
2747 arm_epilogue_frame_this_id (struct frame_info
*this_frame
,
2749 struct frame_id
*this_id
)
2751 struct arm_prologue_cache
*cache
;
2754 if (*this_cache
== NULL
)
2755 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2756 cache
= (struct arm_prologue_cache
*) *this_cache
;
2758 /* Use function start address as part of the frame ID. If we cannot
2759 identify the start address (due to missing symbol information),
2760 fall back to just using the current PC. */
2761 pc
= get_frame_pc (this_frame
);
2762 func
= get_frame_func (this_frame
);
2766 (*this_id
) = frame_id_build (cache
->prev_sp
, pc
);
2769 /* Implementation of function hook 'prev_register' in
2770 'struct frame_uwnind' for epilogue unwinder. */
2772 static struct value
*
2773 arm_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2774 void **this_cache
, int regnum
)
2776 if (*this_cache
== NULL
)
2777 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2779 return arm_prologue_prev_register (this_frame
, this_cache
, regnum
);
2782 static int arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
,
2784 static int thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
,
2787 /* Implementation of function hook 'sniffer' in
2788 'struct frame_uwnind' for epilogue unwinder. */
2791 arm_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2792 struct frame_info
*this_frame
,
2793 void **this_prologue_cache
)
2795 if (frame_relative_level (this_frame
) == 0)
2797 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2798 CORE_ADDR pc
= get_frame_pc (this_frame
);
2800 if (arm_frame_is_thumb (this_frame
))
2801 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
2803 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
2809 /* Frame unwinder from epilogue. */
2811 static const struct frame_unwind arm_epilogue_frame_unwind
=
2814 default_frame_unwind_stop_reason
,
2815 arm_epilogue_frame_this_id
,
2816 arm_epilogue_frame_prev_register
,
2818 arm_epilogue_frame_sniffer
,
2821 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2822 trampoline, return the target PC. Otherwise return 0.
2824 void call0a (char c, short s, int i, long l) {}
2828 (*pointer_to_call0a) (c, s, i, l);
2831 Instead of calling a stub library function _call_via_xx (xx is
2832 the register name), GCC may inline the trampoline in the object
2833 file as below (register r2 has the address of call0a).
2836 .type main, %function
2845 The trampoline 'bx r2' doesn't belong to main. */
2848 arm_skip_bx_reg (struct frame_info
*frame
, CORE_ADDR pc
)
2850 /* The heuristics of recognizing such trampoline is that FRAME is
2851 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2852 if (arm_frame_is_thumb (frame
))
2856 if (target_read_memory (pc
, buf
, 2) == 0)
2858 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2859 enum bfd_endian byte_order_for_code
2860 = gdbarch_byte_order_for_code (gdbarch
);
2862 = extract_unsigned_integer (buf
, 2, byte_order_for_code
);
2864 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
2867 = get_frame_register_unsigned (frame
, bits (insn
, 3, 6));
2869 /* Clear the LSB so that gdb core sets step-resume
2870 breakpoint at the right address. */
2871 return UNMAKE_THUMB_ADDR (dest
);
2879 static struct arm_prologue_cache
*
2880 arm_make_stub_cache (struct frame_info
*this_frame
)
2882 struct arm_prologue_cache
*cache
;
2884 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2885 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2887 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2892 /* Our frame ID for a stub frame is the current SP and LR. */
2895 arm_stub_this_id (struct frame_info
*this_frame
,
2897 struct frame_id
*this_id
)
2899 struct arm_prologue_cache
*cache
;
2901 if (*this_cache
== NULL
)
2902 *this_cache
= arm_make_stub_cache (this_frame
);
2903 cache
= (struct arm_prologue_cache
*) *this_cache
;
2905 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
2909 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
2910 struct frame_info
*this_frame
,
2911 void **this_prologue_cache
)
2913 CORE_ADDR addr_in_block
;
2915 CORE_ADDR pc
, start_addr
;
2918 addr_in_block
= get_frame_address_in_block (this_frame
);
2919 pc
= get_frame_pc (this_frame
);
2920 if (in_plt_section (addr_in_block
)
2921 /* We also use the stub winder if the target memory is unreadable
2922 to avoid having the prologue unwinder trying to read it. */
2923 || target_read_memory (pc
, dummy
, 4) != 0)
2926 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0
2927 && arm_skip_bx_reg (this_frame
, pc
) != 0)
2933 struct frame_unwind arm_stub_unwind
= {
2935 default_frame_unwind_stop_reason
,
2937 arm_prologue_prev_register
,
2939 arm_stub_unwind_sniffer
2942 /* Put here the code to store, into CACHE->saved_regs, the addresses
2943 of the saved registers of frame described by THIS_FRAME. CACHE is
2946 static struct arm_prologue_cache
*
2947 arm_m_exception_cache (struct frame_info
*this_frame
)
2949 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2950 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2951 struct arm_prologue_cache
*cache
;
2952 CORE_ADDR unwound_sp
;
2955 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2956 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2958 unwound_sp
= get_frame_register_unsigned (this_frame
,
2961 /* The hardware saves eight 32-bit words, comprising xPSR,
2962 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
2963 "B1.5.6 Exception entry behavior" in
2964 "ARMv7-M Architecture Reference Manual". */
2965 cache
->saved_regs
[0].addr
= unwound_sp
;
2966 cache
->saved_regs
[1].addr
= unwound_sp
+ 4;
2967 cache
->saved_regs
[2].addr
= unwound_sp
+ 8;
2968 cache
->saved_regs
[3].addr
= unwound_sp
+ 12;
2969 cache
->saved_regs
[12].addr
= unwound_sp
+ 16;
2970 cache
->saved_regs
[14].addr
= unwound_sp
+ 20;
2971 cache
->saved_regs
[15].addr
= unwound_sp
+ 24;
2972 cache
->saved_regs
[ARM_PS_REGNUM
].addr
= unwound_sp
+ 28;
2974 /* If bit 9 of the saved xPSR is set, then there is a four-byte
2975 aligner between the top of the 32-byte stack frame and the
2976 previous context's stack pointer. */
2977 cache
->prev_sp
= unwound_sp
+ 32;
2978 if (safe_read_memory_integer (unwound_sp
+ 28, 4, byte_order
, &xpsr
)
2979 && (xpsr
& (1 << 9)) != 0)
2980 cache
->prev_sp
+= 4;
2985 /* Implementation of function hook 'this_id' in
2986 'struct frame_uwnind'. */
2989 arm_m_exception_this_id (struct frame_info
*this_frame
,
2991 struct frame_id
*this_id
)
2993 struct arm_prologue_cache
*cache
;
2995 if (*this_cache
== NULL
)
2996 *this_cache
= arm_m_exception_cache (this_frame
);
2997 cache
= (struct arm_prologue_cache
*) *this_cache
;
2999 /* Our frame ID for a stub frame is the current SP and LR. */
3000 *this_id
= frame_id_build (cache
->prev_sp
,
3001 get_frame_pc (this_frame
));
3004 /* Implementation of function hook 'prev_register' in
3005 'struct frame_uwnind'. */
3007 static struct value
*
3008 arm_m_exception_prev_register (struct frame_info
*this_frame
,
3012 struct arm_prologue_cache
*cache
;
3014 if (*this_cache
== NULL
)
3015 *this_cache
= arm_m_exception_cache (this_frame
);
3016 cache
= (struct arm_prologue_cache
*) *this_cache
;
3018 /* The value was already reconstructed into PREV_SP. */
3019 if (prev_regnum
== ARM_SP_REGNUM
)
3020 return frame_unwind_got_constant (this_frame
, prev_regnum
,
3023 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
3027 /* Implementation of function hook 'sniffer' in
3028 'struct frame_uwnind'. */
3031 arm_m_exception_unwind_sniffer (const struct frame_unwind
*self
,
3032 struct frame_info
*this_frame
,
3033 void **this_prologue_cache
)
3035 CORE_ADDR this_pc
= get_frame_pc (this_frame
);
3037 /* No need to check is_m; this sniffer is only registered for
3038 M-profile architectures. */
3040 /* Check if exception frame returns to a magic PC value. */
3041 return arm_m_addr_is_magic (this_pc
);
3044 /* Frame unwinder for M-profile exceptions. */
3046 struct frame_unwind arm_m_exception_unwind
=
3049 default_frame_unwind_stop_reason
,
3050 arm_m_exception_this_id
,
3051 arm_m_exception_prev_register
,
3053 arm_m_exception_unwind_sniffer
3057 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
3059 struct arm_prologue_cache
*cache
;
3061 if (*this_cache
== NULL
)
3062 *this_cache
= arm_make_prologue_cache (this_frame
);
3063 cache
= (struct arm_prologue_cache
*) *this_cache
;
3065 return cache
->prev_sp
- cache
->framesize
;
3068 struct frame_base arm_normal_base
= {
3069 &arm_prologue_unwind
,
3070 arm_normal_frame_base
,
3071 arm_normal_frame_base
,
3072 arm_normal_frame_base
3075 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3076 dummy frame. The frame ID's base needs to match the TOS value
3077 saved by save_dummy_frame_tos() and returned from
3078 arm_push_dummy_call, and the PC needs to match the dummy frame's
3081 static struct frame_id
3082 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3084 return frame_id_build (get_frame_register_unsigned (this_frame
,
3086 get_frame_pc (this_frame
));
3089 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3090 be used to construct the previous frame's ID, after looking up the
3091 containing function). */
3094 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3097 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
3098 return arm_addr_bits_remove (gdbarch
, pc
);
3102 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3104 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
3107 static struct value
*
3108 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
3111 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
3113 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
3118 /* The PC is normally copied from the return column, which
3119 describes saves of LR. However, that version may have an
3120 extra bit set to indicate Thumb state. The bit is not
3122 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3123 return frame_unwind_got_constant (this_frame
, regnum
,
3124 arm_addr_bits_remove (gdbarch
, lr
));
3127 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3128 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
3129 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3130 if (IS_THUMB_ADDR (lr
))
3134 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
3137 internal_error (__FILE__
, __LINE__
,
3138 _("Unexpected register %d"), regnum
);
3143 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3144 struct dwarf2_frame_state_reg
*reg
,
3145 struct frame_info
*this_frame
)
3151 reg
->how
= DWARF2_FRAME_REG_FN
;
3152 reg
->loc
.fn
= arm_dwarf2_prev_register
;
3155 reg
->how
= DWARF2_FRAME_REG_CFA
;
3160 /* Implement the stack_frame_destroyed_p gdbarch method. */
3163 thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3165 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3166 unsigned int insn
, insn2
;
3167 int found_return
= 0, found_stack_adjust
= 0;
3168 CORE_ADDR func_start
, func_end
;
3172 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3175 /* The epilogue is a sequence of instructions along the following lines:
3177 - add stack frame size to SP or FP
3178 - [if frame pointer used] restore SP from FP
3179 - restore registers from SP [may include PC]
3180 - a return-type instruction [if PC wasn't already restored]
3182 In a first pass, we scan forward from the current PC and verify the
3183 instructions we find as compatible with this sequence, ending in a
3186 However, this is not sufficient to distinguish indirect function calls
3187 within a function from indirect tail calls in the epilogue in some cases.
3188 Therefore, if we didn't already find any SP-changing instruction during
3189 forward scan, we add a backward scanning heuristic to ensure we actually
3190 are in the epilogue. */
3193 while (scan_pc
< func_end
&& !found_return
)
3195 if (target_read_memory (scan_pc
, buf
, 2))
3199 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3201 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3203 else if (insn
== 0x46f7) /* mov pc, lr */
3205 else if (thumb_instruction_restores_sp (insn
))
3207 if ((insn
& 0xff00) == 0xbd00) /* pop <registers, PC> */
3210 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instruction */
3212 if (target_read_memory (scan_pc
, buf
, 2))
3216 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3218 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3220 if (insn2
& 0x8000) /* <registers> include PC. */
3223 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3224 && (insn2
& 0x0fff) == 0x0b04)
3226 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
3229 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3230 && (insn2
& 0x0e00) == 0x0a00)
3242 /* Since any instruction in the epilogue sequence, with the possible
3243 exception of return itself, updates the stack pointer, we need to
3244 scan backwards for at most one instruction. Try either a 16-bit or
3245 a 32-bit instruction. This is just a heuristic, so we do not worry
3246 too much about false positives. */
3248 if (pc
- 4 < func_start
)
3250 if (target_read_memory (pc
- 4, buf
, 4))
3253 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3254 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
3256 if (thumb_instruction_restores_sp (insn2
))
3257 found_stack_adjust
= 1;
3258 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3259 found_stack_adjust
= 1;
3260 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3261 && (insn2
& 0x0fff) == 0x0b04)
3262 found_stack_adjust
= 1;
3263 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3264 && (insn2
& 0x0e00) == 0x0a00)
3265 found_stack_adjust
= 1;
3267 return found_stack_adjust
;
3271 arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3273 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3276 CORE_ADDR func_start
, func_end
;
3278 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3281 /* We are in the epilogue if the previous instruction was a stack
3282 adjustment and the next instruction is a possible return (bx, mov
3283 pc, or pop). We could have to scan backwards to find the stack
3284 adjustment, or forwards to find the return, but this is a decent
3285 approximation. First scan forwards. */
3288 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3289 if (bits (insn
, 28, 31) != INST_NV
)
3291 if ((insn
& 0x0ffffff0) == 0x012fff10)
3294 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
3297 else if ((insn
& 0x0fff0000) == 0x08bd0000
3298 && (insn
& 0x0000c000) != 0)
3299 /* POP (LDMIA), including PC or LR. */
3306 /* Scan backwards. This is just a heuristic, so do not worry about
3307 false positives from mode changes. */
3309 if (pc
< func_start
+ 4)
3312 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
3313 if (arm_instruction_restores_sp (insn
))
3319 /* Implement the stack_frame_destroyed_p gdbarch method. */
3322 arm_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3324 if (arm_pc_is_thumb (gdbarch
, pc
))
3325 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
3327 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
3330 /* When arguments must be pushed onto the stack, they go on in reverse
3331 order. The code below implements a FILO (stack) to do this. */
3336 struct stack_item
*prev
;
3340 static struct stack_item
*
3341 push_stack_item (struct stack_item
*prev
, const gdb_byte
*contents
, int len
)
3343 struct stack_item
*si
;
3344 si
= XNEW (struct stack_item
);
3345 si
->data
= (gdb_byte
*) xmalloc (len
);
3348 memcpy (si
->data
, contents
, len
);
3352 static struct stack_item
*
3353 pop_stack_item (struct stack_item
*si
)
3355 struct stack_item
*dead
= si
;
3363 /* Return the alignment (in bytes) of the given type. */
3366 arm_type_align (struct type
*t
)
3372 t
= check_typedef (t
);
3373 switch (TYPE_CODE (t
))
3376 /* Should never happen. */
3377 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
3381 case TYPE_CODE_ENUM
:
3385 case TYPE_CODE_RANGE
:
3387 case TYPE_CODE_CHAR
:
3388 case TYPE_CODE_BOOL
:
3389 return TYPE_LENGTH (t
);
3391 case TYPE_CODE_ARRAY
:
3392 if (TYPE_VECTOR (t
))
3394 /* Use the natural alignment for vector types (the same for
3395 scalar type), but the maximum alignment is 64-bit. */
3396 if (TYPE_LENGTH (t
) > 8)
3399 return TYPE_LENGTH (t
);
3402 return arm_type_align (TYPE_TARGET_TYPE (t
));
3403 case TYPE_CODE_COMPLEX
:
3404 return arm_type_align (TYPE_TARGET_TYPE (t
));
3406 case TYPE_CODE_STRUCT
:
3407 case TYPE_CODE_UNION
:
3409 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
3411 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
3419 /* Possible base types for a candidate for passing and returning in
3422 enum arm_vfp_cprc_base_type
3431 /* The length of one element of base type B. */
3434 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
3438 case VFP_CPRC_SINGLE
:
3440 case VFP_CPRC_DOUBLE
:
3442 case VFP_CPRC_VEC64
:
3444 case VFP_CPRC_VEC128
:
3447 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3452 /* The character ('s', 'd' or 'q') for the type of VFP register used
3453 for passing base type B. */
3456 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
3460 case VFP_CPRC_SINGLE
:
3462 case VFP_CPRC_DOUBLE
:
3464 case VFP_CPRC_VEC64
:
3466 case VFP_CPRC_VEC128
:
3469 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3474 /* Determine whether T may be part of a candidate for passing and
3475 returning in VFP registers, ignoring the limit on the total number
3476 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3477 classification of the first valid component found; if it is not
3478 VFP_CPRC_UNKNOWN, all components must have the same classification
3479 as *BASE_TYPE. If it is found that T contains a type not permitted
3480 for passing and returning in VFP registers, a type differently
3481 classified from *BASE_TYPE, or two types differently classified
3482 from each other, return -1, otherwise return the total number of
3483 base-type elements found (possibly 0 in an empty structure or
3484 array). Vector types are not currently supported, matching the
3485 generic AAPCS support. */
3488 arm_vfp_cprc_sub_candidate (struct type
*t
,
3489 enum arm_vfp_cprc_base_type
*base_type
)
3491 t
= check_typedef (t
);
3492 switch (TYPE_CODE (t
))
3495 switch (TYPE_LENGTH (t
))
3498 if (*base_type
== VFP_CPRC_UNKNOWN
)
3499 *base_type
= VFP_CPRC_SINGLE
;
3500 else if (*base_type
!= VFP_CPRC_SINGLE
)
3505 if (*base_type
== VFP_CPRC_UNKNOWN
)
3506 *base_type
= VFP_CPRC_DOUBLE
;
3507 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3516 case TYPE_CODE_COMPLEX
:
3517 /* Arguments of complex T where T is one of the types float or
3518 double get treated as if they are implemented as:
3527 switch (TYPE_LENGTH (t
))
3530 if (*base_type
== VFP_CPRC_UNKNOWN
)
3531 *base_type
= VFP_CPRC_SINGLE
;
3532 else if (*base_type
!= VFP_CPRC_SINGLE
)
3537 if (*base_type
== VFP_CPRC_UNKNOWN
)
3538 *base_type
= VFP_CPRC_DOUBLE
;
3539 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3548 case TYPE_CODE_ARRAY
:
3550 if (TYPE_VECTOR (t
))
3552 /* A 64-bit or 128-bit containerized vector type are VFP
3554 switch (TYPE_LENGTH (t
))
3557 if (*base_type
== VFP_CPRC_UNKNOWN
)
3558 *base_type
= VFP_CPRC_VEC64
;
3561 if (*base_type
== VFP_CPRC_UNKNOWN
)
3562 *base_type
= VFP_CPRC_VEC128
;
3573 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
),
3577 if (TYPE_LENGTH (t
) == 0)
3579 gdb_assert (count
== 0);
3582 else if (count
== 0)
3584 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3585 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
3586 return TYPE_LENGTH (t
) / unitlen
;
3591 case TYPE_CODE_STRUCT
:
3596 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3600 if (!field_is_static (&TYPE_FIELD (t
, i
)))
3601 sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3603 if (sub_count
== -1)
3607 if (TYPE_LENGTH (t
) == 0)
3609 gdb_assert (count
== 0);
3612 else if (count
== 0)
3614 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3615 if (TYPE_LENGTH (t
) != unitlen
* count
)
3620 case TYPE_CODE_UNION
:
3625 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3627 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3629 if (sub_count
== -1)
3631 count
= (count
> sub_count
? count
: sub_count
);
3633 if (TYPE_LENGTH (t
) == 0)
3635 gdb_assert (count
== 0);
3638 else if (count
== 0)
3640 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3641 if (TYPE_LENGTH (t
) != unitlen
* count
)
3653 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3654 if passed to or returned from a non-variadic function with the VFP
3655 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3656 *BASE_TYPE to the base type for T and *COUNT to the number of
3657 elements of that base type before returning. */
3660 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
3663 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
3664 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
3665 if (c
<= 0 || c
> 4)
3672 /* Return 1 if the VFP ABI should be used for passing arguments to and
3673 returning values from a function of type FUNC_TYPE, 0
3677 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
3679 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3680 /* Variadic functions always use the base ABI. Assume that functions
3681 without debug info are not variadic. */
3682 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
3684 /* The VFP ABI is only supported as a variant of AAPCS. */
3685 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
3687 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
3690 /* We currently only support passing parameters in integer registers, which
3691 conforms with GCC's default model, and VFP argument passing following
3692 the VFP variant of AAPCS. Several other variants exist and
3693 we should probably support some of them based on the selected ABI. */
3696 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3697 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3698 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3699 CORE_ADDR struct_addr
)
3701 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3705 struct stack_item
*si
= NULL
;
3708 unsigned vfp_regs_free
= (1 << 16) - 1;
3710 /* Determine the type of this function and whether the VFP ABI
3712 ftype
= check_typedef (value_type (function
));
3713 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
3714 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
3715 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
3717 /* Set the return address. For the ARM, the return breakpoint is
3718 always at BP_ADDR. */
3719 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
3721 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
3723 /* Walk through the list of args and determine how large a temporary
3724 stack is required. Need to take care here as structs may be
3725 passed on the stack, and we have to push them. */
3728 argreg
= ARM_A1_REGNUM
;
3731 /* The struct_return pointer occupies the first parameter
3732 passing register. */
3736 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
3737 gdbarch_register_name (gdbarch
, argreg
),
3738 paddress (gdbarch
, struct_addr
));
3739 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
3743 for (argnum
= 0; argnum
< nargs
; argnum
++)
3746 struct type
*arg_type
;
3747 struct type
*target_type
;
3748 enum type_code typecode
;
3749 const bfd_byte
*val
;
3751 enum arm_vfp_cprc_base_type vfp_base_type
;
3753 int may_use_core_reg
= 1;
3755 arg_type
= check_typedef (value_type (args
[argnum
]));
3756 len
= TYPE_LENGTH (arg_type
);
3757 target_type
= TYPE_TARGET_TYPE (arg_type
);
3758 typecode
= TYPE_CODE (arg_type
);
3759 val
= value_contents (args
[argnum
]);
3761 align
= arm_type_align (arg_type
);
3762 /* Round alignment up to a whole number of words. */
3763 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
3764 /* Different ABIs have different maximum alignments. */
3765 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
3767 /* The APCS ABI only requires word alignment. */
3768 align
= INT_REGISTER_SIZE
;
3772 /* The AAPCS requires at most doubleword alignment. */
3773 if (align
> INT_REGISTER_SIZE
* 2)
3774 align
= INT_REGISTER_SIZE
* 2;
3778 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
3786 /* Because this is a CPRC it cannot go in a core register or
3787 cause a core register to be skipped for alignment.
3788 Either it goes in VFP registers and the rest of this loop
3789 iteration is skipped for this argument, or it goes on the
3790 stack (and the stack alignment code is correct for this
3792 may_use_core_reg
= 0;
3794 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
3795 shift
= unit_length
/ 4;
3796 mask
= (1 << (shift
* vfp_base_count
)) - 1;
3797 for (regno
= 0; regno
< 16; regno
+= shift
)
3798 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
3807 vfp_regs_free
&= ~(mask
<< regno
);
3808 reg_scaled
= regno
/ shift
;
3809 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
3810 for (i
= 0; i
< vfp_base_count
; i
++)
3814 if (reg_char
== 'q')
3815 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
3816 val
+ i
* unit_length
);
3819 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d",
3820 reg_char
, reg_scaled
+ i
);
3821 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3823 regcache_cooked_write (regcache
, regnum
,
3824 val
+ i
* unit_length
);
3831 /* This CPRC could not go in VFP registers, so all VFP
3832 registers are now marked as used. */
3837 /* Push stack padding for dowubleword alignment. */
3838 if (nstack
& (align
- 1))
3840 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3841 nstack
+= INT_REGISTER_SIZE
;
3844 /* Doubleword aligned quantities must go in even register pairs. */
3845 if (may_use_core_reg
3846 && argreg
<= ARM_LAST_ARG_REGNUM
3847 && align
> INT_REGISTER_SIZE
3851 /* If the argument is a pointer to a function, and it is a
3852 Thumb function, create a LOCAL copy of the value and set
3853 the THUMB bit in it. */
3854 if (TYPE_CODE_PTR
== typecode
3855 && target_type
!= NULL
3856 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
3858 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
3859 if (arm_pc_is_thumb (gdbarch
, regval
))
3861 bfd_byte
*copy
= (bfd_byte
*) alloca (len
);
3862 store_unsigned_integer (copy
, len
, byte_order
,
3863 MAKE_THUMB_ADDR (regval
));
3868 /* Copy the argument to general registers or the stack in
3869 register-sized pieces. Large arguments are split between
3870 registers and stack. */
3873 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
3875 = extract_unsigned_integer (val
, partial_len
, byte_order
);
3877 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
3879 /* The argument is being passed in a general purpose
3881 if (byte_order
== BFD_ENDIAN_BIG
)
3882 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
3884 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
3886 gdbarch_register_name
3888 phex (regval
, INT_REGISTER_SIZE
));
3889 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3894 gdb_byte buf
[INT_REGISTER_SIZE
];
3896 memset (buf
, 0, sizeof (buf
));
3897 store_unsigned_integer (buf
, partial_len
, byte_order
, regval
);
3899 /* Push the arguments onto the stack. */
3901 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
3903 si
= push_stack_item (si
, buf
, INT_REGISTER_SIZE
);
3904 nstack
+= INT_REGISTER_SIZE
;
3911 /* If we have an odd number of words to push, then decrement the stack
3912 by one word now, so first stack argument will be dword aligned. */
3919 write_memory (sp
, si
->data
, si
->len
);
3920 si
= pop_stack_item (si
);
3923 /* Finally, update teh SP register. */
3924 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
3930 /* Always align the frame to an 8-byte boundary. This is required on
3931 some platforms and harmless on the rest. */
3934 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3936 /* Align the stack to eight bytes. */
3937 return sp
& ~ (CORE_ADDR
) 7;
3941 print_fpu_flags (struct ui_file
*file
, int flags
)
3943 if (flags
& (1 << 0))
3944 fputs_filtered ("IVO ", file
);
3945 if (flags
& (1 << 1))
3946 fputs_filtered ("DVZ ", file
);
3947 if (flags
& (1 << 2))
3948 fputs_filtered ("OFL ", file
);
3949 if (flags
& (1 << 3))
3950 fputs_filtered ("UFL ", file
);
3951 if (flags
& (1 << 4))
3952 fputs_filtered ("INX ", file
);
3953 fputc_filtered ('\n', file
);
3956 /* Print interesting information about the floating point processor
3957 (if present) or emulator. */
3959 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
3960 struct frame_info
*frame
, const char *args
)
3962 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
3965 type
= (status
>> 24) & 127;
3966 if (status
& (1 << 31))
3967 fprintf_filtered (file
, _("Hardware FPU type %d\n"), type
);
3969 fprintf_filtered (file
, _("Software FPU type %d\n"), type
);
3970 /* i18n: [floating point unit] mask */
3971 fputs_filtered (_("mask: "), file
);
3972 print_fpu_flags (file
, status
>> 16);
3973 /* i18n: [floating point unit] flags */
3974 fputs_filtered (_("flags: "), file
);
3975 print_fpu_flags (file
, status
);
3978 /* Construct the ARM extended floating point type. */
3979 static struct type
*
3980 arm_ext_type (struct gdbarch
*gdbarch
)
3982 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3984 if (!tdep
->arm_ext_type
)
3986 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
3987 floatformats_arm_ext
);
3989 return tdep
->arm_ext_type
;
3992 static struct type
*
3993 arm_neon_double_type (struct gdbarch
*gdbarch
)
3995 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3997 if (tdep
->neon_double_type
== NULL
)
3999 struct type
*t
, *elem
;
4001 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
4003 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4004 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
4005 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4006 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
4007 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4008 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
4009 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4010 append_composite_type_field (t
, "u64", elem
);
4011 elem
= builtin_type (gdbarch
)->builtin_float
;
4012 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
4013 elem
= builtin_type (gdbarch
)->builtin_double
;
4014 append_composite_type_field (t
, "f64", elem
);
4016 TYPE_VECTOR (t
) = 1;
4017 TYPE_NAME (t
) = "neon_d";
4018 tdep
->neon_double_type
= t
;
4021 return tdep
->neon_double_type
;
4024 /* FIXME: The vector types are not correctly ordered on big-endian
4025 targets. Just as s0 is the low bits of d0, d0[0] is also the low
4026 bits of d0 - regardless of what unit size is being held in d0. So
4027 the offset of the first uint8 in d0 is 7, but the offset of the
4028 first float is 4. This code works as-is for little-endian
4031 static struct type
*
4032 arm_neon_quad_type (struct gdbarch
*gdbarch
)
4034 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4036 if (tdep
->neon_quad_type
== NULL
)
4038 struct type
*t
, *elem
;
4040 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
4042 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4043 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
4044 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4045 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
4046 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4047 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
4048 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4049 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
4050 elem
= builtin_type (gdbarch
)->builtin_float
;
4051 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
4052 elem
= builtin_type (gdbarch
)->builtin_double
;
4053 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
4055 TYPE_VECTOR (t
) = 1;
4056 TYPE_NAME (t
) = "neon_q";
4057 tdep
->neon_quad_type
= t
;
4060 return tdep
->neon_quad_type
;
4063 /* Return the GDB type object for the "standard" data type of data in
4066 static struct type
*
4067 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
4069 int num_regs
= gdbarch_num_regs (gdbarch
);
4071 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
4072 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
4073 return builtin_type (gdbarch
)->builtin_float
;
4075 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
4076 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
4077 return arm_neon_quad_type (gdbarch
);
4079 /* If the target description has register information, we are only
4080 in this function so that we can override the types of
4081 double-precision registers for NEON. */
4082 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
4084 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
4086 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
4087 && TYPE_CODE (t
) == TYPE_CODE_FLT
4088 && gdbarch_tdep (gdbarch
)->have_neon
)
4089 return arm_neon_double_type (gdbarch
);
4094 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
4096 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
4097 return builtin_type (gdbarch
)->builtin_void
;
4099 return arm_ext_type (gdbarch
);
4101 else if (regnum
== ARM_SP_REGNUM
)
4102 return builtin_type (gdbarch
)->builtin_data_ptr
;
4103 else if (regnum
== ARM_PC_REGNUM
)
4104 return builtin_type (gdbarch
)->builtin_func_ptr
;
4105 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
4106 /* These registers are only supported on targets which supply
4107 an XML description. */
4108 return builtin_type (gdbarch
)->builtin_int0
;
4110 return builtin_type (gdbarch
)->builtin_uint32
;
4113 /* Map a DWARF register REGNUM onto the appropriate GDB register
4117 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
4119 /* Core integer regs. */
4120 if (reg
>= 0 && reg
<= 15)
4123 /* Legacy FPA encoding. These were once used in a way which
4124 overlapped with VFP register numbering, so their use is
4125 discouraged, but GDB doesn't support the ARM toolchain
4126 which used them for VFP. */
4127 if (reg
>= 16 && reg
<= 23)
4128 return ARM_F0_REGNUM
+ reg
- 16;
4130 /* New assignments for the FPA registers. */
4131 if (reg
>= 96 && reg
<= 103)
4132 return ARM_F0_REGNUM
+ reg
- 96;
4134 /* WMMX register assignments. */
4135 if (reg
>= 104 && reg
<= 111)
4136 return ARM_WCGR0_REGNUM
+ reg
- 104;
4138 if (reg
>= 112 && reg
<= 127)
4139 return ARM_WR0_REGNUM
+ reg
- 112;
4141 if (reg
>= 192 && reg
<= 199)
4142 return ARM_WC0_REGNUM
+ reg
- 192;
4144 /* VFP v2 registers. A double precision value is actually
4145 in d1 rather than s2, but the ABI only defines numbering
4146 for the single precision registers. This will "just work"
4147 in GDB for little endian targets (we'll read eight bytes,
4148 starting in s0 and then progressing to s1), but will be
4149 reversed on big endian targets with VFP. This won't
4150 be a problem for the new Neon quad registers; you're supposed
4151 to use DW_OP_piece for those. */
4152 if (reg
>= 64 && reg
<= 95)
4156 xsnprintf (name_buf
, sizeof (name_buf
), "s%d", reg
- 64);
4157 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4161 /* VFP v3 / Neon registers. This range is also used for VFP v2
4162 registers, except that it now describes d0 instead of s0. */
4163 if (reg
>= 256 && reg
<= 287)
4167 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", reg
- 256);
4168 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4175 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4177 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
4180 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
4182 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
4183 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
4185 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
4186 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
4188 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
4189 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
4191 if (reg
< NUM_GREGS
)
4192 return SIM_ARM_R0_REGNUM
+ reg
;
4195 if (reg
< NUM_FREGS
)
4196 return SIM_ARM_FP0_REGNUM
+ reg
;
4199 if (reg
< NUM_SREGS
)
4200 return SIM_ARM_FPS_REGNUM
+ reg
;
4203 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
4206 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4207 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4208 It is thought that this is is the floating-point register format on
4209 little-endian systems. */
4212 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
4213 void *dbl
, int endianess
)
4217 if (endianess
== BFD_ENDIAN_BIG
)
4218 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
4220 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4222 floatformat_from_doublest (fmt
, &d
, dbl
);
4226 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
4231 floatformat_to_doublest (fmt
, ptr
, &d
);
4232 if (endianess
== BFD_ENDIAN_BIG
)
4233 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
4235 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4239 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
4240 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
4241 NULL if an error occurs. BUF is freed. */
4244 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
4245 int old_len
, int new_len
)
4248 int bytes_to_read
= new_len
- old_len
;
4250 new_buf
= (gdb_byte
*) xmalloc (new_len
);
4251 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
4253 if (target_read_code (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
4261 /* An IT block is at most the 2-byte IT instruction followed by
4262 four 4-byte instructions. The furthest back we must search to
4263 find an IT block that affects the current instruction is thus
4264 2 + 3 * 4 == 14 bytes. */
4265 #define MAX_IT_BLOCK_PREFIX 14
4267 /* Use a quick scan if there are more than this many bytes of
4269 #define IT_SCAN_THRESHOLD 32
4271 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
4272 A breakpoint in an IT block may not be hit, depending on the
4275 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
4279 CORE_ADDR boundary
, func_start
;
4281 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
4282 int i
, any
, last_it
, last_it_count
;
4284 /* If we are using BKPT breakpoints, none of this is necessary. */
4285 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
4288 /* ARM mode does not have this problem. */
4289 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
4292 /* We are setting a breakpoint in Thumb code that could potentially
4293 contain an IT block. The first step is to find how much Thumb
4294 code there is; we do not need to read outside of known Thumb
4296 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
4298 /* Thumb-2 code must have mapping symbols to have a chance. */
4301 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
4303 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
4304 && func_start
> boundary
)
4305 boundary
= func_start
;
4307 /* Search for a candidate IT instruction. We have to do some fancy
4308 footwork to distinguish a real IT instruction from the second
4309 half of a 32-bit instruction, but there is no need for that if
4310 there's no candidate. */
4311 buf_len
= std::min (bpaddr
- boundary
, (CORE_ADDR
) MAX_IT_BLOCK_PREFIX
);
4313 /* No room for an IT instruction. */
4316 buf
= (gdb_byte
*) xmalloc (buf_len
);
4317 if (target_read_code (bpaddr
- buf_len
, buf
, buf_len
) != 0)
4320 for (i
= 0; i
< buf_len
; i
+= 2)
4322 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4323 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4336 /* OK, the code bytes before this instruction contain at least one
4337 halfword which resembles an IT instruction. We know that it's
4338 Thumb code, but there are still two possibilities. Either the
4339 halfword really is an IT instruction, or it is the second half of
4340 a 32-bit Thumb instruction. The only way we can tell is to
4341 scan forwards from a known instruction boundary. */
4342 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
4346 /* There's a lot of code before this instruction. Start with an
4347 optimistic search; it's easy to recognize halfwords that can
4348 not be the start of a 32-bit instruction, and use that to
4349 lock on to the instruction boundaries. */
4350 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
4353 buf_len
= IT_SCAN_THRESHOLD
;
4356 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
4358 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4359 if (thumb_insn_size (inst1
) == 2)
4366 /* At this point, if DEFINITE, BUF[I] is the first place we
4367 are sure that we know the instruction boundaries, and it is far
4368 enough from BPADDR that we could not miss an IT instruction
4369 affecting BPADDR. If ! DEFINITE, give up - start from a
4373 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
,
4377 buf_len
= bpaddr
- boundary
;
4383 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
4386 buf_len
= bpaddr
- boundary
;
4390 /* Scan forwards. Find the last IT instruction before BPADDR. */
4395 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4397 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4402 else if (inst1
& 0x0002)
4404 else if (inst1
& 0x0004)
4409 i
+= thumb_insn_size (inst1
);
4415 /* There wasn't really an IT instruction after all. */
4418 if (last_it_count
< 1)
4419 /* It was too far away. */
4422 /* This really is a trouble spot. Move the breakpoint to the IT
4424 return bpaddr
- buf_len
+ last_it
;
4427 /* ARM displaced stepping support.
4429 Generally ARM displaced stepping works as follows:
4431 1. When an instruction is to be single-stepped, it is first decoded by
4432 arm_process_displaced_insn. Depending on the type of instruction, it is
4433 then copied to a scratch location, possibly in a modified form. The
4434 copy_* set of functions performs such modification, as necessary. A
4435 breakpoint is placed after the modified instruction in the scratch space
4436 to return control to GDB. Note in particular that instructions which
4437 modify the PC will no longer do so after modification.
4439 2. The instruction is single-stepped, by setting the PC to the scratch
4440 location address, and resuming. Control returns to GDB when the
4443 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
4444 function used for the current instruction. This function's job is to
4445 put the CPU/memory state back to what it would have been if the
4446 instruction had been executed unmodified in its original location. */
4448 /* NOP instruction (mov r0, r0). */
4449 #define ARM_NOP 0xe1a00000
4450 #define THUMB_NOP 0x4600
4452 /* Helper for register reads for displaced stepping. In particular, this
4453 returns the PC as it would be seen by the instruction at its original
4457 displaced_read_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4461 CORE_ADDR from
= dsc
->insn_addr
;
4463 if (regno
== ARM_PC_REGNUM
)
4465 /* Compute pipeline offset:
4466 - When executing an ARM instruction, PC reads as the address of the
4467 current instruction plus 8.
4468 - When executing a Thumb instruction, PC reads as the address of the
4469 current instruction plus 4. */
4476 if (debug_displaced
)
4477 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
4478 (unsigned long) from
);
4479 return (ULONGEST
) from
;
4483 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
4484 if (debug_displaced
)
4485 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
4486 regno
, (unsigned long) ret
);
4492 displaced_in_arm_mode (struct regcache
*regs
)
4495 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
4497 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4499 return (ps
& t_bit
) == 0;
4502 /* Write to the PC as from a branch instruction. */
4505 branch_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4509 /* Note: If bits 0/1 are set, this branch would be unpredictable for
4510 architecture versions < 6. */
4511 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4512 val
& ~(ULONGEST
) 0x3);
4514 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4515 val
& ~(ULONGEST
) 0x1);
4518 /* Write to the PC as from a branch-exchange instruction. */
4521 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
4524 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
4526 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4530 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
4531 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
4533 else if ((val
& 2) == 0)
4535 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4536 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
4540 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
4541 mode, align dest to 4 bytes). */
4542 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
4543 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4544 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
4548 /* Write to the PC as if from a load instruction. */
4551 load_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4554 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
4555 bx_write_pc (regs
, val
);
4557 branch_write_pc (regs
, dsc
, val
);
4560 /* Write to the PC as if from an ALU instruction. */
4563 alu_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4566 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && !dsc
->is_thumb
)
4567 bx_write_pc (regs
, val
);
4569 branch_write_pc (regs
, dsc
, val
);
4572 /* Helper for writing to registers for displaced stepping. Writing to the PC
4573 has a varying effects depending on the instruction which does the write:
4574 this is controlled by the WRITE_PC argument. */
4577 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4578 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
4580 if (regno
== ARM_PC_REGNUM
)
4582 if (debug_displaced
)
4583 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
4584 (unsigned long) val
);
4587 case BRANCH_WRITE_PC
:
4588 branch_write_pc (regs
, dsc
, val
);
4592 bx_write_pc (regs
, val
);
4596 load_write_pc (regs
, dsc
, val
);
4600 alu_write_pc (regs
, dsc
, val
);
4603 case CANNOT_WRITE_PC
:
4604 warning (_("Instruction wrote to PC in an unexpected way when "
4605 "single-stepping"));
4609 internal_error (__FILE__
, __LINE__
,
4610 _("Invalid argument to displaced_write_reg"));
4613 dsc
->wrote_to_pc
= 1;
4617 if (debug_displaced
)
4618 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
4619 regno
, (unsigned long) val
);
4620 regcache_cooked_write_unsigned (regs
, regno
, val
);
4624 /* This function is used to concisely determine if an instruction INSN
4625 references PC. Register fields of interest in INSN should have the
4626 corresponding fields of BITMASK set to 0b1111. The function
4627 returns return 1 if any of these fields in INSN reference the PC
4628 (also 0b1111, r15), else it returns 0. */
4631 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
4633 uint32_t lowbit
= 1;
4635 while (bitmask
!= 0)
4639 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
4645 mask
= lowbit
* 0xf;
4647 if ((insn
& mask
) == mask
)
4656 /* The simplest copy function. Many instructions have the same effect no
4657 matter what address they are executed at: in those cases, use this. */
4660 arm_copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
4661 const char *iname
, struct displaced_step_closure
*dsc
)
4663 if (debug_displaced
)
4664 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
4665 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
4668 dsc
->modinsn
[0] = insn
;
4674 thumb_copy_unmodified_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
4675 uint16_t insn2
, const char *iname
,
4676 struct displaced_step_closure
*dsc
)
4678 if (debug_displaced
)
4679 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x %.4x, "
4680 "opcode/class '%s' unmodified\n", insn1
, insn2
,
4683 dsc
->modinsn
[0] = insn1
;
4684 dsc
->modinsn
[1] = insn2
;
4690 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
4693 thumb_copy_unmodified_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
4695 struct displaced_step_closure
*dsc
)
4697 if (debug_displaced
)
4698 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x, "
4699 "opcode/class '%s' unmodified\n", insn
,
4702 dsc
->modinsn
[0] = insn
;
4707 /* Preload instructions with immediate offset. */
4710 cleanup_preload (struct gdbarch
*gdbarch
,
4711 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4713 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4714 if (!dsc
->u
.preload
.immed
)
4715 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
4719 install_preload (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4720 struct displaced_step_closure
*dsc
, unsigned int rn
)
4723 /* Preload instructions:
4725 {pli/pld} [rn, #+/-imm]
4727 {pli/pld} [r0, #+/-imm]. */
4729 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4730 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4731 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4732 dsc
->u
.preload
.immed
= 1;
4734 dsc
->cleanup
= &cleanup_preload
;
4738 arm_copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4739 struct displaced_step_closure
*dsc
)
4741 unsigned int rn
= bits (insn
, 16, 19);
4743 if (!insn_references_pc (insn
, 0x000f0000ul
))
4744 return arm_copy_unmodified (gdbarch
, insn
, "preload", dsc
);
4746 if (debug_displaced
)
4747 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4748 (unsigned long) insn
);
4750 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4752 install_preload (gdbarch
, regs
, dsc
, rn
);
4758 thumb2_copy_preload (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
4759 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4761 unsigned int rn
= bits (insn1
, 0, 3);
4762 unsigned int u_bit
= bit (insn1
, 7);
4763 int imm12
= bits (insn2
, 0, 11);
4766 if (rn
!= ARM_PC_REGNUM
)
4767 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "preload", dsc
);
4769 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
4770 PLD (literal) Encoding T1. */
4771 if (debug_displaced
)
4772 fprintf_unfiltered (gdb_stdlog
,
4773 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
4774 (unsigned int) dsc
->insn_addr
, u_bit
? '+' : '-',
4780 /* Rewrite instruction {pli/pld} PC imm12 into:
4781 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
4785 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
4787 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4788 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4790 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
4792 displaced_write_reg (regs
, dsc
, 0, pc_val
, CANNOT_WRITE_PC
);
4793 displaced_write_reg (regs
, dsc
, 1, imm12
, CANNOT_WRITE_PC
);
4794 dsc
->u
.preload
.immed
= 0;
4796 /* {pli/pld} [r0, r1] */
4797 dsc
->modinsn
[0] = insn1
& 0xfff0;
4798 dsc
->modinsn
[1] = 0xf001;
4801 dsc
->cleanup
= &cleanup_preload
;
4805 /* Preload instructions with register offset. */
4808 install_preload_reg(struct gdbarch
*gdbarch
, struct regcache
*regs
,
4809 struct displaced_step_closure
*dsc
, unsigned int rn
,
4812 ULONGEST rn_val
, rm_val
;
4814 /* Preload register-offset instructions:
4816 {pli/pld} [rn, rm {, shift}]
4818 {pli/pld} [r0, r1 {, shift}]. */
4820 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4821 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4822 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4823 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
4824 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4825 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
4826 dsc
->u
.preload
.immed
= 0;
4828 dsc
->cleanup
= &cleanup_preload
;
4832 arm_copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
4833 struct regcache
*regs
,
4834 struct displaced_step_closure
*dsc
)
4836 unsigned int rn
= bits (insn
, 16, 19);
4837 unsigned int rm
= bits (insn
, 0, 3);
4840 if (!insn_references_pc (insn
, 0x000f000ful
))
4841 return arm_copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
4843 if (debug_displaced
)
4844 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4845 (unsigned long) insn
);
4847 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
4849 install_preload_reg (gdbarch
, regs
, dsc
, rn
, rm
);
4853 /* Copy/cleanup coprocessor load and store instructions. */
4856 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
4857 struct regcache
*regs
,
4858 struct displaced_step_closure
*dsc
)
4860 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 0);
4862 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4864 if (dsc
->u
.ldst
.writeback
)
4865 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
4869 install_copro_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4870 struct displaced_step_closure
*dsc
,
4871 int writeback
, unsigned int rn
)
4875 /* Coprocessor load/store instructions:
4877 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
4879 {stc/stc2} [r0, #+/-imm].
4881 ldc/ldc2 are handled identically. */
4883 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4884 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4885 /* PC should be 4-byte aligned. */
4886 rn_val
= rn_val
& 0xfffffffc;
4887 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4889 dsc
->u
.ldst
.writeback
= writeback
;
4890 dsc
->u
.ldst
.rn
= rn
;
4892 dsc
->cleanup
= &cleanup_copro_load_store
;
4896 arm_copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
4897 struct regcache
*regs
,
4898 struct displaced_step_closure
*dsc
)
4900 unsigned int rn
= bits (insn
, 16, 19);
4902 if (!insn_references_pc (insn
, 0x000f0000ul
))
4903 return arm_copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
4905 if (debug_displaced
)
4906 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4907 "load/store insn %.8lx\n", (unsigned long) insn
);
4909 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4911 install_copro_load_store (gdbarch
, regs
, dsc
, bit (insn
, 25), rn
);
4917 thumb2_copy_copro_load_store (struct gdbarch
*gdbarch
, uint16_t insn1
,
4918 uint16_t insn2
, struct regcache
*regs
,
4919 struct displaced_step_closure
*dsc
)
4921 unsigned int rn
= bits (insn1
, 0, 3);
4923 if (rn
!= ARM_PC_REGNUM
)
4924 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
4925 "copro load/store", dsc
);
4927 if (debug_displaced
)
4928 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4929 "load/store insn %.4x%.4x\n", insn1
, insn2
);
4931 dsc
->modinsn
[0] = insn1
& 0xfff0;
4932 dsc
->modinsn
[1] = insn2
;
4935 /* This function is called for copying instruction LDC/LDC2/VLDR, which
4936 doesn't support writeback, so pass 0. */
4937 install_copro_load_store (gdbarch
, regs
, dsc
, 0, rn
);
4942 /* Clean up branch instructions (actually perform the branch, by setting
4946 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4947 struct displaced_step_closure
*dsc
)
4949 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
4950 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
4951 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
4952 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
4957 if (dsc
->u
.branch
.link
)
4959 /* The value of LR should be the next insn of current one. In order
4960 not to confuse logic hanlding later insn `bx lr', if current insn mode
4961 is Thumb, the bit 0 of LR value should be set to 1. */
4962 ULONGEST next_insn_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
4965 next_insn_addr
|= 0x1;
4967 displaced_write_reg (regs
, dsc
, ARM_LR_REGNUM
, next_insn_addr
,
4971 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, dsc
->u
.branch
.dest
, write_pc
);
4974 /* Copy B/BL/BLX instructions with immediate destinations. */
4977 install_b_bl_blx (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4978 struct displaced_step_closure
*dsc
,
4979 unsigned int cond
, int exchange
, int link
, long offset
)
4981 /* Implement "BL<cond> <label>" as:
4983 Preparation: cond <- instruction condition
4984 Insn: mov r0, r0 (nop)
4985 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
4987 B<cond> similar, but don't set r14 in cleanup. */
4989 dsc
->u
.branch
.cond
= cond
;
4990 dsc
->u
.branch
.link
= link
;
4991 dsc
->u
.branch
.exchange
= exchange
;
4993 dsc
->u
.branch
.dest
= dsc
->insn_addr
;
4994 if (link
&& exchange
)
4995 /* For BLX, offset is computed from the Align (PC, 4). */
4996 dsc
->u
.branch
.dest
= dsc
->u
.branch
.dest
& 0xfffffffc;
4999 dsc
->u
.branch
.dest
+= 4 + offset
;
5001 dsc
->u
.branch
.dest
+= 8 + offset
;
5003 dsc
->cleanup
= &cleanup_branch
;
5006 arm_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
5007 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5009 unsigned int cond
= bits (insn
, 28, 31);
5010 int exchange
= (cond
== 0xf);
5011 int link
= exchange
|| bit (insn
, 24);
5014 if (debug_displaced
)
5015 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
5016 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
5017 (unsigned long) insn
);
5019 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
5020 then arrange the switch into Thumb mode. */
5021 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
5023 offset
= bits (insn
, 0, 23) << 2;
5025 if (bit (offset
, 25))
5026 offset
= offset
| ~0x3ffffff;
5028 dsc
->modinsn
[0] = ARM_NOP
;
5030 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5035 thumb2_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint16_t insn1
,
5036 uint16_t insn2
, struct regcache
*regs
,
5037 struct displaced_step_closure
*dsc
)
5039 int link
= bit (insn2
, 14);
5040 int exchange
= link
&& !bit (insn2
, 12);
5043 int j1
= bit (insn2
, 13);
5044 int j2
= bit (insn2
, 11);
5045 int s
= sbits (insn1
, 10, 10);
5046 int i1
= !(j1
^ bit (insn1
, 10));
5047 int i2
= !(j2
^ bit (insn1
, 10));
5049 if (!link
&& !exchange
) /* B */
5051 offset
= (bits (insn2
, 0, 10) << 1);
5052 if (bit (insn2
, 12)) /* Encoding T4 */
5054 offset
|= (bits (insn1
, 0, 9) << 12)
5060 else /* Encoding T3 */
5062 offset
|= (bits (insn1
, 0, 5) << 12)
5066 cond
= bits (insn1
, 6, 9);
5071 offset
= (bits (insn1
, 0, 9) << 12);
5072 offset
|= ((i2
<< 22) | (i1
<< 23) | (s
<< 24));
5073 offset
|= exchange
?
5074 (bits (insn2
, 1, 10) << 2) : (bits (insn2
, 0, 10) << 1);
5077 if (debug_displaced
)
5078 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s insn "
5079 "%.4x %.4x with offset %.8lx\n",
5080 link
? (exchange
) ? "blx" : "bl" : "b",
5081 insn1
, insn2
, offset
);
5083 dsc
->modinsn
[0] = THUMB_NOP
;
5085 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5089 /* Copy B Thumb instructions. */
5091 thumb_copy_b (struct gdbarch
*gdbarch
, uint16_t insn
,
5092 struct displaced_step_closure
*dsc
)
5094 unsigned int cond
= 0;
5096 unsigned short bit_12_15
= bits (insn
, 12, 15);
5097 CORE_ADDR from
= dsc
->insn_addr
;
5099 if (bit_12_15
== 0xd)
5101 /* offset = SignExtend (imm8:0, 32) */
5102 offset
= sbits ((insn
<< 1), 0, 8);
5103 cond
= bits (insn
, 8, 11);
5105 else if (bit_12_15
== 0xe) /* Encoding T2 */
5107 offset
= sbits ((insn
<< 1), 0, 11);
5111 if (debug_displaced
)
5112 fprintf_unfiltered (gdb_stdlog
,
5113 "displaced: copying b immediate insn %.4x "
5114 "with offset %d\n", insn
, offset
);
5116 dsc
->u
.branch
.cond
= cond
;
5117 dsc
->u
.branch
.link
= 0;
5118 dsc
->u
.branch
.exchange
= 0;
5119 dsc
->u
.branch
.dest
= from
+ 4 + offset
;
5121 dsc
->modinsn
[0] = THUMB_NOP
;
5123 dsc
->cleanup
= &cleanup_branch
;
5128 /* Copy BX/BLX with register-specified destinations. */
5131 install_bx_blx_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5132 struct displaced_step_closure
*dsc
, int link
,
5133 unsigned int cond
, unsigned int rm
)
5135 /* Implement {BX,BLX}<cond> <reg>" as:
5137 Preparation: cond <- instruction condition
5138 Insn: mov r0, r0 (nop)
5139 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
5141 Don't set r14 in cleanup for BX. */
5143 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, dsc
, rm
);
5145 dsc
->u
.branch
.cond
= cond
;
5146 dsc
->u
.branch
.link
= link
;
5148 dsc
->u
.branch
.exchange
= 1;
5150 dsc
->cleanup
= &cleanup_branch
;
5154 arm_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5155 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5157 unsigned int cond
= bits (insn
, 28, 31);
5160 int link
= bit (insn
, 5);
5161 unsigned int rm
= bits (insn
, 0, 3);
5163 if (debug_displaced
)
5164 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx",
5165 (unsigned long) insn
);
5167 dsc
->modinsn
[0] = ARM_NOP
;
5169 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, cond
, rm
);
5174 thumb_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5175 struct regcache
*regs
,
5176 struct displaced_step_closure
*dsc
)
5178 int link
= bit (insn
, 7);
5179 unsigned int rm
= bits (insn
, 3, 6);
5181 if (debug_displaced
)
5182 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x",
5183 (unsigned short) insn
);
5185 dsc
->modinsn
[0] = THUMB_NOP
;
5187 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, INST_AL
, rm
);
5193 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
5196 cleanup_alu_imm (struct gdbarch
*gdbarch
,
5197 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5199 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5200 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5201 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5202 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5206 arm_copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5207 struct displaced_step_closure
*dsc
)
5209 unsigned int rn
= bits (insn
, 16, 19);
5210 unsigned int rd
= bits (insn
, 12, 15);
5211 unsigned int op
= bits (insn
, 21, 24);
5212 int is_mov
= (op
== 0xd);
5213 ULONGEST rd_val
, rn_val
;
5215 if (!insn_references_pc (insn
, 0x000ff000ul
))
5216 return arm_copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
5218 if (debug_displaced
)
5219 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
5220 "%.8lx\n", is_mov
? "move" : "ALU",
5221 (unsigned long) insn
);
5223 /* Instruction is of form:
5225 <op><cond> rd, [rn,] #imm
5229 Preparation: tmp1, tmp2 <- r0, r1;
5231 Insn: <op><cond> r0, r1, #imm
5232 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5235 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5236 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5237 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5238 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5239 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5240 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5244 dsc
->modinsn
[0] = insn
& 0xfff00fff;
5246 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
5248 dsc
->cleanup
= &cleanup_alu_imm
;
5254 thumb2_copy_alu_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5255 uint16_t insn2
, struct regcache
*regs
,
5256 struct displaced_step_closure
*dsc
)
5258 unsigned int op
= bits (insn1
, 5, 8);
5259 unsigned int rn
, rm
, rd
;
5260 ULONGEST rd_val
, rn_val
;
5262 rn
= bits (insn1
, 0, 3); /* Rn */
5263 rm
= bits (insn2
, 0, 3); /* Rm */
5264 rd
= bits (insn2
, 8, 11); /* Rd */
5266 /* This routine is only called for instruction MOV. */
5267 gdb_assert (op
== 0x2 && rn
== 0xf);
5269 if (rm
!= ARM_PC_REGNUM
&& rd
!= ARM_PC_REGNUM
)
5270 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ALU imm", dsc
);
5272 if (debug_displaced
)
5273 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x%.4x\n",
5274 "ALU", insn1
, insn2
);
5276 /* Instruction is of form:
5278 <op><cond> rd, [rn,] #imm
5282 Preparation: tmp1, tmp2 <- r0, r1;
5284 Insn: <op><cond> r0, r1, #imm
5285 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5288 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5289 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5290 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5291 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5292 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5293 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5296 dsc
->modinsn
[0] = insn1
;
5297 dsc
->modinsn
[1] = ((insn2
& 0xf0f0) | 0x1);
5300 dsc
->cleanup
= &cleanup_alu_imm
;
5305 /* Copy/cleanup arithmetic/logic insns with register RHS. */
5308 cleanup_alu_reg (struct gdbarch
*gdbarch
,
5309 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5314 rd_val
= displaced_read_reg (regs
, dsc
, 0);
5316 for (i
= 0; i
< 3; i
++)
5317 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5319 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5323 install_alu_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5324 struct displaced_step_closure
*dsc
,
5325 unsigned int rd
, unsigned int rn
, unsigned int rm
)
5327 ULONGEST rd_val
, rn_val
, rm_val
;
5329 /* Instruction is of form:
5331 <op><cond> rd, [rn,] rm [, <shift>]
5335 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
5336 r0, r1, r2 <- rd, rn, rm
5337 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
5338 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
5341 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5342 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5343 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5344 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5345 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5346 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5347 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5348 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5349 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5352 dsc
->cleanup
= &cleanup_alu_reg
;
5356 arm_copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5357 struct displaced_step_closure
*dsc
)
5359 unsigned int op
= bits (insn
, 21, 24);
5360 int is_mov
= (op
== 0xd);
5362 if (!insn_references_pc (insn
, 0x000ff00ful
))
5363 return arm_copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
5365 if (debug_displaced
)
5366 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
5367 is_mov
? "move" : "ALU", (unsigned long) insn
);
5370 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
5372 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
5374 install_alu_reg (gdbarch
, regs
, dsc
, bits (insn
, 12, 15), bits (insn
, 16, 19),
5380 thumb_copy_alu_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5381 struct regcache
*regs
,
5382 struct displaced_step_closure
*dsc
)
5386 rm
= bits (insn
, 3, 6);
5387 rd
= (bit (insn
, 7) << 3) | bits (insn
, 0, 2);
5389 if (rd
!= ARM_PC_REGNUM
&& rm
!= ARM_PC_REGNUM
)
5390 return thumb_copy_unmodified_16bit (gdbarch
, insn
, "ALU reg", dsc
);
5392 if (debug_displaced
)
5393 fprintf_unfiltered (gdb_stdlog
, "displaced: copying ALU reg insn %.4x\n",
5394 (unsigned short) insn
);
5396 dsc
->modinsn
[0] = ((insn
& 0xff00) | 0x10);
5398 install_alu_reg (gdbarch
, regs
, dsc
, rd
, rd
, rm
);
5403 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
5406 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
5407 struct regcache
*regs
,
5408 struct displaced_step_closure
*dsc
)
5410 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5413 for (i
= 0; i
< 4; i
++)
5414 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5416 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5420 install_alu_shifted_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5421 struct displaced_step_closure
*dsc
,
5422 unsigned int rd
, unsigned int rn
, unsigned int rm
,
5426 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
5428 /* Instruction is of form:
5430 <op><cond> rd, [rn,] rm, <shift> rs
5434 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
5435 r0, r1, r2, r3 <- rd, rn, rm, rs
5436 Insn: <op><cond> r0, r1, r2, <shift> r3
5438 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
5442 for (i
= 0; i
< 4; i
++)
5443 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
5445 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5446 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5447 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5448 rs_val
= displaced_read_reg (regs
, dsc
, rs
);
5449 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5450 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5451 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5452 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
5454 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
5458 arm_copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5459 struct regcache
*regs
,
5460 struct displaced_step_closure
*dsc
)
5462 unsigned int op
= bits (insn
, 21, 24);
5463 int is_mov
= (op
== 0xd);
5464 unsigned int rd
, rn
, rm
, rs
;
5466 if (!insn_references_pc (insn
, 0x000fff0ful
))
5467 return arm_copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
5469 if (debug_displaced
)
5470 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
5471 "%.8lx\n", is_mov
? "move" : "ALU",
5472 (unsigned long) insn
);
5474 rn
= bits (insn
, 16, 19);
5475 rm
= bits (insn
, 0, 3);
5476 rs
= bits (insn
, 8, 11);
5477 rd
= bits (insn
, 12, 15);
5480 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
5482 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
5484 install_alu_shifted_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
, rs
);
5489 /* Clean up load instructions. */
5492 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5493 struct displaced_step_closure
*dsc
)
5495 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
5497 rt_val
= displaced_read_reg (regs
, dsc
, 0);
5498 if (dsc
->u
.ldst
.xfersize
== 8)
5499 rt_val2
= displaced_read_reg (regs
, dsc
, 1);
5500 rn_val
= displaced_read_reg (regs
, dsc
, 2);
5502 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5503 if (dsc
->u
.ldst
.xfersize
> 4)
5504 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5505 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5506 if (!dsc
->u
.ldst
.immed
)
5507 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5509 /* Handle register writeback. */
5510 if (dsc
->u
.ldst
.writeback
)
5511 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5512 /* Put result in right place. */
5513 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
5514 if (dsc
->u
.ldst
.xfersize
== 8)
5515 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
5518 /* Clean up store instructions. */
5521 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5522 struct displaced_step_closure
*dsc
)
5524 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 2);
5526 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5527 if (dsc
->u
.ldst
.xfersize
> 4)
5528 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5529 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5530 if (!dsc
->u
.ldst
.immed
)
5531 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5532 if (!dsc
->u
.ldst
.restore_r4
)
5533 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
5536 if (dsc
->u
.ldst
.writeback
)
5537 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5540 /* Copy "extra" load/store instructions. These are halfword/doubleword
5541 transfers, which have a different encoding to byte/word transfers. */
5544 arm_copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unprivileged
,
5545 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5547 unsigned int op1
= bits (insn
, 20, 24);
5548 unsigned int op2
= bits (insn
, 5, 6);
5549 unsigned int rt
= bits (insn
, 12, 15);
5550 unsigned int rn
= bits (insn
, 16, 19);
5551 unsigned int rm
= bits (insn
, 0, 3);
5552 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
5553 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
5554 int immed
= (op1
& 0x4) != 0;
5556 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
5558 if (!insn_references_pc (insn
, 0x000ff00ful
))
5559 return arm_copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
5561 if (debug_displaced
)
5562 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
5563 "insn %.8lx\n", unprivileged
? "unprivileged " : "",
5564 (unsigned long) insn
);
5566 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
5569 internal_error (__FILE__
, __LINE__
,
5570 _("copy_extra_ld_st: instruction decode error"));
5572 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5573 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5574 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5576 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5578 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5579 if (bytesize
[opcode
] == 8)
5580 rt_val2
= displaced_read_reg (regs
, dsc
, rt
+ 1);
5581 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5583 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5585 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5586 if (bytesize
[opcode
] == 8)
5587 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
5588 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5590 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5593 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
5594 dsc
->u
.ldst
.rn
= rn
;
5595 dsc
->u
.ldst
.immed
= immed
;
5596 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
5597 dsc
->u
.ldst
.restore_r4
= 0;
5600 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
5602 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
5603 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5605 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
5607 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
5608 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5610 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
5615 /* Copy byte/half word/word loads and stores. */
5618 install_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5619 struct displaced_step_closure
*dsc
, int load
,
5620 int immed
, int writeback
, int size
, int usermode
,
5621 int rt
, int rm
, int rn
)
5623 ULONGEST rt_val
, rn_val
, rm_val
= 0;
5625 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5626 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5628 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5630 dsc
->tmp
[4] = displaced_read_reg (regs
, dsc
, 4);
5632 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5633 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5635 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5637 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5638 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5640 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5642 dsc
->u
.ldst
.xfersize
= size
;
5643 dsc
->u
.ldst
.rn
= rn
;
5644 dsc
->u
.ldst
.immed
= immed
;
5645 dsc
->u
.ldst
.writeback
= writeback
;
5647 /* To write PC we can do:
5649 Before this sequence of instructions:
5650 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
5651 r2 is the Rn value got from dispalced_read_reg.
5653 Insn1: push {pc} Write address of STR instruction + offset on stack
5654 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
5655 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
5656 = addr(Insn1) + offset - addr(Insn3) - 8
5658 Insn4: add r4, r4, #8 r4 = offset - 8
5659 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
5661 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
5663 Otherwise we don't know what value to write for PC, since the offset is
5664 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
5665 of this can be found in Section "Saving from r15" in
5666 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
5668 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5673 thumb2_copy_load_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
5674 uint16_t insn2
, struct regcache
*regs
,
5675 struct displaced_step_closure
*dsc
, int size
)
5677 unsigned int u_bit
= bit (insn1
, 7);
5678 unsigned int rt
= bits (insn2
, 12, 15);
5679 int imm12
= bits (insn2
, 0, 11);
5682 if (debug_displaced
)
5683 fprintf_unfiltered (gdb_stdlog
,
5684 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
5685 (unsigned int) dsc
->insn_addr
, rt
, u_bit
? '+' : '-',
5691 /* Rewrite instruction LDR Rt imm12 into:
5693 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
5697 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
5700 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5701 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5702 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5704 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
5706 pc_val
= pc_val
& 0xfffffffc;
5708 displaced_write_reg (regs
, dsc
, 2, pc_val
, CANNOT_WRITE_PC
);
5709 displaced_write_reg (regs
, dsc
, 3, imm12
, CANNOT_WRITE_PC
);
5713 dsc
->u
.ldst
.xfersize
= size
;
5714 dsc
->u
.ldst
.immed
= 0;
5715 dsc
->u
.ldst
.writeback
= 0;
5716 dsc
->u
.ldst
.restore_r4
= 0;
5718 /* LDR R0, R2, R3 */
5719 dsc
->modinsn
[0] = 0xf852;
5720 dsc
->modinsn
[1] = 0x3;
5723 dsc
->cleanup
= &cleanup_load
;
5729 thumb2_copy_load_reg_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5730 uint16_t insn2
, struct regcache
*regs
,
5731 struct displaced_step_closure
*dsc
,
5732 int writeback
, int immed
)
5734 unsigned int rt
= bits (insn2
, 12, 15);
5735 unsigned int rn
= bits (insn1
, 0, 3);
5736 unsigned int rm
= bits (insn2
, 0, 3); /* Only valid if !immed. */
5737 /* In LDR (register), there is also a register Rm, which is not allowed to
5738 be PC, so we don't have to check it. */
5740 if (rt
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
5741 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "load",
5744 if (debug_displaced
)
5745 fprintf_unfiltered (gdb_stdlog
,
5746 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
5747 rt
, rn
, insn1
, insn2
);
5749 install_load_store (gdbarch
, regs
, dsc
, 1, immed
, writeback
, 4,
5752 dsc
->u
.ldst
.restore_r4
= 0;
5755 /* ldr[b]<cond> rt, [rn, #imm], etc.
5757 ldr[b]<cond> r0, [r2, #imm]. */
5759 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5760 dsc
->modinsn
[1] = insn2
& 0x0fff;
5763 /* ldr[b]<cond> rt, [rn, rm], etc.
5765 ldr[b]<cond> r0, [r2, r3]. */
5767 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5768 dsc
->modinsn
[1] = (insn2
& 0x0ff0) | 0x3;
5778 arm_copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
5779 struct regcache
*regs
,
5780 struct displaced_step_closure
*dsc
,
5781 int load
, int size
, int usermode
)
5783 int immed
= !bit (insn
, 25);
5784 int writeback
= (bit (insn
, 24) == 0 || bit (insn
, 21) != 0);
5785 unsigned int rt
= bits (insn
, 12, 15);
5786 unsigned int rn
= bits (insn
, 16, 19);
5787 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
5789 if (!insn_references_pc (insn
, 0x000ff00ful
))
5790 return arm_copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
5792 if (debug_displaced
)
5793 fprintf_unfiltered (gdb_stdlog
,
5794 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
5795 load
? (size
== 1 ? "ldrb" : "ldr")
5796 : (size
== 1 ? "strb" : "str"), usermode
? "t" : "",
5798 (unsigned long) insn
);
5800 install_load_store (gdbarch
, regs
, dsc
, load
, immed
, writeback
, size
,
5801 usermode
, rt
, rm
, rn
);
5803 if (load
|| rt
!= ARM_PC_REGNUM
)
5805 dsc
->u
.ldst
.restore_r4
= 0;
5808 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
5810 {ldr,str}[b]<cond> r0, [r2, #imm]. */
5811 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5813 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
5815 {ldr,str}[b]<cond> r0, [r2, r3]. */
5816 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5820 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
5821 dsc
->u
.ldst
.restore_r4
= 1;
5822 dsc
->modinsn
[0] = 0xe92d8000; /* push {pc} */
5823 dsc
->modinsn
[1] = 0xe8bd0010; /* pop {r4} */
5824 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
5825 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
5826 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
5830 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
5832 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
5837 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5842 /* Cleanup LDM instructions with fully-populated register list. This is an
5843 unfortunate corner case: it's impossible to implement correctly by modifying
5844 the instruction. The issue is as follows: we have an instruction,
5848 which we must rewrite to avoid loading PC. A possible solution would be to
5849 do the load in two halves, something like (with suitable cleanup
5853 ldm[id][ab] r8!, {r0-r7}
5855 ldm[id][ab] r8, {r7-r14}
5858 but at present there's no suitable place for <temp>, since the scratch space
5859 is overwritten before the cleanup routine is called. For now, we simply
5860 emulate the instruction. */
5863 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5864 struct displaced_step_closure
*dsc
)
5866 int inc
= dsc
->u
.block
.increment
;
5867 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
5868 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
5869 uint32_t regmask
= dsc
->u
.block
.regmask
;
5870 int regno
= inc
? 0 : 15;
5871 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
5872 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
5873 && (regmask
& 0x8000) != 0;
5874 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5875 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
5876 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5881 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
5882 sensible we can do here. Complain loudly. */
5883 if (exception_return
)
5884 error (_("Cannot single-step exception return"));
5886 /* We don't handle any stores here for now. */
5887 gdb_assert (dsc
->u
.block
.load
!= 0);
5889 if (debug_displaced
)
5890 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
5891 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
5892 dsc
->u
.block
.increment
? "inc" : "dec",
5893 dsc
->u
.block
.before
? "before" : "after");
5900 while (regno
<= ARM_PC_REGNUM
&& (regmask
& (1 << regno
)) == 0)
5903 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
5906 xfer_addr
+= bump_before
;
5908 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
5909 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
5911 xfer_addr
+= bump_after
;
5913 regmask
&= ~(1 << regno
);
5916 if (dsc
->u
.block
.writeback
)
5917 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
5921 /* Clean up an STM which included the PC in the register list. */
5924 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5925 struct displaced_step_closure
*dsc
)
5927 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5928 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
5929 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
5930 CORE_ADDR stm_insn_addr
;
5933 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5935 /* If condition code fails, there's nothing else to do. */
5936 if (!store_executed
)
5939 if (dsc
->u
.block
.increment
)
5941 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
5943 if (dsc
->u
.block
.before
)
5948 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
5950 if (dsc
->u
.block
.before
)
5954 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
5955 stm_insn_addr
= dsc
->scratch_base
;
5956 offset
= pc_val
- stm_insn_addr
;
5958 if (debug_displaced
)
5959 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
5960 "STM instruction\n", offset
);
5962 /* Rewrite the stored PC to the proper value for the non-displaced original
5964 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
5965 dsc
->insn_addr
+ offset
);
5968 /* Clean up an LDM which includes the PC in the register list. We clumped all
5969 the registers in the transferred list into a contiguous range r0...rX (to
5970 avoid loading PC directly and losing control of the debugged program), so we
5971 must undo that here. */
5974 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
5975 struct regcache
*regs
,
5976 struct displaced_step_closure
*dsc
)
5978 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5979 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
);
5980 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= ARM_PC_REGNUM
;
5981 unsigned int regs_loaded
= bitcount (mask
);
5982 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
5984 /* The method employed here will fail if the register list is fully populated
5985 (we need to avoid loading PC directly). */
5986 gdb_assert (num_to_shuffle
< 16);
5991 clobbered
= (1 << num_to_shuffle
) - 1;
5993 while (num_to_shuffle
> 0)
5995 if ((mask
& (1 << write_reg
)) != 0)
5997 unsigned int read_reg
= num_to_shuffle
- 1;
5999 if (read_reg
!= write_reg
)
6001 ULONGEST rval
= displaced_read_reg (regs
, dsc
, read_reg
);
6002 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
6003 if (debug_displaced
)
6004 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
6005 "loaded register r%d to r%d\n"), read_reg
,
6008 else if (debug_displaced
)
6009 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
6010 "r%d already in the right place\n"),
6013 clobbered
&= ~(1 << write_reg
);
6021 /* Restore any registers we scribbled over. */
6022 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
6024 if ((clobbered
& (1 << write_reg
)) != 0)
6026 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
6028 if (debug_displaced
)
6029 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
6030 "clobbered register r%d\n"), write_reg
);
6031 clobbered
&= ~(1 << write_reg
);
6035 /* Perform register writeback manually. */
6036 if (dsc
->u
.block
.writeback
)
6038 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
6040 if (dsc
->u
.block
.increment
)
6041 new_rn_val
+= regs_loaded
* 4;
6043 new_rn_val
-= regs_loaded
* 4;
6045 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
6050 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
6051 in user-level code (in particular exception return, ldm rn, {...pc}^). */
6054 arm_copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
,
6055 struct regcache
*regs
,
6056 struct displaced_step_closure
*dsc
)
6058 int load
= bit (insn
, 20);
6059 int user
= bit (insn
, 22);
6060 int increment
= bit (insn
, 23);
6061 int before
= bit (insn
, 24);
6062 int writeback
= bit (insn
, 21);
6063 int rn
= bits (insn
, 16, 19);
6065 /* Block transfers which don't mention PC can be run directly
6067 if (rn
!= ARM_PC_REGNUM
&& (insn
& 0x8000) == 0)
6068 return arm_copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
6070 if (rn
== ARM_PC_REGNUM
)
6072 warning (_("displaced: Unpredictable LDM or STM with "
6073 "base register r15"));
6074 return arm_copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
6077 if (debug_displaced
)
6078 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6079 "%.8lx\n", (unsigned long) insn
);
6081 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6082 dsc
->u
.block
.rn
= rn
;
6084 dsc
->u
.block
.load
= load
;
6085 dsc
->u
.block
.user
= user
;
6086 dsc
->u
.block
.increment
= increment
;
6087 dsc
->u
.block
.before
= before
;
6088 dsc
->u
.block
.writeback
= writeback
;
6089 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
6091 dsc
->u
.block
.regmask
= insn
& 0xffff;
6095 if ((insn
& 0xffff) == 0xffff)
6097 /* LDM with a fully-populated register list. This case is
6098 particularly tricky. Implement for now by fully emulating the
6099 instruction (which might not behave perfectly in all cases, but
6100 these instructions should be rare enough for that not to matter
6102 dsc
->modinsn
[0] = ARM_NOP
;
6104 dsc
->cleanup
= &cleanup_block_load_all
;
6108 /* LDM of a list of registers which includes PC. Implement by
6109 rewriting the list of registers to be transferred into a
6110 contiguous chunk r0...rX before doing the transfer, then shuffling
6111 registers into the correct places in the cleanup routine. */
6112 unsigned int regmask
= insn
& 0xffff;
6113 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
6116 for (i
= 0; i
< num_in_list
; i
++)
6117 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6119 /* Writeback makes things complicated. We need to avoid clobbering
6120 the base register with one of the registers in our modified
6121 register list, but just using a different register can't work in
6124 ldm r14!, {r0-r13,pc}
6126 which would need to be rewritten as:
6130 but that can't work, because there's no free register for N.
6132 Solve this by turning off the writeback bit, and emulating
6133 writeback manually in the cleanup routine. */
6138 new_regmask
= (1 << num_in_list
) - 1;
6140 if (debug_displaced
)
6141 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6142 "{..., pc}: original reg list %.4x, modified "
6143 "list %.4x\n"), rn
, writeback
? "!" : "",
6144 (int) insn
& 0xffff, new_regmask
);
6146 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
6148 dsc
->cleanup
= &cleanup_block_load_pc
;
6153 /* STM of a list of registers which includes PC. Run the instruction
6154 as-is, but out of line: this will store the wrong value for the PC,
6155 so we must manually fix up the memory in the cleanup routine.
6156 Doing things this way has the advantage that we can auto-detect
6157 the offset of the PC write (which is architecture-dependent) in
6158 the cleanup routine. */
6159 dsc
->modinsn
[0] = insn
;
6161 dsc
->cleanup
= &cleanup_block_store_pc
;
6168 thumb2_copy_block_xfer (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6169 struct regcache
*regs
,
6170 struct displaced_step_closure
*dsc
)
6172 int rn
= bits (insn1
, 0, 3);
6173 int load
= bit (insn1
, 4);
6174 int writeback
= bit (insn1
, 5);
6176 /* Block transfers which don't mention PC can be run directly
6178 if (rn
!= ARM_PC_REGNUM
&& (insn2
& 0x8000) == 0)
6179 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ldm/stm", dsc
);
6181 if (rn
== ARM_PC_REGNUM
)
6183 warning (_("displaced: Unpredictable LDM or STM with "
6184 "base register r15"));
6185 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6186 "unpredictable ldm/stm", dsc
);
6189 if (debug_displaced
)
6190 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6191 "%.4x%.4x\n", insn1
, insn2
);
6193 /* Clear bit 13, since it should be always zero. */
6194 dsc
->u
.block
.regmask
= (insn2
& 0xdfff);
6195 dsc
->u
.block
.rn
= rn
;
6197 dsc
->u
.block
.load
= load
;
6198 dsc
->u
.block
.user
= 0;
6199 dsc
->u
.block
.increment
= bit (insn1
, 7);
6200 dsc
->u
.block
.before
= bit (insn1
, 8);
6201 dsc
->u
.block
.writeback
= writeback
;
6202 dsc
->u
.block
.cond
= INST_AL
;
6203 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6207 if (dsc
->u
.block
.regmask
== 0xffff)
6209 /* This branch is impossible to happen. */
6214 unsigned int regmask
= dsc
->u
.block
.regmask
;
6215 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
6218 for (i
= 0; i
< num_in_list
; i
++)
6219 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6224 new_regmask
= (1 << num_in_list
) - 1;
6226 if (debug_displaced
)
6227 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6228 "{..., pc}: original reg list %.4x, modified "
6229 "list %.4x\n"), rn
, writeback
? "!" : "",
6230 (int) dsc
->u
.block
.regmask
, new_regmask
);
6232 dsc
->modinsn
[0] = insn1
;
6233 dsc
->modinsn
[1] = (new_regmask
& 0xffff);
6236 dsc
->cleanup
= &cleanup_block_load_pc
;
6241 dsc
->modinsn
[0] = insn1
;
6242 dsc
->modinsn
[1] = insn2
;
6244 dsc
->cleanup
= &cleanup_block_store_pc
;
6249 /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs.
6250 This is used to avoid a dependency on BFD's bfd_endian enum. */
6253 arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr
, int len
,
6256 return read_memory_unsigned_integer (memaddr
, len
,
6257 (enum bfd_endian
) byte_order
);
6260 /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */
6263 arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs
*self
,
6266 return gdbarch_addr_bits_remove (get_regcache_arch (self
->regcache
), val
);
6269 /* Wrapper over syscall_next_pc for use in get_next_pcs. */
6272 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
)
6277 /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */
6280 arm_get_next_pcs_is_thumb (struct arm_get_next_pcs
*self
)
6282 return arm_is_thumb (self
->regcache
);
6285 /* single_step() is called just before we want to resume the inferior,
6286 if we want to single-step it but there is no hardware or kernel
6287 single-step support. We find the target of the coming instructions
6288 and breakpoint them. */
6291 arm_software_single_step (struct regcache
*regcache
)
6293 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
6294 struct arm_get_next_pcs next_pcs_ctx
;
6297 VEC (CORE_ADDR
) *next_pcs
= NULL
;
6298 struct cleanup
*old_chain
= make_cleanup (VEC_cleanup (CORE_ADDR
), &next_pcs
);
6300 arm_get_next_pcs_ctor (&next_pcs_ctx
,
6301 &arm_get_next_pcs_ops
,
6302 gdbarch_byte_order (gdbarch
),
6303 gdbarch_byte_order_for_code (gdbarch
),
6307 next_pcs
= arm_get_next_pcs (&next_pcs_ctx
);
6309 for (i
= 0; VEC_iterate (CORE_ADDR
, next_pcs
, i
, pc
); i
++)
6311 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
6312 VEC_replace (CORE_ADDR
, next_pcs
, i
, pc
);
6315 discard_cleanups (old_chain
);
6320 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
6321 for Linux, where some SVC instructions must be treated specially. */
6324 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6325 struct displaced_step_closure
*dsc
)
6327 CORE_ADDR resume_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
6329 if (debug_displaced
)
6330 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
6331 "%.8lx\n", (unsigned long) resume_addr
);
6333 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
6337 /* Common copy routine for svc instruciton. */
6340 install_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6341 struct displaced_step_closure
*dsc
)
6343 /* Preparation: none.
6344 Insn: unmodified svc.
6345 Cleanup: pc <- insn_addr + insn_size. */
6347 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
6349 dsc
->wrote_to_pc
= 1;
6351 /* Allow OS-specific code to override SVC handling. */
6352 if (dsc
->u
.svc
.copy_svc_os
)
6353 return dsc
->u
.svc
.copy_svc_os (gdbarch
, regs
, dsc
);
6356 dsc
->cleanup
= &cleanup_svc
;
6362 arm_copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
,
6363 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6366 if (debug_displaced
)
6367 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
6368 (unsigned long) insn
);
6370 dsc
->modinsn
[0] = insn
;
6372 return install_svc (gdbarch
, regs
, dsc
);
6376 thumb_copy_svc (struct gdbarch
*gdbarch
, uint16_t insn
,
6377 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6380 if (debug_displaced
)
6381 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.4x\n",
6384 dsc
->modinsn
[0] = insn
;
6386 return install_svc (gdbarch
, regs
, dsc
);
6389 /* Copy undefined instructions. */
6392 arm_copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
6393 struct displaced_step_closure
*dsc
)
6395 if (debug_displaced
)
6396 fprintf_unfiltered (gdb_stdlog
,
6397 "displaced: copying undefined insn %.8lx\n",
6398 (unsigned long) insn
);
6400 dsc
->modinsn
[0] = insn
;
6406 thumb_32bit_copy_undef (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6407 struct displaced_step_closure
*dsc
)
6410 if (debug_displaced
)
6411 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn "
6412 "%.4x %.4x\n", (unsigned short) insn1
,
6413 (unsigned short) insn2
);
6415 dsc
->modinsn
[0] = insn1
;
6416 dsc
->modinsn
[1] = insn2
;
6422 /* Copy unpredictable instructions. */
6425 arm_copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
6426 struct displaced_step_closure
*dsc
)
6428 if (debug_displaced
)
6429 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
6430 "%.8lx\n", (unsigned long) insn
);
6432 dsc
->modinsn
[0] = insn
;
6437 /* The decode_* functions are instruction decoding helpers. They mostly follow
6438 the presentation in the ARM ARM. */
6441 arm_decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
6442 struct regcache
*regs
,
6443 struct displaced_step_closure
*dsc
)
6445 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
6446 unsigned int rn
= bits (insn
, 16, 19);
6448 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
6449 return arm_copy_unmodified (gdbarch
, insn
, "cps", dsc
);
6450 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
6451 return arm_copy_unmodified (gdbarch
, insn
, "setend", dsc
);
6452 else if ((op1
& 0x60) == 0x20)
6453 return arm_copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
6454 else if ((op1
& 0x71) == 0x40)
6455 return arm_copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store",
6457 else if ((op1
& 0x77) == 0x41)
6458 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6459 else if ((op1
& 0x77) == 0x45)
6460 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
6461 else if ((op1
& 0x77) == 0x51)
6464 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6466 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6468 else if ((op1
& 0x77) == 0x55)
6469 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6470 else if (op1
== 0x57)
6473 case 0x1: return arm_copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
6474 case 0x4: return arm_copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
6475 case 0x5: return arm_copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
6476 case 0x6: return arm_copy_unmodified (gdbarch
, insn
, "isb", dsc
);
6477 default: return arm_copy_unpred (gdbarch
, insn
, dsc
);
6479 else if ((op1
& 0x63) == 0x43)
6480 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6481 else if ((op2
& 0x1) == 0x0)
6482 switch (op1
& ~0x80)
6485 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6487 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
6488 case 0x71: case 0x75:
6490 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
6491 case 0x63: case 0x67: case 0x73: case 0x77:
6492 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6494 return arm_copy_undef (gdbarch
, insn
, dsc
);
6497 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
6501 arm_decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
6502 struct regcache
*regs
,
6503 struct displaced_step_closure
*dsc
)
6505 if (bit (insn
, 27) == 0)
6506 return arm_decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
6507 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
6508 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
6511 return arm_copy_unmodified (gdbarch
, insn
, "srs", dsc
);
6514 return arm_copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
6516 case 0x4: case 0x5: case 0x6: case 0x7:
6517 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6520 switch ((insn
& 0xe00000) >> 21)
6522 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
6524 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6527 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6530 return arm_copy_undef (gdbarch
, insn
, dsc
);
6535 int rn_f
= (bits (insn
, 16, 19) == 0xf);
6536 switch ((insn
& 0xe00000) >> 21)
6539 /* ldc/ldc2 imm (undefined for rn == pc). */
6540 return rn_f
? arm_copy_undef (gdbarch
, insn
, dsc
)
6541 : arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6544 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6546 case 0x4: case 0x5: case 0x6: case 0x7:
6547 /* ldc/ldc2 lit (undefined for rn != pc). */
6548 return rn_f
? arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
6549 : arm_copy_undef (gdbarch
, insn
, dsc
);
6552 return arm_copy_undef (gdbarch
, insn
, dsc
);
6557 return arm_copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
6560 if (bits (insn
, 16, 19) == 0xf)
6562 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6564 return arm_copy_undef (gdbarch
, insn
, dsc
);
6568 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6570 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6574 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6576 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6579 return arm_copy_undef (gdbarch
, insn
, dsc
);
6583 /* Decode miscellaneous instructions in dp/misc encoding space. */
6586 arm_decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
6587 struct regcache
*regs
,
6588 struct displaced_step_closure
*dsc
)
6590 unsigned int op2
= bits (insn
, 4, 6);
6591 unsigned int op
= bits (insn
, 21, 22);
6596 return arm_copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
6599 if (op
== 0x1) /* bx. */
6600 return arm_copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
6602 return arm_copy_unmodified (gdbarch
, insn
, "clz", dsc
);
6604 return arm_copy_undef (gdbarch
, insn
, dsc
);
6608 /* Not really supported. */
6609 return arm_copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
6611 return arm_copy_undef (gdbarch
, insn
, dsc
);
6615 return arm_copy_bx_blx_reg (gdbarch
, insn
,
6616 regs
, dsc
); /* blx register. */
6618 return arm_copy_undef (gdbarch
, insn
, dsc
);
6621 return arm_copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
6625 return arm_copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
6627 /* Not really supported. */
6628 return arm_copy_unmodified (gdbarch
, insn
, "smc", dsc
);
6631 return arm_copy_undef (gdbarch
, insn
, dsc
);
6636 arm_decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
,
6637 struct regcache
*regs
,
6638 struct displaced_step_closure
*dsc
)
6641 switch (bits (insn
, 20, 24))
6644 return arm_copy_unmodified (gdbarch
, insn
, "movw", dsc
);
6647 return arm_copy_unmodified (gdbarch
, insn
, "movt", dsc
);
6649 case 0x12: case 0x16:
6650 return arm_copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
6653 return arm_copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
6657 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
6659 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
6660 return arm_copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
6661 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
6662 return arm_copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
6663 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
6664 return arm_decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
6665 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
6666 return arm_copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
6667 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
6668 return arm_copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
6669 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
6670 return arm_copy_unmodified (gdbarch
, insn
, "synch", dsc
);
6671 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
6672 /* 2nd arg means "unprivileged". */
6673 return arm_copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
6677 /* Should be unreachable. */
6682 arm_decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
6683 struct regcache
*regs
,
6684 struct displaced_step_closure
*dsc
)
6686 int a
= bit (insn
, 25), b
= bit (insn
, 4);
6687 uint32_t op1
= bits (insn
, 20, 24);
6689 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
6690 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
6691 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 0);
6692 else if ((!a
&& (op1
& 0x17) == 0x02)
6693 || (a
&& (op1
& 0x17) == 0x02 && !b
))
6694 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 1);
6695 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
6696 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
6697 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 0);
6698 else if ((!a
&& (op1
& 0x17) == 0x03)
6699 || (a
&& (op1
& 0x17) == 0x03 && !b
))
6700 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 1);
6701 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
6702 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
6703 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
6704 else if ((!a
&& (op1
& 0x17) == 0x06)
6705 || (a
&& (op1
& 0x17) == 0x06 && !b
))
6706 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
6707 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
6708 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
6709 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
6710 else if ((!a
&& (op1
& 0x17) == 0x07)
6711 || (a
&& (op1
& 0x17) == 0x07 && !b
))
6712 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
6714 /* Should be unreachable. */
6719 arm_decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
6720 struct displaced_step_closure
*dsc
)
6722 switch (bits (insn
, 20, 24))
6724 case 0x00: case 0x01: case 0x02: case 0x03:
6725 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
6727 case 0x04: case 0x05: case 0x06: case 0x07:
6728 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
6730 case 0x08: case 0x09: case 0x0a: case 0x0b:
6731 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
6732 return arm_copy_unmodified (gdbarch
, insn
,
6733 "decode/pack/unpack/saturate/reverse", dsc
);
6736 if (bits (insn
, 5, 7) == 0) /* op2. */
6738 if (bits (insn
, 12, 15) == 0xf)
6739 return arm_copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
6741 return arm_copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
6744 return arm_copy_undef (gdbarch
, insn
, dsc
);
6746 case 0x1a: case 0x1b:
6747 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6748 return arm_copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
6750 return arm_copy_undef (gdbarch
, insn
, dsc
);
6752 case 0x1c: case 0x1d:
6753 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
6755 if (bits (insn
, 0, 3) == 0xf)
6756 return arm_copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
6758 return arm_copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
6761 return arm_copy_undef (gdbarch
, insn
, dsc
);
6763 case 0x1e: case 0x1f:
6764 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6765 return arm_copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
6767 return arm_copy_undef (gdbarch
, insn
, dsc
);
6770 /* Should be unreachable. */
6775 arm_decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, uint32_t insn
,
6776 struct regcache
*regs
,
6777 struct displaced_step_closure
*dsc
)
6780 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6782 return arm_copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
6786 arm_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
6787 struct regcache
*regs
,
6788 struct displaced_step_closure
*dsc
)
6790 unsigned int opcode
= bits (insn
, 20, 24);
6794 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
6795 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
6797 case 0x08: case 0x0a: case 0x0c: case 0x0e:
6798 case 0x12: case 0x16:
6799 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
6801 case 0x09: case 0x0b: case 0x0d: case 0x0f:
6802 case 0x13: case 0x17:
6803 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
6805 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6806 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6807 /* Note: no writeback for these instructions. Bit 25 will always be
6808 zero though (via caller), so the following works OK. */
6809 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6812 /* Should be unreachable. */
6816 /* Decode shifted register instructions. */
6819 thumb2_decode_dp_shift_reg (struct gdbarch
*gdbarch
, uint16_t insn1
,
6820 uint16_t insn2
, struct regcache
*regs
,
6821 struct displaced_step_closure
*dsc
)
6823 /* PC is only allowed to be used in instruction MOV. */
6825 unsigned int op
= bits (insn1
, 5, 8);
6826 unsigned int rn
= bits (insn1
, 0, 3);
6828 if (op
== 0x2 && rn
== 0xf) /* MOV */
6829 return thumb2_copy_alu_imm (gdbarch
, insn1
, insn2
, regs
, dsc
);
6831 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6832 "dp (shift reg)", dsc
);
6836 /* Decode extension register load/store. Exactly the same as
6837 arm_decode_ext_reg_ld_st. */
6840 thumb2_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint16_t insn1
,
6841 uint16_t insn2
, struct regcache
*regs
,
6842 struct displaced_step_closure
*dsc
)
6844 unsigned int opcode
= bits (insn1
, 4, 8);
6848 case 0x04: case 0x05:
6849 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6850 "vfp/neon vmov", dsc
);
6852 case 0x08: case 0x0c: /* 01x00 */
6853 case 0x0a: case 0x0e: /* 01x10 */
6854 case 0x12: case 0x16: /* 10x10 */
6855 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6856 "vfp/neon vstm/vpush", dsc
);
6858 case 0x09: case 0x0d: /* 01x01 */
6859 case 0x0b: case 0x0f: /* 01x11 */
6860 case 0x13: case 0x17: /* 10x11 */
6861 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6862 "vfp/neon vldm/vpop", dsc
);
6864 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6865 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6867 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6868 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
, regs
, dsc
);
6871 /* Should be unreachable. */
6876 arm_decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
,
6877 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6879 unsigned int op1
= bits (insn
, 20, 25);
6880 int op
= bit (insn
, 4);
6881 unsigned int coproc
= bits (insn
, 8, 11);
6883 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
6884 return arm_decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
6885 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
6886 && (coproc
& 0xe) != 0xa)
6888 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6889 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
6890 && (coproc
& 0xe) != 0xa)
6891 /* ldc/ldc2 imm/lit. */
6892 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6893 else if ((op1
& 0x3e) == 0x00)
6894 return arm_copy_undef (gdbarch
, insn
, dsc
);
6895 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
6896 return arm_copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
6897 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
6898 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6899 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
6900 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6901 else if ((op1
& 0x30) == 0x20 && !op
)
6903 if ((coproc
& 0xe) == 0xa)
6904 return arm_copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
6906 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6908 else if ((op1
& 0x30) == 0x20 && op
)
6909 return arm_copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
6910 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
6911 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6912 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
6913 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6914 else if ((op1
& 0x30) == 0x30)
6915 return arm_copy_svc (gdbarch
, insn
, regs
, dsc
);
6917 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
6921 thumb2_decode_svc_copro (struct gdbarch
*gdbarch
, uint16_t insn1
,
6922 uint16_t insn2
, struct regcache
*regs
,
6923 struct displaced_step_closure
*dsc
)
6925 unsigned int coproc
= bits (insn2
, 8, 11);
6926 unsigned int bit_5_8
= bits (insn1
, 5, 8);
6927 unsigned int bit_9
= bit (insn1
, 9);
6928 unsigned int bit_4
= bit (insn1
, 4);
6933 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6934 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
6936 else if (bit_5_8
== 0) /* UNDEFINED. */
6937 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
6940 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
6941 if ((coproc
& 0xe) == 0xa)
6942 return thumb2_decode_ext_reg_ld_st (gdbarch
, insn1
, insn2
, regs
,
6944 else /* coproc is not 101x. */
6946 if (bit_4
== 0) /* STC/STC2. */
6947 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6949 else /* LDC/LDC2 {literal, immeidate}. */
6950 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
,
6956 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "coproc", dsc
);
6962 install_pc_relative (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6963 struct displaced_step_closure
*dsc
, int rd
)
6969 Preparation: Rd <- PC
6975 int val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
6976 displaced_write_reg (regs
, dsc
, rd
, val
, CANNOT_WRITE_PC
);
6980 thumb_copy_pc_relative_16bit (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6981 struct displaced_step_closure
*dsc
,
6982 int rd
, unsigned int imm
)
6985 /* Encoding T2: ADDS Rd, #imm */
6986 dsc
->modinsn
[0] = (0x3000 | (rd
<< 8) | imm
);
6988 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
6994 thumb_decode_pc_relative_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
6995 struct regcache
*regs
,
6996 struct displaced_step_closure
*dsc
)
6998 unsigned int rd
= bits (insn
, 8, 10);
6999 unsigned int imm8
= bits (insn
, 0, 7);
7001 if (debug_displaced
)
7002 fprintf_unfiltered (gdb_stdlog
,
7003 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
7006 return thumb_copy_pc_relative_16bit (gdbarch
, regs
, dsc
, rd
, imm8
);
7010 thumb_copy_pc_relative_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
7011 uint16_t insn2
, struct regcache
*regs
,
7012 struct displaced_step_closure
*dsc
)
7014 unsigned int rd
= bits (insn2
, 8, 11);
7015 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
7016 extract raw immediate encoding rather than computing immediate. When
7017 generating ADD or SUB instruction, we can simply perform OR operation to
7018 set immediate into ADD. */
7019 unsigned int imm_3_8
= insn2
& 0x70ff;
7020 unsigned int imm_i
= insn1
& 0x0400; /* Clear all bits except bit 10. */
7022 if (debug_displaced
)
7023 fprintf_unfiltered (gdb_stdlog
,
7024 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
7025 rd
, imm_i
, imm_3_8
, insn1
, insn2
);
7027 if (bit (insn1
, 7)) /* Encoding T2 */
7029 /* Encoding T3: SUB Rd, Rd, #imm */
7030 dsc
->modinsn
[0] = (0xf1a0 | rd
| imm_i
);
7031 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7033 else /* Encoding T3 */
7035 /* Encoding T3: ADD Rd, Rd, #imm */
7036 dsc
->modinsn
[0] = (0xf100 | rd
| imm_i
);
7037 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7041 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
7047 thumb_copy_16bit_ldr_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
7048 struct regcache
*regs
,
7049 struct displaced_step_closure
*dsc
)
7051 unsigned int rt
= bits (insn1
, 8, 10);
7053 int imm8
= (bits (insn1
, 0, 7) << 2);
7059 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
7061 Insn: LDR R0, [R2, R3];
7062 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
7064 if (debug_displaced
)
7065 fprintf_unfiltered (gdb_stdlog
,
7066 "displaced: copying thumb ldr r%d [pc #%d]\n"
7069 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
7070 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
7071 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
7072 pc
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
7073 /* The assembler calculates the required value of the offset from the
7074 Align(PC,4) value of this instruction to the label. */
7075 pc
= pc
& 0xfffffffc;
7077 displaced_write_reg (regs
, dsc
, 2, pc
, CANNOT_WRITE_PC
);
7078 displaced_write_reg (regs
, dsc
, 3, imm8
, CANNOT_WRITE_PC
);
7081 dsc
->u
.ldst
.xfersize
= 4;
7083 dsc
->u
.ldst
.immed
= 0;
7084 dsc
->u
.ldst
.writeback
= 0;
7085 dsc
->u
.ldst
.restore_r4
= 0;
7087 dsc
->modinsn
[0] = 0x58d0; /* ldr r0, [r2, r3]*/
7089 dsc
->cleanup
= &cleanup_load
;
7094 /* Copy Thumb cbnz/cbz insruction. */
7097 thumb_copy_cbnz_cbz (struct gdbarch
*gdbarch
, uint16_t insn1
,
7098 struct regcache
*regs
,
7099 struct displaced_step_closure
*dsc
)
7101 int non_zero
= bit (insn1
, 11);
7102 unsigned int imm5
= (bit (insn1
, 9) << 6) | (bits (insn1
, 3, 7) << 1);
7103 CORE_ADDR from
= dsc
->insn_addr
;
7104 int rn
= bits (insn1
, 0, 2);
7105 int rn_val
= displaced_read_reg (regs
, dsc
, rn
);
7107 dsc
->u
.branch
.cond
= (rn_val
&& non_zero
) || (!rn_val
&& !non_zero
);
7108 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
7109 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
7110 condition is false, let it be, cleanup_branch will do nothing. */
7111 if (dsc
->u
.branch
.cond
)
7113 dsc
->u
.branch
.cond
= INST_AL
;
7114 dsc
->u
.branch
.dest
= from
+ 4 + imm5
;
7117 dsc
->u
.branch
.dest
= from
+ 2;
7119 dsc
->u
.branch
.link
= 0;
7120 dsc
->u
.branch
.exchange
= 0;
7122 if (debug_displaced
)
7123 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s [r%d = 0x%x]"
7124 " insn %.4x to %.8lx\n", non_zero
? "cbnz" : "cbz",
7125 rn
, rn_val
, insn1
, dsc
->u
.branch
.dest
);
7127 dsc
->modinsn
[0] = THUMB_NOP
;
7129 dsc
->cleanup
= &cleanup_branch
;
7133 /* Copy Table Branch Byte/Halfword */
7135 thumb2_copy_table_branch (struct gdbarch
*gdbarch
, uint16_t insn1
,
7136 uint16_t insn2
, struct regcache
*regs
,
7137 struct displaced_step_closure
*dsc
)
7139 ULONGEST rn_val
, rm_val
;
7140 int is_tbh
= bit (insn2
, 4);
7141 CORE_ADDR halfwords
= 0;
7142 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7144 rn_val
= displaced_read_reg (regs
, dsc
, bits (insn1
, 0, 3));
7145 rm_val
= displaced_read_reg (regs
, dsc
, bits (insn2
, 0, 3));
7151 target_read_memory (rn_val
+ 2 * rm_val
, buf
, 2);
7152 halfwords
= extract_unsigned_integer (buf
, 2, byte_order
);
7158 target_read_memory (rn_val
+ rm_val
, buf
, 1);
7159 halfwords
= extract_unsigned_integer (buf
, 1, byte_order
);
7162 if (debug_displaced
)
7163 fprintf_unfiltered (gdb_stdlog
, "displaced: %s base 0x%x offset 0x%x"
7164 " offset 0x%x\n", is_tbh
? "tbh" : "tbb",
7165 (unsigned int) rn_val
, (unsigned int) rm_val
,
7166 (unsigned int) halfwords
);
7168 dsc
->u
.branch
.cond
= INST_AL
;
7169 dsc
->u
.branch
.link
= 0;
7170 dsc
->u
.branch
.exchange
= 0;
7171 dsc
->u
.branch
.dest
= dsc
->insn_addr
+ 4 + 2 * halfwords
;
7173 dsc
->cleanup
= &cleanup_branch
;
7179 cleanup_pop_pc_16bit_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7180 struct displaced_step_closure
*dsc
)
7183 int val
= displaced_read_reg (regs
, dsc
, 7);
7184 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, val
, BX_WRITE_PC
);
7187 val
= displaced_read_reg (regs
, dsc
, 8);
7188 displaced_write_reg (regs
, dsc
, 7, val
, CANNOT_WRITE_PC
);
7191 displaced_write_reg (regs
, dsc
, 8, dsc
->tmp
[0], CANNOT_WRITE_PC
);
7196 thumb_copy_pop_pc_16bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
7197 struct regcache
*regs
,
7198 struct displaced_step_closure
*dsc
)
7200 dsc
->u
.block
.regmask
= insn1
& 0x00ff;
7202 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
7205 (1) register list is full, that is, r0-r7 are used.
7206 Prepare: tmp[0] <- r8
7208 POP {r0, r1, ...., r6, r7}; remove PC from reglist
7209 MOV r8, r7; Move value of r7 to r8;
7210 POP {r7}; Store PC value into r7.
7212 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
7214 (2) register list is not full, supposing there are N registers in
7215 register list (except PC, 0 <= N <= 7).
7216 Prepare: for each i, 0 - N, tmp[i] <- ri.
7218 POP {r0, r1, ...., rN};
7220 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
7221 from tmp[] properly.
7223 if (debug_displaced
)
7224 fprintf_unfiltered (gdb_stdlog
,
7225 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
7226 dsc
->u
.block
.regmask
, insn1
);
7228 if (dsc
->u
.block
.regmask
== 0xff)
7230 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 8);
7232 dsc
->modinsn
[0] = (insn1
& 0xfeff); /* POP {r0,r1,...,r6, r7} */
7233 dsc
->modinsn
[1] = 0x46b8; /* MOV r8, r7 */
7234 dsc
->modinsn
[2] = 0xbc80; /* POP {r7} */
7237 dsc
->cleanup
= &cleanup_pop_pc_16bit_all
;
7241 unsigned int num_in_list
= bitcount (dsc
->u
.block
.regmask
);
7243 unsigned int new_regmask
;
7245 for (i
= 0; i
< num_in_list
+ 1; i
++)
7246 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7248 new_regmask
= (1 << (num_in_list
+ 1)) - 1;
7250 if (debug_displaced
)
7251 fprintf_unfiltered (gdb_stdlog
, _("displaced: POP "
7252 "{..., pc}: original reg list %.4x,"
7253 " modified list %.4x\n"),
7254 (int) dsc
->u
.block
.regmask
, new_regmask
);
7256 dsc
->u
.block
.regmask
|= 0x8000;
7257 dsc
->u
.block
.writeback
= 0;
7258 dsc
->u
.block
.cond
= INST_AL
;
7260 dsc
->modinsn
[0] = (insn1
& ~0x1ff) | (new_regmask
& 0xff);
7262 dsc
->cleanup
= &cleanup_block_load_pc
;
7269 thumb_process_displaced_16bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7270 struct regcache
*regs
,
7271 struct displaced_step_closure
*dsc
)
7273 unsigned short op_bit_12_15
= bits (insn1
, 12, 15);
7274 unsigned short op_bit_10_11
= bits (insn1
, 10, 11);
7277 /* 16-bit thumb instructions. */
7278 switch (op_bit_12_15
)
7280 /* Shift (imme), add, subtract, move and compare. */
7281 case 0: case 1: case 2: case 3:
7282 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7283 "shift/add/sub/mov/cmp",
7287 switch (op_bit_10_11
)
7289 case 0: /* Data-processing */
7290 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7294 case 1: /* Special data instructions and branch and exchange. */
7296 unsigned short op
= bits (insn1
, 7, 9);
7297 if (op
== 6 || op
== 7) /* BX or BLX */
7298 err
= thumb_copy_bx_blx_reg (gdbarch
, insn1
, regs
, dsc
);
7299 else if (bits (insn1
, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
7300 err
= thumb_copy_alu_reg (gdbarch
, insn1
, regs
, dsc
);
7302 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "special data",
7306 default: /* LDR (literal) */
7307 err
= thumb_copy_16bit_ldr_literal (gdbarch
, insn1
, regs
, dsc
);
7310 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
7311 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldr/str", dsc
);
7314 if (op_bit_10_11
< 2) /* Generate PC-relative address */
7315 err
= thumb_decode_pc_relative_16bit (gdbarch
, insn1
, regs
, dsc
);
7316 else /* Generate SP-relative address */
7317 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "sp-relative", dsc
);
7319 case 11: /* Misc 16-bit instructions */
7321 switch (bits (insn1
, 8, 11))
7323 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
7324 err
= thumb_copy_cbnz_cbz (gdbarch
, insn1
, regs
, dsc
);
7326 case 12: case 13: /* POP */
7327 if (bit (insn1
, 8)) /* PC is in register list. */
7328 err
= thumb_copy_pop_pc_16bit (gdbarch
, insn1
, regs
, dsc
);
7330 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "pop", dsc
);
7332 case 15: /* If-Then, and hints */
7333 if (bits (insn1
, 0, 3))
7334 /* If-Then makes up to four following instructions conditional.
7335 IT instruction itself is not conditional, so handle it as a
7336 common unmodified instruction. */
7337 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "If-Then",
7340 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "hints", dsc
);
7343 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "misc", dsc
);
7348 if (op_bit_10_11
< 2) /* Store multiple registers */
7349 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "stm", dsc
);
7350 else /* Load multiple registers */
7351 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldm", dsc
);
7353 case 13: /* Conditional branch and supervisor call */
7354 if (bits (insn1
, 9, 11) != 7) /* conditional branch */
7355 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7357 err
= thumb_copy_svc (gdbarch
, insn1
, regs
, dsc
);
7359 case 14: /* Unconditional branch */
7360 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7367 internal_error (__FILE__
, __LINE__
,
7368 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
7372 decode_thumb_32bit_ld_mem_hints (struct gdbarch
*gdbarch
,
7373 uint16_t insn1
, uint16_t insn2
,
7374 struct regcache
*regs
,
7375 struct displaced_step_closure
*dsc
)
7377 int rt
= bits (insn2
, 12, 15);
7378 int rn
= bits (insn1
, 0, 3);
7379 int op1
= bits (insn1
, 7, 8);
7381 switch (bits (insn1
, 5, 6))
7383 case 0: /* Load byte and memory hints */
7384 if (rt
== 0xf) /* PLD/PLI */
7387 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
7388 return thumb2_copy_preload (gdbarch
, insn1
, insn2
, regs
, dsc
);
7390 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7395 if (rn
== 0xf) /* LDRB/LDRSB (literal) */
7396 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7399 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7400 "ldrb{reg, immediate}/ldrbt",
7405 case 1: /* Load halfword and memory hints. */
7406 if (rt
== 0xf) /* PLD{W} and Unalloc memory hint. */
7407 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7408 "pld/unalloc memhint", dsc
);
7412 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7415 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7419 case 2: /* Load word */
7421 int insn2_bit_8_11
= bits (insn2
, 8, 11);
7424 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
, 4);
7425 else if (op1
== 0x1) /* Encoding T3 */
7426 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
, dsc
,
7428 else /* op1 == 0x0 */
7430 if (insn2_bit_8_11
== 0xc || (insn2_bit_8_11
& 0x9) == 0x9)
7431 /* LDR (immediate) */
7432 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7433 dsc
, bit (insn2
, 8), 1);
7434 else if (insn2_bit_8_11
== 0xe) /* LDRT */
7435 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7438 /* LDR (register) */
7439 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7445 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
7452 thumb_process_displaced_32bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7453 uint16_t insn2
, struct regcache
*regs
,
7454 struct displaced_step_closure
*dsc
)
7457 unsigned short op
= bit (insn2
, 15);
7458 unsigned int op1
= bits (insn1
, 11, 12);
7464 switch (bits (insn1
, 9, 10))
7469 /* Load/store {dual, execlusive}, table branch. */
7470 if (bits (insn1
, 7, 8) == 1 && bits (insn1
, 4, 5) == 1
7471 && bits (insn2
, 5, 7) == 0)
7472 err
= thumb2_copy_table_branch (gdbarch
, insn1
, insn2
, regs
,
7475 /* PC is not allowed to use in load/store {dual, exclusive}
7477 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7478 "load/store dual/ex", dsc
);
7480 else /* load/store multiple */
7482 switch (bits (insn1
, 7, 8))
7484 case 0: case 3: /* SRS, RFE */
7485 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7488 case 1: case 2: /* LDM/STM/PUSH/POP */
7489 err
= thumb2_copy_block_xfer (gdbarch
, insn1
, insn2
, regs
, dsc
);
7496 /* Data-processing (shift register). */
7497 err
= thumb2_decode_dp_shift_reg (gdbarch
, insn1
, insn2
, regs
,
7500 default: /* Coprocessor instructions. */
7501 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7506 case 2: /* op1 = 2 */
7507 if (op
) /* Branch and misc control. */
7509 if (bit (insn2
, 14) /* BLX/BL */
7510 || bit (insn2
, 12) /* Unconditional branch */
7511 || (bits (insn1
, 7, 9) != 0x7)) /* Conditional branch */
7512 err
= thumb2_copy_b_bl_blx (gdbarch
, insn1
, insn2
, regs
, dsc
);
7514 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7519 if (bit (insn1
, 9)) /* Data processing (plain binary imm). */
7521 int op
= bits (insn1
, 4, 8);
7522 int rn
= bits (insn1
, 0, 3);
7523 if ((op
== 0 || op
== 0xa) && rn
== 0xf)
7524 err
= thumb_copy_pc_relative_32bit (gdbarch
, insn1
, insn2
,
7527 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7530 else /* Data processing (modified immeidate) */
7531 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7535 case 3: /* op1 = 3 */
7536 switch (bits (insn1
, 9, 10))
7540 err
= decode_thumb_32bit_ld_mem_hints (gdbarch
, insn1
, insn2
,
7542 else /* NEON Load/Store and Store single data item */
7543 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7544 "neon elt/struct load/store",
7547 case 1: /* op1 = 3, bits (9, 10) == 1 */
7548 switch (bits (insn1
, 7, 8))
7550 case 0: case 1: /* Data processing (register) */
7551 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7554 case 2: /* Multiply and absolute difference */
7555 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7556 "mul/mua/diff", dsc
);
7558 case 3: /* Long multiply and divide */
7559 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7564 default: /* Coprocessor instructions */
7565 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7574 internal_error (__FILE__
, __LINE__
,
7575 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
7580 thumb_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7581 struct regcache
*regs
,
7582 struct displaced_step_closure
*dsc
)
7584 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7586 = read_memory_unsigned_integer (from
, 2, byte_order_for_code
);
7588 if (debug_displaced
)
7589 fprintf_unfiltered (gdb_stdlog
, "displaced: process thumb insn %.4x "
7590 "at %.8lx\n", insn1
, (unsigned long) from
);
7593 dsc
->insn_size
= thumb_insn_size (insn1
);
7594 if (thumb_insn_size (insn1
) == 4)
7597 = read_memory_unsigned_integer (from
+ 2, 2, byte_order_for_code
);
7598 thumb_process_displaced_32bit_insn (gdbarch
, insn1
, insn2
, regs
, dsc
);
7601 thumb_process_displaced_16bit_insn (gdbarch
, insn1
, regs
, dsc
);
7605 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7606 CORE_ADDR to
, struct regcache
*regs
,
7607 struct displaced_step_closure
*dsc
)
7610 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7613 /* Most displaced instructions use a 1-instruction scratch space, so set this
7614 here and override below if/when necessary. */
7616 dsc
->insn_addr
= from
;
7617 dsc
->scratch_base
= to
;
7618 dsc
->cleanup
= NULL
;
7619 dsc
->wrote_to_pc
= 0;
7621 if (!displaced_in_arm_mode (regs
))
7622 return thumb_process_displaced_insn (gdbarch
, from
, regs
, dsc
);
7626 insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
7627 if (debug_displaced
)
7628 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
7629 "at %.8lx\n", (unsigned long) insn
,
7630 (unsigned long) from
);
7632 if ((insn
& 0xf0000000) == 0xf0000000)
7633 err
= arm_decode_unconditional (gdbarch
, insn
, regs
, dsc
);
7634 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
7636 case 0x0: case 0x1: case 0x2: case 0x3:
7637 err
= arm_decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
7640 case 0x4: case 0x5: case 0x6:
7641 err
= arm_decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
7645 err
= arm_decode_media (gdbarch
, insn
, dsc
);
7648 case 0x8: case 0x9: case 0xa: case 0xb:
7649 err
= arm_decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
7652 case 0xc: case 0xd: case 0xe: case 0xf:
7653 err
= arm_decode_svc_copro (gdbarch
, insn
, regs
, dsc
);
7658 internal_error (__FILE__
, __LINE__
,
7659 _("arm_process_displaced_insn: Instruction decode error"));
7662 /* Actually set up the scratch space for a displaced instruction. */
7665 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7666 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
7668 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7669 unsigned int i
, len
, offset
;
7670 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7671 int size
= dsc
->is_thumb
? 2 : 4;
7672 const gdb_byte
*bkp_insn
;
7675 /* Poke modified instruction(s). */
7676 for (i
= 0; i
< dsc
->numinsns
; i
++)
7678 if (debug_displaced
)
7680 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn ");
7682 fprintf_unfiltered (gdb_stdlog
, "%.8lx",
7685 fprintf_unfiltered (gdb_stdlog
, "%.4x",
7686 (unsigned short)dsc
->modinsn
[i
]);
7688 fprintf_unfiltered (gdb_stdlog
, " at %.8lx\n",
7689 (unsigned long) to
+ offset
);
7692 write_memory_unsigned_integer (to
+ offset
, size
,
7693 byte_order_for_code
,
7698 /* Choose the correct breakpoint instruction. */
7701 bkp_insn
= tdep
->thumb_breakpoint
;
7702 len
= tdep
->thumb_breakpoint_size
;
7706 bkp_insn
= tdep
->arm_breakpoint
;
7707 len
= tdep
->arm_breakpoint_size
;
7710 /* Put breakpoint afterwards. */
7711 write_memory (to
+ offset
, bkp_insn
, len
);
7713 if (debug_displaced
)
7714 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
7715 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
7718 /* Entry point for cleaning things up after a displaced instruction has been
7722 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
7723 struct displaced_step_closure
*dsc
,
7724 CORE_ADDR from
, CORE_ADDR to
,
7725 struct regcache
*regs
)
7728 dsc
->cleanup (gdbarch
, regs
, dsc
);
7730 if (!dsc
->wrote_to_pc
)
7731 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
7732 dsc
->insn_addr
+ dsc
->insn_size
);
7736 #include "bfd-in2.h"
7737 #include "libcoff.h"
7740 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
7742 struct gdbarch
*gdbarch
= (struct gdbarch
*) info
->application_data
;
7744 if (arm_pc_is_thumb (gdbarch
, memaddr
))
7746 static asymbol
*asym
;
7747 static combined_entry_type ce
;
7748 static struct coff_symbol_struct csym
;
7749 static struct bfd fake_bfd
;
7750 static bfd_target fake_target
;
7752 if (csym
.native
== NULL
)
7754 /* Create a fake symbol vector containing a Thumb symbol.
7755 This is solely so that the code in print_insn_little_arm()
7756 and print_insn_big_arm() in opcodes/arm-dis.c will detect
7757 the presence of a Thumb symbol and switch to decoding
7758 Thumb instructions. */
7760 fake_target
.flavour
= bfd_target_coff_flavour
;
7761 fake_bfd
.xvec
= &fake_target
;
7762 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
7764 csym
.symbol
.the_bfd
= &fake_bfd
;
7765 csym
.symbol
.name
= "fake";
7766 asym
= (asymbol
*) & csym
;
7769 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
7770 info
->symbols
= &asym
;
7773 info
->symbols
= NULL
;
7775 if (info
->endian
== BFD_ENDIAN_BIG
)
7776 return print_insn_big_arm (memaddr
, info
);
7778 return print_insn_little_arm (memaddr
, info
);
7781 /* The following define instruction sequences that will cause ARM
7782 cpu's to take an undefined instruction trap. These are used to
7783 signal a breakpoint to GDB.
7785 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
7786 modes. A different instruction is required for each mode. The ARM
7787 cpu's can also be big or little endian. Thus four different
7788 instructions are needed to support all cases.
7790 Note: ARMv4 defines several new instructions that will take the
7791 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
7792 not in fact add the new instructions. The new undefined
7793 instructions in ARMv4 are all instructions that had no defined
7794 behaviour in earlier chips. There is no guarantee that they will
7795 raise an exception, but may be treated as NOP's. In practice, it
7796 may only safe to rely on instructions matching:
7798 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
7799 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
7800 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
7802 Even this may only true if the condition predicate is true. The
7803 following use a condition predicate of ALWAYS so it is always TRUE.
7805 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
7806 and NetBSD all use a software interrupt rather than an undefined
7807 instruction to force a trap. This can be handled by by the
7808 abi-specific code during establishment of the gdbarch vector. */
7810 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
7811 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
7812 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
7813 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
7815 static const gdb_byte arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
7816 static const gdb_byte arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
7817 static const gdb_byte arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
7818 static const gdb_byte arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
7820 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7823 arm_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7825 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7826 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7828 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
7830 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
7832 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
7833 check whether we are replacing a 32-bit instruction. */
7834 if (tdep
->thumb2_breakpoint
!= NULL
)
7838 if (target_read_memory (*pcptr
, buf
, 2) == 0)
7840 unsigned short inst1
;
7842 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
7843 if (thumb_insn_size (inst1
) == 4)
7844 return ARM_BP_KIND_THUMB2
;
7848 return ARM_BP_KIND_THUMB
;
7851 return ARM_BP_KIND_ARM
;
7855 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7857 static const gdb_byte
*
7858 arm_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7860 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7864 case ARM_BP_KIND_ARM
:
7865 *size
= tdep
->arm_breakpoint_size
;
7866 return tdep
->arm_breakpoint
;
7867 case ARM_BP_KIND_THUMB
:
7868 *size
= tdep
->thumb_breakpoint_size
;
7869 return tdep
->thumb_breakpoint
;
7870 case ARM_BP_KIND_THUMB2
:
7871 *size
= tdep
->thumb2_breakpoint_size
;
7872 return tdep
->thumb2_breakpoint
;
7874 gdb_assert_not_reached ("unexpected arm breakpoint kind");
7878 /* Implement the breakpoint_kind_from_current_state gdbarch method. */
7881 arm_breakpoint_kind_from_current_state (struct gdbarch
*gdbarch
,
7882 struct regcache
*regcache
,
7887 /* Check the memory pointed by PC is readable. */
7888 if (target_read_memory (regcache_read_pc (regcache
), buf
, 4) == 0)
7890 struct arm_get_next_pcs next_pcs_ctx
;
7893 VEC (CORE_ADDR
) *next_pcs
= NULL
;
7894 struct cleanup
*old_chain
7895 = make_cleanup (VEC_cleanup (CORE_ADDR
), &next_pcs
);
7897 arm_get_next_pcs_ctor (&next_pcs_ctx
,
7898 &arm_get_next_pcs_ops
,
7899 gdbarch_byte_order (gdbarch
),
7900 gdbarch_byte_order_for_code (gdbarch
),
7904 next_pcs
= arm_get_next_pcs (&next_pcs_ctx
);
7906 /* If MEMADDR is the next instruction of current pc, do the
7907 software single step computation, and get the thumb mode by
7908 the destination address. */
7909 for (i
= 0; VEC_iterate (CORE_ADDR
, next_pcs
, i
, pc
); i
++)
7911 if (UNMAKE_THUMB_ADDR (pc
) == *pcptr
)
7913 do_cleanups (old_chain
);
7915 if (IS_THUMB_ADDR (pc
))
7917 *pcptr
= MAKE_THUMB_ADDR (*pcptr
);
7918 return arm_breakpoint_kind_from_pc (gdbarch
, pcptr
);
7921 return ARM_BP_KIND_ARM
;
7925 do_cleanups (old_chain
);
7928 return arm_breakpoint_kind_from_pc (gdbarch
, pcptr
);
7931 /* Extract from an array REGBUF containing the (raw) register state a
7932 function return value of type TYPE, and copy that, in virtual
7933 format, into VALBUF. */
7936 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
7939 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
7940 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7942 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
7944 switch (gdbarch_tdep (gdbarch
)->fp_model
)
7948 /* The value is in register F0 in internal format. We need to
7949 extract the raw value and then convert it to the desired
7951 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
7953 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
7954 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
7955 valbuf
, gdbarch_byte_order (gdbarch
));
7959 case ARM_FLOAT_SOFT_FPA
:
7960 case ARM_FLOAT_SOFT_VFP
:
7961 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7962 not using the VFP ABI code. */
7964 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
7965 if (TYPE_LENGTH (type
) > 4)
7966 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
7967 valbuf
+ INT_REGISTER_SIZE
);
7971 internal_error (__FILE__
, __LINE__
,
7972 _("arm_extract_return_value: "
7973 "Floating point model not supported"));
7977 else if (TYPE_CODE (type
) == TYPE_CODE_INT
7978 || TYPE_CODE (type
) == TYPE_CODE_CHAR
7979 || TYPE_CODE (type
) == TYPE_CODE_BOOL
7980 || TYPE_CODE (type
) == TYPE_CODE_PTR
7981 || TYPE_CODE (type
) == TYPE_CODE_REF
7982 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
7984 /* If the type is a plain integer, then the access is
7985 straight-forward. Otherwise we have to play around a bit
7987 int len
= TYPE_LENGTH (type
);
7988 int regno
= ARM_A1_REGNUM
;
7993 /* By using store_unsigned_integer we avoid having to do
7994 anything special for small big-endian values. */
7995 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
7996 store_unsigned_integer (valbuf
,
7997 (len
> INT_REGISTER_SIZE
7998 ? INT_REGISTER_SIZE
: len
),
8000 len
-= INT_REGISTER_SIZE
;
8001 valbuf
+= INT_REGISTER_SIZE
;
8006 /* For a structure or union the behaviour is as if the value had
8007 been stored to word-aligned memory and then loaded into
8008 registers with 32-bit load instruction(s). */
8009 int len
= TYPE_LENGTH (type
);
8010 int regno
= ARM_A1_REGNUM
;
8011 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8015 regcache_cooked_read (regs
, regno
++, tmpbuf
);
8016 memcpy (valbuf
, tmpbuf
,
8017 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
8018 len
-= INT_REGISTER_SIZE
;
8019 valbuf
+= INT_REGISTER_SIZE
;
8025 /* Will a function return an aggregate type in memory or in a
8026 register? Return 0 if an aggregate type can be returned in a
8027 register, 1 if it must be returned in memory. */
8030 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
8032 enum type_code code
;
8034 type
= check_typedef (type
);
8036 /* Simple, non-aggregate types (ie not including vectors and
8037 complex) are always returned in a register (or registers). */
8038 code
= TYPE_CODE (type
);
8039 if (TYPE_CODE_STRUCT
!= code
&& TYPE_CODE_UNION
!= code
8040 && TYPE_CODE_ARRAY
!= code
&& TYPE_CODE_COMPLEX
!= code
)
8043 if (TYPE_CODE_ARRAY
== code
&& TYPE_VECTOR (type
))
8045 /* Vector values should be returned using ARM registers if they
8046 are not over 16 bytes. */
8047 return (TYPE_LENGTH (type
) > 16);
8050 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
8052 /* The AAPCS says all aggregates not larger than a word are returned
8054 if (TYPE_LENGTH (type
) <= INT_REGISTER_SIZE
)
8063 /* All aggregate types that won't fit in a register must be returned
8065 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
8068 /* In the ARM ABI, "integer" like aggregate types are returned in
8069 registers. For an aggregate type to be integer like, its size
8070 must be less than or equal to INT_REGISTER_SIZE and the
8071 offset of each addressable subfield must be zero. Note that bit
8072 fields are not addressable, and all addressable subfields of
8073 unions always start at offset zero.
8075 This function is based on the behaviour of GCC 2.95.1.
8076 See: gcc/arm.c: arm_return_in_memory() for details.
8078 Note: All versions of GCC before GCC 2.95.2 do not set up the
8079 parameters correctly for a function returning the following
8080 structure: struct { float f;}; This should be returned in memory,
8081 not a register. Richard Earnshaw sent me a patch, but I do not
8082 know of any way to detect if a function like the above has been
8083 compiled with the correct calling convention. */
8085 /* Assume all other aggregate types can be returned in a register.
8086 Run a check for structures, unions and arrays. */
8089 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
8092 /* Need to check if this struct/union is "integer" like. For
8093 this to be true, its size must be less than or equal to
8094 INT_REGISTER_SIZE and the offset of each addressable
8095 subfield must be zero. Note that bit fields are not
8096 addressable, and unions always start at offset zero. If any
8097 of the subfields is a floating point type, the struct/union
8098 cannot be an integer type. */
8100 /* For each field in the object, check:
8101 1) Is it FP? --> yes, nRc = 1;
8102 2) Is it addressable (bitpos != 0) and
8103 not packed (bitsize == 0)?
8107 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
8109 enum type_code field_type_code
;
8112 = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
,
8115 /* Is it a floating point type field? */
8116 if (field_type_code
== TYPE_CODE_FLT
)
8122 /* If bitpos != 0, then we have to care about it. */
8123 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
8125 /* Bitfields are not addressable. If the field bitsize is
8126 zero, then the field is not packed. Hence it cannot be
8127 a bitfield or any other packed type. */
8128 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
8141 /* Write into appropriate registers a function return value of type
8142 TYPE, given in virtual format. */
8145 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
8146 const gdb_byte
*valbuf
)
8148 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
8149 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8151 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
8153 gdb_byte buf
[MAX_REGISTER_SIZE
];
8155 switch (gdbarch_tdep (gdbarch
)->fp_model
)
8159 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
8160 gdbarch_byte_order (gdbarch
));
8161 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
8164 case ARM_FLOAT_SOFT_FPA
:
8165 case ARM_FLOAT_SOFT_VFP
:
8166 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8167 not using the VFP ABI code. */
8169 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
8170 if (TYPE_LENGTH (type
) > 4)
8171 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
8172 valbuf
+ INT_REGISTER_SIZE
);
8176 internal_error (__FILE__
, __LINE__
,
8177 _("arm_store_return_value: Floating "
8178 "point model not supported"));
8182 else if (TYPE_CODE (type
) == TYPE_CODE_INT
8183 || TYPE_CODE (type
) == TYPE_CODE_CHAR
8184 || TYPE_CODE (type
) == TYPE_CODE_BOOL
8185 || TYPE_CODE (type
) == TYPE_CODE_PTR
8186 || TYPE_CODE (type
) == TYPE_CODE_REF
8187 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
8189 if (TYPE_LENGTH (type
) <= 4)
8191 /* Values of one word or less are zero/sign-extended and
8193 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8194 LONGEST val
= unpack_long (type
, valbuf
);
8196 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
8197 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
8201 /* Integral values greater than one word are stored in consecutive
8202 registers starting with r0. This will always be a multiple of
8203 the regiser size. */
8204 int len
= TYPE_LENGTH (type
);
8205 int regno
= ARM_A1_REGNUM
;
8209 regcache_cooked_write (regs
, regno
++, valbuf
);
8210 len
-= INT_REGISTER_SIZE
;
8211 valbuf
+= INT_REGISTER_SIZE
;
8217 /* For a structure or union the behaviour is as if the value had
8218 been stored to word-aligned memory and then loaded into
8219 registers with 32-bit load instruction(s). */
8220 int len
= TYPE_LENGTH (type
);
8221 int regno
= ARM_A1_REGNUM
;
8222 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8226 memcpy (tmpbuf
, valbuf
,
8227 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
8228 regcache_cooked_write (regs
, regno
++, tmpbuf
);
8229 len
-= INT_REGISTER_SIZE
;
8230 valbuf
+= INT_REGISTER_SIZE
;
8236 /* Handle function return values. */
8238 static enum return_value_convention
8239 arm_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
8240 struct type
*valtype
, struct regcache
*regcache
,
8241 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
8243 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8244 struct type
*func_type
= function
? value_type (function
) : NULL
;
8245 enum arm_vfp_cprc_base_type vfp_base_type
;
8248 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
8249 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
8251 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
8252 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
8254 for (i
= 0; i
< vfp_base_count
; i
++)
8256 if (reg_char
== 'q')
8259 arm_neon_quad_write (gdbarch
, regcache
, i
,
8260 writebuf
+ i
* unit_length
);
8263 arm_neon_quad_read (gdbarch
, regcache
, i
,
8264 readbuf
+ i
* unit_length
);
8271 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d", reg_char
, i
);
8272 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8275 regcache_cooked_write (regcache
, regnum
,
8276 writebuf
+ i
* unit_length
);
8278 regcache_cooked_read (regcache
, regnum
,
8279 readbuf
+ i
* unit_length
);
8282 return RETURN_VALUE_REGISTER_CONVENTION
;
8285 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
8286 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
8287 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
8289 if (tdep
->struct_return
== pcc_struct_return
8290 || arm_return_in_memory (gdbarch
, valtype
))
8291 return RETURN_VALUE_STRUCT_CONVENTION
;
8293 else if (TYPE_CODE (valtype
) == TYPE_CODE_COMPLEX
)
8295 if (arm_return_in_memory (gdbarch
, valtype
))
8296 return RETURN_VALUE_STRUCT_CONVENTION
;
8300 arm_store_return_value (valtype
, regcache
, writebuf
);
8303 arm_extract_return_value (valtype
, regcache
, readbuf
);
8305 return RETURN_VALUE_REGISTER_CONVENTION
;
8310 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
8312 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
8313 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8314 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8316 gdb_byte buf
[INT_REGISTER_SIZE
];
8318 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
8320 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
8324 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
8328 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
8329 return the target PC. Otherwise return 0. */
8332 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
8336 CORE_ADDR start_addr
;
8338 /* Find the starting address and name of the function containing the PC. */
8339 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
8341 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
8343 start_addr
= arm_skip_bx_reg (frame
, pc
);
8344 if (start_addr
!= 0)
8350 /* If PC is in a Thumb call or return stub, return the address of the
8351 target PC, which is in a register. The thunk functions are called
8352 _call_via_xx, where x is the register name. The possible names
8353 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
8354 functions, named __ARM_call_via_r[0-7]. */
8355 if (startswith (name
, "_call_via_")
8356 || startswith (name
, "__ARM_call_via_"))
8358 /* Use the name suffix to determine which register contains the
8360 static char *table
[15] =
8361 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8362 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
8365 int offset
= strlen (name
) - 2;
8367 for (regno
= 0; regno
<= 14; regno
++)
8368 if (strcmp (&name
[offset
], table
[regno
]) == 0)
8369 return get_frame_register_unsigned (frame
, regno
);
8372 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
8373 non-interworking calls to foo. We could decode the stubs
8374 to find the target but it's easier to use the symbol table. */
8375 namelen
= strlen (name
);
8376 if (name
[0] == '_' && name
[1] == '_'
8377 && ((namelen
> 2 + strlen ("_from_thumb")
8378 && startswith (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb"))
8379 || (namelen
> 2 + strlen ("_from_arm")
8380 && startswith (name
+ namelen
- strlen ("_from_arm"), "_from_arm"))))
8383 int target_len
= namelen
- 2;
8384 struct bound_minimal_symbol minsym
;
8385 struct objfile
*objfile
;
8386 struct obj_section
*sec
;
8388 if (name
[namelen
- 1] == 'b')
8389 target_len
-= strlen ("_from_thumb");
8391 target_len
-= strlen ("_from_arm");
8393 target_name
= (char *) alloca (target_len
+ 1);
8394 memcpy (target_name
, name
+ 2, target_len
);
8395 target_name
[target_len
] = '\0';
8397 sec
= find_pc_section (pc
);
8398 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
8399 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
8400 if (minsym
.minsym
!= NULL
)
8401 return BMSYMBOL_VALUE_ADDRESS (minsym
);
8406 return 0; /* not a stub */
8410 set_arm_command (char *args
, int from_tty
)
8412 printf_unfiltered (_("\
8413 \"set arm\" must be followed by an apporpriate subcommand.\n"));
8414 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
8418 show_arm_command (char *args
, int from_tty
)
8420 cmd_show_list (showarmcmdlist
, from_tty
, "");
8424 arm_update_current_architecture (void)
8426 struct gdbarch_info info
;
8428 /* If the current architecture is not ARM, we have nothing to do. */
8429 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_arm
)
8432 /* Update the architecture. */
8433 gdbarch_info_init (&info
);
8435 if (!gdbarch_update_p (info
))
8436 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
8440 set_fp_model_sfunc (char *args
, int from_tty
,
8441 struct cmd_list_element
*c
)
8445 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
8446 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
8448 arm_fp_model
= (enum arm_float_model
) fp_model
;
8452 if (fp_model
== ARM_FLOAT_LAST
)
8453 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
8456 arm_update_current_architecture ();
8460 show_fp_model (struct ui_file
*file
, int from_tty
,
8461 struct cmd_list_element
*c
, const char *value
)
8463 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8465 if (arm_fp_model
== ARM_FLOAT_AUTO
8466 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8467 fprintf_filtered (file
, _("\
8468 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
8469 fp_model_strings
[tdep
->fp_model
]);
8471 fprintf_filtered (file
, _("\
8472 The current ARM floating point model is \"%s\".\n"),
8473 fp_model_strings
[arm_fp_model
]);
8477 arm_set_abi (char *args
, int from_tty
,
8478 struct cmd_list_element
*c
)
8482 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
8483 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
8485 arm_abi_global
= (enum arm_abi_kind
) arm_abi
;
8489 if (arm_abi
== ARM_ABI_LAST
)
8490 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
8493 arm_update_current_architecture ();
8497 arm_show_abi (struct ui_file
*file
, int from_tty
,
8498 struct cmd_list_element
*c
, const char *value
)
8500 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8502 if (arm_abi_global
== ARM_ABI_AUTO
8503 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8504 fprintf_filtered (file
, _("\
8505 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
8506 arm_abi_strings
[tdep
->arm_abi
]);
8508 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
8513 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
8514 struct cmd_list_element
*c
, const char *value
)
8516 fprintf_filtered (file
,
8517 _("The current execution mode assumed "
8518 "(when symbols are unavailable) is \"%s\".\n"),
8519 arm_fallback_mode_string
);
8523 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
8524 struct cmd_list_element
*c
, const char *value
)
8526 fprintf_filtered (file
,
8527 _("The current execution mode assumed "
8528 "(even when symbols are available) is \"%s\".\n"),
8529 arm_force_mode_string
);
8532 /* If the user changes the register disassembly style used for info
8533 register and other commands, we have to also switch the style used
8534 in opcodes for disassembly output. This function is run in the "set
8535 arm disassembly" command, and does that. */
8538 set_disassembly_style_sfunc (char *args
, int from_tty
,
8539 struct cmd_list_element
*c
)
8541 set_disassembly_style ();
8544 /* Return the ARM register name corresponding to register I. */
8546 arm_register_name (struct gdbarch
*gdbarch
, int i
)
8548 const int num_regs
= gdbarch_num_regs (gdbarch
);
8550 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
8551 && i
>= num_regs
&& i
< num_regs
+ 32)
8553 static const char *const vfp_pseudo_names
[] = {
8554 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
8555 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
8556 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
8557 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
8560 return vfp_pseudo_names
[i
- num_regs
];
8563 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
8564 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
8566 static const char *const neon_pseudo_names
[] = {
8567 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
8568 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
8571 return neon_pseudo_names
[i
- num_regs
- 32];
8574 if (i
>= ARRAY_SIZE (arm_register_names
))
8575 /* These registers are only supported on targets which supply
8576 an XML description. */
8579 return arm_register_names
[i
];
8583 set_disassembly_style (void)
8587 /* Find the style that the user wants. */
8588 for (current
= 0; current
< num_disassembly_options
; current
++)
8589 if (disassembly_style
== valid_disassembly_styles
[current
])
8591 gdb_assert (current
< num_disassembly_options
);
8593 /* Synchronize the disassembler. */
8594 set_arm_regname_option (current
);
8597 /* Test whether the coff symbol specific value corresponds to a Thumb
8601 coff_sym_is_thumb (int val
)
8603 return (val
== C_THUMBEXT
8604 || val
== C_THUMBSTAT
8605 || val
== C_THUMBEXTFUNC
8606 || val
== C_THUMBSTATFUNC
8607 || val
== C_THUMBLABEL
);
8610 /* arm_coff_make_msymbol_special()
8611 arm_elf_make_msymbol_special()
8613 These functions test whether the COFF or ELF symbol corresponds to
8614 an address in thumb code, and set a "special" bit in a minimal
8615 symbol to indicate that it does. */
8618 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
8620 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
8622 if (ARM_GET_SYM_BRANCH_TYPE (elfsym
->internal_elf_sym
.st_target_internal
)
8623 == ST_BRANCH_TO_THUMB
)
8624 MSYMBOL_SET_SPECIAL (msym
);
8628 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
8630 if (coff_sym_is_thumb (val
))
8631 MSYMBOL_SET_SPECIAL (msym
);
8635 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
8637 struct arm_per_objfile
*data
= (struct arm_per_objfile
*) arg
;
8640 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
8641 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
8645 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
8648 const char *name
= bfd_asymbol_name (sym
);
8649 struct arm_per_objfile
*data
;
8650 VEC(arm_mapping_symbol_s
) **map_p
;
8651 struct arm_mapping_symbol new_map_sym
;
8653 gdb_assert (name
[0] == '$');
8654 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
8657 data
= (struct arm_per_objfile
*) objfile_data (objfile
,
8658 arm_objfile_data_key
);
8661 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
8662 struct arm_per_objfile
);
8663 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
8664 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
8665 objfile
->obfd
->section_count
,
8666 VEC(arm_mapping_symbol_s
) *);
8668 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
8670 new_map_sym
.value
= sym
->value
;
8671 new_map_sym
.type
= name
[1];
8673 /* Assume that most mapping symbols appear in order of increasing
8674 value. If they were randomly distributed, it would be faster to
8675 always push here and then sort at first use. */
8676 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
8678 struct arm_mapping_symbol
*prev_map_sym
;
8680 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
8681 if (prev_map_sym
->value
>= sym
->value
)
8684 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
8685 arm_compare_mapping_symbols
);
8686 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
8691 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
8695 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
8697 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
8698 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
8700 /* If necessary, set the T bit. */
8703 ULONGEST val
, t_bit
;
8704 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
8705 t_bit
= arm_psr_thumb_bit (gdbarch
);
8706 if (arm_pc_is_thumb (gdbarch
, pc
))
8707 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8710 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8715 /* Read the contents of a NEON quad register, by reading from two
8716 double registers. This is used to implement the quad pseudo
8717 registers, and for argument passing in case the quad registers are
8718 missing; vectors are passed in quad registers when using the VFP
8719 ABI, even if a NEON unit is not present. REGNUM is the index of
8720 the quad register, in [0, 15]. */
8722 static enum register_status
8723 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8724 int regnum
, gdb_byte
*buf
)
8727 gdb_byte reg_buf
[8];
8728 int offset
, double_regnum
;
8729 enum register_status status
;
8731 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8732 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8735 /* d0 is always the least significant half of q0. */
8736 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8741 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8742 if (status
!= REG_VALID
)
8744 memcpy (buf
+ offset
, reg_buf
, 8);
8746 offset
= 8 - offset
;
8747 status
= regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
8748 if (status
!= REG_VALID
)
8750 memcpy (buf
+ offset
, reg_buf
, 8);
8755 static enum register_status
8756 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8757 int regnum
, gdb_byte
*buf
)
8759 const int num_regs
= gdbarch_num_regs (gdbarch
);
8761 gdb_byte reg_buf
[8];
8762 int offset
, double_regnum
;
8764 gdb_assert (regnum
>= num_regs
);
8767 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8768 /* Quad-precision register. */
8769 return arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
8772 enum register_status status
;
8774 /* Single-precision register. */
8775 gdb_assert (regnum
< 32);
8777 /* s0 is always the least significant half of d0. */
8778 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8779 offset
= (regnum
& 1) ? 0 : 4;
8781 offset
= (regnum
& 1) ? 4 : 0;
8783 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8784 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8787 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8788 if (status
== REG_VALID
)
8789 memcpy (buf
, reg_buf
+ offset
, 4);
8794 /* Store the contents of BUF to a NEON quad register, by writing to
8795 two double registers. This is used to implement the quad pseudo
8796 registers, and for argument passing in case the quad registers are
8797 missing; vectors are passed in quad registers when using the VFP
8798 ABI, even if a NEON unit is not present. REGNUM is the index
8799 of the quad register, in [0, 15]. */
8802 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8803 int regnum
, const gdb_byte
*buf
)
8806 int offset
, double_regnum
;
8808 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8809 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8812 /* d0 is always the least significant half of q0. */
8813 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8818 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
8819 offset
= 8 - offset
;
8820 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
8824 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8825 int regnum
, const gdb_byte
*buf
)
8827 const int num_regs
= gdbarch_num_regs (gdbarch
);
8829 gdb_byte reg_buf
[8];
8830 int offset
, double_regnum
;
8832 gdb_assert (regnum
>= num_regs
);
8835 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8836 /* Quad-precision register. */
8837 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
8840 /* Single-precision register. */
8841 gdb_assert (regnum
< 32);
8843 /* s0 is always the least significant half of d0. */
8844 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8845 offset
= (regnum
& 1) ? 0 : 4;
8847 offset
= (regnum
& 1) ? 4 : 0;
8849 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8850 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8853 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8854 memcpy (reg_buf
+ offset
, buf
, 4);
8855 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
8859 static struct value
*
8860 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
8862 const int *reg_p
= (const int *) baton
;
8863 return value_of_register (*reg_p
, frame
);
8866 static enum gdb_osabi
8867 arm_elf_osabi_sniffer (bfd
*abfd
)
8869 unsigned int elfosabi
;
8870 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
8872 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
8874 if (elfosabi
== ELFOSABI_ARM
)
8875 /* GNU tools use this value. Check note sections in this case,
8877 bfd_map_over_sections (abfd
,
8878 generic_elf_osabi_sniff_abi_tag_sections
,
8881 /* Anything else will be handled by the generic ELF sniffer. */
8886 arm_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
8887 struct reggroup
*group
)
8889 /* FPS register's type is INT, but belongs to float_reggroup. Beside
8890 this, FPS register belongs to save_regroup, restore_reggroup, and
8891 all_reggroup, of course. */
8892 if (regnum
== ARM_FPS_REGNUM
)
8893 return (group
== float_reggroup
8894 || group
== save_reggroup
8895 || group
== restore_reggroup
8896 || group
== all_reggroup
);
8898 return default_register_reggroup_p (gdbarch
, regnum
, group
);
8902 /* For backward-compatibility we allow two 'g' packet lengths with
8903 the remote protocol depending on whether FPA registers are
8904 supplied. M-profile targets do not have FPA registers, but some
8905 stubs already exist in the wild which use a 'g' packet which
8906 supplies them albeit with dummy values. The packet format which
8907 includes FPA registers should be considered deprecated for
8908 M-profile targets. */
8911 arm_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8913 if (gdbarch_tdep (gdbarch
)->is_m
)
8915 /* If we know from the executable this is an M-profile target,
8916 cater for remote targets whose register set layout is the
8917 same as the FPA layout. */
8918 register_remote_g_packet_guess (gdbarch
,
8919 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
8920 (16 * INT_REGISTER_SIZE
)
8921 + (8 * FP_REGISTER_SIZE
)
8922 + (2 * INT_REGISTER_SIZE
),
8923 tdesc_arm_with_m_fpa_layout
);
8925 /* The regular M-profile layout. */
8926 register_remote_g_packet_guess (gdbarch
,
8927 /* r0-r12,sp,lr,pc; xpsr */
8928 (16 * INT_REGISTER_SIZE
)
8929 + INT_REGISTER_SIZE
,
8932 /* M-profile plus M4F VFP. */
8933 register_remote_g_packet_guess (gdbarch
,
8934 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
8935 (16 * INT_REGISTER_SIZE
)
8936 + (16 * VFP_REGISTER_SIZE
)
8937 + (2 * INT_REGISTER_SIZE
),
8938 tdesc_arm_with_m_vfp_d16
);
8941 /* Otherwise we don't have a useful guess. */
8944 /* Implement the code_of_frame_writable gdbarch method. */
8947 arm_code_of_frame_writable (struct gdbarch
*gdbarch
, struct frame_info
*frame
)
8949 if (gdbarch_tdep (gdbarch
)->is_m
8950 && get_frame_type (frame
) == SIGTRAMP_FRAME
)
8952 /* M-profile exception frames return to some magic PCs, where
8953 isn't writable at all. */
8961 /* Initialize the current architecture based on INFO. If possible,
8962 re-use an architecture from ARCHES, which is a list of
8963 architectures already created during this debugging session.
8965 Called e.g. at program startup, when reading a core file, and when
8966 reading a binary file. */
8968 static struct gdbarch
*
8969 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8971 struct gdbarch_tdep
*tdep
;
8972 struct gdbarch
*gdbarch
;
8973 struct gdbarch_list
*best_arch
;
8974 enum arm_abi_kind arm_abi
= arm_abi_global
;
8975 enum arm_float_model fp_model
= arm_fp_model
;
8976 struct tdesc_arch_data
*tdesc_data
= NULL
;
8978 int vfp_register_count
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
8979 int have_wmmx_registers
= 0;
8981 int have_fpa_registers
= 1;
8982 const struct target_desc
*tdesc
= info
.target_desc
;
8984 /* If we have an object to base this architecture on, try to determine
8987 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
8989 int ei_osabi
, e_flags
;
8991 switch (bfd_get_flavour (info
.abfd
))
8993 case bfd_target_coff_flavour
:
8994 /* Assume it's an old APCS-style ABI. */
8996 arm_abi
= ARM_ABI_APCS
;
8999 case bfd_target_elf_flavour
:
9000 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
9001 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9003 if (ei_osabi
== ELFOSABI_ARM
)
9005 /* GNU tools used to use this value, but do not for EABI
9006 objects. There's nowhere to tag an EABI version
9007 anyway, so assume APCS. */
9008 arm_abi
= ARM_ABI_APCS
;
9010 else if (ei_osabi
== ELFOSABI_NONE
|| ei_osabi
== ELFOSABI_GNU
)
9012 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
9013 int attr_arch
, attr_profile
;
9017 case EF_ARM_EABI_UNKNOWN
:
9018 /* Assume GNU tools. */
9019 arm_abi
= ARM_ABI_APCS
;
9022 case EF_ARM_EABI_VER4
:
9023 case EF_ARM_EABI_VER5
:
9024 arm_abi
= ARM_ABI_AAPCS
;
9025 /* EABI binaries default to VFP float ordering.
9026 They may also contain build attributes that can
9027 be used to identify if the VFP argument-passing
9029 if (fp_model
== ARM_FLOAT_AUTO
)
9032 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
9036 case AEABI_VFP_args_base
:
9037 /* "The user intended FP parameter/result
9038 passing to conform to AAPCS, base
9040 fp_model
= ARM_FLOAT_SOFT_VFP
;
9042 case AEABI_VFP_args_vfp
:
9043 /* "The user intended FP parameter/result
9044 passing to conform to AAPCS, VFP
9046 fp_model
= ARM_FLOAT_VFP
;
9048 case AEABI_VFP_args_toolchain
:
9049 /* "The user intended FP parameter/result
9050 passing to conform to tool chain-specific
9051 conventions" - we don't know any such
9052 conventions, so leave it as "auto". */
9054 case AEABI_VFP_args_compatible
:
9055 /* "Code is compatible with both the base
9056 and VFP variants; the user did not permit
9057 non-variadic functions to pass FP
9058 parameters/results" - leave it as
9062 /* Attribute value not mentioned in the
9063 November 2012 ABI, so leave it as
9068 fp_model
= ARM_FLOAT_SOFT_VFP
;
9074 /* Leave it as "auto". */
9075 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
9080 /* Detect M-profile programs. This only works if the
9081 executable file includes build attributes; GCC does
9082 copy them to the executable, but e.g. RealView does
9084 attr_arch
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
9086 attr_profile
= bfd_elf_get_obj_attr_int (info
.abfd
,
9088 Tag_CPU_arch_profile
);
9089 /* GCC specifies the profile for v6-M; RealView only
9090 specifies the profile for architectures starting with
9091 V7 (as opposed to architectures with a tag
9092 numerically greater than TAG_CPU_ARCH_V7). */
9093 if (!tdesc_has_registers (tdesc
)
9094 && (attr_arch
== TAG_CPU_ARCH_V6_M
9095 || attr_arch
== TAG_CPU_ARCH_V6S_M
9096 || attr_profile
== 'M'))
9101 if (fp_model
== ARM_FLOAT_AUTO
)
9103 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9105 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
9108 /* Leave it as "auto". Strictly speaking this case
9109 means FPA, but almost nobody uses that now, and
9110 many toolchains fail to set the appropriate bits
9111 for the floating-point model they use. */
9113 case EF_ARM_SOFT_FLOAT
:
9114 fp_model
= ARM_FLOAT_SOFT_FPA
;
9116 case EF_ARM_VFP_FLOAT
:
9117 fp_model
= ARM_FLOAT_VFP
;
9119 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
9120 fp_model
= ARM_FLOAT_SOFT_VFP
;
9125 if (e_flags
& EF_ARM_BE8
)
9126 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
9131 /* Leave it as "auto". */
9136 /* Check any target description for validity. */
9137 if (tdesc_has_registers (tdesc
))
9139 /* For most registers we require GDB's default names; but also allow
9140 the numeric names for sp / lr / pc, as a convenience. */
9141 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
9142 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
9143 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
9145 const struct tdesc_feature
*feature
;
9148 feature
= tdesc_find_feature (tdesc
,
9149 "org.gnu.gdb.arm.core");
9150 if (feature
== NULL
)
9152 feature
= tdesc_find_feature (tdesc
,
9153 "org.gnu.gdb.arm.m-profile");
9154 if (feature
== NULL
)
9160 tdesc_data
= tdesc_data_alloc ();
9163 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
9164 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9165 arm_register_names
[i
]);
9166 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9169 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9172 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9176 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9177 ARM_PS_REGNUM
, "xpsr");
9179 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9180 ARM_PS_REGNUM
, "cpsr");
9184 tdesc_data_cleanup (tdesc_data
);
9188 feature
= tdesc_find_feature (tdesc
,
9189 "org.gnu.gdb.arm.fpa");
9190 if (feature
!= NULL
)
9193 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
9194 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9195 arm_register_names
[i
]);
9198 tdesc_data_cleanup (tdesc_data
);
9203 have_fpa_registers
= 0;
9205 feature
= tdesc_find_feature (tdesc
,
9206 "org.gnu.gdb.xscale.iwmmxt");
9207 if (feature
!= NULL
)
9209 static const char *const iwmmxt_names
[] = {
9210 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
9211 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
9212 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
9213 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
9217 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
9219 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9220 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9222 /* Check for the control registers, but do not fail if they
9224 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
9225 tdesc_numbered_register (feature
, tdesc_data
, i
,
9226 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9228 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
9230 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9231 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9235 tdesc_data_cleanup (tdesc_data
);
9239 have_wmmx_registers
= 1;
9242 /* If we have a VFP unit, check whether the single precision registers
9243 are present. If not, then we will synthesize them as pseudo
9245 feature
= tdesc_find_feature (tdesc
,
9246 "org.gnu.gdb.arm.vfp");
9247 if (feature
!= NULL
)
9249 static const char *const vfp_double_names
[] = {
9250 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
9251 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
9252 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
9253 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
9256 /* Require the double precision registers. There must be either
9259 for (i
= 0; i
< 32; i
++)
9261 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9263 vfp_double_names
[i
]);
9267 if (!valid_p
&& i
== 16)
9270 /* Also require FPSCR. */
9271 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9272 ARM_FPSCR_REGNUM
, "fpscr");
9275 tdesc_data_cleanup (tdesc_data
);
9279 if (tdesc_unnumbered_register (feature
, "s0") == 0)
9280 have_vfp_pseudos
= 1;
9282 vfp_register_count
= i
;
9284 /* If we have VFP, also check for NEON. The architecture allows
9285 NEON without VFP (integer vector operations only), but GDB
9286 does not support that. */
9287 feature
= tdesc_find_feature (tdesc
,
9288 "org.gnu.gdb.arm.neon");
9289 if (feature
!= NULL
)
9291 /* NEON requires 32 double-precision registers. */
9294 tdesc_data_cleanup (tdesc_data
);
9298 /* If there are quad registers defined by the stub, use
9299 their type; otherwise (normally) provide them with
9300 the default type. */
9301 if (tdesc_unnumbered_register (feature
, "q0") == 0)
9302 have_neon_pseudos
= 1;
9309 /* If there is already a candidate, use it. */
9310 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
9312 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
9314 if (arm_abi
!= ARM_ABI_AUTO
9315 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
9318 if (fp_model
!= ARM_FLOAT_AUTO
9319 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
9322 /* There are various other properties in tdep that we do not
9323 need to check here: those derived from a target description,
9324 since gdbarches with a different target description are
9325 automatically disqualified. */
9327 /* Do check is_m, though, since it might come from the binary. */
9328 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
9331 /* Found a match. */
9335 if (best_arch
!= NULL
)
9337 if (tdesc_data
!= NULL
)
9338 tdesc_data_cleanup (tdesc_data
);
9339 return best_arch
->gdbarch
;
9342 tdep
= XCNEW (struct gdbarch_tdep
);
9343 gdbarch
= gdbarch_alloc (&info
, tdep
);
9345 /* Record additional information about the architecture we are defining.
9346 These are gdbarch discriminators, like the OSABI. */
9347 tdep
->arm_abi
= arm_abi
;
9348 tdep
->fp_model
= fp_model
;
9350 tdep
->have_fpa_registers
= have_fpa_registers
;
9351 tdep
->have_wmmx_registers
= have_wmmx_registers
;
9352 gdb_assert (vfp_register_count
== 0
9353 || vfp_register_count
== 16
9354 || vfp_register_count
== 32);
9355 tdep
->vfp_register_count
= vfp_register_count
;
9356 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
9357 tdep
->have_neon_pseudos
= have_neon_pseudos
;
9358 tdep
->have_neon
= have_neon
;
9360 arm_register_g_packet_guesses (gdbarch
);
9363 switch (info
.byte_order_for_code
)
9365 case BFD_ENDIAN_BIG
:
9366 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
9367 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
9368 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
9369 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
9373 case BFD_ENDIAN_LITTLE
:
9374 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
9375 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
9376 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
9377 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
9382 internal_error (__FILE__
, __LINE__
,
9383 _("arm_gdbarch_init: bad byte order for float format"));
9386 /* On ARM targets char defaults to unsigned. */
9387 set_gdbarch_char_signed (gdbarch
, 0);
9389 /* Note: for displaced stepping, this includes the breakpoint, and one word
9390 of additional scratch space. This setting isn't used for anything beside
9391 displaced stepping at present. */
9392 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
9394 /* This should be low enough for everything. */
9395 tdep
->lowest_pc
= 0x20;
9396 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
9398 /* The default, for both APCS and AAPCS, is to return small
9399 structures in registers. */
9400 tdep
->struct_return
= reg_struct_return
;
9402 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
9403 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
9406 set_gdbarch_code_of_frame_writable (gdbarch
, arm_code_of_frame_writable
);
9408 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
9410 /* Frame handling. */
9411 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
9412 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
9413 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
9415 frame_base_set_default (gdbarch
, &arm_normal_base
);
9417 /* Address manipulation. */
9418 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
9420 /* Advance PC across function entry code. */
9421 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
9423 /* Detect whether PC is at a point where the stack has been destroyed. */
9424 set_gdbarch_stack_frame_destroyed_p (gdbarch
, arm_stack_frame_destroyed_p
);
9426 /* Skip trampolines. */
9427 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
9429 /* The stack grows downward. */
9430 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
9432 /* Breakpoint manipulation. */
9433 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, arm_breakpoint_kind_from_pc
);
9434 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, arm_sw_breakpoint_from_kind
);
9435 set_gdbarch_breakpoint_kind_from_current_state (gdbarch
,
9436 arm_breakpoint_kind_from_current_state
);
9438 /* Information about registers, etc. */
9439 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
9440 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
9441 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
9442 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9443 set_gdbarch_register_reggroup_p (gdbarch
, arm_register_reggroup_p
);
9445 /* This "info float" is FPA-specific. Use the generic version if we
9447 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
9448 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
9450 /* Internal <-> external register number maps. */
9451 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
9452 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
9454 set_gdbarch_register_name (gdbarch
, arm_register_name
);
9456 /* Returning results. */
9457 set_gdbarch_return_value (gdbarch
, arm_return_value
);
9460 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
9462 /* Minsymbol frobbing. */
9463 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
9464 set_gdbarch_coff_make_msymbol_special (gdbarch
,
9465 arm_coff_make_msymbol_special
);
9466 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
9468 /* Thumb-2 IT block support. */
9469 set_gdbarch_adjust_breakpoint_address (gdbarch
,
9470 arm_adjust_breakpoint_address
);
9472 /* Virtual tables. */
9473 set_gdbarch_vbit_in_delta (gdbarch
, 1);
9475 /* Hook in the ABI-specific overrides, if they have been registered. */
9476 gdbarch_init_osabi (info
, gdbarch
);
9478 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
9480 /* Add some default predicates. */
9482 frame_unwind_append_unwinder (gdbarch
, &arm_m_exception_unwind
);
9483 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
9484 dwarf2_append_unwinders (gdbarch
);
9485 frame_unwind_append_unwinder (gdbarch
, &arm_exidx_unwind
);
9486 frame_unwind_append_unwinder (gdbarch
, &arm_epilogue_frame_unwind
);
9487 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
9489 /* Now we have tuned the configuration, set a few final things,
9490 based on what the OS ABI has told us. */
9492 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
9493 binaries are always marked. */
9494 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
9495 tdep
->arm_abi
= ARM_ABI_APCS
;
9497 /* Watchpoints are not steppable. */
9498 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
9500 /* We used to default to FPA for generic ARM, but almost nobody
9501 uses that now, and we now provide a way for the user to force
9502 the model. So default to the most useful variant. */
9503 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
9504 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
9506 if (tdep
->jb_pc
>= 0)
9507 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
9509 /* Floating point sizes and format. */
9510 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
9511 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
9513 set_gdbarch_double_format
9514 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9515 set_gdbarch_long_double_format
9516 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9520 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
9521 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
9524 if (have_vfp_pseudos
)
9526 /* NOTE: These are the only pseudo registers used by
9527 the ARM target at the moment. If more are added, a
9528 little more care in numbering will be needed. */
9530 int num_pseudos
= 32;
9531 if (have_neon_pseudos
)
9533 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
9534 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
9535 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
9540 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
9542 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
9544 /* Override tdesc_register_type to adjust the types of VFP
9545 registers for NEON. */
9546 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9549 /* Add standard register aliases. We add aliases even for those
9550 nanes which are used by the current architecture - it's simpler,
9551 and does no harm, since nothing ever lists user registers. */
9552 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
9553 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
9554 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
9560 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
9562 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9567 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
9568 (unsigned long) tdep
->lowest_pc
);
9571 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
9574 _initialize_arm_tdep (void)
9576 struct ui_file
*stb
;
9578 const char *setname
;
9579 const char *setdesc
;
9580 const char *const *regnames
;
9582 static std::string helptext
;
9583 char regdesc
[1024], *rdptr
= regdesc
;
9584 size_t rest
= sizeof (regdesc
);
9586 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
9588 arm_objfile_data_key
9589 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
9591 /* Add ourselves to objfile event chain. */
9592 observer_attach_new_objfile (arm_exidx_new_objfile
);
9594 = register_objfile_data_with_cleanup (NULL
, arm_exidx_data_free
);
9596 /* Register an ELF OS ABI sniffer for ARM binaries. */
9597 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
9598 bfd_target_elf_flavour
,
9599 arm_elf_osabi_sniffer
);
9601 /* Initialize the standard target descriptions. */
9602 initialize_tdesc_arm_with_m ();
9603 initialize_tdesc_arm_with_m_fpa_layout ();
9604 initialize_tdesc_arm_with_m_vfp_d16 ();
9605 initialize_tdesc_arm_with_iwmmxt ();
9606 initialize_tdesc_arm_with_vfpv2 ();
9607 initialize_tdesc_arm_with_vfpv3 ();
9608 initialize_tdesc_arm_with_neon ();
9610 /* Get the number of possible sets of register names defined in opcodes. */
9611 num_disassembly_options
= get_arm_regname_num_options ();
9613 /* Add root prefix command for all "set arm"/"show arm" commands. */
9614 add_prefix_cmd ("arm", no_class
, set_arm_command
,
9615 _("Various ARM-specific commands."),
9616 &setarmcmdlist
, "set arm ", 0, &setlist
);
9618 add_prefix_cmd ("arm", no_class
, show_arm_command
,
9619 _("Various ARM-specific commands."),
9620 &showarmcmdlist
, "show arm ", 0, &showlist
);
9622 /* Sync the opcode insn printer with our register viewer. */
9623 parse_arm_disassembler_option ("reg-names-std");
9625 /* Initialize the array that will be passed to
9626 add_setshow_enum_cmd(). */
9627 valid_disassembly_styles
= XNEWVEC (const char *,
9628 num_disassembly_options
+ 1);
9629 for (i
= 0; i
< num_disassembly_options
; i
++)
9631 get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
9632 valid_disassembly_styles
[i
] = setname
;
9633 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
9636 /* When we find the default names, tell the disassembler to use
9638 if (!strcmp (setname
, "std"))
9640 disassembly_style
= setname
;
9641 set_arm_regname_option (i
);
9644 /* Mark the end of valid options. */
9645 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
9647 /* Create the help text. */
9648 stb
= mem_fileopen ();
9649 fprintf_unfiltered (stb
, "%s%s%s",
9650 _("The valid values are:\n"),
9652 _("The default is \"std\"."));
9653 helptext
= ui_file_as_string (stb
);
9654 ui_file_delete (stb
);
9656 add_setshow_enum_cmd("disassembler", no_class
,
9657 valid_disassembly_styles
, &disassembly_style
,
9658 _("Set the disassembly style."),
9659 _("Show the disassembly style."),
9661 set_disassembly_style_sfunc
,
9662 NULL
, /* FIXME: i18n: The disassembly style is
9664 &setarmcmdlist
, &showarmcmdlist
);
9666 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
9667 _("Set usage of ARM 32-bit mode."),
9668 _("Show usage of ARM 32-bit mode."),
9669 _("When off, a 26-bit PC will be used."),
9671 NULL
, /* FIXME: i18n: Usage of ARM 32-bit
9673 &setarmcmdlist
, &showarmcmdlist
);
9675 /* Add a command to allow the user to force the FPU model. */
9676 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
9677 _("Set the floating point type."),
9678 _("Show the floating point type."),
9679 _("auto - Determine the FP typefrom the OS-ABI.\n\
9680 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
9681 fpa - FPA co-processor (GCC compiled).\n\
9682 softvfp - Software FP with pure-endian doubles.\n\
9683 vfp - VFP co-processor."),
9684 set_fp_model_sfunc
, show_fp_model
,
9685 &setarmcmdlist
, &showarmcmdlist
);
9687 /* Add a command to allow the user to force the ABI. */
9688 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
9691 NULL
, arm_set_abi
, arm_show_abi
,
9692 &setarmcmdlist
, &showarmcmdlist
);
9694 /* Add two commands to allow the user to force the assumed
9696 add_setshow_enum_cmd ("fallback-mode", class_support
,
9697 arm_mode_strings
, &arm_fallback_mode_string
,
9698 _("Set the mode assumed when symbols are unavailable."),
9699 _("Show the mode assumed when symbols are unavailable."),
9700 NULL
, NULL
, arm_show_fallback_mode
,
9701 &setarmcmdlist
, &showarmcmdlist
);
9702 add_setshow_enum_cmd ("force-mode", class_support
,
9703 arm_mode_strings
, &arm_force_mode_string
,
9704 _("Set the mode assumed even when symbols are available."),
9705 _("Show the mode assumed even when symbols are available."),
9706 NULL
, NULL
, arm_show_force_mode
,
9707 &setarmcmdlist
, &showarmcmdlist
);
9709 /* Debugging flag. */
9710 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
9711 _("Set ARM debugging."),
9712 _("Show ARM debugging."),
9713 _("When on, arm-specific debugging is enabled."),
9715 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
9716 &setdebuglist
, &showdebuglist
);
9719 /* ARM-reversible process record data structures. */
9721 #define ARM_INSN_SIZE_BYTES 4
9722 #define THUMB_INSN_SIZE_BYTES 2
9723 #define THUMB2_INSN_SIZE_BYTES 4
9726 /* Position of the bit within a 32-bit ARM instruction
9727 that defines whether the instruction is a load or store. */
9728 #define INSN_S_L_BIT_NUM 20
9730 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
9733 unsigned int reg_len = LENGTH; \
9736 REGS = XNEWVEC (uint32_t, reg_len); \
9737 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
9742 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
9745 unsigned int mem_len = LENGTH; \
9748 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
9749 memcpy(&MEMS->len, &RECORD_BUF[0], \
9750 sizeof(struct arm_mem_r) * LENGTH); \
9755 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
9756 #define INSN_RECORDED(ARM_RECORD) \
9757 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
9759 /* ARM memory record structure. */
9762 uint32_t len
; /* Record length. */
9763 uint32_t addr
; /* Memory address. */
9766 /* ARM instruction record contains opcode of current insn
9767 and execution state (before entry to decode_insn()),
9768 contains list of to-be-modified registers and
9769 memory blocks (on return from decode_insn()). */
9771 typedef struct insn_decode_record_t
9773 struct gdbarch
*gdbarch
;
9774 struct regcache
*regcache
;
9775 CORE_ADDR this_addr
; /* Address of the insn being decoded. */
9776 uint32_t arm_insn
; /* Should accommodate thumb. */
9777 uint32_t cond
; /* Condition code. */
9778 uint32_t opcode
; /* Insn opcode. */
9779 uint32_t decode
; /* Insn decode bits. */
9780 uint32_t mem_rec_count
; /* No of mem records. */
9781 uint32_t reg_rec_count
; /* No of reg records. */
9782 uint32_t *arm_regs
; /* Registers to be saved for this record. */
9783 struct arm_mem_r
*arm_mems
; /* Memory to be saved for this record. */
9784 } insn_decode_record
;
9787 /* Checks ARM SBZ and SBO mandatory fields. */
9790 sbo_sbz (uint32_t insn
, uint32_t bit_num
, uint32_t len
, uint32_t sbo
)
9792 uint32_t ones
= bits (insn
, bit_num
- 1, (bit_num
-1) + (len
- 1));
9811 enum arm_record_result
9813 ARM_RECORD_SUCCESS
= 0,
9814 ARM_RECORD_FAILURE
= 1
9821 } arm_record_strx_t
;
9832 arm_record_strx (insn_decode_record
*arm_insn_r
, uint32_t *record_buf
,
9833 uint32_t *record_buf_mem
, arm_record_strx_t str_type
)
9836 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
9837 ULONGEST u_regval
[2]= {0};
9839 uint32_t reg_src1
= 0, reg_src2
= 0;
9840 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
9842 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
9843 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
9845 if (14 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
9847 /* 1) Handle misc store, immediate offset. */
9848 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9849 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9850 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9851 regcache_raw_read_unsigned (reg_cache
, reg_src1
,
9853 if (ARM_PC_REGNUM
== reg_src1
)
9855 /* If R15 was used as Rn, hence current PC+8. */
9856 u_regval
[0] = u_regval
[0] + 8;
9858 offset_8
= (immed_high
<< 4) | immed_low
;
9859 /* Calculate target store address. */
9860 if (14 == arm_insn_r
->opcode
)
9862 tgt_mem_addr
= u_regval
[0] + offset_8
;
9866 tgt_mem_addr
= u_regval
[0] - offset_8
;
9868 if (ARM_RECORD_STRH
== str_type
)
9870 record_buf_mem
[0] = 2;
9871 record_buf_mem
[1] = tgt_mem_addr
;
9872 arm_insn_r
->mem_rec_count
= 1;
9874 else if (ARM_RECORD_STRD
== str_type
)
9876 record_buf_mem
[0] = 4;
9877 record_buf_mem
[1] = tgt_mem_addr
;
9878 record_buf_mem
[2] = 4;
9879 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9880 arm_insn_r
->mem_rec_count
= 2;
9883 else if (12 == arm_insn_r
->opcode
|| 8 == arm_insn_r
->opcode
)
9885 /* 2) Store, register offset. */
9887 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9889 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9890 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9891 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9894 /* If R15 was used as Rn, hence current PC+8. */
9895 u_regval
[0] = u_regval
[0] + 8;
9897 /* Calculate target store address, Rn +/- Rm, register offset. */
9898 if (12 == arm_insn_r
->opcode
)
9900 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9904 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9906 if (ARM_RECORD_STRH
== str_type
)
9908 record_buf_mem
[0] = 2;
9909 record_buf_mem
[1] = tgt_mem_addr
;
9910 arm_insn_r
->mem_rec_count
= 1;
9912 else if (ARM_RECORD_STRD
== str_type
)
9914 record_buf_mem
[0] = 4;
9915 record_buf_mem
[1] = tgt_mem_addr
;
9916 record_buf_mem
[2] = 4;
9917 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9918 arm_insn_r
->mem_rec_count
= 2;
9921 else if (11 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
9922 || 2 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9924 /* 3) Store, immediate pre-indexed. */
9925 /* 5) Store, immediate post-indexed. */
9926 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9927 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9928 offset_8
= (immed_high
<< 4) | immed_low
;
9929 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9930 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9931 /* Calculate target store address, Rn +/- Rm, register offset. */
9932 if (15 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9934 tgt_mem_addr
= u_regval
[0] + offset_8
;
9938 tgt_mem_addr
= u_regval
[0] - offset_8
;
9940 if (ARM_RECORD_STRH
== str_type
)
9942 record_buf_mem
[0] = 2;
9943 record_buf_mem
[1] = tgt_mem_addr
;
9944 arm_insn_r
->mem_rec_count
= 1;
9946 else if (ARM_RECORD_STRD
== str_type
)
9948 record_buf_mem
[0] = 4;
9949 record_buf_mem
[1] = tgt_mem_addr
;
9950 record_buf_mem
[2] = 4;
9951 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9952 arm_insn_r
->mem_rec_count
= 2;
9954 /* Record Rn also as it changes. */
9955 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
9956 arm_insn_r
->reg_rec_count
= 1;
9958 else if (9 == arm_insn_r
->opcode
|| 13 == arm_insn_r
->opcode
9959 || 0 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9961 /* 4) Store, register pre-indexed. */
9962 /* 6) Store, register post -indexed. */
9963 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9964 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9965 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9966 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9967 /* Calculate target store address, Rn +/- Rm, register offset. */
9968 if (13 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9970 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9974 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9976 if (ARM_RECORD_STRH
== str_type
)
9978 record_buf_mem
[0] = 2;
9979 record_buf_mem
[1] = tgt_mem_addr
;
9980 arm_insn_r
->mem_rec_count
= 1;
9982 else if (ARM_RECORD_STRD
== str_type
)
9984 record_buf_mem
[0] = 4;
9985 record_buf_mem
[1] = tgt_mem_addr
;
9986 record_buf_mem
[2] = 4;
9987 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9988 arm_insn_r
->mem_rec_count
= 2;
9990 /* Record Rn also as it changes. */
9991 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
9992 arm_insn_r
->reg_rec_count
= 1;
9997 /* Handling ARM extension space insns. */
10000 arm_record_extension_space (insn_decode_record
*arm_insn_r
)
10002 uint32_t ret
= 0; /* Return value: -1:record failure ; 0:success */
10003 uint32_t opcode1
= 0, opcode2
= 0, insn_op1
= 0;
10004 uint32_t record_buf
[8], record_buf_mem
[8];
10005 uint32_t reg_src1
= 0;
10006 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10007 ULONGEST u_regval
= 0;
10009 gdb_assert (!INSN_RECORDED(arm_insn_r
));
10010 /* Handle unconditional insn extension space. */
10012 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 27);
10013 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10014 if (arm_insn_r
->cond
)
10016 /* PLD has no affect on architectural state, it just affects
10018 if (5 == ((opcode1
& 0xE0) >> 5))
10021 record_buf
[0] = ARM_PS_REGNUM
;
10022 record_buf
[1] = ARM_LR_REGNUM
;
10023 arm_insn_r
->reg_rec_count
= 2;
10025 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10029 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10030 if (3 == opcode1
&& bit (arm_insn_r
->arm_insn
, 4))
10033 /* Undefined instruction on ARM V5; need to handle if later
10034 versions define it. */
10037 opcode1
= bits (arm_insn_r
->arm_insn
, 24, 27);
10038 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10039 insn_op1
= bits (arm_insn_r
->arm_insn
, 20, 23);
10041 /* Handle arithmetic insn extension space. */
10042 if (!opcode1
&& 9 == opcode2
&& 1 != arm_insn_r
->cond
10043 && !INSN_RECORDED(arm_insn_r
))
10045 /* Handle MLA(S) and MUL(S). */
10046 if (0 <= insn_op1
&& 3 >= insn_op1
)
10048 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10049 record_buf
[1] = ARM_PS_REGNUM
;
10050 arm_insn_r
->reg_rec_count
= 2;
10052 else if (4 <= insn_op1
&& 15 >= insn_op1
)
10054 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
10055 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10056 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10057 record_buf
[2] = ARM_PS_REGNUM
;
10058 arm_insn_r
->reg_rec_count
= 3;
10062 opcode1
= bits (arm_insn_r
->arm_insn
, 26, 27);
10063 opcode2
= bits (arm_insn_r
->arm_insn
, 23, 24);
10064 insn_op1
= bits (arm_insn_r
->arm_insn
, 21, 22);
10066 /* Handle control insn extension space. */
10068 if (!opcode1
&& 2 == opcode2
&& !bit (arm_insn_r
->arm_insn
, 20)
10069 && 1 != arm_insn_r
->cond
&& !INSN_RECORDED(arm_insn_r
))
10071 if (!bit (arm_insn_r
->arm_insn
,25))
10073 if (!bits (arm_insn_r
->arm_insn
, 4, 7))
10075 if ((0 == insn_op1
) || (2 == insn_op1
))
10078 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10079 arm_insn_r
->reg_rec_count
= 1;
10081 else if (1 == insn_op1
)
10083 /* CSPR is going to be changed. */
10084 record_buf
[0] = ARM_PS_REGNUM
;
10085 arm_insn_r
->reg_rec_count
= 1;
10087 else if (3 == insn_op1
)
10089 /* SPSR is going to be changed. */
10090 /* We need to get SPSR value, which is yet to be done. */
10094 else if (1 == bits (arm_insn_r
->arm_insn
, 4, 7))
10099 record_buf
[0] = ARM_PS_REGNUM
;
10100 arm_insn_r
->reg_rec_count
= 1;
10102 else if (3 == insn_op1
)
10105 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10106 arm_insn_r
->reg_rec_count
= 1;
10109 else if (3 == bits (arm_insn_r
->arm_insn
, 4, 7))
10112 record_buf
[0] = ARM_PS_REGNUM
;
10113 record_buf
[1] = ARM_LR_REGNUM
;
10114 arm_insn_r
->reg_rec_count
= 2;
10116 else if (5 == bits (arm_insn_r
->arm_insn
, 4, 7))
10118 /* QADD, QSUB, QDADD, QDSUB */
10119 record_buf
[0] = ARM_PS_REGNUM
;
10120 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10121 arm_insn_r
->reg_rec_count
= 2;
10123 else if (7 == bits (arm_insn_r
->arm_insn
, 4, 7))
10126 record_buf
[0] = ARM_PS_REGNUM
;
10127 record_buf
[1] = ARM_LR_REGNUM
;
10128 arm_insn_r
->reg_rec_count
= 2;
10130 /* Save SPSR also;how? */
10133 else if(8 == bits (arm_insn_r
->arm_insn
, 4, 7)
10134 || 10 == bits (arm_insn_r
->arm_insn
, 4, 7)
10135 || 12 == bits (arm_insn_r
->arm_insn
, 4, 7)
10136 || 14 == bits (arm_insn_r
->arm_insn
, 4, 7)
10139 if (0 == insn_op1
|| 1 == insn_op1
)
10141 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
10142 /* We dont do optimization for SMULW<y> where we
10144 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10145 record_buf
[1] = ARM_PS_REGNUM
;
10146 arm_insn_r
->reg_rec_count
= 2;
10148 else if (2 == insn_op1
)
10151 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10152 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
10153 arm_insn_r
->reg_rec_count
= 2;
10155 else if (3 == insn_op1
)
10158 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10159 arm_insn_r
->reg_rec_count
= 1;
10165 /* MSR : immediate form. */
10168 /* CSPR is going to be changed. */
10169 record_buf
[0] = ARM_PS_REGNUM
;
10170 arm_insn_r
->reg_rec_count
= 1;
10172 else if (3 == insn_op1
)
10174 /* SPSR is going to be changed. */
10175 /* we need to get SPSR value, which is yet to be done */
10181 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10182 opcode2
= bits (arm_insn_r
->arm_insn
, 20, 24);
10183 insn_op1
= bits (arm_insn_r
->arm_insn
, 5, 6);
10185 /* Handle load/store insn extension space. */
10187 if (!opcode1
&& bit (arm_insn_r
->arm_insn
, 7)
10188 && bit (arm_insn_r
->arm_insn
, 4) && 1 != arm_insn_r
->cond
10189 && !INSN_RECORDED(arm_insn_r
))
10194 /* These insn, changes register and memory as well. */
10195 /* SWP or SWPB insn. */
10196 /* Get memory address given by Rn. */
10197 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10198 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
10199 /* SWP insn ?, swaps word. */
10200 if (8 == arm_insn_r
->opcode
)
10202 record_buf_mem
[0] = 4;
10206 /* SWPB insn, swaps only byte. */
10207 record_buf_mem
[0] = 1;
10209 record_buf_mem
[1] = u_regval
;
10210 arm_insn_r
->mem_rec_count
= 1;
10211 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10212 arm_insn_r
->reg_rec_count
= 1;
10214 else if (1 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10217 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10220 else if (2 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10223 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10224 record_buf
[1] = record_buf
[0] + 1;
10225 arm_insn_r
->reg_rec_count
= 2;
10227 else if (3 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10230 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10233 else if (bit (arm_insn_r
->arm_insn
, 20) && insn_op1
<= 3)
10235 /* LDRH, LDRSB, LDRSH. */
10236 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10237 arm_insn_r
->reg_rec_count
= 1;
10242 opcode1
= bits (arm_insn_r
->arm_insn
, 23, 27);
10243 if (24 == opcode1
&& bit (arm_insn_r
->arm_insn
, 21)
10244 && !INSN_RECORDED(arm_insn_r
))
10247 /* Handle coprocessor insn extension space. */
10250 /* To be done for ARMv5 and later; as of now we return -1. */
10254 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10255 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10260 /* Handling opcode 000 insns. */
10263 arm_record_data_proc_misc_ld_str (insn_decode_record
*arm_insn_r
)
10265 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10266 uint32_t record_buf
[8], record_buf_mem
[8];
10267 ULONGEST u_regval
[2] = {0};
10269 uint32_t reg_src1
= 0, reg_dest
= 0;
10270 uint32_t opcode1
= 0;
10272 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10273 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10274 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
10276 /* Data processing insn /multiply insn. */
10277 if (9 == arm_insn_r
->decode
10278 && ((4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
10279 || (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)))
10281 /* Handle multiply instructions. */
10282 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
10283 if (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)
10285 /* Handle MLA and MUL. */
10286 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10287 record_buf
[1] = ARM_PS_REGNUM
;
10288 arm_insn_r
->reg_rec_count
= 2;
10290 else if (4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
10292 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
10293 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10294 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10295 record_buf
[2] = ARM_PS_REGNUM
;
10296 arm_insn_r
->reg_rec_count
= 3;
10299 else if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
10300 && (11 == arm_insn_r
->decode
|| 13 == arm_insn_r
->decode
))
10302 /* Handle misc load insns, as 20th bit (L = 1). */
10303 /* LDR insn has a capability to do branching, if
10304 MOV LR, PC is precceded by LDR insn having Rn as R15
10305 in that case, it emulates branch and link insn, and hence we
10306 need to save CSPR and PC as well. I am not sure this is right
10307 place; as opcode = 010 LDR insn make this happen, if R15 was
10309 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10310 if (15 != reg_dest
)
10312 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10313 arm_insn_r
->reg_rec_count
= 1;
10317 record_buf
[0] = reg_dest
;
10318 record_buf
[1] = ARM_PS_REGNUM
;
10319 arm_insn_r
->reg_rec_count
= 2;
10322 else if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
10323 && sbo_sbz (arm_insn_r
->arm_insn
, 5, 12, 0)
10324 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
10325 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21))
10327 /* Handle MSR insn. */
10328 if (9 == arm_insn_r
->opcode
)
10330 /* CSPR is going to be changed. */
10331 record_buf
[0] = ARM_PS_REGNUM
;
10332 arm_insn_r
->reg_rec_count
= 1;
10336 /* SPSR is going to be changed. */
10337 /* How to read SPSR value? */
10341 else if (9 == arm_insn_r
->decode
10342 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10343 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10345 /* Handling SWP, SWPB. */
10346 /* These insn, changes register and memory as well. */
10347 /* SWP or SWPB insn. */
10349 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10350 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10351 /* SWP insn ?, swaps word. */
10352 if (8 == arm_insn_r
->opcode
)
10354 record_buf_mem
[0] = 4;
10358 /* SWPB insn, swaps only byte. */
10359 record_buf_mem
[0] = 1;
10361 record_buf_mem
[1] = u_regval
[0];
10362 arm_insn_r
->mem_rec_count
= 1;
10363 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10364 arm_insn_r
->reg_rec_count
= 1;
10366 else if (3 == arm_insn_r
->decode
&& 0x12 == opcode1
10367 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10369 /* Handle BLX, branch and link/exchange. */
10370 if (9 == arm_insn_r
->opcode
)
10372 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
10373 and R14 stores the return address. */
10374 record_buf
[0] = ARM_PS_REGNUM
;
10375 record_buf
[1] = ARM_LR_REGNUM
;
10376 arm_insn_r
->reg_rec_count
= 2;
10379 else if (7 == arm_insn_r
->decode
&& 0x12 == opcode1
)
10381 /* Handle enhanced software breakpoint insn, BKPT. */
10382 /* CPSR is changed to be executed in ARM state, disabling normal
10383 interrupts, entering abort mode. */
10384 /* According to high vector configuration PC is set. */
10385 /* user hit breakpoint and type reverse, in
10386 that case, we need to go back with previous CPSR and
10387 Program Counter. */
10388 record_buf
[0] = ARM_PS_REGNUM
;
10389 record_buf
[1] = ARM_LR_REGNUM
;
10390 arm_insn_r
->reg_rec_count
= 2;
10392 /* Save SPSR also; how? */
10395 else if (11 == arm_insn_r
->decode
10396 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10398 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
10400 /* Handle str(x) insn */
10401 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10404 else if (1 == arm_insn_r
->decode
&& 0x12 == opcode1
10405 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10407 /* Handle BX, branch and link/exchange. */
10408 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
10409 record_buf
[0] = ARM_PS_REGNUM
;
10410 arm_insn_r
->reg_rec_count
= 1;
10412 else if (1 == arm_insn_r
->decode
&& 0x16 == opcode1
10413 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 4, 1)
10414 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1))
10416 /* Count leading zeros: CLZ. */
10417 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10418 arm_insn_r
->reg_rec_count
= 1;
10420 else if (!bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
10421 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10422 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1)
10423 && sbo_sbz (arm_insn_r
->arm_insn
, 1, 12, 0)
10426 /* Handle MRS insn. */
10427 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10428 arm_insn_r
->reg_rec_count
= 1;
10430 else if (arm_insn_r
->opcode
<= 15)
10432 /* Normal data processing insns. */
10433 /* Out of 11 shifter operands mode, all the insn modifies destination
10434 register, which is specified by 13-16 decode. */
10435 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10436 record_buf
[1] = ARM_PS_REGNUM
;
10437 arm_insn_r
->reg_rec_count
= 2;
10444 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10445 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10449 /* Handling opcode 001 insns. */
10452 arm_record_data_proc_imm (insn_decode_record
*arm_insn_r
)
10454 uint32_t record_buf
[8], record_buf_mem
[8];
10456 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10457 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10459 if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
10460 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21)
10461 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
10464 /* Handle MSR insn. */
10465 if (9 == arm_insn_r
->opcode
)
10467 /* CSPR is going to be changed. */
10468 record_buf
[0] = ARM_PS_REGNUM
;
10469 arm_insn_r
->reg_rec_count
= 1;
10473 /* SPSR is going to be changed. */
10476 else if (arm_insn_r
->opcode
<= 15)
10478 /* Normal data processing insns. */
10479 /* Out of 11 shifter operands mode, all the insn modifies destination
10480 register, which is specified by 13-16 decode. */
10481 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10482 record_buf
[1] = ARM_PS_REGNUM
;
10483 arm_insn_r
->reg_rec_count
= 2;
10490 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10491 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10496 arm_record_media (insn_decode_record
*arm_insn_r
)
10498 uint32_t record_buf
[8];
10500 switch (bits (arm_insn_r
->arm_insn
, 22, 24))
10503 /* Parallel addition and subtraction, signed */
10505 /* Parallel addition and subtraction, unsigned */
10508 /* Packing, unpacking, saturation and reversal */
10510 int rd
= bits (arm_insn_r
->arm_insn
, 12, 15);
10512 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10518 /* Signed multiplies */
10520 int rd
= bits (arm_insn_r
->arm_insn
, 16, 19);
10521 unsigned int op1
= bits (arm_insn_r
->arm_insn
, 20, 22);
10523 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10525 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10526 else if (op1
== 0x4)
10527 record_buf
[arm_insn_r
->reg_rec_count
++]
10528 = bits (arm_insn_r
->arm_insn
, 12, 15);
10534 if (bit (arm_insn_r
->arm_insn
, 21)
10535 && bits (arm_insn_r
->arm_insn
, 5, 6) == 0x2)
10538 record_buf
[arm_insn_r
->reg_rec_count
++]
10539 = bits (arm_insn_r
->arm_insn
, 12, 15);
10541 else if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x0
10542 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x0)
10544 /* USAD8 and USADA8 */
10545 record_buf
[arm_insn_r
->reg_rec_count
++]
10546 = bits (arm_insn_r
->arm_insn
, 16, 19);
10553 if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x3
10554 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x7)
10556 /* Permanently UNDEFINED */
10561 /* BFC, BFI and UBFX */
10562 record_buf
[arm_insn_r
->reg_rec_count
++]
10563 = bits (arm_insn_r
->arm_insn
, 12, 15);
10572 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10577 /* Handle ARM mode instructions with opcode 010. */
10580 arm_record_ld_st_imm_offset (insn_decode_record
*arm_insn_r
)
10582 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10584 uint32_t reg_base
, reg_dest
;
10585 uint32_t offset_12
, tgt_mem_addr
;
10586 uint32_t record_buf
[8], record_buf_mem
[8];
10587 unsigned char wback
;
10590 /* Calculate wback. */
10591 wback
= (bit (arm_insn_r
->arm_insn
, 24) == 0)
10592 || (bit (arm_insn_r
->arm_insn
, 21) == 1);
10594 arm_insn_r
->reg_rec_count
= 0;
10595 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
10597 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10599 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
10602 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10603 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_dest
;
10605 /* The LDR instruction is capable of doing branching. If MOV LR, PC
10606 preceeds a LDR instruction having R15 as reg_base, it
10607 emulates a branch and link instruction, and hence we need to save
10608 CPSR and PC as well. */
10609 if (ARM_PC_REGNUM
== reg_dest
)
10610 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10612 /* If wback is true, also save the base register, which is going to be
10615 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10619 /* STR (immediate), STRB (immediate), STRBT and STRT. */
10621 offset_12
= bits (arm_insn_r
->arm_insn
, 0, 11);
10622 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
10624 /* Handle bit U. */
10625 if (bit (arm_insn_r
->arm_insn
, 23))
10627 /* U == 1: Add the offset. */
10628 tgt_mem_addr
= (uint32_t) u_regval
+ offset_12
;
10632 /* U == 0: subtract the offset. */
10633 tgt_mem_addr
= (uint32_t) u_regval
- offset_12
;
10636 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
10638 if (bit (arm_insn_r
->arm_insn
, 22))
10640 /* STRB and STRBT: 1 byte. */
10641 record_buf_mem
[0] = 1;
10645 /* STR and STRT: 4 bytes. */
10646 record_buf_mem
[0] = 4;
10649 /* Handle bit P. */
10650 if (bit (arm_insn_r
->arm_insn
, 24))
10651 record_buf_mem
[1] = tgt_mem_addr
;
10653 record_buf_mem
[1] = (uint32_t) u_regval
;
10655 arm_insn_r
->mem_rec_count
= 1;
10657 /* If wback is true, also save the base register, which is going to be
10660 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10663 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10664 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10668 /* Handling opcode 011 insns. */
10671 arm_record_ld_st_reg_offset (insn_decode_record
*arm_insn_r
)
10673 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10675 uint32_t shift_imm
= 0;
10676 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
10677 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
10678 uint32_t record_buf
[8], record_buf_mem
[8];
10681 ULONGEST u_regval
[2];
10683 if (bit (arm_insn_r
->arm_insn
, 4))
10684 return arm_record_media (arm_insn_r
);
10686 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10687 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10689 /* Handle enhanced store insns and LDRD DSP insn,
10690 order begins according to addressing modes for store insns
10694 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10696 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10697 /* LDR insn has a capability to do branching, if
10698 MOV LR, PC is precedded by LDR insn having Rn as R15
10699 in that case, it emulates branch and link insn, and hence we
10700 need to save CSPR and PC as well. */
10701 if (15 != reg_dest
)
10703 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10704 arm_insn_r
->reg_rec_count
= 1;
10708 record_buf
[0] = reg_dest
;
10709 record_buf
[1] = ARM_PS_REGNUM
;
10710 arm_insn_r
->reg_rec_count
= 2;
10715 if (! bits (arm_insn_r
->arm_insn
, 4, 11))
10717 /* Store insn, register offset and register pre-indexed,
10718 register post-indexed. */
10720 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10722 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10723 regcache_raw_read_unsigned (reg_cache
, reg_src1
10725 regcache_raw_read_unsigned (reg_cache
, reg_src2
10727 if (15 == reg_src2
)
10729 /* If R15 was used as Rn, hence current PC+8. */
10730 /* Pre-indexed mode doesnt reach here ; illegal insn. */
10731 u_regval
[0] = u_regval
[0] + 8;
10733 /* Calculate target store address, Rn +/- Rm, register offset. */
10735 if (bit (arm_insn_r
->arm_insn
, 23))
10737 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10741 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10744 switch (arm_insn_r
->opcode
)
10758 record_buf_mem
[0] = 4;
10773 record_buf_mem
[0] = 1;
10777 gdb_assert_not_reached ("no decoding pattern found");
10780 record_buf_mem
[1] = tgt_mem_addr
;
10781 arm_insn_r
->mem_rec_count
= 1;
10783 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10784 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10785 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10786 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10787 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10788 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10791 /* Rn is going to be changed in pre-indexed mode and
10792 post-indexed mode as well. */
10793 record_buf
[0] = reg_src2
;
10794 arm_insn_r
->reg_rec_count
= 1;
10799 /* Store insn, scaled register offset; scaled pre-indexed. */
10800 offset_12
= bits (arm_insn_r
->arm_insn
, 5, 6);
10802 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10804 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10805 /* Get shift_imm. */
10806 shift_imm
= bits (arm_insn_r
->arm_insn
, 7, 11);
10807 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10808 regcache_raw_read_signed (reg_cache
, reg_src1
, &s_word
);
10809 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10810 /* Offset_12 used as shift. */
10814 /* Offset_12 used as index. */
10815 offset_12
= u_regval
[0] << shift_imm
;
10819 offset_12
= (!shift_imm
)?0:u_regval
[0] >> shift_imm
;
10825 if (bit (u_regval
[0], 31))
10827 offset_12
= 0xFFFFFFFF;
10836 /* This is arithmetic shift. */
10837 offset_12
= s_word
>> shift_imm
;
10844 regcache_raw_read_unsigned (reg_cache
, ARM_PS_REGNUM
,
10846 /* Get C flag value and shift it by 31. */
10847 offset_12
= (((bit (u_regval
[1], 29)) << 31) \
10848 | (u_regval
[0]) >> 1);
10852 offset_12
= (u_regval
[0] >> shift_imm
) \
10854 (sizeof(uint32_t) - shift_imm
));
10859 gdb_assert_not_reached ("no decoding pattern found");
10863 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10865 if (bit (arm_insn_r
->arm_insn
, 23))
10867 tgt_mem_addr
= u_regval
[1] + offset_12
;
10871 tgt_mem_addr
= u_regval
[1] - offset_12
;
10874 switch (arm_insn_r
->opcode
)
10888 record_buf_mem
[0] = 4;
10903 record_buf_mem
[0] = 1;
10907 gdb_assert_not_reached ("no decoding pattern found");
10910 record_buf_mem
[1] = tgt_mem_addr
;
10911 arm_insn_r
->mem_rec_count
= 1;
10913 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10914 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10915 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10916 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10917 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10918 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10921 /* Rn is going to be changed in register scaled pre-indexed
10922 mode,and scaled post indexed mode. */
10923 record_buf
[0] = reg_src2
;
10924 arm_insn_r
->reg_rec_count
= 1;
10929 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10930 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10934 /* Handle ARM mode instructions with opcode 100. */
10937 arm_record_ld_st_multiple (insn_decode_record
*arm_insn_r
)
10939 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10940 uint32_t register_count
= 0, register_bits
;
10941 uint32_t reg_base
, addr_mode
;
10942 uint32_t record_buf
[24], record_buf_mem
[48];
10946 /* Fetch the list of registers. */
10947 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
10948 arm_insn_r
->reg_rec_count
= 0;
10950 /* Fetch the base register that contains the address we are loading data
10952 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
10954 /* Calculate wback. */
10955 wback
= (bit (arm_insn_r
->arm_insn
, 21) == 1);
10957 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10959 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
10961 /* Find out which registers are going to be loaded from memory. */
10962 while (register_bits
)
10964 if (register_bits
& 0x00000001)
10965 record_buf
[arm_insn_r
->reg_rec_count
++] = register_count
;
10966 register_bits
= register_bits
>> 1;
10971 /* If wback is true, also save the base register, which is going to be
10974 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10976 /* Save the CPSR register. */
10977 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10981 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
10983 addr_mode
= bits (arm_insn_r
->arm_insn
, 23, 24);
10985 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
10987 /* Find out how many registers are going to be stored to memory. */
10988 while (register_bits
)
10990 if (register_bits
& 0x00000001)
10992 register_bits
= register_bits
>> 1;
10997 /* STMDA (STMED): Decrement after. */
10999 record_buf_mem
[1] = (uint32_t) u_regval
11000 - register_count
* INT_REGISTER_SIZE
+ 4;
11002 /* STM (STMIA, STMEA): Increment after. */
11004 record_buf_mem
[1] = (uint32_t) u_regval
;
11006 /* STMDB (STMFD): Decrement before. */
11008 record_buf_mem
[1] = (uint32_t) u_regval
11009 - register_count
* INT_REGISTER_SIZE
;
11011 /* STMIB (STMFA): Increment before. */
11013 record_buf_mem
[1] = (uint32_t) u_regval
+ INT_REGISTER_SIZE
;
11016 gdb_assert_not_reached ("no decoding pattern found");
11020 record_buf_mem
[0] = register_count
* INT_REGISTER_SIZE
;
11021 arm_insn_r
->mem_rec_count
= 1;
11023 /* If wback is true, also save the base register, which is going to be
11026 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11029 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11030 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11034 /* Handling opcode 101 insns. */
11037 arm_record_b_bl (insn_decode_record
*arm_insn_r
)
11039 uint32_t record_buf
[8];
11041 /* Handle B, BL, BLX(1) insns. */
11042 /* B simply branches so we do nothing here. */
11043 /* Note: BLX(1) doesnt fall here but instead it falls into
11044 extension space. */
11045 if (bit (arm_insn_r
->arm_insn
, 24))
11047 record_buf
[0] = ARM_LR_REGNUM
;
11048 arm_insn_r
->reg_rec_count
= 1;
11051 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11057 arm_record_unsupported_insn (insn_decode_record
*arm_insn_r
)
11059 printf_unfiltered (_("Process record does not support instruction "
11060 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11061 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11066 /* Record handler for vector data transfer instructions. */
11069 arm_record_vdata_transfer_insn (insn_decode_record
*arm_insn_r
)
11071 uint32_t bits_a
, bit_c
, bit_l
, reg_t
, reg_v
;
11072 uint32_t record_buf
[4];
11074 reg_t
= bits (arm_insn_r
->arm_insn
, 12, 15);
11075 reg_v
= bits (arm_insn_r
->arm_insn
, 21, 23);
11076 bits_a
= bits (arm_insn_r
->arm_insn
, 21, 23);
11077 bit_l
= bit (arm_insn_r
->arm_insn
, 20);
11078 bit_c
= bit (arm_insn_r
->arm_insn
, 8);
11080 /* Handle VMOV instruction. */
11081 if (bit_l
&& bit_c
)
11083 record_buf
[0] = reg_t
;
11084 arm_insn_r
->reg_rec_count
= 1;
11086 else if (bit_l
&& !bit_c
)
11088 /* Handle VMOV instruction. */
11089 if (bits_a
== 0x00)
11091 record_buf
[0] = reg_t
;
11092 arm_insn_r
->reg_rec_count
= 1;
11094 /* Handle VMRS instruction. */
11095 else if (bits_a
== 0x07)
11098 reg_t
= ARM_PS_REGNUM
;
11100 record_buf
[0] = reg_t
;
11101 arm_insn_r
->reg_rec_count
= 1;
11104 else if (!bit_l
&& !bit_c
)
11106 /* Handle VMOV instruction. */
11107 if (bits_a
== 0x00)
11109 record_buf
[0] = ARM_D0_REGNUM
+ reg_v
;
11111 arm_insn_r
->reg_rec_count
= 1;
11113 /* Handle VMSR instruction. */
11114 else if (bits_a
== 0x07)
11116 record_buf
[0] = ARM_FPSCR_REGNUM
;
11117 arm_insn_r
->reg_rec_count
= 1;
11120 else if (!bit_l
&& bit_c
)
11122 /* Handle VMOV instruction. */
11123 if (!(bits_a
& 0x04))
11125 record_buf
[0] = (reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4))
11127 arm_insn_r
->reg_rec_count
= 1;
11129 /* Handle VDUP instruction. */
11132 if (bit (arm_insn_r
->arm_insn
, 21))
11134 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11135 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11136 record_buf
[1] = reg_v
+ ARM_D0_REGNUM
+ 1;
11137 arm_insn_r
->reg_rec_count
= 2;
11141 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11142 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11143 arm_insn_r
->reg_rec_count
= 1;
11148 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11152 /* Record handler for extension register load/store instructions. */
11155 arm_record_exreg_ld_st_insn (insn_decode_record
*arm_insn_r
)
11157 uint32_t opcode
, single_reg
;
11158 uint8_t op_vldm_vstm
;
11159 uint32_t record_buf
[8], record_buf_mem
[128];
11160 ULONGEST u_regval
= 0;
11162 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11164 opcode
= bits (arm_insn_r
->arm_insn
, 20, 24);
11165 single_reg
= !bit (arm_insn_r
->arm_insn
, 8);
11166 op_vldm_vstm
= opcode
& 0x1b;
11168 /* Handle VMOV instructions. */
11169 if ((opcode
& 0x1e) == 0x04)
11171 if (bit (arm_insn_r
->arm_insn
, 20)) /* to_arm_registers bit 20? */
11173 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11174 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11175 arm_insn_r
->reg_rec_count
= 2;
11179 uint8_t reg_m
= bits (arm_insn_r
->arm_insn
, 0, 3);
11180 uint8_t bit_m
= bit (arm_insn_r
->arm_insn
, 5);
11184 /* The first S register number m is REG_M:M (M is bit 5),
11185 the corresponding D register number is REG_M:M / 2, which
11187 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_D0_REGNUM
+ reg_m
;
11188 /* The second S register number is REG_M:M + 1, the
11189 corresponding D register number is (REG_M:M + 1) / 2.
11190 IOW, if bit M is 1, the first and second S registers
11191 are mapped to different D registers, otherwise, they are
11192 in the same D register. */
11195 record_buf
[arm_insn_r
->reg_rec_count
++]
11196 = ARM_D0_REGNUM
+ reg_m
+ 1;
11201 record_buf
[0] = ((bit_m
<< 4) + reg_m
+ ARM_D0_REGNUM
);
11202 arm_insn_r
->reg_rec_count
= 1;
11206 /* Handle VSTM and VPUSH instructions. */
11207 else if (op_vldm_vstm
== 0x08 || op_vldm_vstm
== 0x0a
11208 || op_vldm_vstm
== 0x12)
11210 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
11211 uint32_t memory_index
= 0;
11213 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11214 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11215 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11216 imm_off32
= imm_off8
<< 2;
11217 memory_count
= imm_off8
;
11219 if (bit (arm_insn_r
->arm_insn
, 23))
11220 start_address
= u_regval
;
11222 start_address
= u_regval
- imm_off32
;
11224 if (bit (arm_insn_r
->arm_insn
, 21))
11226 record_buf
[0] = reg_rn
;
11227 arm_insn_r
->reg_rec_count
= 1;
11230 while (memory_count
> 0)
11234 record_buf_mem
[memory_index
] = 4;
11235 record_buf_mem
[memory_index
+ 1] = start_address
;
11236 start_address
= start_address
+ 4;
11237 memory_index
= memory_index
+ 2;
11241 record_buf_mem
[memory_index
] = 4;
11242 record_buf_mem
[memory_index
+ 1] = start_address
;
11243 record_buf_mem
[memory_index
+ 2] = 4;
11244 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11245 start_address
= start_address
+ 8;
11246 memory_index
= memory_index
+ 4;
11250 arm_insn_r
->mem_rec_count
= (memory_index
>> 1);
11252 /* Handle VLDM instructions. */
11253 else if (op_vldm_vstm
== 0x09 || op_vldm_vstm
== 0x0b
11254 || op_vldm_vstm
== 0x13)
11256 uint32_t reg_count
, reg_vd
;
11257 uint32_t reg_index
= 0;
11258 uint32_t bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11260 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11261 reg_count
= bits (arm_insn_r
->arm_insn
, 0, 7);
11263 /* REG_VD is the first D register number. If the instruction
11264 loads memory to S registers (SINGLE_REG is TRUE), the register
11265 number is (REG_VD << 1 | bit D), so the corresponding D
11266 register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */
11268 reg_vd
= reg_vd
| (bit_d
<< 4);
11270 if (bit (arm_insn_r
->arm_insn
, 21) /* write back */)
11271 record_buf
[reg_index
++] = bits (arm_insn_r
->arm_insn
, 16, 19);
11273 /* If the instruction loads memory to D register, REG_COUNT should
11274 be divided by 2, according to the ARM Architecture Reference
11275 Manual. If the instruction loads memory to S register, divide by
11276 2 as well because two S registers are mapped to D register. */
11277 reg_count
= reg_count
/ 2;
11278 if (single_reg
&& bit_d
)
11280 /* Increase the register count if S register list starts from
11281 an odd number (bit d is one). */
11285 while (reg_count
> 0)
11287 record_buf
[reg_index
++] = ARM_D0_REGNUM
+ reg_vd
+ reg_count
- 1;
11290 arm_insn_r
->reg_rec_count
= reg_index
;
11292 /* VSTR Vector store register. */
11293 else if ((opcode
& 0x13) == 0x10)
11295 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
;
11296 uint32_t memory_index
= 0;
11298 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11299 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11300 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11301 imm_off32
= imm_off8
<< 2;
11303 if (bit (arm_insn_r
->arm_insn
, 23))
11304 start_address
= u_regval
+ imm_off32
;
11306 start_address
= u_regval
- imm_off32
;
11310 record_buf_mem
[memory_index
] = 4;
11311 record_buf_mem
[memory_index
+ 1] = start_address
;
11312 arm_insn_r
->mem_rec_count
= 1;
11316 record_buf_mem
[memory_index
] = 4;
11317 record_buf_mem
[memory_index
+ 1] = start_address
;
11318 record_buf_mem
[memory_index
+ 2] = 4;
11319 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11320 arm_insn_r
->mem_rec_count
= 2;
11323 /* VLDR Vector load register. */
11324 else if ((opcode
& 0x13) == 0x11)
11326 uint32_t reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11330 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
11331 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
;
11335 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
11336 /* Record register D rather than pseudo register S. */
11337 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
/ 2;
11339 arm_insn_r
->reg_rec_count
= 1;
11342 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11343 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11347 /* Record handler for arm/thumb mode VFP data processing instructions. */
11350 arm_record_vfp_data_proc_insn (insn_decode_record
*arm_insn_r
)
11352 uint32_t opc1
, opc2
, opc3
, dp_op_sz
, bit_d
, reg_vd
;
11353 uint32_t record_buf
[4];
11354 enum insn_types
{INSN_T0
, INSN_T1
, INSN_T2
, INSN_T3
, INSN_INV
};
11355 enum insn_types curr_insn_type
= INSN_INV
;
11357 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11358 opc1
= bits (arm_insn_r
->arm_insn
, 20, 23);
11359 opc2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11360 opc3
= bits (arm_insn_r
->arm_insn
, 6, 7);
11361 dp_op_sz
= bit (arm_insn_r
->arm_insn
, 8);
11362 bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11363 opc1
= opc1
& 0x04;
11365 /* Handle VMLA, VMLS. */
11368 if (bit (arm_insn_r
->arm_insn
, 10))
11370 if (bit (arm_insn_r
->arm_insn
, 6))
11371 curr_insn_type
= INSN_T0
;
11373 curr_insn_type
= INSN_T1
;
11378 curr_insn_type
= INSN_T1
;
11380 curr_insn_type
= INSN_T2
;
11383 /* Handle VNMLA, VNMLS, VNMUL. */
11384 else if (opc1
== 0x01)
11387 curr_insn_type
= INSN_T1
;
11389 curr_insn_type
= INSN_T2
;
11392 else if (opc1
== 0x02 && !(opc3
& 0x01))
11394 if (bit (arm_insn_r
->arm_insn
, 10))
11396 if (bit (arm_insn_r
->arm_insn
, 6))
11397 curr_insn_type
= INSN_T0
;
11399 curr_insn_type
= INSN_T1
;
11404 curr_insn_type
= INSN_T1
;
11406 curr_insn_type
= INSN_T2
;
11409 /* Handle VADD, VSUB. */
11410 else if (opc1
== 0x03)
11412 if (!bit (arm_insn_r
->arm_insn
, 9))
11414 if (bit (arm_insn_r
->arm_insn
, 6))
11415 curr_insn_type
= INSN_T0
;
11417 curr_insn_type
= INSN_T1
;
11422 curr_insn_type
= INSN_T1
;
11424 curr_insn_type
= INSN_T2
;
11428 else if (opc1
== 0x0b)
11431 curr_insn_type
= INSN_T1
;
11433 curr_insn_type
= INSN_T2
;
11435 /* Handle all other vfp data processing instructions. */
11436 else if (opc1
== 0x0b)
11439 if (!(opc3
& 0x01) || (opc2
== 0x00 && opc3
== 0x01))
11441 if (bit (arm_insn_r
->arm_insn
, 4))
11443 if (bit (arm_insn_r
->arm_insn
, 6))
11444 curr_insn_type
= INSN_T0
;
11446 curr_insn_type
= INSN_T1
;
11451 curr_insn_type
= INSN_T1
;
11453 curr_insn_type
= INSN_T2
;
11456 /* Handle VNEG and VABS. */
11457 else if ((opc2
== 0x01 && opc3
== 0x01)
11458 || (opc2
== 0x00 && opc3
== 0x03))
11460 if (!bit (arm_insn_r
->arm_insn
, 11))
11462 if (bit (arm_insn_r
->arm_insn
, 6))
11463 curr_insn_type
= INSN_T0
;
11465 curr_insn_type
= INSN_T1
;
11470 curr_insn_type
= INSN_T1
;
11472 curr_insn_type
= INSN_T2
;
11475 /* Handle VSQRT. */
11476 else if (opc2
== 0x01 && opc3
== 0x03)
11479 curr_insn_type
= INSN_T1
;
11481 curr_insn_type
= INSN_T2
;
11484 else if (opc2
== 0x07 && opc3
== 0x03)
11487 curr_insn_type
= INSN_T1
;
11489 curr_insn_type
= INSN_T2
;
11491 else if (opc3
& 0x01)
11494 if ((opc2
== 0x08) || (opc2
& 0x0e) == 0x0c)
11496 if (!bit (arm_insn_r
->arm_insn
, 18))
11497 curr_insn_type
= INSN_T2
;
11501 curr_insn_type
= INSN_T1
;
11503 curr_insn_type
= INSN_T2
;
11507 else if ((opc2
& 0x0e) == 0x0a || (opc2
& 0x0e) == 0x0e)
11510 curr_insn_type
= INSN_T1
;
11512 curr_insn_type
= INSN_T2
;
11514 /* Handle VCVTB, VCVTT. */
11515 else if ((opc2
& 0x0e) == 0x02)
11516 curr_insn_type
= INSN_T2
;
11517 /* Handle VCMP, VCMPE. */
11518 else if ((opc2
& 0x0e) == 0x04)
11519 curr_insn_type
= INSN_T3
;
11523 switch (curr_insn_type
)
11526 reg_vd
= reg_vd
| (bit_d
<< 4);
11527 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11528 record_buf
[1] = reg_vd
+ ARM_D0_REGNUM
+ 1;
11529 arm_insn_r
->reg_rec_count
= 2;
11533 reg_vd
= reg_vd
| (bit_d
<< 4);
11534 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11535 arm_insn_r
->reg_rec_count
= 1;
11539 reg_vd
= (reg_vd
<< 1) | bit_d
;
11540 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11541 arm_insn_r
->reg_rec_count
= 1;
11545 record_buf
[0] = ARM_FPSCR_REGNUM
;
11546 arm_insn_r
->reg_rec_count
= 1;
11550 gdb_assert_not_reached ("no decoding pattern found");
11554 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11558 /* Handling opcode 110 insns. */
11561 arm_record_asimd_vfp_coproc (insn_decode_record
*arm_insn_r
)
11563 uint32_t op1
, op1_ebit
, coproc
;
11565 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11566 op1
= bits (arm_insn_r
->arm_insn
, 20, 25);
11567 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11569 if ((coproc
& 0x0e) == 0x0a)
11571 /* Handle extension register ld/st instructions. */
11573 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11575 /* 64-bit transfers between arm core and extension registers. */
11576 if ((op1
& 0x3e) == 0x04)
11577 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11581 /* Handle coprocessor ld/st instructions. */
11586 return arm_record_unsupported_insn (arm_insn_r
);
11589 return arm_record_unsupported_insn (arm_insn_r
);
11592 /* Move to coprocessor from two arm core registers. */
11594 return arm_record_unsupported_insn (arm_insn_r
);
11596 /* Move to two arm core registers from coprocessor. */
11601 reg_t
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11602 reg_t
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11603 arm_insn_r
->reg_rec_count
= 2;
11605 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, reg_t
);
11609 return arm_record_unsupported_insn (arm_insn_r
);
11612 /* Handling opcode 111 insns. */
11615 arm_record_coproc_data_proc (insn_decode_record
*arm_insn_r
)
11617 uint32_t op
, op1_sbit
, op1_ebit
, coproc
;
11618 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arm_insn_r
->gdbarch
);
11619 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11621 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 24, 27);
11622 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11623 op1_sbit
= bit (arm_insn_r
->arm_insn
, 24);
11624 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11625 op
= bit (arm_insn_r
->arm_insn
, 4);
11627 /* Handle arm SWI/SVC system call instructions. */
11630 if (tdep
->arm_syscall_record
!= NULL
)
11632 ULONGEST svc_operand
, svc_number
;
11634 svc_operand
= (0x00ffffff & arm_insn_r
->arm_insn
);
11636 if (svc_operand
) /* OABI. */
11637 svc_number
= svc_operand
- 0x900000;
11639 regcache_raw_read_unsigned (reg_cache
, 7, &svc_number
);
11641 return tdep
->arm_syscall_record (reg_cache
, svc_number
);
11645 printf_unfiltered (_("no syscall record support\n"));
11650 if ((coproc
& 0x0e) == 0x0a)
11652 /* VFP data-processing instructions. */
11653 if (!op1_sbit
&& !op
)
11654 return arm_record_vfp_data_proc_insn (arm_insn_r
);
11656 /* Advanced SIMD, VFP instructions. */
11657 if (!op1_sbit
&& op
)
11658 return arm_record_vdata_transfer_insn (arm_insn_r
);
11662 /* Coprocessor data operations. */
11663 if (!op1_sbit
&& !op
)
11664 return arm_record_unsupported_insn (arm_insn_r
);
11666 /* Move to Coprocessor from ARM core register. */
11667 if (!op1_sbit
&& !op1_ebit
&& op
)
11668 return arm_record_unsupported_insn (arm_insn_r
);
11670 /* Move to arm core register from coprocessor. */
11671 if (!op1_sbit
&& op1_ebit
&& op
)
11673 uint32_t record_buf
[1];
11675 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11676 if (record_buf
[0] == 15)
11677 record_buf
[0] = ARM_PS_REGNUM
;
11679 arm_insn_r
->reg_rec_count
= 1;
11680 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
,
11686 return arm_record_unsupported_insn (arm_insn_r
);
11689 /* Handling opcode 000 insns. */
11692 thumb_record_shift_add_sub (insn_decode_record
*thumb_insn_r
)
11694 uint32_t record_buf
[8];
11695 uint32_t reg_src1
= 0;
11697 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11699 record_buf
[0] = ARM_PS_REGNUM
;
11700 record_buf
[1] = reg_src1
;
11701 thumb_insn_r
->reg_rec_count
= 2;
11703 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11709 /* Handling opcode 001 insns. */
11712 thumb_record_add_sub_cmp_mov (insn_decode_record
*thumb_insn_r
)
11714 uint32_t record_buf
[8];
11715 uint32_t reg_src1
= 0;
11717 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11719 record_buf
[0] = ARM_PS_REGNUM
;
11720 record_buf
[1] = reg_src1
;
11721 thumb_insn_r
->reg_rec_count
= 2;
11723 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11728 /* Handling opcode 010 insns. */
11731 thumb_record_ld_st_reg_offset (insn_decode_record
*thumb_insn_r
)
11733 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11734 uint32_t record_buf
[8], record_buf_mem
[8];
11736 uint32_t reg_src1
= 0, reg_src2
= 0;
11737 uint32_t opcode1
= 0, opcode2
= 0, opcode3
= 0;
11739 ULONGEST u_regval
[2] = {0};
11741 opcode1
= bits (thumb_insn_r
->arm_insn
, 10, 12);
11743 if (bit (thumb_insn_r
->arm_insn
, 12))
11745 /* Handle load/store register offset. */
11746 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 10);
11747 if (opcode2
>= 12 && opcode2
<= 15)
11749 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
11750 reg_src1
= bits (thumb_insn_r
->arm_insn
,0, 2);
11751 record_buf
[0] = reg_src1
;
11752 thumb_insn_r
->reg_rec_count
= 1;
11754 else if (opcode2
>= 8 && opcode2
<= 10)
11756 /* STR(2), STRB(2), STRH(2) . */
11757 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11758 reg_src2
= bits (thumb_insn_r
->arm_insn
, 6, 8);
11759 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11760 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11762 record_buf_mem
[0] = 4; /* STR (2). */
11763 else if (10 == opcode2
)
11764 record_buf_mem
[0] = 1; /* STRB (2). */
11765 else if (9 == opcode2
)
11766 record_buf_mem
[0] = 2; /* STRH (2). */
11767 record_buf_mem
[1] = u_regval
[0] + u_regval
[1];
11768 thumb_insn_r
->mem_rec_count
= 1;
11771 else if (bit (thumb_insn_r
->arm_insn
, 11))
11773 /* Handle load from literal pool. */
11775 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11776 record_buf
[0] = reg_src1
;
11777 thumb_insn_r
->reg_rec_count
= 1;
11781 opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 9);
11782 opcode3
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11783 if ((3 == opcode2
) && (!opcode3
))
11785 /* Branch with exchange. */
11786 record_buf
[0] = ARM_PS_REGNUM
;
11787 thumb_insn_r
->reg_rec_count
= 1;
11791 /* Format 8; special data processing insns. */
11792 record_buf
[0] = ARM_PS_REGNUM
;
11793 record_buf
[1] = (bit (thumb_insn_r
->arm_insn
, 7) << 3
11794 | bits (thumb_insn_r
->arm_insn
, 0, 2));
11795 thumb_insn_r
->reg_rec_count
= 2;
11800 /* Format 5; data processing insns. */
11801 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11802 if (bit (thumb_insn_r
->arm_insn
, 7))
11804 reg_src1
= reg_src1
+ 8;
11806 record_buf
[0] = ARM_PS_REGNUM
;
11807 record_buf
[1] = reg_src1
;
11808 thumb_insn_r
->reg_rec_count
= 2;
11811 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11812 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11818 /* Handling opcode 001 insns. */
11821 thumb_record_ld_st_imm_offset (insn_decode_record
*thumb_insn_r
)
11823 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11824 uint32_t record_buf
[8], record_buf_mem
[8];
11826 uint32_t reg_src1
= 0;
11827 uint32_t opcode
= 0, immed_5
= 0;
11829 ULONGEST u_regval
= 0;
11831 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11836 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11837 record_buf
[0] = reg_src1
;
11838 thumb_insn_r
->reg_rec_count
= 1;
11843 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11844 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11845 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11846 record_buf_mem
[0] = 4;
11847 record_buf_mem
[1] = u_regval
+ (immed_5
* 4);
11848 thumb_insn_r
->mem_rec_count
= 1;
11851 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11852 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11858 /* Handling opcode 100 insns. */
11861 thumb_record_ld_st_stack (insn_decode_record
*thumb_insn_r
)
11863 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11864 uint32_t record_buf
[8], record_buf_mem
[8];
11866 uint32_t reg_src1
= 0;
11867 uint32_t opcode
= 0, immed_8
= 0, immed_5
= 0;
11869 ULONGEST u_regval
= 0;
11871 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11876 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11877 record_buf
[0] = reg_src1
;
11878 thumb_insn_r
->reg_rec_count
= 1;
11880 else if (1 == opcode
)
11883 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11884 record_buf
[0] = reg_src1
;
11885 thumb_insn_r
->reg_rec_count
= 1;
11887 else if (2 == opcode
)
11890 immed_8
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11891 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
11892 record_buf_mem
[0] = 4;
11893 record_buf_mem
[1] = u_regval
+ (immed_8
* 4);
11894 thumb_insn_r
->mem_rec_count
= 1;
11896 else if (0 == opcode
)
11899 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11900 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11901 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11902 record_buf_mem
[0] = 2;
11903 record_buf_mem
[1] = u_regval
+ (immed_5
* 2);
11904 thumb_insn_r
->mem_rec_count
= 1;
11907 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11908 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11914 /* Handling opcode 101 insns. */
11917 thumb_record_misc (insn_decode_record
*thumb_insn_r
)
11919 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11921 uint32_t opcode
= 0, opcode1
= 0, opcode2
= 0;
11922 uint32_t register_bits
= 0, register_count
= 0;
11923 uint32_t index
= 0, start_address
= 0;
11924 uint32_t record_buf
[24], record_buf_mem
[48];
11927 ULONGEST u_regval
= 0;
11929 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11930 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
11931 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 12);
11936 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11937 while (register_bits
)
11939 if (register_bits
& 0x00000001)
11940 record_buf
[index
++] = register_count
;
11941 register_bits
= register_bits
>> 1;
11944 record_buf
[index
++] = ARM_PS_REGNUM
;
11945 record_buf
[index
++] = ARM_SP_REGNUM
;
11946 thumb_insn_r
->reg_rec_count
= index
;
11948 else if (10 == opcode2
)
11951 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11952 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
11953 while (register_bits
)
11955 if (register_bits
& 0x00000001)
11957 register_bits
= register_bits
>> 1;
11959 start_address
= u_regval
- \
11960 (4 * (bit (thumb_insn_r
->arm_insn
, 8) + register_count
));
11961 thumb_insn_r
->mem_rec_count
= register_count
;
11962 while (register_count
)
11964 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11965 record_buf_mem
[(register_count
* 2) - 2] = 4;
11966 start_address
= start_address
+ 4;
11969 record_buf
[0] = ARM_SP_REGNUM
;
11970 thumb_insn_r
->reg_rec_count
= 1;
11972 else if (0x1E == opcode1
)
11975 /* Handle enhanced software breakpoint insn, BKPT. */
11976 /* CPSR is changed to be executed in ARM state, disabling normal
11977 interrupts, entering abort mode. */
11978 /* According to high vector configuration PC is set. */
11979 /* User hits breakpoint and type reverse, in that case, we need to go back with
11980 previous CPSR and Program Counter. */
11981 record_buf
[0] = ARM_PS_REGNUM
;
11982 record_buf
[1] = ARM_LR_REGNUM
;
11983 thumb_insn_r
->reg_rec_count
= 2;
11984 /* We need to save SPSR value, which is not yet done. */
11985 printf_unfiltered (_("Process record does not support instruction "
11986 "0x%0x at address %s.\n"),
11987 thumb_insn_r
->arm_insn
,
11988 paddress (thumb_insn_r
->gdbarch
,
11989 thumb_insn_r
->this_addr
));
11992 else if ((0 == opcode
) || (1 == opcode
))
11994 /* ADD(5), ADD(6). */
11995 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11996 record_buf
[0] = reg_src1
;
11997 thumb_insn_r
->reg_rec_count
= 1;
11999 else if (2 == opcode
)
12001 /* ADD(7), SUB(4). */
12002 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12003 record_buf
[0] = ARM_SP_REGNUM
;
12004 thumb_insn_r
->reg_rec_count
= 1;
12007 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12008 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12014 /* Handling opcode 110 insns. */
12017 thumb_record_ldm_stm_swi (insn_decode_record
*thumb_insn_r
)
12019 struct gdbarch_tdep
*tdep
= gdbarch_tdep (thumb_insn_r
->gdbarch
);
12020 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12022 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
12023 uint32_t reg_src1
= 0;
12024 uint32_t opcode1
= 0, opcode2
= 0, register_bits
= 0, register_count
= 0;
12025 uint32_t index
= 0, start_address
= 0;
12026 uint32_t record_buf
[24], record_buf_mem
[48];
12028 ULONGEST u_regval
= 0;
12030 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12031 opcode2
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12037 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12039 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12040 while (register_bits
)
12042 if (register_bits
& 0x00000001)
12043 record_buf
[index
++] = register_count
;
12044 register_bits
= register_bits
>> 1;
12047 record_buf
[index
++] = reg_src1
;
12048 thumb_insn_r
->reg_rec_count
= index
;
12050 else if (0 == opcode2
)
12052 /* It handles both STMIA. */
12053 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12055 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12056 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12057 while (register_bits
)
12059 if (register_bits
& 0x00000001)
12061 register_bits
= register_bits
>> 1;
12063 start_address
= u_regval
;
12064 thumb_insn_r
->mem_rec_count
= register_count
;
12065 while (register_count
)
12067 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12068 record_buf_mem
[(register_count
* 2) - 2] = 4;
12069 start_address
= start_address
+ 4;
12073 else if (0x1F == opcode1
)
12075 /* Handle arm syscall insn. */
12076 if (tdep
->arm_syscall_record
!= NULL
)
12078 regcache_raw_read_unsigned (reg_cache
, 7, &u_regval
);
12079 ret
= tdep
->arm_syscall_record (reg_cache
, u_regval
);
12083 printf_unfiltered (_("no syscall record support\n"));
12088 /* B (1), conditional branch is automatically taken care in process_record,
12089 as PC is saved there. */
12091 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12092 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12098 /* Handling opcode 111 insns. */
12101 thumb_record_branch (insn_decode_record
*thumb_insn_r
)
12103 uint32_t record_buf
[8];
12104 uint32_t bits_h
= 0;
12106 bits_h
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12108 if (2 == bits_h
|| 3 == bits_h
)
12111 record_buf
[0] = ARM_LR_REGNUM
;
12112 thumb_insn_r
->reg_rec_count
= 1;
12114 else if (1 == bits_h
)
12117 record_buf
[0] = ARM_PS_REGNUM
;
12118 record_buf
[1] = ARM_LR_REGNUM
;
12119 thumb_insn_r
->reg_rec_count
= 2;
12122 /* B(2) is automatically taken care in process_record, as PC is
12125 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12130 /* Handler for thumb2 load/store multiple instructions. */
12133 thumb2_record_ld_st_multiple (insn_decode_record
*thumb2_insn_r
)
12135 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12137 uint32_t reg_rn
, op
;
12138 uint32_t register_bits
= 0, register_count
= 0;
12139 uint32_t index
= 0, start_address
= 0;
12140 uint32_t record_buf
[24], record_buf_mem
[48];
12142 ULONGEST u_regval
= 0;
12144 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12145 op
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12147 if (0 == op
|| 3 == op
)
12149 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12151 /* Handle RFE instruction. */
12152 record_buf
[0] = ARM_PS_REGNUM
;
12153 thumb2_insn_r
->reg_rec_count
= 1;
12157 /* Handle SRS instruction after reading banked SP. */
12158 return arm_record_unsupported_insn (thumb2_insn_r
);
12161 else if (1 == op
|| 2 == op
)
12163 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12165 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
12166 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12167 while (register_bits
)
12169 if (register_bits
& 0x00000001)
12170 record_buf
[index
++] = register_count
;
12173 register_bits
= register_bits
>> 1;
12175 record_buf
[index
++] = reg_rn
;
12176 record_buf
[index
++] = ARM_PS_REGNUM
;
12177 thumb2_insn_r
->reg_rec_count
= index
;
12181 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
12182 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12183 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12184 while (register_bits
)
12186 if (register_bits
& 0x00000001)
12189 register_bits
= register_bits
>> 1;
12194 /* Start address calculation for LDMDB/LDMEA. */
12195 start_address
= u_regval
;
12199 /* Start address calculation for LDMDB/LDMEA. */
12200 start_address
= u_regval
- register_count
* 4;
12203 thumb2_insn_r
->mem_rec_count
= register_count
;
12204 while (register_count
)
12206 record_buf_mem
[register_count
* 2 - 1] = start_address
;
12207 record_buf_mem
[register_count
* 2 - 2] = 4;
12208 start_address
= start_address
+ 4;
12211 record_buf
[0] = reg_rn
;
12212 record_buf
[1] = ARM_PS_REGNUM
;
12213 thumb2_insn_r
->reg_rec_count
= 2;
12217 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12219 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12221 return ARM_RECORD_SUCCESS
;
12224 /* Handler for thumb2 load/store (dual/exclusive) and table branch
12228 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record
*thumb2_insn_r
)
12230 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12232 uint32_t reg_rd
, reg_rn
, offset_imm
;
12233 uint32_t reg_dest1
, reg_dest2
;
12234 uint32_t address
, offset_addr
;
12235 uint32_t record_buf
[8], record_buf_mem
[8];
12236 uint32_t op1
, op2
, op3
;
12238 ULONGEST u_regval
[2];
12240 op1
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12241 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 21);
12242 op3
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12244 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12246 if(!(1 == op1
&& 1 == op2
&& (0 == op3
|| 1 == op3
)))
12248 reg_dest1
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12249 record_buf
[0] = reg_dest1
;
12250 record_buf
[1] = ARM_PS_REGNUM
;
12251 thumb2_insn_r
->reg_rec_count
= 2;
12254 if (3 == op2
|| (op1
& 2) || (1 == op1
&& 1 == op2
&& 7 == op3
))
12256 reg_dest2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12257 record_buf
[2] = reg_dest2
;
12258 thumb2_insn_r
->reg_rec_count
= 3;
12263 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12264 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12266 if (0 == op1
&& 0 == op2
)
12268 /* Handle STREX. */
12269 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12270 address
= u_regval
[0] + (offset_imm
* 4);
12271 record_buf_mem
[0] = 4;
12272 record_buf_mem
[1] = address
;
12273 thumb2_insn_r
->mem_rec_count
= 1;
12274 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12275 record_buf
[0] = reg_rd
;
12276 thumb2_insn_r
->reg_rec_count
= 1;
12278 else if (1 == op1
&& 0 == op2
)
12280 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12281 record_buf
[0] = reg_rd
;
12282 thumb2_insn_r
->reg_rec_count
= 1;
12283 address
= u_regval
[0];
12284 record_buf_mem
[1] = address
;
12288 /* Handle STREXB. */
12289 record_buf_mem
[0] = 1;
12290 thumb2_insn_r
->mem_rec_count
= 1;
12294 /* Handle STREXH. */
12295 record_buf_mem
[0] = 2 ;
12296 thumb2_insn_r
->mem_rec_count
= 1;
12300 /* Handle STREXD. */
12301 address
= u_regval
[0];
12302 record_buf_mem
[0] = 4;
12303 record_buf_mem
[2] = 4;
12304 record_buf_mem
[3] = address
+ 4;
12305 thumb2_insn_r
->mem_rec_count
= 2;
12310 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12312 if (bit (thumb2_insn_r
->arm_insn
, 24))
12314 if (bit (thumb2_insn_r
->arm_insn
, 23))
12315 offset_addr
= u_regval
[0] + (offset_imm
* 4);
12317 offset_addr
= u_regval
[0] - (offset_imm
* 4);
12319 address
= offset_addr
;
12322 address
= u_regval
[0];
12324 record_buf_mem
[0] = 4;
12325 record_buf_mem
[1] = address
;
12326 record_buf_mem
[2] = 4;
12327 record_buf_mem
[3] = address
+ 4;
12328 thumb2_insn_r
->mem_rec_count
= 2;
12329 record_buf
[0] = reg_rn
;
12330 thumb2_insn_r
->reg_rec_count
= 1;
12334 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12336 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12338 return ARM_RECORD_SUCCESS
;
12341 /* Handler for thumb2 data processing (shift register and modified immediate)
12345 thumb2_record_data_proc_sreg_mimm (insn_decode_record
*thumb2_insn_r
)
12347 uint32_t reg_rd
, op
;
12348 uint32_t record_buf
[8];
12350 op
= bits (thumb2_insn_r
->arm_insn
, 21, 24);
12351 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12353 if ((0 == op
|| 4 == op
|| 8 == op
|| 13 == op
) && 15 == reg_rd
)
12355 record_buf
[0] = ARM_PS_REGNUM
;
12356 thumb2_insn_r
->reg_rec_count
= 1;
12360 record_buf
[0] = reg_rd
;
12361 record_buf
[1] = ARM_PS_REGNUM
;
12362 thumb2_insn_r
->reg_rec_count
= 2;
12365 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12367 return ARM_RECORD_SUCCESS
;
12370 /* Generic handler for thumb2 instructions which effect destination and PS
12374 thumb2_record_ps_dest_generic (insn_decode_record
*thumb2_insn_r
)
12377 uint32_t record_buf
[8];
12379 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12381 record_buf
[0] = reg_rd
;
12382 record_buf
[1] = ARM_PS_REGNUM
;
12383 thumb2_insn_r
->reg_rec_count
= 2;
12385 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12387 return ARM_RECORD_SUCCESS
;
12390 /* Handler for thumb2 branch and miscellaneous control instructions. */
12393 thumb2_record_branch_misc_cntrl (insn_decode_record
*thumb2_insn_r
)
12395 uint32_t op
, op1
, op2
;
12396 uint32_t record_buf
[8];
12398 op
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12399 op1
= bits (thumb2_insn_r
->arm_insn
, 12, 14);
12400 op2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12402 /* Handle MSR insn. */
12403 if (!(op1
& 0x2) && 0x38 == op
)
12407 /* CPSR is going to be changed. */
12408 record_buf
[0] = ARM_PS_REGNUM
;
12409 thumb2_insn_r
->reg_rec_count
= 1;
12413 arm_record_unsupported_insn(thumb2_insn_r
);
12417 else if (4 == (op1
& 0x5) || 5 == (op1
& 0x5))
12420 record_buf
[0] = ARM_PS_REGNUM
;
12421 record_buf
[1] = ARM_LR_REGNUM
;
12422 thumb2_insn_r
->reg_rec_count
= 2;
12425 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12427 return ARM_RECORD_SUCCESS
;
12430 /* Handler for thumb2 store single data item instructions. */
12433 thumb2_record_str_single_data (insn_decode_record
*thumb2_insn_r
)
12435 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12437 uint32_t reg_rn
, reg_rm
, offset_imm
, shift_imm
;
12438 uint32_t address
, offset_addr
;
12439 uint32_t record_buf
[8], record_buf_mem
[8];
12442 ULONGEST u_regval
[2];
12444 op1
= bits (thumb2_insn_r
->arm_insn
, 21, 23);
12445 op2
= bits (thumb2_insn_r
->arm_insn
, 6, 11);
12446 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12447 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12449 if (bit (thumb2_insn_r
->arm_insn
, 23))
12452 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 11);
12453 offset_addr
= u_regval
[0] + offset_imm
;
12454 address
= offset_addr
;
12459 if ((0 == op1
|| 1 == op1
|| 2 == op1
) && !(op2
& 0x20))
12461 /* Handle STRB (register). */
12462 reg_rm
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12463 regcache_raw_read_unsigned (reg_cache
, reg_rm
, &u_regval
[1]);
12464 shift_imm
= bits (thumb2_insn_r
->arm_insn
, 4, 5);
12465 offset_addr
= u_regval
[1] << shift_imm
;
12466 address
= u_regval
[0] + offset_addr
;
12470 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12471 if (bit (thumb2_insn_r
->arm_insn
, 10))
12473 if (bit (thumb2_insn_r
->arm_insn
, 9))
12474 offset_addr
= u_regval
[0] + offset_imm
;
12476 offset_addr
= u_regval
[0] - offset_imm
;
12478 address
= offset_addr
;
12481 address
= u_regval
[0];
12487 /* Store byte instructions. */
12490 record_buf_mem
[0] = 1;
12492 /* Store half word instructions. */
12495 record_buf_mem
[0] = 2;
12497 /* Store word instructions. */
12500 record_buf_mem
[0] = 4;
12504 gdb_assert_not_reached ("no decoding pattern found");
12508 record_buf_mem
[1] = address
;
12509 thumb2_insn_r
->mem_rec_count
= 1;
12510 record_buf
[0] = reg_rn
;
12511 thumb2_insn_r
->reg_rec_count
= 1;
12513 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12515 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12517 return ARM_RECORD_SUCCESS
;
12520 /* Handler for thumb2 load memory hints instructions. */
12523 thumb2_record_ld_mem_hints (insn_decode_record
*thumb2_insn_r
)
12525 uint32_t record_buf
[8];
12526 uint32_t reg_rt
, reg_rn
;
12528 reg_rt
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12529 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12531 if (ARM_PC_REGNUM
!= reg_rt
)
12533 record_buf
[0] = reg_rt
;
12534 record_buf
[1] = reg_rn
;
12535 record_buf
[2] = ARM_PS_REGNUM
;
12536 thumb2_insn_r
->reg_rec_count
= 3;
12538 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12540 return ARM_RECORD_SUCCESS
;
12543 return ARM_RECORD_FAILURE
;
12546 /* Handler for thumb2 load word instructions. */
12549 thumb2_record_ld_word (insn_decode_record
*thumb2_insn_r
)
12551 uint32_t record_buf
[8];
12553 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12554 record_buf
[1] = ARM_PS_REGNUM
;
12555 thumb2_insn_r
->reg_rec_count
= 2;
12557 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12559 return ARM_RECORD_SUCCESS
;
12562 /* Handler for thumb2 long multiply, long multiply accumulate, and
12563 divide instructions. */
12566 thumb2_record_lmul_lmla_div (insn_decode_record
*thumb2_insn_r
)
12568 uint32_t opcode1
= 0, opcode2
= 0;
12569 uint32_t record_buf
[8];
12571 opcode1
= bits (thumb2_insn_r
->arm_insn
, 20, 22);
12572 opcode2
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12574 if (0 == opcode1
|| 2 == opcode1
|| (opcode1
>= 4 && opcode1
<= 6))
12576 /* Handle SMULL, UMULL, SMULAL. */
12577 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
12578 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12579 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12580 record_buf
[2] = ARM_PS_REGNUM
;
12581 thumb2_insn_r
->reg_rec_count
= 3;
12583 else if (1 == opcode1
|| 3 == opcode2
)
12585 /* Handle SDIV and UDIV. */
12586 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12587 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12588 record_buf
[2] = ARM_PS_REGNUM
;
12589 thumb2_insn_r
->reg_rec_count
= 3;
12592 return ARM_RECORD_FAILURE
;
12594 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12596 return ARM_RECORD_SUCCESS
;
12599 /* Record handler for thumb32 coprocessor instructions. */
12602 thumb2_record_coproc_insn (insn_decode_record
*thumb2_insn_r
)
12604 if (bit (thumb2_insn_r
->arm_insn
, 25))
12605 return arm_record_coproc_data_proc (thumb2_insn_r
);
12607 return arm_record_asimd_vfp_coproc (thumb2_insn_r
);
12610 /* Record handler for advance SIMD structure load/store instructions. */
12613 thumb2_record_asimd_struct_ld_st (insn_decode_record
*thumb2_insn_r
)
12615 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12616 uint32_t l_bit
, a_bit
, b_bits
;
12617 uint32_t record_buf
[128], record_buf_mem
[128];
12618 uint32_t reg_rn
, reg_vd
, address
, f_elem
;
12619 uint32_t index_r
= 0, index_e
= 0, bf_regs
= 0, index_m
= 0, loop_t
= 0;
12622 l_bit
= bit (thumb2_insn_r
->arm_insn
, 21);
12623 a_bit
= bit (thumb2_insn_r
->arm_insn
, 23);
12624 b_bits
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12625 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12626 reg_vd
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12627 reg_vd
= (bit (thumb2_insn_r
->arm_insn
, 22) << 4) | reg_vd
;
12628 f_ebytes
= (1 << bits (thumb2_insn_r
->arm_insn
, 6, 7));
12629 f_elem
= 8 / f_ebytes
;
12633 ULONGEST u_regval
= 0;
12634 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12635 address
= u_regval
;
12640 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12642 if (b_bits
== 0x07)
12644 else if (b_bits
== 0x0a)
12646 else if (b_bits
== 0x06)
12648 else if (b_bits
== 0x02)
12653 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12655 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12657 record_buf_mem
[index_m
++] = f_ebytes
;
12658 record_buf_mem
[index_m
++] = address
;
12659 address
= address
+ f_ebytes
;
12660 thumb2_insn_r
->mem_rec_count
+= 1;
12665 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12667 if (b_bits
== 0x09 || b_bits
== 0x08)
12669 else if (b_bits
== 0x03)
12674 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12675 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12677 for (loop_t
= 0; loop_t
< 2; loop_t
++)
12679 record_buf_mem
[index_m
++] = f_ebytes
;
12680 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12681 thumb2_insn_r
->mem_rec_count
+= 1;
12683 address
= address
+ (2 * f_ebytes
);
12687 else if ((b_bits
& 0x0e) == 0x04)
12689 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12691 for (loop_t
= 0; loop_t
< 3; loop_t
++)
12693 record_buf_mem
[index_m
++] = f_ebytes
;
12694 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12695 thumb2_insn_r
->mem_rec_count
+= 1;
12697 address
= address
+ (3 * f_ebytes
);
12701 else if (!(b_bits
& 0x0e))
12703 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12705 for (loop_t
= 0; loop_t
< 4; loop_t
++)
12707 record_buf_mem
[index_m
++] = f_ebytes
;
12708 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12709 thumb2_insn_r
->mem_rec_count
+= 1;
12711 address
= address
+ (4 * f_ebytes
);
12717 uint8_t bft_size
= bits (thumb2_insn_r
->arm_insn
, 10, 11);
12719 if (bft_size
== 0x00)
12721 else if (bft_size
== 0x01)
12723 else if (bft_size
== 0x02)
12729 if (!(b_bits
& 0x0b) || b_bits
== 0x08)
12730 thumb2_insn_r
->mem_rec_count
= 1;
12732 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09)
12733 thumb2_insn_r
->mem_rec_count
= 2;
12735 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a)
12736 thumb2_insn_r
->mem_rec_count
= 3;
12738 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b)
12739 thumb2_insn_r
->mem_rec_count
= 4;
12741 for (index_m
= 0; index_m
< thumb2_insn_r
->mem_rec_count
; index_m
++)
12743 record_buf_mem
[index_m
] = f_ebytes
;
12744 record_buf_mem
[index_m
] = address
+ (index_m
* f_ebytes
);
12753 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12754 thumb2_insn_r
->reg_rec_count
= 1;
12756 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12757 thumb2_insn_r
->reg_rec_count
= 2;
12759 else if ((b_bits
& 0x0e) == 0x04)
12760 thumb2_insn_r
->reg_rec_count
= 3;
12762 else if (!(b_bits
& 0x0e))
12763 thumb2_insn_r
->reg_rec_count
= 4;
12768 if (!(b_bits
& 0x0b) || b_bits
== 0x08 || b_bits
== 0x0c)
12769 thumb2_insn_r
->reg_rec_count
= 1;
12771 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09 || b_bits
== 0x0d)
12772 thumb2_insn_r
->reg_rec_count
= 2;
12774 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a || b_bits
== 0x0e)
12775 thumb2_insn_r
->reg_rec_count
= 3;
12777 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b || b_bits
== 0x0f)
12778 thumb2_insn_r
->reg_rec_count
= 4;
12780 for (index_r
= 0; index_r
< thumb2_insn_r
->reg_rec_count
; index_r
++)
12781 record_buf
[index_r
] = reg_vd
+ ARM_D0_REGNUM
+ index_r
;
12785 if (bits (thumb2_insn_r
->arm_insn
, 0, 3) != 15)
12787 record_buf
[index_r
] = reg_rn
;
12788 thumb2_insn_r
->reg_rec_count
+= 1;
12791 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12793 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12798 /* Decodes thumb2 instruction type and invokes its record handler. */
12800 static unsigned int
12801 thumb2_record_decode_insn_handler (insn_decode_record
*thumb2_insn_r
)
12803 uint32_t op
, op1
, op2
;
12805 op
= bit (thumb2_insn_r
->arm_insn
, 15);
12806 op1
= bits (thumb2_insn_r
->arm_insn
, 27, 28);
12807 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12811 if (!(op2
& 0x64 ))
12813 /* Load/store multiple instruction. */
12814 return thumb2_record_ld_st_multiple (thumb2_insn_r
);
12816 else if (!((op2
& 0x64) ^ 0x04))
12818 /* Load/store (dual/exclusive) and table branch instruction. */
12819 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r
);
12821 else if (!((op2
& 0x20) ^ 0x20))
12823 /* Data-processing (shifted register). */
12824 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12826 else if (op2
& 0x40)
12828 /* Co-processor instructions. */
12829 return thumb2_record_coproc_insn (thumb2_insn_r
);
12832 else if (op1
== 0x02)
12836 /* Branches and miscellaneous control instructions. */
12837 return thumb2_record_branch_misc_cntrl (thumb2_insn_r
);
12839 else if (op2
& 0x20)
12841 /* Data-processing (plain binary immediate) instruction. */
12842 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12846 /* Data-processing (modified immediate). */
12847 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12850 else if (op1
== 0x03)
12852 if (!(op2
& 0x71 ))
12854 /* Store single data item. */
12855 return thumb2_record_str_single_data (thumb2_insn_r
);
12857 else if (!((op2
& 0x71) ^ 0x10))
12859 /* Advanced SIMD or structure load/store instructions. */
12860 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r
);
12862 else if (!((op2
& 0x67) ^ 0x01))
12864 /* Load byte, memory hints instruction. */
12865 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
12867 else if (!((op2
& 0x67) ^ 0x03))
12869 /* Load halfword, memory hints instruction. */
12870 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
12872 else if (!((op2
& 0x67) ^ 0x05))
12874 /* Load word instruction. */
12875 return thumb2_record_ld_word (thumb2_insn_r
);
12877 else if (!((op2
& 0x70) ^ 0x20))
12879 /* Data-processing (register) instruction. */
12880 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12882 else if (!((op2
& 0x78) ^ 0x30))
12884 /* Multiply, multiply accumulate, abs diff instruction. */
12885 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12887 else if (!((op2
& 0x78) ^ 0x38))
12889 /* Long multiply, long multiply accumulate, and divide. */
12890 return thumb2_record_lmul_lmla_div (thumb2_insn_r
);
12892 else if (op2
& 0x40)
12894 /* Co-processor instructions. */
12895 return thumb2_record_coproc_insn (thumb2_insn_r
);
12902 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12903 and positive val on fauilure. */
12906 extract_arm_insn (insn_decode_record
*insn_record
, uint32_t insn_size
)
12908 gdb_byte buf
[insn_size
];
12910 memset (&buf
[0], 0, insn_size
);
12912 if (target_read_memory (insn_record
->this_addr
, &buf
[0], insn_size
))
12914 insn_record
->arm_insn
= (uint32_t) extract_unsigned_integer (&buf
[0],
12916 gdbarch_byte_order_for_code (insn_record
->gdbarch
));
12920 typedef int (*sti_arm_hdl_fp_t
) (insn_decode_record
*);
12922 /* Decode arm/thumb insn depending on condition cods and opcodes; and
12926 decode_insn (insn_decode_record
*arm_record
, record_type_t record_type
,
12927 uint32_t insn_size
)
12930 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm
12932 static const sti_arm_hdl_fp_t arm_handle_insn
[8] =
12934 arm_record_data_proc_misc_ld_str
, /* 000. */
12935 arm_record_data_proc_imm
, /* 001. */
12936 arm_record_ld_st_imm_offset
, /* 010. */
12937 arm_record_ld_st_reg_offset
, /* 011. */
12938 arm_record_ld_st_multiple
, /* 100. */
12939 arm_record_b_bl
, /* 101. */
12940 arm_record_asimd_vfp_coproc
, /* 110. */
12941 arm_record_coproc_data_proc
/* 111. */
12944 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb
12946 static const sti_arm_hdl_fp_t thumb_handle_insn
[8] =
12948 thumb_record_shift_add_sub
, /* 000. */
12949 thumb_record_add_sub_cmp_mov
, /* 001. */
12950 thumb_record_ld_st_reg_offset
, /* 010. */
12951 thumb_record_ld_st_imm_offset
, /* 011. */
12952 thumb_record_ld_st_stack
, /* 100. */
12953 thumb_record_misc
, /* 101. */
12954 thumb_record_ldm_stm_swi
, /* 110. */
12955 thumb_record_branch
/* 111. */
12958 uint32_t ret
= 0; /* return value: negative:failure 0:success. */
12959 uint32_t insn_id
= 0;
12961 if (extract_arm_insn (arm_record
, insn_size
))
12965 printf_unfiltered (_("Process record: error reading memory at "
12966 "addr %s len = %d.\n"),
12967 paddress (arm_record
->gdbarch
,
12968 arm_record
->this_addr
), insn_size
);
12972 else if (ARM_RECORD
== record_type
)
12974 arm_record
->cond
= bits (arm_record
->arm_insn
, 28, 31);
12975 insn_id
= bits (arm_record
->arm_insn
, 25, 27);
12977 if (arm_record
->cond
== 0xf)
12978 ret
= arm_record_extension_space (arm_record
);
12981 /* If this insn has fallen into extension space
12982 then we need not decode it anymore. */
12983 ret
= arm_handle_insn
[insn_id
] (arm_record
);
12985 if (ret
!= ARM_RECORD_SUCCESS
)
12987 arm_record_unsupported_insn (arm_record
);
12991 else if (THUMB_RECORD
== record_type
)
12993 /* As thumb does not have condition codes, we set negative. */
12994 arm_record
->cond
= -1;
12995 insn_id
= bits (arm_record
->arm_insn
, 13, 15);
12996 ret
= thumb_handle_insn
[insn_id
] (arm_record
);
12997 if (ret
!= ARM_RECORD_SUCCESS
)
12999 arm_record_unsupported_insn (arm_record
);
13003 else if (THUMB2_RECORD
== record_type
)
13005 /* As thumb does not have condition codes, we set negative. */
13006 arm_record
->cond
= -1;
13008 /* Swap first half of 32bit thumb instruction with second half. */
13009 arm_record
->arm_insn
13010 = (arm_record
->arm_insn
>> 16) | (arm_record
->arm_insn
<< 16);
13012 ret
= thumb2_record_decode_insn_handler (arm_record
);
13014 if (ret
!= ARM_RECORD_SUCCESS
)
13016 arm_record_unsupported_insn (arm_record
);
13022 /* Throw assertion. */
13023 gdb_assert_not_reached ("not a valid instruction, could not decode");
13030 /* Cleans up local record registers and memory allocations. */
13033 deallocate_reg_mem (insn_decode_record
*record
)
13035 xfree (record
->arm_regs
);
13036 xfree (record
->arm_mems
);
13040 /* Parse the current instruction and record the values of the registers and
13041 memory that will be changed in current instruction to record_arch_list".
13042 Return -1 if something is wrong. */
13045 arm_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
13046 CORE_ADDR insn_addr
)
13049 uint32_t no_of_rec
= 0;
13050 uint32_t ret
= 0; /* return value: -1:record failure ; 0:success */
13051 ULONGEST t_bit
= 0, insn_id
= 0;
13053 ULONGEST u_regval
= 0;
13055 insn_decode_record arm_record
;
13057 memset (&arm_record
, 0, sizeof (insn_decode_record
));
13058 arm_record
.regcache
= regcache
;
13059 arm_record
.this_addr
= insn_addr
;
13060 arm_record
.gdbarch
= gdbarch
;
13063 if (record_debug
> 1)
13065 fprintf_unfiltered (gdb_stdlog
, "Process record: arm_process_record "
13067 paddress (gdbarch
, arm_record
.this_addr
));
13070 if (extract_arm_insn (&arm_record
, 2))
13074 printf_unfiltered (_("Process record: error reading memory at "
13075 "addr %s len = %d.\n"),
13076 paddress (arm_record
.gdbarch
,
13077 arm_record
.this_addr
), 2);
13082 /* Check the insn, whether it is thumb or arm one. */
13084 t_bit
= arm_psr_thumb_bit (arm_record
.gdbarch
);
13085 regcache_raw_read_unsigned (arm_record
.regcache
, ARM_PS_REGNUM
, &u_regval
);
13088 if (!(u_regval
& t_bit
))
13090 /* We are decoding arm insn. */
13091 ret
= decode_insn (&arm_record
, ARM_RECORD
, ARM_INSN_SIZE_BYTES
);
13095 insn_id
= bits (arm_record
.arm_insn
, 11, 15);
13096 /* is it thumb2 insn? */
13097 if ((0x1D == insn_id
) || (0x1E == insn_id
) || (0x1F == insn_id
))
13099 ret
= decode_insn (&arm_record
, THUMB2_RECORD
,
13100 THUMB2_INSN_SIZE_BYTES
);
13104 /* We are decoding thumb insn. */
13105 ret
= decode_insn (&arm_record
, THUMB_RECORD
, THUMB_INSN_SIZE_BYTES
);
13111 /* Record registers. */
13112 record_full_arch_list_add_reg (arm_record
.regcache
, ARM_PC_REGNUM
);
13113 if (arm_record
.arm_regs
)
13115 for (no_of_rec
= 0; no_of_rec
< arm_record
.reg_rec_count
; no_of_rec
++)
13117 if (record_full_arch_list_add_reg
13118 (arm_record
.regcache
, arm_record
.arm_regs
[no_of_rec
]))
13122 /* Record memories. */
13123 if (arm_record
.arm_mems
)
13125 for (no_of_rec
= 0; no_of_rec
< arm_record
.mem_rec_count
; no_of_rec
++)
13127 if (record_full_arch_list_add_mem
13128 ((CORE_ADDR
)arm_record
.arm_mems
[no_of_rec
].addr
,
13129 arm_record
.arm_mems
[no_of_rec
].len
))
13134 if (record_full_arch_list_add_end ())
13139 deallocate_reg_mem (&arm_record
);