1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
32 #include "reggroups.h"
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
41 #include "dwarf2-frame.h"
43 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "gdb/sim-arm.h"
52 #include "coff/internal.h"
55 #include "gdb_assert.h"
58 #include "features/arm-with-m.c"
62 /* Macros for setting and testing a bit in a minimal symbol that marks
63 it as Thumb function. The MSB of the minimal symbol's "info" field
64 is used for this purpose.
66 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
67 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
69 #define MSYMBOL_SET_SPECIAL(msym) \
70 MSYMBOL_TARGET_FLAG_1 (msym) = 1
72 #define MSYMBOL_IS_SPECIAL(msym) \
73 MSYMBOL_TARGET_FLAG_1 (msym)
75 /* Per-objfile data used for mapping symbols. */
76 static const struct objfile_data
*arm_objfile_data_key
;
78 struct arm_mapping_symbol
83 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
84 DEF_VEC_O(arm_mapping_symbol_s
);
86 struct arm_per_objfile
88 VEC(arm_mapping_symbol_s
) **section_maps
;
91 /* The list of available "set arm ..." and "show arm ..." commands. */
92 static struct cmd_list_element
*setarmcmdlist
= NULL
;
93 static struct cmd_list_element
*showarmcmdlist
= NULL
;
95 /* The type of floating-point to use. Keep this in sync with enum
96 arm_float_model, and the help string in _initialize_arm_tdep. */
97 static const char *fp_model_strings
[] =
107 /* A variable that can be configured by the user. */
108 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
109 static const char *current_fp_model
= "auto";
111 /* The ABI to use. Keep this in sync with arm_abi_kind. */
112 static const char *arm_abi_strings
[] =
120 /* A variable that can be configured by the user. */
121 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
122 static const char *arm_abi_string
= "auto";
124 /* The execution mode to assume. */
125 static const char *arm_mode_strings
[] =
133 static const char *arm_fallback_mode_string
= "auto";
134 static const char *arm_force_mode_string
= "auto";
136 /* Number of different reg name sets (options). */
137 static int num_disassembly_options
;
139 /* The standard register names, and all the valid aliases for them. Note
140 that `fp', `sp' and `pc' are not added in this alias list, because they
141 have been added as builtin user registers in
142 std-regs.c:_initialize_frame_reg. */
147 } arm_register_aliases
[] = {
148 /* Basic register numbers. */
165 /* Synonyms (argument and variable registers). */
178 /* Other platform-specific names for r9. */
184 /* Names used by GCC (not listed in the ARM EABI). */
186 /* A special name from the older ATPCS. */
190 static const char *const arm_register_names
[] =
191 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
192 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
193 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
194 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
195 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
196 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
197 "fps", "cpsr" }; /* 24 25 */
199 /* Valid register name styles. */
200 static const char **valid_disassembly_styles
;
202 /* Disassembly style to use. Default to "std" register names. */
203 static const char *disassembly_style
;
205 /* This is used to keep the bfd arch_info in sync with the disassembly
207 static void set_disassembly_style_sfunc(char *, int,
208 struct cmd_list_element
*);
209 static void set_disassembly_style (void);
211 static void convert_from_extended (const struct floatformat
*, const void *,
213 static void convert_to_extended (const struct floatformat
*, void *,
216 static void arm_neon_quad_read (struct gdbarch
*gdbarch
,
217 struct regcache
*regcache
,
218 int regnum
, gdb_byte
*buf
);
219 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
220 struct regcache
*regcache
,
221 int regnum
, const gdb_byte
*buf
);
223 struct arm_prologue_cache
225 /* The stack pointer at the time this frame was created; i.e. the
226 caller's stack pointer when this function was called. It is used
227 to identify this frame. */
230 /* The frame base for this frame is just prev_sp - frame size.
231 FRAMESIZE is the distance from the frame pointer to the
232 initial stack pointer. */
236 /* The register used to hold the frame pointer for this frame. */
239 /* Saved register offsets. */
240 struct trad_frame_saved_reg
*saved_regs
;
243 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
244 CORE_ADDR prologue_start
,
245 CORE_ADDR prologue_end
,
246 struct arm_prologue_cache
*cache
);
248 /* Architecture version for displaced stepping. This effects the behaviour of
249 certain instructions, and really should not be hard-wired. */
251 #define DISPLACED_STEPPING_ARCH_VERSION 5
253 /* Addresses for calling Thumb functions have the bit 0 set.
254 Here are some macros to test, set, or clear bit 0 of addresses. */
255 #define IS_THUMB_ADDR(addr) ((addr) & 1)
256 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
257 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
259 /* Set to true if the 32-bit mode is in use. */
263 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
266 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
268 if (gdbarch_tdep (gdbarch
)->is_m
)
274 /* Determine if FRAME is executing in Thumb mode. */
277 arm_frame_is_thumb (struct frame_info
*frame
)
280 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
282 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
283 directly (from a signal frame or dummy frame) or by interpreting
284 the saved LR (from a prologue or DWARF frame). So consult it and
285 trust the unwinders. */
286 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
288 return (cpsr
& t_bit
) != 0;
291 /* Callback for VEC_lower_bound. */
294 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
295 const struct arm_mapping_symbol
*rhs
)
297 return lhs
->value
< rhs
->value
;
300 /* Search for the mapping symbol covering MEMADDR. If one is found,
301 return its type. Otherwise, return 0. If START is non-NULL,
302 set *START to the location of the mapping symbol. */
305 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
307 struct obj_section
*sec
;
309 /* If there are mapping symbols, consult them. */
310 sec
= find_pc_section (memaddr
);
313 struct arm_per_objfile
*data
;
314 VEC(arm_mapping_symbol_s
) *map
;
315 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
319 data
= objfile_data (sec
->objfile
, arm_objfile_data_key
);
322 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
323 if (!VEC_empty (arm_mapping_symbol_s
, map
))
325 struct arm_mapping_symbol
*map_sym
;
327 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
328 arm_compare_mapping_symbols
);
330 /* VEC_lower_bound finds the earliest ordered insertion
331 point. If the following symbol starts at this exact
332 address, we use that; otherwise, the preceding
333 mapping symbol covers this address. */
334 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
336 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
337 if (map_sym
->value
== map_key
.value
)
340 *start
= map_sym
->value
+ obj_section_addr (sec
);
341 return map_sym
->type
;
347 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
349 *start
= map_sym
->value
+ obj_section_addr (sec
);
350 return map_sym
->type
;
359 static CORE_ADDR
arm_get_next_pc_raw (struct frame_info
*frame
,
360 CORE_ADDR pc
, int insert_bkpt
);
362 /* Determine if the program counter specified in MEMADDR is in a Thumb
363 function. This function should be called for addresses unrelated to
364 any executing frame; otherwise, prefer arm_frame_is_thumb. */
367 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
369 struct obj_section
*sec
;
370 struct minimal_symbol
*sym
;
373 /* If bit 0 of the address is set, assume this is a Thumb address. */
374 if (IS_THUMB_ADDR (memaddr
))
377 /* If the user wants to override the symbol table, let him. */
378 if (strcmp (arm_force_mode_string
, "arm") == 0)
380 if (strcmp (arm_force_mode_string
, "thumb") == 0)
383 /* ARM v6-M and v7-M are always in Thumb mode. */
384 if (gdbarch_tdep (gdbarch
)->is_m
)
387 /* If there are mapping symbols, consult them. */
388 type
= arm_find_mapping_symbol (memaddr
, NULL
);
392 /* Thumb functions have a "special" bit set in minimal symbols. */
393 sym
= lookup_minimal_symbol_by_pc (memaddr
);
395 return (MSYMBOL_IS_SPECIAL (sym
));
397 /* If the user wants to override the fallback mode, let them. */
398 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
400 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
403 /* If we couldn't find any symbol, but we're talking to a running
404 target, then trust the current value of $cpsr. This lets
405 "display/i $pc" always show the correct mode (though if there is
406 a symbol table we will not reach here, so it still may not be
407 displayed in the mode it will be executed).
409 As a further heuristic if we detect that we are doing a single-step we
410 see what state executing the current instruction ends up with us being
412 if (target_has_registers
)
414 struct frame_info
*current_frame
= get_current_frame ();
415 CORE_ADDR current_pc
= get_frame_pc (current_frame
);
416 int is_thumb
= arm_frame_is_thumb (current_frame
);
418 if (memaddr
== current_pc
)
422 struct gdbarch
*gdbarch
= get_frame_arch (current_frame
);
423 next_pc
= arm_get_next_pc_raw (current_frame
, current_pc
, FALSE
);
424 if (memaddr
== gdbarch_addr_bits_remove (gdbarch
, next_pc
))
425 return IS_THUMB_ADDR (next_pc
);
431 /* Otherwise we're out of luck; we assume ARM. */
435 /* Remove useless bits from addresses in a running program. */
437 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
440 return UNMAKE_THUMB_ADDR (val
);
442 return (val
& 0x03fffffc);
445 /* When reading symbols, we need to zap the low bit of the address,
446 which may be set to 1 for Thumb functions. */
448 arm_smash_text_address (struct gdbarch
*gdbarch
, CORE_ADDR val
)
453 /* Return 1 if PC is the start of a compiler helper function which
454 can be safely ignored during prologue skipping. IS_THUMB is true
455 if the function is known to be a Thumb function due to the way it
458 skip_prologue_function (struct gdbarch
*gdbarch
, CORE_ADDR pc
, int is_thumb
)
460 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
461 struct minimal_symbol
*msym
;
463 msym
= lookup_minimal_symbol_by_pc (pc
);
465 && SYMBOL_VALUE_ADDRESS (msym
) == pc
466 && SYMBOL_LINKAGE_NAME (msym
) != NULL
)
468 const char *name
= SYMBOL_LINKAGE_NAME (msym
);
470 /* The GNU linker's Thumb call stub to foo is named
472 if (strstr (name
, "_from_thumb") != NULL
)
475 /* On soft-float targets, __truncdfsf2 is called to convert promoted
476 arguments to their argument types in non-prototyped
478 if (strncmp (name
, "__truncdfsf2", strlen ("__truncdfsf2")) == 0)
480 if (strncmp (name
, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
483 /* Internal functions related to thread-local storage. */
484 if (strncmp (name
, "__tls_get_addr", strlen ("__tls_get_addr")) == 0)
486 if (strncmp (name
, "__aeabi_read_tp", strlen ("__aeabi_read_tp")) == 0)
491 /* If we run against a stripped glibc, we may be unable to identify
492 special functions by name. Check for one important case,
493 __aeabi_read_tp, by comparing the *code* against the default
494 implementation (this is hand-written ARM assembler in glibc). */
497 && read_memory_unsigned_integer (pc
, 4, byte_order_for_code
)
498 == 0xe3e00a0f /* mov r0, #0xffff0fff */
499 && read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
)
500 == 0xe240f01f) /* sub pc, r0, #31 */
507 /* Support routines for instruction parsing. */
508 #define submask(x) ((1L << ((x) + 1)) - 1)
509 #define bit(obj,st) (((obj) >> (st)) & 1)
510 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
511 #define sbits(obj,st,fn) \
512 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
513 #define BranchDest(addr,instr) \
514 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
516 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
517 the first 16-bit of instruction, and INSN2 is the second 16-bit of
519 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
520 ((bits ((insn1), 0, 3) << 12) \
521 | (bits ((insn1), 10, 10) << 11) \
522 | (bits ((insn2), 12, 14) << 8) \
523 | bits ((insn2), 0, 7))
525 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
526 the 32-bit instruction. */
527 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
528 ((bits ((insn), 16, 19) << 12) \
529 | bits ((insn), 0, 11))
531 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
534 thumb_expand_immediate (unsigned int imm
)
536 unsigned int count
= imm
>> 7;
544 return (imm
& 0xff) | ((imm
& 0xff) << 16);
546 return ((imm
& 0xff) << 8) | ((imm
& 0xff) << 24);
548 return (imm
& 0xff) | ((imm
& 0xff) << 8)
549 | ((imm
& 0xff) << 16) | ((imm
& 0xff) << 24);
552 return (0x80 | (imm
& 0x7f)) << (32 - count
);
555 /* Return 1 if the 16-bit Thumb instruction INST might change
556 control flow, 0 otherwise. */
559 thumb_instruction_changes_pc (unsigned short inst
)
561 if ((inst
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
564 if ((inst
& 0xf000) == 0xd000) /* conditional branch */
567 if ((inst
& 0xf800) == 0xe000) /* unconditional branch */
570 if ((inst
& 0xff00) == 0x4700) /* bx REG, blx REG */
573 if ((inst
& 0xff87) == 0x4687) /* mov pc, REG */
576 if ((inst
& 0xf500) == 0xb100) /* CBNZ or CBZ. */
582 /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
583 might change control flow, 0 otherwise. */
586 thumb2_instruction_changes_pc (unsigned short inst1
, unsigned short inst2
)
588 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
590 /* Branches and miscellaneous control instructions. */
592 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
597 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
599 /* SUBS PC, LR, #imm8. */
602 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
604 /* Conditional branch. */
611 if ((inst1
& 0xfe50) == 0xe810)
613 /* Load multiple or RFE. */
615 if (bit (inst1
, 7) && !bit (inst1
, 8))
621 else if (!bit (inst1
, 7) && bit (inst1
, 8))
627 else if (bit (inst1
, 7) && bit (inst1
, 8))
632 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
641 if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
643 /* MOV PC or MOVS PC. */
647 if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
650 if (bits (inst1
, 0, 3) == 15)
656 if ((inst2
& 0x0fc0) == 0x0000)
662 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
668 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
677 /* Analyze a Thumb prologue, looking for a recognizable stack frame
678 and frame pointer. Scan until we encounter a store that could
679 clobber the stack frame unexpectedly, or an unknown instruction.
680 Return the last address which is definitely safe to skip for an
681 initial breakpoint. */
684 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
685 CORE_ADDR start
, CORE_ADDR limit
,
686 struct arm_prologue_cache
*cache
)
688 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
689 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
692 struct pv_area
*stack
;
693 struct cleanup
*back_to
;
695 CORE_ADDR unrecognized_pc
= 0;
697 for (i
= 0; i
< 16; i
++)
698 regs
[i
] = pv_register (i
, 0);
699 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
700 back_to
= make_cleanup_free_pv_area (stack
);
702 while (start
< limit
)
706 insn
= read_memory_unsigned_integer (start
, 2, byte_order_for_code
);
708 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
713 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
716 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
717 whether to save LR (R14). */
718 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
720 /* Calculate offsets of saved R0-R7 and LR. */
721 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
722 if (mask
& (1 << regno
))
724 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
726 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
729 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
732 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
733 if (insn
& 0x80) /* Check for SUB. */
734 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
737 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
740 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
741 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
743 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
744 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
745 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
747 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
748 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
749 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
751 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
752 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
753 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
754 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
755 regs
[bits (insn
, 6, 8)]);
756 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
757 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
759 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
760 int rm
= bits (insn
, 3, 6);
761 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
763 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
765 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
766 int src_reg
= (insn
& 0x78) >> 3;
767 regs
[dst_reg
] = regs
[src_reg
];
769 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
771 /* Handle stores to the stack. Normally pushes are used,
772 but with GCC -mtpcs-frame, there may be other stores
773 in the prologue to create the frame. */
774 int regno
= (insn
>> 8) & 0x7;
777 offset
= (insn
& 0xff) << 2;
778 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
780 if (pv_area_store_would_trash (stack
, addr
))
783 pv_area_store (stack
, addr
, 4, regs
[regno
]);
785 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
787 int rd
= bits (insn
, 0, 2);
788 int rn
= bits (insn
, 3, 5);
791 offset
= bits (insn
, 6, 10) << 2;
792 addr
= pv_add_constant (regs
[rn
], offset
);
794 if (pv_area_store_would_trash (stack
, addr
))
797 pv_area_store (stack
, addr
, 4, regs
[rd
]);
799 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
800 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
801 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
802 /* Ignore stores of argument registers to the stack. */
804 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
805 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
806 /* Ignore block loads from the stack, potentially copying
807 parameters from memory. */
809 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
810 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
811 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
812 /* Similarly ignore single loads from the stack. */
814 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
815 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
816 /* Skip register copies, i.e. saves to another register
817 instead of the stack. */
819 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
820 /* Recognize constant loads; even with small stacks these are necessary
822 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
823 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
825 /* Constant pool loads, for the same reason. */
826 unsigned int constant
;
829 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
830 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
831 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
833 else if ((insn
& 0xe000) == 0xe000)
835 unsigned short inst2
;
837 inst2
= read_memory_unsigned_integer (start
+ 2, 2,
838 byte_order_for_code
);
840 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
842 /* BL, BLX. Allow some special function calls when
843 skipping the prologue; GCC generates these before
844 storing arguments to the stack. */
846 int j1
, j2
, imm1
, imm2
;
848 imm1
= sbits (insn
, 0, 10);
849 imm2
= bits (inst2
, 0, 10);
850 j1
= bit (inst2
, 13);
851 j2
= bit (inst2
, 11);
853 offset
= ((imm1
<< 12) + (imm2
<< 1));
854 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
856 nextpc
= start
+ 4 + offset
;
857 /* For BLX make sure to clear the low bits. */
858 if (bit (inst2
, 12) == 0)
859 nextpc
= nextpc
& 0xfffffffc;
861 if (!skip_prologue_function (gdbarch
, nextpc
,
862 bit (inst2
, 12) != 0))
866 else if ((insn
& 0xffd0) == 0xe900 /* stmdb Rn{!},
868 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
870 pv_t addr
= regs
[bits (insn
, 0, 3)];
873 if (pv_area_store_would_trash (stack
, addr
))
876 /* Calculate offsets of saved registers. */
877 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
878 if (inst2
& (1 << regno
))
880 addr
= pv_add_constant (addr
, -4);
881 pv_area_store (stack
, addr
, 4, regs
[regno
]);
885 regs
[bits (insn
, 0, 3)] = addr
;
888 else if ((insn
& 0xff50) == 0xe940 /* strd Rt, Rt2,
890 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
892 int regno1
= bits (inst2
, 12, 15);
893 int regno2
= bits (inst2
, 8, 11);
894 pv_t addr
= regs
[bits (insn
, 0, 3)];
896 offset
= inst2
& 0xff;
898 addr
= pv_add_constant (addr
, offset
);
900 addr
= pv_add_constant (addr
, -offset
);
902 if (pv_area_store_would_trash (stack
, addr
))
905 pv_area_store (stack
, addr
, 4, regs
[regno1
]);
906 pv_area_store (stack
, pv_add_constant (addr
, 4),
910 regs
[bits (insn
, 0, 3)] = addr
;
913 else if ((insn
& 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
914 && (inst2
& 0x0c00) == 0x0c00
915 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
917 int regno
= bits (inst2
, 12, 15);
918 pv_t addr
= regs
[bits (insn
, 0, 3)];
920 offset
= inst2
& 0xff;
922 addr
= pv_add_constant (addr
, offset
);
924 addr
= pv_add_constant (addr
, -offset
);
926 if (pv_area_store_would_trash (stack
, addr
))
929 pv_area_store (stack
, addr
, 4, regs
[regno
]);
932 regs
[bits (insn
, 0, 3)] = addr
;
935 else if ((insn
& 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
936 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
938 int regno
= bits (inst2
, 12, 15);
941 offset
= inst2
& 0xfff;
942 addr
= pv_add_constant (regs
[bits (insn
, 0, 3)], offset
);
944 if (pv_area_store_would_trash (stack
, addr
))
947 pv_area_store (stack
, addr
, 4, regs
[regno
]);
950 else if ((insn
& 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
951 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
952 /* Ignore stores of argument registers to the stack. */
955 else if ((insn
& 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
956 && (inst2
& 0x0d00) == 0x0c00
957 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
958 /* Ignore stores of argument registers to the stack. */
961 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!],
963 && (inst2
& 0x8000) == 0x0000
964 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
965 /* Ignore block loads from the stack, potentially copying
966 parameters from memory. */
969 else if ((insn
& 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
971 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
972 /* Similarly ignore dual loads from the stack. */
975 else if ((insn
& 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
976 && (inst2
& 0x0d00) == 0x0c00
977 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
978 /* Similarly ignore single loads from the stack. */
981 else if ((insn
& 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
982 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
983 /* Similarly ignore single loads from the stack. */
986 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
987 && (inst2
& 0x8000) == 0x0000)
989 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
990 | (bits (inst2
, 12, 14) << 8)
991 | bits (inst2
, 0, 7));
993 regs
[bits (inst2
, 8, 11)]
994 = pv_add_constant (regs
[bits (insn
, 0, 3)],
995 thumb_expand_immediate (imm
));
998 else if ((insn
& 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
999 && (inst2
& 0x8000) == 0x0000)
1001 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1002 | (bits (inst2
, 12, 14) << 8)
1003 | bits (inst2
, 0, 7));
1005 regs
[bits (inst2
, 8, 11)]
1006 = pv_add_constant (regs
[bits (insn
, 0, 3)], imm
);
1009 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
1010 && (inst2
& 0x8000) == 0x0000)
1012 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1013 | (bits (inst2
, 12, 14) << 8)
1014 | bits (inst2
, 0, 7));
1016 regs
[bits (inst2
, 8, 11)]
1017 = pv_add_constant (regs
[bits (insn
, 0, 3)],
1018 - (CORE_ADDR
) thumb_expand_immediate (imm
));
1021 else if ((insn
& 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
1022 && (inst2
& 0x8000) == 0x0000)
1024 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1025 | (bits (inst2
, 12, 14) << 8)
1026 | bits (inst2
, 0, 7));
1028 regs
[bits (inst2
, 8, 11)]
1029 = pv_add_constant (regs
[bits (insn
, 0, 3)], - (CORE_ADDR
) imm
);
1032 else if ((insn
& 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1034 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1035 | (bits (inst2
, 12, 14) << 8)
1036 | bits (inst2
, 0, 7));
1038 regs
[bits (inst2
, 8, 11)]
1039 = pv_constant (thumb_expand_immediate (imm
));
1042 else if ((insn
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1045 = EXTRACT_MOVW_MOVT_IMM_T (insn
, inst2
);
1047 regs
[bits (inst2
, 8, 11)] = pv_constant (imm
);
1050 else if (insn
== 0xea5f /* mov.w Rd,Rm */
1051 && (inst2
& 0xf0f0) == 0)
1053 int dst_reg
= (inst2
& 0x0f00) >> 8;
1054 int src_reg
= inst2
& 0xf;
1055 regs
[dst_reg
] = regs
[src_reg
];
1058 else if ((insn
& 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1060 /* Constant pool loads. */
1061 unsigned int constant
;
1064 offset
= bits (insn
, 0, 11);
1066 loc
= start
+ 4 + offset
;
1068 loc
= start
+ 4 - offset
;
1070 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1071 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1074 else if ((insn
& 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1076 /* Constant pool loads. */
1077 unsigned int constant
;
1080 offset
= bits (insn
, 0, 7) << 2;
1082 loc
= start
+ 4 + offset
;
1084 loc
= start
+ 4 - offset
;
1086 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1087 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1089 constant
= read_memory_unsigned_integer (loc
+ 4, 4, byte_order
);
1090 regs
[bits (inst2
, 8, 11)] = pv_constant (constant
);
1093 else if (thumb2_instruction_changes_pc (insn
, inst2
))
1095 /* Don't scan past anything that might change control flow. */
1100 /* The optimizer might shove anything into the prologue,
1101 so we just skip what we don't recognize. */
1102 unrecognized_pc
= start
;
1107 else if (thumb_instruction_changes_pc (insn
))
1109 /* Don't scan past anything that might change control flow. */
1114 /* The optimizer might shove anything into the prologue,
1115 so we just skip what we don't recognize. */
1116 unrecognized_pc
= start
;
1123 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1124 paddress (gdbarch
, start
));
1126 if (unrecognized_pc
== 0)
1127 unrecognized_pc
= start
;
1131 do_cleanups (back_to
);
1132 return unrecognized_pc
;
1135 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1137 /* Frame pointer is fp. Frame size is constant. */
1138 cache
->framereg
= ARM_FP_REGNUM
;
1139 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1141 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
1143 /* Frame pointer is r7. Frame size is constant. */
1144 cache
->framereg
= THUMB_FP_REGNUM
;
1145 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
1147 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
1149 /* Try the stack pointer... this is a bit desperate. */
1150 cache
->framereg
= ARM_SP_REGNUM
;
1151 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1155 /* We're just out of luck. We don't know where the frame is. */
1156 cache
->framereg
= -1;
1157 cache
->framesize
= 0;
1160 for (i
= 0; i
< 16; i
++)
1161 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
1162 cache
->saved_regs
[i
].addr
= offset
;
1164 do_cleanups (back_to
);
1165 return unrecognized_pc
;
1169 /* Try to analyze the instructions starting from PC, which load symbol
1170 __stack_chk_guard. Return the address of instruction after loading this
1171 symbol, set the dest register number to *BASEREG, and set the size of
1172 instructions for loading symbol in OFFSET. Return 0 if instructions are
1176 arm_analyze_load_stack_chk_guard(CORE_ADDR pc
, struct gdbarch
*gdbarch
,
1177 unsigned int *destreg
, int *offset
)
1179 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1180 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1181 unsigned int low
, high
, address
;
1186 unsigned short insn1
1187 = read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
1189 if ((insn1
& 0xf800) == 0x4800) /* ldr Rd, #immed */
1191 *destreg
= bits (insn1
, 8, 10);
1193 address
= bits (insn1
, 0, 7);
1195 else if ((insn1
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1197 unsigned short insn2
1198 = read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1200 low
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1203 = read_memory_unsigned_integer (pc
+ 4, 2, byte_order_for_code
);
1205 = read_memory_unsigned_integer (pc
+ 6, 2, byte_order_for_code
);
1207 /* movt Rd, #const */
1208 if ((insn1
& 0xfbc0) == 0xf2c0)
1210 high
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1211 *destreg
= bits (insn2
, 8, 11);
1213 address
= (high
<< 16 | low
);
1220 = read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
1222 if ((insn
& 0x0e5f0000) == 0x041f0000) /* ldr Rd, #immed */
1224 address
= bits (insn
, 0, 11);
1225 *destreg
= bits (insn
, 12, 15);
1228 else if ((insn
& 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1230 low
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1233 = read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
);
1235 if ((insn
& 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1237 high
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1238 *destreg
= bits (insn
, 12, 15);
1240 address
= (high
<< 16 | low
);
1248 /* Try to skip a sequence of instructions used for stack protector. If PC
1249 points to the first instruction of this sequence, return the address of
1250 first instruction after this sequence, otherwise, return original PC.
1252 On arm, this sequence of instructions is composed of mainly three steps,
1253 Step 1: load symbol __stack_chk_guard,
1254 Step 2: load from address of __stack_chk_guard,
1255 Step 3: store it to somewhere else.
1257 Usually, instructions on step 2 and step 3 are the same on various ARM
1258 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1259 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1260 instructions in step 1 vary from different ARM architectures. On ARMv7,
1263 movw Rn, #:lower16:__stack_chk_guard
1264 movt Rn, #:upper16:__stack_chk_guard
1271 .word __stack_chk_guard
1273 Since ldr/str is a very popular instruction, we can't use them as
1274 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1275 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1276 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1279 arm_skip_stack_protector(CORE_ADDR pc
, struct gdbarch
*gdbarch
)
1281 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1282 unsigned int address
, basereg
;
1283 struct minimal_symbol
*stack_chk_guard
;
1285 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1288 /* Try to parse the instructions in Step 1. */
1289 addr
= arm_analyze_load_stack_chk_guard (pc
, gdbarch
,
1294 stack_chk_guard
= lookup_minimal_symbol_by_pc (addr
);
1295 /* If name of symbol doesn't start with '__stack_chk_guard', this
1296 instruction sequence is not for stack protector. If symbol is
1297 removed, we conservatively think this sequence is for stack protector. */
1299 && strncmp (SYMBOL_LINKAGE_NAME (stack_chk_guard
), "__stack_chk_guard",
1300 strlen ("__stack_chk_guard")) != 0)
1305 unsigned int destreg
;
1307 = read_memory_unsigned_integer (pc
+ offset
, 2, byte_order_for_code
);
1309 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1310 if ((insn
& 0xf800) != 0x6800)
1312 if (bits (insn
, 3, 5) != basereg
)
1314 destreg
= bits (insn
, 0, 2);
1316 insn
= read_memory_unsigned_integer (pc
+ offset
+ 2, 2,
1317 byte_order_for_code
);
1318 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1319 if ((insn
& 0xf800) != 0x6000)
1321 if (destreg
!= bits (insn
, 0, 2))
1326 unsigned int destreg
;
1328 = read_memory_unsigned_integer (pc
+ offset
, 4, byte_order_for_code
);
1330 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1331 if ((insn
& 0x0e500000) != 0x04100000)
1333 if (bits (insn
, 16, 19) != basereg
)
1335 destreg
= bits (insn
, 12, 15);
1336 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1337 insn
= read_memory_unsigned_integer (pc
+ offset
+ 4,
1338 4, byte_order_for_code
);
1339 if ((insn
& 0x0e500000) != 0x04000000)
1341 if (bits (insn
, 12, 15) != destreg
)
1344 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1347 return pc
+ offset
+ 4;
1349 return pc
+ offset
+ 8;
1352 /* Advance the PC across any function entry prologue instructions to
1353 reach some "real" code.
1355 The APCS (ARM Procedure Call Standard) defines the following
1359 [stmfd sp!, {a1,a2,a3,a4}]
1360 stmfd sp!, {...,fp,ip,lr,pc}
1361 [stfe f7, [sp, #-12]!]
1362 [stfe f6, [sp, #-12]!]
1363 [stfe f5, [sp, #-12]!]
1364 [stfe f4, [sp, #-12]!]
1365 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1368 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1370 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1373 CORE_ADDR func_addr
, limit_pc
;
1374 struct symtab_and_line sal
;
1376 /* See if we can determine the end of the prologue via the symbol table.
1377 If so, then return either PC, or the PC after the prologue, whichever
1379 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1381 CORE_ADDR post_prologue_pc
1382 = skip_prologue_using_sal (gdbarch
, func_addr
);
1383 struct symtab
*s
= find_pc_symtab (func_addr
);
1385 if (post_prologue_pc
)
1387 = arm_skip_stack_protector (post_prologue_pc
, gdbarch
);
1390 /* GCC always emits a line note before the prologue and another
1391 one after, even if the two are at the same address or on the
1392 same line. Take advantage of this so that we do not need to
1393 know every instruction that might appear in the prologue. We
1394 will have producer information for most binaries; if it is
1395 missing (e.g. for -gstabs), assuming the GNU tools. */
1396 if (post_prologue_pc
1398 || s
->producer
== NULL
1399 || strncmp (s
->producer
, "GNU ", sizeof ("GNU ") - 1) == 0))
1400 return post_prologue_pc
;
1402 if (post_prologue_pc
!= 0)
1404 CORE_ADDR analyzed_limit
;
1406 /* For non-GCC compilers, make sure the entire line is an
1407 acceptable prologue; GDB will round this function's
1408 return value up to the end of the following line so we
1409 can not skip just part of a line (and we do not want to).
1411 RealView does not treat the prologue specially, but does
1412 associate prologue code with the opening brace; so this
1413 lets us skip the first line if we think it is the opening
1415 if (arm_pc_is_thumb (gdbarch
, func_addr
))
1416 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
1417 post_prologue_pc
, NULL
);
1419 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
1420 post_prologue_pc
, NULL
);
1422 if (analyzed_limit
!= post_prologue_pc
)
1425 return post_prologue_pc
;
1429 /* Can't determine prologue from the symbol table, need to examine
1432 /* Find an upper limit on the function prologue using the debug
1433 information. If the debug information could not be used to provide
1434 that bound, then use an arbitrary large number as the upper bound. */
1435 /* Like arm_scan_prologue, stop no later than pc + 64. */
1436 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1438 limit_pc
= pc
+ 64; /* Magic. */
1441 /* Check if this is Thumb code. */
1442 if (arm_pc_is_thumb (gdbarch
, pc
))
1443 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1445 for (skip_pc
= pc
; skip_pc
< limit_pc
; skip_pc
+= 4)
1447 inst
= read_memory_unsigned_integer (skip_pc
, 4, byte_order_for_code
);
1449 /* "mov ip, sp" is no longer a required part of the prologue. */
1450 if (inst
== 0xe1a0c00d) /* mov ip, sp */
1453 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
1456 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
1459 /* Some prologues begin with "str lr, [sp, #-4]!". */
1460 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
1463 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
1466 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
1469 /* Any insns after this point may float into the code, if it makes
1470 for better instruction scheduling, so we skip them only if we
1471 find them, but still consider the function to be frame-ful. */
1473 /* We may have either one sfmfd instruction here, or several stfe
1474 insns, depending on the version of floating point code we
1476 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
1479 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
1482 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
1485 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
1488 if ((inst
& 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */
1489 || (inst
& 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */
1490 || (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
1493 if ((inst
& 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */
1494 || (inst
& 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */
1495 || (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
1498 /* Un-recognized instruction; stop scanning. */
1502 return skip_pc
; /* End of prologue. */
1506 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1507 This function decodes a Thumb function prologue to determine:
1508 1) the size of the stack frame
1509 2) which registers are saved on it
1510 3) the offsets of saved regs
1511 4) the offset from the stack pointer to the frame pointer
1513 A typical Thumb function prologue would create this stack frame
1514 (offsets relative to FP)
1515 old SP -> 24 stack parameters
1518 R7 -> 0 local variables (16 bytes)
1519 SP -> -12 additional stack space (12 bytes)
1520 The frame size would thus be 36 bytes, and the frame offset would be
1521 12 bytes. The frame register is R7.
1523 The comments for thumb_skip_prolog() describe the algorithm we use
1524 to detect the end of the prolog. */
1528 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
1529 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
1531 CORE_ADDR prologue_start
;
1532 CORE_ADDR prologue_end
;
1533 CORE_ADDR current_pc
;
1535 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1538 /* See comment in arm_scan_prologue for an explanation of
1540 if (prologue_end
> prologue_start
+ 64)
1542 prologue_end
= prologue_start
+ 64;
1546 /* We're in the boondocks: we have no idea where the start of the
1550 prologue_end
= min (prologue_end
, prev_pc
);
1552 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1555 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
1558 arm_instruction_changes_pc (uint32_t this_instr
)
1560 if (bits (this_instr
, 28, 31) == INST_NV
)
1561 /* Unconditional instructions. */
1562 switch (bits (this_instr
, 24, 27))
1566 /* Branch with Link and change to Thumb. */
1571 /* Coprocessor register transfer. */
1572 if (bits (this_instr
, 12, 15) == 15)
1573 error (_("Invalid update to pc in instruction"));
1579 switch (bits (this_instr
, 25, 27))
1582 if (bits (this_instr
, 23, 24) == 2 && bit (this_instr
, 20) == 0)
1584 /* Multiplies and extra load/stores. */
1585 if (bit (this_instr
, 4) == 1 && bit (this_instr
, 7) == 1)
1586 /* Neither multiplies nor extension load/stores are allowed
1590 /* Otherwise, miscellaneous instructions. */
1592 /* BX <reg>, BXJ <reg>, BLX <reg> */
1593 if (bits (this_instr
, 4, 27) == 0x12fff1
1594 || bits (this_instr
, 4, 27) == 0x12fff2
1595 || bits (this_instr
, 4, 27) == 0x12fff3)
1598 /* Other miscellaneous instructions are unpredictable if they
1602 /* Data processing instruction. Fall through. */
1605 if (bits (this_instr
, 12, 15) == 15)
1612 /* Media instructions and architecturally undefined instructions. */
1613 if (bits (this_instr
, 25, 27) == 3 && bit (this_instr
, 4) == 1)
1617 if (bit (this_instr
, 20) == 0)
1621 if (bits (this_instr
, 12, 15) == ARM_PC_REGNUM
)
1627 /* Load/store multiple. */
1628 if (bit (this_instr
, 20) == 1 && bit (this_instr
, 15) == 1)
1634 /* Branch and branch with link. */
1639 /* Coprocessor transfers or SWIs can not affect PC. */
1643 internal_error (__FILE__
, __LINE__
, _("bad value in switch"));
1647 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1648 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1649 fill it in. Return the first address not recognized as a prologue
1652 We recognize all the instructions typically found in ARM prologues,
1653 plus harmless instructions which can be skipped (either for analysis
1654 purposes, or a more restrictive set that can be skipped when finding
1655 the end of the prologue). */
1658 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1659 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1660 struct arm_prologue_cache
*cache
)
1662 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1663 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1665 CORE_ADDR offset
, current_pc
;
1666 pv_t regs
[ARM_FPS_REGNUM
];
1667 struct pv_area
*stack
;
1668 struct cleanup
*back_to
;
1669 int framereg
, framesize
;
1670 CORE_ADDR unrecognized_pc
= 0;
1672 /* Search the prologue looking for instructions that set up the
1673 frame pointer, adjust the stack pointer, and save registers.
1675 Be careful, however, and if it doesn't look like a prologue,
1676 don't try to scan it. If, for instance, a frameless function
1677 begins with stmfd sp!, then we will tell ourselves there is
1678 a frame, which will confuse stack traceback, as well as "finish"
1679 and other operations that rely on a knowledge of the stack
1682 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1683 regs
[regno
] = pv_register (regno
, 0);
1684 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1685 back_to
= make_cleanup_free_pv_area (stack
);
1687 for (current_pc
= prologue_start
;
1688 current_pc
< prologue_end
;
1692 = read_memory_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1694 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1696 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1699 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1700 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1702 unsigned imm
= insn
& 0xff; /* immediate value */
1703 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1704 int rd
= bits (insn
, 12, 15);
1705 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1706 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1709 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1710 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1712 unsigned imm
= insn
& 0xff; /* immediate value */
1713 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1714 int rd
= bits (insn
, 12, 15);
1715 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1716 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1719 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd,
1722 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1724 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1725 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4,
1726 regs
[bits (insn
, 12, 15)]);
1729 else if ((insn
& 0xffff0000) == 0xe92d0000)
1730 /* stmfd sp!, {..., fp, ip, lr, pc}
1732 stmfd sp!, {a1, a2, a3, a4} */
1734 int mask
= insn
& 0xffff;
1736 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1739 /* Calculate offsets of saved registers. */
1740 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1741 if (mask
& (1 << regno
))
1744 = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1745 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1748 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1749 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1750 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1752 /* No need to add this to saved_regs -- it's just an arg reg. */
1755 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1756 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1757 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1759 /* No need to add this to saved_regs -- it's just an arg reg. */
1762 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn,
1764 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1766 /* No need to add this to saved_regs -- it's just arg regs. */
1769 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1771 unsigned imm
= insn
& 0xff; /* immediate value */
1772 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1773 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1774 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1776 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1778 unsigned imm
= insn
& 0xff; /* immediate value */
1779 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1780 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1781 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1783 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?,
1785 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1787 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1790 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1791 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1792 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1794 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1796 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1798 int n_saved_fp_regs
;
1799 unsigned int fp_start_reg
, fp_bound_reg
;
1801 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1804 if ((insn
& 0x800) == 0x800) /* N0 is set */
1806 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1807 n_saved_fp_regs
= 3;
1809 n_saved_fp_regs
= 1;
1813 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1814 n_saved_fp_regs
= 2;
1816 n_saved_fp_regs
= 4;
1819 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1820 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1821 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1823 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1824 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
1825 regs
[fp_start_reg
++]);
1828 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1830 /* Allow some special function calls when skipping the
1831 prologue; GCC generates these before storing arguments to
1833 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1835 if (skip_prologue_function (gdbarch
, dest
, 0))
1840 else if ((insn
& 0xf0000000) != 0xe0000000)
1841 break; /* Condition not true, exit early. */
1842 else if (arm_instruction_changes_pc (insn
))
1843 /* Don't scan past anything that might change control flow. */
1845 else if ((insn
& 0xfe500000) == 0xe8100000) /* ldm */
1847 /* Ignore block loads from the stack, potentially copying
1848 parameters from memory. */
1849 if (pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1854 else if ((insn
& 0xfc500000) == 0xe4100000)
1856 /* Similarly ignore single loads from the stack. */
1857 if (pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1862 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1863 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1864 register instead of the stack. */
1868 /* The optimizer might shove anything into the prologue,
1869 so we just skip what we don't recognize. */
1870 unrecognized_pc
= current_pc
;
1875 if (unrecognized_pc
== 0)
1876 unrecognized_pc
= current_pc
;
1878 /* The frame size is just the distance from the frame register
1879 to the original stack pointer. */
1880 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1882 /* Frame pointer is fp. */
1883 framereg
= ARM_FP_REGNUM
;
1884 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1886 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
1888 /* Try the stack pointer... this is a bit desperate. */
1889 framereg
= ARM_SP_REGNUM
;
1890 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1894 /* We're just out of luck. We don't know where the frame is. */
1901 cache
->framereg
= framereg
;
1902 cache
->framesize
= framesize
;
1904 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1905 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1906 cache
->saved_regs
[regno
].addr
= offset
;
1910 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1911 paddress (gdbarch
, unrecognized_pc
));
1913 do_cleanups (back_to
);
1914 return unrecognized_pc
;
1918 arm_scan_prologue (struct frame_info
*this_frame
,
1919 struct arm_prologue_cache
*cache
)
1921 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1922 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1924 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
1925 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1926 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1927 pv_t regs
[ARM_FPS_REGNUM
];
1928 struct pv_area
*stack
;
1929 struct cleanup
*back_to
;
1932 /* Assume there is no frame until proven otherwise. */
1933 cache
->framereg
= ARM_SP_REGNUM
;
1934 cache
->framesize
= 0;
1936 /* Check for Thumb prologue. */
1937 if (arm_frame_is_thumb (this_frame
))
1939 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1943 /* Find the function prologue. If we can't find the function in
1944 the symbol table, peek in the stack frame to find the PC. */
1945 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1948 /* One way to find the end of the prologue (which works well
1949 for unoptimized code) is to do the following:
1951 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1954 prologue_end = prev_pc;
1955 else if (sal.end < prologue_end)
1956 prologue_end = sal.end;
1958 This mechanism is very accurate so long as the optimizer
1959 doesn't move any instructions from the function body into the
1960 prologue. If this happens, sal.end will be the last
1961 instruction in the first hunk of prologue code just before
1962 the first instruction that the scheduler has moved from
1963 the body to the prologue.
1965 In order to make sure that we scan all of the prologue
1966 instructions, we use a slightly less accurate mechanism which
1967 may scan more than necessary. To help compensate for this
1968 lack of accuracy, the prologue scanning loop below contains
1969 several clauses which'll cause the loop to terminate early if
1970 an implausible prologue instruction is encountered.
1976 is a suitable endpoint since it accounts for the largest
1977 possible prologue plus up to five instructions inserted by
1980 if (prologue_end
> prologue_start
+ 64)
1982 prologue_end
= prologue_start
+ 64; /* See above. */
1987 /* We have no symbol information. Our only option is to assume this
1988 function has a standard stack frame and the normal frame register.
1989 Then, we can find the value of our frame pointer on entrance to
1990 the callee (or at the present moment if this is the innermost frame).
1991 The value stored there should be the address of the stmfd + 8. */
1992 CORE_ADDR frame_loc
;
1993 LONGEST return_value
;
1995 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
1996 if (!safe_read_memory_integer (frame_loc
, 4, byte_order
, &return_value
))
2000 prologue_start
= gdbarch_addr_bits_remove
2001 (gdbarch
, return_value
) - 8;
2002 prologue_end
= prologue_start
+ 64; /* See above. */
2006 if (prev_pc
< prologue_end
)
2007 prologue_end
= prev_pc
;
2009 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
2012 static struct arm_prologue_cache
*
2013 arm_make_prologue_cache (struct frame_info
*this_frame
)
2016 struct arm_prologue_cache
*cache
;
2017 CORE_ADDR unwound_fp
;
2019 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2020 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2022 arm_scan_prologue (this_frame
, cache
);
2024 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
2025 if (unwound_fp
== 0)
2028 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
2030 /* Calculate actual addresses of saved registers using offsets
2031 determined by arm_scan_prologue. */
2032 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
2033 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
2034 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
2039 /* Our frame ID for a normal frame is the current function's starting PC
2040 and the caller's SP when we were called. */
2043 arm_prologue_this_id (struct frame_info
*this_frame
,
2045 struct frame_id
*this_id
)
2047 struct arm_prologue_cache
*cache
;
2051 if (*this_cache
== NULL
)
2052 *this_cache
= arm_make_prologue_cache (this_frame
);
2053 cache
= *this_cache
;
2055 /* This is meant to halt the backtrace at "_start". */
2056 pc
= get_frame_pc (this_frame
);
2057 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
2060 /* If we've hit a wall, stop. */
2061 if (cache
->prev_sp
== 0)
2064 /* Use function start address as part of the frame ID. If we cannot
2065 identify the start address (due to missing symbol information),
2066 fall back to just using the current PC. */
2067 func
= get_frame_func (this_frame
);
2071 id
= frame_id_build (cache
->prev_sp
, func
);
2075 static struct value
*
2076 arm_prologue_prev_register (struct frame_info
*this_frame
,
2080 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2081 struct arm_prologue_cache
*cache
;
2083 if (*this_cache
== NULL
)
2084 *this_cache
= arm_make_prologue_cache (this_frame
);
2085 cache
= *this_cache
;
2087 /* If we are asked to unwind the PC, then we need to return the LR
2088 instead. The prologue may save PC, but it will point into this
2089 frame's prologue, not the next frame's resume location. Also
2090 strip the saved T bit. A valid LR may have the low bit set, but
2091 a valid PC never does. */
2092 if (prev_regnum
== ARM_PC_REGNUM
)
2096 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2097 return frame_unwind_got_constant (this_frame
, prev_regnum
,
2098 arm_addr_bits_remove (gdbarch
, lr
));
2101 /* SP is generally not saved to the stack, but this frame is
2102 identified by the next frame's stack pointer at the time of the call.
2103 The value was already reconstructed into PREV_SP. */
2104 if (prev_regnum
== ARM_SP_REGNUM
)
2105 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
2107 /* The CPSR may have been changed by the call instruction and by the
2108 called function. The only bit we can reconstruct is the T bit,
2109 by checking the low bit of LR as of the call. This is a reliable
2110 indicator of Thumb-ness except for some ARM v4T pre-interworking
2111 Thumb code, which could get away with a clear low bit as long as
2112 the called function did not use bx. Guess that all other
2113 bits are unchanged; the condition flags are presumably lost,
2114 but the processor status is likely valid. */
2115 if (prev_regnum
== ARM_PS_REGNUM
)
2118 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
2120 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
2121 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2122 if (IS_THUMB_ADDR (lr
))
2126 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
2129 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
2133 struct frame_unwind arm_prologue_unwind
= {
2135 arm_prologue_this_id
,
2136 arm_prologue_prev_register
,
2138 default_frame_sniffer
2141 /* Maintain a list of ARM exception table entries per objfile, similar to the
2142 list of mapping symbols. We only cache entries for standard ARM-defined
2143 personality routines; the cache will contain only the frame unwinding
2144 instructions associated with the entry (not the descriptors). */
2146 static const struct objfile_data
*arm_exidx_data_key
;
2148 struct arm_exidx_entry
2153 typedef struct arm_exidx_entry arm_exidx_entry_s
;
2154 DEF_VEC_O(arm_exidx_entry_s
);
2156 struct arm_exidx_data
2158 VEC(arm_exidx_entry_s
) **section_maps
;
2162 arm_exidx_data_free (struct objfile
*objfile
, void *arg
)
2164 struct arm_exidx_data
*data
= arg
;
2167 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
2168 VEC_free (arm_exidx_entry_s
, data
->section_maps
[i
]);
2172 arm_compare_exidx_entries (const struct arm_exidx_entry
*lhs
,
2173 const struct arm_exidx_entry
*rhs
)
2175 return lhs
->addr
< rhs
->addr
;
2178 static struct obj_section
*
2179 arm_obj_section_from_vma (struct objfile
*objfile
, bfd_vma vma
)
2181 struct obj_section
*osect
;
2183 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
2184 if (bfd_get_section_flags (objfile
->obfd
,
2185 osect
->the_bfd_section
) & SEC_ALLOC
)
2187 bfd_vma start
, size
;
2188 start
= bfd_get_section_vma (objfile
->obfd
, osect
->the_bfd_section
);
2189 size
= bfd_get_section_size (osect
->the_bfd_section
);
2191 if (start
<= vma
&& vma
< start
+ size
)
2198 /* Parse contents of exception table and exception index sections
2199 of OBJFILE, and fill in the exception table entry cache.
2201 For each entry that refers to a standard ARM-defined personality
2202 routine, extract the frame unwinding instructions (from either
2203 the index or the table section). The unwinding instructions
2205 - extracting them from the rest of the table data
2206 - converting to host endianness
2207 - appending the implicit 0xb0 ("Finish") code
2209 The extracted and normalized instructions are stored for later
2210 retrieval by the arm_find_exidx_entry routine. */
2213 arm_exidx_new_objfile (struct objfile
*objfile
)
2215 struct cleanup
*cleanups
= make_cleanup (null_cleanup
, NULL
);
2216 struct arm_exidx_data
*data
;
2217 asection
*exidx
, *extab
;
2218 bfd_vma exidx_vma
= 0, extab_vma
= 0;
2219 bfd_size_type exidx_size
= 0, extab_size
= 0;
2220 gdb_byte
*exidx_data
= NULL
, *extab_data
= NULL
;
2223 /* If we've already touched this file, do nothing. */
2224 if (!objfile
|| objfile_data (objfile
, arm_exidx_data_key
) != NULL
)
2227 /* Read contents of exception table and index. */
2228 exidx
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.exidx");
2231 exidx_vma
= bfd_section_vma (objfile
->obfd
, exidx
);
2232 exidx_size
= bfd_get_section_size (exidx
);
2233 exidx_data
= xmalloc (exidx_size
);
2234 make_cleanup (xfree
, exidx_data
);
2236 if (!bfd_get_section_contents (objfile
->obfd
, exidx
,
2237 exidx_data
, 0, exidx_size
))
2239 do_cleanups (cleanups
);
2244 extab
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.extab");
2247 extab_vma
= bfd_section_vma (objfile
->obfd
, extab
);
2248 extab_size
= bfd_get_section_size (extab
);
2249 extab_data
= xmalloc (extab_size
);
2250 make_cleanup (xfree
, extab_data
);
2252 if (!bfd_get_section_contents (objfile
->obfd
, extab
,
2253 extab_data
, 0, extab_size
))
2255 do_cleanups (cleanups
);
2260 /* Allocate exception table data structure. */
2261 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
, struct arm_exidx_data
);
2262 set_objfile_data (objfile
, arm_exidx_data_key
, data
);
2263 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2264 objfile
->obfd
->section_count
,
2265 VEC(arm_exidx_entry_s
) *);
2267 /* Fill in exception table. */
2268 for (i
= 0; i
< exidx_size
/ 8; i
++)
2270 struct arm_exidx_entry new_exidx_entry
;
2271 bfd_vma idx
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8);
2272 bfd_vma val
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8 + 4);
2273 bfd_vma addr
= 0, word
= 0;
2274 int n_bytes
= 0, n_words
= 0;
2275 struct obj_section
*sec
;
2276 gdb_byte
*entry
= NULL
;
2278 /* Extract address of start of function. */
2279 idx
= ((idx
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2280 idx
+= exidx_vma
+ i
* 8;
2282 /* Find section containing function and compute section offset. */
2283 sec
= arm_obj_section_from_vma (objfile
, idx
);
2286 idx
-= bfd_get_section_vma (objfile
->obfd
, sec
->the_bfd_section
);
2288 /* Determine address of exception table entry. */
2291 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2293 else if ((val
& 0xff000000) == 0x80000000)
2295 /* Exception table entry embedded in .ARM.exidx
2296 -- must be short form. */
2300 else if (!(val
& 0x80000000))
2302 /* Exception table entry in .ARM.extab. */
2303 addr
= ((val
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2304 addr
+= exidx_vma
+ i
* 8 + 4;
2306 if (addr
>= extab_vma
&& addr
+ 4 <= extab_vma
+ extab_size
)
2308 word
= bfd_h_get_32 (objfile
->obfd
,
2309 extab_data
+ addr
- extab_vma
);
2312 if ((word
& 0xff000000) == 0x80000000)
2317 else if ((word
& 0xff000000) == 0x81000000
2318 || (word
& 0xff000000) == 0x82000000)
2322 n_words
= ((word
>> 16) & 0xff);
2324 else if (!(word
& 0x80000000))
2327 struct obj_section
*pers_sec
;
2328 int gnu_personality
= 0;
2330 /* Custom personality routine. */
2331 pers
= ((word
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2332 pers
= UNMAKE_THUMB_ADDR (pers
+ addr
- 4);
2334 /* Check whether we've got one of the variants of the
2335 GNU personality routines. */
2336 pers_sec
= arm_obj_section_from_vma (objfile
, pers
);
2339 static const char *personality
[] =
2341 "__gcc_personality_v0",
2342 "__gxx_personality_v0",
2343 "__gcj_personality_v0",
2344 "__gnu_objc_personality_v0",
2348 CORE_ADDR pc
= pers
+ obj_section_offset (pers_sec
);
2351 for (k
= 0; personality
[k
]; k
++)
2352 if (lookup_minimal_symbol_by_pc_name
2353 (pc
, personality
[k
], objfile
))
2355 gnu_personality
= 1;
2360 /* If so, the next word contains a word count in the high
2361 byte, followed by the same unwind instructions as the
2362 pre-defined forms. */
2364 && addr
+ 4 <= extab_vma
+ extab_size
)
2366 word
= bfd_h_get_32 (objfile
->obfd
,
2367 extab_data
+ addr
- extab_vma
);
2370 n_words
= ((word
>> 24) & 0xff);
2376 /* Sanity check address. */
2378 if (addr
< extab_vma
|| addr
+ 4 * n_words
> extab_vma
+ extab_size
)
2379 n_words
= n_bytes
= 0;
2381 /* The unwind instructions reside in WORD (only the N_BYTES least
2382 significant bytes are valid), followed by N_WORDS words in the
2383 extab section starting at ADDR. */
2384 if (n_bytes
|| n_words
)
2386 gdb_byte
*p
= entry
= obstack_alloc (&objfile
->objfile_obstack
,
2387 n_bytes
+ n_words
* 4 + 1);
2390 *p
++ = (gdb_byte
) ((word
>> (8 * n_bytes
)) & 0xff);
2394 word
= bfd_h_get_32 (objfile
->obfd
,
2395 extab_data
+ addr
- extab_vma
);
2398 *p
++ = (gdb_byte
) ((word
>> 24) & 0xff);
2399 *p
++ = (gdb_byte
) ((word
>> 16) & 0xff);
2400 *p
++ = (gdb_byte
) ((word
>> 8) & 0xff);
2401 *p
++ = (gdb_byte
) (word
& 0xff);
2404 /* Implied "Finish" to terminate the list. */
2408 /* Push entry onto vector. They are guaranteed to always
2409 appear in order of increasing addresses. */
2410 new_exidx_entry
.addr
= idx
;
2411 new_exidx_entry
.entry
= entry
;
2412 VEC_safe_push (arm_exidx_entry_s
,
2413 data
->section_maps
[sec
->the_bfd_section
->index
],
2417 do_cleanups (cleanups
);
2420 /* Search for the exception table entry covering MEMADDR. If one is found,
2421 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2422 set *START to the start of the region covered by this entry. */
2425 arm_find_exidx_entry (CORE_ADDR memaddr
, CORE_ADDR
*start
)
2427 struct obj_section
*sec
;
2429 sec
= find_pc_section (memaddr
);
2432 struct arm_exidx_data
*data
;
2433 VEC(arm_exidx_entry_s
) *map
;
2434 struct arm_exidx_entry map_key
= { memaddr
- obj_section_addr (sec
), 0 };
2437 data
= objfile_data (sec
->objfile
, arm_exidx_data_key
);
2440 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
2441 if (!VEC_empty (arm_exidx_entry_s
, map
))
2443 struct arm_exidx_entry
*map_sym
;
2445 idx
= VEC_lower_bound (arm_exidx_entry_s
, map
, &map_key
,
2446 arm_compare_exidx_entries
);
2448 /* VEC_lower_bound finds the earliest ordered insertion
2449 point. If the following symbol starts at this exact
2450 address, we use that; otherwise, the preceding
2451 exception table entry covers this address. */
2452 if (idx
< VEC_length (arm_exidx_entry_s
, map
))
2454 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
);
2455 if (map_sym
->addr
== map_key
.addr
)
2458 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2459 return map_sym
->entry
;
2465 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
- 1);
2467 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2468 return map_sym
->entry
;
2477 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2478 instruction list from the ARM exception table entry ENTRY, allocate and
2479 return a prologue cache structure describing how to unwind this frame.
2481 Return NULL if the unwinding instruction list contains a "spare",
2482 "reserved" or "refuse to unwind" instruction as defined in section
2483 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2484 for the ARM Architecture" document. */
2486 static struct arm_prologue_cache
*
2487 arm_exidx_fill_cache (struct frame_info
*this_frame
, gdb_byte
*entry
)
2492 struct arm_prologue_cache
*cache
;
2493 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2494 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2500 /* Whenever we reload SP, we actually have to retrieve its
2501 actual value in the current frame. */
2504 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2506 int reg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2507 vsp
= get_frame_register_unsigned (this_frame
, reg
);
2511 CORE_ADDR addr
= cache
->saved_regs
[ARM_SP_REGNUM
].addr
;
2512 vsp
= get_frame_memory_unsigned (this_frame
, addr
, 4);
2518 /* Decode next unwind instruction. */
2521 if ((insn
& 0xc0) == 0)
2523 int offset
= insn
& 0x3f;
2524 vsp
+= (offset
<< 2) + 4;
2526 else if ((insn
& 0xc0) == 0x40)
2528 int offset
= insn
& 0x3f;
2529 vsp
-= (offset
<< 2) + 4;
2531 else if ((insn
& 0xf0) == 0x80)
2533 int mask
= ((insn
& 0xf) << 8) | *entry
++;
2536 /* The special case of an all-zero mask identifies
2537 "Refuse to unwind". We return NULL to fall back
2538 to the prologue analyzer. */
2542 /* Pop registers r4..r15 under mask. */
2543 for (i
= 0; i
< 12; i
++)
2544 if (mask
& (1 << i
))
2546 cache
->saved_regs
[4 + i
].addr
= vsp
;
2550 /* Special-case popping SP -- we need to reload vsp. */
2551 if (mask
& (1 << (ARM_SP_REGNUM
- 4)))
2554 else if ((insn
& 0xf0) == 0x90)
2556 int reg
= insn
& 0xf;
2558 /* Reserved cases. */
2559 if (reg
== ARM_SP_REGNUM
|| reg
== ARM_PC_REGNUM
)
2562 /* Set SP from another register and mark VSP for reload. */
2563 cache
->saved_regs
[ARM_SP_REGNUM
] = cache
->saved_regs
[reg
];
2566 else if ((insn
& 0xf0) == 0xa0)
2568 int count
= insn
& 0x7;
2569 int pop_lr
= (insn
& 0x8) != 0;
2572 /* Pop r4..r[4+count]. */
2573 for (i
= 0; i
<= count
; i
++)
2575 cache
->saved_regs
[4 + i
].addr
= vsp
;
2579 /* If indicated by flag, pop LR as well. */
2582 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= vsp
;
2586 else if (insn
== 0xb0)
2588 /* We could only have updated PC by popping into it; if so, it
2589 will show up as address. Otherwise, copy LR into PC. */
2590 if (!trad_frame_addr_p (cache
->saved_regs
, ARM_PC_REGNUM
))
2591 cache
->saved_regs
[ARM_PC_REGNUM
]
2592 = cache
->saved_regs
[ARM_LR_REGNUM
];
2597 else if (insn
== 0xb1)
2599 int mask
= *entry
++;
2602 /* All-zero mask and mask >= 16 is "spare". */
2603 if (mask
== 0 || mask
>= 16)
2606 /* Pop r0..r3 under mask. */
2607 for (i
= 0; i
< 4; i
++)
2608 if (mask
& (1 << i
))
2610 cache
->saved_regs
[i
].addr
= vsp
;
2614 else if (insn
== 0xb2)
2616 ULONGEST offset
= 0;
2621 offset
|= (*entry
& 0x7f) << shift
;
2624 while (*entry
++ & 0x80);
2626 vsp
+= 0x204 + (offset
<< 2);
2628 else if (insn
== 0xb3)
2630 int start
= *entry
>> 4;
2631 int count
= (*entry
++) & 0xf;
2634 /* Only registers D0..D15 are valid here. */
2635 if (start
+ count
>= 16)
2638 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2639 for (i
= 0; i
<= count
; i
++)
2641 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2645 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2648 else if ((insn
& 0xf8) == 0xb8)
2650 int count
= insn
& 0x7;
2653 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2654 for (i
= 0; i
<= count
; i
++)
2656 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2660 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2663 else if (insn
== 0xc6)
2665 int start
= *entry
>> 4;
2666 int count
= (*entry
++) & 0xf;
2669 /* Only registers WR0..WR15 are valid. */
2670 if (start
+ count
>= 16)
2673 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2674 for (i
= 0; i
<= count
; i
++)
2676 cache
->saved_regs
[ARM_WR0_REGNUM
+ start
+ i
].addr
= vsp
;
2680 else if (insn
== 0xc7)
2682 int mask
= *entry
++;
2685 /* All-zero mask and mask >= 16 is "spare". */
2686 if (mask
== 0 || mask
>= 16)
2689 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2690 for (i
= 0; i
< 4; i
++)
2691 if (mask
& (1 << i
))
2693 cache
->saved_regs
[ARM_WCGR0_REGNUM
+ i
].addr
= vsp
;
2697 else if ((insn
& 0xf8) == 0xc0)
2699 int count
= insn
& 0x7;
2702 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2703 for (i
= 0; i
<= count
; i
++)
2705 cache
->saved_regs
[ARM_WR0_REGNUM
+ 10 + i
].addr
= vsp
;
2709 else if (insn
== 0xc8)
2711 int start
= *entry
>> 4;
2712 int count
= (*entry
++) & 0xf;
2715 /* Only registers D0..D31 are valid. */
2716 if (start
+ count
>= 16)
2719 /* Pop VFP double-precision registers
2720 D[16+start]..D[16+start+count]. */
2721 for (i
= 0; i
<= count
; i
++)
2723 cache
->saved_regs
[ARM_D0_REGNUM
+ 16 + start
+ i
].addr
= vsp
;
2727 else if (insn
== 0xc9)
2729 int start
= *entry
>> 4;
2730 int count
= (*entry
++) & 0xf;
2733 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2734 for (i
= 0; i
<= count
; i
++)
2736 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2740 else if ((insn
& 0xf8) == 0xd0)
2742 int count
= insn
& 0x7;
2745 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2746 for (i
= 0; i
<= count
; i
++)
2748 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2754 /* Everything else is "spare". */
2759 /* If we restore SP from a register, assume this was the frame register.
2760 Otherwise just fall back to SP as frame register. */
2761 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2762 cache
->framereg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2764 cache
->framereg
= ARM_SP_REGNUM
;
2766 /* Determine offset to previous frame. */
2768 = vsp
- get_frame_register_unsigned (this_frame
, cache
->framereg
);
2770 /* We already got the previous SP. */
2771 cache
->prev_sp
= vsp
;
2776 /* Unwinding via ARM exception table entries. Note that the sniffer
2777 already computes a filled-in prologue cache, which is then used
2778 with the same arm_prologue_this_id and arm_prologue_prev_register
2779 routines also used for prologue-parsing based unwinding. */
2782 arm_exidx_unwind_sniffer (const struct frame_unwind
*self
,
2783 struct frame_info
*this_frame
,
2784 void **this_prologue_cache
)
2786 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2787 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2788 CORE_ADDR addr_in_block
, exidx_region
, func_start
;
2789 struct arm_prologue_cache
*cache
;
2792 /* See if we have an ARM exception table entry covering this address. */
2793 addr_in_block
= get_frame_address_in_block (this_frame
);
2794 entry
= arm_find_exidx_entry (addr_in_block
, &exidx_region
);
2798 /* The ARM exception table does not describe unwind information
2799 for arbitrary PC values, but is guaranteed to be correct only
2800 at call sites. We have to decide here whether we want to use
2801 ARM exception table information for this frame, or fall back
2802 to using prologue parsing. (Note that if we have DWARF CFI,
2803 this sniffer isn't even called -- CFI is always preferred.)
2805 Before we make this decision, however, we check whether we
2806 actually have *symbol* information for the current frame.
2807 If not, prologue parsing would not work anyway, so we might
2808 as well use the exception table and hope for the best. */
2809 if (find_pc_partial_function (addr_in_block
, NULL
, &func_start
, NULL
))
2813 /* If the next frame is "normal", we are at a call site in this
2814 frame, so exception information is guaranteed to be valid. */
2815 if (get_next_frame (this_frame
)
2816 && get_frame_type (get_next_frame (this_frame
)) == NORMAL_FRAME
)
2819 /* We also assume exception information is valid if we're currently
2820 blocked in a system call. The system library is supposed to
2821 ensure this, so that e.g. pthread cancellation works. */
2822 if (arm_frame_is_thumb (this_frame
))
2826 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 2, 2,
2827 byte_order_for_code
, &insn
)
2828 && (insn
& 0xff00) == 0xdf00 /* svc */)
2835 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 4, 4,
2836 byte_order_for_code
, &insn
)
2837 && (insn
& 0x0f000000) == 0x0f000000 /* svc */)
2841 /* Bail out if we don't know that exception information is valid. */
2845 /* The ARM exception index does not mark the *end* of the region
2846 covered by the entry, and some functions will not have any entry.
2847 To correctly recognize the end of the covered region, the linker
2848 should have inserted dummy records with a CANTUNWIND marker.
2850 Unfortunately, current versions of GNU ld do not reliably do
2851 this, and thus we may have found an incorrect entry above.
2852 As a (temporary) sanity check, we only use the entry if it
2853 lies *within* the bounds of the function. Note that this check
2854 might reject perfectly valid entries that just happen to cover
2855 multiple functions; therefore this check ought to be removed
2856 once the linker is fixed. */
2857 if (func_start
> exidx_region
)
2861 /* Decode the list of unwinding instructions into a prologue cache.
2862 Note that this may fail due to e.g. a "refuse to unwind" code. */
2863 cache
= arm_exidx_fill_cache (this_frame
, entry
);
2867 *this_prologue_cache
= cache
;
2871 struct frame_unwind arm_exidx_unwind
= {
2873 arm_prologue_this_id
,
2874 arm_prologue_prev_register
,
2876 arm_exidx_unwind_sniffer
2879 static struct arm_prologue_cache
*
2880 arm_make_stub_cache (struct frame_info
*this_frame
)
2882 struct arm_prologue_cache
*cache
;
2884 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2885 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2887 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2892 /* Our frame ID for a stub frame is the current SP and LR. */
2895 arm_stub_this_id (struct frame_info
*this_frame
,
2897 struct frame_id
*this_id
)
2899 struct arm_prologue_cache
*cache
;
2901 if (*this_cache
== NULL
)
2902 *this_cache
= arm_make_stub_cache (this_frame
);
2903 cache
= *this_cache
;
2905 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
2909 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
2910 struct frame_info
*this_frame
,
2911 void **this_prologue_cache
)
2913 CORE_ADDR addr_in_block
;
2916 addr_in_block
= get_frame_address_in_block (this_frame
);
2917 if (in_plt_section (addr_in_block
, NULL
)
2918 /* We also use the stub winder if the target memory is unreadable
2919 to avoid having the prologue unwinder trying to read it. */
2920 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2926 struct frame_unwind arm_stub_unwind
= {
2929 arm_prologue_prev_register
,
2931 arm_stub_unwind_sniffer
2935 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
2937 struct arm_prologue_cache
*cache
;
2939 if (*this_cache
== NULL
)
2940 *this_cache
= arm_make_prologue_cache (this_frame
);
2941 cache
= *this_cache
;
2943 return cache
->prev_sp
- cache
->framesize
;
2946 struct frame_base arm_normal_base
= {
2947 &arm_prologue_unwind
,
2948 arm_normal_frame_base
,
2949 arm_normal_frame_base
,
2950 arm_normal_frame_base
2953 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
2954 dummy frame. The frame ID's base needs to match the TOS value
2955 saved by save_dummy_frame_tos() and returned from
2956 arm_push_dummy_call, and the PC needs to match the dummy frame's
2959 static struct frame_id
2960 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2962 return frame_id_build (get_frame_register_unsigned (this_frame
,
2964 get_frame_pc (this_frame
));
2967 /* Given THIS_FRAME, find the previous frame's resume PC (which will
2968 be used to construct the previous frame's ID, after looking up the
2969 containing function). */
2972 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2975 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
2976 return arm_addr_bits_remove (gdbarch
, pc
);
2980 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2982 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2985 static struct value
*
2986 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2989 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
2991 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
2996 /* The PC is normally copied from the return column, which
2997 describes saves of LR. However, that version may have an
2998 extra bit set to indicate Thumb state. The bit is not
3000 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3001 return frame_unwind_got_constant (this_frame
, regnum
,
3002 arm_addr_bits_remove (gdbarch
, lr
));
3005 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3006 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
3007 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3008 if (IS_THUMB_ADDR (lr
))
3012 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
3015 internal_error (__FILE__
, __LINE__
,
3016 _("Unexpected register %d"), regnum
);
3021 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3022 struct dwarf2_frame_state_reg
*reg
,
3023 struct frame_info
*this_frame
)
3029 reg
->how
= DWARF2_FRAME_REG_FN
;
3030 reg
->loc
.fn
= arm_dwarf2_prev_register
;
3033 reg
->how
= DWARF2_FRAME_REG_CFA
;
3038 /* Return true if we are in the function's epilogue, i.e. after the
3039 instruction that destroyed the function's stack frame. */
3042 thumb_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3044 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3045 unsigned int insn
, insn2
;
3046 int found_return
= 0, found_stack_adjust
= 0;
3047 CORE_ADDR func_start
, func_end
;
3051 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3054 /* The epilogue is a sequence of instructions along the following lines:
3056 - add stack frame size to SP or FP
3057 - [if frame pointer used] restore SP from FP
3058 - restore registers from SP [may include PC]
3059 - a return-type instruction [if PC wasn't already restored]
3061 In a first pass, we scan forward from the current PC and verify the
3062 instructions we find as compatible with this sequence, ending in a
3065 However, this is not sufficient to distinguish indirect function calls
3066 within a function from indirect tail calls in the epilogue in some cases.
3067 Therefore, if we didn't already find any SP-changing instruction during
3068 forward scan, we add a backward scanning heuristic to ensure we actually
3069 are in the epilogue. */
3072 while (scan_pc
< func_end
&& !found_return
)
3074 if (target_read_memory (scan_pc
, buf
, 2))
3078 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3080 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3082 else if (insn
== 0x46f7) /* mov pc, lr */
3084 else if (insn
== 0x46bd) /* mov sp, r7 */
3085 found_stack_adjust
= 1;
3086 else if ((insn
& 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3087 found_stack_adjust
= 1;
3088 else if ((insn
& 0xfe00) == 0xbc00) /* pop <registers> */
3090 found_stack_adjust
= 1;
3091 if (insn
& 0x0100) /* <registers> include PC. */
3094 else if ((insn
& 0xe000) == 0xe000) /* 32-bit Thumb-2 instruction */
3096 if (target_read_memory (scan_pc
, buf
, 2))
3100 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3102 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3104 found_stack_adjust
= 1;
3105 if (insn2
& 0x8000) /* <registers> include PC. */
3108 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3109 && (insn2
& 0x0fff) == 0x0b04)
3111 found_stack_adjust
= 1;
3112 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
3115 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3116 && (insn2
& 0x0e00) == 0x0a00)
3117 found_stack_adjust
= 1;
3128 /* Since any instruction in the epilogue sequence, with the possible
3129 exception of return itself, updates the stack pointer, we need to
3130 scan backwards for at most one instruction. Try either a 16-bit or
3131 a 32-bit instruction. This is just a heuristic, so we do not worry
3132 too much about false positives. */
3134 if (!found_stack_adjust
)
3136 if (pc
- 4 < func_start
)
3138 if (target_read_memory (pc
- 4, buf
, 4))
3141 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3142 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
3144 if (insn2
== 0x46bd) /* mov sp, r7 */
3145 found_stack_adjust
= 1;
3146 else if ((insn2
& 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3147 found_stack_adjust
= 1;
3148 else if ((insn2
& 0xff00) == 0xbc00) /* pop <registers> without PC */
3149 found_stack_adjust
= 1;
3150 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3151 found_stack_adjust
= 1;
3152 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3153 && (insn2
& 0x0fff) == 0x0b04)
3154 found_stack_adjust
= 1;
3155 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3156 && (insn2
& 0x0e00) == 0x0a00)
3157 found_stack_adjust
= 1;
3160 return found_stack_adjust
;
3163 /* Return true if we are in the function's epilogue, i.e. after the
3164 instruction that destroyed the function's stack frame. */
3167 arm_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3169 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3171 int found_return
, found_stack_adjust
;
3172 CORE_ADDR func_start
, func_end
;
3174 if (arm_pc_is_thumb (gdbarch
, pc
))
3175 return thumb_in_function_epilogue_p (gdbarch
, pc
);
3177 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3180 /* We are in the epilogue if the previous instruction was a stack
3181 adjustment and the next instruction is a possible return (bx, mov
3182 pc, or pop). We could have to scan backwards to find the stack
3183 adjustment, or forwards to find the return, but this is a decent
3184 approximation. First scan forwards. */
3187 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3188 if (bits (insn
, 28, 31) != INST_NV
)
3190 if ((insn
& 0x0ffffff0) == 0x012fff10)
3193 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
3196 else if ((insn
& 0x0fff0000) == 0x08bd0000
3197 && (insn
& 0x0000c000) != 0)
3198 /* POP (LDMIA), including PC or LR. */
3205 /* Scan backwards. This is just a heuristic, so do not worry about
3206 false positives from mode changes. */
3208 if (pc
< func_start
+ 4)
3211 found_stack_adjust
= 0;
3212 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
3213 if (bits (insn
, 28, 31) != INST_NV
)
3215 if ((insn
& 0x0df0f000) == 0x0080d000)
3216 /* ADD SP (register or immediate). */
3217 found_stack_adjust
= 1;
3218 else if ((insn
& 0x0df0f000) == 0x0040d000)
3219 /* SUB SP (register or immediate). */
3220 found_stack_adjust
= 1;
3221 else if ((insn
& 0x0ffffff0) == 0x01a0d000)
3223 found_stack_adjust
= 1;
3224 else if ((insn
& 0x0fff0000) == 0x08bd0000)
3226 found_stack_adjust
= 1;
3229 if (found_stack_adjust
)
3236 /* When arguments must be pushed onto the stack, they go on in reverse
3237 order. The code below implements a FILO (stack) to do this. */
3242 struct stack_item
*prev
;
3246 static struct stack_item
*
3247 push_stack_item (struct stack_item
*prev
, const void *contents
, int len
)
3249 struct stack_item
*si
;
3250 si
= xmalloc (sizeof (struct stack_item
));
3251 si
->data
= xmalloc (len
);
3254 memcpy (si
->data
, contents
, len
);
3258 static struct stack_item
*
3259 pop_stack_item (struct stack_item
*si
)
3261 struct stack_item
*dead
= si
;
3269 /* Return the alignment (in bytes) of the given type. */
3272 arm_type_align (struct type
*t
)
3278 t
= check_typedef (t
);
3279 switch (TYPE_CODE (t
))
3282 /* Should never happen. */
3283 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
3287 case TYPE_CODE_ENUM
:
3291 case TYPE_CODE_RANGE
:
3292 case TYPE_CODE_BITSTRING
:
3294 case TYPE_CODE_CHAR
:
3295 case TYPE_CODE_BOOL
:
3296 return TYPE_LENGTH (t
);
3298 case TYPE_CODE_ARRAY
:
3299 case TYPE_CODE_COMPLEX
:
3300 /* TODO: What about vector types? */
3301 return arm_type_align (TYPE_TARGET_TYPE (t
));
3303 case TYPE_CODE_STRUCT
:
3304 case TYPE_CODE_UNION
:
3306 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
3308 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
3316 /* Possible base types for a candidate for passing and returning in
3319 enum arm_vfp_cprc_base_type
3328 /* The length of one element of base type B. */
3331 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
3335 case VFP_CPRC_SINGLE
:
3337 case VFP_CPRC_DOUBLE
:
3339 case VFP_CPRC_VEC64
:
3341 case VFP_CPRC_VEC128
:
3344 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3349 /* The character ('s', 'd' or 'q') for the type of VFP register used
3350 for passing base type B. */
3353 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
3357 case VFP_CPRC_SINGLE
:
3359 case VFP_CPRC_DOUBLE
:
3361 case VFP_CPRC_VEC64
:
3363 case VFP_CPRC_VEC128
:
3366 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3371 /* Determine whether T may be part of a candidate for passing and
3372 returning in VFP registers, ignoring the limit on the total number
3373 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3374 classification of the first valid component found; if it is not
3375 VFP_CPRC_UNKNOWN, all components must have the same classification
3376 as *BASE_TYPE. If it is found that T contains a type not permitted
3377 for passing and returning in VFP registers, a type differently
3378 classified from *BASE_TYPE, or two types differently classified
3379 from each other, return -1, otherwise return the total number of
3380 base-type elements found (possibly 0 in an empty structure or
3381 array). Vectors and complex types are not currently supported,
3382 matching the generic AAPCS support. */
3385 arm_vfp_cprc_sub_candidate (struct type
*t
,
3386 enum arm_vfp_cprc_base_type
*base_type
)
3388 t
= check_typedef (t
);
3389 switch (TYPE_CODE (t
))
3392 switch (TYPE_LENGTH (t
))
3395 if (*base_type
== VFP_CPRC_UNKNOWN
)
3396 *base_type
= VFP_CPRC_SINGLE
;
3397 else if (*base_type
!= VFP_CPRC_SINGLE
)
3402 if (*base_type
== VFP_CPRC_UNKNOWN
)
3403 *base_type
= VFP_CPRC_DOUBLE
;
3404 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3413 case TYPE_CODE_ARRAY
:
3417 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
), base_type
);
3420 if (TYPE_LENGTH (t
) == 0)
3422 gdb_assert (count
== 0);
3425 else if (count
== 0)
3427 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3428 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
3429 return TYPE_LENGTH (t
) / unitlen
;
3433 case TYPE_CODE_STRUCT
:
3438 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3440 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3442 if (sub_count
== -1)
3446 if (TYPE_LENGTH (t
) == 0)
3448 gdb_assert (count
== 0);
3451 else if (count
== 0)
3453 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3454 if (TYPE_LENGTH (t
) != unitlen
* count
)
3459 case TYPE_CODE_UNION
:
3464 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3466 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3468 if (sub_count
== -1)
3470 count
= (count
> sub_count
? count
: sub_count
);
3472 if (TYPE_LENGTH (t
) == 0)
3474 gdb_assert (count
== 0);
3477 else if (count
== 0)
3479 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3480 if (TYPE_LENGTH (t
) != unitlen
* count
)
3492 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3493 if passed to or returned from a non-variadic function with the VFP
3494 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3495 *BASE_TYPE to the base type for T and *COUNT to the number of
3496 elements of that base type before returning. */
3499 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
3502 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
3503 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
3504 if (c
<= 0 || c
> 4)
3511 /* Return 1 if the VFP ABI should be used for passing arguments to and
3512 returning values from a function of type FUNC_TYPE, 0
3516 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
3518 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3519 /* Variadic functions always use the base ABI. Assume that functions
3520 without debug info are not variadic. */
3521 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
3523 /* The VFP ABI is only supported as a variant of AAPCS. */
3524 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
3526 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
3529 /* We currently only support passing parameters in integer registers, which
3530 conforms with GCC's default model, and VFP argument passing following
3531 the VFP variant of AAPCS. Several other variants exist and
3532 we should probably support some of them based on the selected ABI. */
3535 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3536 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3537 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3538 CORE_ADDR struct_addr
)
3540 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3544 struct stack_item
*si
= NULL
;
3547 unsigned vfp_regs_free
= (1 << 16) - 1;
3549 /* Determine the type of this function and whether the VFP ABI
3551 ftype
= check_typedef (value_type (function
));
3552 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
3553 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
3554 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
3556 /* Set the return address. For the ARM, the return breakpoint is
3557 always at BP_ADDR. */
3558 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
3560 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
3562 /* Walk through the list of args and determine how large a temporary
3563 stack is required. Need to take care here as structs may be
3564 passed on the stack, and we have to to push them. */
3567 argreg
= ARM_A1_REGNUM
;
3570 /* The struct_return pointer occupies the first parameter
3571 passing register. */
3575 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
3576 gdbarch_register_name (gdbarch
, argreg
),
3577 paddress (gdbarch
, struct_addr
));
3578 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
3582 for (argnum
= 0; argnum
< nargs
; argnum
++)
3585 struct type
*arg_type
;
3586 struct type
*target_type
;
3587 enum type_code typecode
;
3588 const bfd_byte
*val
;
3590 enum arm_vfp_cprc_base_type vfp_base_type
;
3592 int may_use_core_reg
= 1;
3594 arg_type
= check_typedef (value_type (args
[argnum
]));
3595 len
= TYPE_LENGTH (arg_type
);
3596 target_type
= TYPE_TARGET_TYPE (arg_type
);
3597 typecode
= TYPE_CODE (arg_type
);
3598 val
= value_contents (args
[argnum
]);
3600 align
= arm_type_align (arg_type
);
3601 /* Round alignment up to a whole number of words. */
3602 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
3603 /* Different ABIs have different maximum alignments. */
3604 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
3606 /* The APCS ABI only requires word alignment. */
3607 align
= INT_REGISTER_SIZE
;
3611 /* The AAPCS requires at most doubleword alignment. */
3612 if (align
> INT_REGISTER_SIZE
* 2)
3613 align
= INT_REGISTER_SIZE
* 2;
3617 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
3625 /* Because this is a CPRC it cannot go in a core register or
3626 cause a core register to be skipped for alignment.
3627 Either it goes in VFP registers and the rest of this loop
3628 iteration is skipped for this argument, or it goes on the
3629 stack (and the stack alignment code is correct for this
3631 may_use_core_reg
= 0;
3633 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
3634 shift
= unit_length
/ 4;
3635 mask
= (1 << (shift
* vfp_base_count
)) - 1;
3636 for (regno
= 0; regno
< 16; regno
+= shift
)
3637 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
3646 vfp_regs_free
&= ~(mask
<< regno
);
3647 reg_scaled
= regno
/ shift
;
3648 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
3649 for (i
= 0; i
< vfp_base_count
; i
++)
3653 if (reg_char
== 'q')
3654 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
3655 val
+ i
* unit_length
);
3658 sprintf (name_buf
, "%c%d", reg_char
, reg_scaled
+ i
);
3659 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3661 regcache_cooked_write (regcache
, regnum
,
3662 val
+ i
* unit_length
);
3669 /* This CPRC could not go in VFP registers, so all VFP
3670 registers are now marked as used. */
3675 /* Push stack padding for dowubleword alignment. */
3676 if (nstack
& (align
- 1))
3678 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3679 nstack
+= INT_REGISTER_SIZE
;
3682 /* Doubleword aligned quantities must go in even register pairs. */
3683 if (may_use_core_reg
3684 && argreg
<= ARM_LAST_ARG_REGNUM
3685 && align
> INT_REGISTER_SIZE
3689 /* If the argument is a pointer to a function, and it is a
3690 Thumb function, create a LOCAL copy of the value and set
3691 the THUMB bit in it. */
3692 if (TYPE_CODE_PTR
== typecode
3693 && target_type
!= NULL
3694 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
3696 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
3697 if (arm_pc_is_thumb (gdbarch
, regval
))
3699 bfd_byte
*copy
= alloca (len
);
3700 store_unsigned_integer (copy
, len
, byte_order
,
3701 MAKE_THUMB_ADDR (regval
));
3706 /* Copy the argument to general registers or the stack in
3707 register-sized pieces. Large arguments are split between
3708 registers and stack. */
3711 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
3713 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
3715 /* The argument is being passed in a general purpose
3718 = extract_unsigned_integer (val
, partial_len
, byte_order
);
3719 if (byte_order
== BFD_ENDIAN_BIG
)
3720 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
3722 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
3724 gdbarch_register_name
3726 phex (regval
, INT_REGISTER_SIZE
));
3727 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3732 /* Push the arguments onto the stack. */
3734 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
3736 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3737 nstack
+= INT_REGISTER_SIZE
;
3744 /* If we have an odd number of words to push, then decrement the stack
3745 by one word now, so first stack argument will be dword aligned. */
3752 write_memory (sp
, si
->data
, si
->len
);
3753 si
= pop_stack_item (si
);
3756 /* Finally, update teh SP register. */
3757 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
3763 /* Always align the frame to an 8-byte boundary. This is required on
3764 some platforms and harmless on the rest. */
3767 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3769 /* Align the stack to eight bytes. */
3770 return sp
& ~ (CORE_ADDR
) 7;
3774 print_fpu_flags (int flags
)
3776 if (flags
& (1 << 0))
3777 fputs ("IVO ", stdout
);
3778 if (flags
& (1 << 1))
3779 fputs ("DVZ ", stdout
);
3780 if (flags
& (1 << 2))
3781 fputs ("OFL ", stdout
);
3782 if (flags
& (1 << 3))
3783 fputs ("UFL ", stdout
);
3784 if (flags
& (1 << 4))
3785 fputs ("INX ", stdout
);
3789 /* Print interesting information about the floating point processor
3790 (if present) or emulator. */
3792 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
3793 struct frame_info
*frame
, const char *args
)
3795 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
3798 type
= (status
>> 24) & 127;
3799 if (status
& (1 << 31))
3800 printf (_("Hardware FPU type %d\n"), type
);
3802 printf (_("Software FPU type %d\n"), type
);
3803 /* i18n: [floating point unit] mask */
3804 fputs (_("mask: "), stdout
);
3805 print_fpu_flags (status
>> 16);
3806 /* i18n: [floating point unit] flags */
3807 fputs (_("flags: "), stdout
);
3808 print_fpu_flags (status
);
3811 /* Construct the ARM extended floating point type. */
3812 static struct type
*
3813 arm_ext_type (struct gdbarch
*gdbarch
)
3815 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3817 if (!tdep
->arm_ext_type
)
3819 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
3820 floatformats_arm_ext
);
3822 return tdep
->arm_ext_type
;
3825 static struct type
*
3826 arm_neon_double_type (struct gdbarch
*gdbarch
)
3828 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3830 if (tdep
->neon_double_type
== NULL
)
3832 struct type
*t
, *elem
;
3834 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
3836 elem
= builtin_type (gdbarch
)->builtin_uint8
;
3837 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
3838 elem
= builtin_type (gdbarch
)->builtin_uint16
;
3839 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
3840 elem
= builtin_type (gdbarch
)->builtin_uint32
;
3841 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
3842 elem
= builtin_type (gdbarch
)->builtin_uint64
;
3843 append_composite_type_field (t
, "u64", elem
);
3844 elem
= builtin_type (gdbarch
)->builtin_float
;
3845 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
3846 elem
= builtin_type (gdbarch
)->builtin_double
;
3847 append_composite_type_field (t
, "f64", elem
);
3849 TYPE_VECTOR (t
) = 1;
3850 TYPE_NAME (t
) = "neon_d";
3851 tdep
->neon_double_type
= t
;
3854 return tdep
->neon_double_type
;
3857 /* FIXME: The vector types are not correctly ordered on big-endian
3858 targets. Just as s0 is the low bits of d0, d0[0] is also the low
3859 bits of d0 - regardless of what unit size is being held in d0. So
3860 the offset of the first uint8 in d0 is 7, but the offset of the
3861 first float is 4. This code works as-is for little-endian
3864 static struct type
*
3865 arm_neon_quad_type (struct gdbarch
*gdbarch
)
3867 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3869 if (tdep
->neon_quad_type
== NULL
)
3871 struct type
*t
, *elem
;
3873 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
3875 elem
= builtin_type (gdbarch
)->builtin_uint8
;
3876 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
3877 elem
= builtin_type (gdbarch
)->builtin_uint16
;
3878 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
3879 elem
= builtin_type (gdbarch
)->builtin_uint32
;
3880 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
3881 elem
= builtin_type (gdbarch
)->builtin_uint64
;
3882 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
3883 elem
= builtin_type (gdbarch
)->builtin_float
;
3884 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
3885 elem
= builtin_type (gdbarch
)->builtin_double
;
3886 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
3888 TYPE_VECTOR (t
) = 1;
3889 TYPE_NAME (t
) = "neon_q";
3890 tdep
->neon_quad_type
= t
;
3893 return tdep
->neon_quad_type
;
3896 /* Return the GDB type object for the "standard" data type of data in
3899 static struct type
*
3900 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
3902 int num_regs
= gdbarch_num_regs (gdbarch
);
3904 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
3905 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
3906 return builtin_type (gdbarch
)->builtin_float
;
3908 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
3909 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
3910 return arm_neon_quad_type (gdbarch
);
3912 /* If the target description has register information, we are only
3913 in this function so that we can override the types of
3914 double-precision registers for NEON. */
3915 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
3917 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
3919 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
3920 && TYPE_CODE (t
) == TYPE_CODE_FLT
3921 && gdbarch_tdep (gdbarch
)->have_neon
)
3922 return arm_neon_double_type (gdbarch
);
3927 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
3929 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
3930 return builtin_type (gdbarch
)->builtin_void
;
3932 return arm_ext_type (gdbarch
);
3934 else if (regnum
== ARM_SP_REGNUM
)
3935 return builtin_type (gdbarch
)->builtin_data_ptr
;
3936 else if (regnum
== ARM_PC_REGNUM
)
3937 return builtin_type (gdbarch
)->builtin_func_ptr
;
3938 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
3939 /* These registers are only supported on targets which supply
3940 an XML description. */
3941 return builtin_type (gdbarch
)->builtin_int0
;
3943 return builtin_type (gdbarch
)->builtin_uint32
;
3946 /* Map a DWARF register REGNUM onto the appropriate GDB register
3950 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
3952 /* Core integer regs. */
3953 if (reg
>= 0 && reg
<= 15)
3956 /* Legacy FPA encoding. These were once used in a way which
3957 overlapped with VFP register numbering, so their use is
3958 discouraged, but GDB doesn't support the ARM toolchain
3959 which used them for VFP. */
3960 if (reg
>= 16 && reg
<= 23)
3961 return ARM_F0_REGNUM
+ reg
- 16;
3963 /* New assignments for the FPA registers. */
3964 if (reg
>= 96 && reg
<= 103)
3965 return ARM_F0_REGNUM
+ reg
- 96;
3967 /* WMMX register assignments. */
3968 if (reg
>= 104 && reg
<= 111)
3969 return ARM_WCGR0_REGNUM
+ reg
- 104;
3971 if (reg
>= 112 && reg
<= 127)
3972 return ARM_WR0_REGNUM
+ reg
- 112;
3974 if (reg
>= 192 && reg
<= 199)
3975 return ARM_WC0_REGNUM
+ reg
- 192;
3977 /* VFP v2 registers. A double precision value is actually
3978 in d1 rather than s2, but the ABI only defines numbering
3979 for the single precision registers. This will "just work"
3980 in GDB for little endian targets (we'll read eight bytes,
3981 starting in s0 and then progressing to s1), but will be
3982 reversed on big endian targets with VFP. This won't
3983 be a problem for the new Neon quad registers; you're supposed
3984 to use DW_OP_piece for those. */
3985 if (reg
>= 64 && reg
<= 95)
3989 sprintf (name_buf
, "s%d", reg
- 64);
3990 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3994 /* VFP v3 / Neon registers. This range is also used for VFP v2
3995 registers, except that it now describes d0 instead of s0. */
3996 if (reg
>= 256 && reg
<= 287)
4000 sprintf (name_buf
, "d%d", reg
- 256);
4001 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4008 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4010 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
4013 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
4015 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
4016 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
4018 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
4019 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
4021 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
4022 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
4024 if (reg
< NUM_GREGS
)
4025 return SIM_ARM_R0_REGNUM
+ reg
;
4028 if (reg
< NUM_FREGS
)
4029 return SIM_ARM_FP0_REGNUM
+ reg
;
4032 if (reg
< NUM_SREGS
)
4033 return SIM_ARM_FPS_REGNUM
+ reg
;
4036 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
4039 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4040 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4041 It is thought that this is is the floating-point register format on
4042 little-endian systems. */
4045 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
4046 void *dbl
, int endianess
)
4050 if (endianess
== BFD_ENDIAN_BIG
)
4051 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
4053 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4055 floatformat_from_doublest (fmt
, &d
, dbl
);
4059 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
4064 floatformat_to_doublest (fmt
, ptr
, &d
);
4065 if (endianess
== BFD_ENDIAN_BIG
)
4066 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
4068 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4073 condition_true (unsigned long cond
, unsigned long status_reg
)
4075 if (cond
== INST_AL
|| cond
== INST_NV
)
4081 return ((status_reg
& FLAG_Z
) != 0);
4083 return ((status_reg
& FLAG_Z
) == 0);
4085 return ((status_reg
& FLAG_C
) != 0);
4087 return ((status_reg
& FLAG_C
) == 0);
4089 return ((status_reg
& FLAG_N
) != 0);
4091 return ((status_reg
& FLAG_N
) == 0);
4093 return ((status_reg
& FLAG_V
) != 0);
4095 return ((status_reg
& FLAG_V
) == 0);
4097 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
4099 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
4101 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
4103 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
4105 return (((status_reg
& FLAG_Z
) == 0)
4106 && (((status_reg
& FLAG_N
) == 0)
4107 == ((status_reg
& FLAG_V
) == 0)));
4109 return (((status_reg
& FLAG_Z
) != 0)
4110 || (((status_reg
& FLAG_N
) == 0)
4111 != ((status_reg
& FLAG_V
) == 0)));
4116 static unsigned long
4117 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
4118 unsigned long pc_val
, unsigned long status_reg
)
4120 unsigned long res
, shift
;
4121 int rm
= bits (inst
, 0, 3);
4122 unsigned long shifttype
= bits (inst
, 5, 6);
4126 int rs
= bits (inst
, 8, 11);
4127 shift
= (rs
== 15 ? pc_val
+ 8
4128 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
4131 shift
= bits (inst
, 7, 11);
4134 ? (pc_val
+ (bit (inst
, 4) ? 12 : 8))
4135 : get_frame_register_unsigned (frame
, rm
));
4140 res
= shift
>= 32 ? 0 : res
<< shift
;
4144 res
= shift
>= 32 ? 0 : res
>> shift
;
4150 res
= ((res
& 0x80000000L
)
4151 ? ~((~res
) >> shift
) : res
>> shift
);
4154 case 3: /* ROR/RRX */
4157 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
4159 res
= (res
>> shift
) | (res
<< (32 - shift
));
4163 return res
& 0xffffffff;
4166 /* Return number of 1-bits in VAL. */
4169 bitcount (unsigned long val
)
4172 for (nbits
= 0; val
!= 0; nbits
++)
4173 val
&= val
- 1; /* Delete rightmost 1-bit in val. */
4177 /* Return the size in bytes of the complete Thumb instruction whose
4178 first halfword is INST1. */
4181 thumb_insn_size (unsigned short inst1
)
4183 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
4190 thumb_advance_itstate (unsigned int itstate
)
4192 /* Preserve IT[7:5], the first three bits of the condition. Shift
4193 the upcoming condition flags left by one bit. */
4194 itstate
= (itstate
& 0xe0) | ((itstate
<< 1) & 0x1f);
4196 /* If we have finished the IT block, clear the state. */
4197 if ((itstate
& 0x0f) == 0)
4203 /* Find the next PC after the current instruction executes. In some
4204 cases we can not statically determine the answer (see the IT state
4205 handling in this function); in that case, a breakpoint may be
4206 inserted in addition to the returned PC, which will be used to set
4207 another breakpoint by our caller. */
4210 thumb_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
, int insert_bkpt
)
4212 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4213 struct address_space
*aspace
= get_frame_address_space (frame
);
4214 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4215 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4216 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
4217 unsigned short inst1
;
4218 CORE_ADDR nextpc
= pc
+ 2; /* Default is next instruction. */
4219 unsigned long offset
;
4220 ULONGEST status
, itstate
;
4222 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4223 pc_val
= MAKE_THUMB_ADDR (pc_val
);
4225 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
4227 /* Thumb-2 conditional execution support. There are eight bits in
4228 the CPSR which describe conditional execution state. Once
4229 reconstructed (they're in a funny order), the low five bits
4230 describe the low bit of the condition for each instruction and
4231 how many instructions remain. The high three bits describe the
4232 base condition. One of the low four bits will be set if an IT
4233 block is active. These bits read as zero on earlier
4235 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
4236 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
4238 /* If-Then handling. On GNU/Linux, where this routine is used, we
4239 use an undefined instruction as a breakpoint. Unlike BKPT, IT
4240 can disable execution of the undefined instruction. So we might
4241 miss the breakpoint if we set it on a skipped conditional
4242 instruction. Because conditional instructions can change the
4243 flags, affecting the execution of further instructions, we may
4244 need to set two breakpoints. */
4246 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
!= NULL
)
4248 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4250 /* An IT instruction. Because this instruction does not
4251 modify the flags, we can accurately predict the next
4252 executed instruction. */
4253 itstate
= inst1
& 0x00ff;
4254 pc
+= thumb_insn_size (inst1
);
4256 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
4258 inst1
= read_memory_unsigned_integer (pc
, 2,
4259 byte_order_for_code
);
4260 pc
+= thumb_insn_size (inst1
);
4261 itstate
= thumb_advance_itstate (itstate
);
4264 return MAKE_THUMB_ADDR (pc
);
4266 else if (itstate
!= 0)
4268 /* We are in a conditional block. Check the condition. */
4269 if (! condition_true (itstate
>> 4, status
))
4271 /* Advance to the next executed instruction. */
4272 pc
+= thumb_insn_size (inst1
);
4273 itstate
= thumb_advance_itstate (itstate
);
4275 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
4277 inst1
= read_memory_unsigned_integer (pc
, 2,
4278 byte_order_for_code
);
4279 pc
+= thumb_insn_size (inst1
);
4280 itstate
= thumb_advance_itstate (itstate
);
4283 return MAKE_THUMB_ADDR (pc
);
4285 else if ((itstate
& 0x0f) == 0x08)
4287 /* This is the last instruction of the conditional
4288 block, and it is executed. We can handle it normally
4289 because the following instruction is not conditional,
4290 and we must handle it normally because it is
4291 permitted to branch. Fall through. */
4297 /* There are conditional instructions after this one.
4298 If this instruction modifies the flags, then we can
4299 not predict what the next executed instruction will
4300 be. Fortunately, this instruction is architecturally
4301 forbidden to branch; we know it will fall through.
4302 Start by skipping past it. */
4303 pc
+= thumb_insn_size (inst1
);
4304 itstate
= thumb_advance_itstate (itstate
);
4306 /* Set a breakpoint on the following instruction. */
4307 gdb_assert ((itstate
& 0x0f) != 0);
4309 insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
4310 cond_negated
= (itstate
>> 4) & 1;
4312 /* Skip all following instructions with the same
4313 condition. If there is a later instruction in the IT
4314 block with the opposite condition, set the other
4315 breakpoint there. If not, then set a breakpoint on
4316 the instruction after the IT block. */
4319 inst1
= read_memory_unsigned_integer (pc
, 2,
4320 byte_order_for_code
);
4321 pc
+= thumb_insn_size (inst1
);
4322 itstate
= thumb_advance_itstate (itstate
);
4324 while (itstate
!= 0 && ((itstate
>> 4) & 1) == cond_negated
);
4326 return MAKE_THUMB_ADDR (pc
);
4330 else if (itstate
& 0x0f)
4332 /* We are in a conditional block. Check the condition. */
4333 int cond
= itstate
>> 4;
4335 if (! condition_true (cond
, status
))
4337 /* Advance to the next instruction. All the 32-bit
4338 instructions share a common prefix. */
4339 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
4340 return MAKE_THUMB_ADDR (pc
+ 4);
4342 return MAKE_THUMB_ADDR (pc
+ 2);
4345 /* Otherwise, handle the instruction normally. */
4348 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
4352 /* Fetch the saved PC from the stack. It's stored above
4353 all of the other registers. */
4354 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
4355 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
4356 nextpc
= read_memory_unsigned_integer (sp
+ offset
, 4, byte_order
);
4358 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
4360 unsigned long cond
= bits (inst1
, 8, 11);
4361 if (cond
== 0x0f) /* 0x0f = SWI */
4363 struct gdbarch_tdep
*tdep
;
4364 tdep
= gdbarch_tdep (gdbarch
);
4366 if (tdep
->syscall_next_pc
!= NULL
)
4367 nextpc
= tdep
->syscall_next_pc (frame
);
4370 else if (cond
!= 0x0f && condition_true (cond
, status
))
4371 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
4373 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
4375 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
4377 else if ((inst1
& 0xe000) == 0xe000) /* 32-bit instruction */
4379 unsigned short inst2
;
4380 inst2
= read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
4382 /* Default to the next instruction. */
4384 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4386 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
4388 /* Branches and miscellaneous control instructions. */
4390 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
4393 int j1
, j2
, imm1
, imm2
;
4395 imm1
= sbits (inst1
, 0, 10);
4396 imm2
= bits (inst2
, 0, 10);
4397 j1
= bit (inst2
, 13);
4398 j2
= bit (inst2
, 11);
4400 offset
= ((imm1
<< 12) + (imm2
<< 1));
4401 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
4403 nextpc
= pc_val
+ offset
;
4404 /* For BLX make sure to clear the low bits. */
4405 if (bit (inst2
, 12) == 0)
4406 nextpc
= nextpc
& 0xfffffffc;
4408 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
4410 /* SUBS PC, LR, #imm8. */
4411 nextpc
= get_frame_register_unsigned (frame
, ARM_LR_REGNUM
);
4412 nextpc
-= inst2
& 0x00ff;
4414 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
4416 /* Conditional branch. */
4417 if (condition_true (bits (inst1
, 6, 9), status
))
4419 int sign
, j1
, j2
, imm1
, imm2
;
4421 sign
= sbits (inst1
, 10, 10);
4422 imm1
= bits (inst1
, 0, 5);
4423 imm2
= bits (inst2
, 0, 10);
4424 j1
= bit (inst2
, 13);
4425 j2
= bit (inst2
, 11);
4427 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
4428 offset
+= (imm1
<< 12) + (imm2
<< 1);
4430 nextpc
= pc_val
+ offset
;
4434 else if ((inst1
& 0xfe50) == 0xe810)
4436 /* Load multiple or RFE. */
4437 int rn
, offset
, load_pc
= 1;
4439 rn
= bits (inst1
, 0, 3);
4440 if (bit (inst1
, 7) && !bit (inst1
, 8))
4443 if (!bit (inst2
, 15))
4445 offset
= bitcount (inst2
) * 4 - 4;
4447 else if (!bit (inst1
, 7) && bit (inst1
, 8))
4450 if (!bit (inst2
, 15))
4454 else if (bit (inst1
, 7) && bit (inst1
, 8))
4459 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
4469 CORE_ADDR addr
= get_frame_register_unsigned (frame
, rn
);
4470 nextpc
= get_frame_memory_unsigned (frame
, addr
+ offset
, 4);
4473 else if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
4475 /* MOV PC or MOVS PC. */
4476 nextpc
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4477 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4479 else if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
4483 int rn
, load_pc
= 1;
4485 rn
= bits (inst1
, 0, 3);
4486 base
= get_frame_register_unsigned (frame
, rn
);
4489 base
= (base
+ 4) & ~(CORE_ADDR
) 0x3;
4491 base
+= bits (inst2
, 0, 11);
4493 base
-= bits (inst2
, 0, 11);
4495 else if (bit (inst1
, 7))
4496 base
+= bits (inst2
, 0, 11);
4497 else if (bit (inst2
, 11))
4499 if (bit (inst2
, 10))
4502 base
+= bits (inst2
, 0, 7);
4504 base
-= bits (inst2
, 0, 7);
4507 else if ((inst2
& 0x0fc0) == 0x0000)
4509 int shift
= bits (inst2
, 4, 5), rm
= bits (inst2
, 0, 3);
4510 base
+= get_frame_register_unsigned (frame
, rm
) << shift
;
4517 nextpc
= get_frame_memory_unsigned (frame
, base
, 4);
4519 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
4522 CORE_ADDR tbl_reg
, table
, offset
, length
;
4524 tbl_reg
= bits (inst1
, 0, 3);
4525 if (tbl_reg
== 0x0f)
4526 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
4528 table
= get_frame_register_unsigned (frame
, tbl_reg
);
4530 offset
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4531 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 1);
4532 nextpc
= pc_val
+ length
;
4534 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
4537 CORE_ADDR tbl_reg
, table
, offset
, length
;
4539 tbl_reg
= bits (inst1
, 0, 3);
4540 if (tbl_reg
== 0x0f)
4541 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
4543 table
= get_frame_register_unsigned (frame
, tbl_reg
);
4545 offset
= 2 * get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4546 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 2);
4547 nextpc
= pc_val
+ length
;
4550 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
4552 if (bits (inst1
, 3, 6) == 0x0f)
4555 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
4557 else if ((inst1
& 0xff87) == 0x4687) /* mov pc, REG */
4559 if (bits (inst1
, 3, 6) == 0x0f)
4562 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
4564 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4566 else if ((inst1
& 0xf500) == 0xb100)
4569 int imm
= (bit (inst1
, 9) << 6) + (bits (inst1
, 3, 7) << 1);
4570 ULONGEST reg
= get_frame_register_unsigned (frame
, bits (inst1
, 0, 2));
4572 if (bit (inst1
, 11) && reg
!= 0)
4573 nextpc
= pc_val
+ imm
;
4574 else if (!bit (inst1
, 11) && reg
== 0)
4575 nextpc
= pc_val
+ imm
;
4580 /* Get the raw next address. PC is the current program counter, in
4581 FRAME. INSERT_BKPT should be TRUE if we want a breakpoint set on
4582 the alternative next instruction if there are two options.
4584 The value returned has the execution state of the next instruction
4585 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
4586 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
4590 arm_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
, int insert_bkpt
)
4592 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4593 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4594 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4595 unsigned long pc_val
;
4596 unsigned long this_instr
;
4597 unsigned long status
;
4600 if (arm_frame_is_thumb (frame
))
4601 return thumb_get_next_pc_raw (frame
, pc
, insert_bkpt
);
4603 pc_val
= (unsigned long) pc
;
4604 this_instr
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
4606 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
4607 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
4609 if (bits (this_instr
, 28, 31) == INST_NV
)
4610 switch (bits (this_instr
, 24, 27))
4615 /* Branch with Link and change to Thumb. */
4616 nextpc
= BranchDest (pc
, this_instr
);
4617 nextpc
|= bit (this_instr
, 24) << 1;
4618 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4624 /* Coprocessor register transfer. */
4625 if (bits (this_instr
, 12, 15) == 15)
4626 error (_("Invalid update to pc in instruction"));
4629 else if (condition_true (bits (this_instr
, 28, 31), status
))
4631 switch (bits (this_instr
, 24, 27))
4634 case 0x1: /* data processing */
4638 unsigned long operand1
, operand2
, result
= 0;
4642 if (bits (this_instr
, 12, 15) != 15)
4645 if (bits (this_instr
, 22, 25) == 0
4646 && bits (this_instr
, 4, 7) == 9) /* multiply */
4647 error (_("Invalid update to pc in instruction"));
4649 /* BX <reg>, BLX <reg> */
4650 if (bits (this_instr
, 4, 27) == 0x12fff1
4651 || bits (this_instr
, 4, 27) == 0x12fff3)
4653 rn
= bits (this_instr
, 0, 3);
4654 nextpc
= (rn
== 15) ? pc_val
+ 8
4655 : get_frame_register_unsigned (frame
, rn
);
4659 /* Multiply into PC. */
4660 c
= (status
& FLAG_C
) ? 1 : 0;
4661 rn
= bits (this_instr
, 16, 19);
4662 operand1
= (rn
== 15) ? pc_val
+ 8
4663 : get_frame_register_unsigned (frame
, rn
);
4665 if (bit (this_instr
, 25))
4667 unsigned long immval
= bits (this_instr
, 0, 7);
4668 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
4669 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
4672 else /* operand 2 is a shifted register. */
4673 operand2
= shifted_reg_val (frame
, this_instr
, c
,
4676 switch (bits (this_instr
, 21, 24))
4679 result
= operand1
& operand2
;
4683 result
= operand1
^ operand2
;
4687 result
= operand1
- operand2
;
4691 result
= operand2
- operand1
;
4695 result
= operand1
+ operand2
;
4699 result
= operand1
+ operand2
+ c
;
4703 result
= operand1
- operand2
+ c
;
4707 result
= operand2
- operand1
+ c
;
4713 case 0xb: /* tst, teq, cmp, cmn */
4714 result
= (unsigned long) nextpc
;
4718 result
= operand1
| operand2
;
4722 /* Always step into a function. */
4727 result
= operand1
& ~operand2
;
4735 /* In 26-bit APCS the bottom two bits of the result are
4736 ignored, and we always end up in ARM state. */
4738 nextpc
= arm_addr_bits_remove (gdbarch
, result
);
4746 case 0x5: /* data transfer */
4749 if (bit (this_instr
, 20))
4752 if (bits (this_instr
, 12, 15) == 15)
4758 if (bit (this_instr
, 22))
4759 error (_("Invalid update to pc in instruction"));
4761 /* byte write to PC */
4762 rn
= bits (this_instr
, 16, 19);
4763 base
= (rn
== 15) ? pc_val
+ 8
4764 : get_frame_register_unsigned (frame
, rn
);
4765 if (bit (this_instr
, 24))
4768 int c
= (status
& FLAG_C
) ? 1 : 0;
4769 unsigned long offset
=
4770 (bit (this_instr
, 25)
4771 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
4772 : bits (this_instr
, 0, 11));
4774 if (bit (this_instr
, 23))
4779 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
4786 case 0x9: /* block transfer */
4787 if (bit (this_instr
, 20))
4790 if (bit (this_instr
, 15))
4795 if (bit (this_instr
, 23))
4798 unsigned long reglist
= bits (this_instr
, 0, 14);
4799 offset
= bitcount (reglist
) * 4;
4800 if (bit (this_instr
, 24)) /* pre */
4803 else if (bit (this_instr
, 24))
4807 unsigned long rn_val
=
4808 get_frame_register_unsigned (frame
,
4809 bits (this_instr
, 16, 19));
4811 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
4819 case 0xb: /* branch & link */
4820 case 0xa: /* branch */
4822 nextpc
= BranchDest (pc
, this_instr
);
4828 case 0xe: /* coproc ops */
4832 struct gdbarch_tdep
*tdep
;
4833 tdep
= gdbarch_tdep (gdbarch
);
4835 if (tdep
->syscall_next_pc
!= NULL
)
4836 nextpc
= tdep
->syscall_next_pc (frame
);
4842 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
4851 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
4853 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4855 gdbarch_addr_bits_remove (gdbarch
,
4856 arm_get_next_pc_raw (frame
, pc
, TRUE
));
4858 error (_("Infinite loop detected"));
4862 /* single_step() is called just before we want to resume the inferior,
4863 if we want to single-step it but there is no hardware or kernel
4864 single-step support. We find the target of the coming instruction
4865 and breakpoint it. */
4868 arm_software_single_step (struct frame_info
*frame
)
4870 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4871 struct address_space
*aspace
= get_frame_address_space (frame
);
4873 /* NOTE: This may insert the wrong breakpoint instruction when
4874 single-stepping over a mode-changing instruction, if the
4875 CPSR heuristics are used. */
4877 CORE_ADDR next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
4878 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
4883 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
4884 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
4885 NULL if an error occurs. BUF is freed. */
4888 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
4889 int old_len
, int new_len
)
4891 gdb_byte
*new_buf
, *middle
;
4892 int bytes_to_read
= new_len
- old_len
;
4894 new_buf
= xmalloc (new_len
);
4895 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
4897 if (target_read_memory (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
4905 /* An IT block is at most the 2-byte IT instruction followed by
4906 four 4-byte instructions. The furthest back we must search to
4907 find an IT block that affects the current instruction is thus
4908 2 + 3 * 4 == 14 bytes. */
4909 #define MAX_IT_BLOCK_PREFIX 14
4911 /* Use a quick scan if there are more than this many bytes of
4913 #define IT_SCAN_THRESHOLD 32
4915 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
4916 A breakpoint in an IT block may not be hit, depending on the
4919 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
4923 CORE_ADDR boundary
, func_start
;
4924 int buf_len
, buf2_len
;
4925 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
4926 int i
, any
, last_it
, last_it_count
;
4928 /* If we are using BKPT breakpoints, none of this is necessary. */
4929 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
4932 /* ARM mode does not have this problem. */
4933 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
4936 /* We are setting a breakpoint in Thumb code that could potentially
4937 contain an IT block. The first step is to find how much Thumb
4938 code there is; we do not need to read outside of known Thumb
4940 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
4942 /* Thumb-2 code must have mapping symbols to have a chance. */
4945 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
4947 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
4948 && func_start
> boundary
)
4949 boundary
= func_start
;
4951 /* Search for a candidate IT instruction. We have to do some fancy
4952 footwork to distinguish a real IT instruction from the second
4953 half of a 32-bit instruction, but there is no need for that if
4954 there's no candidate. */
4955 buf_len
= min (bpaddr
- boundary
, MAX_IT_BLOCK_PREFIX
);
4957 /* No room for an IT instruction. */
4960 buf
= xmalloc (buf_len
);
4961 if (target_read_memory (bpaddr
- buf_len
, buf
, buf_len
) != 0)
4964 for (i
= 0; i
< buf_len
; i
+= 2)
4966 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4967 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4979 /* OK, the code bytes before this instruction contain at least one
4980 halfword which resembles an IT instruction. We know that it's
4981 Thumb code, but there are still two possibilities. Either the
4982 halfword really is an IT instruction, or it is the second half of
4983 a 32-bit Thumb instruction. The only way we can tell is to
4984 scan forwards from a known instruction boundary. */
4985 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
4989 /* There's a lot of code before this instruction. Start with an
4990 optimistic search; it's easy to recognize halfwords that can
4991 not be the start of a 32-bit instruction, and use that to
4992 lock on to the instruction boundaries. */
4993 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
4996 buf_len
= IT_SCAN_THRESHOLD
;
4999 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
5001 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5002 if (thumb_insn_size (inst1
) == 2)
5009 /* At this point, if DEFINITE, BUF[I] is the first place we
5010 are sure that we know the instruction boundaries, and it is far
5011 enough from BPADDR that we could not miss an IT instruction
5012 affecting BPADDR. If ! DEFINITE, give up - start from a
5016 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
,
5020 buf_len
= bpaddr
- boundary
;
5026 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
5029 buf_len
= bpaddr
- boundary
;
5033 /* Scan forwards. Find the last IT instruction before BPADDR. */
5038 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5040 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
5045 else if (inst1
& 0x0002)
5047 else if (inst1
& 0x0004)
5052 i
+= thumb_insn_size (inst1
);
5058 /* There wasn't really an IT instruction after all. */
5061 if (last_it_count
< 1)
5062 /* It was too far away. */
5065 /* This really is a trouble spot. Move the breakpoint to the IT
5067 return bpaddr
- buf_len
+ last_it
;
5070 /* ARM displaced stepping support.
5072 Generally ARM displaced stepping works as follows:
5074 1. When an instruction is to be single-stepped, it is first decoded by
5075 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
5076 Depending on the type of instruction, it is then copied to a scratch
5077 location, possibly in a modified form. The copy_* set of functions
5078 performs such modification, as necessary. A breakpoint is placed after
5079 the modified instruction in the scratch space to return control to GDB.
5080 Note in particular that instructions which modify the PC will no longer
5081 do so after modification.
5083 2. The instruction is single-stepped, by setting the PC to the scratch
5084 location address, and resuming. Control returns to GDB when the
5087 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
5088 function used for the current instruction. This function's job is to
5089 put the CPU/memory state back to what it would have been if the
5090 instruction had been executed unmodified in its original location. */
5092 /* NOP instruction (mov r0, r0). */
5093 #define ARM_NOP 0xe1a00000
5095 /* Helper for register reads for displaced stepping. In particular, this
5096 returns the PC as it would be seen by the instruction at its original
5100 displaced_read_reg (struct regcache
*regs
, CORE_ADDR from
, int regno
)
5106 if (debug_displaced
)
5107 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
5108 (unsigned long) from
+ 8);
5109 return (ULONGEST
) from
+ 8; /* Pipeline offset. */
5113 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
5114 if (debug_displaced
)
5115 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
5116 regno
, (unsigned long) ret
);
5122 displaced_in_arm_mode (struct regcache
*regs
)
5125 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
5127 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
5129 return (ps
& t_bit
) == 0;
5132 /* Write to the PC as from a branch instruction. */
5135 branch_write_pc (struct regcache
*regs
, ULONGEST val
)
5137 if (displaced_in_arm_mode (regs
))
5138 /* Note: If bits 0/1 are set, this branch would be unpredictable for
5139 architecture versions < 6. */
5140 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
5141 val
& ~(ULONGEST
) 0x3);
5143 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
5144 val
& ~(ULONGEST
) 0x1);
5147 /* Write to the PC as from a branch-exchange instruction. */
5150 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
5153 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
5155 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
5159 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
5160 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
5162 else if ((val
& 2) == 0)
5164 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
5165 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
5169 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
5170 mode, align dest to 4 bytes). */
5171 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
5172 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
5173 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
5177 /* Write to the PC as if from a load instruction. */
5180 load_write_pc (struct regcache
*regs
, ULONGEST val
)
5182 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
5183 bx_write_pc (regs
, val
);
5185 branch_write_pc (regs
, val
);
5188 /* Write to the PC as if from an ALU instruction. */
5191 alu_write_pc (struct regcache
*regs
, ULONGEST val
)
5193 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && displaced_in_arm_mode (regs
))
5194 bx_write_pc (regs
, val
);
5196 branch_write_pc (regs
, val
);
5199 /* Helper for writing to registers for displaced stepping. Writing to the PC
5200 has a varying effects depending on the instruction which does the write:
5201 this is controlled by the WRITE_PC argument. */
5204 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5205 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
5209 if (debug_displaced
)
5210 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
5211 (unsigned long) val
);
5214 case BRANCH_WRITE_PC
:
5215 branch_write_pc (regs
, val
);
5219 bx_write_pc (regs
, val
);
5223 load_write_pc (regs
, val
);
5227 alu_write_pc (regs
, val
);
5230 case CANNOT_WRITE_PC
:
5231 warning (_("Instruction wrote to PC in an unexpected way when "
5232 "single-stepping"));
5236 internal_error (__FILE__
, __LINE__
,
5237 _("Invalid argument to displaced_write_reg"));
5240 dsc
->wrote_to_pc
= 1;
5244 if (debug_displaced
)
5245 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
5246 regno
, (unsigned long) val
);
5247 regcache_cooked_write_unsigned (regs
, regno
, val
);
5251 /* This function is used to concisely determine if an instruction INSN
5252 references PC. Register fields of interest in INSN should have the
5253 corresponding fields of BITMASK set to 0b1111. The function
5254 returns return 1 if any of these fields in INSN reference the PC
5255 (also 0b1111, r15), else it returns 0. */
5258 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
5260 uint32_t lowbit
= 1;
5262 while (bitmask
!= 0)
5266 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
5272 mask
= lowbit
* 0xf;
5274 if ((insn
& mask
) == mask
)
5283 /* The simplest copy function. Many instructions have the same effect no
5284 matter what address they are executed at: in those cases, use this. */
5287 copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
5288 const char *iname
, struct displaced_step_closure
*dsc
)
5290 if (debug_displaced
)
5291 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
5292 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
5295 dsc
->modinsn
[0] = insn
;
5300 /* Preload instructions with immediate offset. */
5303 cleanup_preload (struct gdbarch
*gdbarch
,
5304 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5306 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5307 if (!dsc
->u
.preload
.immed
)
5308 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5312 copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5313 struct displaced_step_closure
*dsc
)
5315 unsigned int rn
= bits (insn
, 16, 19);
5317 CORE_ADDR from
= dsc
->insn_addr
;
5319 if (!insn_references_pc (insn
, 0x000f0000ul
))
5320 return copy_unmodified (gdbarch
, insn
, "preload", dsc
);
5322 if (debug_displaced
)
5323 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
5324 (unsigned long) insn
);
5326 /* Preload instructions:
5328 {pli/pld} [rn, #+/-imm]
5330 {pli/pld} [r0, #+/-imm]. */
5332 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
5333 rn_val
= displaced_read_reg (regs
, from
, rn
);
5334 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5336 dsc
->u
.preload
.immed
= 1;
5338 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
5340 dsc
->cleanup
= &cleanup_preload
;
5345 /* Preload instructions with register offset. */
5348 copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5349 struct regcache
*regs
,
5350 struct displaced_step_closure
*dsc
)
5352 unsigned int rn
= bits (insn
, 16, 19);
5353 unsigned int rm
= bits (insn
, 0, 3);
5354 ULONGEST rn_val
, rm_val
;
5355 CORE_ADDR from
= dsc
->insn_addr
;
5357 if (!insn_references_pc (insn
, 0x000f000ful
))
5358 return copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
5360 if (debug_displaced
)
5361 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
5362 (unsigned long) insn
);
5364 /* Preload register-offset instructions:
5366 {pli/pld} [rn, rm {, shift}]
5368 {pli/pld} [r0, r1 {, shift}]. */
5370 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
5371 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
5372 rn_val
= displaced_read_reg (regs
, from
, rn
);
5373 rm_val
= displaced_read_reg (regs
, from
, rm
);
5374 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5375 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
5377 dsc
->u
.preload
.immed
= 0;
5379 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
5381 dsc
->cleanup
= &cleanup_preload
;
5386 /* Copy/cleanup coprocessor load and store instructions. */
5389 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
5390 struct regcache
*regs
,
5391 struct displaced_step_closure
*dsc
)
5393 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
5395 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5397 if (dsc
->u
.ldst
.writeback
)
5398 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
5402 copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
5403 struct regcache
*regs
,
5404 struct displaced_step_closure
*dsc
)
5406 unsigned int rn
= bits (insn
, 16, 19);
5408 CORE_ADDR from
= dsc
->insn_addr
;
5410 if (!insn_references_pc (insn
, 0x000f0000ul
))
5411 return copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
5413 if (debug_displaced
)
5414 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
5415 "load/store insn %.8lx\n", (unsigned long) insn
);
5417 /* Coprocessor load/store instructions:
5419 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
5421 {stc/stc2} [r0, #+/-imm].
5423 ldc/ldc2 are handled identically. */
5425 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
5426 rn_val
= displaced_read_reg (regs
, from
, rn
);
5427 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5429 dsc
->u
.ldst
.writeback
= bit (insn
, 25);
5430 dsc
->u
.ldst
.rn
= rn
;
5432 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
5434 dsc
->cleanup
= &cleanup_copro_load_store
;
5439 /* Clean up branch instructions (actually perform the branch, by setting
5443 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5444 struct displaced_step_closure
*dsc
)
5446 ULONGEST from
= dsc
->insn_addr
;
5447 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
5448 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
5449 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
5450 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
5455 if (dsc
->u
.branch
.link
)
5457 ULONGEST pc
= displaced_read_reg (regs
, from
, 15);
5458 displaced_write_reg (regs
, dsc
, 14, pc
- 4, CANNOT_WRITE_PC
);
5461 displaced_write_reg (regs
, dsc
, 15, dsc
->u
.branch
.dest
, write_pc
);
5464 /* Copy B/BL/BLX instructions with immediate destinations. */
5467 copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
5468 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5470 unsigned int cond
= bits (insn
, 28, 31);
5471 int exchange
= (cond
== 0xf);
5472 int link
= exchange
|| bit (insn
, 24);
5473 CORE_ADDR from
= dsc
->insn_addr
;
5476 if (debug_displaced
)
5477 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
5478 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
5479 (unsigned long) insn
);
5481 /* Implement "BL<cond> <label>" as:
5483 Preparation: cond <- instruction condition
5484 Insn: mov r0, r0 (nop)
5485 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
5487 B<cond> similar, but don't set r14 in cleanup. */
5490 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
5491 then arrange the switch into Thumb mode. */
5492 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
5494 offset
= bits (insn
, 0, 23) << 2;
5496 if (bit (offset
, 25))
5497 offset
= offset
| ~0x3ffffff;
5499 dsc
->u
.branch
.cond
= cond
;
5500 dsc
->u
.branch
.link
= link
;
5501 dsc
->u
.branch
.exchange
= exchange
;
5502 dsc
->u
.branch
.dest
= from
+ 8 + offset
;
5504 dsc
->modinsn
[0] = ARM_NOP
;
5506 dsc
->cleanup
= &cleanup_branch
;
5511 /* Copy BX/BLX with register-specified destinations. */
5514 copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5515 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5517 unsigned int cond
= bits (insn
, 28, 31);
5520 int link
= bit (insn
, 5);
5521 unsigned int rm
= bits (insn
, 0, 3);
5522 CORE_ADDR from
= dsc
->insn_addr
;
5524 if (debug_displaced
)
5525 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s register insn "
5526 "%.8lx\n", (link
) ? "blx" : "bx",
5527 (unsigned long) insn
);
5529 /* Implement {BX,BLX}<cond> <reg>" as:
5531 Preparation: cond <- instruction condition
5532 Insn: mov r0, r0 (nop)
5533 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
5535 Don't set r14 in cleanup for BX. */
5537 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, from
, rm
);
5539 dsc
->u
.branch
.cond
= cond
;
5540 dsc
->u
.branch
.link
= link
;
5541 dsc
->u
.branch
.exchange
= 1;
5543 dsc
->modinsn
[0] = ARM_NOP
;
5545 dsc
->cleanup
= &cleanup_branch
;
5550 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
5553 cleanup_alu_imm (struct gdbarch
*gdbarch
,
5554 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5556 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
5557 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5558 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5559 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5563 copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5564 struct displaced_step_closure
*dsc
)
5566 unsigned int rn
= bits (insn
, 16, 19);
5567 unsigned int rd
= bits (insn
, 12, 15);
5568 unsigned int op
= bits (insn
, 21, 24);
5569 int is_mov
= (op
== 0xd);
5570 ULONGEST rd_val
, rn_val
;
5571 CORE_ADDR from
= dsc
->insn_addr
;
5573 if (!insn_references_pc (insn
, 0x000ff000ul
))
5574 return copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
5576 if (debug_displaced
)
5577 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
5578 "%.8lx\n", is_mov
? "move" : "ALU",
5579 (unsigned long) insn
);
5581 /* Instruction is of form:
5583 <op><cond> rd, [rn,] #imm
5587 Preparation: tmp1, tmp2 <- r0, r1;
5589 Insn: <op><cond> r0, r1, #imm
5590 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5593 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
5594 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
5595 rn_val
= displaced_read_reg (regs
, from
, rn
);
5596 rd_val
= displaced_read_reg (regs
, from
, rd
);
5597 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5598 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5602 dsc
->modinsn
[0] = insn
& 0xfff00fff;
5604 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
5606 dsc
->cleanup
= &cleanup_alu_imm
;
5611 /* Copy/cleanup arithmetic/logic insns with register RHS. */
5614 cleanup_alu_reg (struct gdbarch
*gdbarch
,
5615 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5620 rd_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
5622 for (i
= 0; i
< 3; i
++)
5623 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5625 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5629 copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5630 struct displaced_step_closure
*dsc
)
5632 unsigned int rn
= bits (insn
, 16, 19);
5633 unsigned int rm
= bits (insn
, 0, 3);
5634 unsigned int rd
= bits (insn
, 12, 15);
5635 unsigned int op
= bits (insn
, 21, 24);
5636 int is_mov
= (op
== 0xd);
5637 ULONGEST rd_val
, rn_val
, rm_val
;
5638 CORE_ADDR from
= dsc
->insn_addr
;
5640 if (!insn_references_pc (insn
, 0x000ff00ful
))
5641 return copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
5643 if (debug_displaced
)
5644 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
5645 is_mov
? "move" : "ALU", (unsigned long) insn
);
5647 /* Instruction is of form:
5649 <op><cond> rd, [rn,] rm [, <shift>]
5653 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
5654 r0, r1, r2 <- rd, rn, rm
5655 Insn: <op><cond> r0, r1, r2 [, <shift>]
5656 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
5659 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
5660 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
5661 dsc
->tmp
[2] = displaced_read_reg (regs
, from
, 2);
5662 rd_val
= displaced_read_reg (regs
, from
, rd
);
5663 rn_val
= displaced_read_reg (regs
, from
, rn
);
5664 rm_val
= displaced_read_reg (regs
, from
, rm
);
5665 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5666 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5667 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5671 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
5673 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
5675 dsc
->cleanup
= &cleanup_alu_reg
;
5680 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
5683 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
5684 struct regcache
*regs
,
5685 struct displaced_step_closure
*dsc
)
5687 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
5690 for (i
= 0; i
< 4; i
++)
5691 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5693 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5697 copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5698 struct regcache
*regs
,
5699 struct displaced_step_closure
*dsc
)
5701 unsigned int rn
= bits (insn
, 16, 19);
5702 unsigned int rm
= bits (insn
, 0, 3);
5703 unsigned int rd
= bits (insn
, 12, 15);
5704 unsigned int rs
= bits (insn
, 8, 11);
5705 unsigned int op
= bits (insn
, 21, 24);
5706 int is_mov
= (op
== 0xd), i
;
5707 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
5708 CORE_ADDR from
= dsc
->insn_addr
;
5710 if (!insn_references_pc (insn
, 0x000fff0ful
))
5711 return copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
5713 if (debug_displaced
)
5714 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
5715 "%.8lx\n", is_mov
? "move" : "ALU",
5716 (unsigned long) insn
);
5718 /* Instruction is of form:
5720 <op><cond> rd, [rn,] rm, <shift> rs
5724 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
5725 r0, r1, r2, r3 <- rd, rn, rm, rs
5726 Insn: <op><cond> r0, r1, r2, <shift> r3
5728 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
5732 for (i
= 0; i
< 4; i
++)
5733 dsc
->tmp
[i
] = displaced_read_reg (regs
, from
, i
);
5735 rd_val
= displaced_read_reg (regs
, from
, rd
);
5736 rn_val
= displaced_read_reg (regs
, from
, rn
);
5737 rm_val
= displaced_read_reg (regs
, from
, rm
);
5738 rs_val
= displaced_read_reg (regs
, from
, rs
);
5739 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5740 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5741 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5742 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
5746 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
5748 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
5750 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
5755 /* Clean up load instructions. */
5758 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5759 struct displaced_step_closure
*dsc
)
5761 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
5762 CORE_ADDR from
= dsc
->insn_addr
;
5764 rt_val
= displaced_read_reg (regs
, from
, 0);
5765 if (dsc
->u
.ldst
.xfersize
== 8)
5766 rt_val2
= displaced_read_reg (regs
, from
, 1);
5767 rn_val
= displaced_read_reg (regs
, from
, 2);
5769 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5770 if (dsc
->u
.ldst
.xfersize
> 4)
5771 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5772 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5773 if (!dsc
->u
.ldst
.immed
)
5774 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5776 /* Handle register writeback. */
5777 if (dsc
->u
.ldst
.writeback
)
5778 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5779 /* Put result in right place. */
5780 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
5781 if (dsc
->u
.ldst
.xfersize
== 8)
5782 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
5785 /* Clean up store instructions. */
5788 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5789 struct displaced_step_closure
*dsc
)
5791 CORE_ADDR from
= dsc
->insn_addr
;
5792 ULONGEST rn_val
= displaced_read_reg (regs
, from
, 2);
5794 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5795 if (dsc
->u
.ldst
.xfersize
> 4)
5796 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5797 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5798 if (!dsc
->u
.ldst
.immed
)
5799 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5800 if (!dsc
->u
.ldst
.restore_r4
)
5801 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
5804 if (dsc
->u
.ldst
.writeback
)
5805 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5808 /* Copy "extra" load/store instructions. These are halfword/doubleword
5809 transfers, which have a different encoding to byte/word transfers. */
5812 copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unpriveleged
,
5813 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5815 unsigned int op1
= bits (insn
, 20, 24);
5816 unsigned int op2
= bits (insn
, 5, 6);
5817 unsigned int rt
= bits (insn
, 12, 15);
5818 unsigned int rn
= bits (insn
, 16, 19);
5819 unsigned int rm
= bits (insn
, 0, 3);
5820 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
5821 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
5822 int immed
= (op1
& 0x4) != 0;
5824 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
5825 CORE_ADDR from
= dsc
->insn_addr
;
5827 if (!insn_references_pc (insn
, 0x000ff00ful
))
5828 return copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
5830 if (debug_displaced
)
5831 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
5832 "insn %.8lx\n", unpriveleged
? "unpriveleged " : "",
5833 (unsigned long) insn
);
5835 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
5838 internal_error (__FILE__
, __LINE__
,
5839 _("copy_extra_ld_st: instruction decode error"));
5841 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
5842 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
5843 dsc
->tmp
[2] = displaced_read_reg (regs
, from
, 2);
5845 dsc
->tmp
[3] = displaced_read_reg (regs
, from
, 3);
5847 rt_val
= displaced_read_reg (regs
, from
, rt
);
5848 if (bytesize
[opcode
] == 8)
5849 rt_val2
= displaced_read_reg (regs
, from
, rt
+ 1);
5850 rn_val
= displaced_read_reg (regs
, from
, rn
);
5852 rm_val
= displaced_read_reg (regs
, from
, rm
);
5854 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5855 if (bytesize
[opcode
] == 8)
5856 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
5857 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5859 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5862 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
5863 dsc
->u
.ldst
.rn
= rn
;
5864 dsc
->u
.ldst
.immed
= immed
;
5865 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
5866 dsc
->u
.ldst
.restore_r4
= 0;
5869 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
5871 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
5872 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5874 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
5876 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
5877 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5879 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
5884 /* Copy byte/word loads and stores. */
5887 copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
5888 struct regcache
*regs
,
5889 struct displaced_step_closure
*dsc
, int load
, int byte
,
5892 int immed
= !bit (insn
, 25);
5893 unsigned int rt
= bits (insn
, 12, 15);
5894 unsigned int rn
= bits (insn
, 16, 19);
5895 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
5896 ULONGEST rt_val
, rn_val
, rm_val
= 0;
5897 CORE_ADDR from
= dsc
->insn_addr
;
5899 if (!insn_references_pc (insn
, 0x000ff00ful
))
5900 return copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
5902 if (debug_displaced
)
5903 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s%s insn %.8lx\n",
5904 load
? (byte
? "ldrb" : "ldr")
5905 : (byte
? "strb" : "str"), usermode
? "t" : "",
5906 (unsigned long) insn
);
5908 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
5909 dsc
->tmp
[2] = displaced_read_reg (regs
, from
, 2);
5911 dsc
->tmp
[3] = displaced_read_reg (regs
, from
, 3);
5913 dsc
->tmp
[4] = displaced_read_reg (regs
, from
, 4);
5915 rt_val
= displaced_read_reg (regs
, from
, rt
);
5916 rn_val
= displaced_read_reg (regs
, from
, rn
);
5918 rm_val
= displaced_read_reg (regs
, from
, rm
);
5920 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5921 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5923 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5926 dsc
->u
.ldst
.xfersize
= byte
? 1 : 4;
5927 dsc
->u
.ldst
.rn
= rn
;
5928 dsc
->u
.ldst
.immed
= immed
;
5929 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
5931 /* To write PC we can do:
5933 scratch+0: str pc, temp (*temp = scratch + 8 + offset)
5934 scratch+4: ldr r4, temp
5935 scratch+8: sub r4, r4, pc (r4 = scratch + 8 + offset - scratch - 8 - 8)
5936 scratch+12: add r4, r4, #8 (r4 = offset)
5937 scratch+16: add r0, r0, r4
5938 scratch+20: str r0, [r2, #imm] (or str r0, [r2, r3])
5941 Otherwise we don't know what value to write for PC, since the offset is
5942 architecture-dependent (sometimes PC+8, sometimes PC+12). */
5944 if (load
|| rt
!= 15)
5946 dsc
->u
.ldst
.restore_r4
= 0;
5949 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
5951 {ldr,str}[b]<cond> r0, [r2, #imm]. */
5952 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5954 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
5956 {ldr,str}[b]<cond> r0, [r2, r3]. */
5957 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5961 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
5962 dsc
->u
.ldst
.restore_r4
= 1;
5964 dsc
->modinsn
[0] = 0xe58ff014; /* str pc, [pc, #20]. */
5965 dsc
->modinsn
[1] = 0xe59f4010; /* ldr r4, [pc, #16]. */
5966 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
5967 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
5968 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
5972 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
5974 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
5976 dsc
->modinsn
[6] = 0x0; /* breakpoint location. */
5977 dsc
->modinsn
[7] = 0x0; /* scratch space. */
5982 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5987 /* Cleanup LDM instructions with fully-populated register list. This is an
5988 unfortunate corner case: it's impossible to implement correctly by modifying
5989 the instruction. The issue is as follows: we have an instruction,
5993 which we must rewrite to avoid loading PC. A possible solution would be to
5994 do the load in two halves, something like (with suitable cleanup
5998 ldm[id][ab] r8!, {r0-r7}
6000 ldm[id][ab] r8, {r7-r14}
6003 but at present there's no suitable place for <temp>, since the scratch space
6004 is overwritten before the cleanup routine is called. For now, we simply
6005 emulate the instruction. */
6008 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6009 struct displaced_step_closure
*dsc
)
6011 ULONGEST from
= dsc
->insn_addr
;
6012 int inc
= dsc
->u
.block
.increment
;
6013 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
6014 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
6015 uint32_t regmask
= dsc
->u
.block
.regmask
;
6016 int regno
= inc
? 0 : 15;
6017 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
6018 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
6019 && (regmask
& 0x8000) != 0;
6020 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
6021 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
6022 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6027 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
6028 sensible we can do here. Complain loudly. */
6029 if (exception_return
)
6030 error (_("Cannot single-step exception return"));
6032 /* We don't handle any stores here for now. */
6033 gdb_assert (dsc
->u
.block
.load
!= 0);
6035 if (debug_displaced
)
6036 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
6037 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
6038 dsc
->u
.block
.increment
? "inc" : "dec",
6039 dsc
->u
.block
.before
? "before" : "after");
6046 while (regno
<= 15 && (regmask
& (1 << regno
)) == 0)
6049 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
6052 xfer_addr
+= bump_before
;
6054 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
6055 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
6057 xfer_addr
+= bump_after
;
6059 regmask
&= ~(1 << regno
);
6062 if (dsc
->u
.block
.writeback
)
6063 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
6067 /* Clean up an STM which included the PC in the register list. */
6070 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6071 struct displaced_step_closure
*dsc
)
6073 ULONGEST from
= dsc
->insn_addr
;
6074 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
6075 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
6076 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
6077 CORE_ADDR stm_insn_addr
;
6080 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6082 /* If condition code fails, there's nothing else to do. */
6083 if (!store_executed
)
6086 if (dsc
->u
.block
.increment
)
6088 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
6090 if (dsc
->u
.block
.before
)
6095 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
6097 if (dsc
->u
.block
.before
)
6101 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
6102 stm_insn_addr
= dsc
->scratch_base
;
6103 offset
= pc_val
- stm_insn_addr
;
6105 if (debug_displaced
)
6106 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
6107 "STM instruction\n", offset
);
6109 /* Rewrite the stored PC to the proper value for the non-displaced original
6111 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
6112 dsc
->insn_addr
+ offset
);
6115 /* Clean up an LDM which includes the PC in the register list. We clumped all
6116 the registers in the transferred list into a contiguous range r0...rX (to
6117 avoid loading PC directly and losing control of the debugged program), so we
6118 must undo that here. */
6121 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
6122 struct regcache
*regs
,
6123 struct displaced_step_closure
*dsc
)
6125 ULONGEST from
= dsc
->insn_addr
;
6126 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
6127 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
), i
;
6128 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= 15;
6129 unsigned int regs_loaded
= bitcount (mask
);
6130 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
6132 /* The method employed here will fail if the register list is fully populated
6133 (we need to avoid loading PC directly). */
6134 gdb_assert (num_to_shuffle
< 16);
6139 clobbered
= (1 << num_to_shuffle
) - 1;
6141 while (num_to_shuffle
> 0)
6143 if ((mask
& (1 << write_reg
)) != 0)
6145 unsigned int read_reg
= num_to_shuffle
- 1;
6147 if (read_reg
!= write_reg
)
6149 ULONGEST rval
= displaced_read_reg (regs
, from
, read_reg
);
6150 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
6151 if (debug_displaced
)
6152 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
6153 "loaded register r%d to r%d\n"), read_reg
,
6156 else if (debug_displaced
)
6157 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
6158 "r%d already in the right place\n"),
6161 clobbered
&= ~(1 << write_reg
);
6169 /* Restore any registers we scribbled over. */
6170 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
6172 if ((clobbered
& (1 << write_reg
)) != 0)
6174 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
6176 if (debug_displaced
)
6177 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
6178 "clobbered register r%d\n"), write_reg
);
6179 clobbered
&= ~(1 << write_reg
);
6183 /* Perform register writeback manually. */
6184 if (dsc
->u
.block
.writeback
)
6186 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
6188 if (dsc
->u
.block
.increment
)
6189 new_rn_val
+= regs_loaded
* 4;
6191 new_rn_val
-= regs_loaded
* 4;
6193 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
6198 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
6199 in user-level code (in particular exception return, ldm rn, {...pc}^). */
6202 copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
6203 struct displaced_step_closure
*dsc
)
6205 int load
= bit (insn
, 20);
6206 int user
= bit (insn
, 22);
6207 int increment
= bit (insn
, 23);
6208 int before
= bit (insn
, 24);
6209 int writeback
= bit (insn
, 21);
6210 int rn
= bits (insn
, 16, 19);
6211 CORE_ADDR from
= dsc
->insn_addr
;
6213 /* Block transfers which don't mention PC can be run directly
6215 if (rn
!= 15 && (insn
& 0x8000) == 0)
6216 return copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
6220 warning (_("displaced: Unpredictable LDM or STM with "
6221 "base register r15"));
6222 return copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
6225 if (debug_displaced
)
6226 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6227 "%.8lx\n", (unsigned long) insn
);
6229 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, from
, rn
);
6230 dsc
->u
.block
.rn
= rn
;
6232 dsc
->u
.block
.load
= load
;
6233 dsc
->u
.block
.user
= user
;
6234 dsc
->u
.block
.increment
= increment
;
6235 dsc
->u
.block
.before
= before
;
6236 dsc
->u
.block
.writeback
= writeback
;
6237 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
6239 dsc
->u
.block
.regmask
= insn
& 0xffff;
6243 if ((insn
& 0xffff) == 0xffff)
6245 /* LDM with a fully-populated register list. This case is
6246 particularly tricky. Implement for now by fully emulating the
6247 instruction (which might not behave perfectly in all cases, but
6248 these instructions should be rare enough for that not to matter
6250 dsc
->modinsn
[0] = ARM_NOP
;
6252 dsc
->cleanup
= &cleanup_block_load_all
;
6256 /* LDM of a list of registers which includes PC. Implement by
6257 rewriting the list of registers to be transferred into a
6258 contiguous chunk r0...rX before doing the transfer, then shuffling
6259 registers into the correct places in the cleanup routine. */
6260 unsigned int regmask
= insn
& 0xffff;
6261 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
6262 unsigned int to
= 0, from
= 0, i
, new_rn
;
6264 for (i
= 0; i
< num_in_list
; i
++)
6265 dsc
->tmp
[i
] = displaced_read_reg (regs
, from
, i
);
6267 /* Writeback makes things complicated. We need to avoid clobbering
6268 the base register with one of the registers in our modified
6269 register list, but just using a different register can't work in
6272 ldm r14!, {r0-r13,pc}
6274 which would need to be rewritten as:
6278 but that can't work, because there's no free register for N.
6280 Solve this by turning off the writeback bit, and emulating
6281 writeback manually in the cleanup routine. */
6286 new_regmask
= (1 << num_in_list
) - 1;
6288 if (debug_displaced
)
6289 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6290 "{..., pc}: original reg list %.4x, modified "
6291 "list %.4x\n"), rn
, writeback
? "!" : "",
6292 (int) insn
& 0xffff, new_regmask
);
6294 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
6296 dsc
->cleanup
= &cleanup_block_load_pc
;
6301 /* STM of a list of registers which includes PC. Run the instruction
6302 as-is, but out of line: this will store the wrong value for the PC,
6303 so we must manually fix up the memory in the cleanup routine.
6304 Doing things this way has the advantage that we can auto-detect
6305 the offset of the PC write (which is architecture-dependent) in
6306 the cleanup routine. */
6307 dsc
->modinsn
[0] = insn
;
6309 dsc
->cleanup
= &cleanup_block_store_pc
;
6315 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
6316 for Linux, where some SVC instructions must be treated specially. */
6319 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6320 struct displaced_step_closure
*dsc
)
6322 CORE_ADDR from
= dsc
->insn_addr
;
6323 CORE_ADDR resume_addr
= from
+ 4;
6325 if (debug_displaced
)
6326 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
6327 "%.8lx\n", (unsigned long) resume_addr
);
6329 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
6333 copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
6334 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6336 CORE_ADDR from
= dsc
->insn_addr
;
6338 /* Allow OS-specific code to override SVC handling. */
6339 if (dsc
->u
.svc
.copy_svc_os
)
6340 return dsc
->u
.svc
.copy_svc_os (gdbarch
, insn
, to
, regs
, dsc
);
6342 if (debug_displaced
)
6343 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
6344 (unsigned long) insn
);
6346 /* Preparation: none.
6347 Insn: unmodified svc.
6348 Cleanup: pc <- insn_addr + 4. */
6350 dsc
->modinsn
[0] = insn
;
6352 dsc
->cleanup
= &cleanup_svc
;
6353 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
6355 dsc
->wrote_to_pc
= 1;
6360 /* Copy undefined instructions. */
6363 copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
6364 struct displaced_step_closure
*dsc
)
6366 if (debug_displaced
)
6367 fprintf_unfiltered (gdb_stdlog
,
6368 "displaced: copying undefined insn %.8lx\n",
6369 (unsigned long) insn
);
6371 dsc
->modinsn
[0] = insn
;
6376 /* Copy unpredictable instructions. */
6379 copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
6380 struct displaced_step_closure
*dsc
)
6382 if (debug_displaced
)
6383 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
6384 "%.8lx\n", (unsigned long) insn
);
6386 dsc
->modinsn
[0] = insn
;
6391 /* The decode_* functions are instruction decoding helpers. They mostly follow
6392 the presentation in the ARM ARM. */
6395 decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
6396 struct regcache
*regs
,
6397 struct displaced_step_closure
*dsc
)
6399 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
6400 unsigned int rn
= bits (insn
, 16, 19);
6402 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
6403 return copy_unmodified (gdbarch
, insn
, "cps", dsc
);
6404 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
6405 return copy_unmodified (gdbarch
, insn
, "setend", dsc
);
6406 else if ((op1
& 0x60) == 0x20)
6407 return copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
6408 else if ((op1
& 0x71) == 0x40)
6409 return copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store", dsc
);
6410 else if ((op1
& 0x77) == 0x41)
6411 return copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6412 else if ((op1
& 0x77) == 0x45)
6413 return copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
6414 else if ((op1
& 0x77) == 0x51)
6417 return copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6419 return copy_unpred (gdbarch
, insn
, dsc
);
6421 else if ((op1
& 0x77) == 0x55)
6422 return copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6423 else if (op1
== 0x57)
6426 case 0x1: return copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
6427 case 0x4: return copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
6428 case 0x5: return copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
6429 case 0x6: return copy_unmodified (gdbarch
, insn
, "isb", dsc
);
6430 default: return copy_unpred (gdbarch
, insn
, dsc
);
6432 else if ((op1
& 0x63) == 0x43)
6433 return copy_unpred (gdbarch
, insn
, dsc
);
6434 else if ((op2
& 0x1) == 0x0)
6435 switch (op1
& ~0x80)
6438 return copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6440 return copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
6441 case 0x71: case 0x75:
6443 return copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
6444 case 0x63: case 0x67: case 0x73: case 0x77:
6445 return copy_unpred (gdbarch
, insn
, dsc
);
6447 return copy_undef (gdbarch
, insn
, dsc
);
6450 return copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
6454 decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
6455 struct regcache
*regs
,
6456 struct displaced_step_closure
*dsc
)
6458 if (bit (insn
, 27) == 0)
6459 return decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
6460 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
6461 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
6464 return copy_unmodified (gdbarch
, insn
, "srs", dsc
);
6467 return copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
6469 case 0x4: case 0x5: case 0x6: case 0x7:
6470 return copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6473 switch ((insn
& 0xe00000) >> 21)
6475 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
6477 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6480 return copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6483 return copy_undef (gdbarch
, insn
, dsc
);
6488 int rn_f
= (bits (insn
, 16, 19) == 0xf);
6489 switch ((insn
& 0xe00000) >> 21)
6492 /* ldc/ldc2 imm (undefined for rn == pc). */
6493 return rn_f
? copy_undef (gdbarch
, insn
, dsc
)
6494 : copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6497 return copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6499 case 0x4: case 0x5: case 0x6: case 0x7:
6500 /* ldc/ldc2 lit (undefined for rn != pc). */
6501 return rn_f
? copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
6502 : copy_undef (gdbarch
, insn
, dsc
);
6505 return copy_undef (gdbarch
, insn
, dsc
);
6510 return copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
6513 if (bits (insn
, 16, 19) == 0xf)
6515 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6517 return copy_undef (gdbarch
, insn
, dsc
);
6521 return copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6523 return copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6527 return copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6529 return copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6532 return copy_undef (gdbarch
, insn
, dsc
);
6536 /* Decode miscellaneous instructions in dp/misc encoding space. */
6539 decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
6540 struct regcache
*regs
,
6541 struct displaced_step_closure
*dsc
)
6543 unsigned int op2
= bits (insn
, 4, 6);
6544 unsigned int op
= bits (insn
, 21, 22);
6545 unsigned int op1
= bits (insn
, 16, 19);
6550 return copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
6553 if (op
== 0x1) /* bx. */
6554 return copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
6556 return copy_unmodified (gdbarch
, insn
, "clz", dsc
);
6558 return copy_undef (gdbarch
, insn
, dsc
);
6562 /* Not really supported. */
6563 return copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
6565 return copy_undef (gdbarch
, insn
, dsc
);
6569 return copy_bx_blx_reg (gdbarch
, insn
,
6570 regs
, dsc
); /* blx register. */
6572 return copy_undef (gdbarch
, insn
, dsc
);
6575 return copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
6579 return copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
6581 /* Not really supported. */
6582 return copy_unmodified (gdbarch
, insn
, "smc", dsc
);
6585 return copy_undef (gdbarch
, insn
, dsc
);
6590 decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
6591 struct displaced_step_closure
*dsc
)
6594 switch (bits (insn
, 20, 24))
6597 return copy_unmodified (gdbarch
, insn
, "movw", dsc
);
6600 return copy_unmodified (gdbarch
, insn
, "movt", dsc
);
6602 case 0x12: case 0x16:
6603 return copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
6606 return copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
6610 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
6612 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
6613 return copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
6614 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
6615 return copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
6616 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
6617 return decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
6618 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
6619 return copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
6620 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
6621 return copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
6622 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
6623 return copy_unmodified (gdbarch
, insn
, "synch", dsc
);
6624 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
6625 /* 2nd arg means "unpriveleged". */
6626 return copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
6630 /* Should be unreachable. */
6635 decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
6636 struct regcache
*regs
,
6637 struct displaced_step_closure
*dsc
)
6639 int a
= bit (insn
, 25), b
= bit (insn
, 4);
6640 uint32_t op1
= bits (insn
, 20, 24);
6641 int rn_f
= bits (insn
, 16, 19) == 0xf;
6643 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
6644 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
6645 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 0, 0);
6646 else if ((!a
&& (op1
& 0x17) == 0x02)
6647 || (a
&& (op1
& 0x17) == 0x02 && !b
))
6648 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 0, 1);
6649 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
6650 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
6651 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 0, 0);
6652 else if ((!a
&& (op1
& 0x17) == 0x03)
6653 || (a
&& (op1
& 0x17) == 0x03 && !b
))
6654 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 0, 1);
6655 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
6656 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
6657 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
6658 else if ((!a
&& (op1
& 0x17) == 0x06)
6659 || (a
&& (op1
& 0x17) == 0x06 && !b
))
6660 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
6661 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
6662 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
6663 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
6664 else if ((!a
&& (op1
& 0x17) == 0x07)
6665 || (a
&& (op1
& 0x17) == 0x07 && !b
))
6666 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
6668 /* Should be unreachable. */
6673 decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
6674 struct displaced_step_closure
*dsc
)
6676 switch (bits (insn
, 20, 24))
6678 case 0x00: case 0x01: case 0x02: case 0x03:
6679 return copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
6681 case 0x04: case 0x05: case 0x06: case 0x07:
6682 return copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
6684 case 0x08: case 0x09: case 0x0a: case 0x0b:
6685 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
6686 return copy_unmodified (gdbarch
, insn
,
6687 "decode/pack/unpack/saturate/reverse", dsc
);
6690 if (bits (insn
, 5, 7) == 0) /* op2. */
6692 if (bits (insn
, 12, 15) == 0xf)
6693 return copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
6695 return copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
6698 return copy_undef (gdbarch
, insn
, dsc
);
6700 case 0x1a: case 0x1b:
6701 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6702 return copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
6704 return copy_undef (gdbarch
, insn
, dsc
);
6706 case 0x1c: case 0x1d:
6707 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
6709 if (bits (insn
, 0, 3) == 0xf)
6710 return copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
6712 return copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
6715 return copy_undef (gdbarch
, insn
, dsc
);
6717 case 0x1e: case 0x1f:
6718 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6719 return copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
6721 return copy_undef (gdbarch
, insn
, dsc
);
6724 /* Should be unreachable. */
6729 decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, int32_t insn
,
6730 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6733 return copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6735 return copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
6739 decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
6740 struct regcache
*regs
,
6741 struct displaced_step_closure
*dsc
)
6743 unsigned int opcode
= bits (insn
, 20, 24);
6747 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
6748 return copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
6750 case 0x08: case 0x0a: case 0x0c: case 0x0e:
6751 case 0x12: case 0x16:
6752 return copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
6754 case 0x09: case 0x0b: case 0x0d: case 0x0f:
6755 case 0x13: case 0x17:
6756 return copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
6758 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6759 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6760 /* Note: no writeback for these instructions. Bit 25 will always be
6761 zero though (via caller), so the following works OK. */
6762 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6765 /* Should be unreachable. */
6770 decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
6771 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6773 unsigned int op1
= bits (insn
, 20, 25);
6774 int op
= bit (insn
, 4);
6775 unsigned int coproc
= bits (insn
, 8, 11);
6776 unsigned int rn
= bits (insn
, 16, 19);
6778 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
6779 return decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
6780 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
6781 && (coproc
& 0xe) != 0xa)
6783 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6784 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
6785 && (coproc
& 0xe) != 0xa)
6786 /* ldc/ldc2 imm/lit. */
6787 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6788 else if ((op1
& 0x3e) == 0x00)
6789 return copy_undef (gdbarch
, insn
, dsc
);
6790 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
6791 return copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
6792 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
6793 return copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6794 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
6795 return copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6796 else if ((op1
& 0x30) == 0x20 && !op
)
6798 if ((coproc
& 0xe) == 0xa)
6799 return copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
6801 return copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6803 else if ((op1
& 0x30) == 0x20 && op
)
6804 return copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
6805 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
6806 return copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6807 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
6808 return copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6809 else if ((op1
& 0x30) == 0x30)
6810 return copy_svc (gdbarch
, insn
, to
, regs
, dsc
);
6812 return copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
6816 arm_process_displaced_insn (struct gdbarch
*gdbarch
, uint32_t insn
,
6817 CORE_ADDR from
, CORE_ADDR to
,
6818 struct regcache
*regs
,
6819 struct displaced_step_closure
*dsc
)
6823 if (!displaced_in_arm_mode (regs
))
6824 error (_("Displaced stepping is only supported in ARM mode"));
6826 /* Most displaced instructions use a 1-instruction scratch space, so set this
6827 here and override below if/when necessary. */
6829 dsc
->insn_addr
= from
;
6830 dsc
->scratch_base
= to
;
6831 dsc
->cleanup
= NULL
;
6832 dsc
->wrote_to_pc
= 0;
6834 if ((insn
& 0xf0000000) == 0xf0000000)
6835 err
= decode_unconditional (gdbarch
, insn
, regs
, dsc
);
6836 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
6838 case 0x0: case 0x1: case 0x2: case 0x3:
6839 err
= decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
6842 case 0x4: case 0x5: case 0x6:
6843 err
= decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
6847 err
= decode_media (gdbarch
, insn
, dsc
);
6850 case 0x8: case 0x9: case 0xa: case 0xb:
6851 err
= decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
6854 case 0xc: case 0xd: case 0xe: case 0xf:
6855 err
= decode_svc_copro (gdbarch
, insn
, to
, regs
, dsc
);
6860 internal_error (__FILE__
, __LINE__
,
6861 _("arm_process_displaced_insn: Instruction decode error"));
6864 /* Actually set up the scratch space for a displaced instruction. */
6867 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
6868 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
6870 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6872 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
6874 /* Poke modified instruction(s). */
6875 for (i
= 0; i
< dsc
->numinsns
; i
++)
6877 if (debug_displaced
)
6878 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn %.8lx at "
6879 "%.8lx\n", (unsigned long) dsc
->modinsn
[i
],
6880 (unsigned long) to
+ i
* 4);
6881 write_memory_unsigned_integer (to
+ i
* 4, 4, byte_order_for_code
,
6885 /* Put breakpoint afterwards. */
6886 write_memory (to
+ dsc
->numinsns
* 4, tdep
->arm_breakpoint
,
6887 tdep
->arm_breakpoint_size
);
6889 if (debug_displaced
)
6890 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
6891 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
6894 /* Entry point for copying an instruction into scratch space for displaced
6897 struct displaced_step_closure
*
6898 arm_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
6899 CORE_ADDR from
, CORE_ADDR to
,
6900 struct regcache
*regs
)
6902 struct displaced_step_closure
*dsc
6903 = xmalloc (sizeof (struct displaced_step_closure
));
6904 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
6905 uint32_t insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
6907 if (debug_displaced
)
6908 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
6909 "at %.8lx\n", (unsigned long) insn
,
6910 (unsigned long) from
);
6912 arm_process_displaced_insn (gdbarch
, insn
, from
, to
, regs
, dsc
);
6913 arm_displaced_init_closure (gdbarch
, from
, to
, dsc
);
6918 /* Entry point for cleaning things up after a displaced instruction has been
6922 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
6923 struct displaced_step_closure
*dsc
,
6924 CORE_ADDR from
, CORE_ADDR to
,
6925 struct regcache
*regs
)
6928 dsc
->cleanup (gdbarch
, regs
, dsc
);
6930 if (!dsc
->wrote_to_pc
)
6931 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, dsc
->insn_addr
+ 4);
6934 #include "bfd-in2.h"
6935 #include "libcoff.h"
6938 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
6940 struct gdbarch
*gdbarch
= info
->application_data
;
6942 if (arm_pc_is_thumb (gdbarch
, memaddr
))
6944 static asymbol
*asym
;
6945 static combined_entry_type ce
;
6946 static struct coff_symbol_struct csym
;
6947 static struct bfd fake_bfd
;
6948 static bfd_target fake_target
;
6950 if (csym
.native
== NULL
)
6952 /* Create a fake symbol vector containing a Thumb symbol.
6953 This is solely so that the code in print_insn_little_arm()
6954 and print_insn_big_arm() in opcodes/arm-dis.c will detect
6955 the presence of a Thumb symbol and switch to decoding
6956 Thumb instructions. */
6958 fake_target
.flavour
= bfd_target_coff_flavour
;
6959 fake_bfd
.xvec
= &fake_target
;
6960 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
6962 csym
.symbol
.the_bfd
= &fake_bfd
;
6963 csym
.symbol
.name
= "fake";
6964 asym
= (asymbol
*) & csym
;
6967 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
6968 info
->symbols
= &asym
;
6971 info
->symbols
= NULL
;
6973 if (info
->endian
== BFD_ENDIAN_BIG
)
6974 return print_insn_big_arm (memaddr
, info
);
6976 return print_insn_little_arm (memaddr
, info
);
6979 /* The following define instruction sequences that will cause ARM
6980 cpu's to take an undefined instruction trap. These are used to
6981 signal a breakpoint to GDB.
6983 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
6984 modes. A different instruction is required for each mode. The ARM
6985 cpu's can also be big or little endian. Thus four different
6986 instructions are needed to support all cases.
6988 Note: ARMv4 defines several new instructions that will take the
6989 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
6990 not in fact add the new instructions. The new undefined
6991 instructions in ARMv4 are all instructions that had no defined
6992 behaviour in earlier chips. There is no guarantee that they will
6993 raise an exception, but may be treated as NOP's. In practice, it
6994 may only safe to rely on instructions matching:
6996 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
6997 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
6998 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
7000 Even this may only true if the condition predicate is true. The
7001 following use a condition predicate of ALWAYS so it is always TRUE.
7003 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
7004 and NetBSD all use a software interrupt rather than an undefined
7005 instruction to force a trap. This can be handled by by the
7006 abi-specific code during establishment of the gdbarch vector. */
7008 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
7009 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
7010 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
7011 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
7013 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
7014 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
7015 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
7016 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
7018 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
7019 the program counter value to determine whether a 16-bit or 32-bit
7020 breakpoint should be used. It returns a pointer to a string of
7021 bytes that encode a breakpoint instruction, stores the length of
7022 the string to *lenptr, and adjusts the program counter (if
7023 necessary) to point to the actual memory location where the
7024 breakpoint should be inserted. */
7026 static const unsigned char *
7027 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
7029 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7030 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7032 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
7034 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
7036 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
7037 check whether we are replacing a 32-bit instruction. */
7038 if (tdep
->thumb2_breakpoint
!= NULL
)
7041 if (target_read_memory (*pcptr
, buf
, 2) == 0)
7043 unsigned short inst1
;
7044 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
7045 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
7047 *lenptr
= tdep
->thumb2_breakpoint_size
;
7048 return tdep
->thumb2_breakpoint
;
7053 *lenptr
= tdep
->thumb_breakpoint_size
;
7054 return tdep
->thumb_breakpoint
;
7058 *lenptr
= tdep
->arm_breakpoint_size
;
7059 return tdep
->arm_breakpoint
;
7064 arm_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
7067 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7069 arm_breakpoint_from_pc (gdbarch
, pcptr
, kindptr
);
7071 if (arm_pc_is_thumb (gdbarch
, *pcptr
) && *kindptr
== 4)
7072 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
7073 that this is not confused with a 32-bit ARM breakpoint. */
7077 /* Extract from an array REGBUF containing the (raw) register state a
7078 function return value of type TYPE, and copy that, in virtual
7079 format, into VALBUF. */
7082 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
7085 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
7086 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7088 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
7090 switch (gdbarch_tdep (gdbarch
)->fp_model
)
7094 /* The value is in register F0 in internal format. We need to
7095 extract the raw value and then convert it to the desired
7097 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
7099 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
7100 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
7101 valbuf
, gdbarch_byte_order (gdbarch
));
7105 case ARM_FLOAT_SOFT_FPA
:
7106 case ARM_FLOAT_SOFT_VFP
:
7107 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7108 not using the VFP ABI code. */
7110 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
7111 if (TYPE_LENGTH (type
) > 4)
7112 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
7113 valbuf
+ INT_REGISTER_SIZE
);
7117 internal_error (__FILE__
, __LINE__
,
7118 _("arm_extract_return_value: "
7119 "Floating point model not supported"));
7123 else if (TYPE_CODE (type
) == TYPE_CODE_INT
7124 || TYPE_CODE (type
) == TYPE_CODE_CHAR
7125 || TYPE_CODE (type
) == TYPE_CODE_BOOL
7126 || TYPE_CODE (type
) == TYPE_CODE_PTR
7127 || TYPE_CODE (type
) == TYPE_CODE_REF
7128 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
7130 /* If the the type is a plain integer, then the access is
7131 straight-forward. Otherwise we have to play around a bit more. */
7132 int len
= TYPE_LENGTH (type
);
7133 int regno
= ARM_A1_REGNUM
;
7138 /* By using store_unsigned_integer we avoid having to do
7139 anything special for small big-endian values. */
7140 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
7141 store_unsigned_integer (valbuf
,
7142 (len
> INT_REGISTER_SIZE
7143 ? INT_REGISTER_SIZE
: len
),
7145 len
-= INT_REGISTER_SIZE
;
7146 valbuf
+= INT_REGISTER_SIZE
;
7151 /* For a structure or union the behaviour is as if the value had
7152 been stored to word-aligned memory and then loaded into
7153 registers with 32-bit load instruction(s). */
7154 int len
= TYPE_LENGTH (type
);
7155 int regno
= ARM_A1_REGNUM
;
7156 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
7160 regcache_cooked_read (regs
, regno
++, tmpbuf
);
7161 memcpy (valbuf
, tmpbuf
,
7162 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
7163 len
-= INT_REGISTER_SIZE
;
7164 valbuf
+= INT_REGISTER_SIZE
;
7170 /* Will a function return an aggregate type in memory or in a
7171 register? Return 0 if an aggregate type can be returned in a
7172 register, 1 if it must be returned in memory. */
7175 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
7178 enum type_code code
;
7180 CHECK_TYPEDEF (type
);
7182 /* In the ARM ABI, "integer" like aggregate types are returned in
7183 registers. For an aggregate type to be integer like, its size
7184 must be less than or equal to INT_REGISTER_SIZE and the
7185 offset of each addressable subfield must be zero. Note that bit
7186 fields are not addressable, and all addressable subfields of
7187 unions always start at offset zero.
7189 This function is based on the behaviour of GCC 2.95.1.
7190 See: gcc/arm.c: arm_return_in_memory() for details.
7192 Note: All versions of GCC before GCC 2.95.2 do not set up the
7193 parameters correctly for a function returning the following
7194 structure: struct { float f;}; This should be returned in memory,
7195 not a register. Richard Earnshaw sent me a patch, but I do not
7196 know of any way to detect if a function like the above has been
7197 compiled with the correct calling convention. */
7199 /* All aggregate types that won't fit in a register must be returned
7201 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
7206 /* The AAPCS says all aggregates not larger than a word are returned
7208 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
7211 /* The only aggregate types that can be returned in a register are
7212 structs and unions. Arrays must be returned in memory. */
7213 code
= TYPE_CODE (type
);
7214 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
7219 /* Assume all other aggregate types can be returned in a register.
7220 Run a check for structures, unions and arrays. */
7223 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
7226 /* Need to check if this struct/union is "integer" like. For
7227 this to be true, its size must be less than or equal to
7228 INT_REGISTER_SIZE and the offset of each addressable
7229 subfield must be zero. Note that bit fields are not
7230 addressable, and unions always start at offset zero. If any
7231 of the subfields is a floating point type, the struct/union
7232 cannot be an integer type. */
7234 /* For each field in the object, check:
7235 1) Is it FP? --> yes, nRc = 1;
7236 2) Is it addressable (bitpos != 0) and
7237 not packed (bitsize == 0)?
7241 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
7243 enum type_code field_type_code
;
7244 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
,
7247 /* Is it a floating point type field? */
7248 if (field_type_code
== TYPE_CODE_FLT
)
7254 /* If bitpos != 0, then we have to care about it. */
7255 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
7257 /* Bitfields are not addressable. If the field bitsize is
7258 zero, then the field is not packed. Hence it cannot be
7259 a bitfield or any other packed type. */
7260 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
7272 /* Write into appropriate registers a function return value of type
7273 TYPE, given in virtual format. */
7276 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
7277 const gdb_byte
*valbuf
)
7279 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
7280 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7282 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
7284 char buf
[MAX_REGISTER_SIZE
];
7286 switch (gdbarch_tdep (gdbarch
)->fp_model
)
7290 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
7291 gdbarch_byte_order (gdbarch
));
7292 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
7295 case ARM_FLOAT_SOFT_FPA
:
7296 case ARM_FLOAT_SOFT_VFP
:
7297 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7298 not using the VFP ABI code. */
7300 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
7301 if (TYPE_LENGTH (type
) > 4)
7302 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
7303 valbuf
+ INT_REGISTER_SIZE
);
7307 internal_error (__FILE__
, __LINE__
,
7308 _("arm_store_return_value: Floating "
7309 "point model not supported"));
7313 else if (TYPE_CODE (type
) == TYPE_CODE_INT
7314 || TYPE_CODE (type
) == TYPE_CODE_CHAR
7315 || TYPE_CODE (type
) == TYPE_CODE_BOOL
7316 || TYPE_CODE (type
) == TYPE_CODE_PTR
7317 || TYPE_CODE (type
) == TYPE_CODE_REF
7318 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
7320 if (TYPE_LENGTH (type
) <= 4)
7322 /* Values of one word or less are zero/sign-extended and
7324 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
7325 LONGEST val
= unpack_long (type
, valbuf
);
7327 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
7328 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
7332 /* Integral values greater than one word are stored in consecutive
7333 registers starting with r0. This will always be a multiple of
7334 the regiser size. */
7335 int len
= TYPE_LENGTH (type
);
7336 int regno
= ARM_A1_REGNUM
;
7340 regcache_cooked_write (regs
, regno
++, valbuf
);
7341 len
-= INT_REGISTER_SIZE
;
7342 valbuf
+= INT_REGISTER_SIZE
;
7348 /* For a structure or union the behaviour is as if the value had
7349 been stored to word-aligned memory and then loaded into
7350 registers with 32-bit load instruction(s). */
7351 int len
= TYPE_LENGTH (type
);
7352 int regno
= ARM_A1_REGNUM
;
7353 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
7357 memcpy (tmpbuf
, valbuf
,
7358 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
7359 regcache_cooked_write (regs
, regno
++, tmpbuf
);
7360 len
-= INT_REGISTER_SIZE
;
7361 valbuf
+= INT_REGISTER_SIZE
;
7367 /* Handle function return values. */
7369 static enum return_value_convention
7370 arm_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
7371 struct type
*valtype
, struct regcache
*regcache
,
7372 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
7374 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7375 enum arm_vfp_cprc_base_type vfp_base_type
;
7378 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
7379 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
7381 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
7382 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
7384 for (i
= 0; i
< vfp_base_count
; i
++)
7386 if (reg_char
== 'q')
7389 arm_neon_quad_write (gdbarch
, regcache
, i
,
7390 writebuf
+ i
* unit_length
);
7393 arm_neon_quad_read (gdbarch
, regcache
, i
,
7394 readbuf
+ i
* unit_length
);
7401 sprintf (name_buf
, "%c%d", reg_char
, i
);
7402 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
7405 regcache_cooked_write (regcache
, regnum
,
7406 writebuf
+ i
* unit_length
);
7408 regcache_cooked_read (regcache
, regnum
,
7409 readbuf
+ i
* unit_length
);
7412 return RETURN_VALUE_REGISTER_CONVENTION
;
7415 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
7416 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
7417 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
7419 if (tdep
->struct_return
== pcc_struct_return
7420 || arm_return_in_memory (gdbarch
, valtype
))
7421 return RETURN_VALUE_STRUCT_CONVENTION
;
7425 arm_store_return_value (valtype
, regcache
, writebuf
);
7428 arm_extract_return_value (valtype
, regcache
, readbuf
);
7430 return RETURN_VALUE_REGISTER_CONVENTION
;
7435 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
7437 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7438 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7439 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7441 char buf
[INT_REGISTER_SIZE
];
7443 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
7445 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
7449 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
7453 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
7454 return the target PC. Otherwise return 0. */
7457 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
7461 CORE_ADDR start_addr
;
7463 /* Find the starting address and name of the function containing the PC. */
7464 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7467 /* If PC is in a Thumb call or return stub, return the address of the
7468 target PC, which is in a register. The thunk functions are called
7469 _call_via_xx, where x is the register name. The possible names
7470 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
7471 functions, named __ARM_call_via_r[0-7]. */
7472 if (strncmp (name
, "_call_via_", 10) == 0
7473 || strncmp (name
, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0)
7475 /* Use the name suffix to determine which register contains the
7477 static char *table
[15] =
7478 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7479 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
7482 int offset
= strlen (name
) - 2;
7484 for (regno
= 0; regno
<= 14; regno
++)
7485 if (strcmp (&name
[offset
], table
[regno
]) == 0)
7486 return get_frame_register_unsigned (frame
, regno
);
7489 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
7490 non-interworking calls to foo. We could decode the stubs
7491 to find the target but it's easier to use the symbol table. */
7492 namelen
= strlen (name
);
7493 if (name
[0] == '_' && name
[1] == '_'
7494 && ((namelen
> 2 + strlen ("_from_thumb")
7495 && strncmp (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb",
7496 strlen ("_from_thumb")) == 0)
7497 || (namelen
> 2 + strlen ("_from_arm")
7498 && strncmp (name
+ namelen
- strlen ("_from_arm"), "_from_arm",
7499 strlen ("_from_arm")) == 0)))
7502 int target_len
= namelen
- 2;
7503 struct minimal_symbol
*minsym
;
7504 struct objfile
*objfile
;
7505 struct obj_section
*sec
;
7507 if (name
[namelen
- 1] == 'b')
7508 target_len
-= strlen ("_from_thumb");
7510 target_len
-= strlen ("_from_arm");
7512 target_name
= alloca (target_len
+ 1);
7513 memcpy (target_name
, name
+ 2, target_len
);
7514 target_name
[target_len
] = '\0';
7516 sec
= find_pc_section (pc
);
7517 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
7518 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
7520 return SYMBOL_VALUE_ADDRESS (minsym
);
7525 return 0; /* not a stub */
7529 set_arm_command (char *args
, int from_tty
)
7531 printf_unfiltered (_("\
7532 \"set arm\" must be followed by an apporpriate subcommand.\n"));
7533 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
7537 show_arm_command (char *args
, int from_tty
)
7539 cmd_show_list (showarmcmdlist
, from_tty
, "");
7543 arm_update_current_architecture (void)
7545 struct gdbarch_info info
;
7547 /* If the current architecture is not ARM, we have nothing to do. */
7548 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_arm
)
7551 /* Update the architecture. */
7552 gdbarch_info_init (&info
);
7554 if (!gdbarch_update_p (info
))
7555 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
7559 set_fp_model_sfunc (char *args
, int from_tty
,
7560 struct cmd_list_element
*c
)
7562 enum arm_float_model fp_model
;
7564 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
7565 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
7567 arm_fp_model
= fp_model
;
7571 if (fp_model
== ARM_FLOAT_LAST
)
7572 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
7575 arm_update_current_architecture ();
7579 show_fp_model (struct ui_file
*file
, int from_tty
,
7580 struct cmd_list_element
*c
, const char *value
)
7582 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
7584 if (arm_fp_model
== ARM_FLOAT_AUTO
7585 && gdbarch_bfd_arch_info (target_gdbarch
)->arch
== bfd_arch_arm
)
7586 fprintf_filtered (file
, _("\
7587 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
7588 fp_model_strings
[tdep
->fp_model
]);
7590 fprintf_filtered (file
, _("\
7591 The current ARM floating point model is \"%s\".\n"),
7592 fp_model_strings
[arm_fp_model
]);
7596 arm_set_abi (char *args
, int from_tty
,
7597 struct cmd_list_element
*c
)
7599 enum arm_abi_kind arm_abi
;
7601 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
7602 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
7604 arm_abi_global
= arm_abi
;
7608 if (arm_abi
== ARM_ABI_LAST
)
7609 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
7612 arm_update_current_architecture ();
7616 arm_show_abi (struct ui_file
*file
, int from_tty
,
7617 struct cmd_list_element
*c
, const char *value
)
7619 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
7621 if (arm_abi_global
== ARM_ABI_AUTO
7622 && gdbarch_bfd_arch_info (target_gdbarch
)->arch
== bfd_arch_arm
)
7623 fprintf_filtered (file
, _("\
7624 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
7625 arm_abi_strings
[tdep
->arm_abi
]);
7627 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
7632 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
7633 struct cmd_list_element
*c
, const char *value
)
7635 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
7637 fprintf_filtered (file
,
7638 _("The current execution mode assumed "
7639 "(when symbols are unavailable) is \"%s\".\n"),
7640 arm_fallback_mode_string
);
7644 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
7645 struct cmd_list_element
*c
, const char *value
)
7647 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
7649 fprintf_filtered (file
,
7650 _("The current execution mode assumed "
7651 "(even when symbols are available) is \"%s\".\n"),
7652 arm_force_mode_string
);
7655 /* If the user changes the register disassembly style used for info
7656 register and other commands, we have to also switch the style used
7657 in opcodes for disassembly output. This function is run in the "set
7658 arm disassembly" command, and does that. */
7661 set_disassembly_style_sfunc (char *args
, int from_tty
,
7662 struct cmd_list_element
*c
)
7664 set_disassembly_style ();
7667 /* Return the ARM register name corresponding to register I. */
7669 arm_register_name (struct gdbarch
*gdbarch
, int i
)
7671 const int num_regs
= gdbarch_num_regs (gdbarch
);
7673 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
7674 && i
>= num_regs
&& i
< num_regs
+ 32)
7676 static const char *const vfp_pseudo_names
[] = {
7677 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
7678 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
7679 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
7680 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
7683 return vfp_pseudo_names
[i
- num_regs
];
7686 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
7687 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
7689 static const char *const neon_pseudo_names
[] = {
7690 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
7691 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
7694 return neon_pseudo_names
[i
- num_regs
- 32];
7697 if (i
>= ARRAY_SIZE (arm_register_names
))
7698 /* These registers are only supported on targets which supply
7699 an XML description. */
7702 return arm_register_names
[i
];
7706 set_disassembly_style (void)
7710 /* Find the style that the user wants. */
7711 for (current
= 0; current
< num_disassembly_options
; current
++)
7712 if (disassembly_style
== valid_disassembly_styles
[current
])
7714 gdb_assert (current
< num_disassembly_options
);
7716 /* Synchronize the disassembler. */
7717 set_arm_regname_option (current
);
7720 /* Test whether the coff symbol specific value corresponds to a Thumb
7724 coff_sym_is_thumb (int val
)
7726 return (val
== C_THUMBEXT
7727 || val
== C_THUMBSTAT
7728 || val
== C_THUMBEXTFUNC
7729 || val
== C_THUMBSTATFUNC
7730 || val
== C_THUMBLABEL
);
7733 /* arm_coff_make_msymbol_special()
7734 arm_elf_make_msymbol_special()
7736 These functions test whether the COFF or ELF symbol corresponds to
7737 an address in thumb code, and set a "special" bit in a minimal
7738 symbol to indicate that it does. */
7741 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
7743 /* Thumb symbols are of type STT_LOPROC, (synonymous with
7745 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
7747 MSYMBOL_SET_SPECIAL (msym
);
7751 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
7753 if (coff_sym_is_thumb (val
))
7754 MSYMBOL_SET_SPECIAL (msym
);
7758 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
7760 struct arm_per_objfile
*data
= arg
;
7763 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
7764 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
7768 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
7771 const char *name
= bfd_asymbol_name (sym
);
7772 struct arm_per_objfile
*data
;
7773 VEC(arm_mapping_symbol_s
) **map_p
;
7774 struct arm_mapping_symbol new_map_sym
;
7776 gdb_assert (name
[0] == '$');
7777 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
7780 data
= objfile_data (objfile
, arm_objfile_data_key
);
7783 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
7784 struct arm_per_objfile
);
7785 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
7786 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
7787 objfile
->obfd
->section_count
,
7788 VEC(arm_mapping_symbol_s
) *);
7790 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
7792 new_map_sym
.value
= sym
->value
;
7793 new_map_sym
.type
= name
[1];
7795 /* Assume that most mapping symbols appear in order of increasing
7796 value. If they were randomly distributed, it would be faster to
7797 always push here and then sort at first use. */
7798 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
7800 struct arm_mapping_symbol
*prev_map_sym
;
7802 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
7803 if (prev_map_sym
->value
>= sym
->value
)
7806 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
7807 arm_compare_mapping_symbols
);
7808 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
7813 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
7817 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
7819 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
7820 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
7822 /* If necessary, set the T bit. */
7825 ULONGEST val
, t_bit
;
7826 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
7827 t_bit
= arm_psr_thumb_bit (gdbarch
);
7828 if (arm_pc_is_thumb (gdbarch
, pc
))
7829 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
7832 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
7837 /* Read the contents of a NEON quad register, by reading from two
7838 double registers. This is used to implement the quad pseudo
7839 registers, and for argument passing in case the quad registers are
7840 missing; vectors are passed in quad registers when using the VFP
7841 ABI, even if a NEON unit is not present. REGNUM is the index of
7842 the quad register, in [0, 15]. */
7845 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
7846 int regnum
, gdb_byte
*buf
)
7849 gdb_byte reg_buf
[8];
7850 int offset
, double_regnum
;
7852 sprintf (name_buf
, "d%d", regnum
<< 1);
7853 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
7856 /* d0 is always the least significant half of q0. */
7857 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
7862 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
7863 memcpy (buf
+ offset
, reg_buf
, 8);
7865 offset
= 8 - offset
;
7866 regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
7867 memcpy (buf
+ offset
, reg_buf
, 8);
7871 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
7872 int regnum
, gdb_byte
*buf
)
7874 const int num_regs
= gdbarch_num_regs (gdbarch
);
7876 gdb_byte reg_buf
[8];
7877 int offset
, double_regnum
;
7879 gdb_assert (regnum
>= num_regs
);
7882 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
7883 /* Quad-precision register. */
7884 arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
7887 /* Single-precision register. */
7888 gdb_assert (regnum
< 32);
7890 /* s0 is always the least significant half of d0. */
7891 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
7892 offset
= (regnum
& 1) ? 0 : 4;
7894 offset
= (regnum
& 1) ? 4 : 0;
7896 sprintf (name_buf
, "d%d", regnum
>> 1);
7897 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
7900 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
7901 memcpy (buf
, reg_buf
+ offset
, 4);
7905 /* Store the contents of BUF to a NEON quad register, by writing to
7906 two double registers. This is used to implement the quad pseudo
7907 registers, and for argument passing in case the quad registers are
7908 missing; vectors are passed in quad registers when using the VFP
7909 ABI, even if a NEON unit is not present. REGNUM is the index
7910 of the quad register, in [0, 15]. */
7913 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
7914 int regnum
, const gdb_byte
*buf
)
7917 gdb_byte reg_buf
[8];
7918 int offset
, double_regnum
;
7920 sprintf (name_buf
, "d%d", regnum
<< 1);
7921 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
7924 /* d0 is always the least significant half of q0. */
7925 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
7930 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
7931 offset
= 8 - offset
;
7932 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
7936 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
7937 int regnum
, const gdb_byte
*buf
)
7939 const int num_regs
= gdbarch_num_regs (gdbarch
);
7941 gdb_byte reg_buf
[8];
7942 int offset
, double_regnum
;
7944 gdb_assert (regnum
>= num_regs
);
7947 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
7948 /* Quad-precision register. */
7949 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
7952 /* Single-precision register. */
7953 gdb_assert (regnum
< 32);
7955 /* s0 is always the least significant half of d0. */
7956 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
7957 offset
= (regnum
& 1) ? 0 : 4;
7959 offset
= (regnum
& 1) ? 4 : 0;
7961 sprintf (name_buf
, "d%d", regnum
>> 1);
7962 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
7965 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
7966 memcpy (reg_buf
+ offset
, buf
, 4);
7967 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
7971 static struct value
*
7972 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
7974 const int *reg_p
= baton
;
7975 return value_of_register (*reg_p
, frame
);
7978 static enum gdb_osabi
7979 arm_elf_osabi_sniffer (bfd
*abfd
)
7981 unsigned int elfosabi
;
7982 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
7984 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
7986 if (elfosabi
== ELFOSABI_ARM
)
7987 /* GNU tools use this value. Check note sections in this case,
7989 bfd_map_over_sections (abfd
,
7990 generic_elf_osabi_sniff_abi_tag_sections
,
7993 /* Anything else will be handled by the generic ELF sniffer. */
7998 arm_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
7999 struct reggroup
*group
)
8001 /* FPS register's type is INT, but belongs to float_reggroup. Beside
8002 this, FPS register belongs to save_regroup, restore_reggroup, and
8003 all_reggroup, of course. */
8004 if (regnum
== ARM_FPS_REGNUM
)
8005 return (group
== float_reggroup
8006 || group
== save_reggroup
8007 || group
== restore_reggroup
8008 || group
== all_reggroup
);
8010 return default_register_reggroup_p (gdbarch
, regnum
, group
);
8014 /* Initialize the current architecture based on INFO. If possible,
8015 re-use an architecture from ARCHES, which is a list of
8016 architectures already created during this debugging session.
8018 Called e.g. at program startup, when reading a core file, and when
8019 reading a binary file. */
8021 static struct gdbarch
*
8022 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8024 struct gdbarch_tdep
*tdep
;
8025 struct gdbarch
*gdbarch
;
8026 struct gdbarch_list
*best_arch
;
8027 enum arm_abi_kind arm_abi
= arm_abi_global
;
8028 enum arm_float_model fp_model
= arm_fp_model
;
8029 struct tdesc_arch_data
*tdesc_data
= NULL
;
8031 int have_vfp_registers
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
8033 int have_fpa_registers
= 1;
8034 const struct target_desc
*tdesc
= info
.target_desc
;
8036 /* If we have an object to base this architecture on, try to determine
8039 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
8041 int ei_osabi
, e_flags
;
8043 switch (bfd_get_flavour (info
.abfd
))
8045 case bfd_target_aout_flavour
:
8046 /* Assume it's an old APCS-style ABI. */
8047 arm_abi
= ARM_ABI_APCS
;
8050 case bfd_target_coff_flavour
:
8051 /* Assume it's an old APCS-style ABI. */
8053 arm_abi
= ARM_ABI_APCS
;
8056 case bfd_target_elf_flavour
:
8057 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
8058 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8060 if (ei_osabi
== ELFOSABI_ARM
)
8062 /* GNU tools used to use this value, but do not for EABI
8063 objects. There's nowhere to tag an EABI version
8064 anyway, so assume APCS. */
8065 arm_abi
= ARM_ABI_APCS
;
8067 else if (ei_osabi
== ELFOSABI_NONE
)
8069 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
8070 int attr_arch
, attr_profile
;
8074 case EF_ARM_EABI_UNKNOWN
:
8075 /* Assume GNU tools. */
8076 arm_abi
= ARM_ABI_APCS
;
8079 case EF_ARM_EABI_VER4
:
8080 case EF_ARM_EABI_VER5
:
8081 arm_abi
= ARM_ABI_AAPCS
;
8082 /* EABI binaries default to VFP float ordering.
8083 They may also contain build attributes that can
8084 be used to identify if the VFP argument-passing
8086 if (fp_model
== ARM_FLOAT_AUTO
)
8089 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
8094 /* "The user intended FP parameter/result
8095 passing to conform to AAPCS, base
8097 fp_model
= ARM_FLOAT_SOFT_VFP
;
8100 /* "The user intended FP parameter/result
8101 passing to conform to AAPCS, VFP
8103 fp_model
= ARM_FLOAT_VFP
;
8106 /* "The user intended FP parameter/result
8107 passing to conform to tool chain-specific
8108 conventions" - we don't know any such
8109 conventions, so leave it as "auto". */
8112 /* Attribute value not mentioned in the
8113 October 2008 ABI, so leave it as
8118 fp_model
= ARM_FLOAT_SOFT_VFP
;
8124 /* Leave it as "auto". */
8125 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
8130 /* Detect M-profile programs. This only works if the
8131 executable file includes build attributes; GCC does
8132 copy them to the executable, but e.g. RealView does
8134 attr_arch
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
8136 attr_profile
= bfd_elf_get_obj_attr_int (info
.abfd
,
8138 Tag_CPU_arch_profile
);
8139 /* GCC specifies the profile for v6-M; RealView only
8140 specifies the profile for architectures starting with
8141 V7 (as opposed to architectures with a tag
8142 numerically greater than TAG_CPU_ARCH_V7). */
8143 if (!tdesc_has_registers (tdesc
)
8144 && (attr_arch
== TAG_CPU_ARCH_V6_M
8145 || attr_arch
== TAG_CPU_ARCH_V6S_M
8146 || attr_profile
== 'M'))
8147 tdesc
= tdesc_arm_with_m
;
8151 if (fp_model
== ARM_FLOAT_AUTO
)
8153 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8155 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
8158 /* Leave it as "auto". Strictly speaking this case
8159 means FPA, but almost nobody uses that now, and
8160 many toolchains fail to set the appropriate bits
8161 for the floating-point model they use. */
8163 case EF_ARM_SOFT_FLOAT
:
8164 fp_model
= ARM_FLOAT_SOFT_FPA
;
8166 case EF_ARM_VFP_FLOAT
:
8167 fp_model
= ARM_FLOAT_VFP
;
8169 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
8170 fp_model
= ARM_FLOAT_SOFT_VFP
;
8175 if (e_flags
& EF_ARM_BE8
)
8176 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
8181 /* Leave it as "auto". */
8186 /* Check any target description for validity. */
8187 if (tdesc_has_registers (tdesc
))
8189 /* For most registers we require GDB's default names; but also allow
8190 the numeric names for sp / lr / pc, as a convenience. */
8191 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
8192 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
8193 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
8195 const struct tdesc_feature
*feature
;
8198 feature
= tdesc_find_feature (tdesc
,
8199 "org.gnu.gdb.arm.core");
8200 if (feature
== NULL
)
8202 feature
= tdesc_find_feature (tdesc
,
8203 "org.gnu.gdb.arm.m-profile");
8204 if (feature
== NULL
)
8210 tdesc_data
= tdesc_data_alloc ();
8213 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
8214 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
8215 arm_register_names
[i
]);
8216 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
8219 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
8222 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
8226 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8227 ARM_PS_REGNUM
, "xpsr");
8229 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8230 ARM_PS_REGNUM
, "cpsr");
8234 tdesc_data_cleanup (tdesc_data
);
8238 feature
= tdesc_find_feature (tdesc
,
8239 "org.gnu.gdb.arm.fpa");
8240 if (feature
!= NULL
)
8243 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
8244 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
8245 arm_register_names
[i
]);
8248 tdesc_data_cleanup (tdesc_data
);
8253 have_fpa_registers
= 0;
8255 feature
= tdesc_find_feature (tdesc
,
8256 "org.gnu.gdb.xscale.iwmmxt");
8257 if (feature
!= NULL
)
8259 static const char *const iwmmxt_names
[] = {
8260 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
8261 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
8262 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
8263 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
8267 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
8269 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
8270 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
8272 /* Check for the control registers, but do not fail if they
8274 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
8275 tdesc_numbered_register (feature
, tdesc_data
, i
,
8276 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
8278 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
8280 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
8281 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
8285 tdesc_data_cleanup (tdesc_data
);
8290 /* If we have a VFP unit, check whether the single precision registers
8291 are present. If not, then we will synthesize them as pseudo
8293 feature
= tdesc_find_feature (tdesc
,
8294 "org.gnu.gdb.arm.vfp");
8295 if (feature
!= NULL
)
8297 static const char *const vfp_double_names
[] = {
8298 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
8299 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
8300 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
8301 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
8304 /* Require the double precision registers. There must be either
8307 for (i
= 0; i
< 32; i
++)
8309 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8311 vfp_double_names
[i
]);
8316 if (!valid_p
&& i
!= 16)
8318 tdesc_data_cleanup (tdesc_data
);
8322 if (tdesc_unnumbered_register (feature
, "s0") == 0)
8323 have_vfp_pseudos
= 1;
8325 have_vfp_registers
= 1;
8327 /* If we have VFP, also check for NEON. The architecture allows
8328 NEON without VFP (integer vector operations only), but GDB
8329 does not support that. */
8330 feature
= tdesc_find_feature (tdesc
,
8331 "org.gnu.gdb.arm.neon");
8332 if (feature
!= NULL
)
8334 /* NEON requires 32 double-precision registers. */
8337 tdesc_data_cleanup (tdesc_data
);
8341 /* If there are quad registers defined by the stub, use
8342 their type; otherwise (normally) provide them with
8343 the default type. */
8344 if (tdesc_unnumbered_register (feature
, "q0") == 0)
8345 have_neon_pseudos
= 1;
8352 /* If there is already a candidate, use it. */
8353 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
8355 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
8357 if (arm_abi
!= ARM_ABI_AUTO
8358 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
8361 if (fp_model
!= ARM_FLOAT_AUTO
8362 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
8365 /* There are various other properties in tdep that we do not
8366 need to check here: those derived from a target description,
8367 since gdbarches with a different target description are
8368 automatically disqualified. */
8370 /* Do check is_m, though, since it might come from the binary. */
8371 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
8374 /* Found a match. */
8378 if (best_arch
!= NULL
)
8380 if (tdesc_data
!= NULL
)
8381 tdesc_data_cleanup (tdesc_data
);
8382 return best_arch
->gdbarch
;
8385 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
8386 gdbarch
= gdbarch_alloc (&info
, tdep
);
8388 /* Record additional information about the architecture we are defining.
8389 These are gdbarch discriminators, like the OSABI. */
8390 tdep
->arm_abi
= arm_abi
;
8391 tdep
->fp_model
= fp_model
;
8393 tdep
->have_fpa_registers
= have_fpa_registers
;
8394 tdep
->have_vfp_registers
= have_vfp_registers
;
8395 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
8396 tdep
->have_neon_pseudos
= have_neon_pseudos
;
8397 tdep
->have_neon
= have_neon
;
8400 switch (info
.byte_order_for_code
)
8402 case BFD_ENDIAN_BIG
:
8403 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
8404 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
8405 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
8406 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
8410 case BFD_ENDIAN_LITTLE
:
8411 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
8412 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
8413 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
8414 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
8419 internal_error (__FILE__
, __LINE__
,
8420 _("arm_gdbarch_init: bad byte order for float format"));
8423 /* On ARM targets char defaults to unsigned. */
8424 set_gdbarch_char_signed (gdbarch
, 0);
8426 /* Note: for displaced stepping, this includes the breakpoint, and one word
8427 of additional scratch space. This setting isn't used for anything beside
8428 displaced stepping at present. */
8429 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
8431 /* This should be low enough for everything. */
8432 tdep
->lowest_pc
= 0x20;
8433 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
8435 /* The default, for both APCS and AAPCS, is to return small
8436 structures in registers. */
8437 tdep
->struct_return
= reg_struct_return
;
8439 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
8440 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
8442 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
8444 /* Frame handling. */
8445 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
8446 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
8447 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
8449 frame_base_set_default (gdbarch
, &arm_normal_base
);
8451 /* Address manipulation. */
8452 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
8453 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
8455 /* Advance PC across function entry code. */
8456 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
8458 /* Detect whether PC is in function epilogue. */
8459 set_gdbarch_in_function_epilogue_p (gdbarch
, arm_in_function_epilogue_p
);
8461 /* Skip trampolines. */
8462 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
8464 /* The stack grows downward. */
8465 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8467 /* Breakpoint manipulation. */
8468 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
8469 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
8470 arm_remote_breakpoint_from_pc
);
8472 /* Information about registers, etc. */
8473 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
8474 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
8475 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
8476 set_gdbarch_register_type (gdbarch
, arm_register_type
);
8477 set_gdbarch_register_reggroup_p (gdbarch
, arm_register_reggroup_p
);
8479 /* This "info float" is FPA-specific. Use the generic version if we
8481 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
8482 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
8484 /* Internal <-> external register number maps. */
8485 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
8486 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
8488 set_gdbarch_register_name (gdbarch
, arm_register_name
);
8490 /* Returning results. */
8491 set_gdbarch_return_value (gdbarch
, arm_return_value
);
8494 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
8496 /* Minsymbol frobbing. */
8497 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
8498 set_gdbarch_coff_make_msymbol_special (gdbarch
,
8499 arm_coff_make_msymbol_special
);
8500 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
8502 /* Thumb-2 IT block support. */
8503 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8504 arm_adjust_breakpoint_address
);
8506 /* Virtual tables. */
8507 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8509 /* Hook in the ABI-specific overrides, if they have been registered. */
8510 gdbarch_init_osabi (info
, gdbarch
);
8512 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
8514 /* Add some default predicates. */
8515 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
8516 dwarf2_append_unwinders (gdbarch
);
8517 frame_unwind_append_unwinder (gdbarch
, &arm_exidx_unwind
);
8518 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
8520 /* Now we have tuned the configuration, set a few final things,
8521 based on what the OS ABI has told us. */
8523 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
8524 binaries are always marked. */
8525 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
8526 tdep
->arm_abi
= ARM_ABI_APCS
;
8528 /* We used to default to FPA for generic ARM, but almost nobody
8529 uses that now, and we now provide a way for the user to force
8530 the model. So default to the most useful variant. */
8531 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
8532 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
8534 if (tdep
->jb_pc
>= 0)
8535 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
8537 /* Floating point sizes and format. */
8538 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
8539 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
8541 set_gdbarch_double_format
8542 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
8543 set_gdbarch_long_double_format
8544 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
8548 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
8549 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
8552 if (have_vfp_pseudos
)
8554 /* NOTE: These are the only pseudo registers used by
8555 the ARM target at the moment. If more are added, a
8556 little more care in numbering will be needed. */
8558 int num_pseudos
= 32;
8559 if (have_neon_pseudos
)
8561 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
8562 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
8563 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
8568 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
8570 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
8572 /* Override tdesc_register_type to adjust the types of VFP
8573 registers for NEON. */
8574 set_gdbarch_register_type (gdbarch
, arm_register_type
);
8577 /* Add standard register aliases. We add aliases even for those
8578 nanes which are used by the current architecture - it's simpler,
8579 and does no harm, since nothing ever lists user registers. */
8580 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
8581 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
8582 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
8588 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8590 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8595 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
8596 (unsigned long) tdep
->lowest_pc
);
8599 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
8602 _initialize_arm_tdep (void)
8604 struct ui_file
*stb
;
8606 struct cmd_list_element
*new_set
, *new_show
;
8607 const char *setname
;
8608 const char *setdesc
;
8609 const char *const *regnames
;
8611 static char *helptext
;
8612 char regdesc
[1024], *rdptr
= regdesc
;
8613 size_t rest
= sizeof (regdesc
);
8615 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
8617 arm_objfile_data_key
8618 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
8620 /* Add ourselves to objfile event chain. */
8621 observer_attach_new_objfile (arm_exidx_new_objfile
);
8623 = register_objfile_data_with_cleanup (NULL
, arm_exidx_data_free
);
8625 /* Register an ELF OS ABI sniffer for ARM binaries. */
8626 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
8627 bfd_target_elf_flavour
,
8628 arm_elf_osabi_sniffer
);
8630 /* Initialize the standard target descriptions. */
8631 initialize_tdesc_arm_with_m ();
8633 /* Get the number of possible sets of register names defined in opcodes. */
8634 num_disassembly_options
= get_arm_regname_num_options ();
8636 /* Add root prefix command for all "set arm"/"show arm" commands. */
8637 add_prefix_cmd ("arm", no_class
, set_arm_command
,
8638 _("Various ARM-specific commands."),
8639 &setarmcmdlist
, "set arm ", 0, &setlist
);
8641 add_prefix_cmd ("arm", no_class
, show_arm_command
,
8642 _("Various ARM-specific commands."),
8643 &showarmcmdlist
, "show arm ", 0, &showlist
);
8645 /* Sync the opcode insn printer with our register viewer. */
8646 parse_arm_disassembler_option ("reg-names-std");
8648 /* Initialize the array that will be passed to
8649 add_setshow_enum_cmd(). */
8650 valid_disassembly_styles
8651 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
8652 for (i
= 0; i
< num_disassembly_options
; i
++)
8654 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
8655 valid_disassembly_styles
[i
] = setname
;
8656 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
8659 /* When we find the default names, tell the disassembler to use
8661 if (!strcmp (setname
, "std"))
8663 disassembly_style
= setname
;
8664 set_arm_regname_option (i
);
8667 /* Mark the end of valid options. */
8668 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
8670 /* Create the help text. */
8671 stb
= mem_fileopen ();
8672 fprintf_unfiltered (stb
, "%s%s%s",
8673 _("The valid values are:\n"),
8675 _("The default is \"std\"."));
8676 helptext
= ui_file_xstrdup (stb
, NULL
);
8677 ui_file_delete (stb
);
8679 add_setshow_enum_cmd("disassembler", no_class
,
8680 valid_disassembly_styles
, &disassembly_style
,
8681 _("Set the disassembly style."),
8682 _("Show the disassembly style."),
8684 set_disassembly_style_sfunc
,
8685 NULL
, /* FIXME: i18n: The disassembly style is
8687 &setarmcmdlist
, &showarmcmdlist
);
8689 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
8690 _("Set usage of ARM 32-bit mode."),
8691 _("Show usage of ARM 32-bit mode."),
8692 _("When off, a 26-bit PC will be used."),
8694 NULL
, /* FIXME: i18n: Usage of ARM 32-bit
8696 &setarmcmdlist
, &showarmcmdlist
);
8698 /* Add a command to allow the user to force the FPU model. */
8699 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
8700 _("Set the floating point type."),
8701 _("Show the floating point type."),
8702 _("auto - Determine the FP typefrom the OS-ABI.\n\
8703 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
8704 fpa - FPA co-processor (GCC compiled).\n\
8705 softvfp - Software FP with pure-endian doubles.\n\
8706 vfp - VFP co-processor."),
8707 set_fp_model_sfunc
, show_fp_model
,
8708 &setarmcmdlist
, &showarmcmdlist
);
8710 /* Add a command to allow the user to force the ABI. */
8711 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
8714 NULL
, arm_set_abi
, arm_show_abi
,
8715 &setarmcmdlist
, &showarmcmdlist
);
8717 /* Add two commands to allow the user to force the assumed
8719 add_setshow_enum_cmd ("fallback-mode", class_support
,
8720 arm_mode_strings
, &arm_fallback_mode_string
,
8721 _("Set the mode assumed when symbols are unavailable."),
8722 _("Show the mode assumed when symbols are unavailable."),
8723 NULL
, NULL
, arm_show_fallback_mode
,
8724 &setarmcmdlist
, &showarmcmdlist
);
8725 add_setshow_enum_cmd ("force-mode", class_support
,
8726 arm_mode_strings
, &arm_force_mode_string
,
8727 _("Set the mode assumed even when symbols are available."),
8728 _("Show the mode assumed even when symbols are available."),
8729 NULL
, NULL
, arm_show_force_mode
,
8730 &setarmcmdlist
, &showarmcmdlist
);
8732 /* Debugging flag. */
8733 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
8734 _("Set ARM debugging."),
8735 _("Show ARM debugging."),
8736 _("When on, arm-specific debugging is enabled."),
8738 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
8739 &setdebuglist
, &showdebuglist
);