1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper () */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
43 #include "target-descriptions.h"
44 #include "user-regs.h"
47 #include "gdb/sim-arm.h"
50 #include "coff/internal.h"
53 #include "gdb_assert.h"
58 /* Macros for setting and testing a bit in a minimal symbol that marks
59 it as Thumb function. The MSB of the minimal symbol's "info" field
60 is used for this purpose.
62 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
63 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
65 #define MSYMBOL_SET_SPECIAL(msym) \
66 MSYMBOL_TARGET_FLAG_1 (msym) = 1
68 #define MSYMBOL_IS_SPECIAL(msym) \
69 MSYMBOL_TARGET_FLAG_1 (msym)
71 /* Macros for swapping shorts and ints. In the unlikely case that anybody else needs these,
72 move to a general header. (A better solution might be to define memory read routines that
73 know whether they are reading code or data.) */
75 #define SWAP_SHORT(x) \
76 ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8));
79 ( ((x & 0xff000000) >> 24) \
80 | ((x & 0x00ff0000) >> 8) \
81 | ((x & 0x0000ff00) << 8) \
82 | ((x & 0x000000ff) << 24))
84 /* Per-objfile data used for mapping symbols. */
85 static const struct objfile_data
*arm_objfile_data_key
;
87 struct arm_mapping_symbol
92 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
93 DEF_VEC_O(arm_mapping_symbol_s
);
95 struct arm_per_objfile
97 VEC(arm_mapping_symbol_s
) **section_maps
;
100 /* The list of available "set arm ..." and "show arm ..." commands. */
101 static struct cmd_list_element
*setarmcmdlist
= NULL
;
102 static struct cmd_list_element
*showarmcmdlist
= NULL
;
104 /* The type of floating-point to use. Keep this in sync with enum
105 arm_float_model, and the help string in _initialize_arm_tdep. */
106 static const char *fp_model_strings
[] =
116 /* A variable that can be configured by the user. */
117 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
118 static const char *current_fp_model
= "auto";
120 /* The ABI to use. Keep this in sync with arm_abi_kind. */
121 static const char *arm_abi_strings
[] =
129 /* A variable that can be configured by the user. */
130 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
131 static const char *arm_abi_string
= "auto";
133 /* The execution mode to assume. */
134 static const char *arm_mode_strings
[] =
141 static const char *arm_fallback_mode_string
= "auto";
142 static const char *arm_force_mode_string
= "auto";
144 /* Number of different reg name sets (options). */
145 static int num_disassembly_options
;
147 /* The standard register names, and all the valid aliases for them. */
152 } arm_register_aliases
[] = {
153 /* Basic register numbers. */
170 /* Synonyms (argument and variable registers). */
183 /* Other platform-specific names for r9. */
191 /* Names used by GCC (not listed in the ARM EABI). */
194 /* A special name from the older ATPCS. */
198 static const char *const arm_register_names
[] =
199 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
200 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
201 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
202 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
203 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
204 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
205 "fps", "cpsr" }; /* 24 25 */
207 /* Valid register name styles. */
208 static const char **valid_disassembly_styles
;
210 /* Disassembly style to use. Default to "std" register names. */
211 static const char *disassembly_style
;
213 /* This is used to keep the bfd arch_info in sync with the disassembly
215 static void set_disassembly_style_sfunc(char *, int,
216 struct cmd_list_element
*);
217 static void set_disassembly_style (void);
219 static void convert_from_extended (const struct floatformat
*, const void *,
221 static void convert_to_extended (const struct floatformat
*, void *,
224 struct arm_prologue_cache
226 /* The stack pointer at the time this frame was created; i.e. the
227 caller's stack pointer when this function was called. It is used
228 to identify this frame. */
231 /* The frame base for this frame is just prev_sp - frame size.
232 FRAMESIZE is the distance from the frame pointer to the
233 initial stack pointer. */
237 /* The register used to hold the frame pointer for this frame. */
240 /* Saved register offsets. */
241 struct trad_frame_saved_reg
*saved_regs
;
244 /* Addresses for calling Thumb functions have the bit 0 set.
245 Here are some macros to test, set, or clear bit 0 of addresses. */
246 #define IS_THUMB_ADDR(addr) ((addr) & 1)
247 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
248 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
250 /* Set to true if the 32-bit mode is in use. */
254 /* Determine if FRAME is executing in Thumb mode. */
257 arm_frame_is_thumb (struct frame_info
*frame
)
261 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
262 directly (from a signal frame or dummy frame) or by interpreting
263 the saved LR (from a prologue or DWARF frame). So consult it and
264 trust the unwinders. */
265 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
267 return (cpsr
& CPSR_T
) != 0;
270 /* Callback for VEC_lower_bound. */
273 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
274 const struct arm_mapping_symbol
*rhs
)
276 return lhs
->value
< rhs
->value
;
279 /* Determine if the program counter specified in MEMADDR is in a Thumb
280 function. This function should be called for addresses unrelated to
281 any executing frame; otherwise, prefer arm_frame_is_thumb. */
284 arm_pc_is_thumb (CORE_ADDR memaddr
)
286 struct obj_section
*sec
;
287 struct minimal_symbol
*sym
;
289 /* If bit 0 of the address is set, assume this is a Thumb address. */
290 if (IS_THUMB_ADDR (memaddr
))
293 /* If the user wants to override the symbol table, let him. */
294 if (strcmp (arm_force_mode_string
, "arm") == 0)
296 if (strcmp (arm_force_mode_string
, "thumb") == 0)
299 /* If there are mapping symbols, consult them. */
300 sec
= find_pc_section (memaddr
);
303 struct arm_per_objfile
*data
;
304 VEC(arm_mapping_symbol_s
) *map
;
305 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
309 data
= objfile_data (sec
->objfile
, arm_objfile_data_key
);
312 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
313 if (!VEC_empty (arm_mapping_symbol_s
, map
))
315 struct arm_mapping_symbol
*map_sym
;
317 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
318 arm_compare_mapping_symbols
);
320 /* VEC_lower_bound finds the earliest ordered insertion
321 point. If the following symbol starts at this exact
322 address, we use that; otherwise, the preceding
323 mapping symbol covers this address. */
324 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
326 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
327 if (map_sym
->value
== map_key
.value
)
328 return map_sym
->type
== 't';
333 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
334 return map_sym
->type
== 't';
340 /* Thumb functions have a "special" bit set in minimal symbols. */
341 sym
= lookup_minimal_symbol_by_pc (memaddr
);
343 return (MSYMBOL_IS_SPECIAL (sym
));
345 /* If the user wants to override the fallback mode, let them. */
346 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
348 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
351 /* If we couldn't find any symbol, but we're talking to a running
352 target, then trust the current value of $cpsr. This lets
353 "display/i $pc" always show the correct mode (though if there is
354 a symbol table we will not reach here, so it still may not be
355 displayed in the mode it will be executed). */
356 if (target_has_registers
)
357 return arm_frame_is_thumb (get_current_frame ());
359 /* Otherwise we're out of luck; we assume ARM. */
363 /* Remove useless bits from addresses in a running program. */
365 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
368 return UNMAKE_THUMB_ADDR (val
);
370 return (val
& 0x03fffffc);
373 /* When reading symbols, we need to zap the low bit of the address,
374 which may be set to 1 for Thumb functions. */
376 arm_smash_text_address (struct gdbarch
*gdbarch
, CORE_ADDR val
)
381 /* Analyze a Thumb prologue, looking for a recognizable stack frame
382 and frame pointer. Scan until we encounter a store that could
383 clobber the stack frame unexpectedly, or an unknown instruction. */
386 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
387 CORE_ADDR start
, CORE_ADDR limit
,
388 struct arm_prologue_cache
*cache
)
392 struct pv_area
*stack
;
393 struct cleanup
*back_to
;
396 for (i
= 0; i
< 16; i
++)
397 regs
[i
] = pv_register (i
, 0);
398 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
399 back_to
= make_cleanup_free_pv_area (stack
);
401 while (start
< limit
)
405 insn
= read_memory_unsigned_integer (start
, 2);
407 if (gdbarch_byte_order_for_code (gdbarch
) != gdbarch_byte_order (gdbarch
))
408 insn
= SWAP_SHORT (insn
);
410 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
415 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
418 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
419 whether to save LR (R14). */
420 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
422 /* Calculate offsets of saved R0-R7 and LR. */
423 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
424 if (mask
& (1 << regno
))
426 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
428 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
431 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
434 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
435 if (insn
& 0x80) /* Check for SUB. */
436 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
439 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
442 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
443 regs
[THUMB_FP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
445 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
447 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
448 int src_reg
= (insn
& 0x78) >> 3;
449 regs
[dst_reg
] = regs
[src_reg
];
451 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
453 /* Handle stores to the stack. Normally pushes are used,
454 but with GCC -mtpcs-frame, there may be other stores
455 in the prologue to create the frame. */
456 int regno
= (insn
>> 8) & 0x7;
459 offset
= (insn
& 0xff) << 2;
460 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
462 if (pv_area_store_would_trash (stack
, addr
))
465 pv_area_store (stack
, addr
, 4, regs
[regno
]);
469 /* We don't know what this instruction is. We're finished
470 scanning. NOTE: Recognizing more safe-to-ignore
471 instructions here will improve support for optimized
481 do_cleanups (back_to
);
485 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
487 /* Frame pointer is fp. Frame size is constant. */
488 cache
->framereg
= ARM_FP_REGNUM
;
489 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
491 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
493 /* Frame pointer is r7. Frame size is constant. */
494 cache
->framereg
= THUMB_FP_REGNUM
;
495 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
497 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
499 /* Try the stack pointer... this is a bit desperate. */
500 cache
->framereg
= ARM_SP_REGNUM
;
501 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
505 /* We're just out of luck. We don't know where the frame is. */
506 cache
->framereg
= -1;
507 cache
->framesize
= 0;
510 for (i
= 0; i
< 16; i
++)
511 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
512 cache
->saved_regs
[i
].addr
= offset
;
514 do_cleanups (back_to
);
518 /* Advance the PC across any function entry prologue instructions to
519 reach some "real" code.
521 The APCS (ARM Procedure Call Standard) defines the following
525 [stmfd sp!, {a1,a2,a3,a4}]
526 stmfd sp!, {...,fp,ip,lr,pc}
527 [stfe f7, [sp, #-12]!]
528 [stfe f6, [sp, #-12]!]
529 [stfe f5, [sp, #-12]!]
530 [stfe f4, [sp, #-12]!]
531 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
534 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
538 CORE_ADDR func_addr
, limit_pc
;
539 struct symtab_and_line sal
;
541 /* If we're in a dummy frame, don't even try to skip the prologue. */
542 if (deprecated_pc_in_call_dummy (gdbarch
, pc
))
545 /* See if we can determine the end of the prologue via the symbol table.
546 If so, then return either PC, or the PC after the prologue, whichever
548 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
550 CORE_ADDR post_prologue_pc
551 = skip_prologue_using_sal (gdbarch
, func_addr
);
552 if (post_prologue_pc
!= 0)
553 return max (pc
, post_prologue_pc
);
556 /* Can't determine prologue from the symbol table, need to examine
559 /* Find an upper limit on the function prologue using the debug
560 information. If the debug information could not be used to provide
561 that bound, then use an arbitrary large number as the upper bound. */
562 /* Like arm_scan_prologue, stop no later than pc + 64. */
563 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
565 limit_pc
= pc
+ 64; /* Magic. */
568 /* Check if this is Thumb code. */
569 if (arm_pc_is_thumb (pc
))
570 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
572 for (skip_pc
= pc
; skip_pc
< limit_pc
; skip_pc
+= 4)
574 inst
= read_memory_unsigned_integer (skip_pc
, 4);
576 if (gdbarch_byte_order_for_code (gdbarch
) != gdbarch_byte_order (gdbarch
))
577 inst
= SWAP_INT (inst
);
579 /* "mov ip, sp" is no longer a required part of the prologue. */
580 if (inst
== 0xe1a0c00d) /* mov ip, sp */
583 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
586 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
589 /* Some prologues begin with "str lr, [sp, #-4]!". */
590 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
593 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
596 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
599 /* Any insns after this point may float into the code, if it makes
600 for better instruction scheduling, so we skip them only if we
601 find them, but still consider the function to be frame-ful. */
603 /* We may have either one sfmfd instruction here, or several stfe
604 insns, depending on the version of floating point code we
606 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
609 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
612 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
615 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
618 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
619 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
620 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
623 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
624 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
625 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
628 /* Un-recognized instruction; stop scanning. */
632 return skip_pc
; /* End of prologue */
636 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
637 This function decodes a Thumb function prologue to determine:
638 1) the size of the stack frame
639 2) which registers are saved on it
640 3) the offsets of saved regs
641 4) the offset from the stack pointer to the frame pointer
643 A typical Thumb function prologue would create this stack frame
644 (offsets relative to FP)
645 old SP -> 24 stack parameters
648 R7 -> 0 local variables (16 bytes)
649 SP -> -12 additional stack space (12 bytes)
650 The frame size would thus be 36 bytes, and the frame offset would be
651 12 bytes. The frame register is R7.
653 The comments for thumb_skip_prolog() describe the algorithm we use
654 to detect the end of the prolog. */
658 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
659 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
661 CORE_ADDR prologue_start
;
662 CORE_ADDR prologue_end
;
663 CORE_ADDR current_pc
;
665 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
668 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
670 if (sal
.line
== 0) /* no line info, use current PC */
671 prologue_end
= prev_pc
;
672 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
673 prologue_end
= sal
.end
; /* (probably means no prologue) */
676 /* We're in the boondocks: we have no idea where the start of the
680 prologue_end
= min (prologue_end
, prev_pc
);
682 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
685 /* This function decodes an ARM function prologue to determine:
686 1) the size of the stack frame
687 2) which registers are saved on it
688 3) the offsets of saved regs
689 4) the offset from the stack pointer to the frame pointer
690 This information is stored in the "extra" fields of the frame_info.
692 There are two basic forms for the ARM prologue. The fixed argument
693 function call will look like:
696 stmfd sp!, {fp, ip, lr, pc}
700 Which would create this stack frame (offsets relative to FP):
701 IP -> 4 (caller's stack)
702 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
703 -4 LR (return address in caller)
704 -8 IP (copy of caller's SP)
706 SP -> -28 Local variables
708 The frame size would thus be 32 bytes, and the frame offset would be
709 28 bytes. The stmfd call can also save any of the vN registers it
710 plans to use, which increases the frame size accordingly.
712 Note: The stored PC is 8 off of the STMFD instruction that stored it
713 because the ARM Store instructions always store PC + 8 when you read
716 A variable argument function call will look like:
719 stmfd sp!, {a1, a2, a3, a4}
720 stmfd sp!, {fp, ip, lr, pc}
723 Which would create this stack frame (offsets relative to FP):
724 IP -> 20 (caller's stack)
729 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
730 -4 LR (return address in caller)
731 -8 IP (copy of caller's SP)
733 SP -> -28 Local variables
735 The frame size would thus be 48 bytes, and the frame offset would be
738 There is another potential complication, which is that the optimizer
739 will try to separate the store of fp in the "stmfd" instruction from
740 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
741 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
743 Also, note, the original version of the ARM toolchain claimed that there
746 instruction at the end of the prologue. I have never seen GCC produce
747 this, and the ARM docs don't mention it. We still test for it below in
753 arm_scan_prologue (struct frame_info
*this_frame
,
754 struct arm_prologue_cache
*cache
)
756 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
758 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
759 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
760 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
761 pv_t regs
[ARM_FPS_REGNUM
];
762 struct pv_area
*stack
;
763 struct cleanup
*back_to
;
766 /* Assume there is no frame until proven otherwise. */
767 cache
->framereg
= ARM_SP_REGNUM
;
768 cache
->framesize
= 0;
770 /* Check for Thumb prologue. */
771 if (arm_frame_is_thumb (this_frame
))
773 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
777 /* Find the function prologue. If we can't find the function in
778 the symbol table, peek in the stack frame to find the PC. */
779 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
782 /* One way to find the end of the prologue (which works well
783 for unoptimized code) is to do the following:
785 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
788 prologue_end = prev_pc;
789 else if (sal.end < prologue_end)
790 prologue_end = sal.end;
792 This mechanism is very accurate so long as the optimizer
793 doesn't move any instructions from the function body into the
794 prologue. If this happens, sal.end will be the last
795 instruction in the first hunk of prologue code just before
796 the first instruction that the scheduler has moved from
797 the body to the prologue.
799 In order to make sure that we scan all of the prologue
800 instructions, we use a slightly less accurate mechanism which
801 may scan more than necessary. To help compensate for this
802 lack of accuracy, the prologue scanning loop below contains
803 several clauses which'll cause the loop to terminate early if
804 an implausible prologue instruction is encountered.
810 is a suitable endpoint since it accounts for the largest
811 possible prologue plus up to five instructions inserted by
814 if (prologue_end
> prologue_start
+ 64)
816 prologue_end
= prologue_start
+ 64; /* See above. */
821 /* We have no symbol information. Our only option is to assume this
822 function has a standard stack frame and the normal frame register.
823 Then, we can find the value of our frame pointer on entrance to
824 the callee (or at the present moment if this is the innermost frame).
825 The value stored there should be the address of the stmfd + 8. */
827 LONGEST return_value
;
829 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
830 if (!safe_read_memory_integer (frame_loc
, 4, &return_value
))
834 prologue_start
= gdbarch_addr_bits_remove
835 (gdbarch
, return_value
) - 8;
836 prologue_end
= prologue_start
+ 64; /* See above. */
840 if (prev_pc
< prologue_end
)
841 prologue_end
= prev_pc
;
843 /* Now search the prologue looking for instructions that set up the
844 frame pointer, adjust the stack pointer, and save registers.
846 Be careful, however, and if it doesn't look like a prologue,
847 don't try to scan it. If, for instance, a frameless function
848 begins with stmfd sp!, then we will tell ourselves there is
849 a frame, which will confuse stack traceback, as well as "finish"
850 and other operations that rely on a knowledge of the stack
853 In the APCS, the prologue should start with "mov ip, sp" so
854 if we don't see this as the first insn, we will stop.
856 [Note: This doesn't seem to be true any longer, so it's now an
857 optional part of the prologue. - Kevin Buettner, 2001-11-20]
859 [Note further: The "mov ip,sp" only seems to be missing in
860 frameless functions at optimization level "-O2" or above,
861 in which case it is often (but not always) replaced by
862 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
864 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
865 regs
[regno
] = pv_register (regno
, 0);
866 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
867 back_to
= make_cleanup_free_pv_area (stack
);
869 for (current_pc
= prologue_start
;
870 current_pc
< prologue_end
;
873 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
875 if (gdbarch_byte_order_for_code (gdbarch
) != gdbarch_byte_order (gdbarch
))
876 insn
= SWAP_INT (insn
);
878 if (insn
== 0xe1a0c00d) /* mov ip, sp */
880 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
883 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
885 unsigned imm
= insn
& 0xff; /* immediate value */
886 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
887 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
888 regs
[ARM_IP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], imm
);
891 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
893 unsigned imm
= insn
& 0xff; /* immediate value */
894 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
895 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
896 regs
[ARM_IP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
899 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
901 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
903 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
904 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[ARM_LR_REGNUM
]);
907 else if ((insn
& 0xffff0000) == 0xe92d0000)
908 /* stmfd sp!, {..., fp, ip, lr, pc}
910 stmfd sp!, {a1, a2, a3, a4} */
912 int mask
= insn
& 0xffff;
914 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
917 /* Calculate offsets of saved registers. */
918 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
919 if (mask
& (1 << regno
))
921 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
922 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
925 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
926 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
927 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
929 /* No need to add this to saved_regs -- it's just an arg reg. */
932 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
933 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
934 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
936 /* No need to add this to saved_regs -- it's just an arg reg. */
939 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
941 unsigned imm
= insn
& 0xff; /* immediate value */
942 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
943 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
944 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
946 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
948 unsigned imm
= insn
& 0xff; /* immediate value */
949 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
950 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
951 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
953 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
954 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
956 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
959 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
960 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
961 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
963 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
964 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
967 unsigned int fp_start_reg
, fp_bound_reg
;
969 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
972 if ((insn
& 0x800) == 0x800) /* N0 is set */
974 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
981 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
987 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
988 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
989 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
991 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
992 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
993 regs
[fp_start_reg
++]);
996 else if ((insn
& 0xf0000000) != 0xe0000000)
997 break; /* Condition not true, exit early */
998 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
999 break; /* Don't scan past a block load */
1001 /* The optimizer might shove anything into the prologue,
1002 so we just skip what we don't recognize. */
1006 /* The frame size is just the distance from the frame register
1007 to the original stack pointer. */
1008 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1010 /* Frame pointer is fp. */
1011 cache
->framereg
= ARM_FP_REGNUM
;
1012 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1014 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
1016 /* Try the stack pointer... this is a bit desperate. */
1017 cache
->framereg
= ARM_SP_REGNUM
;
1018 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1022 /* We're just out of luck. We don't know where the frame is. */
1023 cache
->framereg
= -1;
1024 cache
->framesize
= 0;
1027 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1028 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1029 cache
->saved_regs
[regno
].addr
= offset
;
1031 do_cleanups (back_to
);
1034 static struct arm_prologue_cache
*
1035 arm_make_prologue_cache (struct frame_info
*this_frame
)
1038 struct arm_prologue_cache
*cache
;
1039 CORE_ADDR unwound_fp
;
1041 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1042 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1044 arm_scan_prologue (this_frame
, cache
);
1046 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
1047 if (unwound_fp
== 0)
1050 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
1052 /* Calculate actual addresses of saved registers using offsets
1053 determined by arm_scan_prologue. */
1054 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
1055 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
1056 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
1061 /* Our frame ID for a normal frame is the current function's starting PC
1062 and the caller's SP when we were called. */
1065 arm_prologue_this_id (struct frame_info
*this_frame
,
1067 struct frame_id
*this_id
)
1069 struct arm_prologue_cache
*cache
;
1073 if (*this_cache
== NULL
)
1074 *this_cache
= arm_make_prologue_cache (this_frame
);
1075 cache
= *this_cache
;
1077 /* This is meant to halt the backtrace at "_start". */
1078 pc
= get_frame_pc (this_frame
);
1079 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1082 /* If we've hit a wall, stop. */
1083 if (cache
->prev_sp
== 0)
1086 func
= get_frame_func (this_frame
);
1087 id
= frame_id_build (cache
->prev_sp
, func
);
1091 static struct value
*
1092 arm_prologue_prev_register (struct frame_info
*this_frame
,
1096 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1097 struct arm_prologue_cache
*cache
;
1099 if (*this_cache
== NULL
)
1100 *this_cache
= arm_make_prologue_cache (this_frame
);
1101 cache
= *this_cache
;
1103 /* If we are asked to unwind the PC, then we need to return the LR
1104 instead. The prologue may save PC, but it will point into this
1105 frame's prologue, not the next frame's resume location. Also
1106 strip the saved T bit. A valid LR may have the low bit set, but
1107 a valid PC never does. */
1108 if (prev_regnum
== ARM_PC_REGNUM
)
1112 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1113 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1114 arm_addr_bits_remove (gdbarch
, lr
));
1117 /* SP is generally not saved to the stack, but this frame is
1118 identified by the next frame's stack pointer at the time of the call.
1119 The value was already reconstructed into PREV_SP. */
1120 if (prev_regnum
== ARM_SP_REGNUM
)
1121 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1123 /* The CPSR may have been changed by the call instruction and by the
1124 called function. The only bit we can reconstruct is the T bit,
1125 by checking the low bit of LR as of the call. This is a reliable
1126 indicator of Thumb-ness except for some ARM v4T pre-interworking
1127 Thumb code, which could get away with a clear low bit as long as
1128 the called function did not use bx. Guess that all other
1129 bits are unchanged; the condition flags are presumably lost,
1130 but the processor status is likely valid. */
1131 if (prev_regnum
== ARM_PS_REGNUM
)
1135 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1136 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1137 if (IS_THUMB_ADDR (lr
))
1141 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1144 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1148 struct frame_unwind arm_prologue_unwind
= {
1150 arm_prologue_this_id
,
1151 arm_prologue_prev_register
,
1153 default_frame_sniffer
1156 static struct arm_prologue_cache
*
1157 arm_make_stub_cache (struct frame_info
*this_frame
)
1160 struct arm_prologue_cache
*cache
;
1161 CORE_ADDR unwound_fp
;
1163 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1164 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1166 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1171 /* Our frame ID for a stub frame is the current SP and LR. */
1174 arm_stub_this_id (struct frame_info
*this_frame
,
1176 struct frame_id
*this_id
)
1178 struct arm_prologue_cache
*cache
;
1180 if (*this_cache
== NULL
)
1181 *this_cache
= arm_make_stub_cache (this_frame
);
1182 cache
= *this_cache
;
1184 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
1188 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
1189 struct frame_info
*this_frame
,
1190 void **this_prologue_cache
)
1192 CORE_ADDR addr_in_block
;
1195 addr_in_block
= get_frame_address_in_block (this_frame
);
1196 if (in_plt_section (addr_in_block
, NULL
)
1197 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
1203 struct frame_unwind arm_stub_unwind
= {
1206 arm_prologue_prev_register
,
1208 arm_stub_unwind_sniffer
1212 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
1214 struct arm_prologue_cache
*cache
;
1216 if (*this_cache
== NULL
)
1217 *this_cache
= arm_make_prologue_cache (this_frame
);
1218 cache
= *this_cache
;
1220 return cache
->prev_sp
- cache
->framesize
;
1223 struct frame_base arm_normal_base
= {
1224 &arm_prologue_unwind
,
1225 arm_normal_frame_base
,
1226 arm_normal_frame_base
,
1227 arm_normal_frame_base
1230 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1231 dummy frame. The frame ID's base needs to match the TOS value
1232 saved by save_dummy_frame_tos() and returned from
1233 arm_push_dummy_call, and the PC needs to match the dummy frame's
1236 static struct frame_id
1237 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1239 return frame_id_build (get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
),
1240 get_frame_pc (this_frame
));
1243 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1244 be used to construct the previous frame's ID, after looking up the
1245 containing function). */
1248 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1251 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1252 return arm_addr_bits_remove (gdbarch
, pc
);
1256 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1258 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1261 static struct value
*
1262 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1265 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
1271 /* The PC is normally copied from the return column, which
1272 describes saves of LR. However, that version may have an
1273 extra bit set to indicate Thumb state. The bit is not
1275 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1276 return frame_unwind_got_constant (this_frame
, regnum
,
1277 arm_addr_bits_remove (gdbarch
, lr
));
1280 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
1281 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
1282 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1283 if (IS_THUMB_ADDR (lr
))
1287 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
1290 internal_error (__FILE__
, __LINE__
,
1291 _("Unexpected register %d"), regnum
);
1296 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1297 struct dwarf2_frame_state_reg
*reg
,
1298 struct frame_info
*this_frame
)
1304 reg
->how
= DWARF2_FRAME_REG_FN
;
1305 reg
->loc
.fn
= arm_dwarf2_prev_register
;
1308 reg
->how
= DWARF2_FRAME_REG_CFA
;
1313 /* When arguments must be pushed onto the stack, they go on in reverse
1314 order. The code below implements a FILO (stack) to do this. */
1319 struct stack_item
*prev
;
1323 static struct stack_item
*
1324 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1326 struct stack_item
*si
;
1327 si
= xmalloc (sizeof (struct stack_item
));
1328 si
->data
= xmalloc (len
);
1331 memcpy (si
->data
, contents
, len
);
1335 static struct stack_item
*
1336 pop_stack_item (struct stack_item
*si
)
1338 struct stack_item
*dead
= si
;
1346 /* Return the alignment (in bytes) of the given type. */
1349 arm_type_align (struct type
*t
)
1355 t
= check_typedef (t
);
1356 switch (TYPE_CODE (t
))
1359 /* Should never happen. */
1360 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1364 case TYPE_CODE_ENUM
:
1368 case TYPE_CODE_RANGE
:
1369 case TYPE_CODE_BITSTRING
:
1371 case TYPE_CODE_CHAR
:
1372 case TYPE_CODE_BOOL
:
1373 return TYPE_LENGTH (t
);
1375 case TYPE_CODE_ARRAY
:
1376 case TYPE_CODE_COMPLEX
:
1377 /* TODO: What about vector types? */
1378 return arm_type_align (TYPE_TARGET_TYPE (t
));
1380 case TYPE_CODE_STRUCT
:
1381 case TYPE_CODE_UNION
:
1383 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1385 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
1393 /* We currently only support passing parameters in integer registers. This
1394 conforms with GCC's default model. Several other variants exist and
1395 we should probably support some of them based on the selected ABI. */
1398 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1399 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1400 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1401 CORE_ADDR struct_addr
)
1406 struct stack_item
*si
= NULL
;
1408 /* Set the return address. For the ARM, the return breakpoint is
1409 always at BP_ADDR. */
1410 /* XXX Fix for Thumb. */
1411 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1413 /* Walk through the list of args and determine how large a temporary
1414 stack is required. Need to take care here as structs may be
1415 passed on the stack, and we have to to push them. */
1418 argreg
= ARM_A1_REGNUM
;
1421 /* The struct_return pointer occupies the first parameter
1422 passing register. */
1426 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = 0x%s\n",
1427 gdbarch_register_name (gdbarch
, argreg
),
1428 paddr (struct_addr
));
1429 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1433 for (argnum
= 0; argnum
< nargs
; argnum
++)
1436 struct type
*arg_type
;
1437 struct type
*target_type
;
1438 enum type_code typecode
;
1442 arg_type
= check_typedef (value_type (args
[argnum
]));
1443 len
= TYPE_LENGTH (arg_type
);
1444 target_type
= TYPE_TARGET_TYPE (arg_type
);
1445 typecode
= TYPE_CODE (arg_type
);
1446 val
= value_contents_writeable (args
[argnum
]);
1448 align
= arm_type_align (arg_type
);
1449 /* Round alignment up to a whole number of words. */
1450 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
1451 /* Different ABIs have different maximum alignments. */
1452 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
1454 /* The APCS ABI only requires word alignment. */
1455 align
= INT_REGISTER_SIZE
;
1459 /* The AAPCS requires at most doubleword alignment. */
1460 if (align
> INT_REGISTER_SIZE
* 2)
1461 align
= INT_REGISTER_SIZE
* 2;
1464 /* Push stack padding for dowubleword alignment. */
1465 if (nstack
& (align
- 1))
1467 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1468 nstack
+= INT_REGISTER_SIZE
;
1471 /* Doubleword aligned quantities must go in even register pairs. */
1472 if (argreg
<= ARM_LAST_ARG_REGNUM
1473 && align
> INT_REGISTER_SIZE
1477 /* If the argument is a pointer to a function, and it is a
1478 Thumb function, create a LOCAL copy of the value and set
1479 the THUMB bit in it. */
1480 if (TYPE_CODE_PTR
== typecode
1481 && target_type
!= NULL
1482 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1484 CORE_ADDR regval
= extract_unsigned_integer (val
, len
);
1485 if (arm_pc_is_thumb (regval
))
1488 store_unsigned_integer (val
, len
, MAKE_THUMB_ADDR (regval
));
1492 /* Copy the argument to general registers or the stack in
1493 register-sized pieces. Large arguments are split between
1494 registers and stack. */
1497 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
1499 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1501 /* The argument is being passed in a general purpose
1503 CORE_ADDR regval
= extract_unsigned_integer (val
, partial_len
);
1504 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1505 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
1507 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1509 gdbarch_register_name
1511 phex (regval
, INT_REGISTER_SIZE
));
1512 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1517 /* Push the arguments onto the stack. */
1519 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1521 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1522 nstack
+= INT_REGISTER_SIZE
;
1529 /* If we have an odd number of words to push, then decrement the stack
1530 by one word now, so first stack argument will be dword aligned. */
1537 write_memory (sp
, si
->data
, si
->len
);
1538 si
= pop_stack_item (si
);
1541 /* Finally, update teh SP register. */
1542 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1548 /* Always align the frame to an 8-byte boundary. This is required on
1549 some platforms and harmless on the rest. */
1552 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1554 /* Align the stack to eight bytes. */
1555 return sp
& ~ (CORE_ADDR
) 7;
1559 print_fpu_flags (int flags
)
1561 if (flags
& (1 << 0))
1562 fputs ("IVO ", stdout
);
1563 if (flags
& (1 << 1))
1564 fputs ("DVZ ", stdout
);
1565 if (flags
& (1 << 2))
1566 fputs ("OFL ", stdout
);
1567 if (flags
& (1 << 3))
1568 fputs ("UFL ", stdout
);
1569 if (flags
& (1 << 4))
1570 fputs ("INX ", stdout
);
1574 /* Print interesting information about the floating point processor
1575 (if present) or emulator. */
1577 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1578 struct frame_info
*frame
, const char *args
)
1580 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
1583 type
= (status
>> 24) & 127;
1584 if (status
& (1 << 31))
1585 printf (_("Hardware FPU type %d\n"), type
);
1587 printf (_("Software FPU type %d\n"), type
);
1588 /* i18n: [floating point unit] mask */
1589 fputs (_("mask: "), stdout
);
1590 print_fpu_flags (status
>> 16);
1591 /* i18n: [floating point unit] flags */
1592 fputs (_("flags: "), stdout
);
1593 print_fpu_flags (status
);
1596 /* Return the GDB type object for the "standard" data type of data in
1599 static struct type
*
1600 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
1602 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1603 return builtin_type_arm_ext
;
1604 else if (regnum
== ARM_SP_REGNUM
)
1605 return builtin_type (gdbarch
)->builtin_data_ptr
;
1606 else if (regnum
== ARM_PC_REGNUM
)
1607 return builtin_type (gdbarch
)->builtin_func_ptr
;
1608 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
1609 /* These registers are only supported on targets which supply
1610 an XML description. */
1611 return builtin_type_int0
;
1613 return builtin_type_uint32
;
1616 /* Map a DWARF register REGNUM onto the appropriate GDB register
1620 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
1622 /* Core integer regs. */
1623 if (reg
>= 0 && reg
<= 15)
1626 /* Legacy FPA encoding. These were once used in a way which
1627 overlapped with VFP register numbering, so their use is
1628 discouraged, but GDB doesn't support the ARM toolchain
1629 which used them for VFP. */
1630 if (reg
>= 16 && reg
<= 23)
1631 return ARM_F0_REGNUM
+ reg
- 16;
1633 /* New assignments for the FPA registers. */
1634 if (reg
>= 96 && reg
<= 103)
1635 return ARM_F0_REGNUM
+ reg
- 96;
1637 /* WMMX register assignments. */
1638 if (reg
>= 104 && reg
<= 111)
1639 return ARM_WCGR0_REGNUM
+ reg
- 104;
1641 if (reg
>= 112 && reg
<= 127)
1642 return ARM_WR0_REGNUM
+ reg
- 112;
1644 if (reg
>= 192 && reg
<= 199)
1645 return ARM_WC0_REGNUM
+ reg
- 192;
1650 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1652 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
1655 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
1657 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
1658 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
1660 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
1661 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
1663 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
1664 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
1666 if (reg
< NUM_GREGS
)
1667 return SIM_ARM_R0_REGNUM
+ reg
;
1670 if (reg
< NUM_FREGS
)
1671 return SIM_ARM_FP0_REGNUM
+ reg
;
1674 if (reg
< NUM_SREGS
)
1675 return SIM_ARM_FPS_REGNUM
+ reg
;
1678 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
1681 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1682 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1683 It is thought that this is is the floating-point register format on
1684 little-endian systems. */
1687 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
1688 void *dbl
, int endianess
)
1692 if (endianess
== BFD_ENDIAN_BIG
)
1693 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1695 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1697 floatformat_from_doublest (fmt
, &d
, dbl
);
1701 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
1706 floatformat_to_doublest (fmt
, ptr
, &d
);
1707 if (endianess
== BFD_ENDIAN_BIG
)
1708 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1710 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1715 condition_true (unsigned long cond
, unsigned long status_reg
)
1717 if (cond
== INST_AL
|| cond
== INST_NV
)
1723 return ((status_reg
& FLAG_Z
) != 0);
1725 return ((status_reg
& FLAG_Z
) == 0);
1727 return ((status_reg
& FLAG_C
) != 0);
1729 return ((status_reg
& FLAG_C
) == 0);
1731 return ((status_reg
& FLAG_N
) != 0);
1733 return ((status_reg
& FLAG_N
) == 0);
1735 return ((status_reg
& FLAG_V
) != 0);
1737 return ((status_reg
& FLAG_V
) == 0);
1739 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1741 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1743 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1745 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1747 return (((status_reg
& FLAG_Z
) == 0) &&
1748 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1750 return (((status_reg
& FLAG_Z
) != 0) ||
1751 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1756 /* Support routines for single stepping. Calculate the next PC value. */
1757 #define submask(x) ((1L << ((x) + 1)) - 1)
1758 #define bit(obj,st) (((obj) >> (st)) & 1)
1759 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1760 #define sbits(obj,st,fn) \
1761 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1762 #define BranchDest(addr,instr) \
1763 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1766 static unsigned long
1767 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
1768 unsigned long pc_val
, unsigned long status_reg
)
1770 unsigned long res
, shift
;
1771 int rm
= bits (inst
, 0, 3);
1772 unsigned long shifttype
= bits (inst
, 5, 6);
1776 int rs
= bits (inst
, 8, 11);
1777 shift
= (rs
== 15 ? pc_val
+ 8
1778 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
1781 shift
= bits (inst
, 7, 11);
1784 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1785 + (bit (inst
, 4) ? 12 : 8))
1786 : get_frame_register_unsigned (frame
, rm
));
1791 res
= shift
>= 32 ? 0 : res
<< shift
;
1795 res
= shift
>= 32 ? 0 : res
>> shift
;
1801 res
= ((res
& 0x80000000L
)
1802 ? ~((~res
) >> shift
) : res
>> shift
);
1805 case 3: /* ROR/RRX */
1808 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1810 res
= (res
>> shift
) | (res
<< (32 - shift
));
1814 return res
& 0xffffffff;
1817 /* Return number of 1-bits in VAL. */
1820 bitcount (unsigned long val
)
1823 for (nbits
= 0; val
!= 0; nbits
++)
1824 val
&= val
- 1; /* delete rightmost 1-bit in val */
1829 thumb_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1831 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1832 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1833 unsigned short inst1
= read_memory_unsigned_integer (pc
, 2);
1834 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1835 unsigned long offset
;
1837 if (gdbarch_byte_order_for_code (gdbarch
) != gdbarch_byte_order (gdbarch
))
1838 inst1
= SWAP_SHORT (inst1
);
1840 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1844 /* Fetch the saved PC from the stack. It's stored above
1845 all of the other registers. */
1846 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
1847 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
1848 nextpc
= (CORE_ADDR
) read_memory_unsigned_integer (sp
+ offset
, 4);
1849 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1851 error (_("Infinite loop detected"));
1853 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1855 unsigned long status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
1856 unsigned long cond
= bits (inst1
, 8, 11);
1857 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1858 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1860 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1862 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1864 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link, and blx */
1866 unsigned short inst2
= read_memory_unsigned_integer (pc
+ 2, 2);
1867 if (gdbarch_byte_order_for_code (gdbarch
) != gdbarch_byte_order (gdbarch
))
1868 inst2
= SWAP_SHORT (inst2
);
1869 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1870 nextpc
= pc_val
+ offset
;
1871 /* For BLX make sure to clear the low bits. */
1872 if (bits (inst2
, 11, 12) == 1)
1873 nextpc
= nextpc
& 0xfffffffc;
1875 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
1877 if (bits (inst1
, 3, 6) == 0x0f)
1880 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
1882 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1884 error (_("Infinite loop detected"));
1891 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1893 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1894 unsigned long pc_val
;
1895 unsigned long this_instr
;
1896 unsigned long status
;
1899 if (arm_frame_is_thumb (frame
))
1900 return thumb_get_next_pc (frame
, pc
);
1902 pc_val
= (unsigned long) pc
;
1903 this_instr
= read_memory_unsigned_integer (pc
, 4);
1905 if (gdbarch_byte_order_for_code (gdbarch
) != gdbarch_byte_order (gdbarch
))
1906 this_instr
= SWAP_INT (this_instr
);
1908 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
1909 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1911 if (bits (this_instr
, 28, 31) == INST_NV
)
1912 switch (bits (this_instr
, 24, 27))
1917 /* Branch with Link and change to Thumb. */
1918 nextpc
= BranchDest (pc
, this_instr
);
1919 nextpc
|= bit (this_instr
, 24) << 1;
1921 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1923 error (_("Infinite loop detected"));
1929 /* Coprocessor register transfer. */
1930 if (bits (this_instr
, 12, 15) == 15)
1931 error (_("Invalid update to pc in instruction"));
1934 else if (condition_true (bits (this_instr
, 28, 31), status
))
1936 switch (bits (this_instr
, 24, 27))
1939 case 0x1: /* data processing */
1943 unsigned long operand1
, operand2
, result
= 0;
1947 if (bits (this_instr
, 12, 15) != 15)
1950 if (bits (this_instr
, 22, 25) == 0
1951 && bits (this_instr
, 4, 7) == 9) /* multiply */
1952 error (_("Invalid update to pc in instruction"));
1954 /* BX <reg>, BLX <reg> */
1955 if (bits (this_instr
, 4, 27) == 0x12fff1
1956 || bits (this_instr
, 4, 27) == 0x12fff3)
1958 rn
= bits (this_instr
, 0, 3);
1959 result
= (rn
== 15) ? pc_val
+ 8
1960 : get_frame_register_unsigned (frame
, rn
);
1961 nextpc
= (CORE_ADDR
) gdbarch_addr_bits_remove
1965 error (_("Infinite loop detected"));
1970 /* Multiply into PC */
1971 c
= (status
& FLAG_C
) ? 1 : 0;
1972 rn
= bits (this_instr
, 16, 19);
1973 operand1
= (rn
== 15) ? pc_val
+ 8
1974 : get_frame_register_unsigned (frame
, rn
);
1976 if (bit (this_instr
, 25))
1978 unsigned long immval
= bits (this_instr
, 0, 7);
1979 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1980 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1983 else /* operand 2 is a shifted register */
1984 operand2
= shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
);
1986 switch (bits (this_instr
, 21, 24))
1989 result
= operand1
& operand2
;
1993 result
= operand1
^ operand2
;
1997 result
= operand1
- operand2
;
2001 result
= operand2
- operand1
;
2005 result
= operand1
+ operand2
;
2009 result
= operand1
+ operand2
+ c
;
2013 result
= operand1
- operand2
+ c
;
2017 result
= operand2
- operand1
+ c
;
2023 case 0xb: /* tst, teq, cmp, cmn */
2024 result
= (unsigned long) nextpc
;
2028 result
= operand1
| operand2
;
2032 /* Always step into a function. */
2037 result
= operand1
& ~operand2
;
2044 nextpc
= (CORE_ADDR
) gdbarch_addr_bits_remove
2048 error (_("Infinite loop detected"));
2053 case 0x5: /* data transfer */
2056 if (bit (this_instr
, 20))
2059 if (bits (this_instr
, 12, 15) == 15)
2065 if (bit (this_instr
, 22))
2066 error (_("Invalid update to pc in instruction"));
2068 /* byte write to PC */
2069 rn
= bits (this_instr
, 16, 19);
2070 base
= (rn
== 15) ? pc_val
+ 8
2071 : get_frame_register_unsigned (frame
, rn
);
2072 if (bit (this_instr
, 24))
2075 int c
= (status
& FLAG_C
) ? 1 : 0;
2076 unsigned long offset
=
2077 (bit (this_instr
, 25)
2078 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
2079 : bits (this_instr
, 0, 11));
2081 if (bit (this_instr
, 23))
2086 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
2089 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
2092 error (_("Infinite loop detected"));
2098 case 0x9: /* block transfer */
2099 if (bit (this_instr
, 20))
2102 if (bit (this_instr
, 15))
2107 if (bit (this_instr
, 23))
2110 unsigned long reglist
= bits (this_instr
, 0, 14);
2111 offset
= bitcount (reglist
) * 4;
2112 if (bit (this_instr
, 24)) /* pre */
2115 else if (bit (this_instr
, 24))
2119 unsigned long rn_val
=
2120 get_frame_register_unsigned (frame
,
2121 bits (this_instr
, 16, 19));
2123 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
2127 nextpc
= gdbarch_addr_bits_remove
2130 error (_("Infinite loop detected"));
2135 case 0xb: /* branch & link */
2136 case 0xa: /* branch */
2138 nextpc
= BranchDest (pc
, this_instr
);
2140 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
2142 error (_("Infinite loop detected"));
2148 case 0xe: /* coproc ops */
2153 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
2161 /* single_step() is called just before we want to resume the inferior,
2162 if we want to single-step it but there is no hardware or kernel
2163 single-step support. We find the target of the coming instruction
2164 and breakpoint it. */
2167 arm_software_single_step (struct frame_info
*frame
)
2169 /* NOTE: This may insert the wrong breakpoint instruction when
2170 single-stepping over a mode-changing instruction, if the
2171 CPSR heuristics are used. */
2173 CORE_ADDR next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
2174 insert_single_step_breakpoint (next_pc
);
2179 #include "bfd-in2.h"
2180 #include "libcoff.h"
2183 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
2185 if (arm_pc_is_thumb (memaddr
))
2187 static asymbol
*asym
;
2188 static combined_entry_type ce
;
2189 static struct coff_symbol_struct csym
;
2190 static struct bfd fake_bfd
;
2191 static bfd_target fake_target
;
2193 if (csym
.native
== NULL
)
2195 /* Create a fake symbol vector containing a Thumb symbol.
2196 This is solely so that the code in print_insn_little_arm()
2197 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2198 the presence of a Thumb symbol and switch to decoding
2199 Thumb instructions. */
2201 fake_target
.flavour
= bfd_target_coff_flavour
;
2202 fake_bfd
.xvec
= &fake_target
;
2203 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
2205 csym
.symbol
.the_bfd
= &fake_bfd
;
2206 csym
.symbol
.name
= "fake";
2207 asym
= (asymbol
*) & csym
;
2210 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
2211 info
->symbols
= &asym
;
2214 info
->symbols
= NULL
;
2216 if (info
->endian
== BFD_ENDIAN_BIG
)
2217 return print_insn_big_arm (memaddr
, info
);
2219 return print_insn_little_arm (memaddr
, info
);
2222 /* The following define instruction sequences that will cause ARM
2223 cpu's to take an undefined instruction trap. These are used to
2224 signal a breakpoint to GDB.
2226 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2227 modes. A different instruction is required for each mode. The ARM
2228 cpu's can also be big or little endian. Thus four different
2229 instructions are needed to support all cases.
2231 Note: ARMv4 defines several new instructions that will take the
2232 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2233 not in fact add the new instructions. The new undefined
2234 instructions in ARMv4 are all instructions that had no defined
2235 behaviour in earlier chips. There is no guarantee that they will
2236 raise an exception, but may be treated as NOP's. In practice, it
2237 may only safe to rely on instructions matching:
2239 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2240 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2241 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2243 Even this may only true if the condition predicate is true. The
2244 following use a condition predicate of ALWAYS so it is always TRUE.
2246 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2247 and NetBSD all use a software interrupt rather than an undefined
2248 instruction to force a trap. This can be handled by by the
2249 abi-specific code during establishment of the gdbarch vector. */
2251 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2252 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2253 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
2254 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
2256 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
2257 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
2258 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2259 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2261 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2262 the program counter value to determine whether a 16-bit or 32-bit
2263 breakpoint should be used. It returns a pointer to a string of
2264 bytes that encode a breakpoint instruction, stores the length of
2265 the string to *lenptr, and adjusts the program counter (if
2266 necessary) to point to the actual memory location where the
2267 breakpoint should be inserted. */
2269 static const unsigned char *
2270 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
2272 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2274 if (arm_pc_is_thumb (*pcptr
))
2276 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2277 *lenptr
= tdep
->thumb_breakpoint_size
;
2278 return tdep
->thumb_breakpoint
;
2282 *lenptr
= tdep
->arm_breakpoint_size
;
2283 return tdep
->arm_breakpoint
;
2287 /* Extract from an array REGBUF containing the (raw) register state a
2288 function return value of type TYPE, and copy that, in virtual
2289 format, into VALBUF. */
2292 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
2295 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
2297 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2299 switch (gdbarch_tdep (gdbarch
)->fp_model
)
2303 /* The value is in register F0 in internal format. We need to
2304 extract the raw value and then convert it to the desired
2306 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
2308 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
2309 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
2310 valbuf
, gdbarch_byte_order (gdbarch
));
2314 case ARM_FLOAT_SOFT_FPA
:
2315 case ARM_FLOAT_SOFT_VFP
:
2316 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
2317 if (TYPE_LENGTH (type
) > 4)
2318 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
2319 valbuf
+ INT_REGISTER_SIZE
);
2324 (__FILE__
, __LINE__
,
2325 _("arm_extract_return_value: Floating point model not supported"));
2329 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2330 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2331 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2332 || TYPE_CODE (type
) == TYPE_CODE_PTR
2333 || TYPE_CODE (type
) == TYPE_CODE_REF
2334 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2336 /* If the the type is a plain integer, then the access is
2337 straight-forward. Otherwise we have to play around a bit more. */
2338 int len
= TYPE_LENGTH (type
);
2339 int regno
= ARM_A1_REGNUM
;
2344 /* By using store_unsigned_integer we avoid having to do
2345 anything special for small big-endian values. */
2346 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2347 store_unsigned_integer (valbuf
,
2348 (len
> INT_REGISTER_SIZE
2349 ? INT_REGISTER_SIZE
: len
),
2351 len
-= INT_REGISTER_SIZE
;
2352 valbuf
+= INT_REGISTER_SIZE
;
2357 /* For a structure or union the behaviour is as if the value had
2358 been stored to word-aligned memory and then loaded into
2359 registers with 32-bit load instruction(s). */
2360 int len
= TYPE_LENGTH (type
);
2361 int regno
= ARM_A1_REGNUM
;
2362 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2366 regcache_cooked_read (regs
, regno
++, tmpbuf
);
2367 memcpy (valbuf
, tmpbuf
,
2368 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2369 len
-= INT_REGISTER_SIZE
;
2370 valbuf
+= INT_REGISTER_SIZE
;
2376 /* Will a function return an aggregate type in memory or in a
2377 register? Return 0 if an aggregate type can be returned in a
2378 register, 1 if it must be returned in memory. */
2381 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2384 enum type_code code
;
2386 CHECK_TYPEDEF (type
);
2388 /* In the ARM ABI, "integer" like aggregate types are returned in
2389 registers. For an aggregate type to be integer like, its size
2390 must be less than or equal to INT_REGISTER_SIZE and the
2391 offset of each addressable subfield must be zero. Note that bit
2392 fields are not addressable, and all addressable subfields of
2393 unions always start at offset zero.
2395 This function is based on the behaviour of GCC 2.95.1.
2396 See: gcc/arm.c: arm_return_in_memory() for details.
2398 Note: All versions of GCC before GCC 2.95.2 do not set up the
2399 parameters correctly for a function returning the following
2400 structure: struct { float f;}; This should be returned in memory,
2401 not a register. Richard Earnshaw sent me a patch, but I do not
2402 know of any way to detect if a function like the above has been
2403 compiled with the correct calling convention. */
2405 /* All aggregate types that won't fit in a register must be returned
2407 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
2412 /* The AAPCS says all aggregates not larger than a word are returned
2414 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
2417 /* The only aggregate types that can be returned in a register are
2418 structs and unions. Arrays must be returned in memory. */
2419 code
= TYPE_CODE (type
);
2420 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2425 /* Assume all other aggregate types can be returned in a register.
2426 Run a check for structures, unions and arrays. */
2429 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2432 /* Need to check if this struct/union is "integer" like. For
2433 this to be true, its size must be less than or equal to
2434 INT_REGISTER_SIZE and the offset of each addressable
2435 subfield must be zero. Note that bit fields are not
2436 addressable, and unions always start at offset zero. If any
2437 of the subfields is a floating point type, the struct/union
2438 cannot be an integer type. */
2440 /* For each field in the object, check:
2441 1) Is it FP? --> yes, nRc = 1;
2442 2) Is it addressable (bitpos != 0) and
2443 not packed (bitsize == 0)?
2447 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2449 enum type_code field_type_code
;
2450 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, i
)));
2452 /* Is it a floating point type field? */
2453 if (field_type_code
== TYPE_CODE_FLT
)
2459 /* If bitpos != 0, then we have to care about it. */
2460 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2462 /* Bitfields are not addressable. If the field bitsize is
2463 zero, then the field is not packed. Hence it cannot be
2464 a bitfield or any other packed type. */
2465 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2477 /* Write into appropriate registers a function return value of type
2478 TYPE, given in virtual format. */
2481 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
2482 const gdb_byte
*valbuf
)
2484 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
2486 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2488 char buf
[MAX_REGISTER_SIZE
];
2490 switch (gdbarch_tdep (gdbarch
)->fp_model
)
2494 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
2495 gdbarch_byte_order (gdbarch
));
2496 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
2499 case ARM_FLOAT_SOFT_FPA
:
2500 case ARM_FLOAT_SOFT_VFP
:
2501 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
2502 if (TYPE_LENGTH (type
) > 4)
2503 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
2504 valbuf
+ INT_REGISTER_SIZE
);
2509 (__FILE__
, __LINE__
,
2510 _("arm_store_return_value: Floating point model not supported"));
2514 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2515 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2516 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2517 || TYPE_CODE (type
) == TYPE_CODE_PTR
2518 || TYPE_CODE (type
) == TYPE_CODE_REF
2519 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2521 if (TYPE_LENGTH (type
) <= 4)
2523 /* Values of one word or less are zero/sign-extended and
2525 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2526 LONGEST val
= unpack_long (type
, valbuf
);
2528 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, val
);
2529 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
2533 /* Integral values greater than one word are stored in consecutive
2534 registers starting with r0. This will always be a multiple of
2535 the regiser size. */
2536 int len
= TYPE_LENGTH (type
);
2537 int regno
= ARM_A1_REGNUM
;
2541 regcache_cooked_write (regs
, regno
++, valbuf
);
2542 len
-= INT_REGISTER_SIZE
;
2543 valbuf
+= INT_REGISTER_SIZE
;
2549 /* For a structure or union the behaviour is as if the value had
2550 been stored to word-aligned memory and then loaded into
2551 registers with 32-bit load instruction(s). */
2552 int len
= TYPE_LENGTH (type
);
2553 int regno
= ARM_A1_REGNUM
;
2554 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2558 memcpy (tmpbuf
, valbuf
,
2559 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2560 regcache_cooked_write (regs
, regno
++, tmpbuf
);
2561 len
-= INT_REGISTER_SIZE
;
2562 valbuf
+= INT_REGISTER_SIZE
;
2568 /* Handle function return values. */
2570 static enum return_value_convention
2571 arm_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2572 struct type
*valtype
, struct regcache
*regcache
,
2573 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2575 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2577 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2578 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2579 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2581 if (tdep
->struct_return
== pcc_struct_return
2582 || arm_return_in_memory (gdbarch
, valtype
))
2583 return RETURN_VALUE_STRUCT_CONVENTION
;
2587 arm_store_return_value (valtype
, regcache
, writebuf
);
2590 arm_extract_return_value (valtype
, regcache
, readbuf
);
2592 return RETURN_VALUE_REGISTER_CONVENTION
;
2597 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2600 char buf
[INT_REGISTER_SIZE
];
2601 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (frame
));
2603 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
2605 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2609 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
);
2613 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
2614 return the target PC. Otherwise return 0. */
2617 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
2621 CORE_ADDR start_addr
;
2623 /* Find the starting address and name of the function containing the PC. */
2624 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2627 /* If PC is in a Thumb call or return stub, return the address of the
2628 target PC, which is in a register. The thunk functions are called
2629 _call_via_xx, where x is the register name. The possible names
2630 are r0-r9, sl, fp, ip, sp, and lr. */
2631 if (strncmp (name
, "_call_via_", 10) == 0)
2633 /* Use the name suffix to determine which register contains the
2635 static char *table
[15] =
2636 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2637 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2640 int offset
= strlen (name
) - 2;
2642 for (regno
= 0; regno
<= 14; regno
++)
2643 if (strcmp (&name
[offset
], table
[regno
]) == 0)
2644 return get_frame_register_unsigned (frame
, regno
);
2647 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
2648 non-interworking calls to foo. We could decode the stubs
2649 to find the target but it's easier to use the symbol table. */
2650 namelen
= strlen (name
);
2651 if (name
[0] == '_' && name
[1] == '_'
2652 && ((namelen
> 2 + strlen ("_from_thumb")
2653 && strncmp (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb",
2654 strlen ("_from_thumb")) == 0)
2655 || (namelen
> 2 + strlen ("_from_arm")
2656 && strncmp (name
+ namelen
- strlen ("_from_arm"), "_from_arm",
2657 strlen ("_from_arm")) == 0)))
2660 int target_len
= namelen
- 2;
2661 struct minimal_symbol
*minsym
;
2662 struct objfile
*objfile
;
2663 struct obj_section
*sec
;
2665 if (name
[namelen
- 1] == 'b')
2666 target_len
-= strlen ("_from_thumb");
2668 target_len
-= strlen ("_from_arm");
2670 target_name
= alloca (target_len
+ 1);
2671 memcpy (target_name
, name
+ 2, target_len
);
2672 target_name
[target_len
] = '\0';
2674 sec
= find_pc_section (pc
);
2675 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
2676 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
2678 return SYMBOL_VALUE_ADDRESS (minsym
);
2683 return 0; /* not a stub */
2687 set_arm_command (char *args
, int from_tty
)
2689 printf_unfiltered (_("\
2690 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2691 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
2695 show_arm_command (char *args
, int from_tty
)
2697 cmd_show_list (showarmcmdlist
, from_tty
, "");
2701 arm_update_current_architecture (void)
2703 struct gdbarch_info info
;
2705 /* If the current architecture is not ARM, we have nothing to do. */
2706 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_arm
)
2709 /* Update the architecture. */
2710 gdbarch_info_init (&info
);
2712 if (!gdbarch_update_p (info
))
2713 internal_error (__FILE__
, __LINE__
, "could not update architecture");
2717 set_fp_model_sfunc (char *args
, int from_tty
,
2718 struct cmd_list_element
*c
)
2720 enum arm_float_model fp_model
;
2722 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
2723 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
2725 arm_fp_model
= fp_model
;
2729 if (fp_model
== ARM_FLOAT_LAST
)
2730 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
2733 arm_update_current_architecture ();
2737 show_fp_model (struct ui_file
*file
, int from_tty
,
2738 struct cmd_list_element
*c
, const char *value
)
2740 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
2742 if (arm_fp_model
== ARM_FLOAT_AUTO
2743 && gdbarch_bfd_arch_info (target_gdbarch
)->arch
== bfd_arch_arm
)
2744 fprintf_filtered (file
, _("\
2745 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2746 fp_model_strings
[tdep
->fp_model
]);
2748 fprintf_filtered (file
, _("\
2749 The current ARM floating point model is \"%s\".\n"),
2750 fp_model_strings
[arm_fp_model
]);
2754 arm_set_abi (char *args
, int from_tty
,
2755 struct cmd_list_element
*c
)
2757 enum arm_abi_kind arm_abi
;
2759 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
2760 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
2762 arm_abi_global
= arm_abi
;
2766 if (arm_abi
== ARM_ABI_LAST
)
2767 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
2770 arm_update_current_architecture ();
2774 arm_show_abi (struct ui_file
*file
, int from_tty
,
2775 struct cmd_list_element
*c
, const char *value
)
2777 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
2779 if (arm_abi_global
== ARM_ABI_AUTO
2780 && gdbarch_bfd_arch_info (target_gdbarch
)->arch
== bfd_arch_arm
)
2781 fprintf_filtered (file
, _("\
2782 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2783 arm_abi_strings
[tdep
->arm_abi
]);
2785 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
2790 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
2791 struct cmd_list_element
*c
, const char *value
)
2793 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
2795 fprintf_filtered (file
, _("\
2796 The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"),
2797 arm_fallback_mode_string
);
2801 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
2802 struct cmd_list_element
*c
, const char *value
)
2804 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
2806 fprintf_filtered (file
, _("\
2807 The current execution mode assumed (even when symbols are available) is \"%s\".\n"),
2808 arm_force_mode_string
);
2811 /* If the user changes the register disassembly style used for info
2812 register and other commands, we have to also switch the style used
2813 in opcodes for disassembly output. This function is run in the "set
2814 arm disassembly" command, and does that. */
2817 set_disassembly_style_sfunc (char *args
, int from_tty
,
2818 struct cmd_list_element
*c
)
2820 set_disassembly_style ();
2823 /* Return the ARM register name corresponding to register I. */
2825 arm_register_name (struct gdbarch
*gdbarch
, int i
)
2827 if (i
>= ARRAY_SIZE (arm_register_names
))
2828 /* These registers are only supported on targets which supply
2829 an XML description. */
2832 return arm_register_names
[i
];
2836 set_disassembly_style (void)
2840 /* Find the style that the user wants. */
2841 for (current
= 0; current
< num_disassembly_options
; current
++)
2842 if (disassembly_style
== valid_disassembly_styles
[current
])
2844 gdb_assert (current
< num_disassembly_options
);
2846 /* Synchronize the disassembler. */
2847 set_arm_regname_option (current
);
2850 /* Test whether the coff symbol specific value corresponds to a Thumb
2854 coff_sym_is_thumb (int val
)
2856 return (val
== C_THUMBEXT
||
2857 val
== C_THUMBSTAT
||
2858 val
== C_THUMBEXTFUNC
||
2859 val
== C_THUMBSTATFUNC
||
2860 val
== C_THUMBLABEL
);
2863 /* arm_coff_make_msymbol_special()
2864 arm_elf_make_msymbol_special()
2866 These functions test whether the COFF or ELF symbol corresponds to
2867 an address in thumb code, and set a "special" bit in a minimal
2868 symbol to indicate that it does. */
2871 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2873 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2875 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2877 MSYMBOL_SET_SPECIAL (msym
);
2881 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2883 if (coff_sym_is_thumb (val
))
2884 MSYMBOL_SET_SPECIAL (msym
);
2888 arm_objfile_data_cleanup (struct objfile
*objfile
, void *arg
)
2890 struct arm_per_objfile
*data
= arg
;
2893 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
2894 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
2898 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
2901 const char *name
= bfd_asymbol_name (sym
);
2902 struct arm_per_objfile
*data
;
2903 VEC(arm_mapping_symbol_s
) **map_p
;
2904 struct arm_mapping_symbol new_map_sym
;
2906 gdb_assert (name
[0] == '$');
2907 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
2910 data
= objfile_data (objfile
, arm_objfile_data_key
);
2913 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
2914 struct arm_per_objfile
);
2915 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
2916 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2917 objfile
->obfd
->section_count
,
2918 VEC(arm_mapping_symbol_s
) *);
2920 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
2922 new_map_sym
.value
= sym
->value
;
2923 new_map_sym
.type
= name
[1];
2925 /* Assume that most mapping symbols appear in order of increasing
2926 value. If they were randomly distributed, it would be faster to
2927 always push here and then sort at first use. */
2928 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
2930 struct arm_mapping_symbol
*prev_map_sym
;
2932 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
2933 if (prev_map_sym
->value
>= sym
->value
)
2936 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
2937 arm_compare_mapping_symbols
);
2938 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
2943 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
2947 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2949 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
2951 /* If necessary, set the T bit. */
2955 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
2956 if (arm_pc_is_thumb (pc
))
2957 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
, val
| CPSR_T
);
2959 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
2960 val
& ~(ULONGEST
) CPSR_T
);
2964 static struct value
*
2965 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
2967 const int *reg_p
= baton
;
2968 return value_of_register (*reg_p
, frame
);
2971 static enum gdb_osabi
2972 arm_elf_osabi_sniffer (bfd
*abfd
)
2974 unsigned int elfosabi
;
2975 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2977 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2979 if (elfosabi
== ELFOSABI_ARM
)
2980 /* GNU tools use this value. Check note sections in this case,
2982 bfd_map_over_sections (abfd
,
2983 generic_elf_osabi_sniff_abi_tag_sections
,
2986 /* Anything else will be handled by the generic ELF sniffer. */
2991 /* Initialize the current architecture based on INFO. If possible,
2992 re-use an architecture from ARCHES, which is a list of
2993 architectures already created during this debugging session.
2995 Called e.g. at program startup, when reading a core file, and when
2996 reading a binary file. */
2998 static struct gdbarch
*
2999 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3001 struct gdbarch_tdep
*tdep
;
3002 struct gdbarch
*gdbarch
;
3003 struct gdbarch_list
*best_arch
;
3004 enum arm_abi_kind arm_abi
= arm_abi_global
;
3005 enum arm_float_model fp_model
= arm_fp_model
;
3006 struct tdesc_arch_data
*tdesc_data
= NULL
;
3008 int have_fpa_registers
= 1;
3010 /* Check any target description for validity. */
3011 if (tdesc_has_registers (info
.target_desc
))
3013 /* For most registers we require GDB's default names; but also allow
3014 the numeric names for sp / lr / pc, as a convenience. */
3015 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
3016 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
3017 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
3019 const struct tdesc_feature
*feature
;
3022 feature
= tdesc_find_feature (info
.target_desc
,
3023 "org.gnu.gdb.arm.core");
3024 if (feature
== NULL
)
3027 tdesc_data
= tdesc_data_alloc ();
3030 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
3031 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
3032 arm_register_names
[i
]);
3033 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
3036 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
3039 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
3042 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3043 ARM_PS_REGNUM
, "cpsr");
3047 tdesc_data_cleanup (tdesc_data
);
3051 feature
= tdesc_find_feature (info
.target_desc
,
3052 "org.gnu.gdb.arm.fpa");
3053 if (feature
!= NULL
)
3056 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
3057 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
3058 arm_register_names
[i
]);
3061 tdesc_data_cleanup (tdesc_data
);
3066 have_fpa_registers
= 0;
3068 feature
= tdesc_find_feature (info
.target_desc
,
3069 "org.gnu.gdb.xscale.iwmmxt");
3070 if (feature
!= NULL
)
3072 static const char *const iwmmxt_names
[] = {
3073 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
3074 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
3075 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
3076 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
3080 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
3082 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
3083 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
3085 /* Check for the control registers, but do not fail if they
3087 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
3088 tdesc_numbered_register (feature
, tdesc_data
, i
,
3089 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
3091 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
3093 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
3094 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
3098 tdesc_data_cleanup (tdesc_data
);
3104 /* If we have an object to base this architecture on, try to determine
3107 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
3109 int ei_osabi
, e_flags
;
3111 switch (bfd_get_flavour (info
.abfd
))
3113 case bfd_target_aout_flavour
:
3114 /* Assume it's an old APCS-style ABI. */
3115 arm_abi
= ARM_ABI_APCS
;
3118 case bfd_target_coff_flavour
:
3119 /* Assume it's an old APCS-style ABI. */
3121 arm_abi
= ARM_ABI_APCS
;
3124 case bfd_target_elf_flavour
:
3125 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
3126 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
3128 if (ei_osabi
== ELFOSABI_ARM
)
3130 /* GNU tools used to use this value, but do not for EABI
3131 objects. There's nowhere to tag an EABI version
3132 anyway, so assume APCS. */
3133 arm_abi
= ARM_ABI_APCS
;
3135 else if (ei_osabi
== ELFOSABI_NONE
)
3137 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
3141 case EF_ARM_EABI_UNKNOWN
:
3142 /* Assume GNU tools. */
3143 arm_abi
= ARM_ABI_APCS
;
3146 case EF_ARM_EABI_VER4
:
3147 case EF_ARM_EABI_VER5
:
3148 arm_abi
= ARM_ABI_AAPCS
;
3149 /* EABI binaries default to VFP float ordering. */
3150 if (fp_model
== ARM_FLOAT_AUTO
)
3151 fp_model
= ARM_FLOAT_SOFT_VFP
;
3155 /* Leave it as "auto". */
3156 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
3161 if (fp_model
== ARM_FLOAT_AUTO
)
3163 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
3165 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
3168 /* Leave it as "auto". Strictly speaking this case
3169 means FPA, but almost nobody uses that now, and
3170 many toolchains fail to set the appropriate bits
3171 for the floating-point model they use. */
3173 case EF_ARM_SOFT_FLOAT
:
3174 fp_model
= ARM_FLOAT_SOFT_FPA
;
3176 case EF_ARM_VFP_FLOAT
:
3177 fp_model
= ARM_FLOAT_VFP
;
3179 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
3180 fp_model
= ARM_FLOAT_SOFT_VFP
;
3185 if (e_flags
& EF_ARM_BE8
)
3186 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
3191 /* Leave it as "auto". */
3196 /* If there is already a candidate, use it. */
3197 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
3199 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
3201 if (arm_abi
!= ARM_ABI_AUTO
3202 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
3205 if (fp_model
!= ARM_FLOAT_AUTO
3206 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
3209 /* Found a match. */
3213 if (best_arch
!= NULL
)
3215 if (tdesc_data
!= NULL
)
3216 tdesc_data_cleanup (tdesc_data
);
3217 return best_arch
->gdbarch
;
3220 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
3221 gdbarch
= gdbarch_alloc (&info
, tdep
);
3223 /* Record additional information about the architecture we are defining.
3224 These are gdbarch discriminators, like the OSABI. */
3225 tdep
->arm_abi
= arm_abi
;
3226 tdep
->fp_model
= fp_model
;
3227 tdep
->have_fpa_registers
= have_fpa_registers
;
3230 switch (info
.byte_order_for_code
)
3232 case BFD_ENDIAN_BIG
:
3233 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
3234 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
3235 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
3236 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
3240 case BFD_ENDIAN_LITTLE
:
3241 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
3242 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
3243 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
3244 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
3249 internal_error (__FILE__
, __LINE__
,
3250 _("arm_gdbarch_init: bad byte order for float format"));
3253 /* On ARM targets char defaults to unsigned. */
3254 set_gdbarch_char_signed (gdbarch
, 0);
3256 /* This should be low enough for everything. */
3257 tdep
->lowest_pc
= 0x20;
3258 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
3260 /* The default, for both APCS and AAPCS, is to return small
3261 structures in registers. */
3262 tdep
->struct_return
= reg_struct_return
;
3264 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
3265 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
3267 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
3269 /* Frame handling. */
3270 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
3271 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
3272 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
3274 frame_base_set_default (gdbarch
, &arm_normal_base
);
3276 /* Address manipulation. */
3277 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
3278 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
3280 /* Advance PC across function entry code. */
3281 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
3283 /* Skip trampolines. */
3284 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
3286 /* The stack grows downward. */
3287 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3289 /* Breakpoint manipulation. */
3290 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
3292 /* Information about registers, etc. */
3293 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
3294 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
3295 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
3296 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
3297 set_gdbarch_register_type (gdbarch
, arm_register_type
);
3299 /* This "info float" is FPA-specific. Use the generic version if we
3301 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
3302 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
3304 /* Internal <-> external register number maps. */
3305 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
3306 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
3308 set_gdbarch_register_name (gdbarch
, arm_register_name
);
3310 /* Returning results. */
3311 set_gdbarch_return_value (gdbarch
, arm_return_value
);
3314 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
3316 /* Minsymbol frobbing. */
3317 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
3318 set_gdbarch_coff_make_msymbol_special (gdbarch
,
3319 arm_coff_make_msymbol_special
);
3320 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
3322 /* Virtual tables. */
3323 set_gdbarch_vbit_in_delta (gdbarch
, 1);
3325 /* Hook in the ABI-specific overrides, if they have been registered. */
3326 gdbarch_init_osabi (info
, gdbarch
);
3328 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
3330 /* Add some default predicates. */
3331 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
3332 dwarf2_append_unwinders (gdbarch
);
3333 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
3335 /* Now we have tuned the configuration, set a few final things,
3336 based on what the OS ABI has told us. */
3338 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
3339 binaries are always marked. */
3340 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
3341 tdep
->arm_abi
= ARM_ABI_APCS
;
3343 /* We used to default to FPA for generic ARM, but almost nobody
3344 uses that now, and we now provide a way for the user to force
3345 the model. So default to the most useful variant. */
3346 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
3347 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
3349 if (tdep
->jb_pc
>= 0)
3350 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
3352 /* Floating point sizes and format. */
3353 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
3354 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
3356 set_gdbarch_double_format
3357 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
3358 set_gdbarch_long_double_format
3359 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
3363 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
3364 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
3368 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
3370 /* Add standard register aliases. We add aliases even for those
3371 nanes which are used by the current architecture - it's simpler,
3372 and does no harm, since nothing ever lists user registers. */
3373 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
3374 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
3375 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
3381 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3383 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3388 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
3389 (unsigned long) tdep
->lowest_pc
);
3392 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
3395 _initialize_arm_tdep (void)
3397 struct ui_file
*stb
;
3399 struct cmd_list_element
*new_set
, *new_show
;
3400 const char *setname
;
3401 const char *setdesc
;
3402 const char *const *regnames
;
3404 static char *helptext
;
3405 char regdesc
[1024], *rdptr
= regdesc
;
3406 size_t rest
= sizeof (regdesc
);
3408 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
3410 arm_objfile_data_key
3411 = register_objfile_data_with_cleanup (arm_objfile_data_cleanup
);
3413 /* Register an ELF OS ABI sniffer for ARM binaries. */
3414 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
3415 bfd_target_elf_flavour
,
3416 arm_elf_osabi_sniffer
);
3418 /* Get the number of possible sets of register names defined in opcodes. */
3419 num_disassembly_options
= get_arm_regname_num_options ();
3421 /* Add root prefix command for all "set arm"/"show arm" commands. */
3422 add_prefix_cmd ("arm", no_class
, set_arm_command
,
3423 _("Various ARM-specific commands."),
3424 &setarmcmdlist
, "set arm ", 0, &setlist
);
3426 add_prefix_cmd ("arm", no_class
, show_arm_command
,
3427 _("Various ARM-specific commands."),
3428 &showarmcmdlist
, "show arm ", 0, &showlist
);
3430 /* Sync the opcode insn printer with our register viewer. */
3431 parse_arm_disassembler_option ("reg-names-std");
3433 /* Initialize the array that will be passed to
3434 add_setshow_enum_cmd(). */
3435 valid_disassembly_styles
3436 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
3437 for (i
= 0; i
< num_disassembly_options
; i
++)
3439 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
3440 valid_disassembly_styles
[i
] = setname
;
3441 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
3444 /* When we find the default names, tell the disassembler to use
3446 if (!strcmp (setname
, "std"))
3448 disassembly_style
= setname
;
3449 set_arm_regname_option (i
);
3452 /* Mark the end of valid options. */
3453 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
3455 /* Create the help text. */
3456 stb
= mem_fileopen ();
3457 fprintf_unfiltered (stb
, "%s%s%s",
3458 _("The valid values are:\n"),
3460 _("The default is \"std\"."));
3461 helptext
= ui_file_xstrdup (stb
, &length
);
3462 ui_file_delete (stb
);
3464 add_setshow_enum_cmd("disassembler", no_class
,
3465 valid_disassembly_styles
, &disassembly_style
,
3466 _("Set the disassembly style."),
3467 _("Show the disassembly style."),
3469 set_disassembly_style_sfunc
,
3470 NULL
, /* FIXME: i18n: The disassembly style is \"%s\". */
3471 &setarmcmdlist
, &showarmcmdlist
);
3473 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
3474 _("Set usage of ARM 32-bit mode."),
3475 _("Show usage of ARM 32-bit mode."),
3476 _("When off, a 26-bit PC will be used."),
3478 NULL
, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
3479 &setarmcmdlist
, &showarmcmdlist
);
3481 /* Add a command to allow the user to force the FPU model. */
3482 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
3483 _("Set the floating point type."),
3484 _("Show the floating point type."),
3485 _("auto - Determine the FP typefrom the OS-ABI.\n\
3486 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
3487 fpa - FPA co-processor (GCC compiled).\n\
3488 softvfp - Software FP with pure-endian doubles.\n\
3489 vfp - VFP co-processor."),
3490 set_fp_model_sfunc
, show_fp_model
,
3491 &setarmcmdlist
, &showarmcmdlist
);
3493 /* Add a command to allow the user to force the ABI. */
3494 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
3497 NULL
, arm_set_abi
, arm_show_abi
,
3498 &setarmcmdlist
, &showarmcmdlist
);
3500 /* Add two commands to allow the user to force the assumed
3502 add_setshow_enum_cmd ("fallback-mode", class_support
,
3503 arm_mode_strings
, &arm_fallback_mode_string
,
3504 _("Set the mode assumed when symbols are unavailable."),
3505 _("Show the mode assumed when symbols are unavailable."),
3506 NULL
, NULL
, arm_show_fallback_mode
,
3507 &setarmcmdlist
, &showarmcmdlist
);
3508 add_setshow_enum_cmd ("force-mode", class_support
,
3509 arm_mode_strings
, &arm_force_mode_string
,
3510 _("Set the mode assumed even when symbols are available."),
3511 _("Show the mode assumed even when symbols are available."),
3512 NULL
, NULL
, arm_show_force_mode
,
3513 &setarmcmdlist
, &showarmcmdlist
);
3515 /* Debugging flag. */
3516 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
3517 _("Set ARM debugging."),
3518 _("Show ARM debugging."),
3519 _("When on, arm-specific debugging is enabled."),
3521 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
3522 &setdebuglist
, &showdebuglist
);