1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "coff/internal.h" /* Internal format of COFF symbols in BFD */
30 #include "dis-asm.h" /* For register flavors. */
31 #include <ctype.h> /* for isupper () */
35 #include "solib-svr4.h"
37 /* Each OS has a different mechanism for accessing the various
38 registers stored in the sigcontext structure.
40 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
41 function pointer) which may be used to determine the addresses
42 of the various saved registers in the sigcontext structure.
44 For the ARM target, there are three parameters to this function.
45 The first is the pc value of the frame under consideration, the
46 second the stack pointer of this frame, and the last is the
47 register number to fetch.
49 If the tm.h file does not define this macro, then it's assumed that
50 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
53 When it comes time to multi-arching this code, see the identically
54 named machinery in ia64-tdep.c for an example of how it could be
55 done. It should not be necessary to modify the code below where
56 this macro is used. */
58 #ifdef SIGCONTEXT_REGISTER_ADDRESS
59 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
60 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
63 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
64 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
67 extern void _initialize_arm_tdep (void);
69 /* Number of different reg name sets (options). */
70 static int num_flavor_options
;
72 /* We have more registers than the disassembler as gdb can print the value
73 of special registers as well.
74 The general register names are overwritten by whatever is being used by
75 the disassembler at the moment. We also adjust the case of cpsr and fps. */
77 /* Initial value: Register names used in ARM's ISA documentation. */
78 static char * arm_register_name_strings
[] =
79 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
80 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
81 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
82 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
83 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
84 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
85 "fps", "cpsr" }; /* 24 25 */
86 static char **arm_register_names
= arm_register_name_strings
;
88 /* Valid register name flavors. */
89 static const char **valid_flavors
;
91 /* Disassembly flavor to use. Default to "std" register names. */
92 static const char *disassembly_flavor
;
93 static int current_option
; /* Index to that option in the opcodes table. */
95 /* This is used to keep the bfd arch_info in sync with the disassembly
97 static void set_disassembly_flavor_sfunc(char *, int,
98 struct cmd_list_element
*);
99 static void set_disassembly_flavor (void);
101 static void convert_from_extended (void *ptr
, void *dbl
);
103 /* Define other aspects of the stack frame. We keep the offsets of
104 all saved registers, 'cause we need 'em a lot! We also keep the
105 current size of the stack frame, and the offset of the frame
106 pointer from the stack pointer (for frameless functions, and when
107 we're still in the prologue of a function with a frame) */
109 struct frame_extra_info
116 /* Addresses for calling Thumb functions have the bit 0 set.
117 Here are some macros to test, set, or clear bit 0 of addresses. */
118 #define IS_THUMB_ADDR(addr) ((addr) & 1)
119 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
120 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
122 /* Will a function return an aggregate type in memory or in a
123 register? Return 0 if an aggregate type can be returned in a
124 register, 1 if it must be returned in memory. */
127 arm_use_struct_convention (int gcc_p
, struct type
*type
)
130 register enum type_code code
;
132 /* In the ARM ABI, "integer" like aggregate types are returned in
133 registers. For an aggregate type to be integer like, its size
134 must be less than or equal to REGISTER_SIZE and the offset of
135 each addressable subfield must be zero. Note that bit fields are
136 not addressable, and all addressable subfields of unions always
137 start at offset zero.
139 This function is based on the behaviour of GCC 2.95.1.
140 See: gcc/arm.c: arm_return_in_memory() for details.
142 Note: All versions of GCC before GCC 2.95.2 do not set up the
143 parameters correctly for a function returning the following
144 structure: struct { float f;}; This should be returned in memory,
145 not a register. Richard Earnshaw sent me a patch, but I do not
146 know of any way to detect if a function like the above has been
147 compiled with the correct calling convention. */
149 /* All aggregate types that won't fit in a register must be returned
151 if (TYPE_LENGTH (type
) > REGISTER_SIZE
)
156 /* The only aggregate types that can be returned in a register are
157 structs and unions. Arrays must be returned in memory. */
158 code
= TYPE_CODE (type
);
159 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
164 /* Assume all other aggregate types can be returned in a register.
165 Run a check for structures, unions and arrays. */
168 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
171 /* Need to check if this struct/union is "integer" like. For
172 this to be true, its size must be less than or equal to
173 REGISTER_SIZE and the offset of each addressable subfield
174 must be zero. Note that bit fields are not addressable, and
175 unions always start at offset zero. If any of the subfields
176 is a floating point type, the struct/union cannot be an
179 /* For each field in the object, check:
180 1) Is it FP? --> yes, nRc = 1;
181 2) Is it addressable (bitpos != 0) and
182 not packed (bitsize == 0)?
186 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
188 enum type_code field_type_code
;
189 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
191 /* Is it a floating point type field? */
192 if (field_type_code
== TYPE_CODE_FLT
)
198 /* If bitpos != 0, then we have to care about it. */
199 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
201 /* Bitfields are not addressable. If the field bitsize is
202 zero, then the field is not packed. Hence it cannot be
203 a bitfield or any other packed type. */
204 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
217 arm_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*thisframe
)
219 return (chain
!= 0 && (FRAME_SAVED_PC (thisframe
) >= LOWEST_PC
));
222 /* Set to true if the 32-bit mode is in use. */
226 /* Flag set by arm_fix_call_dummy that tells whether the target
227 function is a Thumb function. This flag is checked by
228 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
229 its use in valops.c) to pass the function address as an additional
232 static int target_is_thumb
;
234 /* Flag set by arm_fix_call_dummy that tells whether the calling
235 function is a Thumb function. This flag is checked by
236 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
238 static int caller_is_thumb
;
240 /* Determine if the program counter specified in MEMADDR is in a Thumb
244 arm_pc_is_thumb (CORE_ADDR memaddr
)
246 struct minimal_symbol
*sym
;
248 /* If bit 0 of the address is set, assume this is a Thumb address. */
249 if (IS_THUMB_ADDR (memaddr
))
252 /* Thumb functions have a "special" bit set in minimal symbols. */
253 sym
= lookup_minimal_symbol_by_pc (memaddr
);
256 return (MSYMBOL_IS_SPECIAL (sym
));
264 /* Determine if the program counter specified in MEMADDR is in a call
265 dummy being called from a Thumb function. */
268 arm_pc_is_thumb_dummy (CORE_ADDR memaddr
)
270 CORE_ADDR sp
= read_sp ();
272 /* FIXME: Until we switch for the new call dummy macros, this heuristic
273 is the best we can do. We are trying to determine if the pc is on
274 the stack, which (hopefully) will only happen in a call dummy.
275 We hope the current stack pointer is not so far alway from the dummy
276 frame location (true if we have not pushed large data structures or
277 gone too many levels deep) and that our 1024 is not enough to consider
278 code regions as part of the stack (true for most practical purposes) */
279 if (PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 1024))
280 return caller_is_thumb
;
286 arm_addr_bits_remove (CORE_ADDR val
)
288 if (arm_pc_is_thumb (val
))
289 return (val
& (arm_apcs_32
? 0xfffffffe : 0x03fffffe));
291 return (val
& (arm_apcs_32
? 0xfffffffc : 0x03fffffc));
295 arm_saved_pc_after_call (struct frame_info
*frame
)
297 return ADDR_BITS_REMOVE (read_register (LR_REGNUM
));
301 arm_frameless_function_invocation (struct frame_info
*fi
)
303 CORE_ADDR func_start
, after_prologue
;
306 func_start
= (get_pc_function_start ((fi
)->pc
) + FUNCTION_START_OFFSET
);
307 after_prologue
= SKIP_PROLOGUE (func_start
);
309 /* There are some frameless functions whose first two instructions
310 follow the standard APCS form, in which case after_prologue will
311 be func_start + 8. */
313 frameless
= (after_prologue
< func_start
+ 12);
317 /* A typical Thumb prologue looks like this:
321 Sometimes the latter instruction may be replaced by:
329 or, on tpcs, like this:
336 There is always one instruction of three classes:
341 When we have found at least one of each class we are done with the prolog.
342 Note that the "sub sp, #NN" before the push does not count.
346 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
348 CORE_ADDR current_pc
;
349 int findmask
= 0; /* findmask:
350 bit 0 - push { rlist }
351 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
352 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
355 for (current_pc
= pc
; current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40; current_pc
+= 2)
357 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
359 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
361 findmask
|= 1; /* push found */
363 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
365 if ((findmask
& 1) == 0) /* before push ? */
368 findmask
|= 4; /* add/sub sp found */
370 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
372 findmask
|= 2; /* setting of r7 found */
374 else if (insn
== 0x466f) /* mov r7, sp */
376 findmask
|= 2; /* setting of r7 found */
379 continue; /* something in the prolog that we don't care about or some
380 instruction from outside the prolog scheduled here for optimization */
386 /* The APCS (ARM Procedure Call Standard) defines the following
390 [stmfd sp!, {a1,a2,a3,a4}]
391 stmfd sp!, {...,fp,ip,lr,pc}
392 [stfe f7, [sp, #-12]!]
393 [stfe f6, [sp, #-12]!]
394 [stfe f5, [sp, #-12]!]
395 [stfe f4, [sp, #-12]!]
396 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
399 arm_skip_prologue (CORE_ADDR pc
)
403 CORE_ADDR func_addr
, func_end
;
405 struct symtab_and_line sal
;
407 /* See what the symbol table says. */
409 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
413 /* Found a function. */
414 sym
= lookup_symbol (func_name
, NULL
, VAR_NAMESPACE
, NULL
, NULL
);
415 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
417 /* Don't use this trick for assembly source files. */
418 sal
= find_pc_line (func_addr
, 0);
419 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
424 /* Check if this is Thumb code. */
425 if (arm_pc_is_thumb (pc
))
426 return thumb_skip_prologue (pc
, func_end
);
428 /* Can't find the prologue end in the symbol table, try it the hard way
429 by disassembling the instructions. */
431 inst
= read_memory_integer (skip_pc
, 4);
432 if (inst
!= 0xe1a0c00d) /* mov ip, sp */
436 inst
= read_memory_integer (skip_pc
, 4);
437 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
440 inst
= read_memory_integer (skip_pc
, 4);
443 if ((inst
& 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */
447 inst
= read_memory_integer (skip_pc
, 4);
449 /* Any insns after this point may float into the code, if it makes
450 for better instruction scheduling, so we skip them only if we
451 find them, but still consdier the function to be frame-ful. */
453 /* We may have either one sfmfd instruction here, or several stfe
454 insns, depending on the version of floating point code we
456 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
459 inst
= read_memory_integer (skip_pc
, 4);
463 while ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
466 inst
= read_memory_integer (skip_pc
, 4);
470 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
476 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
477 This function decodes a Thumb function prologue to determine:
478 1) the size of the stack frame
479 2) which registers are saved on it
480 3) the offsets of saved regs
481 4) the offset from the stack pointer to the frame pointer
482 This information is stored in the "extra" fields of the frame_info.
484 A typical Thumb function prologue would create this stack frame
485 (offsets relative to FP)
486 old SP -> 24 stack parameters
489 R7 -> 0 local variables (16 bytes)
490 SP -> -12 additional stack space (12 bytes)
491 The frame size would thus be 36 bytes, and the frame offset would be
492 12 bytes. The frame register is R7.
494 The comments for thumb_skip_prolog() describe the algorithm we use to detect
495 the end of the prolog */
499 thumb_scan_prologue (struct frame_info
*fi
)
501 CORE_ADDR prologue_start
;
502 CORE_ADDR prologue_end
;
503 CORE_ADDR current_pc
;
504 int saved_reg
[16]; /* which register has been copied to register n? */
505 int findmask
= 0; /* findmask:
506 bit 0 - push { rlist }
507 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
508 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
512 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
514 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
516 if (sal
.line
== 0) /* no line info, use current PC */
517 prologue_end
= fi
->pc
;
518 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
519 prologue_end
= sal
.end
; /* (probably means no prologue) */
522 prologue_end
= prologue_start
+ 40; /* We're in the boondocks: allow for */
523 /* 16 pushes, an add, and "mv fp,sp" */
525 prologue_end
= min (prologue_end
, fi
->pc
);
527 /* Initialize the saved register map. When register H is copied to
528 register L, we will put H in saved_reg[L]. */
529 for (i
= 0; i
< 16; i
++)
532 /* Search the prologue looking for instructions that set up the
533 frame pointer, adjust the stack pointer, and save registers.
534 Do this until all basic prolog instructions are found. */
536 fi
->extra_info
->framesize
= 0;
537 for (current_pc
= prologue_start
;
538 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
545 insn
= read_memory_unsigned_integer (current_pc
, 2);
547 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
550 findmask
|= 1; /* push found */
551 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
552 whether to save LR (R14). */
553 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
555 /* Calculate offsets of saved R0-R7 and LR. */
556 for (regno
= LR_REGNUM
; regno
>= 0; regno
--)
557 if (mask
& (1 << regno
))
559 fi
->extra_info
->framesize
+= 4;
560 fi
->saved_regs
[saved_reg
[regno
]] =
561 -(fi
->extra_info
->framesize
);
562 saved_reg
[regno
] = regno
; /* reset saved register map */
565 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
567 if ((findmask
& 1) == 0) /* before push ? */
570 findmask
|= 4; /* add/sub sp found */
572 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
573 if (insn
& 0x80) /* is it signed? (==subtracting) */
575 fi
->extra_info
->frameoffset
+= offset
;
578 fi
->extra_info
->framesize
-= offset
;
580 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
582 findmask
|= 2; /* setting of r7 found */
583 fi
->extra_info
->framereg
= THUMB_FP_REGNUM
;
584 /* get scaled offset */
585 fi
->extra_info
->frameoffset
= (insn
& 0xff) << 2;
587 else if (insn
== 0x466f) /* mov r7, sp */
589 findmask
|= 2; /* setting of r7 found */
590 fi
->extra_info
->framereg
= THUMB_FP_REGNUM
;
591 fi
->extra_info
->frameoffset
= 0;
592 saved_reg
[THUMB_FP_REGNUM
] = SP_REGNUM
;
594 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
596 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
597 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
598 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
601 continue; /* something in the prolog that we don't care about or some
602 instruction from outside the prolog scheduled here for optimization */
606 /* Check if prologue for this frame's PC has already been scanned. If
607 it has, copy the relevant information about that prologue and
608 return non-zero. Otherwise do not copy anything and return zero.
610 The information saved in the cache includes:
611 * the frame register number;
612 * the size of the stack frame;
613 * the offsets of saved regs (relative to the old SP); and
614 * the offset from the stack pointer to the frame pointer
616 The cache contains only one entry, since this is adequate for the
617 typical sequence of prologue scan requests we get. When performing
618 a backtrace, GDB will usually ask to scan the same function twice
619 in a row (once to get the frame chain, and once to fill in the
620 extra frame information). */
622 static struct frame_info prologue_cache
;
625 check_prologue_cache (struct frame_info
*fi
)
629 if (fi
->pc
== prologue_cache
.pc
)
631 fi
->extra_info
->framereg
= prologue_cache
.extra_info
->framereg
;
632 fi
->extra_info
->framesize
= prologue_cache
.extra_info
->framesize
;
633 fi
->extra_info
->frameoffset
= prologue_cache
.extra_info
->frameoffset
;
634 for (i
= 0; i
< NUM_REGS
+ NUM_PSEUDO_REGS
; i
++)
635 fi
->saved_regs
[i
] = prologue_cache
.saved_regs
[i
];
643 /* Copy the prologue information from fi to the prologue cache. */
646 save_prologue_cache (struct frame_info
*fi
)
650 prologue_cache
.pc
= fi
->pc
;
651 prologue_cache
.extra_info
->framereg
= fi
->extra_info
->framereg
;
652 prologue_cache
.extra_info
->framesize
= fi
->extra_info
->framesize
;
653 prologue_cache
.extra_info
->frameoffset
= fi
->extra_info
->frameoffset
;
655 for (i
= 0; i
< NUM_REGS
+ NUM_PSEUDO_REGS
; i
++)
656 prologue_cache
.saved_regs
[i
] = fi
->saved_regs
[i
];
660 /* This function decodes an ARM function prologue to determine:
661 1) the size of the stack frame
662 2) which registers are saved on it
663 3) the offsets of saved regs
664 4) the offset from the stack pointer to the frame pointer
665 This information is stored in the "extra" fields of the frame_info.
667 There are two basic forms for the ARM prologue. The fixed argument
668 function call will look like:
671 stmfd sp!, {fp, ip, lr, pc}
675 Which would create this stack frame (offsets relative to FP):
676 IP -> 4 (caller's stack)
677 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
678 -4 LR (return address in caller)
679 -8 IP (copy of caller's SP)
681 SP -> -28 Local variables
683 The frame size would thus be 32 bytes, and the frame offset would be
684 28 bytes. The stmfd call can also save any of the vN registers it
685 plans to use, which increases the frame size accordingly.
687 Note: The stored PC is 8 off of the STMFD instruction that stored it
688 because the ARM Store instructions always store PC + 8 when you read
691 A variable argument function call will look like:
694 stmfd sp!, {a1, a2, a3, a4}
695 stmfd sp!, {fp, ip, lr, pc}
698 Which would create this stack frame (offsets relative to FP):
699 IP -> 20 (caller's stack)
704 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
705 -4 LR (return address in caller)
706 -8 IP (copy of caller's SP)
708 SP -> -28 Local variables
710 The frame size would thus be 48 bytes, and the frame offset would be
713 There is another potential complication, which is that the optimizer
714 will try to separate the store of fp in the "stmfd" instruction from
715 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
716 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
718 Also, note, the original version of the ARM toolchain claimed that there
721 instruction at the end of the prologue. I have never seen GCC produce
722 this, and the ARM docs don't mention it. We still test for it below in
728 arm_scan_prologue (struct frame_info
*fi
)
730 int regno
, sp_offset
, fp_offset
;
731 LONGEST return_value
;
732 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
734 /* Check if this function is already in the cache of frame information. */
735 if (check_prologue_cache (fi
))
738 /* Assume there is no frame until proven otherwise. */
739 fi
->extra_info
->framereg
= SP_REGNUM
;
740 fi
->extra_info
->framesize
= 0;
741 fi
->extra_info
->frameoffset
= 0;
743 /* Check for Thumb prologue. */
744 if (arm_pc_is_thumb (fi
->pc
))
746 thumb_scan_prologue (fi
);
747 save_prologue_cache (fi
);
751 /* Find the function prologue. If we can't find the function in
752 the symbol table, peek in the stack frame to find the PC. */
753 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
755 /* One way to find the end of the prologue (which works well
756 for unoptimized code) is to do the following:
758 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
761 prologue_end = fi->pc;
762 else if (sal.end < prologue_end)
763 prologue_end = sal.end;
765 This mechanism is very accurate so long as the optimizer
766 doesn't move any instructions from the function body into the
767 prologue. If this happens, sal.end will be the last
768 instruction in the first hunk of prologue code just before
769 the first instruction that the scheduler has moved from
770 the body to the prologue.
772 In order to make sure that we scan all of the prologue
773 instructions, we use a slightly less accurate mechanism which
774 may scan more than necessary. To help compensate for this
775 lack of accuracy, the prologue scanning loop below contains
776 several clauses which'll cause the loop to terminate early if
777 an implausible prologue instruction is encountered.
783 is a suitable endpoint since it accounts for the largest
784 possible prologue plus up to five instructions inserted by
787 if (prologue_end
> prologue_start
+ 64)
789 prologue_end
= prologue_start
+ 64; /* See above. */
794 /* Get address of the stmfd in the prologue of the callee; the saved
795 PC is the address of the stmfd + 8. */
796 if (!safe_read_memory_integer (fi
->frame
, 4, &return_value
))
800 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
801 prologue_end
= prologue_start
+ 64; /* See above. */
805 /* Now search the prologue looking for instructions that set up the
806 frame pointer, adjust the stack pointer, and save registers.
808 Be careful, however, and if it doesn't look like a prologue,
809 don't try to scan it. If, for instance, a frameless function
810 begins with stmfd sp!, then we will tell ourselves there is
811 a frame, which will confuse stack traceback, as well ad"finish"
812 and other operations that rely on a knowledge of the stack
815 In the APCS, the prologue should start with "mov ip, sp" so
816 if we don't see this as the first insn, we will stop. [Note:
817 This doesn't seem to be true any longer, so it's now an optional
818 part of the prologue. - Kevin Buettner, 2001-11-20] */
820 sp_offset
= fp_offset
= 0;
822 if (read_memory_unsigned_integer (prologue_start
, 4)
823 == 0xe1a0c00d) /* mov ip, sp */
824 current_pc
= prologue_start
+ 4;
826 current_pc
= prologue_start
;
828 for (; current_pc
< prologue_end
; current_pc
+= 4)
830 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
832 if ((insn
& 0xffff0000) == 0xe92d0000)
833 /* stmfd sp!, {..., fp, ip, lr, pc}
835 stmfd sp!, {a1, a2, a3, a4} */
837 int mask
= insn
& 0xffff;
839 /* Calculate offsets of saved registers. */
840 for (regno
= PC_REGNUM
; regno
>= 0; regno
--)
841 if (mask
& (1 << regno
))
844 fi
->saved_regs
[regno
] = sp_offset
;
847 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
849 unsigned imm
= insn
& 0xff; /* immediate value */
850 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
851 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
853 fi
->extra_info
->framereg
= FP_REGNUM
;
855 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
857 unsigned imm
= insn
& 0xff; /* immediate value */
858 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
859 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
862 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
865 regno
= F0_REGNUM
+ ((insn
>> 12) & 0x07);
866 fi
->saved_regs
[regno
] = sp_offset
;
868 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
871 unsigned int fp_start_reg
, fp_bound_reg
;
873 if ((insn
& 0x800) == 0x800) /* N0 is set */
875 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
882 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
888 fp_start_reg
= F0_REGNUM
+ ((insn
>> 12) & 0x7);
889 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
890 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
893 fi
->saved_regs
[fp_start_reg
++] = sp_offset
;
896 else if ((insn
& 0xf0000000) != 0xe0000000)
897 break; /* Condition not true, exit early */
898 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
899 break; /* Don't scan past a block load */
901 /* The optimizer might shove anything into the prologue,
902 so we just skip what we don't recognize. */
906 /* The frame size is just the negative of the offset (from the original SP)
907 of the last thing thing we pushed on the stack. The frame offset is
908 [new FP] - [new SP]. */
909 fi
->extra_info
->framesize
= -sp_offset
;
910 if (fi
->extra_info
->framereg
== FP_REGNUM
)
911 fi
->extra_info
->frameoffset
= fp_offset
- sp_offset
;
913 fi
->extra_info
->frameoffset
= 0;
915 save_prologue_cache (fi
);
918 /* Find REGNUM on the stack. Otherwise, it's in an active register.
919 One thing we might want to do here is to check REGNUM against the
920 clobber mask, and somehow flag it as invalid if it isn't saved on
921 the stack somewhere. This would provide a graceful failure mode
922 when trying to get the value of caller-saves registers for an inner
926 arm_find_callers_reg (struct frame_info
*fi
, int regnum
)
928 for (; fi
; fi
= fi
->next
)
930 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
931 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
932 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
935 if (fi
->saved_regs
[regnum
] != 0)
936 return read_memory_integer (fi
->saved_regs
[regnum
],
937 REGISTER_RAW_SIZE (regnum
));
938 return read_register (regnum
);
941 /* Function: frame_chain
942 Given a GDB frame, determine the address of the calling function's frame.
943 This will be used to create a new GDB frame struct, and then
944 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
945 For ARM, we save the frame size when we initialize the frame_info.
947 The original definition of this function was a macro in tm-arm.h:
948 { In the case of the ARM, the frame's nominal address is the FP value,
949 and 12 bytes before comes the saved previous FP value as a 4-byte word. }
951 #define FRAME_CHAIN(thisframe) \
952 ((thisframe)->pc >= LOWEST_PC ? \
953 read_memory_integer ((thisframe)->frame - 12, 4) :\
959 arm_frame_chain (struct frame_info
*fi
)
961 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
962 CORE_ADDR fn_start
, callers_pc
, fp
;
964 /* is this a dummy frame? */
965 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
966 return fi
->frame
; /* dummy frame same as caller's frame */
968 /* is caller-of-this a dummy frame? */
969 callers_pc
= FRAME_SAVED_PC (fi
); /* find out who called us: */
970 fp
= arm_find_callers_reg (fi
, FP_REGNUM
);
971 if (PC_IN_CALL_DUMMY (callers_pc
, fp
, fp
))
972 return fp
; /* dummy frame's frame may bear no relation to ours */
974 if (find_pc_partial_function (fi
->pc
, 0, &fn_start
, 0))
975 if (fn_start
== entry_point_address ())
976 return 0; /* in _start fn, don't chain further */
978 CORE_ADDR caller_pc
, fn_start
;
979 int framereg
= fi
->extra_info
->framereg
;
981 if (fi
->pc
< LOWEST_PC
)
984 /* If the caller is the startup code, we're at the end of the chain. */
985 caller_pc
= FRAME_SAVED_PC (fi
);
986 if (find_pc_partial_function (caller_pc
, 0, &fn_start
, 0))
987 if (fn_start
== entry_point_address ())
990 /* If the caller is Thumb and the caller is ARM, or vice versa,
991 the frame register of the caller is different from ours.
992 So we must scan the prologue of the caller to determine its
993 frame register number. */
994 /* XXX Fixme, we should try to do this without creating a temporary
996 if (arm_pc_is_thumb (caller_pc
) != arm_pc_is_thumb (fi
->pc
))
998 struct frame_info caller_fi
;
999 struct cleanup
*old_chain
;
1001 /* Create a temporary frame suitable for scanning the caller's
1003 memset (&caller_fi
, 0, sizeof (caller_fi
));
1004 caller_fi
.extra_info
= (struct frame_extra_info
*)
1005 xcalloc (1, sizeof (struct frame_extra_info
));
1006 old_chain
= make_cleanup (xfree
, caller_fi
.extra_info
);
1007 caller_fi
.saved_regs
= (CORE_ADDR
*)
1008 xcalloc (1, SIZEOF_FRAME_SAVED_REGS
);
1009 make_cleanup (xfree
, caller_fi
.saved_regs
);
1011 /* Now, scan the prologue and obtain the frame register. */
1012 caller_fi
.pc
= caller_pc
;
1013 arm_scan_prologue (&caller_fi
);
1014 framereg
= caller_fi
.extra_info
->framereg
;
1016 /* Deallocate the storage associated with the temporary frame
1018 do_cleanups (old_chain
);
1021 /* If the caller used a frame register, return its value.
1022 Otherwise, return the caller's stack pointer. */
1023 if (framereg
== FP_REGNUM
|| framereg
== THUMB_FP_REGNUM
)
1024 return arm_find_callers_reg (fi
, framereg
);
1026 return fi
->frame
+ fi
->extra_info
->framesize
;
1029 /* This function actually figures out the frame address for a given pc
1030 and sp. This is tricky because we sometimes don't use an explicit
1031 frame pointer, and the previous stack pointer isn't necessarily
1032 recorded on the stack. The only reliable way to get this info is
1033 to examine the prologue. FROMLEAF is a little confusing, it means
1034 this is the next frame up the chain AFTER a frameless function. If
1035 this is true, then the frame value for this frame is still in the
1039 arm_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1044 if (fi
->saved_regs
== NULL
)
1045 frame_saved_regs_zalloc (fi
);
1047 fi
->extra_info
= (struct frame_extra_info
*)
1048 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1050 fi
->extra_info
->framesize
= 0;
1051 fi
->extra_info
->frameoffset
= 0;
1052 fi
->extra_info
->framereg
= 0;
1055 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1057 memset (fi
->saved_regs
, '\000', sizeof fi
->saved_regs
);
1059 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1060 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1062 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1063 by assuming it's always FP. */
1064 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
, SP_REGNUM
);
1065 fi
->extra_info
->framesize
= 0;
1066 fi
->extra_info
->frameoffset
= 0;
1072 /* Compute stack pointer for this frame. We use this value for both the
1073 sigtramp and call dummy cases. */
1077 sp
= (fi
->next
->frame
- fi
->next
->extra_info
->frameoffset
1078 + fi
->next
->extra_info
->framesize
);
1080 /* Determine whether or not we're in a sigtramp frame.
1081 Unfortunately, it isn't sufficient to test
1082 fi->signal_handler_caller because this value is sometimes set
1083 after invoking INIT_EXTRA_FRAME_INFO. So we test *both*
1084 fi->signal_handler_caller and IN_SIGTRAMP to determine if we need
1085 to use the sigcontext addresses for the saved registers.
1087 Note: If an ARM IN_SIGTRAMP method ever needs to compare against
1088 the name of the function, the code below will have to be changed
1089 to first fetch the name of the function and then pass this name
1092 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1093 && (fi
->signal_handler_caller
|| IN_SIGTRAMP (fi
->pc
, (char *)0)))
1095 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1096 fi
->saved_regs
[reg
] = SIGCONTEXT_REGISTER_ADDRESS (sp
, fi
->pc
, reg
);
1098 /* FIXME: What about thumb mode? */
1099 fi
->extra_info
->framereg
= SP_REGNUM
;
1101 read_memory_integer (fi
->saved_regs
[fi
->extra_info
->framereg
],
1102 REGISTER_RAW_SIZE (fi
->extra_info
->framereg
));
1103 fi
->extra_info
->framesize
= 0;
1104 fi
->extra_info
->frameoffset
= 0;
1107 else if (PC_IN_CALL_DUMMY (fi
->pc
, sp
, fi
->frame
))
1110 CORE_ADDR callers_sp
;
1112 /* Set rp point at the high end of the saved registers. */
1113 rp
= fi
->frame
- REGISTER_SIZE
;
1115 /* Fill in addresses of saved registers. */
1116 fi
->saved_regs
[PS_REGNUM
] = rp
;
1117 rp
-= REGISTER_RAW_SIZE (PS_REGNUM
);
1118 for (reg
= PC_REGNUM
; reg
>= 0; reg
--)
1120 fi
->saved_regs
[reg
] = rp
;
1121 rp
-= REGISTER_RAW_SIZE (reg
);
1124 callers_sp
= read_memory_integer (fi
->saved_regs
[SP_REGNUM
],
1125 REGISTER_RAW_SIZE (SP_REGNUM
));
1126 fi
->extra_info
->framereg
= FP_REGNUM
;
1127 fi
->extra_info
->framesize
= callers_sp
- sp
;
1128 fi
->extra_info
->frameoffset
= fi
->frame
- sp
;
1132 arm_scan_prologue (fi
);
1135 /* this is the innermost frame? */
1136 fi
->frame
= read_register (fi
->extra_info
->framereg
);
1137 else if (fi
->extra_info
->framereg
== FP_REGNUM
1138 || fi
->extra_info
->framereg
== THUMB_FP_REGNUM
)
1140 /* not the innermost frame */
1141 /* If we have an FP, the callee saved it. */
1142 if (fi
->next
->saved_regs
[fi
->extra_info
->framereg
] != 0)
1144 read_memory_integer (fi
->next
1145 ->saved_regs
[fi
->extra_info
->framereg
], 4);
1147 /* If we were called by a frameless fn. then our frame is
1148 still in the frame pointer register on the board... */
1149 fi
->frame
= read_fp ();
1152 /* Calculate actual addresses of saved registers using offsets
1153 determined by arm_scan_prologue. */
1154 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1155 if (fi
->saved_regs
[reg
] != 0)
1156 fi
->saved_regs
[reg
] += (fi
->frame
+ fi
->extra_info
->framesize
1157 - fi
->extra_info
->frameoffset
);
1162 /* Find the caller of this frame. We do this by seeing if LR_REGNUM
1163 is saved in the stack anywhere, otherwise we get it from the
1166 The old definition of this function was a macro:
1167 #define FRAME_SAVED_PC(FRAME) \
1168 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1171 arm_frame_saved_pc (struct frame_info
*fi
)
1173 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1174 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1175 return generic_read_register_dummy (fi
->pc
, fi
->frame
, PC_REGNUM
);
1178 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
- fi
->extra_info
->frameoffset
,
1181 return read_memory_integer (fi
->saved_regs
[PC_REGNUM
],
1182 REGISTER_RAW_SIZE (PC_REGNUM
));
1186 CORE_ADDR pc
= arm_find_callers_reg (fi
, LR_REGNUM
);
1187 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1191 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1192 Examine the Program Status Register to decide which state we're in. */
1195 arm_target_read_fp (void)
1197 if (read_register (PS_REGNUM
) & 0x20) /* Bit 5 is Thumb state bit */
1198 return read_register (THUMB_FP_REGNUM
); /* R7 if Thumb */
1200 return read_register (FP_REGNUM
); /* R11 if ARM */
1203 /* Calculate the frame offsets of the saved registers (ARM version). */
1206 arm_frame_init_saved_regs (struct frame_info
*fip
)
1209 if (fip
->saved_regs
)
1212 arm_init_extra_frame_info (0, fip
);
1216 arm_push_dummy_frame (void)
1218 CORE_ADDR old_sp
= read_register (SP_REGNUM
);
1219 CORE_ADDR sp
= old_sp
;
1220 CORE_ADDR fp
, prologue_start
;
1223 /* Push the two dummy prologue instructions in reverse order,
1224 so that they'll be in the correct low-to-high order in memory. */
1225 /* sub fp, ip, #4 */
1226 sp
= push_word (sp
, 0xe24cb004);
1227 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1228 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
1230 /* Push a pointer to the dummy prologue + 12, because when stm
1231 instruction stores the PC, it stores the address of the stm
1232 instruction itself plus 12. */
1233 fp
= sp
= push_word (sp
, prologue_start
+ 12);
1235 /* Push the processor status. */
1236 sp
= push_word (sp
, read_register (PS_REGNUM
));
1238 /* Push all 16 registers starting with r15. */
1239 for (regnum
= PC_REGNUM
; regnum
>= 0; regnum
--)
1240 sp
= push_word (sp
, read_register (regnum
));
1242 /* Update fp (for both Thumb and ARM) and sp. */
1243 write_register (FP_REGNUM
, fp
);
1244 write_register (THUMB_FP_REGNUM
, fp
);
1245 write_register (SP_REGNUM
, sp
);
1248 /* Fix up the call dummy, based on whether the processor is currently
1249 in Thumb or ARM mode, and whether the target function is Thumb or
1250 ARM. There are three different situations requiring three
1253 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1254 been copied into the dummy parameter to this function.
1255 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1256 "mov pc,r4" instruction patched to be a "bx r4" instead.
1257 * Thumb calling anything: uses the Thumb dummy defined below, which
1258 works for calling both ARM and Thumb functions.
1260 All three call dummies expect to receive the target function
1261 address in R4, with the low bit set if it's a Thumb function. */
1264 arm_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
1265 struct value
**args
, struct type
*type
, int gcc_p
)
1267 static short thumb_dummy
[4] =
1269 0xf000, 0xf801, /* bl label */
1270 0xdf18, /* swi 24 */
1271 0x4720, /* label: bx r4 */
1273 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
1275 /* Set flag indicating whether the current PC is in a Thumb function. */
1276 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
1278 /* If the target function is Thumb, set the low bit of the function
1279 address. And if the CPU is currently in ARM mode, patch the
1280 second instruction of call dummy to use a BX instruction to
1281 switch to Thumb mode. */
1282 target_is_thumb
= arm_pc_is_thumb (fun
);
1283 if (target_is_thumb
)
1286 if (!caller_is_thumb
)
1287 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
1290 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1291 instead of the ARM one that's already been copied. This will
1292 work for both Thumb and ARM target functions. */
1293 if (caller_is_thumb
)
1297 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
1299 for (i
= 0; i
< len
; i
++)
1301 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1302 p
+= sizeof (thumb_dummy
[0]);
1306 /* Put the target address in r4; the call dummy will copy this to
1308 write_register (4, fun
);
1311 /* Return the offset in the call dummy of the instruction that needs
1312 to have a breakpoint placed on it. This is the offset of the 'swi
1313 24' instruction, which is no longer actually used, but simply acts
1314 as a place-holder now.
1316 This implements the CALL_DUMMY_BREAK_OFFSET macro. */
1319 arm_call_dummy_breakpoint_offset (void)
1321 if (caller_is_thumb
)
1329 This function does not support passing parameters using the FPA
1330 variant of the APCS. It passes any floating point arguments in the
1331 general registers and/or on the stack. */
1334 arm_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
1335 int struct_return
, CORE_ADDR struct_addr
)
1338 int argnum
, argreg
, nstack_size
;
1340 /* Walk through the list of args and determine how large a temporary
1341 stack is required. Need to take care here as structs may be
1342 passed on the stack, and we have to to push them. */
1343 nstack_size
= -4 * REGISTER_SIZE
; /* Some arguments go into A1-A4. */
1344 if (struct_return
) /* The struct address goes in A1. */
1345 nstack_size
+= REGISTER_SIZE
;
1347 /* Walk through the arguments and add their size to nstack_size. */
1348 for (argnum
= 0; argnum
< nargs
; argnum
++)
1351 struct type
*arg_type
;
1353 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1354 len
= TYPE_LENGTH (arg_type
);
1356 /* ANSI C code passes float arguments as integers, K&R code
1357 passes float arguments as doubles. Correct for this here. */
1358 if (TYPE_CODE_FLT
== TYPE_CODE (arg_type
) && REGISTER_SIZE
== len
)
1359 nstack_size
+= FP_REGISTER_VIRTUAL_SIZE
;
1364 /* Allocate room on the stack, and initialize our stack frame
1367 if (nstack_size
> 0)
1373 /* Initialize the integer argument register pointer. */
1376 /* The struct_return pointer occupies the first parameter passing
1379 write_register (argreg
++, struct_addr
);
1381 /* Process arguments from left to right. Store as many as allowed
1382 in the parameter passing registers (A1-A4), and save the rest on
1383 the temporary stack. */
1384 for (argnum
= 0; argnum
< nargs
; argnum
++)
1389 enum type_code typecode
;
1390 struct type
*arg_type
, *target_type
;
1392 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1393 target_type
= TYPE_TARGET_TYPE (arg_type
);
1394 len
= TYPE_LENGTH (arg_type
);
1395 typecode
= TYPE_CODE (arg_type
);
1396 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
1398 /* ANSI C code passes float arguments as integers, K&R code
1399 passes float arguments as doubles. The .stabs record for
1400 for ANSI prototype floating point arguments records the
1401 type as FP_INTEGER, while a K&R style (no prototype)
1402 .stabs records the type as FP_FLOAT. In this latter case
1403 the compiler converts the float arguments to double before
1404 calling the function. */
1405 if (TYPE_CODE_FLT
== typecode
&& REGISTER_SIZE
== len
)
1408 dblval
= extract_floating (val
, len
);
1409 len
= TARGET_DOUBLE_BIT
/ TARGET_CHAR_BIT
;
1411 store_floating (val
, len
, dblval
);
1414 /* I don't know why this code was disable. The only logical use
1415 for a function pointer is to call that function, so setting
1416 the mode bit is perfectly fine. FN */
1417 /* If the argument is a pointer to a function, and it is a Thumb
1418 function, set the low bit of the pointer. */
1419 if (TYPE_CODE_PTR
== typecode
1420 && NULL
!= target_type
1421 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1423 CORE_ADDR regval
= extract_address (val
, len
);
1424 if (arm_pc_is_thumb (regval
))
1425 store_address (val
, len
, MAKE_THUMB_ADDR (regval
));
1428 /* Copy the argument to general registers or the stack in
1429 register-sized pieces. Large arguments are split between
1430 registers and stack. */
1433 int partial_len
= len
< REGISTER_SIZE
? len
: REGISTER_SIZE
;
1435 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1437 /* It's an argument being passed in a general register. */
1438 regval
= extract_address (val
, partial_len
);
1439 write_register (argreg
++, regval
);
1443 /* Push the arguments onto the stack. */
1444 write_memory ((CORE_ADDR
) fp
, val
, REGISTER_SIZE
);
1445 fp
+= REGISTER_SIZE
;
1453 /* Return adjusted stack pointer. */
1457 /* Pop the current frame. So long as the frame info has been initialized
1458 properly (see arm_init_extra_frame_info), this code works for dummy frames
1459 as well as regular frames. I.e, there's no need to have a special case
1460 for dummy frames. */
1462 arm_pop_frame (void)
1465 struct frame_info
*frame
= get_current_frame ();
1466 CORE_ADDR old_SP
= (frame
->frame
- frame
->extra_info
->frameoffset
1467 + frame
->extra_info
->framesize
);
1469 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1470 if (frame
->saved_regs
[regnum
] != 0)
1471 write_register (regnum
,
1472 read_memory_integer (frame
->saved_regs
[regnum
],
1473 REGISTER_RAW_SIZE (regnum
)));
1475 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
1476 write_register (SP_REGNUM
, old_SP
);
1478 flush_cached_frames ();
1482 print_fpu_flags (int flags
)
1484 if (flags
& (1 << 0))
1485 fputs ("IVO ", stdout
);
1486 if (flags
& (1 << 1))
1487 fputs ("DVZ ", stdout
);
1488 if (flags
& (1 << 2))
1489 fputs ("OFL ", stdout
);
1490 if (flags
& (1 << 3))
1491 fputs ("UFL ", stdout
);
1492 if (flags
& (1 << 4))
1493 fputs ("INX ", stdout
);
1498 arm_float_info (void)
1500 register unsigned long status
= read_register (FPS_REGNUM
);
1503 type
= (status
>> 24) & 127;
1504 printf ("%s FPU type %d\n",
1505 (status
& (1 << 31)) ? "Hardware" : "Software",
1507 fputs ("mask: ", stdout
);
1508 print_fpu_flags (status
>> 16);
1509 fputs ("flags: ", stdout
);
1510 print_fpu_flags (status
);
1514 arm_register_type (int regnum
)
1516 if (regnum
>= F0_REGNUM
&& regnum
< F0_REGNUM
+ NUM_FREGS
)
1518 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1519 return builtin_type_arm_ext_big
;
1521 return builtin_type_arm_ext_littlebyte_bigword
;
1524 return builtin_type_int32
;
1527 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1528 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1529 It is thought that this is is the floating-point register format on
1530 little-endian systems. */
1533 convert_from_extended (void *ptr
, void *dbl
)
1536 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1537 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1539 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1541 floatformat_from_doublest (TARGET_DOUBLE_FORMAT
, &d
, dbl
);
1545 convert_to_extended (void *dbl
, void *ptr
)
1548 floatformat_to_doublest (TARGET_DOUBLE_FORMAT
, ptr
, &d
);
1549 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1550 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1552 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1557 condition_true (unsigned long cond
, unsigned long status_reg
)
1559 if (cond
== INST_AL
|| cond
== INST_NV
)
1565 return ((status_reg
& FLAG_Z
) != 0);
1567 return ((status_reg
& FLAG_Z
) == 0);
1569 return ((status_reg
& FLAG_C
) != 0);
1571 return ((status_reg
& FLAG_C
) == 0);
1573 return ((status_reg
& FLAG_N
) != 0);
1575 return ((status_reg
& FLAG_N
) == 0);
1577 return ((status_reg
& FLAG_V
) != 0);
1579 return ((status_reg
& FLAG_V
) == 0);
1581 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1583 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1585 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1587 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1589 return (((status_reg
& FLAG_Z
) == 0) &&
1590 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1592 return (((status_reg
& FLAG_Z
) != 0) ||
1593 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1598 /* Support routines for single stepping. Calculate the next PC value. */
1599 #define submask(x) ((1L << ((x) + 1)) - 1)
1600 #define bit(obj,st) (((obj) >> (st)) & 1)
1601 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1602 #define sbits(obj,st,fn) \
1603 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1604 #define BranchDest(addr,instr) \
1605 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1608 static unsigned long
1609 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1610 unsigned long status_reg
)
1612 unsigned long res
, shift
;
1613 int rm
= bits (inst
, 0, 3);
1614 unsigned long shifttype
= bits (inst
, 5, 6);
1618 int rs
= bits (inst
, 8, 11);
1619 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1622 shift
= bits (inst
, 7, 11);
1625 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1626 + (bit (inst
, 4) ? 12 : 8))
1627 : read_register (rm
));
1632 res
= shift
>= 32 ? 0 : res
<< shift
;
1636 res
= shift
>= 32 ? 0 : res
>> shift
;
1642 res
= ((res
& 0x80000000L
)
1643 ? ~((~res
) >> shift
) : res
>> shift
);
1646 case 3: /* ROR/RRX */
1649 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1651 res
= (res
>> shift
) | (res
<< (32 - shift
));
1655 return res
& 0xffffffff;
1658 /* Return number of 1-bits in VAL. */
1661 bitcount (unsigned long val
)
1664 for (nbits
= 0; val
!= 0; nbits
++)
1665 val
&= val
- 1; /* delete rightmost 1-bit in val */
1670 thumb_get_next_pc (CORE_ADDR pc
)
1672 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1673 unsigned short inst1
= read_memory_integer (pc
, 2);
1674 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1675 unsigned long offset
;
1677 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1681 /* Fetch the saved PC from the stack. It's stored above
1682 all of the other registers. */
1683 offset
= bitcount (bits (inst1
, 0, 7)) * REGISTER_SIZE
;
1684 sp
= read_register (SP_REGNUM
);
1685 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1686 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1688 error ("Infinite loop detected");
1690 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1692 unsigned long status
= read_register (PS_REGNUM
);
1693 unsigned long cond
= bits (inst1
, 8, 11);
1694 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1695 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1697 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1699 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1701 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1703 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1704 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1705 nextpc
= pc_val
+ offset
;
1712 arm_get_next_pc (CORE_ADDR pc
)
1714 unsigned long pc_val
;
1715 unsigned long this_instr
;
1716 unsigned long status
;
1719 if (arm_pc_is_thumb (pc
))
1720 return thumb_get_next_pc (pc
);
1722 pc_val
= (unsigned long) pc
;
1723 this_instr
= read_memory_integer (pc
, 4);
1724 status
= read_register (PS_REGNUM
);
1725 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1727 if (condition_true (bits (this_instr
, 28, 31), status
))
1729 switch (bits (this_instr
, 24, 27))
1732 case 0x1: /* data processing */
1736 unsigned long operand1
, operand2
, result
= 0;
1740 if (bits (this_instr
, 12, 15) != 15)
1743 if (bits (this_instr
, 22, 25) == 0
1744 && bits (this_instr
, 4, 7) == 9) /* multiply */
1745 error ("Illegal update to pc in instruction");
1747 /* Multiply into PC */
1748 c
= (status
& FLAG_C
) ? 1 : 0;
1749 rn
= bits (this_instr
, 16, 19);
1750 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1752 if (bit (this_instr
, 25))
1754 unsigned long immval
= bits (this_instr
, 0, 7);
1755 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1756 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1759 else /* operand 2 is a shifted register */
1760 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1762 switch (bits (this_instr
, 21, 24))
1765 result
= operand1
& operand2
;
1769 result
= operand1
^ operand2
;
1773 result
= operand1
- operand2
;
1777 result
= operand2
- operand1
;
1781 result
= operand1
+ operand2
;
1785 result
= operand1
+ operand2
+ c
;
1789 result
= operand1
- operand2
+ c
;
1793 result
= operand2
- operand1
+ c
;
1799 case 0xb: /* tst, teq, cmp, cmn */
1800 result
= (unsigned long) nextpc
;
1804 result
= operand1
| operand2
;
1808 /* Always step into a function. */
1813 result
= operand1
& ~operand2
;
1820 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1823 error ("Infinite loop detected");
1828 case 0x5: /* data transfer */
1831 if (bit (this_instr
, 20))
1834 if (bits (this_instr
, 12, 15) == 15)
1840 if (bit (this_instr
, 22))
1841 error ("Illegal update to pc in instruction");
1843 /* byte write to PC */
1844 rn
= bits (this_instr
, 16, 19);
1845 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1846 if (bit (this_instr
, 24))
1849 int c
= (status
& FLAG_C
) ? 1 : 0;
1850 unsigned long offset
=
1851 (bit (this_instr
, 25)
1852 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1853 : bits (this_instr
, 0, 11));
1855 if (bit (this_instr
, 23))
1860 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1863 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1866 error ("Infinite loop detected");
1872 case 0x9: /* block transfer */
1873 if (bit (this_instr
, 20))
1876 if (bit (this_instr
, 15))
1881 if (bit (this_instr
, 23))
1884 unsigned long reglist
= bits (this_instr
, 0, 14);
1885 offset
= bitcount (reglist
) * 4;
1886 if (bit (this_instr
, 24)) /* pre */
1889 else if (bit (this_instr
, 24))
1893 unsigned long rn_val
=
1894 read_register (bits (this_instr
, 16, 19));
1896 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1900 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1902 error ("Infinite loop detected");
1907 case 0xb: /* branch & link */
1908 case 0xa: /* branch */
1910 nextpc
= BranchDest (pc
, this_instr
);
1912 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1914 error ("Infinite loop detected");
1920 case 0xe: /* coproc ops */
1925 fprintf (stderr
, "Bad bit-field extraction\n");
1933 /* single_step() is called just before we want to resume the inferior,
1934 if we want to single-step it but there is no hardware or kernel
1935 single-step support. We find the target of the coming instruction
1938 single_step is also called just after the inferior stops. If we had
1939 set up a simulated single-step, we undo our damage. */
1942 arm_software_single_step (ignore
, insert_bpt
)
1943 int ignore
; /* Signal, not needed */
1946 static int next_pc
; /* State between setting and unsetting. */
1947 static char break_mem
[BREAKPOINT_MAX
]; /* Temporary storage for mem@bpt */
1951 next_pc
= arm_get_next_pc (read_register (PC_REGNUM
));
1952 target_insert_breakpoint (next_pc
, break_mem
);
1955 target_remove_breakpoint (next_pc
, break_mem
);
1958 #include "bfd-in2.h"
1959 #include "libcoff.h"
1962 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
1964 if (arm_pc_is_thumb (memaddr
))
1966 static asymbol
*asym
;
1967 static combined_entry_type ce
;
1968 static struct coff_symbol_struct csym
;
1969 static struct _bfd fake_bfd
;
1970 static bfd_target fake_target
;
1972 if (csym
.native
== NULL
)
1974 /* Create a fake symbol vector containing a Thumb symbol. This is
1975 solely so that the code in print_insn_little_arm() and
1976 print_insn_big_arm() in opcodes/arm-dis.c will detect the presence
1977 of a Thumb symbol and switch to decoding Thumb instructions. */
1979 fake_target
.flavour
= bfd_target_coff_flavour
;
1980 fake_bfd
.xvec
= &fake_target
;
1981 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
1983 csym
.symbol
.the_bfd
= &fake_bfd
;
1984 csym
.symbol
.name
= "fake";
1985 asym
= (asymbol
*) & csym
;
1988 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
1989 info
->symbols
= &asym
;
1992 info
->symbols
= NULL
;
1994 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1995 return print_insn_big_arm (memaddr
, info
);
1997 return print_insn_little_arm (memaddr
, info
);
2000 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the
2001 program counter value to determine whether a 16-bit or 32-bit
2002 breakpoint should be used. It returns a pointer to a string of
2003 bytes that encode a breakpoint instruction, stores the length of
2004 the string to *lenptr, and adjusts the program counter (if
2005 necessary) to point to the actual memory location where the
2006 breakpoint should be inserted. */
2009 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
2011 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
2013 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2015 static char thumb_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2016 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2017 *lenptr
= sizeof (thumb_breakpoint
);
2018 return thumb_breakpoint
;
2022 static char thumb_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2023 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2024 *lenptr
= sizeof (thumb_breakpoint
);
2025 return thumb_breakpoint
;
2030 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2032 static char arm_breakpoint
[] = ARM_BE_BREAKPOINT
;
2033 *lenptr
= sizeof (arm_breakpoint
);
2034 return arm_breakpoint
;
2038 static char arm_breakpoint
[] = ARM_LE_BREAKPOINT
;
2039 *lenptr
= sizeof (arm_breakpoint
);
2040 return arm_breakpoint
;
2045 /* Extract from an array REGBUF containing the (raw) register state a
2046 function return value of type TYPE, and copy that, in virtual
2047 format, into VALBUF. */
2050 arm_extract_return_value (struct type
*type
,
2051 char regbuf
[REGISTER_BYTES
],
2054 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2055 convert_from_extended (®buf
[REGISTER_BYTE (F0_REGNUM
)], valbuf
);
2057 memcpy (valbuf
, ®buf
[REGISTER_BYTE (A1_REGNUM
)], TYPE_LENGTH (type
));
2060 /* Return non-zero if the PC is inside a thumb call thunk. */
2063 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2065 CORE_ADDR start_addr
;
2067 /* Find the starting address of the function containing the PC. If
2068 the caller didn't give us a name, look it up at the same time. */
2069 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
2072 return strncmp (name
, "_call_via_r", 11) == 0;
2075 /* If PC is in a Thumb call or return stub, return the address of the
2076 target PC, which is in a register. The thunk functions are called
2077 _called_via_xx, where x is the register name. The possible names
2078 are r0-r9, sl, fp, ip, sp, and lr. */
2081 arm_skip_stub (CORE_ADDR pc
)
2084 CORE_ADDR start_addr
;
2086 /* Find the starting address and name of the function containing the PC. */
2087 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2090 /* Call thunks always start with "_call_via_". */
2091 if (strncmp (name
, "_call_via_", 10) == 0)
2093 /* Use the name suffix to determine which register contains the
2095 static char *table
[15] =
2096 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2097 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2101 for (regno
= 0; regno
<= 14; regno
++)
2102 if (strcmp (&name
[10], table
[regno
]) == 0)
2103 return read_register (regno
);
2106 return 0; /* not a stub */
2109 /* If the user changes the register disassembly flavor used for info register
2110 and other commands, we have to also switch the flavor used in opcodes
2111 for disassembly output.
2112 This function is run in the set disassembly_flavor command, and does that. */
2115 set_disassembly_flavor_sfunc (char *args
, int from_tty
,
2116 struct cmd_list_element
*c
)
2118 set_disassembly_flavor ();
2121 /* Return the ARM register name corresponding to register I. */
2123 arm_register_name(int i
)
2125 return arm_register_names
[i
];
2129 set_disassembly_flavor (void)
2131 const char *setname
, *setdesc
, **regnames
;
2134 /* Find the flavor that the user wants in the opcodes table. */
2136 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2137 while ((disassembly_flavor
!= setname
)
2138 && (current
< num_flavor_options
))
2139 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2140 current_option
= current
;
2142 /* Fill our copy. */
2143 for (j
= 0; j
< numregs
; j
++)
2144 arm_register_names
[j
] = (char *) regnames
[j
];
2147 if (isupper (*regnames
[PC_REGNUM
]))
2149 arm_register_names
[FPS_REGNUM
] = "FPS";
2150 arm_register_names
[PS_REGNUM
] = "CPSR";
2154 arm_register_names
[FPS_REGNUM
] = "fps";
2155 arm_register_names
[PS_REGNUM
] = "cpsr";
2158 /* Synchronize the disassembler. */
2159 set_arm_regname_option (current
);
2162 /* arm_othernames implements the "othernames" command. This is kind
2163 of hacky, and I prefer the set-show disassembly-flavor which is
2164 also used for the x86 gdb. I will keep this around, however, in
2165 case anyone is actually using it. */
2168 arm_othernames (char *names
, int n
)
2170 /* Circle through the various flavors. */
2171 current_option
= (current_option
+ 1) % num_flavor_options
;
2173 disassembly_flavor
= valid_flavors
[current_option
];
2174 set_disassembly_flavor ();
2177 /* Fetch, and possibly build, an appropriate link_map_offsets structure
2178 for ARM linux targets using the struct offsets defined in <link.h>.
2179 Note, however, that link.h is not actually referred to in this file.
2180 Instead, the relevant structs offsets were obtained from examining
2181 link.h. (We can't refer to link.h from this file because the host
2182 system won't necessarily have it, or if it does, the structs which
2183 it defines will refer to the host system, not the target.) */
2185 struct link_map_offsets
*
2186 arm_linux_svr4_fetch_link_map_offsets (void)
2188 static struct link_map_offsets lmo
;
2189 static struct link_map_offsets
*lmp
= 0;
2195 lmo
.r_debug_size
= 8; /* Actual size is 20, but this is all we
2198 lmo
.r_map_offset
= 4;
2201 lmo
.link_map_size
= 20; /* Actual size is 552, but this is all we
2204 lmo
.l_addr_offset
= 0;
2205 lmo
.l_addr_size
= 4;
2207 lmo
.l_name_offset
= 4;
2208 lmo
.l_name_size
= 4;
2210 lmo
.l_next_offset
= 12;
2211 lmo
.l_next_size
= 4;
2213 lmo
.l_prev_offset
= 16;
2214 lmo
.l_prev_size
= 4;
2221 _initialize_arm_tdep (void)
2223 struct ui_file
*stb
;
2225 struct cmd_list_element
*new_cmd
;
2226 const char *setname
;
2227 const char *setdesc
;
2228 const char **regnames
;
2230 static char *helptext
;
2232 tm_print_insn
= gdb_print_insn_arm
;
2234 /* Get the number of possible sets of register names defined in opcodes. */
2235 num_flavor_options
= get_arm_regname_num_options ();
2237 /* Sync the opcode insn printer with our register viewer: */
2238 parse_arm_disassembler_option ("reg-names-std");
2240 /* Begin creating the help text. */
2241 stb
= mem_fileopen ();
2242 fprintf_unfiltered (stb
, "Set the disassembly flavor.\n\
2243 The valid values are:\n");
2245 /* Initialize the array that will be passed to add_set_enum_cmd(). */
2246 valid_flavors
= xmalloc ((num_flavor_options
+ 1) * sizeof (char *));
2247 for (i
= 0; i
< num_flavor_options
; i
++)
2249 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
2250 valid_flavors
[i
] = setname
;
2251 fprintf_unfiltered (stb
, "%s - %s\n", setname
,
2253 /* Copy the default names (if found) and synchronize disassembler. */
2254 if (!strcmp (setname
, "std"))
2256 disassembly_flavor
= setname
;
2258 for (j
= 0; j
< numregs
; j
++)
2259 arm_register_names
[j
] = (char *) regnames
[j
];
2260 set_arm_regname_option (i
);
2263 /* Mark the end of valid options. */
2264 valid_flavors
[num_flavor_options
] = NULL
;
2266 /* Finish the creation of the help text. */
2267 fprintf_unfiltered (stb
, "The default is \"std\".");
2268 helptext
= ui_file_xstrdup (stb
, &length
);
2269 ui_file_delete (stb
);
2271 /* Add the disassembly-flavor command */
2272 new_cmd
= add_set_enum_cmd ("disassembly-flavor", no_class
,
2274 &disassembly_flavor
,
2277 new_cmd
->function
.sfunc
= set_disassembly_flavor_sfunc
;
2278 add_show_from_set (new_cmd
, &showlist
);
2280 /* ??? Maybe this should be a boolean. */
2281 add_show_from_set (add_set_cmd ("apcs32", no_class
,
2282 var_zinteger
, (char *) &arm_apcs_32
,
2283 "Set usage of ARM 32-bit mode.\n", &setlist
),
2286 /* Add the deprecated "othernames" command */
2288 add_com ("othernames", class_obscure
, arm_othernames
,
2289 "Switch to the next set of register names.");
2291 /* Fill in the prologue_cache fields. */
2292 prologue_cache
.extra_info
= (struct frame_extra_info
*)
2293 xcalloc (1, sizeof (struct frame_extra_info
));
2294 prologue_cache
.saved_regs
= (CORE_ADDR
*)
2295 xcalloc (1, SIZEOF_FRAME_SAVED_REGS
);
2298 /* Test whether the coff symbol specific value corresponds to a Thumb
2302 coff_sym_is_thumb (int val
)
2304 return (val
== C_THUMBEXT
||
2305 val
== C_THUMBSTAT
||
2306 val
== C_THUMBEXTFUNC
||
2307 val
== C_THUMBSTATFUNC
||
2308 val
== C_THUMBLABEL
);