1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include <ctype.h> /* XXX for isupper () */
28 #include "gdb_string.h"
29 #include "dis-asm.h" /* For register styles. */
33 #include "arch-utils.h"
35 #include "frame-unwind.h"
36 #include "frame-base.h"
37 #include "trad-frame.h"
39 #include "dwarf2-frame.h"
41 #include "prologue-value.h"
42 #include "target-descriptions.h"
43 #include "user-regs.h"
46 #include "gdb/sim-arm.h"
49 #include "coff/internal.h"
52 #include "gdb_assert.h"
56 /* Macros for setting and testing a bit in a minimal symbol that marks
57 it as Thumb function. The MSB of the minimal symbol's "info" field
58 is used for this purpose.
60 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
61 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
63 #define MSYMBOL_SET_SPECIAL(msym) \
64 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
67 #define MSYMBOL_IS_SPECIAL(msym) \
68 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
70 /* The list of available "set arm ..." and "show arm ..." commands. */
71 static struct cmd_list_element
*setarmcmdlist
= NULL
;
72 static struct cmd_list_element
*showarmcmdlist
= NULL
;
74 /* The type of floating-point to use. Keep this in sync with enum
75 arm_float_model, and the help string in _initialize_arm_tdep. */
76 static const char *fp_model_strings
[] =
86 /* A variable that can be configured by the user. */
87 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
88 static const char *current_fp_model
= "auto";
90 /* The ABI to use. Keep this in sync with arm_abi_kind. */
91 static const char *arm_abi_strings
[] =
99 /* A variable that can be configured by the user. */
100 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
101 static const char *arm_abi_string
= "auto";
103 /* Number of different reg name sets (options). */
104 static int num_disassembly_options
;
106 /* The standard register names, and all the valid aliases for them. */
111 } arm_register_aliases
[] = {
112 /* Basic register numbers. */
129 /* Synonyms (argument and variable registers). */
142 /* Other platform-specific names for r9. */
150 /* Names used by GCC (not listed in the ARM EABI). */
153 /* A special name from the older ATPCS. */
157 static const char *const arm_register_names
[] =
158 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
159 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
160 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
161 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
162 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
163 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
164 "fps", "cpsr" }; /* 24 25 */
166 /* Valid register name styles. */
167 static const char **valid_disassembly_styles
;
169 /* Disassembly style to use. Default to "std" register names. */
170 static const char *disassembly_style
;
172 /* This is used to keep the bfd arch_info in sync with the disassembly
174 static void set_disassembly_style_sfunc(char *, int,
175 struct cmd_list_element
*);
176 static void set_disassembly_style (void);
178 static void convert_from_extended (const struct floatformat
*, const void *,
180 static void convert_to_extended (const struct floatformat
*, void *,
183 struct arm_prologue_cache
185 /* The stack pointer at the time this frame was created; i.e. the
186 caller's stack pointer when this function was called. It is used
187 to identify this frame. */
190 /* The frame base for this frame is just prev_sp + frame offset -
191 frame size. FRAMESIZE is the size of this stack frame, and
192 FRAMEOFFSET if the initial offset from the stack pointer (this
193 frame's stack pointer, not PREV_SP) to the frame base. */
198 /* The register used to hold the frame pointer for this frame. */
201 /* Saved register offsets. */
202 struct trad_frame_saved_reg
*saved_regs
;
205 /* Addresses for calling Thumb functions have the bit 0 set.
206 Here are some macros to test, set, or clear bit 0 of addresses. */
207 #define IS_THUMB_ADDR(addr) ((addr) & 1)
208 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
209 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
211 /* Set to true if the 32-bit mode is in use. */
215 /* Determine if the program counter specified in MEMADDR is in a Thumb
219 arm_pc_is_thumb (CORE_ADDR memaddr
)
221 struct minimal_symbol
*sym
;
223 /* If bit 0 of the address is set, assume this is a Thumb address. */
224 if (IS_THUMB_ADDR (memaddr
))
227 /* Thumb functions have a "special" bit set in minimal symbols. */
228 sym
= lookup_minimal_symbol_by_pc (memaddr
);
231 return (MSYMBOL_IS_SPECIAL (sym
));
239 /* Remove useless bits from addresses in a running program. */
241 arm_addr_bits_remove (CORE_ADDR val
)
244 return (val
& (arm_pc_is_thumb (val
) ? 0xfffffffe : 0xfffffffc));
246 return (val
& 0x03fffffc);
249 /* When reading symbols, we need to zap the low bit of the address,
250 which may be set to 1 for Thumb functions. */
252 arm_smash_text_address (CORE_ADDR val
)
257 /* Analyze a Thumb prologue, looking for a recognizable stack frame
258 and frame pointer. Scan until we encounter a store that could
259 clobber the stack frame unexpectedly, or an unknown instruction. */
262 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
263 CORE_ADDR start
, CORE_ADDR limit
,
264 struct arm_prologue_cache
*cache
)
268 struct pv_area
*stack
;
269 struct cleanup
*back_to
;
272 for (i
= 0; i
< 16; i
++)
273 regs
[i
] = pv_register (i
, 0);
274 stack
= make_pv_area (ARM_SP_REGNUM
);
275 back_to
= make_cleanup_free_pv_area (stack
);
277 /* The call instruction saved PC in LR, and the current PC is not
278 interesting. Due to this file's conventions, we want the value
279 of LR at this function's entry, not at the call site, so we do
280 not record the save of the PC - when the ARM prologue analyzer
281 has also been converted to the pv mechanism, we could record the
282 save here and remove the hack in prev_register. */
283 regs
[ARM_PC_REGNUM
] = pv_unknown ();
285 while (start
< limit
)
289 insn
= read_memory_unsigned_integer (start
, 2);
291 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
297 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
298 whether to save LR (R14). */
299 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
301 /* Calculate offsets of saved R0-R7 and LR. */
302 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
303 if (mask
& (1 << regno
))
305 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
311 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
313 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
319 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
322 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
323 if (insn
& 0x80) /* Check for SUB. */
324 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
327 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
330 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
331 regs
[THUMB_FP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
333 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
335 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
336 int src_reg
= (insn
& 0x78) >> 3;
337 regs
[dst_reg
] = regs
[src_reg
];
339 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
341 /* Handle stores to the stack. Normally pushes are used,
342 but with GCC -mtpcs-frame, there may be other stores
343 in the prologue to create the frame. */
344 int regno
= (insn
>> 8) & 0x7;
347 offset
= (insn
& 0xff) << 2;
348 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
350 if (pv_area_store_would_trash (stack
, addr
))
353 pv_area_store (stack
, addr
, 4, regs
[regno
]);
357 /* We don't know what this instruction is. We're finished
358 scanning. NOTE: Recognizing more safe-to-ignore
359 instructions here will improve support for optimized
369 do_cleanups (back_to
);
373 /* frameoffset is unused for this unwinder. */
374 cache
->frameoffset
= 0;
376 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
378 /* Frame pointer is fp. Frame size is constant. */
379 cache
->framereg
= ARM_FP_REGNUM
;
380 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
382 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
384 /* Frame pointer is r7. Frame size is constant. */
385 cache
->framereg
= THUMB_FP_REGNUM
;
386 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
388 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
390 /* Try the stack pointer... this is a bit desperate. */
391 cache
->framereg
= ARM_SP_REGNUM
;
392 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
396 /* We're just out of luck. We don't know where the frame is. */
397 cache
->framereg
= -1;
398 cache
->framesize
= 0;
401 for (i
= 0; i
< 16; i
++)
402 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
403 cache
->saved_regs
[i
].addr
= offset
;
405 do_cleanups (back_to
);
409 /* Advance the PC across any function entry prologue instructions to
410 reach some "real" code.
412 The APCS (ARM Procedure Call Standard) defines the following
416 [stmfd sp!, {a1,a2,a3,a4}]
417 stmfd sp!, {...,fp,ip,lr,pc}
418 [stfe f7, [sp, #-12]!]
419 [stfe f6, [sp, #-12]!]
420 [stfe f5, [sp, #-12]!]
421 [stfe f4, [sp, #-12]!]
422 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
425 arm_skip_prologue (CORE_ADDR pc
)
429 CORE_ADDR func_addr
, func_end
= 0;
431 struct symtab_and_line sal
;
433 /* If we're in a dummy frame, don't even try to skip the prologue. */
434 if (deprecated_pc_in_call_dummy (pc
))
437 /* See what the symbol table says. */
439 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
443 /* Found a function. */
444 sym
= lookup_symbol (func_name
, NULL
, VAR_DOMAIN
, NULL
, NULL
);
445 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
447 /* Don't use this trick for assembly source files. */
448 sal
= find_pc_line (func_addr
, 0);
449 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
454 /* Can't find the prologue end in the symbol table, try it the hard way
455 by disassembling the instructions. */
457 /* Like arm_scan_prologue, stop no later than pc + 64. */
458 if (func_end
== 0 || func_end
> pc
+ 64)
461 /* Check if this is Thumb code. */
462 if (arm_pc_is_thumb (pc
))
463 return thumb_analyze_prologue (current_gdbarch
, pc
, func_end
, NULL
);
465 for (skip_pc
= pc
; skip_pc
< func_end
; skip_pc
+= 4)
467 inst
= read_memory_unsigned_integer (skip_pc
, 4);
469 /* "mov ip, sp" is no longer a required part of the prologue. */
470 if (inst
== 0xe1a0c00d) /* mov ip, sp */
473 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
476 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
479 /* Some prologues begin with "str lr, [sp, #-4]!". */
480 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
483 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
486 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
489 /* Any insns after this point may float into the code, if it makes
490 for better instruction scheduling, so we skip them only if we
491 find them, but still consider the function to be frame-ful. */
493 /* We may have either one sfmfd instruction here, or several stfe
494 insns, depending on the version of floating point code we
496 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
499 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
502 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
505 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
508 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
509 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
510 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
513 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
514 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
515 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
518 /* Un-recognized instruction; stop scanning. */
522 return skip_pc
; /* End of prologue */
526 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
527 This function decodes a Thumb function prologue to determine:
528 1) the size of the stack frame
529 2) which registers are saved on it
530 3) the offsets of saved regs
531 4) the offset from the stack pointer to the frame pointer
533 A typical Thumb function prologue would create this stack frame
534 (offsets relative to FP)
535 old SP -> 24 stack parameters
538 R7 -> 0 local variables (16 bytes)
539 SP -> -12 additional stack space (12 bytes)
540 The frame size would thus be 36 bytes, and the frame offset would be
541 12 bytes. The frame register is R7.
543 The comments for thumb_skip_prolog() describe the algorithm we use
544 to detect the end of the prolog. */
548 thumb_scan_prologue (CORE_ADDR prev_pc
, struct arm_prologue_cache
*cache
)
550 CORE_ADDR prologue_start
;
551 CORE_ADDR prologue_end
;
552 CORE_ADDR current_pc
;
553 /* Which register has been copied to register n? */
556 bit 0 - push { rlist }
557 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
558 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
563 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
565 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
567 if (sal
.line
== 0) /* no line info, use current PC */
568 prologue_end
= prev_pc
;
569 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
570 prologue_end
= sal
.end
; /* (probably means no prologue) */
573 /* We're in the boondocks: we have no idea where the start of the
577 prologue_end
= min (prologue_end
, prev_pc
);
579 thumb_analyze_prologue (current_gdbarch
, prologue_start
, prologue_end
,
583 /* This function decodes an ARM function prologue to determine:
584 1) the size of the stack frame
585 2) which registers are saved on it
586 3) the offsets of saved regs
587 4) the offset from the stack pointer to the frame pointer
588 This information is stored in the "extra" fields of the frame_info.
590 There are two basic forms for the ARM prologue. The fixed argument
591 function call will look like:
594 stmfd sp!, {fp, ip, lr, pc}
598 Which would create this stack frame (offsets relative to FP):
599 IP -> 4 (caller's stack)
600 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
601 -4 LR (return address in caller)
602 -8 IP (copy of caller's SP)
604 SP -> -28 Local variables
606 The frame size would thus be 32 bytes, and the frame offset would be
607 28 bytes. The stmfd call can also save any of the vN registers it
608 plans to use, which increases the frame size accordingly.
610 Note: The stored PC is 8 off of the STMFD instruction that stored it
611 because the ARM Store instructions always store PC + 8 when you read
614 A variable argument function call will look like:
617 stmfd sp!, {a1, a2, a3, a4}
618 stmfd sp!, {fp, ip, lr, pc}
621 Which would create this stack frame (offsets relative to FP):
622 IP -> 20 (caller's stack)
627 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
628 -4 LR (return address in caller)
629 -8 IP (copy of caller's SP)
631 SP -> -28 Local variables
633 The frame size would thus be 48 bytes, and the frame offset would be
636 There is another potential complication, which is that the optimizer
637 will try to separate the store of fp in the "stmfd" instruction from
638 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
639 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
641 Also, note, the original version of the ARM toolchain claimed that there
644 instruction at the end of the prologue. I have never seen GCC produce
645 this, and the ARM docs don't mention it. We still test for it below in
651 arm_scan_prologue (struct frame_info
*next_frame
, struct arm_prologue_cache
*cache
)
653 int regno
, sp_offset
, fp_offset
, ip_offset
;
654 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
655 CORE_ADDR prev_pc
= frame_pc_unwind (next_frame
);
657 /* Assume there is no frame until proven otherwise. */
658 cache
->framereg
= ARM_SP_REGNUM
;
659 cache
->framesize
= 0;
660 cache
->frameoffset
= 0;
662 /* Check for Thumb prologue. */
663 if (arm_pc_is_thumb (prev_pc
))
665 thumb_scan_prologue (prev_pc
, cache
);
669 /* Find the function prologue. If we can't find the function in
670 the symbol table, peek in the stack frame to find the PC. */
671 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
673 /* One way to find the end of the prologue (which works well
674 for unoptimized code) is to do the following:
676 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
679 prologue_end = prev_pc;
680 else if (sal.end < prologue_end)
681 prologue_end = sal.end;
683 This mechanism is very accurate so long as the optimizer
684 doesn't move any instructions from the function body into the
685 prologue. If this happens, sal.end will be the last
686 instruction in the first hunk of prologue code just before
687 the first instruction that the scheduler has moved from
688 the body to the prologue.
690 In order to make sure that we scan all of the prologue
691 instructions, we use a slightly less accurate mechanism which
692 may scan more than necessary. To help compensate for this
693 lack of accuracy, the prologue scanning loop below contains
694 several clauses which'll cause the loop to terminate early if
695 an implausible prologue instruction is encountered.
701 is a suitable endpoint since it accounts for the largest
702 possible prologue plus up to five instructions inserted by
705 if (prologue_end
> prologue_start
+ 64)
707 prologue_end
= prologue_start
+ 64; /* See above. */
712 /* We have no symbol information. Our only option is to assume this
713 function has a standard stack frame and the normal frame register.
714 Then, we can find the value of our frame pointer on entrance to
715 the callee (or at the present moment if this is the innermost frame).
716 The value stored there should be the address of the stmfd + 8. */
718 LONGEST return_value
;
720 frame_loc
= frame_unwind_register_unsigned (next_frame
, ARM_FP_REGNUM
);
721 if (!safe_read_memory_integer (frame_loc
, 4, &return_value
))
725 prologue_start
= gdbarch_addr_bits_remove
726 (current_gdbarch
, return_value
) - 8;
727 prologue_end
= prologue_start
+ 64; /* See above. */
731 if (prev_pc
< prologue_end
)
732 prologue_end
= prev_pc
;
734 /* Now search the prologue looking for instructions that set up the
735 frame pointer, adjust the stack pointer, and save registers.
737 Be careful, however, and if it doesn't look like a prologue,
738 don't try to scan it. If, for instance, a frameless function
739 begins with stmfd sp!, then we will tell ourselves there is
740 a frame, which will confuse stack traceback, as well as "finish"
741 and other operations that rely on a knowledge of the stack
744 In the APCS, the prologue should start with "mov ip, sp" so
745 if we don't see this as the first insn, we will stop.
747 [Note: This doesn't seem to be true any longer, so it's now an
748 optional part of the prologue. - Kevin Buettner, 2001-11-20]
750 [Note further: The "mov ip,sp" only seems to be missing in
751 frameless functions at optimization level "-O2" or above,
752 in which case it is often (but not always) replaced by
753 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
755 sp_offset
= fp_offset
= ip_offset
= 0;
757 for (current_pc
= prologue_start
;
758 current_pc
< prologue_end
;
761 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
763 if (insn
== 0xe1a0c00d) /* mov ip, sp */
768 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
770 unsigned imm
= insn
& 0xff; /* immediate value */
771 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
772 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
776 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
778 unsigned imm
= insn
& 0xff; /* immediate value */
779 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
780 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
784 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
787 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= sp_offset
;
790 else if ((insn
& 0xffff0000) == 0xe92d0000)
791 /* stmfd sp!, {..., fp, ip, lr, pc}
793 stmfd sp!, {a1, a2, a3, a4} */
795 int mask
= insn
& 0xffff;
797 /* Calculate offsets of saved registers. */
798 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
799 if (mask
& (1 << regno
))
802 cache
->saved_regs
[regno
].addr
= sp_offset
;
805 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
806 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
807 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
809 /* No need to add this to saved_regs -- it's just an arg reg. */
812 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
813 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
814 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
816 /* No need to add this to saved_regs -- it's just an arg reg. */
819 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
821 unsigned imm
= insn
& 0xff; /* immediate value */
822 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
823 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
824 fp_offset
= -imm
+ ip_offset
;
825 cache
->framereg
= ARM_FP_REGNUM
;
827 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
829 unsigned imm
= insn
& 0xff; /* immediate value */
830 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
831 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
834 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
835 && gdbarch_tdep (current_gdbarch
)->have_fpa_registers
)
838 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
839 cache
->saved_regs
[regno
].addr
= sp_offset
;
841 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
842 && gdbarch_tdep (current_gdbarch
)->have_fpa_registers
)
845 unsigned int fp_start_reg
, fp_bound_reg
;
847 if ((insn
& 0x800) == 0x800) /* N0 is set */
849 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
856 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
862 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
863 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
864 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
867 cache
->saved_regs
[fp_start_reg
++].addr
= sp_offset
;
870 else if ((insn
& 0xf0000000) != 0xe0000000)
871 break; /* Condition not true, exit early */
872 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
873 break; /* Don't scan past a block load */
875 /* The optimizer might shove anything into the prologue,
876 so we just skip what we don't recognize. */
880 /* The frame size is just the negative of the offset (from the
881 original SP) of the last thing thing we pushed on the stack.
882 The frame offset is [new FP] - [new SP]. */
883 cache
->framesize
= -sp_offset
;
884 if (cache
->framereg
== ARM_FP_REGNUM
)
885 cache
->frameoffset
= fp_offset
- sp_offset
;
887 cache
->frameoffset
= 0;
890 static struct arm_prologue_cache
*
891 arm_make_prologue_cache (struct frame_info
*next_frame
)
894 struct arm_prologue_cache
*cache
;
895 CORE_ADDR unwound_fp
;
897 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
898 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
900 arm_scan_prologue (next_frame
, cache
);
902 unwound_fp
= frame_unwind_register_unsigned (next_frame
, cache
->framereg
);
906 cache
->prev_sp
= unwound_fp
+ cache
->framesize
- cache
->frameoffset
;
908 /* Calculate actual addresses of saved registers using offsets
909 determined by arm_scan_prologue. */
910 for (reg
= 0; reg
< gdbarch_num_regs (current_gdbarch
); reg
++)
911 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
912 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
917 /* Our frame ID for a normal frame is the current function's starting PC
918 and the caller's SP when we were called. */
921 arm_prologue_this_id (struct frame_info
*next_frame
,
923 struct frame_id
*this_id
)
925 struct arm_prologue_cache
*cache
;
929 if (*this_cache
== NULL
)
930 *this_cache
= arm_make_prologue_cache (next_frame
);
933 func
= frame_func_unwind (next_frame
, NORMAL_FRAME
);
935 /* This is meant to halt the backtrace at "_start". Make sure we
936 don't halt it at a generic dummy frame. */
937 if (func
<= LOWEST_PC
)
940 /* If we've hit a wall, stop. */
941 if (cache
->prev_sp
== 0)
944 id
= frame_id_build (cache
->prev_sp
, func
);
949 arm_prologue_prev_register (struct frame_info
*next_frame
,
953 enum lval_type
*lvalp
,
958 struct arm_prologue_cache
*cache
;
960 if (*this_cache
== NULL
)
961 *this_cache
= arm_make_prologue_cache (next_frame
);
964 /* If we are asked to unwind the PC, then we need to return the LR
965 instead. The saved value of PC points into this frame's
966 prologue, not the next frame's resume location. */
967 if (prev_regnum
== ARM_PC_REGNUM
)
968 prev_regnum
= ARM_LR_REGNUM
;
970 /* SP is generally not saved to the stack, but this frame is
971 identified by NEXT_FRAME's stack pointer at the time of the call.
972 The value was already reconstructed into PREV_SP. */
973 if (prev_regnum
== ARM_SP_REGNUM
)
977 store_unsigned_integer (valuep
, 4, cache
->prev_sp
);
981 trad_frame_get_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
982 optimized
, lvalp
, addrp
, realnump
, valuep
);
985 struct frame_unwind arm_prologue_unwind
= {
987 arm_prologue_this_id
,
988 arm_prologue_prev_register
991 static const struct frame_unwind
*
992 arm_prologue_unwind_sniffer (struct frame_info
*next_frame
)
994 return &arm_prologue_unwind
;
997 static struct arm_prologue_cache
*
998 arm_make_stub_cache (struct frame_info
*next_frame
)
1001 struct arm_prologue_cache
*cache
;
1002 CORE_ADDR unwound_fp
;
1004 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1005 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1007 cache
->prev_sp
= frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
);
1012 /* Our frame ID for a stub frame is the current SP and LR. */
1015 arm_stub_this_id (struct frame_info
*next_frame
,
1017 struct frame_id
*this_id
)
1019 struct arm_prologue_cache
*cache
;
1021 if (*this_cache
== NULL
)
1022 *this_cache
= arm_make_stub_cache (next_frame
);
1023 cache
= *this_cache
;
1025 *this_id
= frame_id_build (cache
->prev_sp
,
1026 frame_pc_unwind (next_frame
));
1029 struct frame_unwind arm_stub_unwind
= {
1032 arm_prologue_prev_register
1035 static const struct frame_unwind
*
1036 arm_stub_unwind_sniffer (struct frame_info
*next_frame
)
1038 CORE_ADDR addr_in_block
;
1041 addr_in_block
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1042 if (in_plt_section (addr_in_block
, NULL
)
1043 || target_read_memory (frame_pc_unwind (next_frame
), dummy
, 4) != 0)
1044 return &arm_stub_unwind
;
1050 arm_normal_frame_base (struct frame_info
*next_frame
, void **this_cache
)
1052 struct arm_prologue_cache
*cache
;
1054 if (*this_cache
== NULL
)
1055 *this_cache
= arm_make_prologue_cache (next_frame
);
1056 cache
= *this_cache
;
1058 return cache
->prev_sp
+ cache
->frameoffset
- cache
->framesize
;
1061 struct frame_base arm_normal_base
= {
1062 &arm_prologue_unwind
,
1063 arm_normal_frame_base
,
1064 arm_normal_frame_base
,
1065 arm_normal_frame_base
1068 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1069 dummy frame. The frame ID's base needs to match the TOS value
1070 saved by save_dummy_frame_tos() and returned from
1071 arm_push_dummy_call, and the PC needs to match the dummy frame's
1074 static struct frame_id
1075 arm_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1077 return frame_id_build (frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
),
1078 frame_pc_unwind (next_frame
));
1081 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1082 be used to construct the previous frame's ID, after looking up the
1083 containing function). */
1086 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1089 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1090 return arm_addr_bits_remove (pc
);
1094 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1096 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1099 /* When arguments must be pushed onto the stack, they go on in reverse
1100 order. The code below implements a FILO (stack) to do this. */
1105 struct stack_item
*prev
;
1109 static struct stack_item
*
1110 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1112 struct stack_item
*si
;
1113 si
= xmalloc (sizeof (struct stack_item
));
1114 si
->data
= xmalloc (len
);
1117 memcpy (si
->data
, contents
, len
);
1121 static struct stack_item
*
1122 pop_stack_item (struct stack_item
*si
)
1124 struct stack_item
*dead
= si
;
1132 /* Return the alignment (in bytes) of the given type. */
1135 arm_type_align (struct type
*t
)
1141 t
= check_typedef (t
);
1142 switch (TYPE_CODE (t
))
1145 /* Should never happen. */
1146 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1150 case TYPE_CODE_ENUM
:
1154 case TYPE_CODE_RANGE
:
1155 case TYPE_CODE_BITSTRING
:
1157 case TYPE_CODE_CHAR
:
1158 case TYPE_CODE_BOOL
:
1159 return TYPE_LENGTH (t
);
1161 case TYPE_CODE_ARRAY
:
1162 case TYPE_CODE_COMPLEX
:
1163 /* TODO: What about vector types? */
1164 return arm_type_align (TYPE_TARGET_TYPE (t
));
1166 case TYPE_CODE_STRUCT
:
1167 case TYPE_CODE_UNION
:
1169 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1171 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
1179 /* We currently only support passing parameters in integer registers. This
1180 conforms with GCC's default model. Several other variants exist and
1181 we should probably support some of them based on the selected ABI. */
1184 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1185 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1186 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1187 CORE_ADDR struct_addr
)
1192 struct stack_item
*si
= NULL
;
1194 /* Set the return address. For the ARM, the return breakpoint is
1195 always at BP_ADDR. */
1196 /* XXX Fix for Thumb. */
1197 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1199 /* Walk through the list of args and determine how large a temporary
1200 stack is required. Need to take care here as structs may be
1201 passed on the stack, and we have to to push them. */
1204 argreg
= ARM_A1_REGNUM
;
1207 /* The struct_return pointer occupies the first parameter
1208 passing register. */
1212 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = 0x%s\n",
1213 gdbarch_register_name (current_gdbarch
, argreg
),
1214 paddr (struct_addr
));
1215 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1219 for (argnum
= 0; argnum
< nargs
; argnum
++)
1222 struct type
*arg_type
;
1223 struct type
*target_type
;
1224 enum type_code typecode
;
1228 arg_type
= check_typedef (value_type (args
[argnum
]));
1229 len
= TYPE_LENGTH (arg_type
);
1230 target_type
= TYPE_TARGET_TYPE (arg_type
);
1231 typecode
= TYPE_CODE (arg_type
);
1232 val
= value_contents_writeable (args
[argnum
]);
1234 align
= arm_type_align (arg_type
);
1235 /* Round alignment up to a whole number of words. */
1236 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
1237 /* Different ABIs have different maximum alignments. */
1238 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
1240 /* The APCS ABI only requires word alignment. */
1241 align
= INT_REGISTER_SIZE
;
1245 /* The AAPCS requires at most doubleword alignment. */
1246 if (align
> INT_REGISTER_SIZE
* 2)
1247 align
= INT_REGISTER_SIZE
* 2;
1250 /* Push stack padding for dowubleword alignment. */
1251 if (nstack
& (align
- 1))
1253 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1254 nstack
+= INT_REGISTER_SIZE
;
1257 /* Doubleword aligned quantities must go in even register pairs. */
1258 if (argreg
<= ARM_LAST_ARG_REGNUM
1259 && align
> INT_REGISTER_SIZE
1263 /* If the argument is a pointer to a function, and it is a
1264 Thumb function, create a LOCAL copy of the value and set
1265 the THUMB bit in it. */
1266 if (TYPE_CODE_PTR
== typecode
1267 && target_type
!= NULL
1268 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1270 CORE_ADDR regval
= extract_unsigned_integer (val
, len
);
1271 if (arm_pc_is_thumb (regval
))
1274 store_unsigned_integer (val
, len
, MAKE_THUMB_ADDR (regval
));
1278 /* Copy the argument to general registers or the stack in
1279 register-sized pieces. Large arguments are split between
1280 registers and stack. */
1283 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
1285 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1287 /* The argument is being passed in a general purpose
1289 CORE_ADDR regval
= extract_unsigned_integer (val
, partial_len
);
1290 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1291 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
1293 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1295 gdbarch_register_name
1296 (current_gdbarch
, argreg
),
1297 phex (regval
, INT_REGISTER_SIZE
));
1298 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1303 /* Push the arguments onto the stack. */
1305 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1307 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1308 nstack
+= INT_REGISTER_SIZE
;
1315 /* If we have an odd number of words to push, then decrement the stack
1316 by one word now, so first stack argument will be dword aligned. */
1323 write_memory (sp
, si
->data
, si
->len
);
1324 si
= pop_stack_item (si
);
1327 /* Finally, update teh SP register. */
1328 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1334 /* Always align the frame to an 8-byte boundary. This is required on
1335 some platforms and harmless on the rest. */
1338 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1340 /* Align the stack to eight bytes. */
1341 return sp
& ~ (CORE_ADDR
) 7;
1345 print_fpu_flags (int flags
)
1347 if (flags
& (1 << 0))
1348 fputs ("IVO ", stdout
);
1349 if (flags
& (1 << 1))
1350 fputs ("DVZ ", stdout
);
1351 if (flags
& (1 << 2))
1352 fputs ("OFL ", stdout
);
1353 if (flags
& (1 << 3))
1354 fputs ("UFL ", stdout
);
1355 if (flags
& (1 << 4))
1356 fputs ("INX ", stdout
);
1360 /* Print interesting information about the floating point processor
1361 (if present) or emulator. */
1363 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1364 struct frame_info
*frame
, const char *args
)
1366 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
1369 type
= (status
>> 24) & 127;
1370 if (status
& (1 << 31))
1371 printf (_("Hardware FPU type %d\n"), type
);
1373 printf (_("Software FPU type %d\n"), type
);
1374 /* i18n: [floating point unit] mask */
1375 fputs (_("mask: "), stdout
);
1376 print_fpu_flags (status
>> 16);
1377 /* i18n: [floating point unit] flags */
1378 fputs (_("flags: "), stdout
);
1379 print_fpu_flags (status
);
1382 /* Return the GDB type object for the "standard" data type of data in
1385 static struct type
*
1386 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
1388 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1389 return builtin_type_arm_ext
;
1390 else if (regnum
== ARM_SP_REGNUM
)
1391 return builtin_type_void_data_ptr
;
1392 else if (regnum
== ARM_PC_REGNUM
)
1393 return builtin_type_void_func_ptr
;
1394 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
1395 /* These registers are only supported on targets which supply
1396 an XML description. */
1397 return builtin_type_int0
;
1399 return builtin_type_uint32
;
1402 /* Map a DWARF register REGNUM onto the appropriate GDB register
1406 arm_dwarf_reg_to_regnum (int reg
)
1408 /* Core integer regs. */
1409 if (reg
>= 0 && reg
<= 15)
1412 /* Legacy FPA encoding. These were once used in a way which
1413 overlapped with VFP register numbering, so their use is
1414 discouraged, but GDB doesn't support the ARM toolchain
1415 which used them for VFP. */
1416 if (reg
>= 16 && reg
<= 23)
1417 return ARM_F0_REGNUM
+ reg
- 16;
1419 /* New assignments for the FPA registers. */
1420 if (reg
>= 96 && reg
<= 103)
1421 return ARM_F0_REGNUM
+ reg
- 96;
1423 /* WMMX register assignments. */
1424 if (reg
>= 104 && reg
<= 111)
1425 return ARM_WCGR0_REGNUM
+ reg
- 104;
1427 if (reg
>= 112 && reg
<= 127)
1428 return ARM_WR0_REGNUM
+ reg
- 112;
1430 if (reg
>= 192 && reg
<= 199)
1431 return ARM_WC0_REGNUM
+ reg
- 192;
1436 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1438 arm_register_sim_regno (int regnum
)
1441 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (current_gdbarch
));
1443 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
1444 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
1446 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
1447 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
1449 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
1450 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
1452 if (reg
< NUM_GREGS
)
1453 return SIM_ARM_R0_REGNUM
+ reg
;
1456 if (reg
< NUM_FREGS
)
1457 return SIM_ARM_FP0_REGNUM
+ reg
;
1460 if (reg
< NUM_SREGS
)
1461 return SIM_ARM_FPS_REGNUM
+ reg
;
1464 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
1467 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1468 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1469 It is thought that this is is the floating-point register format on
1470 little-endian systems. */
1473 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
1477 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1478 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1480 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1482 floatformat_from_doublest (fmt
, &d
, dbl
);
1486 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
)
1489 floatformat_to_doublest (fmt
, ptr
, &d
);
1490 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1491 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1493 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1498 condition_true (unsigned long cond
, unsigned long status_reg
)
1500 if (cond
== INST_AL
|| cond
== INST_NV
)
1506 return ((status_reg
& FLAG_Z
) != 0);
1508 return ((status_reg
& FLAG_Z
) == 0);
1510 return ((status_reg
& FLAG_C
) != 0);
1512 return ((status_reg
& FLAG_C
) == 0);
1514 return ((status_reg
& FLAG_N
) != 0);
1516 return ((status_reg
& FLAG_N
) == 0);
1518 return ((status_reg
& FLAG_V
) != 0);
1520 return ((status_reg
& FLAG_V
) == 0);
1522 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1524 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1526 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1528 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1530 return (((status_reg
& FLAG_Z
) == 0) &&
1531 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1533 return (((status_reg
& FLAG_Z
) != 0) ||
1534 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1539 /* Support routines for single stepping. Calculate the next PC value. */
1540 #define submask(x) ((1L << ((x) + 1)) - 1)
1541 #define bit(obj,st) (((obj) >> (st)) & 1)
1542 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1543 #define sbits(obj,st,fn) \
1544 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1545 #define BranchDest(addr,instr) \
1546 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1549 static unsigned long
1550 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
1551 unsigned long pc_val
, unsigned long status_reg
)
1553 unsigned long res
, shift
;
1554 int rm
= bits (inst
, 0, 3);
1555 unsigned long shifttype
= bits (inst
, 5, 6);
1559 int rs
= bits (inst
, 8, 11);
1560 shift
= (rs
== 15 ? pc_val
+ 8
1561 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
1564 shift
= bits (inst
, 7, 11);
1567 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1568 + (bit (inst
, 4) ? 12 : 8))
1569 : get_frame_register_unsigned (frame
, rm
));
1574 res
= shift
>= 32 ? 0 : res
<< shift
;
1578 res
= shift
>= 32 ? 0 : res
>> shift
;
1584 res
= ((res
& 0x80000000L
)
1585 ? ~((~res
) >> shift
) : res
>> shift
);
1588 case 3: /* ROR/RRX */
1591 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1593 res
= (res
>> shift
) | (res
<< (32 - shift
));
1597 return res
& 0xffffffff;
1600 /* Return number of 1-bits in VAL. */
1603 bitcount (unsigned long val
)
1606 for (nbits
= 0; val
!= 0; nbits
++)
1607 val
&= val
- 1; /* delete rightmost 1-bit in val */
1612 thumb_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1614 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1615 unsigned short inst1
= read_memory_unsigned_integer (pc
, 2);
1616 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1617 unsigned long offset
;
1619 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1623 /* Fetch the saved PC from the stack. It's stored above
1624 all of the other registers. */
1625 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
1626 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
1627 nextpc
= (CORE_ADDR
) read_memory_unsigned_integer (sp
+ offset
, 4);
1628 nextpc
= gdbarch_addr_bits_remove (current_gdbarch
, nextpc
);
1630 error (_("Infinite loop detected"));
1632 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1634 unsigned long status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
1635 unsigned long cond
= bits (inst1
, 8, 11);
1636 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1637 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1639 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1641 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1643 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link, and blx */
1645 unsigned short inst2
= read_memory_unsigned_integer (pc
+ 2, 2);
1646 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1647 nextpc
= pc_val
+ offset
;
1648 /* For BLX make sure to clear the low bits. */
1649 if (bits (inst2
, 11, 12) == 1)
1650 nextpc
= nextpc
& 0xfffffffc;
1652 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
1654 if (bits (inst1
, 3, 6) == 0x0f)
1657 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
1659 nextpc
= gdbarch_addr_bits_remove (current_gdbarch
, nextpc
);
1661 error (_("Infinite loop detected"));
1668 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1670 unsigned long pc_val
;
1671 unsigned long this_instr
;
1672 unsigned long status
;
1675 if (arm_pc_is_thumb (pc
))
1676 return thumb_get_next_pc (frame
, pc
);
1678 pc_val
= (unsigned long) pc
;
1679 this_instr
= read_memory_unsigned_integer (pc
, 4);
1680 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
1681 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1683 if (condition_true (bits (this_instr
, 28, 31), status
))
1685 switch (bits (this_instr
, 24, 27))
1688 case 0x1: /* data processing */
1692 unsigned long operand1
, operand2
, result
= 0;
1696 if (bits (this_instr
, 12, 15) != 15)
1699 if (bits (this_instr
, 22, 25) == 0
1700 && bits (this_instr
, 4, 7) == 9) /* multiply */
1701 error (_("Invalid update to pc in instruction"));
1703 /* BX <reg>, BLX <reg> */
1704 if (bits (this_instr
, 4, 27) == 0x12fff1
1705 || bits (this_instr
, 4, 27) == 0x12fff3)
1707 rn
= bits (this_instr
, 0, 3);
1708 result
= (rn
== 15) ? pc_val
+ 8
1709 : get_frame_register_unsigned (frame
, rn
);
1710 nextpc
= (CORE_ADDR
) gdbarch_addr_bits_remove
1711 (current_gdbarch
, result
);
1714 error (_("Infinite loop detected"));
1719 /* Multiply into PC */
1720 c
= (status
& FLAG_C
) ? 1 : 0;
1721 rn
= bits (this_instr
, 16, 19);
1722 operand1
= (rn
== 15) ? pc_val
+ 8
1723 : get_frame_register_unsigned (frame
, rn
);
1725 if (bit (this_instr
, 25))
1727 unsigned long immval
= bits (this_instr
, 0, 7);
1728 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1729 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1732 else /* operand 2 is a shifted register */
1733 operand2
= shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
);
1735 switch (bits (this_instr
, 21, 24))
1738 result
= operand1
& operand2
;
1742 result
= operand1
^ operand2
;
1746 result
= operand1
- operand2
;
1750 result
= operand2
- operand1
;
1754 result
= operand1
+ operand2
;
1758 result
= operand1
+ operand2
+ c
;
1762 result
= operand1
- operand2
+ c
;
1766 result
= operand2
- operand1
+ c
;
1772 case 0xb: /* tst, teq, cmp, cmn */
1773 result
= (unsigned long) nextpc
;
1777 result
= operand1
| operand2
;
1781 /* Always step into a function. */
1786 result
= operand1
& ~operand2
;
1793 nextpc
= (CORE_ADDR
) gdbarch_addr_bits_remove
1794 (current_gdbarch
, result
);
1797 error (_("Infinite loop detected"));
1802 case 0x5: /* data transfer */
1805 if (bit (this_instr
, 20))
1808 if (bits (this_instr
, 12, 15) == 15)
1814 if (bit (this_instr
, 22))
1815 error (_("Invalid update to pc in instruction"));
1817 /* byte write to PC */
1818 rn
= bits (this_instr
, 16, 19);
1819 base
= (rn
== 15) ? pc_val
+ 8
1820 : get_frame_register_unsigned (frame
, rn
);
1821 if (bit (this_instr
, 24))
1824 int c
= (status
& FLAG_C
) ? 1 : 0;
1825 unsigned long offset
=
1826 (bit (this_instr
, 25)
1827 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
1828 : bits (this_instr
, 0, 11));
1830 if (bit (this_instr
, 23))
1835 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1838 nextpc
= gdbarch_addr_bits_remove (current_gdbarch
, nextpc
);
1841 error (_("Infinite loop detected"));
1847 case 0x9: /* block transfer */
1848 if (bit (this_instr
, 20))
1851 if (bit (this_instr
, 15))
1856 if (bit (this_instr
, 23))
1859 unsigned long reglist
= bits (this_instr
, 0, 14);
1860 offset
= bitcount (reglist
) * 4;
1861 if (bit (this_instr
, 24)) /* pre */
1864 else if (bit (this_instr
, 24))
1868 unsigned long rn_val
=
1869 get_frame_register_unsigned (frame
,
1870 bits (this_instr
, 16, 19));
1872 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1876 nextpc
= gdbarch_addr_bits_remove
1877 (current_gdbarch
, nextpc
);
1879 error (_("Infinite loop detected"));
1884 case 0xb: /* branch & link */
1885 case 0xa: /* branch */
1887 nextpc
= BranchDest (pc
, this_instr
);
1890 if (bits (this_instr
, 28, 31) == INST_NV
)
1891 nextpc
|= bit (this_instr
, 24) << 1;
1893 nextpc
= gdbarch_addr_bits_remove (current_gdbarch
, nextpc
);
1895 error (_("Infinite loop detected"));
1901 case 0xe: /* coproc ops */
1906 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
1914 /* single_step() is called just before we want to resume the inferior,
1915 if we want to single-step it but there is no hardware or kernel
1916 single-step support. We find the target of the coming instruction
1917 and breakpoint it. */
1920 arm_software_single_step (struct frame_info
*frame
)
1922 /* NOTE: This may insert the wrong breakpoint instruction when
1923 single-stepping over a mode-changing instruction, if the
1924 CPSR heuristics are used. */
1926 CORE_ADDR next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
1927 insert_single_step_breakpoint (next_pc
);
1932 #include "bfd-in2.h"
1933 #include "libcoff.h"
1936 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
1938 if (arm_pc_is_thumb (memaddr
))
1940 static asymbol
*asym
;
1941 static combined_entry_type ce
;
1942 static struct coff_symbol_struct csym
;
1943 static struct bfd fake_bfd
;
1944 static bfd_target fake_target
;
1946 if (csym
.native
== NULL
)
1948 /* Create a fake symbol vector containing a Thumb symbol.
1949 This is solely so that the code in print_insn_little_arm()
1950 and print_insn_big_arm() in opcodes/arm-dis.c will detect
1951 the presence of a Thumb symbol and switch to decoding
1952 Thumb instructions. */
1954 fake_target
.flavour
= bfd_target_coff_flavour
;
1955 fake_bfd
.xvec
= &fake_target
;
1956 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
1958 csym
.symbol
.the_bfd
= &fake_bfd
;
1959 csym
.symbol
.name
= "fake";
1960 asym
= (asymbol
*) & csym
;
1963 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
1964 info
->symbols
= &asym
;
1967 info
->symbols
= NULL
;
1969 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1970 return print_insn_big_arm (memaddr
, info
);
1972 return print_insn_little_arm (memaddr
, info
);
1975 /* The following define instruction sequences that will cause ARM
1976 cpu's to take an undefined instruction trap. These are used to
1977 signal a breakpoint to GDB.
1979 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
1980 modes. A different instruction is required for each mode. The ARM
1981 cpu's can also be big or little endian. Thus four different
1982 instructions are needed to support all cases.
1984 Note: ARMv4 defines several new instructions that will take the
1985 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
1986 not in fact add the new instructions. The new undefined
1987 instructions in ARMv4 are all instructions that had no defined
1988 behaviour in earlier chips. There is no guarantee that they will
1989 raise an exception, but may be treated as NOP's. In practice, it
1990 may only safe to rely on instructions matching:
1992 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1993 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1994 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
1996 Even this may only true if the condition predicate is true. The
1997 following use a condition predicate of ALWAYS so it is always TRUE.
1999 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2000 and NetBSD all use a software interrupt rather than an undefined
2001 instruction to force a trap. This can be handled by by the
2002 abi-specific code during establishment of the gdbarch vector. */
2004 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2005 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2006 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
2007 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
2009 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
2010 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
2011 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2012 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2014 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2015 the program counter value to determine whether a 16-bit or 32-bit
2016 breakpoint should be used. It returns a pointer to a string of
2017 bytes that encode a breakpoint instruction, stores the length of
2018 the string to *lenptr, and adjusts the program counter (if
2019 necessary) to point to the actual memory location where the
2020 breakpoint should be inserted. */
2022 static const unsigned char *
2023 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
2025 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2027 if (arm_pc_is_thumb (*pcptr
))
2029 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2030 *lenptr
= tdep
->thumb_breakpoint_size
;
2031 return tdep
->thumb_breakpoint
;
2035 *lenptr
= tdep
->arm_breakpoint_size
;
2036 return tdep
->arm_breakpoint
;
2040 /* Extract from an array REGBUF containing the (raw) register state a
2041 function return value of type TYPE, and copy that, in virtual
2042 format, into VALBUF. */
2045 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
2048 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2050 switch (gdbarch_tdep (current_gdbarch
)->fp_model
)
2054 /* The value is in register F0 in internal format. We need to
2055 extract the raw value and then convert it to the desired
2057 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
2059 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
2060 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
2065 case ARM_FLOAT_SOFT_FPA
:
2066 case ARM_FLOAT_SOFT_VFP
:
2067 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
2068 if (TYPE_LENGTH (type
) > 4)
2069 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
2070 valbuf
+ INT_REGISTER_SIZE
);
2075 (__FILE__
, __LINE__
,
2076 _("arm_extract_return_value: Floating point model not supported"));
2080 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2081 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2082 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2083 || TYPE_CODE (type
) == TYPE_CODE_PTR
2084 || TYPE_CODE (type
) == TYPE_CODE_REF
2085 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2087 /* If the the type is a plain integer, then the access is
2088 straight-forward. Otherwise we have to play around a bit more. */
2089 int len
= TYPE_LENGTH (type
);
2090 int regno
= ARM_A1_REGNUM
;
2095 /* By using store_unsigned_integer we avoid having to do
2096 anything special for small big-endian values. */
2097 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2098 store_unsigned_integer (valbuf
,
2099 (len
> INT_REGISTER_SIZE
2100 ? INT_REGISTER_SIZE
: len
),
2102 len
-= INT_REGISTER_SIZE
;
2103 valbuf
+= INT_REGISTER_SIZE
;
2108 /* For a structure or union the behaviour is as if the value had
2109 been stored to word-aligned memory and then loaded into
2110 registers with 32-bit load instruction(s). */
2111 int len
= TYPE_LENGTH (type
);
2112 int regno
= ARM_A1_REGNUM
;
2113 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2117 regcache_cooked_read (regs
, regno
++, tmpbuf
);
2118 memcpy (valbuf
, tmpbuf
,
2119 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2120 len
-= INT_REGISTER_SIZE
;
2121 valbuf
+= INT_REGISTER_SIZE
;
2127 /* Will a function return an aggregate type in memory or in a
2128 register? Return 0 if an aggregate type can be returned in a
2129 register, 1 if it must be returned in memory. */
2132 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2135 enum type_code code
;
2137 CHECK_TYPEDEF (type
);
2139 /* In the ARM ABI, "integer" like aggregate types are returned in
2140 registers. For an aggregate type to be integer like, its size
2141 must be less than or equal to INT_REGISTER_SIZE and the
2142 offset of each addressable subfield must be zero. Note that bit
2143 fields are not addressable, and all addressable subfields of
2144 unions always start at offset zero.
2146 This function is based on the behaviour of GCC 2.95.1.
2147 See: gcc/arm.c: arm_return_in_memory() for details.
2149 Note: All versions of GCC before GCC 2.95.2 do not set up the
2150 parameters correctly for a function returning the following
2151 structure: struct { float f;}; This should be returned in memory,
2152 not a register. Richard Earnshaw sent me a patch, but I do not
2153 know of any way to detect if a function like the above has been
2154 compiled with the correct calling convention. */
2156 /* All aggregate types that won't fit in a register must be returned
2158 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
2163 /* The AAPCS says all aggregates not larger than a word are returned
2165 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
2168 /* The only aggregate types that can be returned in a register are
2169 structs and unions. Arrays must be returned in memory. */
2170 code
= TYPE_CODE (type
);
2171 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2176 /* Assume all other aggregate types can be returned in a register.
2177 Run a check for structures, unions and arrays. */
2180 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2183 /* Need to check if this struct/union is "integer" like. For
2184 this to be true, its size must be less than or equal to
2185 INT_REGISTER_SIZE and the offset of each addressable
2186 subfield must be zero. Note that bit fields are not
2187 addressable, and unions always start at offset zero. If any
2188 of the subfields is a floating point type, the struct/union
2189 cannot be an integer type. */
2191 /* For each field in the object, check:
2192 1) Is it FP? --> yes, nRc = 1;
2193 2) Is it addressable (bitpos != 0) and
2194 not packed (bitsize == 0)?
2198 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2200 enum type_code field_type_code
;
2201 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, i
)));
2203 /* Is it a floating point type field? */
2204 if (field_type_code
== TYPE_CODE_FLT
)
2210 /* If bitpos != 0, then we have to care about it. */
2211 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2213 /* Bitfields are not addressable. If the field bitsize is
2214 zero, then the field is not packed. Hence it cannot be
2215 a bitfield or any other packed type. */
2216 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2228 /* Write into appropriate registers a function return value of type
2229 TYPE, given in virtual format. */
2232 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
2233 const gdb_byte
*valbuf
)
2235 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2237 char buf
[MAX_REGISTER_SIZE
];
2239 switch (gdbarch_tdep (current_gdbarch
)->fp_model
)
2243 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
);
2244 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
2247 case ARM_FLOAT_SOFT_FPA
:
2248 case ARM_FLOAT_SOFT_VFP
:
2249 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
2250 if (TYPE_LENGTH (type
) > 4)
2251 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
2252 valbuf
+ INT_REGISTER_SIZE
);
2257 (__FILE__
, __LINE__
,
2258 _("arm_store_return_value: Floating point model not supported"));
2262 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2263 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2264 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2265 || TYPE_CODE (type
) == TYPE_CODE_PTR
2266 || TYPE_CODE (type
) == TYPE_CODE_REF
2267 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2269 if (TYPE_LENGTH (type
) <= 4)
2271 /* Values of one word or less are zero/sign-extended and
2273 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2274 LONGEST val
= unpack_long (type
, valbuf
);
2276 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, val
);
2277 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
2281 /* Integral values greater than one word are stored in consecutive
2282 registers starting with r0. This will always be a multiple of
2283 the regiser size. */
2284 int len
= TYPE_LENGTH (type
);
2285 int regno
= ARM_A1_REGNUM
;
2289 regcache_cooked_write (regs
, regno
++, valbuf
);
2290 len
-= INT_REGISTER_SIZE
;
2291 valbuf
+= INT_REGISTER_SIZE
;
2297 /* For a structure or union the behaviour is as if the value had
2298 been stored to word-aligned memory and then loaded into
2299 registers with 32-bit load instruction(s). */
2300 int len
= TYPE_LENGTH (type
);
2301 int regno
= ARM_A1_REGNUM
;
2302 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2306 memcpy (tmpbuf
, valbuf
,
2307 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2308 regcache_cooked_write (regs
, regno
++, tmpbuf
);
2309 len
-= INT_REGISTER_SIZE
;
2310 valbuf
+= INT_REGISTER_SIZE
;
2316 /* Handle function return values. */
2318 static enum return_value_convention
2319 arm_return_value (struct gdbarch
*gdbarch
, struct type
*valtype
,
2320 struct regcache
*regcache
, gdb_byte
*readbuf
,
2321 const gdb_byte
*writebuf
)
2323 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2325 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2326 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2327 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2329 if (tdep
->struct_return
== pcc_struct_return
2330 || arm_return_in_memory (gdbarch
, valtype
))
2331 return RETURN_VALUE_STRUCT_CONVENTION
;
2335 arm_store_return_value (valtype
, regcache
, writebuf
);
2338 arm_extract_return_value (valtype
, regcache
, readbuf
);
2340 return RETURN_VALUE_REGISTER_CONVENTION
;
2345 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2348 char buf
[INT_REGISTER_SIZE
];
2349 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (frame
));
2351 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
2353 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2357 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
);
2361 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
2362 return the target PC. Otherwise return 0. */
2365 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
2369 CORE_ADDR start_addr
;
2371 /* Find the starting address and name of the function containing the PC. */
2372 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2375 /* If PC is in a Thumb call or return stub, return the address of the
2376 target PC, which is in a register. The thunk functions are called
2377 _call_via_xx, where x is the register name. The possible names
2378 are r0-r9, sl, fp, ip, sp, and lr. */
2379 if (strncmp (name
, "_call_via_", 10) == 0)
2381 /* Use the name suffix to determine which register contains the
2383 static char *table
[15] =
2384 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2385 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2388 int offset
= strlen (name
) - 2;
2390 for (regno
= 0; regno
<= 14; regno
++)
2391 if (strcmp (&name
[offset
], table
[regno
]) == 0)
2392 return get_frame_register_unsigned (frame
, regno
);
2395 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
2396 non-interworking calls to foo. We could decode the stubs
2397 to find the target but it's easier to use the symbol table. */
2398 namelen
= strlen (name
);
2399 if (name
[0] == '_' && name
[1] == '_'
2400 && ((namelen
> 2 + strlen ("_from_thumb")
2401 && strncmp (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb",
2402 strlen ("_from_thumb")) == 0)
2403 || (namelen
> 2 + strlen ("_from_arm")
2404 && strncmp (name
+ namelen
- strlen ("_from_arm"), "_from_arm",
2405 strlen ("_from_arm")) == 0)))
2408 int target_len
= namelen
- 2;
2409 struct minimal_symbol
*minsym
;
2410 struct objfile
*objfile
;
2411 struct obj_section
*sec
;
2413 if (name
[namelen
- 1] == 'b')
2414 target_len
-= strlen ("_from_thumb");
2416 target_len
-= strlen ("_from_arm");
2418 target_name
= alloca (target_len
+ 1);
2419 memcpy (target_name
, name
+ 2, target_len
);
2420 target_name
[target_len
] = '\0';
2422 sec
= find_pc_section (pc
);
2423 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
2424 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
2426 return SYMBOL_VALUE_ADDRESS (minsym
);
2431 return 0; /* not a stub */
2435 set_arm_command (char *args
, int from_tty
)
2437 printf_unfiltered (_("\
2438 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2439 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
2443 show_arm_command (char *args
, int from_tty
)
2445 cmd_show_list (showarmcmdlist
, from_tty
, "");
2449 arm_update_current_architecture (void)
2451 struct gdbarch_info info
;
2453 /* If the current architecture is not ARM, we have nothing to do. */
2454 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_arm
)
2457 /* Update the architecture. */
2458 gdbarch_info_init (&info
);
2460 if (!gdbarch_update_p (info
))
2461 internal_error (__FILE__
, __LINE__
, "could not update architecture");
2465 set_fp_model_sfunc (char *args
, int from_tty
,
2466 struct cmd_list_element
*c
)
2468 enum arm_float_model fp_model
;
2470 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
2471 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
2473 arm_fp_model
= fp_model
;
2477 if (fp_model
== ARM_FLOAT_LAST
)
2478 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
2481 arm_update_current_architecture ();
2485 show_fp_model (struct ui_file
*file
, int from_tty
,
2486 struct cmd_list_element
*c
, const char *value
)
2488 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2490 if (arm_fp_model
== ARM_FLOAT_AUTO
2491 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2492 fprintf_filtered (file
, _("\
2493 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2494 fp_model_strings
[tdep
->fp_model
]);
2496 fprintf_filtered (file
, _("\
2497 The current ARM floating point model is \"%s\".\n"),
2498 fp_model_strings
[arm_fp_model
]);
2502 arm_set_abi (char *args
, int from_tty
,
2503 struct cmd_list_element
*c
)
2505 enum arm_abi_kind arm_abi
;
2507 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
2508 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
2510 arm_abi_global
= arm_abi
;
2514 if (arm_abi
== ARM_ABI_LAST
)
2515 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
2518 arm_update_current_architecture ();
2522 arm_show_abi (struct ui_file
*file
, int from_tty
,
2523 struct cmd_list_element
*c
, const char *value
)
2525 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2527 if (arm_abi_global
== ARM_ABI_AUTO
2528 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2529 fprintf_filtered (file
, _("\
2530 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2531 arm_abi_strings
[tdep
->arm_abi
]);
2533 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
2537 /* If the user changes the register disassembly style used for info
2538 register and other commands, we have to also switch the style used
2539 in opcodes for disassembly output. This function is run in the "set
2540 arm disassembly" command, and does that. */
2543 set_disassembly_style_sfunc (char *args
, int from_tty
,
2544 struct cmd_list_element
*c
)
2546 set_disassembly_style ();
2549 /* Return the ARM register name corresponding to register I. */
2551 arm_register_name (int i
)
2553 if (i
>= ARRAY_SIZE (arm_register_names
))
2554 /* These registers are only supported on targets which supply
2555 an XML description. */
2558 return arm_register_names
[i
];
2562 set_disassembly_style (void)
2566 /* Find the style that the user wants. */
2567 for (current
= 0; current
< num_disassembly_options
; current
++)
2568 if (disassembly_style
== valid_disassembly_styles
[current
])
2570 gdb_assert (current
< num_disassembly_options
);
2572 /* Synchronize the disassembler. */
2573 set_arm_regname_option (current
);
2576 /* Test whether the coff symbol specific value corresponds to a Thumb
2580 coff_sym_is_thumb (int val
)
2582 return (val
== C_THUMBEXT
||
2583 val
== C_THUMBSTAT
||
2584 val
== C_THUMBEXTFUNC
||
2585 val
== C_THUMBSTATFUNC
||
2586 val
== C_THUMBLABEL
);
2589 /* arm_coff_make_msymbol_special()
2590 arm_elf_make_msymbol_special()
2592 These functions test whether the COFF or ELF symbol corresponds to
2593 an address in thumb code, and set a "special" bit in a minimal
2594 symbol to indicate that it does. */
2597 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2599 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2601 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2603 MSYMBOL_SET_SPECIAL (msym
);
2607 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2609 if (coff_sym_is_thumb (val
))
2610 MSYMBOL_SET_SPECIAL (msym
);
2614 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2616 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
2618 /* If necessary, set the T bit. */
2622 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
2623 if (arm_pc_is_thumb (pc
))
2624 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
, val
| 0x20);
2626 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
2627 val
& ~(ULONGEST
) 0x20);
2631 static struct value
*
2632 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
2634 const int *reg_p
= baton
;
2635 return value_of_register (*reg_p
, frame
);
2638 static enum gdb_osabi
2639 arm_elf_osabi_sniffer (bfd
*abfd
)
2641 unsigned int elfosabi
;
2642 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2644 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2646 if (elfosabi
== ELFOSABI_ARM
)
2647 /* GNU tools use this value. Check note sections in this case,
2649 bfd_map_over_sections (abfd
,
2650 generic_elf_osabi_sniff_abi_tag_sections
,
2653 /* Anything else will be handled by the generic ELF sniffer. */
2658 /* Initialize the current architecture based on INFO. If possible,
2659 re-use an architecture from ARCHES, which is a list of
2660 architectures already created during this debugging session.
2662 Called e.g. at program startup, when reading a core file, and when
2663 reading a binary file. */
2665 static struct gdbarch
*
2666 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2668 struct gdbarch_tdep
*tdep
;
2669 struct gdbarch
*gdbarch
;
2670 struct gdbarch_list
*best_arch
;
2671 enum arm_abi_kind arm_abi
= arm_abi_global
;
2672 enum arm_float_model fp_model
= arm_fp_model
;
2673 struct tdesc_arch_data
*tdesc_data
= NULL
;
2675 int have_fpa_registers
= 1;
2677 /* Check any target description for validity. */
2678 if (tdesc_has_registers (info
.target_desc
))
2680 /* For most registers we require GDB's default names; but also allow
2681 the numeric names for sp / lr / pc, as a convenience. */
2682 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
2683 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
2684 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
2686 const struct tdesc_feature
*feature
;
2689 feature
= tdesc_find_feature (info
.target_desc
,
2690 "org.gnu.gdb.arm.core");
2691 if (feature
== NULL
)
2694 tdesc_data
= tdesc_data_alloc ();
2697 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
2698 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
2699 arm_register_names
[i
]);
2700 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2703 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2706 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2709 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2710 ARM_PS_REGNUM
, "cpsr");
2714 tdesc_data_cleanup (tdesc_data
);
2718 feature
= tdesc_find_feature (info
.target_desc
,
2719 "org.gnu.gdb.arm.fpa");
2720 if (feature
!= NULL
)
2723 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
2724 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
2725 arm_register_names
[i
]);
2728 tdesc_data_cleanup (tdesc_data
);
2733 have_fpa_registers
= 0;
2735 feature
= tdesc_find_feature (info
.target_desc
,
2736 "org.gnu.gdb.xscale.iwmmxt");
2737 if (feature
!= NULL
)
2739 static const char *const iwmmxt_names
[] = {
2740 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
2741 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
2742 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
2743 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
2747 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
2749 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
2750 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
2752 /* Check for the control registers, but do not fail if they
2754 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
2755 tdesc_numbered_register (feature
, tdesc_data
, i
,
2756 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
2758 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
2760 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
2761 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
2765 tdesc_data_cleanup (tdesc_data
);
2771 /* If we have an object to base this architecture on, try to determine
2774 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
2776 int ei_osabi
, e_flags
;
2778 switch (bfd_get_flavour (info
.abfd
))
2780 case bfd_target_aout_flavour
:
2781 /* Assume it's an old APCS-style ABI. */
2782 arm_abi
= ARM_ABI_APCS
;
2785 case bfd_target_coff_flavour
:
2786 /* Assume it's an old APCS-style ABI. */
2788 arm_abi
= ARM_ABI_APCS
;
2791 case bfd_target_elf_flavour
:
2792 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
2793 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2795 if (ei_osabi
== ELFOSABI_ARM
)
2797 /* GNU tools used to use this value, but do not for EABI
2798 objects. There's nowhere to tag an EABI version
2799 anyway, so assume APCS. */
2800 arm_abi
= ARM_ABI_APCS
;
2802 else if (ei_osabi
== ELFOSABI_NONE
)
2804 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
2808 case EF_ARM_EABI_UNKNOWN
:
2809 /* Assume GNU tools. */
2810 arm_abi
= ARM_ABI_APCS
;
2813 case EF_ARM_EABI_VER4
:
2814 case EF_ARM_EABI_VER5
:
2815 arm_abi
= ARM_ABI_AAPCS
;
2816 /* EABI binaries default to VFP float ordering. */
2817 if (fp_model
== ARM_FLOAT_AUTO
)
2818 fp_model
= ARM_FLOAT_SOFT_VFP
;
2822 /* Leave it as "auto". */
2823 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
2828 if (fp_model
== ARM_FLOAT_AUTO
)
2830 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2832 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
2835 /* Leave it as "auto". Strictly speaking this case
2836 means FPA, but almost nobody uses that now, and
2837 many toolchains fail to set the appropriate bits
2838 for the floating-point model they use. */
2840 case EF_ARM_SOFT_FLOAT
:
2841 fp_model
= ARM_FLOAT_SOFT_FPA
;
2843 case EF_ARM_VFP_FLOAT
:
2844 fp_model
= ARM_FLOAT_VFP
;
2846 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
2847 fp_model
= ARM_FLOAT_SOFT_VFP
;
2854 /* Leave it as "auto". */
2859 /* If there is already a candidate, use it. */
2860 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
2862 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
2864 if (arm_abi
!= ARM_ABI_AUTO
2865 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
2868 if (fp_model
!= ARM_FLOAT_AUTO
2869 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
2872 /* Found a match. */
2876 if (best_arch
!= NULL
)
2878 if (tdesc_data
!= NULL
)
2879 tdesc_data_cleanup (tdesc_data
);
2880 return best_arch
->gdbarch
;
2883 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
2884 gdbarch
= gdbarch_alloc (&info
, tdep
);
2886 /* Record additional information about the architecture we are defining.
2887 These are gdbarch discriminators, like the OSABI. */
2888 tdep
->arm_abi
= arm_abi
;
2889 tdep
->fp_model
= fp_model
;
2890 tdep
->have_fpa_registers
= have_fpa_registers
;
2893 switch (info
.byte_order
)
2895 case BFD_ENDIAN_BIG
:
2896 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
2897 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
2898 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
2899 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
2903 case BFD_ENDIAN_LITTLE
:
2904 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
2905 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
2906 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
2907 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
2912 internal_error (__FILE__
, __LINE__
,
2913 _("arm_gdbarch_init: bad byte order for float format"));
2916 /* On ARM targets char defaults to unsigned. */
2917 set_gdbarch_char_signed (gdbarch
, 0);
2919 /* This should be low enough for everything. */
2920 tdep
->lowest_pc
= 0x20;
2921 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
2923 /* The default, for both APCS and AAPCS, is to return small
2924 structures in registers. */
2925 tdep
->struct_return
= reg_struct_return
;
2927 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
2928 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
2930 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
2932 /* Frame handling. */
2933 set_gdbarch_unwind_dummy_id (gdbarch
, arm_unwind_dummy_id
);
2934 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
2935 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
2937 frame_base_set_default (gdbarch
, &arm_normal_base
);
2939 /* Address manipulation. */
2940 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
2941 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
2943 /* Advance PC across function entry code. */
2944 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
2946 /* Skip trampolines. */
2947 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
2949 /* The stack grows downward. */
2950 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2952 /* Breakpoint manipulation. */
2953 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
2955 /* Information about registers, etc. */
2956 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
2957 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
2958 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
2959 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
2960 set_gdbarch_register_type (gdbarch
, arm_register_type
);
2962 /* This "info float" is FPA-specific. Use the generic version if we
2964 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
2965 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
2967 /* Internal <-> external register number maps. */
2968 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
2969 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
2970 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
2972 set_gdbarch_register_name (gdbarch
, arm_register_name
);
2974 /* Returning results. */
2975 set_gdbarch_return_value (gdbarch
, arm_return_value
);
2978 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
2980 /* Minsymbol frobbing. */
2981 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
2982 set_gdbarch_coff_make_msymbol_special (gdbarch
,
2983 arm_coff_make_msymbol_special
);
2985 /* Virtual tables. */
2986 set_gdbarch_vbit_in_delta (gdbarch
, 1);
2988 /* Hook in the ABI-specific overrides, if they have been registered. */
2989 gdbarch_init_osabi (info
, gdbarch
);
2991 /* Add some default predicates. */
2992 frame_unwind_append_sniffer (gdbarch
, arm_stub_unwind_sniffer
);
2993 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
2994 frame_unwind_append_sniffer (gdbarch
, arm_prologue_unwind_sniffer
);
2996 /* Now we have tuned the configuration, set a few final things,
2997 based on what the OS ABI has told us. */
2999 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
3000 binaries are always marked. */
3001 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
3002 tdep
->arm_abi
= ARM_ABI_APCS
;
3004 /* We used to default to FPA for generic ARM, but almost nobody
3005 uses that now, and we now provide a way for the user to force
3006 the model. So default to the most useful variant. */
3007 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
3008 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
3010 if (tdep
->jb_pc
>= 0)
3011 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
3013 /* Floating point sizes and format. */
3014 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
3015 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
3017 set_gdbarch_double_format
3018 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
3019 set_gdbarch_long_double_format
3020 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
3024 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
3025 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
3029 tdesc_use_registers (gdbarch
, tdesc_data
);
3031 /* Add standard register aliases. We add aliases even for those
3032 nanes which are used by the current architecture - it's simpler,
3033 and does no harm, since nothing ever lists user registers. */
3034 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
3035 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
3036 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
3042 arm_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
3044 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3049 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
3050 (unsigned long) tdep
->lowest_pc
);
3053 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
3056 _initialize_arm_tdep (void)
3058 struct ui_file
*stb
;
3060 struct cmd_list_element
*new_set
, *new_show
;
3061 const char *setname
;
3062 const char *setdesc
;
3063 const char *const *regnames
;
3065 static char *helptext
;
3066 char regdesc
[1024], *rdptr
= regdesc
;
3067 size_t rest
= sizeof (regdesc
);
3069 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
3071 /* Register an ELF OS ABI sniffer for ARM binaries. */
3072 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
3073 bfd_target_elf_flavour
,
3074 arm_elf_osabi_sniffer
);
3076 /* Get the number of possible sets of register names defined in opcodes. */
3077 num_disassembly_options
= get_arm_regname_num_options ();
3079 /* Add root prefix command for all "set arm"/"show arm" commands. */
3080 add_prefix_cmd ("arm", no_class
, set_arm_command
,
3081 _("Various ARM-specific commands."),
3082 &setarmcmdlist
, "set arm ", 0, &setlist
);
3084 add_prefix_cmd ("arm", no_class
, show_arm_command
,
3085 _("Various ARM-specific commands."),
3086 &showarmcmdlist
, "show arm ", 0, &showlist
);
3088 /* Sync the opcode insn printer with our register viewer. */
3089 parse_arm_disassembler_option ("reg-names-std");
3091 /* Initialize the array that will be passed to
3092 add_setshow_enum_cmd(). */
3093 valid_disassembly_styles
3094 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
3095 for (i
= 0; i
< num_disassembly_options
; i
++)
3097 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
3098 valid_disassembly_styles
[i
] = setname
;
3099 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
3102 /* When we find the default names, tell the disassembler to use
3104 if (!strcmp (setname
, "std"))
3106 disassembly_style
= setname
;
3107 set_arm_regname_option (i
);
3110 /* Mark the end of valid options. */
3111 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
3113 /* Create the help text. */
3114 stb
= mem_fileopen ();
3115 fprintf_unfiltered (stb
, "%s%s%s",
3116 _("The valid values are:\n"),
3118 _("The default is \"std\"."));
3119 helptext
= ui_file_xstrdup (stb
, &length
);
3120 ui_file_delete (stb
);
3122 add_setshow_enum_cmd("disassembler", no_class
,
3123 valid_disassembly_styles
, &disassembly_style
,
3124 _("Set the disassembly style."),
3125 _("Show the disassembly style."),
3127 set_disassembly_style_sfunc
,
3128 NULL
, /* FIXME: i18n: The disassembly style is \"%s\". */
3129 &setarmcmdlist
, &showarmcmdlist
);
3131 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
3132 _("Set usage of ARM 32-bit mode."),
3133 _("Show usage of ARM 32-bit mode."),
3134 _("When off, a 26-bit PC will be used."),
3136 NULL
, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
3137 &setarmcmdlist
, &showarmcmdlist
);
3139 /* Add a command to allow the user to force the FPU model. */
3140 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
3141 _("Set the floating point type."),
3142 _("Show the floating point type."),
3143 _("auto - Determine the FP typefrom the OS-ABI.\n\
3144 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
3145 fpa - FPA co-processor (GCC compiled).\n\
3146 softvfp - Software FP with pure-endian doubles.\n\
3147 vfp - VFP co-processor."),
3148 set_fp_model_sfunc
, show_fp_model
,
3149 &setarmcmdlist
, &showarmcmdlist
);
3151 /* Add a command to allow the user to force the ABI. */
3152 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
3155 NULL
, arm_set_abi
, arm_show_abi
,
3156 &setarmcmdlist
, &showarmcmdlist
);
3158 /* Debugging flag. */
3159 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
3160 _("Set ARM debugging."),
3161 _("Show ARM debugging."),
3162 _("When on, arm-specific debugging is enabled."),
3164 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
3165 &setdebuglist
, &showdebuglist
);