1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 #include <ctype.h> /* XXX for isupper () */
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register styles. */
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
42 #include "gdb/sim-arm.h"
45 #include "coff/internal.h"
48 #include "gdb_assert.h"
52 /* Each OS has a different mechanism for accessing the various
53 registers stored in the sigcontext structure.
55 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
56 function pointer) which may be used to determine the addresses
57 of the various saved registers in the sigcontext structure.
59 For the ARM target, there are three parameters to this function.
60 The first is the pc value of the frame under consideration, the
61 second the stack pointer of this frame, and the last is the
62 register number to fetch.
64 If the tm.h file does not define this macro, then it's assumed that
65 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
68 When it comes time to multi-arching this code, see the identically
69 named machinery in ia64-tdep.c for an example of how it could be
70 done. It should not be necessary to modify the code below where
71 this macro is used. */
73 #ifdef SIGCONTEXT_REGISTER_ADDRESS
74 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
75 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
78 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
79 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
82 /* Macros for setting and testing a bit in a minimal symbol that marks
83 it as Thumb function. The MSB of the minimal symbol's "info" field
84 is used for this purpose.
86 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
87 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
89 #define MSYMBOL_SET_SPECIAL(msym) \
90 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
93 #define MSYMBOL_IS_SPECIAL(msym) \
94 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
96 /* The list of available "set arm ..." and "show arm ..." commands. */
97 static struct cmd_list_element
*setarmcmdlist
= NULL
;
98 static struct cmd_list_element
*showarmcmdlist
= NULL
;
100 /* The type of floating-point to use. Keep this in sync with enum
101 arm_float_model, and the help string in _initialize_arm_tdep. */
102 static const char *fp_model_strings
[] =
111 /* A variable that can be configured by the user. */
112 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
113 static const char *current_fp_model
= "auto";
115 /* Number of different reg name sets (options). */
116 static int num_disassembly_options
;
118 /* We have more registers than the disassembler as gdb can print the value
119 of special registers as well.
120 The general register names are overwritten by whatever is being used by
121 the disassembler at the moment. We also adjust the case of cpsr and fps. */
123 /* Initial value: Register names used in ARM's ISA documentation. */
124 static char * arm_register_name_strings
[] =
125 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
126 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
127 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
128 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
129 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
130 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
131 "fps", "cpsr" }; /* 24 25 */
132 static char **arm_register_names
= arm_register_name_strings
;
134 /* Valid register name styles. */
135 static const char **valid_disassembly_styles
;
137 /* Disassembly style to use. Default to "std" register names. */
138 static const char *disassembly_style
;
139 /* Index to that option in the opcodes table. */
140 static int current_option
;
142 /* This is used to keep the bfd arch_info in sync with the disassembly
144 static void set_disassembly_style_sfunc(char *, int,
145 struct cmd_list_element
*);
146 static void set_disassembly_style (void);
148 static void convert_from_extended (const struct floatformat
*, const void *,
150 static void convert_to_extended (const struct floatformat
*, void *,
153 struct arm_prologue_cache
155 /* The stack pointer at the time this frame was created; i.e. the
156 caller's stack pointer when this function was called. It is used
157 to identify this frame. */
160 /* The frame base for this frame is just prev_sp + frame offset -
161 frame size. FRAMESIZE is the size of this stack frame, and
162 FRAMEOFFSET if the initial offset from the stack pointer (this
163 frame's stack pointer, not PREV_SP) to the frame base. */
168 /* The register used to hold the frame pointer for this frame. */
171 /* Saved register offsets. */
172 struct trad_frame_saved_reg
*saved_regs
;
175 /* Addresses for calling Thumb functions have the bit 0 set.
176 Here are some macros to test, set, or clear bit 0 of addresses. */
177 #define IS_THUMB_ADDR(addr) ((addr) & 1)
178 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
179 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
181 /* Set to true if the 32-bit mode is in use. */
185 /* Flag set by arm_fix_call_dummy that tells whether the target
186 function is a Thumb function. This flag is checked by
187 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
188 its use in valops.c) to pass the function address as an additional
191 static int target_is_thumb
;
193 /* Flag set by arm_fix_call_dummy that tells whether the calling
194 function is a Thumb function. This flag is checked by
195 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
197 static int caller_is_thumb
;
199 /* Determine if the program counter specified in MEMADDR is in a Thumb
203 arm_pc_is_thumb (CORE_ADDR memaddr
)
205 struct minimal_symbol
*sym
;
207 /* If bit 0 of the address is set, assume this is a Thumb address. */
208 if (IS_THUMB_ADDR (memaddr
))
211 /* Thumb functions have a "special" bit set in minimal symbols. */
212 sym
= lookup_minimal_symbol_by_pc (memaddr
);
215 return (MSYMBOL_IS_SPECIAL (sym
));
223 /* Determine if the program counter specified in MEMADDR is in a call
224 dummy being called from a Thumb function. */
227 arm_pc_is_thumb_dummy (CORE_ADDR memaddr
)
229 CORE_ADDR sp
= read_sp ();
231 /* FIXME: Until we switch for the new call dummy macros, this heuristic
232 is the best we can do. We are trying to determine if the pc is on
233 the stack, which (hopefully) will only happen in a call dummy.
234 We hope the current stack pointer is not so far alway from the dummy
235 frame location (true if we have not pushed large data structures or
236 gone too many levels deep) and that our 1024 is not enough to consider
237 code regions as part of the stack (true for most practical purposes). */
238 if (DEPRECATED_PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 1024))
239 return caller_is_thumb
;
244 /* Remove useless bits from addresses in a running program. */
246 arm_addr_bits_remove (CORE_ADDR val
)
249 return (val
& (arm_pc_is_thumb (val
) ? 0xfffffffe : 0xfffffffc));
251 return (val
& 0x03fffffc);
254 /* When reading symbols, we need to zap the low bit of the address,
255 which may be set to 1 for Thumb functions. */
257 arm_smash_text_address (CORE_ADDR val
)
262 /* Immediately after a function call, return the saved pc. Can't
263 always go through the frames for this because on some machines the
264 new frame is not set up until the new function executes some
268 arm_saved_pc_after_call (struct frame_info
*frame
)
270 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM
));
273 /* Determine whether the function invocation represented by FI has a
274 frame on the stack associated with it. If it does return zero,
275 otherwise return 1. */
278 arm_frameless_function_invocation (struct frame_info
*fi
)
280 CORE_ADDR func_start
, after_prologue
;
283 /* Sometimes we have functions that do a little setup (like saving the
284 vN registers with the stmdb instruction, but DO NOT set up a frame.
285 The symbol table will report this as a prologue. However, it is
286 important not to try to parse these partial frames as frames, or we
287 will get really confused.
289 So I will demand 3 instructions between the start & end of the
290 prologue before I call it a real prologue, i.e. at least
295 func_start
= (get_frame_func (fi
) + FUNCTION_START_OFFSET
);
296 after_prologue
= SKIP_PROLOGUE (func_start
);
298 /* There are some frameless functions whose first two instructions
299 follow the standard APCS form, in which case after_prologue will
300 be func_start + 8. */
302 frameless
= (after_prologue
< func_start
+ 12);
306 /* A typical Thumb prologue looks like this:
310 Sometimes the latter instruction may be replaced by:
318 or, on tpcs, like this:
325 There is always one instruction of three classes:
330 When we have found at least one of each class we are done with the prolog.
331 Note that the "sub sp, #NN" before the push does not count.
335 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
337 CORE_ADDR current_pc
;
339 bit 0 - push { rlist }
340 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
341 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
345 for (current_pc
= pc
;
346 current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40;
349 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
351 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
353 findmask
|= 1; /* push found */
355 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
358 if ((findmask
& 1) == 0) /* before push ? */
361 findmask
|= 4; /* add/sub sp found */
363 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
365 findmask
|= 2; /* setting of r7 found */
367 else if (insn
== 0x466f) /* mov r7, sp */
369 findmask
|= 2; /* setting of r7 found */
371 else if (findmask
== (4+2+1))
373 /* We have found one of each type of prologue instruction */
377 /* Something in the prolog that we don't care about or some
378 instruction from outside the prolog scheduled here for
386 /* Advance the PC across any function entry prologue instructions to
387 reach some "real" code.
389 The APCS (ARM Procedure Call Standard) defines the following
393 [stmfd sp!, {a1,a2,a3,a4}]
394 stmfd sp!, {...,fp,ip,lr,pc}
395 [stfe f7, [sp, #-12]!]
396 [stfe f6, [sp, #-12]!]
397 [stfe f5, [sp, #-12]!]
398 [stfe f4, [sp, #-12]!]
399 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
402 arm_skip_prologue (CORE_ADDR pc
)
406 CORE_ADDR func_addr
, func_end
= 0;
408 struct symtab_and_line sal
;
410 /* If we're in a dummy frame, don't even try to skip the prologue. */
411 if (DEPRECATED_PC_IN_CALL_DUMMY (pc
, 0, 0))
414 /* See what the symbol table says. */
416 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
420 /* Found a function. */
421 sym
= lookup_symbol (func_name
, NULL
, VAR_DOMAIN
, NULL
, NULL
);
422 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
424 /* Don't use this trick for assembly source files. */
425 sal
= find_pc_line (func_addr
, 0);
426 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
431 /* Check if this is Thumb code. */
432 if (arm_pc_is_thumb (pc
))
433 return thumb_skip_prologue (pc
, func_end
);
435 /* Can't find the prologue end in the symbol table, try it the hard way
436 by disassembling the instructions. */
438 /* Like arm_scan_prologue, stop no later than pc + 64. */
439 if (func_end
== 0 || func_end
> pc
+ 64)
442 for (skip_pc
= pc
; skip_pc
< func_end
; skip_pc
+= 4)
444 inst
= read_memory_integer (skip_pc
, 4);
446 /* "mov ip, sp" is no longer a required part of the prologue. */
447 if (inst
== 0xe1a0c00d) /* mov ip, sp */
450 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
453 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
456 /* Some prologues begin with "str lr, [sp, #-4]!". */
457 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
460 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
463 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
466 /* Any insns after this point may float into the code, if it makes
467 for better instruction scheduling, so we skip them only if we
468 find them, but still consider the function to be frame-ful. */
470 /* We may have either one sfmfd instruction here, or several stfe
471 insns, depending on the version of floating point code we
473 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
476 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
479 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
482 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
485 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
486 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
487 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
490 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
491 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
492 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
495 /* Un-recognized instruction; stop scanning. */
499 return skip_pc
; /* End of prologue */
503 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
504 This function decodes a Thumb function prologue to determine:
505 1) the size of the stack frame
506 2) which registers are saved on it
507 3) the offsets of saved regs
508 4) the offset from the stack pointer to the frame pointer
510 A typical Thumb function prologue would create this stack frame
511 (offsets relative to FP)
512 old SP -> 24 stack parameters
515 R7 -> 0 local variables (16 bytes)
516 SP -> -12 additional stack space (12 bytes)
517 The frame size would thus be 36 bytes, and the frame offset would be
518 12 bytes. The frame register is R7.
520 The comments for thumb_skip_prolog() describe the algorithm we use
521 to detect the end of the prolog. */
525 thumb_scan_prologue (CORE_ADDR prev_pc
, struct arm_prologue_cache
*cache
)
527 CORE_ADDR prologue_start
;
528 CORE_ADDR prologue_end
;
529 CORE_ADDR current_pc
;
530 /* Which register has been copied to register n? */
533 bit 0 - push { rlist }
534 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
535 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
540 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
542 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
544 if (sal
.line
== 0) /* no line info, use current PC */
545 prologue_end
= prev_pc
;
546 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
547 prologue_end
= sal
.end
; /* (probably means no prologue) */
550 /* We're in the boondocks: allow for
551 16 pushes, an add, and "mv fp,sp". */
552 prologue_end
= prologue_start
+ 40;
554 prologue_end
= min (prologue_end
, prev_pc
);
556 /* Initialize the saved register map. When register H is copied to
557 register L, we will put H in saved_reg[L]. */
558 for (i
= 0; i
< 16; i
++)
561 /* Search the prologue looking for instructions that set up the
562 frame pointer, adjust the stack pointer, and save registers.
563 Do this until all basic prolog instructions are found. */
565 cache
->framesize
= 0;
566 for (current_pc
= prologue_start
;
567 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
574 insn
= read_memory_unsigned_integer (current_pc
, 2);
576 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
579 findmask
|= 1; /* push found */
580 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
581 whether to save LR (R14). */
582 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
584 /* Calculate offsets of saved R0-R7 and LR. */
585 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
586 if (mask
& (1 << regno
))
588 cache
->framesize
+= 4;
589 cache
->saved_regs
[saved_reg
[regno
]].addr
= -cache
->framesize
;
590 /* Reset saved register map. */
591 saved_reg
[regno
] = regno
;
594 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
597 if ((findmask
& 1) == 0) /* before push? */
600 findmask
|= 4; /* add/sub sp found */
602 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
603 if (insn
& 0x80) /* is it signed? (==subtracting) */
605 cache
->frameoffset
+= offset
;
608 cache
->framesize
-= offset
;
610 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
612 findmask
|= 2; /* setting of r7 found */
613 cache
->framereg
= THUMB_FP_REGNUM
;
614 /* get scaled offset */
615 cache
->frameoffset
= (insn
& 0xff) << 2;
617 else if (insn
== 0x466f) /* mov r7, sp */
619 findmask
|= 2; /* setting of r7 found */
620 cache
->framereg
= THUMB_FP_REGNUM
;
621 cache
->frameoffset
= 0;
622 saved_reg
[THUMB_FP_REGNUM
] = ARM_SP_REGNUM
;
624 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
626 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
627 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
628 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
631 /* Something in the prolog that we don't care about or some
632 instruction from outside the prolog scheduled here for
638 /* This function decodes an ARM function prologue to determine:
639 1) the size of the stack frame
640 2) which registers are saved on it
641 3) the offsets of saved regs
642 4) the offset from the stack pointer to the frame pointer
643 This information is stored in the "extra" fields of the frame_info.
645 There are two basic forms for the ARM prologue. The fixed argument
646 function call will look like:
649 stmfd sp!, {fp, ip, lr, pc}
653 Which would create this stack frame (offsets relative to FP):
654 IP -> 4 (caller's stack)
655 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
656 -4 LR (return address in caller)
657 -8 IP (copy of caller's SP)
659 SP -> -28 Local variables
661 The frame size would thus be 32 bytes, and the frame offset would be
662 28 bytes. The stmfd call can also save any of the vN registers it
663 plans to use, which increases the frame size accordingly.
665 Note: The stored PC is 8 off of the STMFD instruction that stored it
666 because the ARM Store instructions always store PC + 8 when you read
669 A variable argument function call will look like:
672 stmfd sp!, {a1, a2, a3, a4}
673 stmfd sp!, {fp, ip, lr, pc}
676 Which would create this stack frame (offsets relative to FP):
677 IP -> 20 (caller's stack)
682 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
683 -4 LR (return address in caller)
684 -8 IP (copy of caller's SP)
686 SP -> -28 Local variables
688 The frame size would thus be 48 bytes, and the frame offset would be
691 There is another potential complication, which is that the optimizer
692 will try to separate the store of fp in the "stmfd" instruction from
693 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
694 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
696 Also, note, the original version of the ARM toolchain claimed that there
699 instruction at the end of the prologue. I have never seen GCC produce
700 this, and the ARM docs don't mention it. We still test for it below in
706 arm_scan_prologue (struct frame_info
*next_frame
, struct arm_prologue_cache
*cache
)
708 int regno
, sp_offset
, fp_offset
, ip_offset
;
709 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
710 CORE_ADDR prev_pc
= frame_pc_unwind (next_frame
);
712 /* Assume there is no frame until proven otherwise. */
713 cache
->framereg
= ARM_SP_REGNUM
;
714 cache
->framesize
= 0;
715 cache
->frameoffset
= 0;
717 /* Check for Thumb prologue. */
718 if (arm_pc_is_thumb (prev_pc
))
720 thumb_scan_prologue (prev_pc
, cache
);
724 /* Find the function prologue. If we can't find the function in
725 the symbol table, peek in the stack frame to find the PC. */
726 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
728 /* One way to find the end of the prologue (which works well
729 for unoptimized code) is to do the following:
731 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
734 prologue_end = prev_pc;
735 else if (sal.end < prologue_end)
736 prologue_end = sal.end;
738 This mechanism is very accurate so long as the optimizer
739 doesn't move any instructions from the function body into the
740 prologue. If this happens, sal.end will be the last
741 instruction in the first hunk of prologue code just before
742 the first instruction that the scheduler has moved from
743 the body to the prologue.
745 In order to make sure that we scan all of the prologue
746 instructions, we use a slightly less accurate mechanism which
747 may scan more than necessary. To help compensate for this
748 lack of accuracy, the prologue scanning loop below contains
749 several clauses which'll cause the loop to terminate early if
750 an implausible prologue instruction is encountered.
756 is a suitable endpoint since it accounts for the largest
757 possible prologue plus up to five instructions inserted by
760 if (prologue_end
> prologue_start
+ 64)
762 prologue_end
= prologue_start
+ 64; /* See above. */
767 /* We have no symbol information. Our only option is to assume this
768 function has a standard stack frame and the normal frame register.
769 Then, we can find the value of our frame pointer on entrance to
770 the callee (or at the present moment if this is the innermost frame).
771 The value stored there should be the address of the stmfd + 8. */
773 LONGEST return_value
;
775 frame_loc
= frame_unwind_register_unsigned (next_frame
, ARM_FP_REGNUM
);
776 if (!safe_read_memory_integer (frame_loc
, 4, &return_value
))
780 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
781 prologue_end
= prologue_start
+ 64; /* See above. */
785 if (prev_pc
< prologue_end
)
786 prologue_end
= prev_pc
;
788 /* Now search the prologue looking for instructions that set up the
789 frame pointer, adjust the stack pointer, and save registers.
791 Be careful, however, and if it doesn't look like a prologue,
792 don't try to scan it. If, for instance, a frameless function
793 begins with stmfd sp!, then we will tell ourselves there is
794 a frame, which will confuse stack traceback, as well as "finish"
795 and other operations that rely on a knowledge of the stack
798 In the APCS, the prologue should start with "mov ip, sp" so
799 if we don't see this as the first insn, we will stop.
801 [Note: This doesn't seem to be true any longer, so it's now an
802 optional part of the prologue. - Kevin Buettner, 2001-11-20]
804 [Note further: The "mov ip,sp" only seems to be missing in
805 frameless functions at optimization level "-O2" or above,
806 in which case it is often (but not always) replaced by
807 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
809 sp_offset
= fp_offset
= ip_offset
= 0;
811 for (current_pc
= prologue_start
;
812 current_pc
< prologue_end
;
815 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
817 if (insn
== 0xe1a0c00d) /* mov ip, sp */
822 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
824 unsigned imm
= insn
& 0xff; /* immediate value */
825 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
826 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
830 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
832 unsigned imm
= insn
& 0xff; /* immediate value */
833 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
834 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
838 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
841 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= sp_offset
;
844 else if ((insn
& 0xffff0000) == 0xe92d0000)
845 /* stmfd sp!, {..., fp, ip, lr, pc}
847 stmfd sp!, {a1, a2, a3, a4} */
849 int mask
= insn
& 0xffff;
851 /* Calculate offsets of saved registers. */
852 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
853 if (mask
& (1 << regno
))
856 cache
->saved_regs
[regno
].addr
= sp_offset
;
859 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
860 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
861 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
863 /* No need to add this to saved_regs -- it's just an arg reg. */
866 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
867 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
868 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
870 /* No need to add this to saved_regs -- it's just an arg reg. */
873 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
875 unsigned imm
= insn
& 0xff; /* immediate value */
876 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
877 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
878 fp_offset
= -imm
+ ip_offset
;
879 cache
->framereg
= ARM_FP_REGNUM
;
881 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
883 unsigned imm
= insn
& 0xff; /* immediate value */
884 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
885 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
888 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
891 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
892 cache
->saved_regs
[regno
].addr
= sp_offset
;
894 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
897 unsigned int fp_start_reg
, fp_bound_reg
;
899 if ((insn
& 0x800) == 0x800) /* N0 is set */
901 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
908 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
914 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
915 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
916 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
919 cache
->saved_regs
[fp_start_reg
++].addr
= sp_offset
;
922 else if ((insn
& 0xf0000000) != 0xe0000000)
923 break; /* Condition not true, exit early */
924 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
925 break; /* Don't scan past a block load */
927 /* The optimizer might shove anything into the prologue,
928 so we just skip what we don't recognize. */
932 /* The frame size is just the negative of the offset (from the
933 original SP) of the last thing thing we pushed on the stack.
934 The frame offset is [new FP] - [new SP]. */
935 cache
->framesize
= -sp_offset
;
936 if (cache
->framereg
== ARM_FP_REGNUM
)
937 cache
->frameoffset
= fp_offset
- sp_offset
;
939 cache
->frameoffset
= 0;
942 static struct arm_prologue_cache
*
943 arm_make_prologue_cache (struct frame_info
*next_frame
)
946 struct arm_prologue_cache
*cache
;
947 CORE_ADDR unwound_fp
;
949 cache
= frame_obstack_zalloc (sizeof (struct arm_prologue_cache
));
950 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
952 arm_scan_prologue (next_frame
, cache
);
954 unwound_fp
= frame_unwind_register_unsigned (next_frame
, cache
->framereg
);
958 cache
->prev_sp
= unwound_fp
+ cache
->framesize
- cache
->frameoffset
;
960 /* Calculate actual addresses of saved registers using offsets
961 determined by arm_scan_prologue. */
962 for (reg
= 0; reg
< NUM_REGS
; reg
++)
963 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
964 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
969 /* Our frame ID for a normal frame is the current function's starting PC
970 and the caller's SP when we were called. */
973 arm_prologue_this_id (struct frame_info
*next_frame
,
975 struct frame_id
*this_id
)
977 struct arm_prologue_cache
*cache
;
981 if (*this_cache
== NULL
)
982 *this_cache
= arm_make_prologue_cache (next_frame
);
985 func
= frame_func_unwind (next_frame
);
987 /* This is meant to halt the backtrace at "_start". Make sure we
988 don't halt it at a generic dummy frame. */
989 if (func
<= LOWEST_PC
)
992 /* If we've hit a wall, stop. */
993 if (cache
->prev_sp
== 0)
996 id
= frame_id_build (cache
->prev_sp
, func
);
998 /* Check that we're not going round in circles with the same frame
999 ID (but avoid applying the test to sentinel frames which do go
1000 round in circles). */
1001 if (frame_relative_level (next_frame
) >= 0
1002 && get_frame_type (next_frame
) == NORMAL_FRAME
1003 && frame_id_eq (get_frame_id (next_frame
), id
))
1010 arm_prologue_prev_register (struct frame_info
*next_frame
,
1014 enum lval_type
*lvalp
,
1019 struct arm_prologue_cache
*cache
;
1021 if (*this_cache
== NULL
)
1022 *this_cache
= arm_make_prologue_cache (next_frame
);
1023 cache
= *this_cache
;
1025 /* If we are asked to unwind the PC, then we need to return the LR
1026 instead. The saved value of PC points into this frame's
1027 prologue, not the next frame's resume location. */
1028 if (prev_regnum
== ARM_PC_REGNUM
)
1029 prev_regnum
= ARM_LR_REGNUM
;
1031 /* SP is generally not saved to the stack, but this frame is
1032 identified by NEXT_FRAME's stack pointer at the time of the call.
1033 The value was already reconstructed into PREV_SP. */
1034 if (prev_regnum
== ARM_SP_REGNUM
)
1038 store_unsigned_integer (valuep
, 4, cache
->prev_sp
);
1042 trad_frame_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
1043 optimized
, lvalp
, addrp
, realnump
, valuep
);
1046 struct frame_unwind arm_prologue_unwind
= {
1048 arm_prologue_this_id
,
1049 arm_prologue_prev_register
1052 static const struct frame_unwind
*
1053 arm_prologue_unwind_sniffer (struct frame_info
*next_frame
)
1055 return &arm_prologue_unwind
;
1059 arm_normal_frame_base (struct frame_info
*next_frame
, void **this_cache
)
1061 struct arm_prologue_cache
*cache
;
1063 if (*this_cache
== NULL
)
1064 *this_cache
= arm_make_prologue_cache (next_frame
);
1065 cache
= *this_cache
;
1067 return cache
->prev_sp
+ cache
->frameoffset
- cache
->framesize
;
1070 struct frame_base arm_normal_base
= {
1071 &arm_prologue_unwind
,
1072 arm_normal_frame_base
,
1073 arm_normal_frame_base
,
1074 arm_normal_frame_base
1077 static struct arm_prologue_cache
*
1078 arm_make_sigtramp_cache (struct frame_info
*next_frame
)
1080 struct arm_prologue_cache
*cache
;
1083 cache
= frame_obstack_zalloc (sizeof (struct arm_prologue_cache
));
1085 cache
->prev_sp
= frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
);
1087 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1089 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1090 cache
->saved_regs
[reg
].addr
1091 = SIGCONTEXT_REGISTER_ADDRESS (cache
->prev_sp
,
1092 frame_pc_unwind (next_frame
), reg
);
1094 /* FIXME: What about thumb mode? */
1095 cache
->framereg
= ARM_SP_REGNUM
;
1097 = read_memory_integer (cache
->saved_regs
[cache
->framereg
].addr
,
1098 DEPRECATED_REGISTER_RAW_SIZE (cache
->framereg
));
1104 arm_sigtramp_this_id (struct frame_info
*next_frame
,
1106 struct frame_id
*this_id
)
1108 struct arm_prologue_cache
*cache
;
1110 if (*this_cache
== NULL
)
1111 *this_cache
= arm_make_sigtramp_cache (next_frame
);
1112 cache
= *this_cache
;
1114 /* FIXME drow/2003-07-07: This isn't right if we single-step within
1115 the sigtramp frame; the PC should be the beginning of the trampoline. */
1116 *this_id
= frame_id_build (cache
->prev_sp
, frame_pc_unwind (next_frame
));
1120 arm_sigtramp_prev_register (struct frame_info
*next_frame
,
1124 enum lval_type
*lvalp
,
1129 struct arm_prologue_cache
*cache
;
1131 if (*this_cache
== NULL
)
1132 *this_cache
= arm_make_sigtramp_cache (next_frame
);
1133 cache
= *this_cache
;
1135 trad_frame_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
1136 optimized
, lvalp
, addrp
, realnump
, valuep
);
1139 struct frame_unwind arm_sigtramp_unwind
= {
1141 arm_sigtramp_this_id
,
1142 arm_sigtramp_prev_register
1145 static const struct frame_unwind
*
1146 arm_sigtramp_unwind_sniffer (struct frame_info
*next_frame
)
1148 /* Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare
1149 against the name of the function, the code below will have to be
1150 changed to first fetch the name of the function and then pass
1151 this name to PC_IN_SIGTRAMP. */
1153 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1154 && PC_IN_SIGTRAMP (frame_pc_unwind (next_frame
), (char *) 0))
1155 return &arm_sigtramp_unwind
;
1160 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1161 dummy frame. The frame ID's base needs to match the TOS value
1162 saved by save_dummy_frame_tos() and returned from
1163 arm_push_dummy_call, and the PC needs to match the dummy frame's
1166 static struct frame_id
1167 arm_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1169 return frame_id_build (frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
),
1170 frame_pc_unwind (next_frame
));
1173 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1174 be used to construct the previous frame's ID, after looking up the
1175 containing function). */
1178 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1181 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1182 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1186 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1188 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1191 /* Set the return address for a generic dummy frame. ARM uses the
1195 arm_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
1197 write_register (ARM_LR_REGNUM
, entry_point_address ());
1201 /* Push an empty stack frame, to record the current PC, etc. */
1204 arm_push_dummy_frame (void)
1206 CORE_ADDR old_sp
= read_register (ARM_SP_REGNUM
);
1207 CORE_ADDR sp
= old_sp
;
1208 CORE_ADDR fp
, prologue_start
;
1211 /* Push the two dummy prologue instructions in reverse order,
1212 so that they'll be in the correct low-to-high order in memory. */
1213 /* sub fp, ip, #4 */
1214 sp
= push_word (sp
, 0xe24cb004);
1215 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1216 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
1218 /* Push a pointer to the dummy prologue + 12, because when stm
1219 instruction stores the PC, it stores the address of the stm
1220 instruction itself plus 12. */
1221 fp
= sp
= push_word (sp
, prologue_start
+ 12);
1223 /* Push the processor status. */
1224 sp
= push_word (sp
, read_register (ARM_PS_REGNUM
));
1226 /* Push all 16 registers starting with r15. */
1227 for (regnum
= ARM_PC_REGNUM
; regnum
>= 0; regnum
--)
1228 sp
= push_word (sp
, read_register (regnum
));
1230 /* Update fp (for both Thumb and ARM) and sp. */
1231 write_register (ARM_FP_REGNUM
, fp
);
1232 write_register (THUMB_FP_REGNUM
, fp
);
1233 write_register (ARM_SP_REGNUM
, sp
);
1236 /* DEPRECATED_CALL_DUMMY_WORDS:
1237 This sequence of words is the instructions
1243 Note this is 12 bytes. */
1245 static LONGEST arm_call_dummy_words
[] =
1247 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
1250 /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy
1251 breakpoint to the proper address in the call dummy, so that
1252 `finish' after a stop in a call dummy works.
1254 FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an
1255 optimal solution, but the call to arm_fix_call_dummy is immediately
1256 followed by a call to call_function_by_hand, which is the only
1257 function where call_dummy_breakpoint_offset is actually used. */
1261 arm_set_call_dummy_breakpoint_offset (void)
1263 if (caller_is_thumb
)
1264 set_gdbarch_deprecated_call_dummy_breakpoint_offset (current_gdbarch
, 4);
1266 set_gdbarch_deprecated_call_dummy_breakpoint_offset (current_gdbarch
, 8);
1269 /* Fix up the call dummy, based on whether the processor is currently
1270 in Thumb or ARM mode, and whether the target function is Thumb or
1271 ARM. There are three different situations requiring three
1274 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1275 been copied into the dummy parameter to this function.
1276 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1277 "mov pc,r4" instruction patched to be a "bx r4" instead.
1278 * Thumb calling anything: uses the Thumb dummy defined below, which
1279 works for calling both ARM and Thumb functions.
1281 All three call dummies expect to receive the target function
1282 address in R4, with the low bit set if it's a Thumb function. */
1285 arm_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
1286 struct value
**args
, struct type
*type
, int gcc_p
)
1288 static short thumb_dummy
[4] =
1290 0xf000, 0xf801, /* bl label */
1291 0xdf18, /* swi 24 */
1292 0x4720, /* label: bx r4 */
1294 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
1296 /* Set flag indicating whether the current PC is in a Thumb function. */
1297 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
1298 arm_set_call_dummy_breakpoint_offset ();
1300 /* If the target function is Thumb, set the low bit of the function
1301 address. And if the CPU is currently in ARM mode, patch the
1302 second instruction of call dummy to use a BX instruction to
1303 switch to Thumb mode. */
1304 target_is_thumb
= arm_pc_is_thumb (fun
);
1305 if (target_is_thumb
)
1308 if (!caller_is_thumb
)
1309 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
1312 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1313 instead of the ARM one that's already been copied. This will
1314 work for both Thumb and ARM target functions. */
1315 if (caller_is_thumb
)
1319 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
1321 for (i
= 0; i
< len
; i
++)
1323 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1324 p
+= sizeof (thumb_dummy
[0]);
1328 /* Put the target address in r4; the call dummy will copy this to
1330 write_register (4, fun
);
1333 /* When arguments must be pushed onto the stack, they go on in reverse
1334 order. The code below implements a FILO (stack) to do this. */
1339 struct stack_item
*prev
;
1343 static struct stack_item
*
1344 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1346 struct stack_item
*si
;
1347 si
= xmalloc (sizeof (struct stack_item
));
1348 si
->data
= xmalloc (len
);
1351 memcpy (si
->data
, contents
, len
);
1355 static struct stack_item
*
1356 pop_stack_item (struct stack_item
*si
)
1358 struct stack_item
*dead
= si
;
1365 /* We currently only support passing parameters in integer registers. This
1366 conforms with GCC's default model. Several other variants exist and
1367 we should probably support some of them based on the selected ABI. */
1370 arm_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
1371 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1372 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1373 CORE_ADDR struct_addr
)
1378 struct stack_item
*si
= NULL
;
1380 /* Set the return address. For the ARM, the return breakpoint is
1381 always at BP_ADDR. */
1382 /* XXX Fix for Thumb. */
1383 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1385 /* Walk through the list of args and determine how large a temporary
1386 stack is required. Need to take care here as structs may be
1387 passed on the stack, and we have to to push them. */
1390 argreg
= ARM_A1_REGNUM
;
1393 /* Some platforms require a double-word aligned stack. Make sure sp
1394 is correctly aligned before we start. We always do this even if
1395 it isn't really needed -- it can never hurt things. */
1396 sp
&= ~(CORE_ADDR
)(2 * DEPRECATED_REGISTER_SIZE
- 1);
1398 /* The struct_return pointer occupies the first parameter
1399 passing register. */
1403 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = 0x%s\n",
1404 REGISTER_NAME (argreg
), paddr (struct_addr
));
1405 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1409 for (argnum
= 0; argnum
< nargs
; argnum
++)
1412 struct type
*arg_type
;
1413 struct type
*target_type
;
1414 enum type_code typecode
;
1417 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1418 len
= TYPE_LENGTH (arg_type
);
1419 target_type
= TYPE_TARGET_TYPE (arg_type
);
1420 typecode
= TYPE_CODE (arg_type
);
1421 val
= VALUE_CONTENTS (args
[argnum
]);
1423 /* If the argument is a pointer to a function, and it is a
1424 Thumb function, create a LOCAL copy of the value and set
1425 the THUMB bit in it. */
1426 if (TYPE_CODE_PTR
== typecode
1427 && target_type
!= NULL
1428 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1430 CORE_ADDR regval
= extract_unsigned_integer (val
, len
);
1431 if (arm_pc_is_thumb (regval
))
1434 store_unsigned_integer (val
, len
, MAKE_THUMB_ADDR (regval
));
1438 /* Copy the argument to general registers or the stack in
1439 register-sized pieces. Large arguments are split between
1440 registers and stack. */
1443 int partial_len
= len
< DEPRECATED_REGISTER_SIZE
? len
: DEPRECATED_REGISTER_SIZE
;
1445 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1447 /* The argument is being passed in a general purpose
1449 CORE_ADDR regval
= extract_unsigned_integer (val
, partial_len
);
1451 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1452 argnum
, REGISTER_NAME (argreg
),
1453 phex (regval
, DEPRECATED_REGISTER_SIZE
));
1454 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1459 /* Push the arguments onto the stack. */
1461 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1463 si
= push_stack_item (si
, val
, DEPRECATED_REGISTER_SIZE
);
1464 nstack
+= DEPRECATED_REGISTER_SIZE
;
1471 /* If we have an odd number of words to push, then decrement the stack
1472 by one word now, so first stack argument will be dword aligned. */
1479 write_memory (sp
, si
->data
, si
->len
);
1480 si
= pop_stack_item (si
);
1483 /* Finally, update teh SP register. */
1484 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1490 print_fpu_flags (int flags
)
1492 if (flags
& (1 << 0))
1493 fputs ("IVO ", stdout
);
1494 if (flags
& (1 << 1))
1495 fputs ("DVZ ", stdout
);
1496 if (flags
& (1 << 2))
1497 fputs ("OFL ", stdout
);
1498 if (flags
& (1 << 3))
1499 fputs ("UFL ", stdout
);
1500 if (flags
& (1 << 4))
1501 fputs ("INX ", stdout
);
1505 /* Print interesting information about the floating point processor
1506 (if present) or emulator. */
1508 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1509 struct frame_info
*frame
, const char *args
)
1511 unsigned long status
= read_register (ARM_FPS_REGNUM
);
1514 type
= (status
>> 24) & 127;
1515 printf ("%s FPU type %d\n",
1516 (status
& (1 << 31)) ? "Hardware" : "Software",
1518 fputs ("mask: ", stdout
);
1519 print_fpu_flags (status
>> 16);
1520 fputs ("flags: ", stdout
);
1521 print_fpu_flags (status
);
1524 /* Return the GDB type object for the "standard" data type of data in
1527 static struct type
*
1528 arm_register_type (int regnum
)
1530 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1532 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1533 return builtin_type_arm_ext_big
;
1535 return builtin_type_arm_ext_littlebyte_bigword
;
1538 return builtin_type_int32
;
1541 /* Index within `registers' of the first byte of the space for
1545 arm_register_byte (int regnum
)
1547 if (regnum
< ARM_F0_REGNUM
)
1548 return regnum
* INT_REGISTER_RAW_SIZE
;
1549 else if (regnum
< ARM_PS_REGNUM
)
1550 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1551 + (regnum
- ARM_F0_REGNUM
) * FP_REGISTER_RAW_SIZE
);
1553 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1554 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
1555 + (regnum
- ARM_FPS_REGNUM
) * STATUS_REGISTER_SIZE
);
1558 /* Number of bytes of storage in the actual machine representation for
1559 register N. All registers are 4 bytes, except fp0 - fp7, which are
1560 12 bytes in length. */
1563 arm_register_raw_size (int regnum
)
1565 if (regnum
< ARM_F0_REGNUM
)
1566 return INT_REGISTER_RAW_SIZE
;
1567 else if (regnum
< ARM_FPS_REGNUM
)
1568 return FP_REGISTER_RAW_SIZE
;
1570 return STATUS_REGISTER_SIZE
;
1573 /* Number of bytes of storage in a program's representation
1576 arm_register_virtual_size (int regnum
)
1578 if (regnum
< ARM_F0_REGNUM
)
1579 return INT_REGISTER_VIRTUAL_SIZE
;
1580 else if (regnum
< ARM_FPS_REGNUM
)
1581 return FP_REGISTER_VIRTUAL_SIZE
;
1583 return STATUS_REGISTER_SIZE
;
1586 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1588 arm_register_sim_regno (int regnum
)
1591 gdb_assert (reg
>= 0 && reg
< NUM_REGS
);
1593 if (reg
< NUM_GREGS
)
1594 return SIM_ARM_R0_REGNUM
+ reg
;
1597 if (reg
< NUM_FREGS
)
1598 return SIM_ARM_FP0_REGNUM
+ reg
;
1601 if (reg
< NUM_SREGS
)
1602 return SIM_ARM_FPS_REGNUM
+ reg
;
1605 internal_error (__FILE__
, __LINE__
, "Bad REGNUM %d", regnum
);
1608 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1609 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1610 It is thought that this is is the floating-point register format on
1611 little-endian systems. */
1614 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
1618 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1619 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1621 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1623 floatformat_from_doublest (fmt
, &d
, dbl
);
1627 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
)
1630 floatformat_to_doublest (fmt
, ptr
, &d
);
1631 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1632 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1634 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1639 condition_true (unsigned long cond
, unsigned long status_reg
)
1641 if (cond
== INST_AL
|| cond
== INST_NV
)
1647 return ((status_reg
& FLAG_Z
) != 0);
1649 return ((status_reg
& FLAG_Z
) == 0);
1651 return ((status_reg
& FLAG_C
) != 0);
1653 return ((status_reg
& FLAG_C
) == 0);
1655 return ((status_reg
& FLAG_N
) != 0);
1657 return ((status_reg
& FLAG_N
) == 0);
1659 return ((status_reg
& FLAG_V
) != 0);
1661 return ((status_reg
& FLAG_V
) == 0);
1663 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1665 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1667 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1669 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1671 return (((status_reg
& FLAG_Z
) == 0) &&
1672 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1674 return (((status_reg
& FLAG_Z
) != 0) ||
1675 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1680 /* Support routines for single stepping. Calculate the next PC value. */
1681 #define submask(x) ((1L << ((x) + 1)) - 1)
1682 #define bit(obj,st) (((obj) >> (st)) & 1)
1683 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1684 #define sbits(obj,st,fn) \
1685 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1686 #define BranchDest(addr,instr) \
1687 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1690 static unsigned long
1691 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1692 unsigned long status_reg
)
1694 unsigned long res
, shift
;
1695 int rm
= bits (inst
, 0, 3);
1696 unsigned long shifttype
= bits (inst
, 5, 6);
1700 int rs
= bits (inst
, 8, 11);
1701 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1704 shift
= bits (inst
, 7, 11);
1707 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1708 + (bit (inst
, 4) ? 12 : 8))
1709 : read_register (rm
));
1714 res
= shift
>= 32 ? 0 : res
<< shift
;
1718 res
= shift
>= 32 ? 0 : res
>> shift
;
1724 res
= ((res
& 0x80000000L
)
1725 ? ~((~res
) >> shift
) : res
>> shift
);
1728 case 3: /* ROR/RRX */
1731 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1733 res
= (res
>> shift
) | (res
<< (32 - shift
));
1737 return res
& 0xffffffff;
1740 /* Return number of 1-bits in VAL. */
1743 bitcount (unsigned long val
)
1746 for (nbits
= 0; val
!= 0; nbits
++)
1747 val
&= val
- 1; /* delete rightmost 1-bit in val */
1752 thumb_get_next_pc (CORE_ADDR pc
)
1754 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1755 unsigned short inst1
= read_memory_integer (pc
, 2);
1756 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1757 unsigned long offset
;
1759 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1763 /* Fetch the saved PC from the stack. It's stored above
1764 all of the other registers. */
1765 offset
= bitcount (bits (inst1
, 0, 7)) * DEPRECATED_REGISTER_SIZE
;
1766 sp
= read_register (ARM_SP_REGNUM
);
1767 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1768 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1770 error ("Infinite loop detected");
1772 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1774 unsigned long status
= read_register (ARM_PS_REGNUM
);
1775 unsigned long cond
= bits (inst1
, 8, 11);
1776 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1777 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1779 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1781 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1783 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1785 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1786 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1787 nextpc
= pc_val
+ offset
;
1794 arm_get_next_pc (CORE_ADDR pc
)
1796 unsigned long pc_val
;
1797 unsigned long this_instr
;
1798 unsigned long status
;
1801 if (arm_pc_is_thumb (pc
))
1802 return thumb_get_next_pc (pc
);
1804 pc_val
= (unsigned long) pc
;
1805 this_instr
= read_memory_integer (pc
, 4);
1806 status
= read_register (ARM_PS_REGNUM
);
1807 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1809 if (condition_true (bits (this_instr
, 28, 31), status
))
1811 switch (bits (this_instr
, 24, 27))
1814 case 0x1: /* data processing */
1818 unsigned long operand1
, operand2
, result
= 0;
1822 if (bits (this_instr
, 12, 15) != 15)
1825 if (bits (this_instr
, 22, 25) == 0
1826 && bits (this_instr
, 4, 7) == 9) /* multiply */
1827 error ("Illegal update to pc in instruction");
1829 /* Multiply into PC */
1830 c
= (status
& FLAG_C
) ? 1 : 0;
1831 rn
= bits (this_instr
, 16, 19);
1832 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1834 if (bit (this_instr
, 25))
1836 unsigned long immval
= bits (this_instr
, 0, 7);
1837 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1838 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1841 else /* operand 2 is a shifted register */
1842 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1844 switch (bits (this_instr
, 21, 24))
1847 result
= operand1
& operand2
;
1851 result
= operand1
^ operand2
;
1855 result
= operand1
- operand2
;
1859 result
= operand2
- operand1
;
1863 result
= operand1
+ operand2
;
1867 result
= operand1
+ operand2
+ c
;
1871 result
= operand1
- operand2
+ c
;
1875 result
= operand2
- operand1
+ c
;
1881 case 0xb: /* tst, teq, cmp, cmn */
1882 result
= (unsigned long) nextpc
;
1886 result
= operand1
| operand2
;
1890 /* Always step into a function. */
1895 result
= operand1
& ~operand2
;
1902 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1905 error ("Infinite loop detected");
1910 case 0x5: /* data transfer */
1913 if (bit (this_instr
, 20))
1916 if (bits (this_instr
, 12, 15) == 15)
1922 if (bit (this_instr
, 22))
1923 error ("Illegal update to pc in instruction");
1925 /* byte write to PC */
1926 rn
= bits (this_instr
, 16, 19);
1927 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1928 if (bit (this_instr
, 24))
1931 int c
= (status
& FLAG_C
) ? 1 : 0;
1932 unsigned long offset
=
1933 (bit (this_instr
, 25)
1934 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1935 : bits (this_instr
, 0, 11));
1937 if (bit (this_instr
, 23))
1942 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1945 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1948 error ("Infinite loop detected");
1954 case 0x9: /* block transfer */
1955 if (bit (this_instr
, 20))
1958 if (bit (this_instr
, 15))
1963 if (bit (this_instr
, 23))
1966 unsigned long reglist
= bits (this_instr
, 0, 14);
1967 offset
= bitcount (reglist
) * 4;
1968 if (bit (this_instr
, 24)) /* pre */
1971 else if (bit (this_instr
, 24))
1975 unsigned long rn_val
=
1976 read_register (bits (this_instr
, 16, 19));
1978 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1982 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1984 error ("Infinite loop detected");
1989 case 0xb: /* branch & link */
1990 case 0xa: /* branch */
1992 nextpc
= BranchDest (pc
, this_instr
);
1994 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1996 error ("Infinite loop detected");
2002 case 0xe: /* coproc ops */
2007 fprintf_filtered (gdb_stderr
, "Bad bit-field extraction\n");
2015 /* single_step() is called just before we want to resume the inferior,
2016 if we want to single-step it but there is no hardware or kernel
2017 single-step support. We find the target of the coming instruction
2020 single_step() is also called just after the inferior stops. If we
2021 had set up a simulated single-step, we undo our damage. */
2024 arm_software_single_step (enum target_signal sig
, int insert_bpt
)
2026 static int next_pc
; /* State between setting and unsetting. */
2027 static char break_mem
[BREAKPOINT_MAX
]; /* Temporary storage for mem@bpt */
2031 next_pc
= arm_get_next_pc (read_register (ARM_PC_REGNUM
));
2032 target_insert_breakpoint (next_pc
, break_mem
);
2035 target_remove_breakpoint (next_pc
, break_mem
);
2038 #include "bfd-in2.h"
2039 #include "libcoff.h"
2042 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
2044 if (arm_pc_is_thumb (memaddr
))
2046 static asymbol
*asym
;
2047 static combined_entry_type ce
;
2048 static struct coff_symbol_struct csym
;
2049 static struct bfd fake_bfd
;
2050 static bfd_target fake_target
;
2052 if (csym
.native
== NULL
)
2054 /* Create a fake symbol vector containing a Thumb symbol.
2055 This is solely so that the code in print_insn_little_arm()
2056 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2057 the presence of a Thumb symbol and switch to decoding
2058 Thumb instructions. */
2060 fake_target
.flavour
= bfd_target_coff_flavour
;
2061 fake_bfd
.xvec
= &fake_target
;
2062 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
2064 csym
.symbol
.the_bfd
= &fake_bfd
;
2065 csym
.symbol
.name
= "fake";
2066 asym
= (asymbol
*) & csym
;
2069 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
2070 info
->symbols
= &asym
;
2073 info
->symbols
= NULL
;
2075 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2076 return print_insn_big_arm (memaddr
, info
);
2078 return print_insn_little_arm (memaddr
, info
);
2081 /* The following define instruction sequences that will cause ARM
2082 cpu's to take an undefined instruction trap. These are used to
2083 signal a breakpoint to GDB.
2085 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2086 modes. A different instruction is required for each mode. The ARM
2087 cpu's can also be big or little endian. Thus four different
2088 instructions are needed to support all cases.
2090 Note: ARMv4 defines several new instructions that will take the
2091 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2092 not in fact add the new instructions. The new undefined
2093 instructions in ARMv4 are all instructions that had no defined
2094 behaviour in earlier chips. There is no guarantee that they will
2095 raise an exception, but may be treated as NOP's. In practice, it
2096 may only safe to rely on instructions matching:
2098 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2099 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2100 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2102 Even this may only true if the condition predicate is true. The
2103 following use a condition predicate of ALWAYS so it is always TRUE.
2105 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2106 and NetBSD all use a software interrupt rather than an undefined
2107 instruction to force a trap. This can be handled by by the
2108 abi-specific code during establishment of the gdbarch vector. */
2111 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
2112 override these definitions. */
2113 #ifndef ARM_LE_BREAKPOINT
2114 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2116 #ifndef ARM_BE_BREAKPOINT
2117 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2119 #ifndef THUMB_LE_BREAKPOINT
2120 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
2122 #ifndef THUMB_BE_BREAKPOINT
2123 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
2126 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
2127 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
2128 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2129 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2131 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2132 the program counter value to determine whether a 16-bit or 32-bit
2133 breakpoint should be used. It returns a pointer to a string of
2134 bytes that encode a breakpoint instruction, stores the length of
2135 the string to *lenptr, and adjusts the program counter (if
2136 necessary) to point to the actual memory location where the
2137 breakpoint should be inserted. */
2139 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
2140 breakpoints and storing their handles instread of what was in
2141 memory. It is nice that this is the same size as a handle -
2142 otherwise remote-rdp will have to change. */
2144 static const unsigned char *
2145 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
2147 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2149 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
2151 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2152 *lenptr
= tdep
->thumb_breakpoint_size
;
2153 return tdep
->thumb_breakpoint
;
2157 *lenptr
= tdep
->arm_breakpoint_size
;
2158 return tdep
->arm_breakpoint
;
2162 /* Extract from an array REGBUF containing the (raw) register state a
2163 function return value of type TYPE, and copy that, in virtual
2164 format, into VALBUF. */
2167 arm_extract_return_value (struct type
*type
,
2168 struct regcache
*regs
,
2171 bfd_byte
*valbuf
= dst
;
2173 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2175 switch (arm_get_fp_model (current_gdbarch
))
2179 /* The value is in register F0 in internal format. We need to
2180 extract the raw value and then convert it to the desired
2182 bfd_byte tmpbuf
[FP_REGISTER_RAW_SIZE
];
2184 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
2185 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
2190 case ARM_FLOAT_SOFT_FPA
:
2191 case ARM_FLOAT_SOFT_VFP
:
2192 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
2193 if (TYPE_LENGTH (type
) > 4)
2194 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
2195 valbuf
+ INT_REGISTER_RAW_SIZE
);
2200 (__FILE__
, __LINE__
,
2201 "arm_extract_return_value: Floating point model not supported");
2205 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2206 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2207 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2208 || TYPE_CODE (type
) == TYPE_CODE_PTR
2209 || TYPE_CODE (type
) == TYPE_CODE_REF
2210 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2212 /* If the the type is a plain integer, then the access is
2213 straight-forward. Otherwise we have to play around a bit more. */
2214 int len
= TYPE_LENGTH (type
);
2215 int regno
= ARM_A1_REGNUM
;
2220 /* By using store_unsigned_integer we avoid having to do
2221 anything special for small big-endian values. */
2222 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2223 store_unsigned_integer (valbuf
,
2224 (len
> INT_REGISTER_RAW_SIZE
2225 ? INT_REGISTER_RAW_SIZE
: len
),
2227 len
-= INT_REGISTER_RAW_SIZE
;
2228 valbuf
+= INT_REGISTER_RAW_SIZE
;
2233 /* For a structure or union the behaviour is as if the value had
2234 been stored to word-aligned memory and then loaded into
2235 registers with 32-bit load instruction(s). */
2236 int len
= TYPE_LENGTH (type
);
2237 int regno
= ARM_A1_REGNUM
;
2238 bfd_byte tmpbuf
[INT_REGISTER_RAW_SIZE
];
2242 regcache_cooked_read (regs
, regno
++, tmpbuf
);
2243 memcpy (valbuf
, tmpbuf
,
2244 len
> INT_REGISTER_RAW_SIZE
? INT_REGISTER_RAW_SIZE
: len
);
2245 len
-= INT_REGISTER_RAW_SIZE
;
2246 valbuf
+= INT_REGISTER_RAW_SIZE
;
2251 /* Extract from an array REGBUF containing the (raw) register state
2252 the address in which a function should return its structure value. */
2255 arm_extract_struct_value_address (struct regcache
*regcache
)
2259 regcache_cooked_read_unsigned (regcache
, ARM_A1_REGNUM
, &ret
);
2263 /* Will a function return an aggregate type in memory or in a
2264 register? Return 0 if an aggregate type can be returned in a
2265 register, 1 if it must be returned in memory. */
2268 arm_use_struct_convention (int gcc_p
, struct type
*type
)
2271 enum type_code code
;
2273 /* In the ARM ABI, "integer" like aggregate types are returned in
2274 registers. For an aggregate type to be integer like, its size
2275 must be less than or equal to DEPRECATED_REGISTER_SIZE and the
2276 offset of each addressable subfield must be zero. Note that bit
2277 fields are not addressable, and all addressable subfields of
2278 unions always start at offset zero.
2280 This function is based on the behaviour of GCC 2.95.1.
2281 See: gcc/arm.c: arm_return_in_memory() for details.
2283 Note: All versions of GCC before GCC 2.95.2 do not set up the
2284 parameters correctly for a function returning the following
2285 structure: struct { float f;}; This should be returned in memory,
2286 not a register. Richard Earnshaw sent me a patch, but I do not
2287 know of any way to detect if a function like the above has been
2288 compiled with the correct calling convention. */
2290 /* All aggregate types that won't fit in a register must be returned
2292 if (TYPE_LENGTH (type
) > DEPRECATED_REGISTER_SIZE
)
2297 /* The only aggregate types that can be returned in a register are
2298 structs and unions. Arrays must be returned in memory. */
2299 code
= TYPE_CODE (type
);
2300 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2305 /* Assume all other aggregate types can be returned in a register.
2306 Run a check for structures, unions and arrays. */
2309 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2312 /* Need to check if this struct/union is "integer" like. For
2313 this to be true, its size must be less than or equal to
2314 DEPRECATED_REGISTER_SIZE and the offset of each addressable
2315 subfield must be zero. Note that bit fields are not
2316 addressable, and unions always start at offset zero. If any
2317 of the subfields is a floating point type, the struct/union
2318 cannot be an integer type. */
2320 /* For each field in the object, check:
2321 1) Is it FP? --> yes, nRc = 1;
2322 2) Is it addressable (bitpos != 0) and
2323 not packed (bitsize == 0)?
2327 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2329 enum type_code field_type_code
;
2330 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
2332 /* Is it a floating point type field? */
2333 if (field_type_code
== TYPE_CODE_FLT
)
2339 /* If bitpos != 0, then we have to care about it. */
2340 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2342 /* Bitfields are not addressable. If the field bitsize is
2343 zero, then the field is not packed. Hence it cannot be
2344 a bitfield or any other packed type. */
2345 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2357 /* Write into appropriate registers a function return value of type
2358 TYPE, given in virtual format. */
2361 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
2364 const bfd_byte
*valbuf
= src
;
2366 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2368 char buf
[ARM_MAX_REGISTER_RAW_SIZE
];
2370 switch (arm_get_fp_model (current_gdbarch
))
2374 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
);
2375 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
2378 case ARM_FLOAT_SOFT_FPA
:
2379 case ARM_FLOAT_SOFT_VFP
:
2380 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
2381 if (TYPE_LENGTH (type
) > 4)
2382 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
2383 valbuf
+ INT_REGISTER_RAW_SIZE
);
2388 (__FILE__
, __LINE__
,
2389 "arm_store_return_value: Floating point model not supported");
2393 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2394 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2395 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2396 || TYPE_CODE (type
) == TYPE_CODE_PTR
2397 || TYPE_CODE (type
) == TYPE_CODE_REF
2398 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2400 if (TYPE_LENGTH (type
) <= 4)
2402 /* Values of one word or less are zero/sign-extended and
2404 bfd_byte tmpbuf
[INT_REGISTER_RAW_SIZE
];
2405 LONGEST val
= unpack_long (type
, valbuf
);
2407 store_signed_integer (tmpbuf
, INT_REGISTER_RAW_SIZE
, val
);
2408 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
2412 /* Integral values greater than one word are stored in consecutive
2413 registers starting with r0. This will always be a multiple of
2414 the regiser size. */
2415 int len
= TYPE_LENGTH (type
);
2416 int regno
= ARM_A1_REGNUM
;
2420 regcache_cooked_write (regs
, regno
++, valbuf
);
2421 len
-= INT_REGISTER_RAW_SIZE
;
2422 valbuf
+= INT_REGISTER_RAW_SIZE
;
2428 /* For a structure or union the behaviour is as if the value had
2429 been stored to word-aligned memory and then loaded into
2430 registers with 32-bit load instruction(s). */
2431 int len
= TYPE_LENGTH (type
);
2432 int regno
= ARM_A1_REGNUM
;
2433 bfd_byte tmpbuf
[INT_REGISTER_RAW_SIZE
];
2437 memcpy (tmpbuf
, valbuf
,
2438 len
> INT_REGISTER_RAW_SIZE
? INT_REGISTER_RAW_SIZE
: len
);
2439 regcache_cooked_write (regs
, regno
++, tmpbuf
);
2440 len
-= INT_REGISTER_RAW_SIZE
;
2441 valbuf
+= INT_REGISTER_RAW_SIZE
;
2447 arm_get_longjmp_target (CORE_ADDR
*pc
)
2450 char buf
[INT_REGISTER_RAW_SIZE
];
2451 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2453 jb_addr
= read_register (ARM_A1_REGNUM
);
2455 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2456 INT_REGISTER_RAW_SIZE
))
2459 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_RAW_SIZE
);
2463 /* Return non-zero if the PC is inside a thumb call thunk. */
2466 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2468 CORE_ADDR start_addr
;
2470 /* Find the starting address of the function containing the PC. If
2471 the caller didn't give us a name, look it up at the same time. */
2472 if (0 == find_pc_partial_function (pc
, name
? NULL
: &name
,
2476 return strncmp (name
, "_call_via_r", 11) == 0;
2479 /* If PC is in a Thumb call or return stub, return the address of the
2480 target PC, which is in a register. The thunk functions are called
2481 _called_via_xx, where x is the register name. The possible names
2482 are r0-r9, sl, fp, ip, sp, and lr. */
2485 arm_skip_stub (CORE_ADDR pc
)
2488 CORE_ADDR start_addr
;
2490 /* Find the starting address and name of the function containing the PC. */
2491 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2494 /* Call thunks always start with "_call_via_". */
2495 if (strncmp (name
, "_call_via_", 10) == 0)
2497 /* Use the name suffix to determine which register contains the
2499 static char *table
[15] =
2500 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2501 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2505 for (regno
= 0; regno
<= 14; regno
++)
2506 if (strcmp (&name
[10], table
[regno
]) == 0)
2507 return read_register (regno
);
2510 return 0; /* not a stub */
2514 set_arm_command (char *args
, int from_tty
)
2516 printf_unfiltered ("\"set arm\" must be followed by an apporpriate subcommand.\n");
2517 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
2521 show_arm_command (char *args
, int from_tty
)
2523 cmd_show_list (showarmcmdlist
, from_tty
, "");
2526 enum arm_float_model
2527 arm_get_fp_model (struct gdbarch
*gdbarch
)
2529 if (arm_fp_model
== ARM_FLOAT_AUTO
)
2530 return gdbarch_tdep (gdbarch
)->fp_model
;
2532 return arm_fp_model
;
2536 arm_set_fp (struct gdbarch
*gdbarch
)
2538 enum arm_float_model fp_model
= arm_get_fp_model (gdbarch
);
2540 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
2541 && (fp_model
== ARM_FLOAT_SOFT_FPA
|| fp_model
== ARM_FLOAT_FPA
))
2543 set_gdbarch_double_format (gdbarch
,
2544 &floatformat_ieee_double_littlebyte_bigword
);
2545 set_gdbarch_long_double_format
2546 (gdbarch
, &floatformat_ieee_double_littlebyte_bigword
);
2550 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_little
);
2551 set_gdbarch_long_double_format (gdbarch
,
2552 &floatformat_ieee_double_little
);
2557 set_fp_model_sfunc (char *args
, int from_tty
,
2558 struct cmd_list_element
*c
)
2560 enum arm_float_model fp_model
;
2562 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
2563 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
2565 arm_fp_model
= fp_model
;
2569 if (fp_model
== ARM_FLOAT_LAST
)
2570 internal_error (__FILE__
, __LINE__
, "Invalid fp model accepted: %s.",
2573 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2574 arm_set_fp (current_gdbarch
);
2578 show_fp_model (char *args
, int from_tty
,
2579 struct cmd_list_element
*c
)
2581 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2583 if (arm_fp_model
== ARM_FLOAT_AUTO
2584 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2585 printf_filtered (" - the default for the current ABI is \"%s\".\n",
2586 fp_model_strings
[tdep
->fp_model
]);
2589 /* If the user changes the register disassembly style used for info
2590 register and other commands, we have to also switch the style used
2591 in opcodes for disassembly output. This function is run in the "set
2592 arm disassembly" command, and does that. */
2595 set_disassembly_style_sfunc (char *args
, int from_tty
,
2596 struct cmd_list_element
*c
)
2598 set_disassembly_style ();
2601 /* Return the ARM register name corresponding to register I. */
2603 arm_register_name (int i
)
2605 return arm_register_names
[i
];
2609 set_disassembly_style (void)
2611 const char *setname
, *setdesc
, **regnames
;
2614 /* Find the style that the user wants in the opcodes table. */
2616 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2617 while ((disassembly_style
!= setname
)
2618 && (current
< num_disassembly_options
))
2619 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2620 current_option
= current
;
2622 /* Fill our copy. */
2623 for (j
= 0; j
< numregs
; j
++)
2624 arm_register_names
[j
] = (char *) regnames
[j
];
2627 if (isupper (*regnames
[ARM_PC_REGNUM
]))
2629 arm_register_names
[ARM_FPS_REGNUM
] = "FPS";
2630 arm_register_names
[ARM_PS_REGNUM
] = "CPSR";
2634 arm_register_names
[ARM_FPS_REGNUM
] = "fps";
2635 arm_register_names
[ARM_PS_REGNUM
] = "cpsr";
2638 /* Synchronize the disassembler. */
2639 set_arm_regname_option (current
);
2642 /* arm_othernames implements the "othernames" command. This is deprecated
2643 by the "set arm disassembly" command. */
2646 arm_othernames (char *names
, int n
)
2648 /* Circle through the various flavors. */
2649 current_option
= (current_option
+ 1) % num_disassembly_options
;
2651 disassembly_style
= valid_disassembly_styles
[current_option
];
2652 set_disassembly_style ();
2655 /* Test whether the coff symbol specific value corresponds to a Thumb
2659 coff_sym_is_thumb (int val
)
2661 return (val
== C_THUMBEXT
||
2662 val
== C_THUMBSTAT
||
2663 val
== C_THUMBEXTFUNC
||
2664 val
== C_THUMBSTATFUNC
||
2665 val
== C_THUMBLABEL
);
2668 /* arm_coff_make_msymbol_special()
2669 arm_elf_make_msymbol_special()
2671 These functions test whether the COFF or ELF symbol corresponds to
2672 an address in thumb code, and set a "special" bit in a minimal
2673 symbol to indicate that it does. */
2676 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2678 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2680 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2682 MSYMBOL_SET_SPECIAL (msym
);
2686 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2688 if (coff_sym_is_thumb (val
))
2689 MSYMBOL_SET_SPECIAL (msym
);
2693 arm_write_pc (CORE_ADDR pc
, ptid_t ptid
)
2695 write_register_pid (ARM_PC_REGNUM
, pc
, ptid
);
2697 /* If necessary, set the T bit. */
2700 CORE_ADDR val
= read_register_pid (ARM_PS_REGNUM
, ptid
);
2701 if (arm_pc_is_thumb (pc
))
2702 write_register_pid (ARM_PS_REGNUM
, val
| 0x20, ptid
);
2704 write_register_pid (ARM_PS_REGNUM
, val
& ~(CORE_ADDR
) 0x20, ptid
);
2708 static enum gdb_osabi
2709 arm_elf_osabi_sniffer (bfd
*abfd
)
2711 unsigned int elfosabi
, eflags
;
2712 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2714 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2719 /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the
2720 file are conforming to the base specification for that machine
2721 (there are no OS-specific extensions). In order to determine the
2722 real OS in use we must look for OS notes that have been added. */
2723 bfd_map_over_sections (abfd
,
2724 generic_elf_osabi_sniff_abi_tag_sections
,
2726 if (osabi
== GDB_OSABI_UNKNOWN
)
2728 /* Existing ARM tools don't set this field, so look at the EI_FLAGS
2729 field for more information. */
2730 eflags
= EF_ARM_EABI_VERSION(elf_elfheader(abfd
)->e_flags
);
2733 case EF_ARM_EABI_VER1
:
2734 osabi
= GDB_OSABI_ARM_EABI_V1
;
2737 case EF_ARM_EABI_VER2
:
2738 osabi
= GDB_OSABI_ARM_EABI_V2
;
2741 case EF_ARM_EABI_UNKNOWN
:
2742 /* Assume GNU tools. */
2743 osabi
= GDB_OSABI_ARM_APCS
;
2747 internal_error (__FILE__
, __LINE__
,
2748 "arm_elf_osabi_sniffer: Unknown ARM EABI "
2749 "version 0x%x", eflags
);
2755 /* GNU tools use this value. Check note sections in this case,
2757 bfd_map_over_sections (abfd
,
2758 generic_elf_osabi_sniff_abi_tag_sections
,
2760 if (osabi
== GDB_OSABI_UNKNOWN
)
2762 /* Assume APCS ABI. */
2763 osabi
= GDB_OSABI_ARM_APCS
;
2767 case ELFOSABI_FREEBSD
:
2768 osabi
= GDB_OSABI_FREEBSD_ELF
;
2771 case ELFOSABI_NETBSD
:
2772 osabi
= GDB_OSABI_NETBSD_ELF
;
2775 case ELFOSABI_LINUX
:
2776 osabi
= GDB_OSABI_LINUX
;
2784 /* Initialize the current architecture based on INFO. If possible,
2785 re-use an architecture from ARCHES, which is a list of
2786 architectures already created during this debugging session.
2788 Called e.g. at program startup, when reading a core file, and when
2789 reading a binary file. */
2791 static struct gdbarch
*
2792 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2794 struct gdbarch_tdep
*tdep
;
2795 struct gdbarch
*gdbarch
;
2797 /* Try to deterimine the ABI of the object we are loading. */
2799 if (info
.abfd
!= NULL
&& info
.osabi
== GDB_OSABI_UNKNOWN
)
2801 switch (bfd_get_flavour (info
.abfd
))
2803 case bfd_target_aout_flavour
:
2804 /* Assume it's an old APCS-style ABI. */
2805 info
.osabi
= GDB_OSABI_ARM_APCS
;
2808 case bfd_target_coff_flavour
:
2809 /* Assume it's an old APCS-style ABI. */
2811 info
.osabi
= GDB_OSABI_ARM_APCS
;
2815 /* Leave it as "unknown". */
2820 /* If there is already a candidate, use it. */
2821 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2823 return arches
->gdbarch
;
2825 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
2826 gdbarch
= gdbarch_alloc (&info
, tdep
);
2828 /* We used to default to FPA for generic ARM, but almost nobody uses that
2829 now, and we now provide a way for the user to force the model. So
2830 default to the most useful variant. */
2831 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
2834 switch (info
.byte_order
)
2836 case BFD_ENDIAN_BIG
:
2837 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
2838 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
2839 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
2840 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
2844 case BFD_ENDIAN_LITTLE
:
2845 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
2846 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
2847 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
2848 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
2853 internal_error (__FILE__
, __LINE__
,
2854 "arm_gdbarch_init: bad byte order for float format");
2857 /* On ARM targets char defaults to unsigned. */
2858 set_gdbarch_char_signed (gdbarch
, 0);
2860 /* This should be low enough for everything. */
2861 tdep
->lowest_pc
= 0x20;
2862 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
2864 set_gdbarch_deprecated_call_dummy_words (gdbarch
, arm_call_dummy_words
);
2865 set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch
, 0);
2867 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
2869 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
2871 /* Frame handling. */
2872 set_gdbarch_unwind_dummy_id (gdbarch
, arm_unwind_dummy_id
);
2873 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
2874 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
2876 set_gdbarch_frameless_function_invocation
2877 (gdbarch
, arm_frameless_function_invocation
);
2878 set_gdbarch_frame_args_skip (gdbarch
, 0);
2880 frame_base_set_default (gdbarch
, &arm_normal_base
);
2882 /* Address manipulation. */
2883 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
2884 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
2886 /* Advance PC across function entry code. */
2887 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
2889 /* Get the PC when a frame might not be available. */
2890 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
, arm_saved_pc_after_call
);
2892 /* The stack grows downward. */
2893 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2895 /* Breakpoint manipulation. */
2896 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
2898 /* Information about registers, etc. */
2899 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
2900 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
2901 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
2902 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
2903 set_gdbarch_deprecated_register_byte (gdbarch
, arm_register_byte
);
2904 set_gdbarch_deprecated_register_bytes (gdbarch
,
2905 (NUM_GREGS
* INT_REGISTER_RAW_SIZE
2906 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
2907 + NUM_SREGS
* STATUS_REGISTER_SIZE
));
2908 set_gdbarch_num_regs (gdbarch
, NUM_GREGS
+ NUM_FREGS
+ NUM_SREGS
);
2909 set_gdbarch_deprecated_register_raw_size (gdbarch
, arm_register_raw_size
);
2910 set_gdbarch_deprecated_register_virtual_size (gdbarch
, arm_register_virtual_size
);
2911 set_gdbarch_deprecated_max_register_raw_size (gdbarch
, FP_REGISTER_RAW_SIZE
);
2912 set_gdbarch_deprecated_max_register_virtual_size (gdbarch
, FP_REGISTER_VIRTUAL_SIZE
);
2913 set_gdbarch_deprecated_register_virtual_type (gdbarch
, arm_register_type
);
2915 /* Internal <-> external register number maps. */
2916 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
2918 /* Integer registers are 4 bytes. */
2919 set_gdbarch_deprecated_register_size (gdbarch
, 4);
2920 set_gdbarch_register_name (gdbarch
, arm_register_name
);
2922 /* Returning results. */
2923 set_gdbarch_extract_return_value (gdbarch
, arm_extract_return_value
);
2924 set_gdbarch_store_return_value (gdbarch
, arm_store_return_value
);
2925 set_gdbarch_use_struct_convention (gdbarch
, arm_use_struct_convention
);
2926 set_gdbarch_deprecated_extract_struct_value_address (gdbarch
, arm_extract_struct_value_address
);
2928 /* Single stepping. */
2929 /* XXX For an RDI target we should ask the target if it can single-step. */
2930 set_gdbarch_software_single_step (gdbarch
, arm_software_single_step
);
2933 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
2935 /* Minsymbol frobbing. */
2936 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
2937 set_gdbarch_coff_make_msymbol_special (gdbarch
,
2938 arm_coff_make_msymbol_special
);
2940 /* Hook in the ABI-specific overrides, if they have been registered. */
2941 gdbarch_init_osabi (info
, gdbarch
);
2943 /* Add some default predicates. */
2944 frame_unwind_append_sniffer (gdbarch
, arm_sigtramp_unwind_sniffer
);
2945 frame_unwind_append_sniffer (gdbarch
, arm_prologue_unwind_sniffer
);
2947 /* Now we have tuned the configuration, set a few final things,
2948 based on what the OS ABI has told us. */
2950 if (tdep
->jb_pc
>= 0)
2951 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
2953 /* Floating point sizes and format. */
2954 switch (info
.byte_order
)
2956 case BFD_ENDIAN_BIG
:
2957 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
2958 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_big
);
2959 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
2963 case BFD_ENDIAN_LITTLE
:
2964 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
2965 arm_set_fp (gdbarch
);
2969 internal_error (__FILE__
, __LINE__
,
2970 "arm_gdbarch_init: bad byte order for float format");
2977 arm_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
2979 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2984 fprintf_unfiltered (file
, "arm_dump_tdep: Lowest pc = 0x%lx",
2985 (unsigned long) tdep
->lowest_pc
);
2989 arm_init_abi_eabi_v1 (struct gdbarch_info info
,
2990 struct gdbarch
*gdbarch
)
2996 arm_init_abi_eabi_v2 (struct gdbarch_info info
,
2997 struct gdbarch
*gdbarch
)
3003 arm_init_abi_apcs (struct gdbarch_info info
,
3004 struct gdbarch
*gdbarch
)
3009 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
3012 _initialize_arm_tdep (void)
3014 struct ui_file
*stb
;
3016 struct cmd_list_element
*new_set
, *new_show
;
3017 const char *setname
;
3018 const char *setdesc
;
3019 const char **regnames
;
3021 static char *helptext
;
3023 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
3025 /* Register an ELF OS ABI sniffer for ARM binaries. */
3026 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
3027 bfd_target_elf_flavour
,
3028 arm_elf_osabi_sniffer
);
3030 /* Register some ABI variants for embedded systems. */
3031 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_EABI_V1
,
3032 arm_init_abi_eabi_v1
);
3033 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_EABI_V2
,
3034 arm_init_abi_eabi_v2
);
3035 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_APCS
,
3038 /* Get the number of possible sets of register names defined in opcodes. */
3039 num_disassembly_options
= get_arm_regname_num_options ();
3041 /* Add root prefix command for all "set arm"/"show arm" commands. */
3042 add_prefix_cmd ("arm", no_class
, set_arm_command
,
3043 "Various ARM-specific commands.",
3044 &setarmcmdlist
, "set arm ", 0, &setlist
);
3046 add_prefix_cmd ("arm", no_class
, show_arm_command
,
3047 "Various ARM-specific commands.",
3048 &showarmcmdlist
, "show arm ", 0, &showlist
);
3050 /* Sync the opcode insn printer with our register viewer. */
3051 parse_arm_disassembler_option ("reg-names-std");
3053 /* Begin creating the help text. */
3054 stb
= mem_fileopen ();
3055 fprintf_unfiltered (stb
, "Set the disassembly style.\n"
3056 "The valid values are:\n");
3058 /* Initialize the array that will be passed to add_set_enum_cmd(). */
3059 valid_disassembly_styles
3060 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
3061 for (i
= 0; i
< num_disassembly_options
; i
++)
3063 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
3064 valid_disassembly_styles
[i
] = setname
;
3065 fprintf_unfiltered (stb
, "%s - %s\n", setname
,
3067 /* Copy the default names (if found) and synchronize disassembler. */
3068 if (!strcmp (setname
, "std"))
3070 disassembly_style
= setname
;
3072 for (j
= 0; j
< numregs
; j
++)
3073 arm_register_names
[j
] = (char *) regnames
[j
];
3074 set_arm_regname_option (i
);
3077 /* Mark the end of valid options. */
3078 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
3080 /* Finish the creation of the help text. */
3081 fprintf_unfiltered (stb
, "The default is \"std\".");
3082 helptext
= ui_file_xstrdup (stb
, &length
);
3083 ui_file_delete (stb
);
3085 /* Add the deprecated disassembly-flavor command. */
3086 new_set
= add_set_enum_cmd ("disassembly-flavor", no_class
,
3087 valid_disassembly_styles
,
3091 set_cmd_sfunc (new_set
, set_disassembly_style_sfunc
);
3092 deprecate_cmd (new_set
, "set arm disassembly");
3093 deprecate_cmd (add_show_from_set (new_set
, &showlist
),
3094 "show arm disassembly");
3096 /* And now add the new interface. */
3097 new_set
= add_set_enum_cmd ("disassembler", no_class
,
3098 valid_disassembly_styles
, &disassembly_style
,
3099 helptext
, &setarmcmdlist
);
3101 set_cmd_sfunc (new_set
, set_disassembly_style_sfunc
);
3102 add_show_from_set (new_set
, &showarmcmdlist
);
3104 add_setshow_cmd_full ("apcs32", no_class
,
3105 var_boolean
, (char *) &arm_apcs_32
,
3106 "Set usage of ARM 32-bit mode.",
3107 "Show usage of ARM 32-bit mode.",
3109 &setlist
, &showlist
, &new_set
, &new_show
);
3110 deprecate_cmd (new_set
, "set arm apcs32");
3111 deprecate_cmd (new_show
, "show arm apcs32");
3113 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
3114 "Set usage of ARM 32-bit mode. "
3115 "When off, a 26-bit PC will be used.",
3116 "Show usage of ARM 32-bit mode. "
3117 "When off, a 26-bit PC will be used.",
3119 &setarmcmdlist
, &showarmcmdlist
);
3121 /* Add a command to allow the user to force the FPU model. */
3122 new_set
= add_set_enum_cmd
3123 ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
3124 "Set the floating point type.\n"
3125 "auto - Determine the FP typefrom the OS-ABI.\n"
3126 "softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n"
3127 "fpa - FPA co-processor (GCC compiled).\n"
3128 "softvfp - Software FP with pure-endian doubles.\n"
3129 "vfp - VFP co-processor.",
3131 set_cmd_sfunc (new_set
, set_fp_model_sfunc
);
3132 set_cmd_sfunc (add_show_from_set (new_set
, &showarmcmdlist
), show_fp_model
);
3134 /* Add the deprecated "othernames" command. */
3135 deprecate_cmd (add_com ("othernames", class_obscure
, arm_othernames
,
3136 "Switch to the next set of register names."),
3137 "set arm disassembly");
3139 /* Debugging flag. */
3140 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
3141 "Set ARM debugging. "
3142 "When on, arm-specific debugging is enabled.",
3143 "Show ARM debugging. "
3144 "When on, arm-specific debugging is enabled.",
3146 &setdebuglist
, &showdebuglist
);