1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "coff/internal.h" /* Internal format of COFF symbols in BFD */
31 extern void _initialize_arm_tdep (void);
34 The following macros are actually wrong. Neither arm nor thumb can
35 or should set the lsb on addr.
36 The thumb addresses are mod 2, so (addr & 2) would be a good heuristic
37 to use when checking for thumb (see arm_pc_is_thumb() below).
38 Unfortunately, something else depends on these (incorrect) macros, so
39 fixing them actually breaks gdb. I didn't have time to investigate. Z.R.
41 /* Thumb function addresses are odd (bit 0 is set). Here are some
42 macros to test, set, or clear bit 0 of addresses. */
43 #define IS_THUMB_ADDR(addr) ((addr) & 1)
44 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
45 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
47 /* Default register names as specified by APCS. */
48 static char * atpcs_register_names
[] =
49 {"a1", "a2", "a3", "a4", /* 0 1 2 3 */
50 "v1", "v2", "v3", "v4", /* 4 5 6 7 */
51 "v5", "v6", "v7", "v8", /* 8 9 10 11 */
52 "IP", "SP", "LR", "PC", /* 12 13 14 15 */
53 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
54 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
55 "FPS", "PS" }; /* 24 25 */
57 /* Alternate set of registers names used by GCC. */
58 static char * additional_register_names
[] =
59 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
60 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
61 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
62 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
63 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
64 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
65 "fps", "ps" }; /* 24 25 */
67 /* This is the variable that is set with "set disassembly-flavor".
68 By default use the APCS registers names. */
69 char ** arm_register_names
= atpcs_register_names
;
71 /* Valid register name flavours. */
72 static char apcs_flavor
[] = "apcs";
73 static char r_prefix_flavor
[] = "r-prefix";
74 static char * valid_flavors
[] =
81 /* Disassembly flavor to use. */
82 static char *disassembly_flavor
= apcs_flavor
;
84 /* This is used to keep the bfd arch_info in sync with the disassembly
86 static void set_disassembly_flavor_sfunc(char *, int,
87 struct cmd_list_element
*);
88 static void set_disassembly_flavor (void);
90 static void convert_from_extended (void *ptr
, void *dbl
);
92 /* Define other aspects of the stack frame. We keep the offsets of
93 all saved registers, 'cause we need 'em a lot! We also keep the
94 current size of the stack frame, and the offset of the frame
95 pointer from the stack pointer (for frameless functions, and when
96 we're still in the prologue of a function with a frame) */
98 struct frame_extra_info
100 struct frame_saved_regs fsr
;
106 #define SWAP_TARGET_AND_HOST(buffer,len) \
109 if (TARGET_BYTE_ORDER != HOST_BYTE_ORDER) \
112 char *p = (char *)(buffer); \
113 char *q = ((char *)(buffer)) + len - 1; \
114 for (; p < q; p++, q--) \
124 /* Will a function return an aggregate type in memory or in a
125 register? Return 0 if an aggregate type can be returned in a
126 register, 1 if it must be returned in memory. */
129 arm_use_struct_convention (int gcc_p
, struct type
*type
)
132 register enum type_code code
;
134 /* In the ARM ABI, "integer" like aggregate types are returned in
135 registers. For an aggregate type to be integer like, its size
136 must be less than or equal to REGISTER_SIZE and the offset of
137 each addressable subfield must be zero. Note that bit fields are
138 not addressable, and all addressable subfields of unions always
139 start at offset zero.
141 This function is based on the behaviour of GCC 2.95.1.
142 See: gcc/arm.c: arm_return_in_memory() for details.
144 Note: All versions of GCC before GCC 2.95.2 do not set up the
145 parameters correctly for a function returning the following
146 structure: struct { float f;}; This should be returned in memory,
147 not a register. Richard Earnshaw sent me a patch, but I do not
148 know of any way to detect if a function like the above has been
149 compiled with the correct calling convention. */
151 /* All aggregate types that won't fit in a register must be returned
153 if (TYPE_LENGTH (type
) > REGISTER_SIZE
)
158 /* The only aggregate types that can be returned in a register are
159 structs and unions. Arrays must be returned in memory. */
160 code
= TYPE_CODE (type
);
161 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
166 /* Assume all other aggregate types can be returned in a register.
167 Run a check for structures, unions and arrays. */
170 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
173 /* Need to check if this struct/union is "integer" like. For
174 this to be true, its size must be less than or equal to
175 REGISTER_SIZE and the offset of each addressable subfield
176 must be zero. Note that bit fields are not addressable, and
177 unions always start at offset zero. If any of the subfields
178 is a floating point type, the struct/union cannot be an
181 /* For each field in the object, check:
182 1) Is it FP? --> yes, nRc = 1;
183 2) Is it addressable (bitpos != 0) and
184 not packed (bitsize == 0)?
188 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
190 enum type_code field_type_code
;
191 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
193 /* Is it a floating point type field? */
194 if (field_type_code
== TYPE_CODE_FLT
)
200 /* If bitpos != 0, then we have to care about it. */
201 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
203 /* Bitfields are not addressable. If the field bitsize is
204 zero, then the field is not packed. Hence it cannot be
205 a bitfield or any other packed type. */
206 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
219 arm_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*thisframe
)
221 return (chain
!= 0 && (FRAME_SAVED_PC (thisframe
) >= LOWEST_PC
));
224 /* Set to true if the 32-bit mode is in use. */
228 /* Flag set by arm_fix_call_dummy that tells whether the target
229 function is a Thumb function. This flag is checked by
230 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
231 its use in valops.c) to pass the function address as an additional
234 static int target_is_thumb
;
236 /* Flag set by arm_fix_call_dummy that tells whether the calling
237 function is a Thumb function. This flag is checked by
238 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
240 static int caller_is_thumb
;
242 /* Determine if the program counter specified in MEMADDR is in a Thumb
246 arm_pc_is_thumb (bfd_vma memaddr
)
248 struct minimal_symbol
*sym
;
250 /* If bit 0 of the address is set, assume this is a Thumb address. */
251 if (IS_THUMB_ADDR (memaddr
))
254 /* Thumb functions have a "special" bit set in minimal symbols. */
255 sym
= lookup_minimal_symbol_by_pc (memaddr
);
258 return (MSYMBOL_IS_SPECIAL (sym
));
266 /* Determine if the program counter specified in MEMADDR is in a call
267 dummy being called from a Thumb function. */
270 arm_pc_is_thumb_dummy (bfd_vma memaddr
)
272 CORE_ADDR sp
= read_sp ();
273 CORE_ADDR fp
= read_fp ();
275 if (PC_IN_CALL_DUMMY (memaddr
, sp
, fp
))
276 return caller_is_thumb
;
282 arm_addr_bits_remove (CORE_ADDR val
)
284 if (arm_pc_is_thumb (val
))
285 return (val
& (arm_apcs_32
? 0xfffffffe : 0x03fffffe));
287 return (val
& (arm_apcs_32
? 0xfffffffc : 0x03fffffc));
291 arm_saved_pc_after_call (struct frame_info
*frame
)
293 return ADDR_BITS_REMOVE (read_register (LR_REGNUM
));
297 arm_frameless_function_invocation (struct frame_info
*fi
)
299 CORE_ADDR func_start
, after_prologue
;
302 func_start
= (get_pc_function_start ((fi
)->pc
) + FUNCTION_START_OFFSET
);
303 after_prologue
= SKIP_PROLOGUE (func_start
);
305 /* There are some frameless functions whose first two instructions
306 follow the standard APCS form, in which case after_prologue will
307 be func_start + 8. */
309 frameless
= (after_prologue
< func_start
+ 12);
313 /* A typical Thumb prologue looks like this:
317 Sometimes the latter instruction may be replaced by:
325 or, on tpcs, like this:
332 There is always one instruction of three classes:
337 When we have found at least one of each class we are done with the prolog.
338 Note that the "sub sp, #NN" before the push does not count.
342 thumb_skip_prologue (CORE_ADDR pc
)
344 CORE_ADDR current_pc
;
345 int findmask
= 0; /* findmask:
346 bit 0 - push { rlist }
347 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
348 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
351 for (current_pc
= pc
; current_pc
< pc
+ 40; current_pc
+= 2)
353 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
355 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
357 findmask
|= 1; /* push found */
359 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
361 if ((findmask
& 1) == 0) /* before push ? */
364 findmask
|= 4; /* add/sub sp found */
366 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
368 findmask
|= 2; /* setting of r7 found */
370 else if (insn
== 0x466f) /* mov r7, sp */
372 findmask
|= 2; /* setting of r7 found */
375 continue; /* something in the prolog that we don't care about or some
376 instruction from outside the prolog scheduled here for optimization */
382 /* The APCS (ARM Procedure Call Standard) defines the following
386 [stmfd sp!, {a1,a2,a3,a4}]
387 stmfd sp!, {...,fp,ip,lr,pc}
388 [stfe f7, [sp, #-12]!]
389 [stfe f6, [sp, #-12]!]
390 [stfe f5, [sp, #-12]!]
391 [stfe f4, [sp, #-12]!]
392 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
395 arm_skip_prologue (CORE_ADDR pc
)
399 CORE_ADDR func_addr
, func_end
;
400 struct symtab_and_line sal
;
402 /* See what the symbol table says. */
404 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
406 sal
= find_pc_line (func_addr
, 0);
407 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
411 /* Check if this is Thumb code. */
412 if (arm_pc_is_thumb (pc
))
413 return thumb_skip_prologue (pc
);
415 /* Can't find the prologue end in the symbol table, try it the hard way
416 by disassembling the instructions. */
418 inst
= read_memory_integer (skip_pc
, 4);
419 if (inst
!= 0xe1a0c00d) /* mov ip, sp */
423 inst
= read_memory_integer (skip_pc
, 4);
424 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
427 inst
= read_memory_integer (skip_pc
, 4);
430 if ((inst
& 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */
434 inst
= read_memory_integer (skip_pc
, 4);
436 /* Any insns after this point may float into the code, if it makes
437 for better instruction scheduling, so we skip them only if we
438 find them, but still consdier the function to be frame-ful. */
440 /* We may have either one sfmfd instruction here, or several stfe
441 insns, depending on the version of floating point code we
443 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
446 inst
= read_memory_integer (skip_pc
, 4);
450 while ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
453 inst
= read_memory_integer (skip_pc
, 4);
457 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
463 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
464 This function decodes a Thumb function prologue to determine:
465 1) the size of the stack frame
466 2) which registers are saved on it
467 3) the offsets of saved regs
468 4) the offset from the stack pointer to the frame pointer
469 This information is stored in the "extra" fields of the frame_info.
471 A typical Thumb function prologue would create this stack frame
472 (offsets relative to FP)
473 old SP -> 24 stack parameters
476 R7 -> 0 local variables (16 bytes)
477 SP -> -12 additional stack space (12 bytes)
478 The frame size would thus be 36 bytes, and the frame offset would be
479 12 bytes. The frame register is R7.
481 The comments for thumb_skip_prolog() describe the algorithm we use to detect
482 the end of the prolog */
486 thumb_scan_prologue (struct frame_info
*fi
)
488 CORE_ADDR prologue_start
;
489 CORE_ADDR prologue_end
;
490 CORE_ADDR current_pc
;
491 int saved_reg
[16]; /* which register has been copied to register n? */
492 int findmask
= 0; /* findmask:
493 bit 0 - push { rlist }
494 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
495 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
499 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
501 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
503 if (sal
.line
== 0) /* no line info, use current PC */
504 prologue_end
= fi
->pc
;
505 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
506 prologue_end
= sal
.end
; /* (probably means no prologue) */
509 prologue_end
= prologue_start
+ 40; /* We're in the boondocks: allow for */
510 /* 16 pushes, an add, and "mv fp,sp" */
512 prologue_end
= min (prologue_end
, fi
->pc
);
514 /* Initialize the saved register map. When register H is copied to
515 register L, we will put H in saved_reg[L]. */
516 for (i
= 0; i
< 16; i
++)
519 /* Search the prologue looking for instructions that set up the
520 frame pointer, adjust the stack pointer, and save registers.
521 Do this until all basic prolog instructions are found. */
524 for (current_pc
= prologue_start
;
525 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
532 insn
= read_memory_unsigned_integer (current_pc
, 2);
534 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
537 findmask
|= 1; /* push found */
538 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
539 whether to save LR (R14). */
540 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
542 /* Calculate offsets of saved R0-R7 and LR. */
543 for (regno
= LR_REGNUM
; regno
>= 0; regno
--)
544 if (mask
& (1 << regno
))
547 fi
->fsr
.regs
[saved_reg
[regno
]] = -(fi
->framesize
);
548 saved_reg
[regno
] = regno
; /* reset saved register map */
551 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
553 if ((findmask
& 1) == 0) /* before push ? */
556 findmask
|= 4; /* add/sub sp found */
558 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
559 if (insn
& 0x80) /* is it signed? (==subtracting) */
561 fi
->frameoffset
+= offset
;
564 fi
->framesize
-= offset
;
566 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
568 findmask
|= 2; /* setting of r7 found */
569 fi
->framereg
= THUMB_FP_REGNUM
;
570 fi
->frameoffset
= (insn
& 0xff) << 2; /* get scaled offset */
572 else if (insn
== 0x466f) /* mov r7, sp */
574 findmask
|= 2; /* setting of r7 found */
575 fi
->framereg
= THUMB_FP_REGNUM
;
577 saved_reg
[THUMB_FP_REGNUM
] = SP_REGNUM
;
579 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
581 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
582 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
583 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
586 continue; /* something in the prolog that we don't care about or some
587 instruction from outside the prolog scheduled here for optimization */
591 /* Check if prologue for this frame's PC has already been scanned. If
592 it has, copy the relevant information about that prologue and
593 return non-zero. Otherwise do not copy anything and return zero.
595 The information saved in the cache includes:
596 * the frame register number;
597 * the size of the stack frame;
598 * the offsets of saved regs (relative to the old SP); and
599 * the offset from the stack pointer to the frame pointer
601 The cache contains only one entry, since this is adequate for the
602 typical sequence of prologue scan requests we get. When performing
603 a backtrace, GDB will usually ask to scan the same function twice
604 in a row (once to get the frame chain, and once to fill in the
605 extra frame information). */
607 static struct frame_info prologue_cache
;
610 check_prologue_cache (struct frame_info
*fi
)
614 if (fi
->pc
== prologue_cache
.pc
)
616 fi
->framereg
= prologue_cache
.framereg
;
617 fi
->framesize
= prologue_cache
.framesize
;
618 fi
->frameoffset
= prologue_cache
.frameoffset
;
619 for (i
= 0; i
<= NUM_REGS
; i
++)
620 fi
->fsr
.regs
[i
] = prologue_cache
.fsr
.regs
[i
];
628 /* Copy the prologue information from fi to the prologue cache. */
631 save_prologue_cache (struct frame_info
*fi
)
635 prologue_cache
.pc
= fi
->pc
;
636 prologue_cache
.framereg
= fi
->framereg
;
637 prologue_cache
.framesize
= fi
->framesize
;
638 prologue_cache
.frameoffset
= fi
->frameoffset
;
640 for (i
= 0; i
<= NUM_REGS
; i
++)
641 prologue_cache
.fsr
.regs
[i
] = fi
->fsr
.regs
[i
];
645 /* This function decodes an ARM function prologue to determine:
646 1) the size of the stack frame
647 2) which registers are saved on it
648 3) the offsets of saved regs
649 4) the offset from the stack pointer to the frame pointer
650 This information is stored in the "extra" fields of the frame_info.
652 There are two basic forms for the ARM prologue. The fixed argument
653 function call will look like:
656 stmfd sp!, {fp, ip, lr, pc}
660 Which would create this stack frame (offsets relative to FP):
661 IP -> 4 (caller's stack)
662 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
663 -4 LR (return address in caller)
664 -8 IP (copy of caller's SP)
666 SP -> -28 Local variables
668 The frame size would thus be 32 bytes, and the frame offset would be
669 28 bytes. The stmfd call can also save any of the vN registers it
670 plans to use, which increases the frame size accordingly.
672 Note: The stored PC is 8 off of the STMFD instruction that stored it
673 because the ARM Store instructions always store PC + 8 when you read
676 A variable argument function call will look like:
679 stmfd sp!, {a1, a2, a3, a4}
680 stmfd sp!, {fp, ip, lr, pc}
683 Which would create this stack frame (offsets relative to FP):
684 IP -> 20 (caller's stack)
689 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
690 -4 LR (return address in caller)
691 -8 IP (copy of caller's SP)
693 SP -> -28 Local variables
695 The frame size would thus be 48 bytes, and the frame offset would be
698 There is another potential complication, which is that the optimizer
699 will try to separate the store of fp in the "stmfd" instruction from
700 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
701 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
703 Also, note, the original version of the ARM toolchain claimed that there
706 instruction at the end of the prologue. I have never seen GCC produce
707 this, and the ARM docs don't mention it. We still test for it below in
713 arm_scan_prologue (struct frame_info
*fi
)
715 int regno
, sp_offset
, fp_offset
;
716 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
718 /* Check if this function is already in the cache of frame information. */
719 if (check_prologue_cache (fi
))
722 /* Assume there is no frame until proven otherwise. */
723 fi
->framereg
= SP_REGNUM
;
727 /* Check for Thumb prologue. */
728 if (arm_pc_is_thumb (fi
->pc
))
730 thumb_scan_prologue (fi
);
731 save_prologue_cache (fi
);
735 /* Find the function prologue. If we can't find the function in
736 the symbol table, peek in the stack frame to find the PC. */
737 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
739 /* Assume the prologue is everything between the first instruction
740 in the function and the first source line. */
741 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
743 if (sal
.line
== 0) /* no line info, use current PC */
744 prologue_end
= fi
->pc
;
745 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
746 prologue_end
= sal
.end
; /* (probably means no prologue) */
750 /* Get address of the stmfd in the prologue of the callee; the saved
751 PC is the address of the stmfd + 8. */
752 prologue_start
= ADDR_BITS_REMOVE (read_memory_integer (fi
->frame
, 4))
754 prologue_end
= prologue_start
+ 64; /* This is all the insn's
755 that could be in the prologue,
756 plus room for 5 insn's inserted
760 /* Now search the prologue looking for instructions that set up the
761 frame pointer, adjust the stack pointer, and save registers.
763 Be careful, however, and if it doesn't look like a prologue,
764 don't try to scan it. If, for instance, a frameless function
765 begins with stmfd sp!, then we will tell ourselves there is
766 a frame, which will confuse stack traceback, as well ad"finish"
767 and other operations that rely on a knowledge of the stack
770 In the APCS, the prologue should start with "mov ip, sp" so
771 if we don't see this as the first insn, we will stop. */
773 sp_offset
= fp_offset
= 0;
775 if (read_memory_unsigned_integer (prologue_start
, 4)
776 == 0xe1a0c00d) /* mov ip, sp */
778 for (current_pc
= prologue_start
+ 4; current_pc
< prologue_end
;
781 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
783 if ((insn
& 0xffff0000) == 0xe92d0000)
784 /* stmfd sp!, {..., fp, ip, lr, pc}
786 stmfd sp!, {a1, a2, a3, a4} */
788 int mask
= insn
& 0xffff;
790 /* Calculate offsets of saved registers. */
791 for (regno
= PC_REGNUM
; regno
>= 0; regno
--)
792 if (mask
& (1 << regno
))
795 fi
->fsr
.regs
[regno
] = sp_offset
;
798 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
800 unsigned imm
= insn
& 0xff; /* immediate value */
801 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
802 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
804 fi
->framereg
= FP_REGNUM
;
806 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
808 unsigned imm
= insn
& 0xff; /* immediate value */
809 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
810 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
813 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
816 regno
= F0_REGNUM
+ ((insn
>> 12) & 0x07);
817 fi
->fsr
.regs
[regno
] = sp_offset
;
819 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
822 unsigned int fp_start_reg
, fp_bound_reg
;
824 if ((insn
& 0x800) == 0x800) /* N0 is set */
826 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
833 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
839 fp_start_reg
= F0_REGNUM
+ ((insn
>> 12) & 0x7);
840 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
841 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
844 fi
->fsr
.regs
[fp_start_reg
++] = sp_offset
;
848 /* The optimizer might shove anything into the prologue,
849 so we just skip what we don't recognize. */
854 /* The frame size is just the negative of the offset (from the original SP)
855 of the last thing thing we pushed on the stack. The frame offset is
856 [new FP] - [new SP]. */
857 fi
->framesize
= -sp_offset
;
858 fi
->frameoffset
= fp_offset
- sp_offset
;
860 save_prologue_cache (fi
);
863 /* Find REGNUM on the stack. Otherwise, it's in an active register.
864 One thing we might want to do here is to check REGNUM against the
865 clobber mask, and somehow flag it as invalid if it isn't saved on
866 the stack somewhere. This would provide a graceful failure mode
867 when trying to get the value of caller-saves registers for an inner
871 arm_find_callers_reg (struct frame_info
*fi
, int regnum
)
873 for (; fi
; fi
= fi
->next
)
875 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
876 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
877 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
880 if (fi
->fsr
.regs
[regnum
] != 0)
881 return read_memory_integer (fi
->fsr
.regs
[regnum
],
882 REGISTER_RAW_SIZE (regnum
));
883 return read_register (regnum
);
886 /* Function: frame_chain
887 Given a GDB frame, determine the address of the calling function's frame.
888 This will be used to create a new GDB frame struct, and then
889 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
890 For ARM, we save the frame size when we initialize the frame_info.
892 The original definition of this function was a macro in tm-arm.h:
893 { In the case of the ARM, the frame's nominal address is the FP value,
894 and 12 bytes before comes the saved previous FP value as a 4-byte word. }
896 #define FRAME_CHAIN(thisframe) \
897 ((thisframe)->pc >= LOWEST_PC ? \
898 read_memory_integer ((thisframe)->frame - 12, 4) :\
904 arm_frame_chain (struct frame_info
*fi
)
906 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
907 CORE_ADDR fn_start
, callers_pc
, fp
;
909 /* is this a dummy frame? */
910 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
911 return fi
->frame
; /* dummy frame same as caller's frame */
913 /* is caller-of-this a dummy frame? */
914 callers_pc
= FRAME_SAVED_PC (fi
); /* find out who called us: */
915 fp
= arm_find_callers_reg (fi
, FP_REGNUM
);
916 if (PC_IN_CALL_DUMMY (callers_pc
, fp
, fp
))
917 return fp
; /* dummy frame's frame may bear no relation to ours */
919 if (find_pc_partial_function (fi
->pc
, 0, &fn_start
, 0))
920 if (fn_start
== entry_point_address ())
921 return 0; /* in _start fn, don't chain further */
923 CORE_ADDR caller_pc
, fn_start
;
924 struct frame_info caller_fi
;
925 int framereg
= fi
->framereg
;
927 if (fi
->pc
< LOWEST_PC
)
930 /* If the caller is the startup code, we're at the end of the chain. */
931 caller_pc
= FRAME_SAVED_PC (fi
);
932 if (find_pc_partial_function (caller_pc
, 0, &fn_start
, 0))
933 if (fn_start
== entry_point_address ())
936 /* If the caller is Thumb and the caller is ARM, or vice versa,
937 the frame register of the caller is different from ours.
938 So we must scan the prologue of the caller to determine its
939 frame register number. */
940 if (arm_pc_is_thumb (caller_pc
) != arm_pc_is_thumb (fi
->pc
))
942 memset (&caller_fi
, 0, sizeof (caller_fi
));
943 caller_fi
.pc
= caller_pc
;
944 arm_scan_prologue (&caller_fi
);
945 framereg
= caller_fi
.framereg
;
948 /* If the caller used a frame register, return its value.
949 Otherwise, return the caller's stack pointer. */
950 if (framereg
== FP_REGNUM
|| framereg
== THUMB_FP_REGNUM
)
951 return arm_find_callers_reg (fi
, framereg
);
953 return fi
->frame
+ fi
->framesize
;
956 /* This function actually figures out the frame address for a given pc
957 and sp. This is tricky because we sometimes don't use an explicit
958 frame pointer, and the previous stack pointer isn't necessarily
959 recorded on the stack. The only reliable way to get this info is
960 to examine the prologue. FROMLEAF is a little confusing, it means
961 this is the next frame up the chain AFTER a frameless function. If
962 this is true, then the frame value for this frame is still in the
966 arm_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
971 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
973 memset (fi
->fsr
.regs
, '\000', sizeof fi
->fsr
.regs
);
975 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
976 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
978 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
979 by assuming it's always FP. */
980 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
, SP_REGNUM
);
988 arm_scan_prologue (fi
);
991 /* this is the innermost frame? */
992 fi
->frame
= read_register (fi
->framereg
);
993 else if (fi
->framereg
== FP_REGNUM
|| fi
->framereg
== THUMB_FP_REGNUM
)
995 /* not the innermost frame */
996 /* If we have an FP, the callee saved it. */
997 if (fi
->next
->fsr
.regs
[fi
->framereg
] != 0)
999 read_memory_integer (fi
->next
->fsr
.regs
[fi
->framereg
], 4);
1001 /* If we were called by a frameless fn. then our frame is
1002 still in the frame pointer register on the board... */
1003 fi
->frame
= read_fp ();
1006 /* Calculate actual addresses of saved registers using offsets
1007 determined by arm_scan_prologue. */
1008 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1009 if (fi
->fsr
.regs
[reg
] != 0)
1010 fi
->fsr
.regs
[reg
] += fi
->frame
+ fi
->framesize
- fi
->frameoffset
;
1015 /* Find the caller of this frame. We do this by seeing if LR_REGNUM
1016 is saved in the stack anywhere, otherwise we get it from the
1019 The old definition of this function was a macro:
1020 #define FRAME_SAVED_PC(FRAME) \
1021 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1024 arm_frame_saved_pc (struct frame_info
*fi
)
1026 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1027 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1028 return generic_read_register_dummy (fi
->pc
, fi
->frame
, PC_REGNUM
);
1032 CORE_ADDR pc
= arm_find_callers_reg (fi
, LR_REGNUM
);
1033 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1037 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1038 Examine the Program Status Register to decide which state we're in. */
1041 arm_target_read_fp (void)
1043 if (read_register (PS_REGNUM
) & 0x20) /* Bit 5 is Thumb state bit */
1044 return read_register (THUMB_FP_REGNUM
); /* R7 if Thumb */
1046 return read_register (FP_REGNUM
); /* R11 if ARM */
1049 /* Calculate the frame offsets of the saved registers (ARM version). */
1052 arm_frame_find_saved_regs (struct frame_info
*fi
,
1053 struct frame_saved_regs
*regaddr
)
1055 memcpy (regaddr
, &fi
->fsr
, sizeof (struct frame_saved_regs
));
1059 arm_push_dummy_frame (void)
1061 CORE_ADDR old_sp
= read_register (SP_REGNUM
);
1062 CORE_ADDR sp
= old_sp
;
1063 CORE_ADDR fp
, prologue_start
;
1066 /* Push the two dummy prologue instructions in reverse order,
1067 so that they'll be in the correct low-to-high order in memory. */
1068 /* sub fp, ip, #4 */
1069 sp
= push_word (sp
, 0xe24cb004);
1070 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1071 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
1073 /* Push a pointer to the dummy prologue + 12, because when stm
1074 instruction stores the PC, it stores the address of the stm
1075 instruction itself plus 12. */
1076 fp
= sp
= push_word (sp
, prologue_start
+ 12);
1077 sp
= push_word (sp
, read_register (PC_REGNUM
)); /* FIXME: was PS_REGNUM */
1078 sp
= push_word (sp
, old_sp
);
1079 sp
= push_word (sp
, read_register (FP_REGNUM
));
1081 for (regnum
= 10; regnum
>= 0; regnum
--)
1082 sp
= push_word (sp
, read_register (regnum
));
1084 write_register (FP_REGNUM
, fp
);
1085 write_register (THUMB_FP_REGNUM
, fp
);
1086 write_register (SP_REGNUM
, sp
);
1089 /* Fix up the call dummy, based on whether the processor is currently
1090 in Thumb or ARM mode, and whether the target function is Thumb or
1091 ARM. There are three different situations requiring three
1094 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1095 been copied into the dummy parameter to this function.
1096 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1097 "mov pc,r4" instruction patched to be a "bx r4" instead.
1098 * Thumb calling anything: uses the Thumb dummy defined below, which
1099 works for calling both ARM and Thumb functions.
1101 All three call dummies expect to receive the target function
1102 address in R4, with the low bit set if it's a Thumb function. */
1105 arm_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
1106 value_ptr
*args
, struct type
*type
, int gcc_p
)
1108 static short thumb_dummy
[4] =
1110 0xf000, 0xf801, /* bl label */
1111 0xdf18, /* swi 24 */
1112 0x4720, /* label: bx r4 */
1114 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
1116 /* Set flag indicating whether the current PC is in a Thumb function. */
1117 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
1119 /* If the target function is Thumb, set the low bit of the function
1120 address. And if the CPU is currently in ARM mode, patch the
1121 second instruction of call dummy to use a BX instruction to
1122 switch to Thumb mode. */
1123 target_is_thumb
= arm_pc_is_thumb (fun
);
1124 if (target_is_thumb
)
1127 if (!caller_is_thumb
)
1128 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
1131 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1132 instead of the ARM one that's already been copied. This will
1133 work for both Thumb and ARM target functions. */
1134 if (caller_is_thumb
)
1138 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
1140 for (i
= 0; i
< len
; i
++)
1142 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1143 p
+= sizeof (thumb_dummy
[0]);
1147 /* Put the target address in r4; the call dummy will copy this to
1149 write_register (4, fun
);
1152 /* Return the offset in the call dummy of the instruction that needs
1153 to have a breakpoint placed on it. This is the offset of the 'swi
1154 24' instruction, which is no longer actually used, but simply acts
1155 as a place-holder now.
1157 This implements the CALL_DUMMY_BREAK_OFFSET macro. */
1160 arm_call_dummy_breakpoint_offset (void)
1162 if (caller_is_thumb
)
1170 This function does not support passing parameters using the FPA
1171 variant of the APCS. It passes any floating point arguments in the
1172 general registers and/or on the stack. */
1175 arm_push_arguments (int nargs
, value_ptr
* args
, CORE_ADDR sp
,
1176 int struct_return
, CORE_ADDR struct_addr
)
1179 int argnum
, argreg
, nstack_size
;
1181 /* Walk through the list of args and determine how large a temporary
1182 stack is required. Need to take care here as structs may be
1183 passed on the stack, and we have to to push them. */
1184 nstack_size
= -4 * REGISTER_SIZE
; /* Some arguments go into A1-A4. */
1185 if (struct_return
) /* The struct address goes in A1. */
1186 nstack_size
+= REGISTER_SIZE
;
1188 /* Walk through the arguments and add their size to nstack_size. */
1189 for (argnum
= 0; argnum
< nargs
; argnum
++)
1192 struct type
*arg_type
;
1194 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1195 len
= TYPE_LENGTH (arg_type
);
1197 /* ANSI C code passes float arguments as integers, K&R code
1198 passes float arguments as doubles. Correct for this here. */
1199 if (TYPE_CODE_FLT
== TYPE_CODE (arg_type
) && REGISTER_SIZE
== len
)
1200 nstack_size
+= FP_REGISTER_VIRTUAL_SIZE
;
1205 /* Allocate room on the stack, and initialize our stack frame
1208 if (nstack_size
> 0)
1214 /* Initialize the integer argument register pointer. */
1217 /* The struct_return pointer occupies the first parameter passing
1220 write_register (argreg
++, struct_addr
);
1222 /* Process arguments from left to right. Store as many as allowed
1223 in the parameter passing registers (A1-A4), and save the rest on
1224 the temporary stack. */
1225 for (argnum
= 0; argnum
< nargs
; argnum
++)
1231 enum type_code typecode
;
1232 struct type
*arg_type
, *target_type
;
1234 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1235 target_type
= TYPE_TARGET_TYPE (arg_type
);
1236 len
= TYPE_LENGTH (arg_type
);
1237 typecode
= TYPE_CODE (arg_type
);
1238 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
1240 /* ANSI C code passes float arguments as integers, K&R code
1241 passes float arguments as doubles. The .stabs record for
1242 for ANSI prototype floating point arguments records the
1243 type as FP_INTEGER, while a K&R style (no prototype)
1244 .stabs records the type as FP_FLOAT. In this latter case
1245 the compiler converts the float arguments to double before
1246 calling the function. */
1247 if (TYPE_CODE_FLT
== typecode
&& REGISTER_SIZE
== len
)
1251 char * bufo
= (char *) &d
;
1252 char * bufd
= (char *) &dbl_arg
;
1254 len
= sizeof (double);
1256 SWAP_TARGET_AND_HOST (&f
, sizeof (float)); /* adjust endianess */
1258 /* We must revert the longwords so they get loaded into the
1259 the right registers. */
1260 memcpy (bufd
, bufo
+ len
/ 2, len
/ 2);
1261 SWAP_TARGET_AND_HOST (bufd
, len
/ 2); /* adjust endianess */
1262 memcpy (bufd
+ len
/ 2, bufo
, len
/ 2);
1263 SWAP_TARGET_AND_HOST (bufd
+ len
/ 2, len
/ 2); /* adjust endianess */
1264 val
= (char *) &dbl_arg
;
1267 /* I don't know why this code was disable. The only logical use
1268 for a function pointer is to call that function, so setting
1269 the mode bit is perfectly fine. FN */
1270 /* If the argument is a pointer to a function, and it is a Thumb
1271 function, set the low bit of the pointer. */
1272 if (TYPE_CODE_PTR
== typecode
1273 && NULL
!= target_type
1274 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1276 CORE_ADDR regval
= extract_address (val
, len
);
1277 if (arm_pc_is_thumb (regval
))
1278 store_address (val
, len
, MAKE_THUMB_ADDR (regval
));
1281 /* Copy the argument to general registers or the stack in
1282 register-sized pieces. Large arguments are split between
1283 registers and stack. */
1286 int partial_len
= len
< REGISTER_SIZE
? len
: REGISTER_SIZE
;
1288 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1290 /* It's an argument being passed in a general register. */
1291 regval
= extract_address (val
, partial_len
);
1292 write_register (argreg
++, regval
);
1296 /* Push the arguments onto the stack. */
1297 write_memory ((CORE_ADDR
) fp
, val
, REGISTER_SIZE
);
1298 fp
+= REGISTER_SIZE
;
1306 /* Return adjusted stack pointer. */
1311 arm_pop_frame (void)
1314 struct frame_info
*frame
= get_current_frame ();
1316 if (!PC_IN_CALL_DUMMY(frame
->pc
, frame
->frame
, read_fp()))
1320 old_SP
= read_register (frame
->framereg
);
1321 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1322 if (frame
->fsr
.regs
[regnum
] != 0)
1323 write_register (regnum
,
1324 read_memory_integer (frame
->fsr
.regs
[regnum
], 4));
1326 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
1327 write_register (SP_REGNUM
, old_SP
);
1333 sp
= read_register (FP_REGNUM
);
1334 sp
-= sizeof(CORE_ADDR
); /* we don't care about this first word */
1336 write_register (PC_REGNUM
, read_memory_integer (sp
, 4));
1337 sp
-= sizeof(CORE_ADDR
);
1338 write_register (SP_REGNUM
, read_memory_integer (sp
, 4));
1339 sp
-= sizeof(CORE_ADDR
);
1340 write_register (FP_REGNUM
, read_memory_integer (sp
, 4));
1341 sp
-= sizeof(CORE_ADDR
);
1343 for (regnum
= 10; regnum
>= 0; regnum
--)
1345 write_register (regnum
, read_memory_integer (sp
, 4));
1346 sp
-= sizeof(CORE_ADDR
);
1350 flush_cached_frames ();
1354 print_fpu_flags (int flags
)
1356 if (flags
& (1 << 0))
1357 fputs ("IVO ", stdout
);
1358 if (flags
& (1 << 1))
1359 fputs ("DVZ ", stdout
);
1360 if (flags
& (1 << 2))
1361 fputs ("OFL ", stdout
);
1362 if (flags
& (1 << 3))
1363 fputs ("UFL ", stdout
);
1364 if (flags
& (1 << 4))
1365 fputs ("INX ", stdout
);
1370 arm_float_info (void)
1372 register unsigned long status
= read_register (FPS_REGNUM
);
1375 type
= (status
>> 24) & 127;
1376 printf ("%s FPU type %d\n",
1377 (status
& (1 << 31)) ? "Hardware" : "Software",
1379 fputs ("mask: ", stdout
);
1380 print_fpu_flags (status
>> 16);
1381 fputs ("flags: ", stdout
);
1382 print_fpu_flags (status
);
1385 /* If the disassembly mode is APCS, we have to also switch the
1386 bfd mach_type. This function is run in the set disassembly_flavor
1387 command, and does that. */
1390 set_disassembly_flavor_sfunc (char *args
, int from_tty
,
1391 struct cmd_list_element
*c
)
1393 set_disassembly_flavor ();
1397 set_disassembly_flavor (void)
1399 if (disassembly_flavor
== apcs_flavor
)
1401 parse_arm_disassembler_option ("reg-names-atpcs");
1402 arm_register_names
= atpcs_register_names
;
1404 else if (disassembly_flavor
== r_prefix_flavor
)
1406 parse_arm_disassembler_option ("reg-names-std");
1407 arm_register_names
= additional_register_names
;
1411 /* arm_othernames implements the "othernames" command. This is kind
1412 of hacky, and I prefer the set-show disassembly-flavor which is
1413 also used for the x86 gdb. I will keep this around, however, in
1414 case anyone is actually using it. */
1417 arm_othernames (char *names
, int n
)
1419 if (disassembly_flavor
== r_prefix_flavor
)
1421 disassembly_flavor
= apcs_flavor
;
1422 set_disassembly_flavor ();
1426 disassembly_flavor
= r_prefix_flavor
;
1427 set_disassembly_flavor ();
1432 /* FIXME: The generated assembler works but sucks. Instead of using
1433 r0, r1 it pushes them on the stack, then loads them into r3, r4 and
1434 uses those registers. I must be missing something. ScottB */
1437 convert_from_extended (void *ptr
, void *dbl
)
1443 : "r" (ptr
), "r" (dbl
));
1447 convert_to_extended (void *dbl
, void *ptr
)
1453 : "r" (dbl
), "r" (ptr
));
1457 convert_from_extended (void *ptr
, void *dbl
)
1459 *(double *) dbl
= *(double *) ptr
;
1463 convert_to_extended (void *dbl
, void *ptr
)
1465 *(double *) ptr
= *(double *) dbl
;
1469 /* Nonzero if register N requires conversion from raw format to
1473 arm_register_convertible (unsigned int regnum
)
1475 return ((regnum
- F0_REGNUM
) < 8);
1478 /* Convert data from raw format for register REGNUM in buffer FROM to
1479 virtual format with type TYPE in buffer TO. */
1482 arm_register_convert_to_virtual (unsigned int regnum
, struct type
*type
,
1483 void *from
, void *to
)
1487 convert_from_extended (from
, &val
);
1488 store_floating (to
, TYPE_LENGTH (type
), val
);
1491 /* Convert data from virtual format with type TYPE in buffer FROM to
1492 raw format for register REGNUM in buffer TO. */
1495 arm_register_convert_to_raw (unsigned int regnum
, struct type
*type
,
1496 void *from
, void *to
)
1498 double val
= extract_floating (from
, TYPE_LENGTH (type
));
1500 convert_to_extended (&val
, to
);
1504 condition_true (unsigned long cond
, unsigned long status_reg
)
1506 if (cond
== INST_AL
|| cond
== INST_NV
)
1512 return ((status_reg
& FLAG_Z
) != 0);
1514 return ((status_reg
& FLAG_Z
) == 0);
1516 return ((status_reg
& FLAG_C
) != 0);
1518 return ((status_reg
& FLAG_C
) == 0);
1520 return ((status_reg
& FLAG_N
) != 0);
1522 return ((status_reg
& FLAG_N
) == 0);
1524 return ((status_reg
& FLAG_V
) != 0);
1526 return ((status_reg
& FLAG_V
) == 0);
1528 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1530 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1532 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1534 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1536 return (((status_reg
& FLAG_Z
) == 0) &&
1537 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1539 return (((status_reg
& FLAG_Z
) != 0) ||
1540 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1545 #define submask(x) ((1L << ((x) + 1)) - 1)
1546 #define bit(obj,st) (((obj) >> (st)) & 1)
1547 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1548 #define sbits(obj,st,fn) \
1549 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1550 #define BranchDest(addr,instr) \
1551 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1554 static unsigned long
1555 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1556 unsigned long status_reg
)
1558 unsigned long res
, shift
;
1559 int rm
= bits (inst
, 0, 3);
1560 unsigned long shifttype
= bits (inst
, 5, 6);
1564 int rs
= bits (inst
, 8, 11);
1565 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1568 shift
= bits (inst
, 7, 11);
1571 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1572 + (bit (inst
, 4) ? 12 : 8))
1573 : read_register (rm
));
1578 res
= shift
>= 32 ? 0 : res
<< shift
;
1582 res
= shift
>= 32 ? 0 : res
>> shift
;
1588 res
= ((res
& 0x80000000L
)
1589 ? ~((~res
) >> shift
) : res
>> shift
);
1592 case 3: /* ROR/RRX */
1595 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1597 res
= (res
>> shift
) | (res
<< (32 - shift
));
1601 return res
& 0xffffffff;
1604 /* Return number of 1-bits in VAL. */
1607 bitcount (unsigned long val
)
1610 for (nbits
= 0; val
!= 0; nbits
++)
1611 val
&= val
- 1; /* delete rightmost 1-bit in val */
1616 thumb_get_next_pc (CORE_ADDR pc
)
1618 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1619 unsigned short inst1
= read_memory_integer (pc
, 2);
1620 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1621 unsigned long offset
;
1623 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1627 /* Fetch the saved PC from the stack. It's stored above
1628 all of the other registers. */
1629 offset
= bitcount (bits (inst1
, 0, 7)) * REGISTER_SIZE
;
1630 sp
= read_register (SP_REGNUM
);
1631 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1632 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1634 error ("Infinite loop detected");
1636 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1638 unsigned long status
= read_register (PS_REGNUM
);
1639 unsigned long cond
= bits (inst1
, 8, 11);
1640 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1641 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1643 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1645 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1647 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1649 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1650 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1651 nextpc
= pc_val
+ offset
;
1658 arm_get_next_pc (CORE_ADDR pc
)
1660 unsigned long pc_val
;
1661 unsigned long this_instr
;
1662 unsigned long status
;
1665 if (arm_pc_is_thumb (pc
))
1666 return thumb_get_next_pc (pc
);
1668 pc_val
= (unsigned long) pc
;
1669 this_instr
= read_memory_integer (pc
, 4);
1670 status
= read_register (PS_REGNUM
);
1671 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1673 if (condition_true (bits (this_instr
, 28, 31), status
))
1675 switch (bits (this_instr
, 24, 27))
1678 case 0x1: /* data processing */
1682 unsigned long operand1
, operand2
, result
= 0;
1686 if (bits (this_instr
, 12, 15) != 15)
1689 if (bits (this_instr
, 22, 25) == 0
1690 && bits (this_instr
, 4, 7) == 9) /* multiply */
1691 error ("Illegal update to pc in instruction");
1693 /* Multiply into PC */
1694 c
= (status
& FLAG_C
) ? 1 : 0;
1695 rn
= bits (this_instr
, 16, 19);
1696 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1698 if (bit (this_instr
, 25))
1700 unsigned long immval
= bits (this_instr
, 0, 7);
1701 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1702 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1705 else /* operand 2 is a shifted register */
1706 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1708 switch (bits (this_instr
, 21, 24))
1711 result
= operand1
& operand2
;
1715 result
= operand1
^ operand2
;
1719 result
= operand1
- operand2
;
1723 result
= operand2
- operand1
;
1727 result
= operand1
+ operand2
;
1731 result
= operand1
+ operand2
+ c
;
1735 result
= operand1
- operand2
+ c
;
1739 result
= operand2
- operand1
+ c
;
1745 case 0xb: /* tst, teq, cmp, cmn */
1746 result
= (unsigned long) nextpc
;
1750 result
= operand1
| operand2
;
1754 /* Always step into a function. */
1759 result
= operand1
& ~operand2
;
1766 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1769 error ("Infinite loop detected");
1774 case 0x5: /* data transfer */
1777 if (bit (this_instr
, 20))
1780 if (bits (this_instr
, 12, 15) == 15)
1786 if (bit (this_instr
, 22))
1787 error ("Illegal update to pc in instruction");
1789 /* byte write to PC */
1790 rn
= bits (this_instr
, 16, 19);
1791 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1792 if (bit (this_instr
, 24))
1795 int c
= (status
& FLAG_C
) ? 1 : 0;
1796 unsigned long offset
=
1797 (bit (this_instr
, 25)
1798 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1799 : bits (this_instr
, 0, 11));
1801 if (bit (this_instr
, 23))
1806 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1809 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1812 error ("Infinite loop detected");
1818 case 0x9: /* block transfer */
1819 if (bit (this_instr
, 20))
1822 if (bit (this_instr
, 15))
1827 if (bit (this_instr
, 23))
1830 unsigned long reglist
= bits (this_instr
, 0, 14);
1831 offset
= bitcount (reglist
) * 4;
1832 if (bit (this_instr
, 24)) /* pre */
1835 else if (bit (this_instr
, 24))
1839 unsigned long rn_val
=
1840 read_register (bits (this_instr
, 16, 19));
1842 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1846 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1848 error ("Infinite loop detected");
1853 case 0xb: /* branch & link */
1854 case 0xa: /* branch */
1856 nextpc
= BranchDest (pc
, this_instr
);
1858 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1860 error ("Infinite loop detected");
1866 case 0xe: /* coproc ops */
1871 fprintf (stderr
, "Bad bit-field extraction\n");
1879 #include "bfd-in2.h"
1880 #include "libcoff.h"
1883 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
1885 if (arm_pc_is_thumb (memaddr
))
1887 static asymbol
*asym
;
1888 static combined_entry_type ce
;
1889 static struct coff_symbol_struct csym
;
1890 static struct _bfd fake_bfd
;
1891 static bfd_target fake_target
;
1893 if (csym
.native
== NULL
)
1895 /* Create a fake symbol vector containing a Thumb symbol. This is
1896 solely so that the code in print_insn_little_arm() and
1897 print_insn_big_arm() in opcodes/arm-dis.c will detect the presence
1898 of a Thumb symbol and switch to decoding Thumb instructions. */
1900 fake_target
.flavour
= bfd_target_coff_flavour
;
1901 fake_bfd
.xvec
= &fake_target
;
1902 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
1904 csym
.symbol
.the_bfd
= &fake_bfd
;
1905 csym
.symbol
.name
= "fake";
1906 asym
= (asymbol
*) & csym
;
1909 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
1910 info
->symbols
= &asym
;
1913 info
->symbols
= NULL
;
1915 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1916 return print_insn_big_arm (memaddr
, info
);
1918 return print_insn_little_arm (memaddr
, info
);
1921 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the
1922 program counter value to determine whether a 16-bit or 32-bit
1923 breakpoint should be used. It returns a pointer to a string of
1924 bytes that encode a breakpoint instruction, stores the length of
1925 the string to *lenptr, and adjusts the program counter (if
1926 necessary) to point to the actual memory location where the
1927 breakpoint should be inserted. */
1930 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1932 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
1934 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1936 static char thumb_breakpoint
[] = THUMB_BE_BREAKPOINT
;
1937 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1938 *lenptr
= sizeof (thumb_breakpoint
);
1939 return thumb_breakpoint
;
1943 static char thumb_breakpoint
[] = THUMB_LE_BREAKPOINT
;
1944 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1945 *lenptr
= sizeof (thumb_breakpoint
);
1946 return thumb_breakpoint
;
1951 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1953 static char arm_breakpoint
[] = ARM_BE_BREAKPOINT
;
1954 *lenptr
= sizeof (arm_breakpoint
);
1955 return arm_breakpoint
;
1959 static char arm_breakpoint
[] = ARM_LE_BREAKPOINT
;
1960 *lenptr
= sizeof (arm_breakpoint
);
1961 return arm_breakpoint
;
1966 /* Extract from an array REGBUF containing the (raw) register state a
1967 function return value of type TYPE, and copy that, in virtual
1968 format, into VALBUF. */
1971 arm_extract_return_value (struct type
*type
,
1972 char regbuf
[REGISTER_BYTES
],
1975 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
1976 convert_from_extended (®buf
[REGISTER_BYTE (F0_REGNUM
)], valbuf
);
1978 memcpy (valbuf
, ®buf
[REGISTER_BYTE (A1_REGNUM
)], TYPE_LENGTH (type
));
1981 /* Return non-zero if the PC is inside a thumb call thunk. */
1984 arm_in_call_stub (CORE_ADDR pc
, char *name
)
1986 CORE_ADDR start_addr
;
1988 /* Find the starting address of the function containing the PC. If
1989 the caller didn't give us a name, look it up at the same time. */
1990 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
1993 return strncmp (name
, "_call_via_r", 11) == 0;
1996 /* If PC is in a Thumb call or return stub, return the address of the
1997 target PC, which is in a register. The thunk functions are called
1998 _called_via_xx, where x is the register name. The possible names
1999 are r0-r9, sl, fp, ip, sp, and lr. */
2002 arm_skip_stub (CORE_ADDR pc
)
2005 CORE_ADDR start_addr
;
2007 /* Find the starting address and name of the function containing the PC. */
2008 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2011 /* Call thunks always start with "_call_via_". */
2012 if (strncmp (name
, "_call_via_", 10) == 0)
2014 /* Use the name suffix to determine which register contains the
2016 static char *table
[15] =
2017 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2018 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2022 for (regno
= 0; regno
<= 14; regno
++)
2023 if (strcmp (&name
[10], table
[regno
]) == 0)
2024 return read_register (regno
);
2027 return 0; /* not a stub */
2031 _initialize_arm_tdep (void)
2033 struct cmd_list_element
*new_cmd
;
2035 tm_print_insn
= gdb_print_insn_arm
;
2037 /* Sync the opcode insn printer with our register viewer: */
2038 parse_arm_disassembler_option ("reg-names-atpcs");
2040 /* Add the deprecated "othernames" command */
2042 add_com ("othernames", class_obscure
, arm_othernames
,
2043 "Switch to the other set of register names.");
2045 /* Add the disassembly-flavor command */
2047 new_cmd
= add_set_enum_cmd ("disassembly-flavor", no_class
,
2049 (char *) &disassembly_flavor
,
2050 "Set the disassembly flavor, \
2051 the valid values are \"apcs\" and \"r-prefix\", \
2052 and the default value is \"apcs\".",
2054 new_cmd
->function
.sfunc
= set_disassembly_flavor_sfunc
;
2055 add_show_from_set (new_cmd
, &showlist
);
2057 /* ??? Maybe this should be a boolean. */
2058 add_show_from_set (add_set_cmd ("apcs32", no_class
,
2059 var_zinteger
, (char *) &arm_apcs_32
,
2060 "Set usage of ARM 32-bit mode.\n", &setlist
),
2065 /* Test whether the coff symbol specific value corresponds to a Thumb
2069 coff_sym_is_thumb (int val
)
2071 return (val
== C_THUMBEXT
||
2072 val
== C_THUMBSTAT
||
2073 val
== C_THUMBEXTFUNC
||
2074 val
== C_THUMBSTATFUNC
||
2075 val
== C_THUMBLABEL
);