1 /* Target-dependent code for the Acorn Risc Machine, for GDB, the GNU Debugger.
2 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
28 #include "coff/internal.h" /* Internal format of COFF symbols in BFD */
30 /* Thumb function addresses are odd (bit 0 is set). Here are some
31 macros to test, set, or clear bit 0 of addresses. */
32 #define IS_THUMB_ADDR(addr) ((addr) & 1)
33 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
34 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
36 /* Macros to round N up or down to the next A boundary; A must be
38 #define ROUND_DOWN(n,a) ((n) & ~((a) - 1))
39 #define ROUND_UP(n,a) (((n) + (a) - 1) & ~((a) - 1))
41 /* Set to true if the 32-bit mode is in use. */
45 /* Flag set by arm_fix_call_dummy that tells whether the target function
46 is a Thumb function. This flag is checked by arm_push_arguments.
47 FIXME: Change the PUSH_ARGUMENTS macro (and its use in valops.c) to
48 pass the function address as an additional parameter. */
50 static int target_is_thumb
;
52 /* Flag set by arm_fix_call_dummy that tells whether the calling function
53 is a Thumb function. This flag is checked by arm_pc_is_thumb
54 and arm_call_dummy_breakpoint_offset. */
56 static int caller_is_thumb
;
58 /* Tell if the program counter value in MEMADDR is in a Thumb function. */
61 arm_pc_is_thumb (memaddr
)
64 struct minimal_symbol
* sym
;
67 /* If bit 0 of the address is set, assume this is a Thumb address. */
68 if (IS_THUMB_ADDR (memaddr
))
71 /* Thumb function have a "special" bit set in minimal symbols */
72 sym
= lookup_minimal_symbol_by_pc (memaddr
);
75 return (MSYMBOL_IS_SPECIAL(sym
));
81 /* Tell if the program counter value in MEMADDR is in a call dummy that
82 is being called from a Thumb function. */
85 arm_pc_is_thumb_dummy (memaddr
)
88 CORE_ADDR sp
= read_sp();
90 if (PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+64))
91 return caller_is_thumb
;
97 arm_addr_bits_remove (val
)
100 if (arm_pc_is_thumb (val
))
101 return (val
& (arm_apcs_32
? 0xfffffffe : 0x03fffffe));
103 return (val
& (arm_apcs_32
? 0xfffffffc : 0x03fffffc));
107 arm_saved_pc_after_call (frame
)
108 struct frame_info
*frame
;
110 return ADDR_BITS_REMOVE (read_register (LR_REGNUM
));
113 /* A typical Thumb prologue looks like this:
117 Sometimes the latter instruction may be replaced by:
122 thumb_skip_prologue (pc
)
125 CORE_ADDR current_pc
;
127 for (current_pc
= pc
; current_pc
< pc
+ 20; current_pc
+= 2)
129 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
131 if ( (insn
& 0xfe00) != 0xb400 /* push {..., r7, lr} */
132 && (insn
& 0xff00) != 0xb000 /* add sp, #simm */
133 && (insn
& 0xff00) != 0xaf00 /* add r7, sp, #imm */
134 && insn
!= 0x466f /* mov r7, sp */
135 && (insn
& 0xffc0) != 0x4640) /* mov r0-r7, r8-r15 */
142 /* APCS (ARM procedure call standard) defines the following prologue:
145 [stmfd sp!, {a1,a2,a3,a4}]
146 stmfd sp!, {...,fp,ip,lr,pc}
147 [stfe f7, [sp, #-12]!]
148 [stfe f6, [sp, #-12]!]
149 [stfe f5, [sp, #-12]!]
150 [stfe f4, [sp, #-12]!]
151 sub fp, ip, #nn // nn == 20 or 4 depending on second ins
155 arm_skip_prologue (pc
)
160 CORE_ADDR func_addr
, func_end
;
161 struct symtab_and_line sal
;
163 /* See what the symbol table says. */
164 if (find_pc_partial_function (pc
, NULL
, & func_addr
, & func_end
))
166 sal
= find_pc_line (func_addr
, 0);
167 if (sal
.line
!= 0 && sal
.end
< func_end
)
171 /* Check if this is Thumb code. */
172 if (arm_pc_is_thumb (pc
))
173 return thumb_skip_prologue (pc
);
175 /* Can't find the prologue end in the symbol table, try it the hard way
176 by disassembling the instructions. */
178 inst
= read_memory_integer (skip_pc
, 4);
179 if (inst
!= 0xe1a0c00d) /* mov ip, sp */
183 inst
= read_memory_integer (skip_pc
, 4);
184 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
187 inst
= read_memory_integer (skip_pc
, 4);
190 if ((inst
& 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */
194 inst
= read_memory_integer (skip_pc
, 4);
196 /* Any insns after this point may float into the code, if it makes
197 for better instruction scheduling, so we skip them only if
198 we find them, but still consdier the function to be frame-ful */
200 /* We may have either one sfmfd instruction here, or several stfe insns,
201 depending on the version of floating point code we support. */
202 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
205 inst
= read_memory_integer (skip_pc
, 4);
209 while ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
212 inst
= read_memory_integer (skip_pc
, 4);
216 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
224 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
225 This function decodes a Thumb function prologue to determine:
226 1) the size of the stack frame
227 2) which registers are saved on it
228 3) the offsets of saved regs
229 4) the offset from the stack pointer to the frame pointer
230 This information is stored in the "extra" fields of the frame_info.
232 A typical Thumb function prologue might look like this:
236 Which would create this stack frame (offsets relative to FP)
237 old SP -> 24 stack parameters
240 R7 -> 0 local variables (16 bytes)
241 SP -> -12 additional stack space (12 bytes)
242 The frame size would thus be 36 bytes, and the frame offset would be
243 12 bytes. The frame register is R7. */
246 thumb_scan_prologue (fi
)
247 struct frame_info
* fi
;
249 CORE_ADDR prologue_start
;
250 CORE_ADDR prologue_end
;
251 CORE_ADDR current_pc
;
252 int saved_reg
[16]; /* which register has been copied to register n? */
255 if (find_pc_partial_function (fi
->pc
, NULL
, & prologue_start
, & prologue_end
))
257 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
259 if (sal
.line
== 0) /* no line info, use current PC */
260 prologue_end
= fi
->pc
;
261 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
262 prologue_end
= sal
.end
; /* (probably means no prologue) */
265 prologue_end
= prologue_start
+ 40; /* We're in the boondocks: allow for */
266 /* 16 pushes, an add, and "mv fp,sp" */
268 prologue_end
= min (prologue_end
, fi
->pc
);
270 /* Initialize the saved register map. When register H is copied to
271 register L, we will put H in saved_reg[L]. */
272 for (i
= 0; i
< 16; i
++)
275 /* Search the prologue looking for instructions that set up the
276 frame pointer, adjust the stack pointer, and save registers. */
279 for (current_pc
= prologue_start
; current_pc
< prologue_end
; current_pc
+= 2)
285 insn
= read_memory_unsigned_integer (current_pc
, 2);
287 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
289 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
290 whether to save LR (R14). */
291 int mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
293 /* Calculate offsets of saved R0-R7 and LR. */
294 for (regno
= LR_REGNUM
; regno
>= 0; regno
--)
295 if (mask
& (1 << regno
))
298 fi
->fsr
.regs
[saved_reg
[regno
]] = -(fi
->framesize
);
299 saved_reg
[regno
] = regno
; /* reset saved register map */
302 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm */
304 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
305 if (insn
& 0x80) /* is it signed? */
307 fi
->framesize
-= offset
;
309 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
311 fi
->framereg
= THUMB_FP_REGNUM
;
312 fi
->frameoffset
= (insn
& 0xff) << 2; /* get scaled offset */
314 else if (insn
== 0x466f) /* mov r7, sp */
316 fi
->framereg
= THUMB_FP_REGNUM
;
318 saved_reg
[THUMB_FP_REGNUM
] = SP_REGNUM
;
320 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
322 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
323 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
324 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
327 break; /* anything else isn't prologue */
331 /* Function: check_prologue_cache
332 Check if prologue for this frame's PC has already been scanned.
333 If it has, copy the relevant information about that prologue and
334 return non-zero. Otherwise do not copy anything and return zero.
336 The information saved in the cache includes:
337 * the frame register number;
338 * the size of the stack frame;
339 * the offsets of saved regs (relative to the old SP); and
340 * the offset from the stack pointer to the frame pointer
342 The cache contains only one entry, since this is adequate
343 for the typical sequence of prologue scan requests we get.
344 When performing a backtrace, GDB will usually ask to scan
345 the same function twice in a row (once to get the frame chain,
346 and once to fill in the extra frame information).
349 static struct frame_info prologue_cache
;
352 check_prologue_cache (fi
)
353 struct frame_info
* fi
;
357 if (fi
->pc
== prologue_cache
.pc
)
359 fi
->framereg
= prologue_cache
.framereg
;
360 fi
->framesize
= prologue_cache
.framesize
;
361 fi
->frameoffset
= prologue_cache
.frameoffset
;
362 for (i
= 0; i
<= NUM_REGS
; i
++)
363 fi
->fsr
.regs
[i
] = prologue_cache
.fsr
.regs
[i
];
371 /* Function: save_prologue_cache
372 Copy the prologue information from fi to the prologue cache.
376 save_prologue_cache (fi
)
377 struct frame_info
* fi
;
381 prologue_cache
.pc
= fi
->pc
;
382 prologue_cache
.framereg
= fi
->framereg
;
383 prologue_cache
.framesize
= fi
->framesize
;
384 prologue_cache
.frameoffset
= fi
->frameoffset
;
386 for (i
= 0; i
<= NUM_REGS
; i
++)
387 prologue_cache
.fsr
.regs
[i
] = fi
->fsr
.regs
[i
];
391 /* Function: arm_scan_prologue
392 This function decodes an ARM function prologue to determine:
393 1) the size of the stack frame
394 2) which registers are saved on it
395 3) the offsets of saved regs
396 4) the offset from the stack pointer to the frame pointer
397 This information is stored in the "extra" fields of the frame_info.
399 A typical Arm function prologue might look like this:
401 stmfd sp!, {fp, ip, lr, pc}
404 Which would create this stack frame (offsets relative to FP):
405 IP -> 4 (caller's stack)
406 FP -> 0 PC (points to address of stmfd instruction + 12 in callee)
407 -4 LR (return address in caller)
408 -8 IP (copy of caller's SP)
410 SP -> -28 Local variables
411 The frame size would thus be 32 bytes, and the frame offset would be
415 arm_scan_prologue (fi
)
416 struct frame_info
* fi
;
418 int regno
, sp_offset
, fp_offset
;
419 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
421 /* Check if this function is already in the cache of frame information. */
422 if (check_prologue_cache (fi
))
425 /* Assume there is no frame until proven otherwise. */
426 fi
->framereg
= SP_REGNUM
;
430 /* Check for Thumb prologue. */
431 if (arm_pc_is_thumb (fi
->pc
))
433 thumb_scan_prologue (fi
);
434 save_prologue_cache (fi
);
438 /* Find the function prologue. If we can't find the function in
439 the symbol table, peek in the stack frame to find the PC. */
440 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
442 /* Assume the prologue is everything between the first instruction
443 in the function and the first source line. */
444 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
446 if (sal
.line
== 0) /* no line info, use current PC */
447 prologue_end
= fi
->pc
;
448 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
449 prologue_end
= sal
.end
; /* (probably means no prologue) */
453 /* Get address of the stmfd in the prologue of the callee; the saved
454 PC is the address of the stmfd + 12. */
455 prologue_start
= (read_memory_integer (fi
->frame
, 4) & 0x03fffffc) - 12;
456 prologue_end
= prologue_start
+ 40; /* FIXME: should be big enough */
459 /* Now search the prologue looking for instructions that set up the
460 frame pointer, adjust the stack pointer, and save registers. */
462 sp_offset
= fp_offset
= 0;
463 for (current_pc
= prologue_start
; current_pc
< prologue_end
; current_pc
+= 4)
465 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
467 if ((insn
& 0xffff0000) == 0xe92d0000) /* stmfd sp!, {..., r7, lr} */
469 int mask
= insn
& 0xffff;
471 /* Calculate offsets of saved registers. */
472 for (regno
= PC_REGNUM
; regno
>= 0; regno
--)
473 if (mask
& (1 << regno
))
476 fi
->fsr
.regs
[regno
] = sp_offset
;
479 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
481 unsigned imm
= insn
& 0xff; /* immediate value */
482 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
483 imm
= (imm
>> rot
) | (imm
<< (32-rot
));
485 fi
->framereg
= FP_REGNUM
;
487 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
489 unsigned imm
= insn
& 0xff; /* immediate value */
490 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
491 imm
= (imm
>> rot
) | (imm
<< (32-rot
));
494 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
497 regno
= F0_REGNUM
+ ((insn
>> 12) & 0x07);
498 fi
->fsr
.regs
[regno
] = sp_offset
;
500 else if (insn
== 0xe1a0c00d) /* mov ip, sp */
503 break; /* not a recognized prologue instruction */
506 /* The frame size is just the negative of the offset (from the original SP)
507 of the last thing thing we pushed on the stack. The frame offset is
508 [new FP] - [new SP]. */
509 fi
->framesize
= -sp_offset
;
510 fi
->frameoffset
= fp_offset
- sp_offset
;
512 save_prologue_cache (fi
);
516 /* Function: find_callers_reg
517 Find REGNUM on the stack. Otherwise, it's in an active register. One thing
518 we might want to do here is to check REGNUM against the clobber mask, and
519 somehow flag it as invalid if it isn't saved on the stack somewhere. This
520 would provide a graceful failure mode when trying to get the value of
521 caller-saves registers for an inner frame. */
524 arm_find_callers_reg (fi
, regnum
)
525 struct frame_info
* fi
;
528 for (; fi
; fi
= fi
->next
)
530 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
531 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
532 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
535 if (fi
->fsr
.regs
[regnum
] != 0)
536 return read_memory_integer (fi
->fsr
.regs
[regnum
],
537 REGISTER_RAW_SIZE(regnum
));
538 return read_register (regnum
);
542 /* Function: frame_chain
543 Given a GDB frame, determine the address of the calling function's frame.
544 This will be used to create a new GDB frame struct, and then
545 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
546 For ARM, we save the frame size when we initialize the frame_info.
548 The original definition of this function was a macro in tm-arm.h:
549 { In the case of the ARM, the frame's nominal address is the FP value,
550 and 12 bytes before comes the saved previous FP value as a 4-byte word. }
552 #define FRAME_CHAIN(thisframe) \
553 ((thisframe)->pc >= LOWEST_PC ? \
554 read_memory_integer ((thisframe)->frame - 12, 4) :\
560 struct frame_info
* fi
;
562 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
563 CORE_ADDR fn_start
, callers_pc
, fp
;
565 /* is this a dummy frame? */
566 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
567 return fi
->frame
; /* dummy frame same as caller's frame */
569 /* is caller-of-this a dummy frame? */
570 callers_pc
= FRAME_SAVED_PC(fi
); /* find out who called us: */
571 fp
= arm_find_callers_reg (fi
, FP_REGNUM
);
572 if (PC_IN_CALL_DUMMY (callers_pc
, fp
, fp
))
573 return fp
; /* dummy frame's frame may bear no relation to ours */
575 if (find_pc_partial_function (fi
->pc
, 0, &fn_start
, 0))
576 if (fn_start
== entry_point_address ())
577 return 0; /* in _start fn, don't chain further */
579 CORE_ADDR caller_pc
, fn_start
;
580 struct frame_info caller_fi
;
581 int framereg
= fi
->framereg
;
583 if (fi
->pc
< LOWEST_PC
)
586 /* If the caller is the startup code, we're at the end of the chain. */
587 caller_pc
= FRAME_SAVED_PC (fi
);
588 if (find_pc_partial_function (caller_pc
, 0, &fn_start
, 0))
589 if (fn_start
== entry_point_address ())
592 /* If the caller is Thumb and the caller is ARM, or vice versa,
593 the frame register of the caller is different from ours.
594 So we must scan the prologue of the caller to determine its
595 frame register number. */
596 if (arm_pc_is_thumb (caller_pc
) != arm_pc_is_thumb (fi
->pc
))
598 memset (& caller_fi
, 0, sizeof (caller_fi
));
599 caller_fi
.pc
= caller_pc
;
600 arm_scan_prologue (& caller_fi
);
601 framereg
= caller_fi
.framereg
;
604 /* If the caller used a frame register, return its value.
605 Otherwise, return the caller's stack pointer. */
606 if (framereg
== FP_REGNUM
|| framereg
== THUMB_FP_REGNUM
)
607 return arm_find_callers_reg (fi
, framereg
);
609 return fi
->frame
+ fi
->framesize
;
612 /* Function: init_extra_frame_info
613 This function actually figures out the frame address for a given pc and
614 sp. This is tricky because we sometimes don't use an explicit
615 frame pointer, and the previous stack pointer isn't necessarily recorded
616 on the stack. The only reliable way to get this info is to
617 examine the prologue. */
620 arm_init_extra_frame_info (fi
)
621 struct frame_info
* fi
;
626 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
628 memset (fi
->fsr
.regs
, '\000', sizeof fi
->fsr
.regs
);
630 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
631 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
633 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
634 by assuming it's always FP. */
635 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
, SP_REGNUM
);
643 arm_scan_prologue (fi
);
645 if (!fi
->next
) /* this is the innermost frame? */
646 fi
->frame
= read_register (fi
->framereg
);
647 else /* not the innermost frame */
648 /* If we have an FP, the callee saved it. */
649 if (fi
->framereg
== FP_REGNUM
|| fi
->framereg
== THUMB_FP_REGNUM
)
650 if (fi
->next
->fsr
.regs
[fi
->framereg
] != 0)
651 fi
->frame
= read_memory_integer (fi
->next
->fsr
.regs
[fi
->framereg
],
654 /* Calculate actual addresses of saved registers using offsets determined
655 by arm_scan_prologue. */
656 for (reg
= 0; reg
< NUM_REGS
; reg
++)
657 if (fi
->fsr
.regs
[reg
] != 0)
658 fi
->fsr
.regs
[reg
] += fi
->frame
+ fi
->framesize
- fi
->frameoffset
;
663 /* Function: frame_saved_pc
664 Find the caller of this frame. We do this by seeing if LR_REGNUM is saved
665 in the stack anywhere, otherwise we get it from the registers.
667 The old definition of this function was a macro:
668 #define FRAME_SAVED_PC(FRAME) \
669 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4))
673 arm_frame_saved_pc (fi
)
674 struct frame_info
* fi
;
676 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
677 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
678 return generic_read_register_dummy (fi
->pc
, fi
->frame
, PC_REGNUM
);
682 CORE_ADDR pc
= arm_find_callers_reg (fi
, LR_REGNUM
);
683 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
688 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
689 Examine the Program Status Register to decide which state we're in. */
692 arm_target_read_fp ()
694 if (read_register (PS_REGNUM
) & 0x20) /* Bit 5 is Thumb state bit */
695 return read_register (THUMB_FP_REGNUM
); /* R7 if Thumb */
697 return read_register (FP_REGNUM
); /* R11 if ARM */
701 /* Calculate the frame offsets of the saved registers (ARM version). */
703 arm_frame_find_saved_regs (fi
, regaddr
)
704 struct frame_info
*fi
;
705 struct frame_saved_regs
*regaddr
;
707 memcpy (regaddr
, &fi
->fsr
, sizeof (struct frame_saved_regs
));
712 arm_push_dummy_frame ()
714 CORE_ADDR old_sp
= read_register (SP_REGNUM
);
715 CORE_ADDR sp
= old_sp
;
716 CORE_ADDR fp
, prologue_start
;
719 /* Push the two dummy prologue instructions in reverse order,
720 so that they'll be in the correct low-to-high order in memory. */
722 sp
= push_word (sp
, 0xe24cb004);
723 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
724 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
726 /* push a pointer to the dummy prologue + 12, because when
727 stm instruction stores the PC, it stores the address of the stm
728 instruction itself plus 12. */
729 fp
= sp
= push_word (sp
, prologue_start
+ 12);
730 sp
= push_word (sp
, read_register (PC_REGNUM
)); /* FIXME: was PS_REGNUM */
731 sp
= push_word (sp
, old_sp
);
732 sp
= push_word (sp
, read_register (FP_REGNUM
));
734 for (regnum
= 10; regnum
>= 0; regnum
--)
735 sp
= push_word (sp
, read_register (regnum
));
737 write_register (FP_REGNUM
, fp
);
738 write_register (THUMB_FP_REGNUM
, fp
);
739 write_register (SP_REGNUM
, sp
);
742 /* Fix up the call dummy, based on whether the processor is currently
743 in Thumb or ARM mode, and whether the target function is Thumb
744 or ARM. There are three different situations requiring three
747 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
748 been copied into the dummy parameter to this function.
749 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
750 "mov pc,r4" instruction patched to be a "bx r4" instead.
751 * Thumb calling anything: uses the Thumb dummy defined below, which
752 works for calling both ARM and Thumb functions.
754 All three call dummies expect to receive the target function address
755 in R4, with the low bit set if it's a Thumb function.
759 arm_fix_call_dummy (dummy
, pc
, fun
, nargs
, args
, type
, gcc_p
)
768 static short thumb_dummy
[4] =
770 0xf000, 0xf801, /* bl label */
772 0x4720, /* label: bx r4 */
774 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
776 /* Set flag indicating whether the current PC is in a Thumb function. */
777 caller_is_thumb
= arm_pc_is_thumb (read_pc());
779 /* If the target function is Thumb, set the low bit of the function address.
780 And if the CPU is currently in ARM mode, patch the second instruction
781 of call dummy to use a BX instruction to switch to Thumb mode. */
782 target_is_thumb
= arm_pc_is_thumb (fun
);
786 if (!caller_is_thumb
)
787 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
790 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
791 instead of the ARM one that's already been copied. This will
792 work for both Thumb and ARM target functions. */
797 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
799 for (i
= 0; i
< len
; i
++)
801 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
802 p
+= sizeof (thumb_dummy
[0]);
806 /* Put the target address in r4; the call dummy will copy this to the PC. */
807 write_register (4, fun
);
811 /* Return the offset in the call dummy of the instruction that needs
812 to have a breakpoint placed on it. This is the offset of the 'swi 24'
813 instruction, which is no longer actually used, but simply acts
814 as a place-holder now.
816 This implements the CALL_DUMMY_BREAK_OFFSET macro.
820 arm_call_dummy_breakpoint_offset ()
830 arm_push_arguments(nargs
, args
, sp
, struct_return
, struct_addr
)
835 CORE_ADDR struct_addr
;
842 /* Initialize the integer and float register pointers. */
844 float_argreg
= F0_REGNUM
;
846 /* the struct_return pointer occupies the first parameter-passing reg */
848 write_register (argreg
++, struct_addr
);
850 /* The offset onto the stack at which we will start copying parameters
851 (after the registers are used up) begins at 16 in the old ABI.
852 This leaves room for the "home" area for register parameters. */
853 stack_offset
= REGISTER_SIZE
* 4;
855 /* Now load as many as possible of the first arguments into
856 registers, and push the rest onto the stack. Loop thru args
857 from first to last. */
858 for (argnum
= 0; argnum
< nargs
; argnum
++)
861 value_ptr arg
= args
[argnum
];
862 struct type
* arg_type
= check_typedef (VALUE_TYPE (arg
));
863 struct type
* target_type
= TYPE_TARGET_TYPE (arg_type
);
864 int len
= TYPE_LENGTH (arg_type
);
865 enum type_code typecode
= TYPE_CODE (arg_type
);
868 val
= (char *) VALUE_CONTENTS (arg
);
870 /* If the argument is a pointer to a function, and it's a Thumb
871 function, set the low bit of the pointer. */
872 if (typecode
== TYPE_CODE_PTR
873 && target_type
!= NULL
874 && TYPE_CODE (target_type
) == TYPE_CODE_FUNC
)
876 regval
= extract_address (val
, len
);
877 if (arm_pc_is_thumb (regval
))
878 store_address (val
, len
, MAKE_THUMB_ADDR (regval
));
881 #define MAPCS_FLOAT 0 /* --mapcs-float not implemented by the compiler yet */
883 /* Up to four floating point arguments can be passed in floating
884 point registers on ARM (not on Thumb). */
885 if (typecode
== TYPE_CODE_FLT
886 && float_argreg
<= ARM_LAST_FP_ARG_REGNUM
889 /* This is a floating point value that fits entirely
890 in a single register. */
891 regval
= extract_address (val
, len
);
892 write_register (float_argreg
++, regval
);
897 /* Copy the argument to general registers or the stack in
898 register-sized pieces. Large arguments are split between
899 registers and stack. */
902 int partial_len
= len
< REGISTER_SIZE
? len
: REGISTER_SIZE
;
904 if (argreg
<= ARM_LAST_ARG_REGNUM
)
906 regval
= extract_address (val
, partial_len
);
908 /* It's a simple argument being passed in a general
910 write_register (argreg
, regval
);
915 /* Write this portion of the argument to the stack. */
918 write_memory (sp
, val
, partial_len
);
927 /* Return adjusted stack pointer. */
934 struct frame_info
*frame
= get_current_frame();
937 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
938 if (frame
->fsr
.regs
[regnum
] != 0)
939 write_register (regnum
,
940 read_memory_integer (frame
->fsr
.regs
[regnum
], 4));
942 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
943 write_register (SP_REGNUM
, read_register (frame
->framereg
));
945 flush_cached_frames ();
949 print_fpu_flags (flags
)
952 if (flags
& (1 << 0)) fputs ("IVO ", stdout
);
953 if (flags
& (1 << 1)) fputs ("DVZ ", stdout
);
954 if (flags
& (1 << 2)) fputs ("OFL ", stdout
);
955 if (flags
& (1 << 3)) fputs ("UFL ", stdout
);
956 if (flags
& (1 << 4)) fputs ("INX ", stdout
);
963 register unsigned long status
= read_register (FPS_REGNUM
);
966 type
= (status
>> 24) & 127;
967 printf ("%s FPU type %d\n",
968 (status
& (1<<31)) ? "Hardware" : "Software",
970 fputs ("mask: ", stdout
);
971 print_fpu_flags (status
>> 16);
972 fputs ("flags: ", stdout
);
973 print_fpu_flags (status
);
980 static char *original
[] = ORIGINAL_REGISTER_NAMES
;
981 static char *extra_crispy
[] = ADDITIONAL_REGISTER_NAMES
;
983 memcpy (reg_names
, toggle
? extra_crispy
: original
, sizeof(original
));
987 /* FIXME: Fill in with the 'right thing', see asm
988 template in arm-convert.s */
991 convert_from_extended (ptr
, dbl
)
995 *dbl
= *(double*)ptr
;
999 convert_to_extended (dbl
, ptr
)
1003 *(double*)ptr
= *dbl
;
1007 condition_true (cond
, status_reg
)
1009 unsigned long status_reg
;
1011 if (cond
== INST_AL
|| cond
== INST_NV
)
1017 return ((status_reg
& FLAG_Z
) != 0);
1019 return ((status_reg
& FLAG_Z
) == 0);
1021 return ((status_reg
& FLAG_C
) != 0);
1023 return ((status_reg
& FLAG_C
) == 0);
1025 return ((status_reg
& FLAG_N
) != 0);
1027 return ((status_reg
& FLAG_N
) == 0);
1029 return ((status_reg
& FLAG_V
) != 0);
1031 return ((status_reg
& FLAG_V
) == 0);
1033 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1035 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1037 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1039 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1041 return (((status_reg
& FLAG_Z
) == 0) &&
1042 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1044 return (((status_reg
& FLAG_Z
) != 0) ||
1045 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1050 #define submask(x) ((1L << ((x) + 1)) - 1)
1051 #define bit(obj,st) (((obj) >> (st)) & 1)
1052 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1053 #define sbits(obj,st,fn) \
1054 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1055 #define BranchDest(addr,instr) \
1056 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1059 static unsigned long
1060 shifted_reg_val (inst
, carry
, pc_val
, status_reg
)
1063 unsigned long pc_val
;
1064 unsigned long status_reg
;
1066 unsigned long res
, shift
;
1067 int rm
= bits (inst
, 0, 3);
1068 unsigned long shifttype
= bits (inst
, 5, 6);
1072 int rs
= bits (inst
, 8, 11);
1073 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1076 shift
= bits (inst
, 7, 11);
1079 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1080 + (bit (inst
, 4) ? 12 : 8))
1081 : read_register (rm
));
1086 res
= shift
>= 32 ? 0 : res
<< shift
;
1090 res
= shift
>= 32 ? 0 : res
>> shift
;
1094 if (shift
>= 32) shift
= 31;
1095 res
= ((res
& 0x80000000L
)
1096 ? ~((~res
) >> shift
) : res
>> shift
);
1099 case 3: /* ROR/RRX */
1102 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1104 res
= (res
>> shift
) | (res
<< (32-shift
));
1108 return res
& 0xffffffff;
1112 /* Return number of 1-bits in VAL. */
1119 for (nbits
= 0; val
!= 0; nbits
++)
1120 val
&= val
- 1; /* delete rightmost 1-bit in val */
1126 thumb_get_next_pc (pc
)
1129 unsigned long pc_val
= ((unsigned long)pc
) + 4; /* PC after prefetch */
1130 unsigned short inst1
= read_memory_integer (pc
, 2);
1131 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1132 unsigned long offset
;
1134 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1138 /* Fetch the saved PC from the stack. It's stored above
1139 all of the other registers. */
1140 offset
= bitcount (bits (inst1
, 0, 7)) * REGISTER_SIZE
;
1141 sp
= read_register (SP_REGNUM
);
1142 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1143 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1145 error ("Infinite loop detected");
1147 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1149 unsigned long status
= read_register (PS_REGNUM
);
1150 unsigned long cond
= bits (inst1
, 8, 11);
1151 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1152 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1154 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1156 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1158 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1160 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1161 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1162 nextpc
= pc_val
+ offset
;
1170 arm_get_next_pc (pc
)
1173 unsigned long pc_val
;
1174 unsigned long this_instr
;
1175 unsigned long status
;
1178 if (arm_pc_is_thumb (pc
))
1179 return thumb_get_next_pc (pc
);
1181 pc_val
= (unsigned long) pc
;
1182 this_instr
= read_memory_integer (pc
, 4);
1183 status
= read_register (PS_REGNUM
);
1184 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1186 if (condition_true (bits (this_instr
, 28, 31), status
))
1188 switch (bits (this_instr
, 24, 27))
1190 case 0x0: case 0x1: /* data processing */
1193 unsigned long operand1
, operand2
, result
= 0;
1197 if (bits (this_instr
, 12, 15) != 15)
1200 if (bits (this_instr
, 22, 25) == 0
1201 && bits (this_instr
, 4, 7) == 9) /* multiply */
1202 error ("Illegal update to pc in instruction");
1204 /* Multiply into PC */
1205 c
= (status
& FLAG_C
) ? 1 : 0;
1206 rn
= bits (this_instr
, 16, 19);
1207 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1209 if (bit (this_instr
, 25))
1211 unsigned long immval
= bits (this_instr
, 0, 7);
1212 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1213 operand2
= ((immval
>> rotate
) | (immval
<< (32-rotate
)))
1216 else /* operand 2 is a shifted register */
1217 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1219 switch (bits (this_instr
, 21, 24))
1222 result
= operand1
& operand2
;
1226 result
= operand1
^ operand2
;
1230 result
= operand1
- operand2
;
1234 result
= operand2
- operand1
;
1238 result
= operand1
+ operand2
;
1242 result
= operand1
+ operand2
+ c
;
1246 result
= operand1
- operand2
+ c
;
1250 result
= operand2
- operand1
+ c
;
1253 case 0x8: case 0x9: case 0xa: case 0xb: /* tst, teq, cmp, cmn */
1254 result
= (unsigned long) nextpc
;
1258 result
= operand1
| operand2
;
1262 /* Always step into a function. */
1267 result
= operand1
& ~operand2
;
1274 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1277 error ("Infinite loop detected");
1281 case 0x4: case 0x5: /* data transfer */
1283 if (bit (this_instr
, 20))
1286 if (bits (this_instr
, 12, 15) == 15)
1292 if (bit (this_instr
, 22))
1293 error ("Illegal update to pc in instruction");
1295 /* byte write to PC */
1296 rn
= bits (this_instr
, 16, 19);
1297 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1298 if (bit (this_instr
, 24))
1301 int c
= (status
& FLAG_C
) ? 1 : 0;
1302 unsigned long offset
=
1303 (bit (this_instr
, 25)
1304 ? shifted_reg_val (this_instr
, c
, pc_val
)
1305 : bits (this_instr
, 0, 11));
1307 if (bit (this_instr
, 23))
1312 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1315 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1318 error ("Infinite loop detected");
1323 case 0x8: case 0x9: /* block transfer */
1324 if (bit (this_instr
, 20))
1327 if (bit (this_instr
, 15))
1332 if (bit (this_instr
, 23))
1335 unsigned long reglist
= bits (this_instr
, 0, 14);
1336 offset
= bitcount (reglist
) * 4;
1337 if (bit (this_instr
, 24)) /* pre */
1340 else if (bit (this_instr
, 24))
1344 unsigned long rn_val
=
1345 read_register (bits (this_instr
, 16, 19));
1347 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1351 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1353 error ("Infinite loop detected");
1358 case 0xb: /* branch & link */
1359 case 0xa: /* branch */
1361 nextpc
= BranchDest (pc
, this_instr
);
1363 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1365 error ("Infinite loop detected");
1370 case 0xe: /* coproc ops */
1375 fprintf (stderr
, "Bad bit-field extraction\n");
1383 #include "bfd-in2.h"
1384 #include "libcoff.h"
1387 gdb_print_insn_arm (memaddr
, info
)
1389 disassemble_info
* info
;
1391 if (arm_pc_is_thumb (memaddr
))
1393 static asymbol
* asym
;
1394 static combined_entry_type ce
;
1395 static struct coff_symbol_struct csym
;
1396 static struct _bfd fake_bfd
;
1397 static bfd_target fake_target
;
1399 if (csym
.native
== NULL
)
1401 /* Create a fake symbol vector containing a Thumb symbol. This is
1402 solely so that the code in print_insn_little_arm() and
1403 print_insn_big_arm() in opcodes/arm-dis.c will detect the presence
1404 of a Thumb symbol and switch to decoding Thumb instructions. */
1406 fake_target
.flavour
= bfd_target_coff_flavour
;
1407 fake_bfd
.xvec
= & fake_target
;
1408 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
1410 csym
.symbol
.the_bfd
= & fake_bfd
;
1411 csym
.symbol
.name
= "fake";
1412 asym
= (asymbol
*) & csym
;
1415 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
1416 info
->symbols
= & asym
;
1419 info
->symbols
= NULL
;
1421 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1422 return print_insn_big_arm (memaddr
, info
);
1424 return print_insn_little_arm (memaddr
, info
);
1427 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
1428 counter value to determine whether a 16- or 32-bit breakpoint should be
1429 used. It returns a pointer to a string of bytes that encode a breakpoint
1430 instruction, stores the length of the string to *lenptr, and adjusts pc
1431 (if necessary) to point to the actual memory location where the
1432 breakpoint should be inserted. */
1435 arm_breakpoint_from_pc (pcptr
, lenptr
)
1439 CORE_ADDR sp
= read_sp();
1441 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
1443 static char thumb_breakpoint
[] = THUMB_BREAKPOINT
;
1445 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1446 *lenptr
= sizeof (thumb_breakpoint
);
1448 return thumb_breakpoint
;
1452 static char arm_breakpoint
[] = ARM_BREAKPOINT
;
1454 *lenptr
= sizeof (arm_breakpoint
);
1456 return arm_breakpoint
;
1460 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
1461 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
1464 arm_in_call_stub (pc
, name
)
1468 CORE_ADDR start_addr
;
1470 /* Find the starting address of the function containing the PC. If the
1471 caller didn't give us a name, look it up at the same time. */
1472 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
1475 return strncmp (name
, "_call_via_r", 11) == 0;
1479 /* If PC is in a Thumb call or return stub, return the address of the target
1480 PC, which is in a register. The thunk functions are called _called_via_xx,
1481 where x is the register name. The possible names are r0-r9, sl, fp, ip,
1489 CORE_ADDR start_addr
;
1491 /* Find the starting address and name of the function containing the PC. */
1492 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1495 /* Call thunks always start with "_call_via_". */
1496 if (strncmp (name
, "_call_via_", 10) == 0)
1498 /* Use the name suffix to determine which register contains
1500 static char *table
[15] =
1501 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1502 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
1506 for (regno
= 0; regno
<= 14; regno
++)
1507 if (strcmp (&name
[10], table
[regno
]) == 0)
1508 return read_register (regno
);
1510 return 0; /* not a stub */
1515 _initialize_arm_tdep ()
1517 tm_print_insn
= gdb_print_insn_arm
;
1519 add_com ("othernames", class_obscure
, arm_othernames
,
1520 "Switch to the other set of register names.");
1522 /* ??? Maybe this should be a boolean. */
1523 add_show_from_set (add_set_cmd ("apcs32", no_class
,
1524 var_zinteger
, (char *)&arm_apcs_32
,
1525 "Set usage of ARM 32-bit mode.\n", &setlist
),
1530 /* Test whether the coff symbol specific value corresponds to a Thumb function */
1532 coff_sym_is_thumb(int val
)
1534 return (val
== C_THUMBEXT
||
1535 val
== C_THUMBSTAT
||
1536 val
== C_THUMBEXTFUNC
||
1537 val
== C_THUMBSTATFUNC
||
1538 val
== C_THUMBLABEL
);