1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
31 #include "reggroups.h"
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "arch/arm-get-next-pcs.h"
51 #include "gdb/sim-arm.h"
54 #include "coff/internal.h"
60 #include "record-full.h"
62 #include "features/arm-with-m.c"
63 #include "features/arm-with-m-fpa-layout.c"
64 #include "features/arm-with-m-vfp-d16.c"
65 #include "features/arm-with-iwmmxt.c"
66 #include "features/arm-with-vfpv2.c"
67 #include "features/arm-with-vfpv3.c"
68 #include "features/arm-with-neon.c"
72 /* Macros for setting and testing a bit in a minimal symbol that marks
73 it as Thumb function. The MSB of the minimal symbol's "info" field
74 is used for this purpose.
76 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
77 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
79 #define MSYMBOL_SET_SPECIAL(msym) \
80 MSYMBOL_TARGET_FLAG_1 (msym) = 1
82 #define MSYMBOL_IS_SPECIAL(msym) \
83 MSYMBOL_TARGET_FLAG_1 (msym)
85 /* Per-objfile data used for mapping symbols. */
86 static const struct objfile_data
*arm_objfile_data_key
;
88 struct arm_mapping_symbol
93 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
94 DEF_VEC_O(arm_mapping_symbol_s
);
96 struct arm_per_objfile
98 VEC(arm_mapping_symbol_s
) **section_maps
;
101 /* The list of available "set arm ..." and "show arm ..." commands. */
102 static struct cmd_list_element
*setarmcmdlist
= NULL
;
103 static struct cmd_list_element
*showarmcmdlist
= NULL
;
105 /* The type of floating-point to use. Keep this in sync with enum
106 arm_float_model, and the help string in _initialize_arm_tdep. */
107 static const char *const fp_model_strings
[] =
117 /* A variable that can be configured by the user. */
118 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
119 static const char *current_fp_model
= "auto";
121 /* The ABI to use. Keep this in sync with arm_abi_kind. */
122 static const char *const arm_abi_strings
[] =
130 /* A variable that can be configured by the user. */
131 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
132 static const char *arm_abi_string
= "auto";
134 /* The execution mode to assume. */
135 static const char *const arm_mode_strings
[] =
143 static const char *arm_fallback_mode_string
= "auto";
144 static const char *arm_force_mode_string
= "auto";
146 /* Internal override of the execution mode. -1 means no override,
147 0 means override to ARM mode, 1 means override to Thumb mode.
148 The effect is the same as if arm_force_mode has been set by the
149 user (except the internal override has precedence over a user's
150 arm_force_mode override). */
151 static int arm_override_mode
= -1;
153 /* Number of different reg name sets (options). */
154 static int num_disassembly_options
;
156 /* The standard register names, and all the valid aliases for them. Note
157 that `fp', `sp' and `pc' are not added in this alias list, because they
158 have been added as builtin user registers in
159 std-regs.c:_initialize_frame_reg. */
164 } arm_register_aliases
[] = {
165 /* Basic register numbers. */
182 /* Synonyms (argument and variable registers). */
195 /* Other platform-specific names for r9. */
201 /* Names used by GCC (not listed in the ARM EABI). */
203 /* A special name from the older ATPCS. */
207 static const char *const arm_register_names
[] =
208 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
209 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
210 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
211 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
212 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
213 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
214 "fps", "cpsr" }; /* 24 25 */
216 /* Valid register name styles. */
217 static const char **valid_disassembly_styles
;
219 /* Disassembly style to use. Default to "std" register names. */
220 static const char *disassembly_style
;
222 /* This is used to keep the bfd arch_info in sync with the disassembly
224 static void set_disassembly_style_sfunc(char *, int,
225 struct cmd_list_element
*);
226 static void set_disassembly_style (void);
228 static void convert_from_extended (const struct floatformat
*, const void *,
230 static void convert_to_extended (const struct floatformat
*, void *,
233 static enum register_status
arm_neon_quad_read (struct gdbarch
*gdbarch
,
234 struct regcache
*regcache
,
235 int regnum
, gdb_byte
*buf
);
236 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
237 struct regcache
*regcache
,
238 int regnum
, const gdb_byte
*buf
);
241 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
);
244 /* get_next_pcs operations. */
245 static struct arm_get_next_pcs_ops arm_get_next_pcs_ops
= {
246 arm_get_next_pcs_read_memory_unsigned_integer
,
247 arm_get_next_pcs_syscall_next_pc
,
248 arm_get_next_pcs_addr_bits_remove
,
249 arm_get_next_pcs_is_thumb
,
253 struct arm_prologue_cache
255 /* The stack pointer at the time this frame was created; i.e. the
256 caller's stack pointer when this function was called. It is used
257 to identify this frame. */
260 /* The frame base for this frame is just prev_sp - frame size.
261 FRAMESIZE is the distance from the frame pointer to the
262 initial stack pointer. */
266 /* The register used to hold the frame pointer for this frame. */
269 /* Saved register offsets. */
270 struct trad_frame_saved_reg
*saved_regs
;
273 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
274 CORE_ADDR prologue_start
,
275 CORE_ADDR prologue_end
,
276 struct arm_prologue_cache
*cache
);
278 /* Architecture version for displaced stepping. This effects the behaviour of
279 certain instructions, and really should not be hard-wired. */
281 #define DISPLACED_STEPPING_ARCH_VERSION 5
283 /* Set to true if the 32-bit mode is in use. */
287 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
290 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
292 if (gdbarch_tdep (gdbarch
)->is_m
)
298 /* Determine if the processor is currently executing in Thumb mode. */
301 arm_is_thumb (struct regcache
*regcache
)
304 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regcache
));
306 cpsr
= regcache_raw_get_unsigned (regcache
, ARM_PS_REGNUM
);
308 return (cpsr
& t_bit
) != 0;
311 /* Determine if FRAME is executing in Thumb mode. */
314 arm_frame_is_thumb (struct frame_info
*frame
)
317 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
319 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
320 directly (from a signal frame or dummy frame) or by interpreting
321 the saved LR (from a prologue or DWARF frame). So consult it and
322 trust the unwinders. */
323 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
325 return (cpsr
& t_bit
) != 0;
328 /* Callback for VEC_lower_bound. */
331 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
332 const struct arm_mapping_symbol
*rhs
)
334 return lhs
->value
< rhs
->value
;
337 /* Search for the mapping symbol covering MEMADDR. If one is found,
338 return its type. Otherwise, return 0. If START is non-NULL,
339 set *START to the location of the mapping symbol. */
342 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
344 struct obj_section
*sec
;
346 /* If there are mapping symbols, consult them. */
347 sec
= find_pc_section (memaddr
);
350 struct arm_per_objfile
*data
;
351 VEC(arm_mapping_symbol_s
) *map
;
352 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
356 data
= (struct arm_per_objfile
*) objfile_data (sec
->objfile
,
357 arm_objfile_data_key
);
360 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
361 if (!VEC_empty (arm_mapping_symbol_s
, map
))
363 struct arm_mapping_symbol
*map_sym
;
365 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
366 arm_compare_mapping_symbols
);
368 /* VEC_lower_bound finds the earliest ordered insertion
369 point. If the following symbol starts at this exact
370 address, we use that; otherwise, the preceding
371 mapping symbol covers this address. */
372 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
374 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
375 if (map_sym
->value
== map_key
.value
)
378 *start
= map_sym
->value
+ obj_section_addr (sec
);
379 return map_sym
->type
;
385 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
387 *start
= map_sym
->value
+ obj_section_addr (sec
);
388 return map_sym
->type
;
397 /* Determine if the program counter specified in MEMADDR is in a Thumb
398 function. This function should be called for addresses unrelated to
399 any executing frame; otherwise, prefer arm_frame_is_thumb. */
402 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
404 struct bound_minimal_symbol sym
;
406 struct displaced_step_closure
* dsc
407 = get_displaced_step_closure_by_addr(memaddr
);
409 /* If checking the mode of displaced instruction in copy area, the mode
410 should be determined by instruction on the original address. */
414 fprintf_unfiltered (gdb_stdlog
,
415 "displaced: check mode of %.8lx instead of %.8lx\n",
416 (unsigned long) dsc
->insn_addr
,
417 (unsigned long) memaddr
);
418 memaddr
= dsc
->insn_addr
;
421 /* If bit 0 of the address is set, assume this is a Thumb address. */
422 if (IS_THUMB_ADDR (memaddr
))
425 /* Respect internal mode override if active. */
426 if (arm_override_mode
!= -1)
427 return arm_override_mode
;
429 /* If the user wants to override the symbol table, let him. */
430 if (strcmp (arm_force_mode_string
, "arm") == 0)
432 if (strcmp (arm_force_mode_string
, "thumb") == 0)
435 /* ARM v6-M and v7-M are always in Thumb mode. */
436 if (gdbarch_tdep (gdbarch
)->is_m
)
439 /* If there are mapping symbols, consult them. */
440 type
= arm_find_mapping_symbol (memaddr
, NULL
);
444 /* Thumb functions have a "special" bit set in minimal symbols. */
445 sym
= lookup_minimal_symbol_by_pc (memaddr
);
447 return (MSYMBOL_IS_SPECIAL (sym
.minsym
));
449 /* If the user wants to override the fallback mode, let them. */
450 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
452 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
455 /* If we couldn't find any symbol, but we're talking to a running
456 target, then trust the current value of $cpsr. This lets
457 "display/i $pc" always show the correct mode (though if there is
458 a symbol table we will not reach here, so it still may not be
459 displayed in the mode it will be executed). */
460 if (target_has_registers
)
461 return arm_frame_is_thumb (get_current_frame ());
463 /* Otherwise we're out of luck; we assume ARM. */
467 /* Remove useless bits from addresses in a running program. */
469 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
471 /* On M-profile devices, do not strip the low bit from EXC_RETURN
472 (the magic exception return address). */
473 if (gdbarch_tdep (gdbarch
)->is_m
474 && (val
& 0xfffffff0) == 0xfffffff0)
478 return UNMAKE_THUMB_ADDR (val
);
480 return (val
& 0x03fffffc);
483 /* Return 1 if PC is the start of a compiler helper function which
484 can be safely ignored during prologue skipping. IS_THUMB is true
485 if the function is known to be a Thumb function due to the way it
488 skip_prologue_function (struct gdbarch
*gdbarch
, CORE_ADDR pc
, int is_thumb
)
490 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
491 struct bound_minimal_symbol msym
;
493 msym
= lookup_minimal_symbol_by_pc (pc
);
494 if (msym
.minsym
!= NULL
495 && BMSYMBOL_VALUE_ADDRESS (msym
) == pc
496 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
)
498 const char *name
= MSYMBOL_LINKAGE_NAME (msym
.minsym
);
500 /* The GNU linker's Thumb call stub to foo is named
502 if (strstr (name
, "_from_thumb") != NULL
)
505 /* On soft-float targets, __truncdfsf2 is called to convert promoted
506 arguments to their argument types in non-prototyped
508 if (startswith (name
, "__truncdfsf2"))
510 if (startswith (name
, "__aeabi_d2f"))
513 /* Internal functions related to thread-local storage. */
514 if (startswith (name
, "__tls_get_addr"))
516 if (startswith (name
, "__aeabi_read_tp"))
521 /* If we run against a stripped glibc, we may be unable to identify
522 special functions by name. Check for one important case,
523 __aeabi_read_tp, by comparing the *code* against the default
524 implementation (this is hand-written ARM assembler in glibc). */
527 && read_memory_unsigned_integer (pc
, 4, byte_order_for_code
)
528 == 0xe3e00a0f /* mov r0, #0xffff0fff */
529 && read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
)
530 == 0xe240f01f) /* sub pc, r0, #31 */
537 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
538 the first 16-bit of instruction, and INSN2 is the second 16-bit of
540 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
541 ((bits ((insn1), 0, 3) << 12) \
542 | (bits ((insn1), 10, 10) << 11) \
543 | (bits ((insn2), 12, 14) << 8) \
544 | bits ((insn2), 0, 7))
546 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
547 the 32-bit instruction. */
548 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
549 ((bits ((insn), 16, 19) << 12) \
550 | bits ((insn), 0, 11))
552 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
555 thumb_expand_immediate (unsigned int imm
)
557 unsigned int count
= imm
>> 7;
565 return (imm
& 0xff) | ((imm
& 0xff) << 16);
567 return ((imm
& 0xff) << 8) | ((imm
& 0xff) << 24);
569 return (imm
& 0xff) | ((imm
& 0xff) << 8)
570 | ((imm
& 0xff) << 16) | ((imm
& 0xff) << 24);
573 return (0x80 | (imm
& 0x7f)) << (32 - count
);
576 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
577 epilogue, 0 otherwise. */
580 thumb_instruction_restores_sp (unsigned short insn
)
582 return (insn
== 0x46bd /* mov sp, r7 */
583 || (insn
& 0xff80) == 0xb000 /* add sp, imm */
584 || (insn
& 0xfe00) == 0xbc00); /* pop <registers> */
587 /* Analyze a Thumb prologue, looking for a recognizable stack frame
588 and frame pointer. Scan until we encounter a store that could
589 clobber the stack frame unexpectedly, or an unknown instruction.
590 Return the last address which is definitely safe to skip for an
591 initial breakpoint. */
594 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
595 CORE_ADDR start
, CORE_ADDR limit
,
596 struct arm_prologue_cache
*cache
)
598 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
599 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
602 struct pv_area
*stack
;
603 struct cleanup
*back_to
;
605 CORE_ADDR unrecognized_pc
= 0;
607 for (i
= 0; i
< 16; i
++)
608 regs
[i
] = pv_register (i
, 0);
609 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
610 back_to
= make_cleanup_free_pv_area (stack
);
612 while (start
< limit
)
616 insn
= read_memory_unsigned_integer (start
, 2, byte_order_for_code
);
618 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
623 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
626 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
627 whether to save LR (R14). */
628 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
630 /* Calculate offsets of saved R0-R7 and LR. */
631 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
632 if (mask
& (1 << regno
))
634 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
636 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
639 else if ((insn
& 0xff80) == 0xb080) /* sub sp, #imm */
641 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
642 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
645 else if (thumb_instruction_restores_sp (insn
))
647 /* Don't scan past the epilogue. */
650 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
651 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
653 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
654 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
655 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
657 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
658 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
659 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
661 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
662 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
663 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
664 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
665 regs
[bits (insn
, 6, 8)]);
666 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
667 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
669 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
670 int rm
= bits (insn
, 3, 6);
671 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
673 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
675 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
676 int src_reg
= (insn
& 0x78) >> 3;
677 regs
[dst_reg
] = regs
[src_reg
];
679 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
681 /* Handle stores to the stack. Normally pushes are used,
682 but with GCC -mtpcs-frame, there may be other stores
683 in the prologue to create the frame. */
684 int regno
= (insn
>> 8) & 0x7;
687 offset
= (insn
& 0xff) << 2;
688 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
690 if (pv_area_store_would_trash (stack
, addr
))
693 pv_area_store (stack
, addr
, 4, regs
[regno
]);
695 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
697 int rd
= bits (insn
, 0, 2);
698 int rn
= bits (insn
, 3, 5);
701 offset
= bits (insn
, 6, 10) << 2;
702 addr
= pv_add_constant (regs
[rn
], offset
);
704 if (pv_area_store_would_trash (stack
, addr
))
707 pv_area_store (stack
, addr
, 4, regs
[rd
]);
709 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
710 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
711 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
712 /* Ignore stores of argument registers to the stack. */
714 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
715 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
716 /* Ignore block loads from the stack, potentially copying
717 parameters from memory. */
719 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
720 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
721 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
722 /* Similarly ignore single loads from the stack. */
724 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
725 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
726 /* Skip register copies, i.e. saves to another register
727 instead of the stack. */
729 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
730 /* Recognize constant loads; even with small stacks these are necessary
732 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
733 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
735 /* Constant pool loads, for the same reason. */
736 unsigned int constant
;
739 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
740 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
741 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
743 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instructions. */
745 unsigned short inst2
;
747 inst2
= read_memory_unsigned_integer (start
+ 2, 2,
748 byte_order_for_code
);
750 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
752 /* BL, BLX. Allow some special function calls when
753 skipping the prologue; GCC generates these before
754 storing arguments to the stack. */
756 int j1
, j2
, imm1
, imm2
;
758 imm1
= sbits (insn
, 0, 10);
759 imm2
= bits (inst2
, 0, 10);
760 j1
= bit (inst2
, 13);
761 j2
= bit (inst2
, 11);
763 offset
= ((imm1
<< 12) + (imm2
<< 1));
764 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
766 nextpc
= start
+ 4 + offset
;
767 /* For BLX make sure to clear the low bits. */
768 if (bit (inst2
, 12) == 0)
769 nextpc
= nextpc
& 0xfffffffc;
771 if (!skip_prologue_function (gdbarch
, nextpc
,
772 bit (inst2
, 12) != 0))
776 else if ((insn
& 0xffd0) == 0xe900 /* stmdb Rn{!},
778 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
780 pv_t addr
= regs
[bits (insn
, 0, 3)];
783 if (pv_area_store_would_trash (stack
, addr
))
786 /* Calculate offsets of saved registers. */
787 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
788 if (inst2
& (1 << regno
))
790 addr
= pv_add_constant (addr
, -4);
791 pv_area_store (stack
, addr
, 4, regs
[regno
]);
795 regs
[bits (insn
, 0, 3)] = addr
;
798 else if ((insn
& 0xff50) == 0xe940 /* strd Rt, Rt2,
800 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
802 int regno1
= bits (inst2
, 12, 15);
803 int regno2
= bits (inst2
, 8, 11);
804 pv_t addr
= regs
[bits (insn
, 0, 3)];
806 offset
= inst2
& 0xff;
808 addr
= pv_add_constant (addr
, offset
);
810 addr
= pv_add_constant (addr
, -offset
);
812 if (pv_area_store_would_trash (stack
, addr
))
815 pv_area_store (stack
, addr
, 4, regs
[regno1
]);
816 pv_area_store (stack
, pv_add_constant (addr
, 4),
820 regs
[bits (insn
, 0, 3)] = addr
;
823 else if ((insn
& 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
824 && (inst2
& 0x0c00) == 0x0c00
825 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
827 int regno
= bits (inst2
, 12, 15);
828 pv_t addr
= regs
[bits (insn
, 0, 3)];
830 offset
= inst2
& 0xff;
832 addr
= pv_add_constant (addr
, offset
);
834 addr
= pv_add_constant (addr
, -offset
);
836 if (pv_area_store_would_trash (stack
, addr
))
839 pv_area_store (stack
, addr
, 4, regs
[regno
]);
842 regs
[bits (insn
, 0, 3)] = addr
;
845 else if ((insn
& 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
846 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
848 int regno
= bits (inst2
, 12, 15);
851 offset
= inst2
& 0xfff;
852 addr
= pv_add_constant (regs
[bits (insn
, 0, 3)], offset
);
854 if (pv_area_store_would_trash (stack
, addr
))
857 pv_area_store (stack
, addr
, 4, regs
[regno
]);
860 else if ((insn
& 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
861 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
862 /* Ignore stores of argument registers to the stack. */
865 else if ((insn
& 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
866 && (inst2
& 0x0d00) == 0x0c00
867 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
868 /* Ignore stores of argument registers to the stack. */
871 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!],
873 && (inst2
& 0x8000) == 0x0000
874 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
875 /* Ignore block loads from the stack, potentially copying
876 parameters from memory. */
879 else if ((insn
& 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
881 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
882 /* Similarly ignore dual loads from the stack. */
885 else if ((insn
& 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
886 && (inst2
& 0x0d00) == 0x0c00
887 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
888 /* Similarly ignore single loads from the stack. */
891 else if ((insn
& 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
892 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
893 /* Similarly ignore single loads from the stack. */
896 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
897 && (inst2
& 0x8000) == 0x0000)
899 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
900 | (bits (inst2
, 12, 14) << 8)
901 | bits (inst2
, 0, 7));
903 regs
[bits (inst2
, 8, 11)]
904 = pv_add_constant (regs
[bits (insn
, 0, 3)],
905 thumb_expand_immediate (imm
));
908 else if ((insn
& 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
909 && (inst2
& 0x8000) == 0x0000)
911 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
912 | (bits (inst2
, 12, 14) << 8)
913 | bits (inst2
, 0, 7));
915 regs
[bits (inst2
, 8, 11)]
916 = pv_add_constant (regs
[bits (insn
, 0, 3)], imm
);
919 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
920 && (inst2
& 0x8000) == 0x0000)
922 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
923 | (bits (inst2
, 12, 14) << 8)
924 | bits (inst2
, 0, 7));
926 regs
[bits (inst2
, 8, 11)]
927 = pv_add_constant (regs
[bits (insn
, 0, 3)],
928 - (CORE_ADDR
) thumb_expand_immediate (imm
));
931 else if ((insn
& 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
932 && (inst2
& 0x8000) == 0x0000)
934 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
935 | (bits (inst2
, 12, 14) << 8)
936 | bits (inst2
, 0, 7));
938 regs
[bits (inst2
, 8, 11)]
939 = pv_add_constant (regs
[bits (insn
, 0, 3)], - (CORE_ADDR
) imm
);
942 else if ((insn
& 0xfbff) == 0xf04f) /* mov.w Rd, #const */
944 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
945 | (bits (inst2
, 12, 14) << 8)
946 | bits (inst2
, 0, 7));
948 regs
[bits (inst2
, 8, 11)]
949 = pv_constant (thumb_expand_immediate (imm
));
952 else if ((insn
& 0xfbf0) == 0xf240) /* movw Rd, #const */
955 = EXTRACT_MOVW_MOVT_IMM_T (insn
, inst2
);
957 regs
[bits (inst2
, 8, 11)] = pv_constant (imm
);
960 else if (insn
== 0xea5f /* mov.w Rd,Rm */
961 && (inst2
& 0xf0f0) == 0)
963 int dst_reg
= (inst2
& 0x0f00) >> 8;
964 int src_reg
= inst2
& 0xf;
965 regs
[dst_reg
] = regs
[src_reg
];
968 else if ((insn
& 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
970 /* Constant pool loads. */
971 unsigned int constant
;
974 offset
= bits (inst2
, 0, 11);
976 loc
= start
+ 4 + offset
;
978 loc
= start
+ 4 - offset
;
980 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
981 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
984 else if ((insn
& 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
986 /* Constant pool loads. */
987 unsigned int constant
;
990 offset
= bits (inst2
, 0, 7) << 2;
992 loc
= start
+ 4 + offset
;
994 loc
= start
+ 4 - offset
;
996 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
997 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
999 constant
= read_memory_unsigned_integer (loc
+ 4, 4, byte_order
);
1000 regs
[bits (inst2
, 8, 11)] = pv_constant (constant
);
1003 else if (thumb2_instruction_changes_pc (insn
, inst2
))
1005 /* Don't scan past anything that might change control flow. */
1010 /* The optimizer might shove anything into the prologue,
1011 so we just skip what we don't recognize. */
1012 unrecognized_pc
= start
;
1017 else if (thumb_instruction_changes_pc (insn
))
1019 /* Don't scan past anything that might change control flow. */
1024 /* The optimizer might shove anything into the prologue,
1025 so we just skip what we don't recognize. */
1026 unrecognized_pc
= start
;
1033 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1034 paddress (gdbarch
, start
));
1036 if (unrecognized_pc
== 0)
1037 unrecognized_pc
= start
;
1041 do_cleanups (back_to
);
1042 return unrecognized_pc
;
1045 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1047 /* Frame pointer is fp. Frame size is constant. */
1048 cache
->framereg
= ARM_FP_REGNUM
;
1049 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1051 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
1053 /* Frame pointer is r7. Frame size is constant. */
1054 cache
->framereg
= THUMB_FP_REGNUM
;
1055 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
1059 /* Try the stack pointer... this is a bit desperate. */
1060 cache
->framereg
= ARM_SP_REGNUM
;
1061 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1064 for (i
= 0; i
< 16; i
++)
1065 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
1066 cache
->saved_regs
[i
].addr
= offset
;
1068 do_cleanups (back_to
);
1069 return unrecognized_pc
;
1073 /* Try to analyze the instructions starting from PC, which load symbol
1074 __stack_chk_guard. Return the address of instruction after loading this
1075 symbol, set the dest register number to *BASEREG, and set the size of
1076 instructions for loading symbol in OFFSET. Return 0 if instructions are
1080 arm_analyze_load_stack_chk_guard(CORE_ADDR pc
, struct gdbarch
*gdbarch
,
1081 unsigned int *destreg
, int *offset
)
1083 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1084 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1085 unsigned int low
, high
, address
;
1090 unsigned short insn1
1091 = read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
1093 if ((insn1
& 0xf800) == 0x4800) /* ldr Rd, #immed */
1095 *destreg
= bits (insn1
, 8, 10);
1097 address
= (pc
& 0xfffffffc) + 4 + (bits (insn1
, 0, 7) << 2);
1098 address
= read_memory_unsigned_integer (address
, 4,
1099 byte_order_for_code
);
1101 else if ((insn1
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1103 unsigned short insn2
1104 = read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1106 low
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1109 = read_memory_unsigned_integer (pc
+ 4, 2, byte_order_for_code
);
1111 = read_memory_unsigned_integer (pc
+ 6, 2, byte_order_for_code
);
1113 /* movt Rd, #const */
1114 if ((insn1
& 0xfbc0) == 0xf2c0)
1116 high
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1117 *destreg
= bits (insn2
, 8, 11);
1119 address
= (high
<< 16 | low
);
1126 = read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
1128 if ((insn
& 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1130 address
= bits (insn
, 0, 11) + pc
+ 8;
1131 address
= read_memory_unsigned_integer (address
, 4,
1132 byte_order_for_code
);
1134 *destreg
= bits (insn
, 12, 15);
1137 else if ((insn
& 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1139 low
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1142 = read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
);
1144 if ((insn
& 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1146 high
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1147 *destreg
= bits (insn
, 12, 15);
1149 address
= (high
<< 16 | low
);
1157 /* Try to skip a sequence of instructions used for stack protector. If PC
1158 points to the first instruction of this sequence, return the address of
1159 first instruction after this sequence, otherwise, return original PC.
1161 On arm, this sequence of instructions is composed of mainly three steps,
1162 Step 1: load symbol __stack_chk_guard,
1163 Step 2: load from address of __stack_chk_guard,
1164 Step 3: store it to somewhere else.
1166 Usually, instructions on step 2 and step 3 are the same on various ARM
1167 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1168 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1169 instructions in step 1 vary from different ARM architectures. On ARMv7,
1172 movw Rn, #:lower16:__stack_chk_guard
1173 movt Rn, #:upper16:__stack_chk_guard
1180 .word __stack_chk_guard
1182 Since ldr/str is a very popular instruction, we can't use them as
1183 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1184 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1185 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1188 arm_skip_stack_protector(CORE_ADDR pc
, struct gdbarch
*gdbarch
)
1190 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1191 unsigned int basereg
;
1192 struct bound_minimal_symbol stack_chk_guard
;
1194 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1197 /* Try to parse the instructions in Step 1. */
1198 addr
= arm_analyze_load_stack_chk_guard (pc
, gdbarch
,
1203 stack_chk_guard
= lookup_minimal_symbol_by_pc (addr
);
1204 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1205 Otherwise, this sequence cannot be for stack protector. */
1206 if (stack_chk_guard
.minsym
== NULL
1207 || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard
.minsym
), "__stack_chk_guard"))
1212 unsigned int destreg
;
1214 = read_memory_unsigned_integer (pc
+ offset
, 2, byte_order_for_code
);
1216 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1217 if ((insn
& 0xf800) != 0x6800)
1219 if (bits (insn
, 3, 5) != basereg
)
1221 destreg
= bits (insn
, 0, 2);
1223 insn
= read_memory_unsigned_integer (pc
+ offset
+ 2, 2,
1224 byte_order_for_code
);
1225 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1226 if ((insn
& 0xf800) != 0x6000)
1228 if (destreg
!= bits (insn
, 0, 2))
1233 unsigned int destreg
;
1235 = read_memory_unsigned_integer (pc
+ offset
, 4, byte_order_for_code
);
1237 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1238 if ((insn
& 0x0e500000) != 0x04100000)
1240 if (bits (insn
, 16, 19) != basereg
)
1242 destreg
= bits (insn
, 12, 15);
1243 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1244 insn
= read_memory_unsigned_integer (pc
+ offset
+ 4,
1245 4, byte_order_for_code
);
1246 if ((insn
& 0x0e500000) != 0x04000000)
1248 if (bits (insn
, 12, 15) != destreg
)
1251 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1254 return pc
+ offset
+ 4;
1256 return pc
+ offset
+ 8;
1259 /* Advance the PC across any function entry prologue instructions to
1260 reach some "real" code.
1262 The APCS (ARM Procedure Call Standard) defines the following
1266 [stmfd sp!, {a1,a2,a3,a4}]
1267 stmfd sp!, {...,fp,ip,lr,pc}
1268 [stfe f7, [sp, #-12]!]
1269 [stfe f6, [sp, #-12]!]
1270 [stfe f5, [sp, #-12]!]
1271 [stfe f4, [sp, #-12]!]
1272 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1275 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1277 CORE_ADDR func_addr
, limit_pc
;
1279 /* See if we can determine the end of the prologue via the symbol table.
1280 If so, then return either PC, or the PC after the prologue, whichever
1282 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1284 CORE_ADDR post_prologue_pc
1285 = skip_prologue_using_sal (gdbarch
, func_addr
);
1286 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1288 if (post_prologue_pc
)
1290 = arm_skip_stack_protector (post_prologue_pc
, gdbarch
);
1293 /* GCC always emits a line note before the prologue and another
1294 one after, even if the two are at the same address or on the
1295 same line. Take advantage of this so that we do not need to
1296 know every instruction that might appear in the prologue. We
1297 will have producer information for most binaries; if it is
1298 missing (e.g. for -gstabs), assuming the GNU tools. */
1299 if (post_prologue_pc
1301 || COMPUNIT_PRODUCER (cust
) == NULL
1302 || startswith (COMPUNIT_PRODUCER (cust
), "GNU ")
1303 || startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
1304 return post_prologue_pc
;
1306 if (post_prologue_pc
!= 0)
1308 CORE_ADDR analyzed_limit
;
1310 /* For non-GCC compilers, make sure the entire line is an
1311 acceptable prologue; GDB will round this function's
1312 return value up to the end of the following line so we
1313 can not skip just part of a line (and we do not want to).
1315 RealView does not treat the prologue specially, but does
1316 associate prologue code with the opening brace; so this
1317 lets us skip the first line if we think it is the opening
1319 if (arm_pc_is_thumb (gdbarch
, func_addr
))
1320 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
1321 post_prologue_pc
, NULL
);
1323 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
1324 post_prologue_pc
, NULL
);
1326 if (analyzed_limit
!= post_prologue_pc
)
1329 return post_prologue_pc
;
1333 /* Can't determine prologue from the symbol table, need to examine
1336 /* Find an upper limit on the function prologue using the debug
1337 information. If the debug information could not be used to provide
1338 that bound, then use an arbitrary large number as the upper bound. */
1339 /* Like arm_scan_prologue, stop no later than pc + 64. */
1340 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1342 limit_pc
= pc
+ 64; /* Magic. */
1345 /* Check if this is Thumb code. */
1346 if (arm_pc_is_thumb (gdbarch
, pc
))
1347 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1349 return arm_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1353 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1354 This function decodes a Thumb function prologue to determine:
1355 1) the size of the stack frame
1356 2) which registers are saved on it
1357 3) the offsets of saved regs
1358 4) the offset from the stack pointer to the frame pointer
1360 A typical Thumb function prologue would create this stack frame
1361 (offsets relative to FP)
1362 old SP -> 24 stack parameters
1365 R7 -> 0 local variables (16 bytes)
1366 SP -> -12 additional stack space (12 bytes)
1367 The frame size would thus be 36 bytes, and the frame offset would be
1368 12 bytes. The frame register is R7.
1370 The comments for thumb_skip_prolog() describe the algorithm we use
1371 to detect the end of the prolog. */
1375 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
1376 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
1378 CORE_ADDR prologue_start
;
1379 CORE_ADDR prologue_end
;
1381 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1384 /* See comment in arm_scan_prologue for an explanation of
1386 if (prologue_end
> prologue_start
+ 64)
1388 prologue_end
= prologue_start
+ 64;
1392 /* We're in the boondocks: we have no idea where the start of the
1396 prologue_end
= min (prologue_end
, prev_pc
);
1398 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1401 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1405 arm_instruction_restores_sp (unsigned int insn
)
1407 if (bits (insn
, 28, 31) != INST_NV
)
1409 if ((insn
& 0x0df0f000) == 0x0080d000
1410 /* ADD SP (register or immediate). */
1411 || (insn
& 0x0df0f000) == 0x0040d000
1412 /* SUB SP (register or immediate). */
1413 || (insn
& 0x0ffffff0) == 0x01a0d000
1415 || (insn
& 0x0fff0000) == 0x08bd0000
1417 || (insn
& 0x0fff0000) == 0x049d0000)
1418 /* POP of a single register. */
1425 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1426 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1427 fill it in. Return the first address not recognized as a prologue
1430 We recognize all the instructions typically found in ARM prologues,
1431 plus harmless instructions which can be skipped (either for analysis
1432 purposes, or a more restrictive set that can be skipped when finding
1433 the end of the prologue). */
1436 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1437 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1438 struct arm_prologue_cache
*cache
)
1440 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1442 CORE_ADDR offset
, current_pc
;
1443 pv_t regs
[ARM_FPS_REGNUM
];
1444 struct pv_area
*stack
;
1445 struct cleanup
*back_to
;
1446 CORE_ADDR unrecognized_pc
= 0;
1448 /* Search the prologue looking for instructions that set up the
1449 frame pointer, adjust the stack pointer, and save registers.
1451 Be careful, however, and if it doesn't look like a prologue,
1452 don't try to scan it. If, for instance, a frameless function
1453 begins with stmfd sp!, then we will tell ourselves there is
1454 a frame, which will confuse stack traceback, as well as "finish"
1455 and other operations that rely on a knowledge of the stack
1458 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1459 regs
[regno
] = pv_register (regno
, 0);
1460 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1461 back_to
= make_cleanup_free_pv_area (stack
);
1463 for (current_pc
= prologue_start
;
1464 current_pc
< prologue_end
;
1468 = read_memory_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1470 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1472 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1475 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1476 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1478 unsigned imm
= insn
& 0xff; /* immediate value */
1479 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1480 int rd
= bits (insn
, 12, 15);
1481 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1482 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1485 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1486 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1488 unsigned imm
= insn
& 0xff; /* immediate value */
1489 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1490 int rd
= bits (insn
, 12, 15);
1491 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1492 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1495 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd,
1498 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1500 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1501 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4,
1502 regs
[bits (insn
, 12, 15)]);
1505 else if ((insn
& 0xffff0000) == 0xe92d0000)
1506 /* stmfd sp!, {..., fp, ip, lr, pc}
1508 stmfd sp!, {a1, a2, a3, a4} */
1510 int mask
= insn
& 0xffff;
1512 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1515 /* Calculate offsets of saved registers. */
1516 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1517 if (mask
& (1 << regno
))
1520 = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1521 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1524 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1525 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1526 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1528 /* No need to add this to saved_regs -- it's just an arg reg. */
1531 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1532 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1533 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1535 /* No need to add this to saved_regs -- it's just an arg reg. */
1538 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn,
1540 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1542 /* No need to add this to saved_regs -- it's just arg regs. */
1545 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1547 unsigned imm
= insn
& 0xff; /* immediate value */
1548 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1549 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1550 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1552 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1554 unsigned imm
= insn
& 0xff; /* immediate value */
1555 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1556 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1557 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1559 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?,
1561 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1563 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1566 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1567 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1568 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1570 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1572 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1574 int n_saved_fp_regs
;
1575 unsigned int fp_start_reg
, fp_bound_reg
;
1577 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1580 if ((insn
& 0x800) == 0x800) /* N0 is set */
1582 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1583 n_saved_fp_regs
= 3;
1585 n_saved_fp_regs
= 1;
1589 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1590 n_saved_fp_regs
= 2;
1592 n_saved_fp_regs
= 4;
1595 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1596 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1597 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1599 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1600 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
1601 regs
[fp_start_reg
++]);
1604 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1606 /* Allow some special function calls when skipping the
1607 prologue; GCC generates these before storing arguments to
1609 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1611 if (skip_prologue_function (gdbarch
, dest
, 0))
1616 else if ((insn
& 0xf0000000) != 0xe0000000)
1617 break; /* Condition not true, exit early. */
1618 else if (arm_instruction_changes_pc (insn
))
1619 /* Don't scan past anything that might change control flow. */
1621 else if (arm_instruction_restores_sp (insn
))
1623 /* Don't scan past the epilogue. */
1626 else if ((insn
& 0xfe500000) == 0xe8100000 /* ldm */
1627 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1628 /* Ignore block loads from the stack, potentially copying
1629 parameters from memory. */
1631 else if ((insn
& 0xfc500000) == 0xe4100000
1632 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1633 /* Similarly ignore single loads from the stack. */
1635 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1636 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1637 register instead of the stack. */
1641 /* The optimizer might shove anything into the prologue, if
1642 we build up cache (cache != NULL) from scanning prologue,
1643 we just skip what we don't recognize and scan further to
1644 make cache as complete as possible. However, if we skip
1645 prologue, we'll stop immediately on unrecognized
1647 unrecognized_pc
= current_pc
;
1655 if (unrecognized_pc
== 0)
1656 unrecognized_pc
= current_pc
;
1660 int framereg
, framesize
;
1662 /* The frame size is just the distance from the frame register
1663 to the original stack pointer. */
1664 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1666 /* Frame pointer is fp. */
1667 framereg
= ARM_FP_REGNUM
;
1668 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1672 /* Try the stack pointer... this is a bit desperate. */
1673 framereg
= ARM_SP_REGNUM
;
1674 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1677 cache
->framereg
= framereg
;
1678 cache
->framesize
= framesize
;
1680 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1681 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1682 cache
->saved_regs
[regno
].addr
= offset
;
1686 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1687 paddress (gdbarch
, unrecognized_pc
));
1689 do_cleanups (back_to
);
1690 return unrecognized_pc
;
1694 arm_scan_prologue (struct frame_info
*this_frame
,
1695 struct arm_prologue_cache
*cache
)
1697 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1698 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1699 CORE_ADDR prologue_start
, prologue_end
;
1700 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1701 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1703 /* Assume there is no frame until proven otherwise. */
1704 cache
->framereg
= ARM_SP_REGNUM
;
1705 cache
->framesize
= 0;
1707 /* Check for Thumb prologue. */
1708 if (arm_frame_is_thumb (this_frame
))
1710 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1714 /* Find the function prologue. If we can't find the function in
1715 the symbol table, peek in the stack frame to find the PC. */
1716 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1719 /* One way to find the end of the prologue (which works well
1720 for unoptimized code) is to do the following:
1722 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1725 prologue_end = prev_pc;
1726 else if (sal.end < prologue_end)
1727 prologue_end = sal.end;
1729 This mechanism is very accurate so long as the optimizer
1730 doesn't move any instructions from the function body into the
1731 prologue. If this happens, sal.end will be the last
1732 instruction in the first hunk of prologue code just before
1733 the first instruction that the scheduler has moved from
1734 the body to the prologue.
1736 In order to make sure that we scan all of the prologue
1737 instructions, we use a slightly less accurate mechanism which
1738 may scan more than necessary. To help compensate for this
1739 lack of accuracy, the prologue scanning loop below contains
1740 several clauses which'll cause the loop to terminate early if
1741 an implausible prologue instruction is encountered.
1747 is a suitable endpoint since it accounts for the largest
1748 possible prologue plus up to five instructions inserted by
1751 if (prologue_end
> prologue_start
+ 64)
1753 prologue_end
= prologue_start
+ 64; /* See above. */
1758 /* We have no symbol information. Our only option is to assume this
1759 function has a standard stack frame and the normal frame register.
1760 Then, we can find the value of our frame pointer on entrance to
1761 the callee (or at the present moment if this is the innermost frame).
1762 The value stored there should be the address of the stmfd + 8. */
1763 CORE_ADDR frame_loc
;
1764 LONGEST return_value
;
1766 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
1767 if (!safe_read_memory_integer (frame_loc
, 4, byte_order
, &return_value
))
1771 prologue_start
= gdbarch_addr_bits_remove
1772 (gdbarch
, return_value
) - 8;
1773 prologue_end
= prologue_start
+ 64; /* See above. */
1777 if (prev_pc
< prologue_end
)
1778 prologue_end
= prev_pc
;
1780 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1783 static struct arm_prologue_cache
*
1784 arm_make_prologue_cache (struct frame_info
*this_frame
)
1787 struct arm_prologue_cache
*cache
;
1788 CORE_ADDR unwound_fp
;
1790 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1791 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1793 arm_scan_prologue (this_frame
, cache
);
1795 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
1796 if (unwound_fp
== 0)
1799 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
1801 /* Calculate actual addresses of saved registers using offsets
1802 determined by arm_scan_prologue. */
1803 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
1804 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
1805 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
1810 /* Implementation of the stop_reason hook for arm_prologue frames. */
1812 static enum unwind_stop_reason
1813 arm_prologue_unwind_stop_reason (struct frame_info
*this_frame
,
1816 struct arm_prologue_cache
*cache
;
1819 if (*this_cache
== NULL
)
1820 *this_cache
= arm_make_prologue_cache (this_frame
);
1821 cache
= (struct arm_prologue_cache
*) *this_cache
;
1823 /* This is meant to halt the backtrace at "_start". */
1824 pc
= get_frame_pc (this_frame
);
1825 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1826 return UNWIND_OUTERMOST
;
1828 /* If we've hit a wall, stop. */
1829 if (cache
->prev_sp
== 0)
1830 return UNWIND_OUTERMOST
;
1832 return UNWIND_NO_REASON
;
1835 /* Our frame ID for a normal frame is the current function's starting PC
1836 and the caller's SP when we were called. */
1839 arm_prologue_this_id (struct frame_info
*this_frame
,
1841 struct frame_id
*this_id
)
1843 struct arm_prologue_cache
*cache
;
1847 if (*this_cache
== NULL
)
1848 *this_cache
= arm_make_prologue_cache (this_frame
);
1849 cache
= (struct arm_prologue_cache
*) *this_cache
;
1851 /* Use function start address as part of the frame ID. If we cannot
1852 identify the start address (due to missing symbol information),
1853 fall back to just using the current PC. */
1854 pc
= get_frame_pc (this_frame
);
1855 func
= get_frame_func (this_frame
);
1859 id
= frame_id_build (cache
->prev_sp
, func
);
1863 static struct value
*
1864 arm_prologue_prev_register (struct frame_info
*this_frame
,
1868 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1869 struct arm_prologue_cache
*cache
;
1871 if (*this_cache
== NULL
)
1872 *this_cache
= arm_make_prologue_cache (this_frame
);
1873 cache
= (struct arm_prologue_cache
*) *this_cache
;
1875 /* If we are asked to unwind the PC, then we need to return the LR
1876 instead. The prologue may save PC, but it will point into this
1877 frame's prologue, not the next frame's resume location. Also
1878 strip the saved T bit. A valid LR may have the low bit set, but
1879 a valid PC never does. */
1880 if (prev_regnum
== ARM_PC_REGNUM
)
1884 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1885 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1886 arm_addr_bits_remove (gdbarch
, lr
));
1889 /* SP is generally not saved to the stack, but this frame is
1890 identified by the next frame's stack pointer at the time of the call.
1891 The value was already reconstructed into PREV_SP. */
1892 if (prev_regnum
== ARM_SP_REGNUM
)
1893 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1895 /* The CPSR may have been changed by the call instruction and by the
1896 called function. The only bit we can reconstruct is the T bit,
1897 by checking the low bit of LR as of the call. This is a reliable
1898 indicator of Thumb-ness except for some ARM v4T pre-interworking
1899 Thumb code, which could get away with a clear low bit as long as
1900 the called function did not use bx. Guess that all other
1901 bits are unchanged; the condition flags are presumably lost,
1902 but the processor status is likely valid. */
1903 if (prev_regnum
== ARM_PS_REGNUM
)
1906 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
1908 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1909 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1910 if (IS_THUMB_ADDR (lr
))
1914 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1917 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1921 struct frame_unwind arm_prologue_unwind
= {
1923 arm_prologue_unwind_stop_reason
,
1924 arm_prologue_this_id
,
1925 arm_prologue_prev_register
,
1927 default_frame_sniffer
1930 /* Maintain a list of ARM exception table entries per objfile, similar to the
1931 list of mapping symbols. We only cache entries for standard ARM-defined
1932 personality routines; the cache will contain only the frame unwinding
1933 instructions associated with the entry (not the descriptors). */
1935 static const struct objfile_data
*arm_exidx_data_key
;
1937 struct arm_exidx_entry
1942 typedef struct arm_exidx_entry arm_exidx_entry_s
;
1943 DEF_VEC_O(arm_exidx_entry_s
);
1945 struct arm_exidx_data
1947 VEC(arm_exidx_entry_s
) **section_maps
;
1951 arm_exidx_data_free (struct objfile
*objfile
, void *arg
)
1953 struct arm_exidx_data
*data
= (struct arm_exidx_data
*) arg
;
1956 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
1957 VEC_free (arm_exidx_entry_s
, data
->section_maps
[i
]);
1961 arm_compare_exidx_entries (const struct arm_exidx_entry
*lhs
,
1962 const struct arm_exidx_entry
*rhs
)
1964 return lhs
->addr
< rhs
->addr
;
1967 static struct obj_section
*
1968 arm_obj_section_from_vma (struct objfile
*objfile
, bfd_vma vma
)
1970 struct obj_section
*osect
;
1972 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
1973 if (bfd_get_section_flags (objfile
->obfd
,
1974 osect
->the_bfd_section
) & SEC_ALLOC
)
1976 bfd_vma start
, size
;
1977 start
= bfd_get_section_vma (objfile
->obfd
, osect
->the_bfd_section
);
1978 size
= bfd_get_section_size (osect
->the_bfd_section
);
1980 if (start
<= vma
&& vma
< start
+ size
)
1987 /* Parse contents of exception table and exception index sections
1988 of OBJFILE, and fill in the exception table entry cache.
1990 For each entry that refers to a standard ARM-defined personality
1991 routine, extract the frame unwinding instructions (from either
1992 the index or the table section). The unwinding instructions
1994 - extracting them from the rest of the table data
1995 - converting to host endianness
1996 - appending the implicit 0xb0 ("Finish") code
1998 The extracted and normalized instructions are stored for later
1999 retrieval by the arm_find_exidx_entry routine. */
2002 arm_exidx_new_objfile (struct objfile
*objfile
)
2004 struct cleanup
*cleanups
;
2005 struct arm_exidx_data
*data
;
2006 asection
*exidx
, *extab
;
2007 bfd_vma exidx_vma
= 0, extab_vma
= 0;
2008 bfd_size_type exidx_size
= 0, extab_size
= 0;
2009 gdb_byte
*exidx_data
= NULL
, *extab_data
= NULL
;
2012 /* If we've already touched this file, do nothing. */
2013 if (!objfile
|| objfile_data (objfile
, arm_exidx_data_key
) != NULL
)
2015 cleanups
= make_cleanup (null_cleanup
, NULL
);
2017 /* Read contents of exception table and index. */
2018 exidx
= bfd_get_section_by_name (objfile
->obfd
, ELF_STRING_ARM_unwind
);
2021 exidx_vma
= bfd_section_vma (objfile
->obfd
, exidx
);
2022 exidx_size
= bfd_get_section_size (exidx
);
2023 exidx_data
= (gdb_byte
*) xmalloc (exidx_size
);
2024 make_cleanup (xfree
, exidx_data
);
2026 if (!bfd_get_section_contents (objfile
->obfd
, exidx
,
2027 exidx_data
, 0, exidx_size
))
2029 do_cleanups (cleanups
);
2034 extab
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.extab");
2037 extab_vma
= bfd_section_vma (objfile
->obfd
, extab
);
2038 extab_size
= bfd_get_section_size (extab
);
2039 extab_data
= (gdb_byte
*) xmalloc (extab_size
);
2040 make_cleanup (xfree
, extab_data
);
2042 if (!bfd_get_section_contents (objfile
->obfd
, extab
,
2043 extab_data
, 0, extab_size
))
2045 do_cleanups (cleanups
);
2050 /* Allocate exception table data structure. */
2051 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
, struct arm_exidx_data
);
2052 set_objfile_data (objfile
, arm_exidx_data_key
, data
);
2053 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2054 objfile
->obfd
->section_count
,
2055 VEC(arm_exidx_entry_s
) *);
2057 /* Fill in exception table. */
2058 for (i
= 0; i
< exidx_size
/ 8; i
++)
2060 struct arm_exidx_entry new_exidx_entry
;
2061 bfd_vma idx
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8);
2062 bfd_vma val
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8 + 4);
2063 bfd_vma addr
= 0, word
= 0;
2064 int n_bytes
= 0, n_words
= 0;
2065 struct obj_section
*sec
;
2066 gdb_byte
*entry
= NULL
;
2068 /* Extract address of start of function. */
2069 idx
= ((idx
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2070 idx
+= exidx_vma
+ i
* 8;
2072 /* Find section containing function and compute section offset. */
2073 sec
= arm_obj_section_from_vma (objfile
, idx
);
2076 idx
-= bfd_get_section_vma (objfile
->obfd
, sec
->the_bfd_section
);
2078 /* Determine address of exception table entry. */
2081 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2083 else if ((val
& 0xff000000) == 0x80000000)
2085 /* Exception table entry embedded in .ARM.exidx
2086 -- must be short form. */
2090 else if (!(val
& 0x80000000))
2092 /* Exception table entry in .ARM.extab. */
2093 addr
= ((val
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2094 addr
+= exidx_vma
+ i
* 8 + 4;
2096 if (addr
>= extab_vma
&& addr
+ 4 <= extab_vma
+ extab_size
)
2098 word
= bfd_h_get_32 (objfile
->obfd
,
2099 extab_data
+ addr
- extab_vma
);
2102 if ((word
& 0xff000000) == 0x80000000)
2107 else if ((word
& 0xff000000) == 0x81000000
2108 || (word
& 0xff000000) == 0x82000000)
2112 n_words
= ((word
>> 16) & 0xff);
2114 else if (!(word
& 0x80000000))
2117 struct obj_section
*pers_sec
;
2118 int gnu_personality
= 0;
2120 /* Custom personality routine. */
2121 pers
= ((word
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2122 pers
= UNMAKE_THUMB_ADDR (pers
+ addr
- 4);
2124 /* Check whether we've got one of the variants of the
2125 GNU personality routines. */
2126 pers_sec
= arm_obj_section_from_vma (objfile
, pers
);
2129 static const char *personality
[] =
2131 "__gcc_personality_v0",
2132 "__gxx_personality_v0",
2133 "__gcj_personality_v0",
2134 "__gnu_objc_personality_v0",
2138 CORE_ADDR pc
= pers
+ obj_section_offset (pers_sec
);
2141 for (k
= 0; personality
[k
]; k
++)
2142 if (lookup_minimal_symbol_by_pc_name
2143 (pc
, personality
[k
], objfile
))
2145 gnu_personality
= 1;
2150 /* If so, the next word contains a word count in the high
2151 byte, followed by the same unwind instructions as the
2152 pre-defined forms. */
2154 && addr
+ 4 <= extab_vma
+ extab_size
)
2156 word
= bfd_h_get_32 (objfile
->obfd
,
2157 extab_data
+ addr
- extab_vma
);
2160 n_words
= ((word
>> 24) & 0xff);
2166 /* Sanity check address. */
2168 if (addr
< extab_vma
|| addr
+ 4 * n_words
> extab_vma
+ extab_size
)
2169 n_words
= n_bytes
= 0;
2171 /* The unwind instructions reside in WORD (only the N_BYTES least
2172 significant bytes are valid), followed by N_WORDS words in the
2173 extab section starting at ADDR. */
2174 if (n_bytes
|| n_words
)
2177 = (gdb_byte
*) obstack_alloc (&objfile
->objfile_obstack
,
2178 n_bytes
+ n_words
* 4 + 1);
2181 *p
++ = (gdb_byte
) ((word
>> (8 * n_bytes
)) & 0xff);
2185 word
= bfd_h_get_32 (objfile
->obfd
,
2186 extab_data
+ addr
- extab_vma
);
2189 *p
++ = (gdb_byte
) ((word
>> 24) & 0xff);
2190 *p
++ = (gdb_byte
) ((word
>> 16) & 0xff);
2191 *p
++ = (gdb_byte
) ((word
>> 8) & 0xff);
2192 *p
++ = (gdb_byte
) (word
& 0xff);
2195 /* Implied "Finish" to terminate the list. */
2199 /* Push entry onto vector. They are guaranteed to always
2200 appear in order of increasing addresses. */
2201 new_exidx_entry
.addr
= idx
;
2202 new_exidx_entry
.entry
= entry
;
2203 VEC_safe_push (arm_exidx_entry_s
,
2204 data
->section_maps
[sec
->the_bfd_section
->index
],
2208 do_cleanups (cleanups
);
2211 /* Search for the exception table entry covering MEMADDR. If one is found,
2212 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2213 set *START to the start of the region covered by this entry. */
2216 arm_find_exidx_entry (CORE_ADDR memaddr
, CORE_ADDR
*start
)
2218 struct obj_section
*sec
;
2220 sec
= find_pc_section (memaddr
);
2223 struct arm_exidx_data
*data
;
2224 VEC(arm_exidx_entry_s
) *map
;
2225 struct arm_exidx_entry map_key
= { memaddr
- obj_section_addr (sec
), 0 };
2228 data
= ((struct arm_exidx_data
*)
2229 objfile_data (sec
->objfile
, arm_exidx_data_key
));
2232 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
2233 if (!VEC_empty (arm_exidx_entry_s
, map
))
2235 struct arm_exidx_entry
*map_sym
;
2237 idx
= VEC_lower_bound (arm_exidx_entry_s
, map
, &map_key
,
2238 arm_compare_exidx_entries
);
2240 /* VEC_lower_bound finds the earliest ordered insertion
2241 point. If the following symbol starts at this exact
2242 address, we use that; otherwise, the preceding
2243 exception table entry covers this address. */
2244 if (idx
< VEC_length (arm_exidx_entry_s
, map
))
2246 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
);
2247 if (map_sym
->addr
== map_key
.addr
)
2250 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2251 return map_sym
->entry
;
2257 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
- 1);
2259 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2260 return map_sym
->entry
;
2269 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2270 instruction list from the ARM exception table entry ENTRY, allocate and
2271 return a prologue cache structure describing how to unwind this frame.
2273 Return NULL if the unwinding instruction list contains a "spare",
2274 "reserved" or "refuse to unwind" instruction as defined in section
2275 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2276 for the ARM Architecture" document. */
2278 static struct arm_prologue_cache
*
2279 arm_exidx_fill_cache (struct frame_info
*this_frame
, gdb_byte
*entry
)
2284 struct arm_prologue_cache
*cache
;
2285 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2286 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2292 /* Whenever we reload SP, we actually have to retrieve its
2293 actual value in the current frame. */
2296 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2298 int reg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2299 vsp
= get_frame_register_unsigned (this_frame
, reg
);
2303 CORE_ADDR addr
= cache
->saved_regs
[ARM_SP_REGNUM
].addr
;
2304 vsp
= get_frame_memory_unsigned (this_frame
, addr
, 4);
2310 /* Decode next unwind instruction. */
2313 if ((insn
& 0xc0) == 0)
2315 int offset
= insn
& 0x3f;
2316 vsp
+= (offset
<< 2) + 4;
2318 else if ((insn
& 0xc0) == 0x40)
2320 int offset
= insn
& 0x3f;
2321 vsp
-= (offset
<< 2) + 4;
2323 else if ((insn
& 0xf0) == 0x80)
2325 int mask
= ((insn
& 0xf) << 8) | *entry
++;
2328 /* The special case of an all-zero mask identifies
2329 "Refuse to unwind". We return NULL to fall back
2330 to the prologue analyzer. */
2334 /* Pop registers r4..r15 under mask. */
2335 for (i
= 0; i
< 12; i
++)
2336 if (mask
& (1 << i
))
2338 cache
->saved_regs
[4 + i
].addr
= vsp
;
2342 /* Special-case popping SP -- we need to reload vsp. */
2343 if (mask
& (1 << (ARM_SP_REGNUM
- 4)))
2346 else if ((insn
& 0xf0) == 0x90)
2348 int reg
= insn
& 0xf;
2350 /* Reserved cases. */
2351 if (reg
== ARM_SP_REGNUM
|| reg
== ARM_PC_REGNUM
)
2354 /* Set SP from another register and mark VSP for reload. */
2355 cache
->saved_regs
[ARM_SP_REGNUM
] = cache
->saved_regs
[reg
];
2358 else if ((insn
& 0xf0) == 0xa0)
2360 int count
= insn
& 0x7;
2361 int pop_lr
= (insn
& 0x8) != 0;
2364 /* Pop r4..r[4+count]. */
2365 for (i
= 0; i
<= count
; i
++)
2367 cache
->saved_regs
[4 + i
].addr
= vsp
;
2371 /* If indicated by flag, pop LR as well. */
2374 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= vsp
;
2378 else if (insn
== 0xb0)
2380 /* We could only have updated PC by popping into it; if so, it
2381 will show up as address. Otherwise, copy LR into PC. */
2382 if (!trad_frame_addr_p (cache
->saved_regs
, ARM_PC_REGNUM
))
2383 cache
->saved_regs
[ARM_PC_REGNUM
]
2384 = cache
->saved_regs
[ARM_LR_REGNUM
];
2389 else if (insn
== 0xb1)
2391 int mask
= *entry
++;
2394 /* All-zero mask and mask >= 16 is "spare". */
2395 if (mask
== 0 || mask
>= 16)
2398 /* Pop r0..r3 under mask. */
2399 for (i
= 0; i
< 4; i
++)
2400 if (mask
& (1 << i
))
2402 cache
->saved_regs
[i
].addr
= vsp
;
2406 else if (insn
== 0xb2)
2408 ULONGEST offset
= 0;
2413 offset
|= (*entry
& 0x7f) << shift
;
2416 while (*entry
++ & 0x80);
2418 vsp
+= 0x204 + (offset
<< 2);
2420 else if (insn
== 0xb3)
2422 int start
= *entry
>> 4;
2423 int count
= (*entry
++) & 0xf;
2426 /* Only registers D0..D15 are valid here. */
2427 if (start
+ count
>= 16)
2430 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2431 for (i
= 0; i
<= count
; i
++)
2433 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2437 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2440 else if ((insn
& 0xf8) == 0xb8)
2442 int count
= insn
& 0x7;
2445 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2446 for (i
= 0; i
<= count
; i
++)
2448 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2452 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2455 else if (insn
== 0xc6)
2457 int start
= *entry
>> 4;
2458 int count
= (*entry
++) & 0xf;
2461 /* Only registers WR0..WR15 are valid. */
2462 if (start
+ count
>= 16)
2465 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2466 for (i
= 0; i
<= count
; i
++)
2468 cache
->saved_regs
[ARM_WR0_REGNUM
+ start
+ i
].addr
= vsp
;
2472 else if (insn
== 0xc7)
2474 int mask
= *entry
++;
2477 /* All-zero mask and mask >= 16 is "spare". */
2478 if (mask
== 0 || mask
>= 16)
2481 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2482 for (i
= 0; i
< 4; i
++)
2483 if (mask
& (1 << i
))
2485 cache
->saved_regs
[ARM_WCGR0_REGNUM
+ i
].addr
= vsp
;
2489 else if ((insn
& 0xf8) == 0xc0)
2491 int count
= insn
& 0x7;
2494 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2495 for (i
= 0; i
<= count
; i
++)
2497 cache
->saved_regs
[ARM_WR0_REGNUM
+ 10 + i
].addr
= vsp
;
2501 else if (insn
== 0xc8)
2503 int start
= *entry
>> 4;
2504 int count
= (*entry
++) & 0xf;
2507 /* Only registers D0..D31 are valid. */
2508 if (start
+ count
>= 16)
2511 /* Pop VFP double-precision registers
2512 D[16+start]..D[16+start+count]. */
2513 for (i
= 0; i
<= count
; i
++)
2515 cache
->saved_regs
[ARM_D0_REGNUM
+ 16 + start
+ i
].addr
= vsp
;
2519 else if (insn
== 0xc9)
2521 int start
= *entry
>> 4;
2522 int count
= (*entry
++) & 0xf;
2525 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2526 for (i
= 0; i
<= count
; i
++)
2528 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2532 else if ((insn
& 0xf8) == 0xd0)
2534 int count
= insn
& 0x7;
2537 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2538 for (i
= 0; i
<= count
; i
++)
2540 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2546 /* Everything else is "spare". */
2551 /* If we restore SP from a register, assume this was the frame register.
2552 Otherwise just fall back to SP as frame register. */
2553 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2554 cache
->framereg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2556 cache
->framereg
= ARM_SP_REGNUM
;
2558 /* Determine offset to previous frame. */
2560 = vsp
- get_frame_register_unsigned (this_frame
, cache
->framereg
);
2562 /* We already got the previous SP. */
2563 cache
->prev_sp
= vsp
;
2568 /* Unwinding via ARM exception table entries. Note that the sniffer
2569 already computes a filled-in prologue cache, which is then used
2570 with the same arm_prologue_this_id and arm_prologue_prev_register
2571 routines also used for prologue-parsing based unwinding. */
2574 arm_exidx_unwind_sniffer (const struct frame_unwind
*self
,
2575 struct frame_info
*this_frame
,
2576 void **this_prologue_cache
)
2578 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2579 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2580 CORE_ADDR addr_in_block
, exidx_region
, func_start
;
2581 struct arm_prologue_cache
*cache
;
2584 /* See if we have an ARM exception table entry covering this address. */
2585 addr_in_block
= get_frame_address_in_block (this_frame
);
2586 entry
= arm_find_exidx_entry (addr_in_block
, &exidx_region
);
2590 /* The ARM exception table does not describe unwind information
2591 for arbitrary PC values, but is guaranteed to be correct only
2592 at call sites. We have to decide here whether we want to use
2593 ARM exception table information for this frame, or fall back
2594 to using prologue parsing. (Note that if we have DWARF CFI,
2595 this sniffer isn't even called -- CFI is always preferred.)
2597 Before we make this decision, however, we check whether we
2598 actually have *symbol* information for the current frame.
2599 If not, prologue parsing would not work anyway, so we might
2600 as well use the exception table and hope for the best. */
2601 if (find_pc_partial_function (addr_in_block
, NULL
, &func_start
, NULL
))
2605 /* If the next frame is "normal", we are at a call site in this
2606 frame, so exception information is guaranteed to be valid. */
2607 if (get_next_frame (this_frame
)
2608 && get_frame_type (get_next_frame (this_frame
)) == NORMAL_FRAME
)
2611 /* We also assume exception information is valid if we're currently
2612 blocked in a system call. The system library is supposed to
2613 ensure this, so that e.g. pthread cancellation works. */
2614 if (arm_frame_is_thumb (this_frame
))
2618 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 2, 2,
2619 byte_order_for_code
, &insn
)
2620 && (insn
& 0xff00) == 0xdf00 /* svc */)
2627 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 4, 4,
2628 byte_order_for_code
, &insn
)
2629 && (insn
& 0x0f000000) == 0x0f000000 /* svc */)
2633 /* Bail out if we don't know that exception information is valid. */
2637 /* The ARM exception index does not mark the *end* of the region
2638 covered by the entry, and some functions will not have any entry.
2639 To correctly recognize the end of the covered region, the linker
2640 should have inserted dummy records with a CANTUNWIND marker.
2642 Unfortunately, current versions of GNU ld do not reliably do
2643 this, and thus we may have found an incorrect entry above.
2644 As a (temporary) sanity check, we only use the entry if it
2645 lies *within* the bounds of the function. Note that this check
2646 might reject perfectly valid entries that just happen to cover
2647 multiple functions; therefore this check ought to be removed
2648 once the linker is fixed. */
2649 if (func_start
> exidx_region
)
2653 /* Decode the list of unwinding instructions into a prologue cache.
2654 Note that this may fail due to e.g. a "refuse to unwind" code. */
2655 cache
= arm_exidx_fill_cache (this_frame
, entry
);
2659 *this_prologue_cache
= cache
;
2663 struct frame_unwind arm_exidx_unwind
= {
2665 default_frame_unwind_stop_reason
,
2666 arm_prologue_this_id
,
2667 arm_prologue_prev_register
,
2669 arm_exidx_unwind_sniffer
2672 static struct arm_prologue_cache
*
2673 arm_make_epilogue_frame_cache (struct frame_info
*this_frame
)
2675 struct arm_prologue_cache
*cache
;
2678 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2679 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2681 /* Still rely on the offset calculated from prologue. */
2682 arm_scan_prologue (this_frame
, cache
);
2684 /* Since we are in epilogue, the SP has been restored. */
2685 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2687 /* Calculate actual addresses of saved registers using offsets
2688 determined by arm_scan_prologue. */
2689 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
2690 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
2691 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
2696 /* Implementation of function hook 'this_id' in
2697 'struct frame_uwnind' for epilogue unwinder. */
2700 arm_epilogue_frame_this_id (struct frame_info
*this_frame
,
2702 struct frame_id
*this_id
)
2704 struct arm_prologue_cache
*cache
;
2707 if (*this_cache
== NULL
)
2708 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2709 cache
= (struct arm_prologue_cache
*) *this_cache
;
2711 /* Use function start address as part of the frame ID. If we cannot
2712 identify the start address (due to missing symbol information),
2713 fall back to just using the current PC. */
2714 pc
= get_frame_pc (this_frame
);
2715 func
= get_frame_func (this_frame
);
2719 (*this_id
) = frame_id_build (cache
->prev_sp
, pc
);
2722 /* Implementation of function hook 'prev_register' in
2723 'struct frame_uwnind' for epilogue unwinder. */
2725 static struct value
*
2726 arm_epilogue_frame_prev_register (struct frame_info
*this_frame
,
2727 void **this_cache
, int regnum
)
2729 if (*this_cache
== NULL
)
2730 *this_cache
= arm_make_epilogue_frame_cache (this_frame
);
2732 return arm_prologue_prev_register (this_frame
, this_cache
, regnum
);
2735 static int arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
,
2737 static int thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
,
2740 /* Implementation of function hook 'sniffer' in
2741 'struct frame_uwnind' for epilogue unwinder. */
2744 arm_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2745 struct frame_info
*this_frame
,
2746 void **this_prologue_cache
)
2748 if (frame_relative_level (this_frame
) == 0)
2750 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2751 CORE_ADDR pc
= get_frame_pc (this_frame
);
2753 if (arm_frame_is_thumb (this_frame
))
2754 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
2756 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
2762 /* Frame unwinder from epilogue. */
2764 static const struct frame_unwind arm_epilogue_frame_unwind
=
2767 default_frame_unwind_stop_reason
,
2768 arm_epilogue_frame_this_id
,
2769 arm_epilogue_frame_prev_register
,
2771 arm_epilogue_frame_sniffer
,
2774 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2775 trampoline, return the target PC. Otherwise return 0.
2777 void call0a (char c, short s, int i, long l) {}
2781 (*pointer_to_call0a) (c, s, i, l);
2784 Instead of calling a stub library function _call_via_xx (xx is
2785 the register name), GCC may inline the trampoline in the object
2786 file as below (register r2 has the address of call0a).
2789 .type main, %function
2798 The trampoline 'bx r2' doesn't belong to main. */
2801 arm_skip_bx_reg (struct frame_info
*frame
, CORE_ADDR pc
)
2803 /* The heuristics of recognizing such trampoline is that FRAME is
2804 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2805 if (arm_frame_is_thumb (frame
))
2809 if (target_read_memory (pc
, buf
, 2) == 0)
2811 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2812 enum bfd_endian byte_order_for_code
2813 = gdbarch_byte_order_for_code (gdbarch
);
2815 = extract_unsigned_integer (buf
, 2, byte_order_for_code
);
2817 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
2820 = get_frame_register_unsigned (frame
, bits (insn
, 3, 6));
2822 /* Clear the LSB so that gdb core sets step-resume
2823 breakpoint at the right address. */
2824 return UNMAKE_THUMB_ADDR (dest
);
2832 static struct arm_prologue_cache
*
2833 arm_make_stub_cache (struct frame_info
*this_frame
)
2835 struct arm_prologue_cache
*cache
;
2837 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2838 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2840 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2845 /* Our frame ID for a stub frame is the current SP and LR. */
2848 arm_stub_this_id (struct frame_info
*this_frame
,
2850 struct frame_id
*this_id
)
2852 struct arm_prologue_cache
*cache
;
2854 if (*this_cache
== NULL
)
2855 *this_cache
= arm_make_stub_cache (this_frame
);
2856 cache
= (struct arm_prologue_cache
*) *this_cache
;
2858 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
2862 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
2863 struct frame_info
*this_frame
,
2864 void **this_prologue_cache
)
2866 CORE_ADDR addr_in_block
;
2868 CORE_ADDR pc
, start_addr
;
2871 addr_in_block
= get_frame_address_in_block (this_frame
);
2872 pc
= get_frame_pc (this_frame
);
2873 if (in_plt_section (addr_in_block
)
2874 /* We also use the stub winder if the target memory is unreadable
2875 to avoid having the prologue unwinder trying to read it. */
2876 || target_read_memory (pc
, dummy
, 4) != 0)
2879 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0
2880 && arm_skip_bx_reg (this_frame
, pc
) != 0)
2886 struct frame_unwind arm_stub_unwind
= {
2888 default_frame_unwind_stop_reason
,
2890 arm_prologue_prev_register
,
2892 arm_stub_unwind_sniffer
2895 /* Put here the code to store, into CACHE->saved_regs, the addresses
2896 of the saved registers of frame described by THIS_FRAME. CACHE is
2899 static struct arm_prologue_cache
*
2900 arm_m_exception_cache (struct frame_info
*this_frame
)
2902 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2903 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2904 struct arm_prologue_cache
*cache
;
2905 CORE_ADDR unwound_sp
;
2908 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2909 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2911 unwound_sp
= get_frame_register_unsigned (this_frame
,
2914 /* The hardware saves eight 32-bit words, comprising xPSR,
2915 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
2916 "B1.5.6 Exception entry behavior" in
2917 "ARMv7-M Architecture Reference Manual". */
2918 cache
->saved_regs
[0].addr
= unwound_sp
;
2919 cache
->saved_regs
[1].addr
= unwound_sp
+ 4;
2920 cache
->saved_regs
[2].addr
= unwound_sp
+ 8;
2921 cache
->saved_regs
[3].addr
= unwound_sp
+ 12;
2922 cache
->saved_regs
[12].addr
= unwound_sp
+ 16;
2923 cache
->saved_regs
[14].addr
= unwound_sp
+ 20;
2924 cache
->saved_regs
[15].addr
= unwound_sp
+ 24;
2925 cache
->saved_regs
[ARM_PS_REGNUM
].addr
= unwound_sp
+ 28;
2927 /* If bit 9 of the saved xPSR is set, then there is a four-byte
2928 aligner between the top of the 32-byte stack frame and the
2929 previous context's stack pointer. */
2930 cache
->prev_sp
= unwound_sp
+ 32;
2931 if (safe_read_memory_integer (unwound_sp
+ 28, 4, byte_order
, &xpsr
)
2932 && (xpsr
& (1 << 9)) != 0)
2933 cache
->prev_sp
+= 4;
2938 /* Implementation of function hook 'this_id' in
2939 'struct frame_uwnind'. */
2942 arm_m_exception_this_id (struct frame_info
*this_frame
,
2944 struct frame_id
*this_id
)
2946 struct arm_prologue_cache
*cache
;
2948 if (*this_cache
== NULL
)
2949 *this_cache
= arm_m_exception_cache (this_frame
);
2950 cache
= (struct arm_prologue_cache
*) *this_cache
;
2952 /* Our frame ID for a stub frame is the current SP and LR. */
2953 *this_id
= frame_id_build (cache
->prev_sp
,
2954 get_frame_pc (this_frame
));
2957 /* Implementation of function hook 'prev_register' in
2958 'struct frame_uwnind'. */
2960 static struct value
*
2961 arm_m_exception_prev_register (struct frame_info
*this_frame
,
2965 struct arm_prologue_cache
*cache
;
2967 if (*this_cache
== NULL
)
2968 *this_cache
= arm_m_exception_cache (this_frame
);
2969 cache
= (struct arm_prologue_cache
*) *this_cache
;
2971 /* The value was already reconstructed into PREV_SP. */
2972 if (prev_regnum
== ARM_SP_REGNUM
)
2973 return frame_unwind_got_constant (this_frame
, prev_regnum
,
2976 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
2980 /* Implementation of function hook 'sniffer' in
2981 'struct frame_uwnind'. */
2984 arm_m_exception_unwind_sniffer (const struct frame_unwind
*self
,
2985 struct frame_info
*this_frame
,
2986 void **this_prologue_cache
)
2988 CORE_ADDR this_pc
= get_frame_pc (this_frame
);
2990 /* No need to check is_m; this sniffer is only registered for
2991 M-profile architectures. */
2993 /* Exception frames return to one of these magic PCs. Other values
2994 are not defined as of v7-M. See details in "B1.5.8 Exception
2995 return behavior" in "ARMv7-M Architecture Reference Manual". */
2996 if (this_pc
== 0xfffffff1 || this_pc
== 0xfffffff9
2997 || this_pc
== 0xfffffffd)
3003 /* Frame unwinder for M-profile exceptions. */
3005 struct frame_unwind arm_m_exception_unwind
=
3008 default_frame_unwind_stop_reason
,
3009 arm_m_exception_this_id
,
3010 arm_m_exception_prev_register
,
3012 arm_m_exception_unwind_sniffer
3016 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
3018 struct arm_prologue_cache
*cache
;
3020 if (*this_cache
== NULL
)
3021 *this_cache
= arm_make_prologue_cache (this_frame
);
3022 cache
= (struct arm_prologue_cache
*) *this_cache
;
3024 return cache
->prev_sp
- cache
->framesize
;
3027 struct frame_base arm_normal_base
= {
3028 &arm_prologue_unwind
,
3029 arm_normal_frame_base
,
3030 arm_normal_frame_base
,
3031 arm_normal_frame_base
3034 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3035 dummy frame. The frame ID's base needs to match the TOS value
3036 saved by save_dummy_frame_tos() and returned from
3037 arm_push_dummy_call, and the PC needs to match the dummy frame's
3040 static struct frame_id
3041 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3043 return frame_id_build (get_frame_register_unsigned (this_frame
,
3045 get_frame_pc (this_frame
));
3048 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3049 be used to construct the previous frame's ID, after looking up the
3050 containing function). */
3053 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3056 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
3057 return arm_addr_bits_remove (gdbarch
, pc
);
3061 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3063 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
3066 static struct value
*
3067 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
3070 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
3072 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
3077 /* The PC is normally copied from the return column, which
3078 describes saves of LR. However, that version may have an
3079 extra bit set to indicate Thumb state. The bit is not
3081 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3082 return frame_unwind_got_constant (this_frame
, regnum
,
3083 arm_addr_bits_remove (gdbarch
, lr
));
3086 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3087 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
3088 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3089 if (IS_THUMB_ADDR (lr
))
3093 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
3096 internal_error (__FILE__
, __LINE__
,
3097 _("Unexpected register %d"), regnum
);
3102 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3103 struct dwarf2_frame_state_reg
*reg
,
3104 struct frame_info
*this_frame
)
3110 reg
->how
= DWARF2_FRAME_REG_FN
;
3111 reg
->loc
.fn
= arm_dwarf2_prev_register
;
3114 reg
->how
= DWARF2_FRAME_REG_CFA
;
3119 /* Implement the stack_frame_destroyed_p gdbarch method. */
3122 thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3124 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3125 unsigned int insn
, insn2
;
3126 int found_return
= 0, found_stack_adjust
= 0;
3127 CORE_ADDR func_start
, func_end
;
3131 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3134 /* The epilogue is a sequence of instructions along the following lines:
3136 - add stack frame size to SP or FP
3137 - [if frame pointer used] restore SP from FP
3138 - restore registers from SP [may include PC]
3139 - a return-type instruction [if PC wasn't already restored]
3141 In a first pass, we scan forward from the current PC and verify the
3142 instructions we find as compatible with this sequence, ending in a
3145 However, this is not sufficient to distinguish indirect function calls
3146 within a function from indirect tail calls in the epilogue in some cases.
3147 Therefore, if we didn't already find any SP-changing instruction during
3148 forward scan, we add a backward scanning heuristic to ensure we actually
3149 are in the epilogue. */
3152 while (scan_pc
< func_end
&& !found_return
)
3154 if (target_read_memory (scan_pc
, buf
, 2))
3158 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3160 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3162 else if (insn
== 0x46f7) /* mov pc, lr */
3164 else if (thumb_instruction_restores_sp (insn
))
3166 if ((insn
& 0xff00) == 0xbd00) /* pop <registers, PC> */
3169 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instruction */
3171 if (target_read_memory (scan_pc
, buf
, 2))
3175 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3177 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3179 if (insn2
& 0x8000) /* <registers> include PC. */
3182 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3183 && (insn2
& 0x0fff) == 0x0b04)
3185 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
3188 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3189 && (insn2
& 0x0e00) == 0x0a00)
3201 /* Since any instruction in the epilogue sequence, with the possible
3202 exception of return itself, updates the stack pointer, we need to
3203 scan backwards for at most one instruction. Try either a 16-bit or
3204 a 32-bit instruction. This is just a heuristic, so we do not worry
3205 too much about false positives. */
3207 if (pc
- 4 < func_start
)
3209 if (target_read_memory (pc
- 4, buf
, 4))
3212 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3213 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
3215 if (thumb_instruction_restores_sp (insn2
))
3216 found_stack_adjust
= 1;
3217 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3218 found_stack_adjust
= 1;
3219 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3220 && (insn2
& 0x0fff) == 0x0b04)
3221 found_stack_adjust
= 1;
3222 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3223 && (insn2
& 0x0e00) == 0x0a00)
3224 found_stack_adjust
= 1;
3226 return found_stack_adjust
;
3230 arm_stack_frame_destroyed_p_1 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3232 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3235 CORE_ADDR func_start
, func_end
;
3237 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3240 /* We are in the epilogue if the previous instruction was a stack
3241 adjustment and the next instruction is a possible return (bx, mov
3242 pc, or pop). We could have to scan backwards to find the stack
3243 adjustment, or forwards to find the return, but this is a decent
3244 approximation. First scan forwards. */
3247 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3248 if (bits (insn
, 28, 31) != INST_NV
)
3250 if ((insn
& 0x0ffffff0) == 0x012fff10)
3253 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
3256 else if ((insn
& 0x0fff0000) == 0x08bd0000
3257 && (insn
& 0x0000c000) != 0)
3258 /* POP (LDMIA), including PC or LR. */
3265 /* Scan backwards. This is just a heuristic, so do not worry about
3266 false positives from mode changes. */
3268 if (pc
< func_start
+ 4)
3271 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
3272 if (arm_instruction_restores_sp (insn
))
3278 /* Implement the stack_frame_destroyed_p gdbarch method. */
3281 arm_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3283 if (arm_pc_is_thumb (gdbarch
, pc
))
3284 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
3286 return arm_stack_frame_destroyed_p_1 (gdbarch
, pc
);
3289 /* When arguments must be pushed onto the stack, they go on in reverse
3290 order. The code below implements a FILO (stack) to do this. */
3295 struct stack_item
*prev
;
3299 static struct stack_item
*
3300 push_stack_item (struct stack_item
*prev
, const gdb_byte
*contents
, int len
)
3302 struct stack_item
*si
;
3303 si
= XNEW (struct stack_item
);
3304 si
->data
= (gdb_byte
*) xmalloc (len
);
3307 memcpy (si
->data
, contents
, len
);
3311 static struct stack_item
*
3312 pop_stack_item (struct stack_item
*si
)
3314 struct stack_item
*dead
= si
;
3322 /* Return the alignment (in bytes) of the given type. */
3325 arm_type_align (struct type
*t
)
3331 t
= check_typedef (t
);
3332 switch (TYPE_CODE (t
))
3335 /* Should never happen. */
3336 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
3340 case TYPE_CODE_ENUM
:
3344 case TYPE_CODE_RANGE
:
3346 case TYPE_CODE_CHAR
:
3347 case TYPE_CODE_BOOL
:
3348 return TYPE_LENGTH (t
);
3350 case TYPE_CODE_ARRAY
:
3351 if (TYPE_VECTOR (t
))
3353 /* Use the natural alignment for vector types (the same for
3354 scalar type), but the maximum alignment is 64-bit. */
3355 if (TYPE_LENGTH (t
) > 8)
3358 return TYPE_LENGTH (t
);
3361 return arm_type_align (TYPE_TARGET_TYPE (t
));
3362 case TYPE_CODE_COMPLEX
:
3363 return arm_type_align (TYPE_TARGET_TYPE (t
));
3365 case TYPE_CODE_STRUCT
:
3366 case TYPE_CODE_UNION
:
3368 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
3370 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
3378 /* Possible base types for a candidate for passing and returning in
3381 enum arm_vfp_cprc_base_type
3390 /* The length of one element of base type B. */
3393 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
3397 case VFP_CPRC_SINGLE
:
3399 case VFP_CPRC_DOUBLE
:
3401 case VFP_CPRC_VEC64
:
3403 case VFP_CPRC_VEC128
:
3406 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3411 /* The character ('s', 'd' or 'q') for the type of VFP register used
3412 for passing base type B. */
3415 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
3419 case VFP_CPRC_SINGLE
:
3421 case VFP_CPRC_DOUBLE
:
3423 case VFP_CPRC_VEC64
:
3425 case VFP_CPRC_VEC128
:
3428 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3433 /* Determine whether T may be part of a candidate for passing and
3434 returning in VFP registers, ignoring the limit on the total number
3435 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3436 classification of the first valid component found; if it is not
3437 VFP_CPRC_UNKNOWN, all components must have the same classification
3438 as *BASE_TYPE. If it is found that T contains a type not permitted
3439 for passing and returning in VFP registers, a type differently
3440 classified from *BASE_TYPE, or two types differently classified
3441 from each other, return -1, otherwise return the total number of
3442 base-type elements found (possibly 0 in an empty structure or
3443 array). Vector types are not currently supported, matching the
3444 generic AAPCS support. */
3447 arm_vfp_cprc_sub_candidate (struct type
*t
,
3448 enum arm_vfp_cprc_base_type
*base_type
)
3450 t
= check_typedef (t
);
3451 switch (TYPE_CODE (t
))
3454 switch (TYPE_LENGTH (t
))
3457 if (*base_type
== VFP_CPRC_UNKNOWN
)
3458 *base_type
= VFP_CPRC_SINGLE
;
3459 else if (*base_type
!= VFP_CPRC_SINGLE
)
3464 if (*base_type
== VFP_CPRC_UNKNOWN
)
3465 *base_type
= VFP_CPRC_DOUBLE
;
3466 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3475 case TYPE_CODE_COMPLEX
:
3476 /* Arguments of complex T where T is one of the types float or
3477 double get treated as if they are implemented as:
3486 switch (TYPE_LENGTH (t
))
3489 if (*base_type
== VFP_CPRC_UNKNOWN
)
3490 *base_type
= VFP_CPRC_SINGLE
;
3491 else if (*base_type
!= VFP_CPRC_SINGLE
)
3496 if (*base_type
== VFP_CPRC_UNKNOWN
)
3497 *base_type
= VFP_CPRC_DOUBLE
;
3498 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3507 case TYPE_CODE_ARRAY
:
3509 if (TYPE_VECTOR (t
))
3511 /* A 64-bit or 128-bit containerized vector type are VFP
3513 switch (TYPE_LENGTH (t
))
3516 if (*base_type
== VFP_CPRC_UNKNOWN
)
3517 *base_type
= VFP_CPRC_VEC64
;
3520 if (*base_type
== VFP_CPRC_UNKNOWN
)
3521 *base_type
= VFP_CPRC_VEC128
;
3532 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
),
3536 if (TYPE_LENGTH (t
) == 0)
3538 gdb_assert (count
== 0);
3541 else if (count
== 0)
3543 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3544 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
3545 return TYPE_LENGTH (t
) / unitlen
;
3550 case TYPE_CODE_STRUCT
:
3555 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3559 if (!field_is_static (&TYPE_FIELD (t
, i
)))
3560 sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3562 if (sub_count
== -1)
3566 if (TYPE_LENGTH (t
) == 0)
3568 gdb_assert (count
== 0);
3571 else if (count
== 0)
3573 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3574 if (TYPE_LENGTH (t
) != unitlen
* count
)
3579 case TYPE_CODE_UNION
:
3584 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3586 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3588 if (sub_count
== -1)
3590 count
= (count
> sub_count
? count
: sub_count
);
3592 if (TYPE_LENGTH (t
) == 0)
3594 gdb_assert (count
== 0);
3597 else if (count
== 0)
3599 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3600 if (TYPE_LENGTH (t
) != unitlen
* count
)
3612 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3613 if passed to or returned from a non-variadic function with the VFP
3614 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3615 *BASE_TYPE to the base type for T and *COUNT to the number of
3616 elements of that base type before returning. */
3619 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
3622 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
3623 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
3624 if (c
<= 0 || c
> 4)
3631 /* Return 1 if the VFP ABI should be used for passing arguments to and
3632 returning values from a function of type FUNC_TYPE, 0
3636 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
3638 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3639 /* Variadic functions always use the base ABI. Assume that functions
3640 without debug info are not variadic. */
3641 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
3643 /* The VFP ABI is only supported as a variant of AAPCS. */
3644 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
3646 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
3649 /* We currently only support passing parameters in integer registers, which
3650 conforms with GCC's default model, and VFP argument passing following
3651 the VFP variant of AAPCS. Several other variants exist and
3652 we should probably support some of them based on the selected ABI. */
3655 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3656 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3657 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3658 CORE_ADDR struct_addr
)
3660 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3664 struct stack_item
*si
= NULL
;
3667 unsigned vfp_regs_free
= (1 << 16) - 1;
3669 /* Determine the type of this function and whether the VFP ABI
3671 ftype
= check_typedef (value_type (function
));
3672 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
3673 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
3674 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
3676 /* Set the return address. For the ARM, the return breakpoint is
3677 always at BP_ADDR. */
3678 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
3680 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
3682 /* Walk through the list of args and determine how large a temporary
3683 stack is required. Need to take care here as structs may be
3684 passed on the stack, and we have to push them. */
3687 argreg
= ARM_A1_REGNUM
;
3690 /* The struct_return pointer occupies the first parameter
3691 passing register. */
3695 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
3696 gdbarch_register_name (gdbarch
, argreg
),
3697 paddress (gdbarch
, struct_addr
));
3698 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
3702 for (argnum
= 0; argnum
< nargs
; argnum
++)
3705 struct type
*arg_type
;
3706 struct type
*target_type
;
3707 enum type_code typecode
;
3708 const bfd_byte
*val
;
3710 enum arm_vfp_cprc_base_type vfp_base_type
;
3712 int may_use_core_reg
= 1;
3714 arg_type
= check_typedef (value_type (args
[argnum
]));
3715 len
= TYPE_LENGTH (arg_type
);
3716 target_type
= TYPE_TARGET_TYPE (arg_type
);
3717 typecode
= TYPE_CODE (arg_type
);
3718 val
= value_contents (args
[argnum
]);
3720 align
= arm_type_align (arg_type
);
3721 /* Round alignment up to a whole number of words. */
3722 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
3723 /* Different ABIs have different maximum alignments. */
3724 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
3726 /* The APCS ABI only requires word alignment. */
3727 align
= INT_REGISTER_SIZE
;
3731 /* The AAPCS requires at most doubleword alignment. */
3732 if (align
> INT_REGISTER_SIZE
* 2)
3733 align
= INT_REGISTER_SIZE
* 2;
3737 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
3745 /* Because this is a CPRC it cannot go in a core register or
3746 cause a core register to be skipped for alignment.
3747 Either it goes in VFP registers and the rest of this loop
3748 iteration is skipped for this argument, or it goes on the
3749 stack (and the stack alignment code is correct for this
3751 may_use_core_reg
= 0;
3753 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
3754 shift
= unit_length
/ 4;
3755 mask
= (1 << (shift
* vfp_base_count
)) - 1;
3756 for (regno
= 0; regno
< 16; regno
+= shift
)
3757 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
3766 vfp_regs_free
&= ~(mask
<< regno
);
3767 reg_scaled
= regno
/ shift
;
3768 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
3769 for (i
= 0; i
< vfp_base_count
; i
++)
3773 if (reg_char
== 'q')
3774 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
3775 val
+ i
* unit_length
);
3778 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d",
3779 reg_char
, reg_scaled
+ i
);
3780 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3782 regcache_cooked_write (regcache
, regnum
,
3783 val
+ i
* unit_length
);
3790 /* This CPRC could not go in VFP registers, so all VFP
3791 registers are now marked as used. */
3796 /* Push stack padding for dowubleword alignment. */
3797 if (nstack
& (align
- 1))
3799 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3800 nstack
+= INT_REGISTER_SIZE
;
3803 /* Doubleword aligned quantities must go in even register pairs. */
3804 if (may_use_core_reg
3805 && argreg
<= ARM_LAST_ARG_REGNUM
3806 && align
> INT_REGISTER_SIZE
3810 /* If the argument is a pointer to a function, and it is a
3811 Thumb function, create a LOCAL copy of the value and set
3812 the THUMB bit in it. */
3813 if (TYPE_CODE_PTR
== typecode
3814 && target_type
!= NULL
3815 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
3817 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
3818 if (arm_pc_is_thumb (gdbarch
, regval
))
3820 bfd_byte
*copy
= (bfd_byte
*) alloca (len
);
3821 store_unsigned_integer (copy
, len
, byte_order
,
3822 MAKE_THUMB_ADDR (regval
));
3827 /* Copy the argument to general registers or the stack in
3828 register-sized pieces. Large arguments are split between
3829 registers and stack. */
3832 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
3834 = extract_unsigned_integer (val
, partial_len
, byte_order
);
3836 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
3838 /* The argument is being passed in a general purpose
3840 if (byte_order
== BFD_ENDIAN_BIG
)
3841 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
3843 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
3845 gdbarch_register_name
3847 phex (regval
, INT_REGISTER_SIZE
));
3848 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3853 gdb_byte buf
[INT_REGISTER_SIZE
];
3855 memset (buf
, 0, sizeof (buf
));
3856 store_unsigned_integer (buf
, partial_len
, byte_order
, regval
);
3858 /* Push the arguments onto the stack. */
3860 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
3862 si
= push_stack_item (si
, buf
, INT_REGISTER_SIZE
);
3863 nstack
+= INT_REGISTER_SIZE
;
3870 /* If we have an odd number of words to push, then decrement the stack
3871 by one word now, so first stack argument will be dword aligned. */
3878 write_memory (sp
, si
->data
, si
->len
);
3879 si
= pop_stack_item (si
);
3882 /* Finally, update teh SP register. */
3883 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
3889 /* Always align the frame to an 8-byte boundary. This is required on
3890 some platforms and harmless on the rest. */
3893 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3895 /* Align the stack to eight bytes. */
3896 return sp
& ~ (CORE_ADDR
) 7;
3900 print_fpu_flags (struct ui_file
*file
, int flags
)
3902 if (flags
& (1 << 0))
3903 fputs_filtered ("IVO ", file
);
3904 if (flags
& (1 << 1))
3905 fputs_filtered ("DVZ ", file
);
3906 if (flags
& (1 << 2))
3907 fputs_filtered ("OFL ", file
);
3908 if (flags
& (1 << 3))
3909 fputs_filtered ("UFL ", file
);
3910 if (flags
& (1 << 4))
3911 fputs_filtered ("INX ", file
);
3912 fputc_filtered ('\n', file
);
3915 /* Print interesting information about the floating point processor
3916 (if present) or emulator. */
3918 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
3919 struct frame_info
*frame
, const char *args
)
3921 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
3924 type
= (status
>> 24) & 127;
3925 if (status
& (1 << 31))
3926 fprintf_filtered (file
, _("Hardware FPU type %d\n"), type
);
3928 fprintf_filtered (file
, _("Software FPU type %d\n"), type
);
3929 /* i18n: [floating point unit] mask */
3930 fputs_filtered (_("mask: "), file
);
3931 print_fpu_flags (file
, status
>> 16);
3932 /* i18n: [floating point unit] flags */
3933 fputs_filtered (_("flags: "), file
);
3934 print_fpu_flags (file
, status
);
3937 /* Construct the ARM extended floating point type. */
3938 static struct type
*
3939 arm_ext_type (struct gdbarch
*gdbarch
)
3941 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3943 if (!tdep
->arm_ext_type
)
3945 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
3946 floatformats_arm_ext
);
3948 return tdep
->arm_ext_type
;
3951 static struct type
*
3952 arm_neon_double_type (struct gdbarch
*gdbarch
)
3954 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3956 if (tdep
->neon_double_type
== NULL
)
3958 struct type
*t
, *elem
;
3960 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
3962 elem
= builtin_type (gdbarch
)->builtin_uint8
;
3963 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
3964 elem
= builtin_type (gdbarch
)->builtin_uint16
;
3965 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
3966 elem
= builtin_type (gdbarch
)->builtin_uint32
;
3967 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
3968 elem
= builtin_type (gdbarch
)->builtin_uint64
;
3969 append_composite_type_field (t
, "u64", elem
);
3970 elem
= builtin_type (gdbarch
)->builtin_float
;
3971 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
3972 elem
= builtin_type (gdbarch
)->builtin_double
;
3973 append_composite_type_field (t
, "f64", elem
);
3975 TYPE_VECTOR (t
) = 1;
3976 TYPE_NAME (t
) = "neon_d";
3977 tdep
->neon_double_type
= t
;
3980 return tdep
->neon_double_type
;
3983 /* FIXME: The vector types are not correctly ordered on big-endian
3984 targets. Just as s0 is the low bits of d0, d0[0] is also the low
3985 bits of d0 - regardless of what unit size is being held in d0. So
3986 the offset of the first uint8 in d0 is 7, but the offset of the
3987 first float is 4. This code works as-is for little-endian
3990 static struct type
*
3991 arm_neon_quad_type (struct gdbarch
*gdbarch
)
3993 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3995 if (tdep
->neon_quad_type
== NULL
)
3997 struct type
*t
, *elem
;
3999 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
4001 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4002 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
4003 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4004 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
4005 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4006 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
4007 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4008 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
4009 elem
= builtin_type (gdbarch
)->builtin_float
;
4010 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
4011 elem
= builtin_type (gdbarch
)->builtin_double
;
4012 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
4014 TYPE_VECTOR (t
) = 1;
4015 TYPE_NAME (t
) = "neon_q";
4016 tdep
->neon_quad_type
= t
;
4019 return tdep
->neon_quad_type
;
4022 /* Return the GDB type object for the "standard" data type of data in
4025 static struct type
*
4026 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
4028 int num_regs
= gdbarch_num_regs (gdbarch
);
4030 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
4031 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
4032 return builtin_type (gdbarch
)->builtin_float
;
4034 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
4035 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
4036 return arm_neon_quad_type (gdbarch
);
4038 /* If the target description has register information, we are only
4039 in this function so that we can override the types of
4040 double-precision registers for NEON. */
4041 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
4043 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
4045 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
4046 && TYPE_CODE (t
) == TYPE_CODE_FLT
4047 && gdbarch_tdep (gdbarch
)->have_neon
)
4048 return arm_neon_double_type (gdbarch
);
4053 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
4055 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
4056 return builtin_type (gdbarch
)->builtin_void
;
4058 return arm_ext_type (gdbarch
);
4060 else if (regnum
== ARM_SP_REGNUM
)
4061 return builtin_type (gdbarch
)->builtin_data_ptr
;
4062 else if (regnum
== ARM_PC_REGNUM
)
4063 return builtin_type (gdbarch
)->builtin_func_ptr
;
4064 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
4065 /* These registers are only supported on targets which supply
4066 an XML description. */
4067 return builtin_type (gdbarch
)->builtin_int0
;
4069 return builtin_type (gdbarch
)->builtin_uint32
;
4072 /* Map a DWARF register REGNUM onto the appropriate GDB register
4076 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
4078 /* Core integer regs. */
4079 if (reg
>= 0 && reg
<= 15)
4082 /* Legacy FPA encoding. These were once used in a way which
4083 overlapped with VFP register numbering, so their use is
4084 discouraged, but GDB doesn't support the ARM toolchain
4085 which used them for VFP. */
4086 if (reg
>= 16 && reg
<= 23)
4087 return ARM_F0_REGNUM
+ reg
- 16;
4089 /* New assignments for the FPA registers. */
4090 if (reg
>= 96 && reg
<= 103)
4091 return ARM_F0_REGNUM
+ reg
- 96;
4093 /* WMMX register assignments. */
4094 if (reg
>= 104 && reg
<= 111)
4095 return ARM_WCGR0_REGNUM
+ reg
- 104;
4097 if (reg
>= 112 && reg
<= 127)
4098 return ARM_WR0_REGNUM
+ reg
- 112;
4100 if (reg
>= 192 && reg
<= 199)
4101 return ARM_WC0_REGNUM
+ reg
- 192;
4103 /* VFP v2 registers. A double precision value is actually
4104 in d1 rather than s2, but the ABI only defines numbering
4105 for the single precision registers. This will "just work"
4106 in GDB for little endian targets (we'll read eight bytes,
4107 starting in s0 and then progressing to s1), but will be
4108 reversed on big endian targets with VFP. This won't
4109 be a problem for the new Neon quad registers; you're supposed
4110 to use DW_OP_piece for those. */
4111 if (reg
>= 64 && reg
<= 95)
4115 xsnprintf (name_buf
, sizeof (name_buf
), "s%d", reg
- 64);
4116 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4120 /* VFP v3 / Neon registers. This range is also used for VFP v2
4121 registers, except that it now describes d0 instead of s0. */
4122 if (reg
>= 256 && reg
<= 287)
4126 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", reg
- 256);
4127 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4134 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4136 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
4139 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
4141 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
4142 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
4144 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
4145 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
4147 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
4148 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
4150 if (reg
< NUM_GREGS
)
4151 return SIM_ARM_R0_REGNUM
+ reg
;
4154 if (reg
< NUM_FREGS
)
4155 return SIM_ARM_FP0_REGNUM
+ reg
;
4158 if (reg
< NUM_SREGS
)
4159 return SIM_ARM_FPS_REGNUM
+ reg
;
4162 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
4165 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4166 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4167 It is thought that this is is the floating-point register format on
4168 little-endian systems. */
4171 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
4172 void *dbl
, int endianess
)
4176 if (endianess
== BFD_ENDIAN_BIG
)
4177 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
4179 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4181 floatformat_from_doublest (fmt
, &d
, dbl
);
4185 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
4190 floatformat_to_doublest (fmt
, ptr
, &d
);
4191 if (endianess
== BFD_ENDIAN_BIG
)
4192 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
4194 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4198 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
4199 of the appropriate mode (as encoded in the PC value), even if this
4200 differs from what would be expected according to the symbol tables. */
4203 arm_insert_single_step_breakpoint (struct gdbarch
*gdbarch
,
4204 struct address_space
*aspace
,
4207 struct cleanup
*old_chain
4208 = make_cleanup_restore_integer (&arm_override_mode
);
4210 arm_override_mode
= IS_THUMB_ADDR (pc
);
4211 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4213 insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
4215 do_cleanups (old_chain
);
4218 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
4219 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
4220 NULL if an error occurs. BUF is freed. */
4223 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
4224 int old_len
, int new_len
)
4227 int bytes_to_read
= new_len
- old_len
;
4229 new_buf
= (gdb_byte
*) xmalloc (new_len
);
4230 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
4232 if (target_read_memory (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
4240 /* An IT block is at most the 2-byte IT instruction followed by
4241 four 4-byte instructions. The furthest back we must search to
4242 find an IT block that affects the current instruction is thus
4243 2 + 3 * 4 == 14 bytes. */
4244 #define MAX_IT_BLOCK_PREFIX 14
4246 /* Use a quick scan if there are more than this many bytes of
4248 #define IT_SCAN_THRESHOLD 32
4250 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
4251 A breakpoint in an IT block may not be hit, depending on the
4254 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
4258 CORE_ADDR boundary
, func_start
;
4260 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
4261 int i
, any
, last_it
, last_it_count
;
4263 /* If we are using BKPT breakpoints, none of this is necessary. */
4264 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
4267 /* ARM mode does not have this problem. */
4268 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
4271 /* We are setting a breakpoint in Thumb code that could potentially
4272 contain an IT block. The first step is to find how much Thumb
4273 code there is; we do not need to read outside of known Thumb
4275 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
4277 /* Thumb-2 code must have mapping symbols to have a chance. */
4280 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
4282 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
4283 && func_start
> boundary
)
4284 boundary
= func_start
;
4286 /* Search for a candidate IT instruction. We have to do some fancy
4287 footwork to distinguish a real IT instruction from the second
4288 half of a 32-bit instruction, but there is no need for that if
4289 there's no candidate. */
4290 buf_len
= min (bpaddr
- boundary
, MAX_IT_BLOCK_PREFIX
);
4292 /* No room for an IT instruction. */
4295 buf
= (gdb_byte
*) xmalloc (buf_len
);
4296 if (target_read_memory (bpaddr
- buf_len
, buf
, buf_len
) != 0)
4299 for (i
= 0; i
< buf_len
; i
+= 2)
4301 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4302 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4315 /* OK, the code bytes before this instruction contain at least one
4316 halfword which resembles an IT instruction. We know that it's
4317 Thumb code, but there are still two possibilities. Either the
4318 halfword really is an IT instruction, or it is the second half of
4319 a 32-bit Thumb instruction. The only way we can tell is to
4320 scan forwards from a known instruction boundary. */
4321 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
4325 /* There's a lot of code before this instruction. Start with an
4326 optimistic search; it's easy to recognize halfwords that can
4327 not be the start of a 32-bit instruction, and use that to
4328 lock on to the instruction boundaries. */
4329 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
4332 buf_len
= IT_SCAN_THRESHOLD
;
4335 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
4337 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4338 if (thumb_insn_size (inst1
) == 2)
4345 /* At this point, if DEFINITE, BUF[I] is the first place we
4346 are sure that we know the instruction boundaries, and it is far
4347 enough from BPADDR that we could not miss an IT instruction
4348 affecting BPADDR. If ! DEFINITE, give up - start from a
4352 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
,
4356 buf_len
= bpaddr
- boundary
;
4362 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
4365 buf_len
= bpaddr
- boundary
;
4369 /* Scan forwards. Find the last IT instruction before BPADDR. */
4374 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
4376 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4381 else if (inst1
& 0x0002)
4383 else if (inst1
& 0x0004)
4388 i
+= thumb_insn_size (inst1
);
4394 /* There wasn't really an IT instruction after all. */
4397 if (last_it_count
< 1)
4398 /* It was too far away. */
4401 /* This really is a trouble spot. Move the breakpoint to the IT
4403 return bpaddr
- buf_len
+ last_it
;
4406 /* ARM displaced stepping support.
4408 Generally ARM displaced stepping works as follows:
4410 1. When an instruction is to be single-stepped, it is first decoded by
4411 arm_process_displaced_insn. Depending on the type of instruction, it is
4412 then copied to a scratch location, possibly in a modified form. The
4413 copy_* set of functions performs such modification, as necessary. A
4414 breakpoint is placed after the modified instruction in the scratch space
4415 to return control to GDB. Note in particular that instructions which
4416 modify the PC will no longer do so after modification.
4418 2. The instruction is single-stepped, by setting the PC to the scratch
4419 location address, and resuming. Control returns to GDB when the
4422 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
4423 function used for the current instruction. This function's job is to
4424 put the CPU/memory state back to what it would have been if the
4425 instruction had been executed unmodified in its original location. */
4427 /* NOP instruction (mov r0, r0). */
4428 #define ARM_NOP 0xe1a00000
4429 #define THUMB_NOP 0x4600
4431 /* Helper for register reads for displaced stepping. In particular, this
4432 returns the PC as it would be seen by the instruction at its original
4436 displaced_read_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4440 CORE_ADDR from
= dsc
->insn_addr
;
4442 if (regno
== ARM_PC_REGNUM
)
4444 /* Compute pipeline offset:
4445 - When executing an ARM instruction, PC reads as the address of the
4446 current instruction plus 8.
4447 - When executing a Thumb instruction, PC reads as the address of the
4448 current instruction plus 4. */
4455 if (debug_displaced
)
4456 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
4457 (unsigned long) from
);
4458 return (ULONGEST
) from
;
4462 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
4463 if (debug_displaced
)
4464 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
4465 regno
, (unsigned long) ret
);
4471 displaced_in_arm_mode (struct regcache
*regs
)
4474 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
4476 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4478 return (ps
& t_bit
) == 0;
4481 /* Write to the PC as from a branch instruction. */
4484 branch_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4488 /* Note: If bits 0/1 are set, this branch would be unpredictable for
4489 architecture versions < 6. */
4490 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4491 val
& ~(ULONGEST
) 0x3);
4493 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
4494 val
& ~(ULONGEST
) 0x1);
4497 /* Write to the PC as from a branch-exchange instruction. */
4500 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
4503 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
4505 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
4509 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
4510 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
4512 else if ((val
& 2) == 0)
4514 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4515 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
4519 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
4520 mode, align dest to 4 bytes). */
4521 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
4522 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
4523 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
4527 /* Write to the PC as if from a load instruction. */
4530 load_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4533 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
4534 bx_write_pc (regs
, val
);
4536 branch_write_pc (regs
, dsc
, val
);
4539 /* Write to the PC as if from an ALU instruction. */
4542 alu_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4545 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && !dsc
->is_thumb
)
4546 bx_write_pc (regs
, val
);
4548 branch_write_pc (regs
, dsc
, val
);
4551 /* Helper for writing to registers for displaced stepping. Writing to the PC
4552 has a varying effects depending on the instruction which does the write:
4553 this is controlled by the WRITE_PC argument. */
4556 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
4557 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
4559 if (regno
== ARM_PC_REGNUM
)
4561 if (debug_displaced
)
4562 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
4563 (unsigned long) val
);
4566 case BRANCH_WRITE_PC
:
4567 branch_write_pc (regs
, dsc
, val
);
4571 bx_write_pc (regs
, val
);
4575 load_write_pc (regs
, dsc
, val
);
4579 alu_write_pc (regs
, dsc
, val
);
4582 case CANNOT_WRITE_PC
:
4583 warning (_("Instruction wrote to PC in an unexpected way when "
4584 "single-stepping"));
4588 internal_error (__FILE__
, __LINE__
,
4589 _("Invalid argument to displaced_write_reg"));
4592 dsc
->wrote_to_pc
= 1;
4596 if (debug_displaced
)
4597 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
4598 regno
, (unsigned long) val
);
4599 regcache_cooked_write_unsigned (regs
, regno
, val
);
4603 /* This function is used to concisely determine if an instruction INSN
4604 references PC. Register fields of interest in INSN should have the
4605 corresponding fields of BITMASK set to 0b1111. The function
4606 returns return 1 if any of these fields in INSN reference the PC
4607 (also 0b1111, r15), else it returns 0. */
4610 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
4612 uint32_t lowbit
= 1;
4614 while (bitmask
!= 0)
4618 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
4624 mask
= lowbit
* 0xf;
4626 if ((insn
& mask
) == mask
)
4635 /* The simplest copy function. Many instructions have the same effect no
4636 matter what address they are executed at: in those cases, use this. */
4639 arm_copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
4640 const char *iname
, struct displaced_step_closure
*dsc
)
4642 if (debug_displaced
)
4643 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
4644 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
4647 dsc
->modinsn
[0] = insn
;
4653 thumb_copy_unmodified_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
4654 uint16_t insn2
, const char *iname
,
4655 struct displaced_step_closure
*dsc
)
4657 if (debug_displaced
)
4658 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x %.4x, "
4659 "opcode/class '%s' unmodified\n", insn1
, insn2
,
4662 dsc
->modinsn
[0] = insn1
;
4663 dsc
->modinsn
[1] = insn2
;
4669 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
4672 thumb_copy_unmodified_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
4674 struct displaced_step_closure
*dsc
)
4676 if (debug_displaced
)
4677 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x, "
4678 "opcode/class '%s' unmodified\n", insn
,
4681 dsc
->modinsn
[0] = insn
;
4686 /* Preload instructions with immediate offset. */
4689 cleanup_preload (struct gdbarch
*gdbarch
,
4690 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4692 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4693 if (!dsc
->u
.preload
.immed
)
4694 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
4698 install_preload (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4699 struct displaced_step_closure
*dsc
, unsigned int rn
)
4702 /* Preload instructions:
4704 {pli/pld} [rn, #+/-imm]
4706 {pli/pld} [r0, #+/-imm]. */
4708 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4709 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4710 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4711 dsc
->u
.preload
.immed
= 1;
4713 dsc
->cleanup
= &cleanup_preload
;
4717 arm_copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4718 struct displaced_step_closure
*dsc
)
4720 unsigned int rn
= bits (insn
, 16, 19);
4722 if (!insn_references_pc (insn
, 0x000f0000ul
))
4723 return arm_copy_unmodified (gdbarch
, insn
, "preload", dsc
);
4725 if (debug_displaced
)
4726 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4727 (unsigned long) insn
);
4729 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4731 install_preload (gdbarch
, regs
, dsc
, rn
);
4737 thumb2_copy_preload (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
4738 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4740 unsigned int rn
= bits (insn1
, 0, 3);
4741 unsigned int u_bit
= bit (insn1
, 7);
4742 int imm12
= bits (insn2
, 0, 11);
4745 if (rn
!= ARM_PC_REGNUM
)
4746 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "preload", dsc
);
4748 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
4749 PLD (literal) Encoding T1. */
4750 if (debug_displaced
)
4751 fprintf_unfiltered (gdb_stdlog
,
4752 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
4753 (unsigned int) dsc
->insn_addr
, u_bit
? '+' : '-',
4759 /* Rewrite instruction {pli/pld} PC imm12 into:
4760 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
4764 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
4766 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4767 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4769 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
4771 displaced_write_reg (regs
, dsc
, 0, pc_val
, CANNOT_WRITE_PC
);
4772 displaced_write_reg (regs
, dsc
, 1, imm12
, CANNOT_WRITE_PC
);
4773 dsc
->u
.preload
.immed
= 0;
4775 /* {pli/pld} [r0, r1] */
4776 dsc
->modinsn
[0] = insn1
& 0xfff0;
4777 dsc
->modinsn
[1] = 0xf001;
4780 dsc
->cleanup
= &cleanup_preload
;
4784 /* Preload instructions with register offset. */
4787 install_preload_reg(struct gdbarch
*gdbarch
, struct regcache
*regs
,
4788 struct displaced_step_closure
*dsc
, unsigned int rn
,
4791 ULONGEST rn_val
, rm_val
;
4793 /* Preload register-offset instructions:
4795 {pli/pld} [rn, rm {, shift}]
4797 {pli/pld} [r0, r1 {, shift}]. */
4799 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4800 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
4801 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4802 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
4803 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4804 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
4805 dsc
->u
.preload
.immed
= 0;
4807 dsc
->cleanup
= &cleanup_preload
;
4811 arm_copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
4812 struct regcache
*regs
,
4813 struct displaced_step_closure
*dsc
)
4815 unsigned int rn
= bits (insn
, 16, 19);
4816 unsigned int rm
= bits (insn
, 0, 3);
4819 if (!insn_references_pc (insn
, 0x000f000ful
))
4820 return arm_copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
4822 if (debug_displaced
)
4823 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
4824 (unsigned long) insn
);
4826 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
4828 install_preload_reg (gdbarch
, regs
, dsc
, rn
, rm
);
4832 /* Copy/cleanup coprocessor load and store instructions. */
4835 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
4836 struct regcache
*regs
,
4837 struct displaced_step_closure
*dsc
)
4839 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 0);
4841 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4843 if (dsc
->u
.ldst
.writeback
)
4844 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
4848 install_copro_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4849 struct displaced_step_closure
*dsc
,
4850 int writeback
, unsigned int rn
)
4854 /* Coprocessor load/store instructions:
4856 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
4858 {stc/stc2} [r0, #+/-imm].
4860 ldc/ldc2 are handled identically. */
4862 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
4863 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
4864 /* PC should be 4-byte aligned. */
4865 rn_val
= rn_val
& 0xfffffffc;
4866 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
4868 dsc
->u
.ldst
.writeback
= writeback
;
4869 dsc
->u
.ldst
.rn
= rn
;
4871 dsc
->cleanup
= &cleanup_copro_load_store
;
4875 arm_copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
4876 struct regcache
*regs
,
4877 struct displaced_step_closure
*dsc
)
4879 unsigned int rn
= bits (insn
, 16, 19);
4881 if (!insn_references_pc (insn
, 0x000f0000ul
))
4882 return arm_copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
4884 if (debug_displaced
)
4885 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4886 "load/store insn %.8lx\n", (unsigned long) insn
);
4888 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
4890 install_copro_load_store (gdbarch
, regs
, dsc
, bit (insn
, 25), rn
);
4896 thumb2_copy_copro_load_store (struct gdbarch
*gdbarch
, uint16_t insn1
,
4897 uint16_t insn2
, struct regcache
*regs
,
4898 struct displaced_step_closure
*dsc
)
4900 unsigned int rn
= bits (insn1
, 0, 3);
4902 if (rn
!= ARM_PC_REGNUM
)
4903 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
4904 "copro load/store", dsc
);
4906 if (debug_displaced
)
4907 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
4908 "load/store insn %.4x%.4x\n", insn1
, insn2
);
4910 dsc
->modinsn
[0] = insn1
& 0xfff0;
4911 dsc
->modinsn
[1] = insn2
;
4914 /* This function is called for copying instruction LDC/LDC2/VLDR, which
4915 doesn't support writeback, so pass 0. */
4916 install_copro_load_store (gdbarch
, regs
, dsc
, 0, rn
);
4921 /* Clean up branch instructions (actually perform the branch, by setting
4925 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4926 struct displaced_step_closure
*dsc
)
4928 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
4929 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
4930 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
4931 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
4936 if (dsc
->u
.branch
.link
)
4938 /* The value of LR should be the next insn of current one. In order
4939 not to confuse logic hanlding later insn `bx lr', if current insn mode
4940 is Thumb, the bit 0 of LR value should be set to 1. */
4941 ULONGEST next_insn_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
4944 next_insn_addr
|= 0x1;
4946 displaced_write_reg (regs
, dsc
, ARM_LR_REGNUM
, next_insn_addr
,
4950 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, dsc
->u
.branch
.dest
, write_pc
);
4953 /* Copy B/BL/BLX instructions with immediate destinations. */
4956 install_b_bl_blx (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4957 struct displaced_step_closure
*dsc
,
4958 unsigned int cond
, int exchange
, int link
, long offset
)
4960 /* Implement "BL<cond> <label>" as:
4962 Preparation: cond <- instruction condition
4963 Insn: mov r0, r0 (nop)
4964 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
4966 B<cond> similar, but don't set r14 in cleanup. */
4968 dsc
->u
.branch
.cond
= cond
;
4969 dsc
->u
.branch
.link
= link
;
4970 dsc
->u
.branch
.exchange
= exchange
;
4972 dsc
->u
.branch
.dest
= dsc
->insn_addr
;
4973 if (link
&& exchange
)
4974 /* For BLX, offset is computed from the Align (PC, 4). */
4975 dsc
->u
.branch
.dest
= dsc
->u
.branch
.dest
& 0xfffffffc;
4978 dsc
->u
.branch
.dest
+= 4 + offset
;
4980 dsc
->u
.branch
.dest
+= 8 + offset
;
4982 dsc
->cleanup
= &cleanup_branch
;
4985 arm_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
4986 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4988 unsigned int cond
= bits (insn
, 28, 31);
4989 int exchange
= (cond
== 0xf);
4990 int link
= exchange
|| bit (insn
, 24);
4993 if (debug_displaced
)
4994 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
4995 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
4996 (unsigned long) insn
);
4998 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
4999 then arrange the switch into Thumb mode. */
5000 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
5002 offset
= bits (insn
, 0, 23) << 2;
5004 if (bit (offset
, 25))
5005 offset
= offset
| ~0x3ffffff;
5007 dsc
->modinsn
[0] = ARM_NOP
;
5009 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5014 thumb2_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint16_t insn1
,
5015 uint16_t insn2
, struct regcache
*regs
,
5016 struct displaced_step_closure
*dsc
)
5018 int link
= bit (insn2
, 14);
5019 int exchange
= link
&& !bit (insn2
, 12);
5022 int j1
= bit (insn2
, 13);
5023 int j2
= bit (insn2
, 11);
5024 int s
= sbits (insn1
, 10, 10);
5025 int i1
= !(j1
^ bit (insn1
, 10));
5026 int i2
= !(j2
^ bit (insn1
, 10));
5028 if (!link
&& !exchange
) /* B */
5030 offset
= (bits (insn2
, 0, 10) << 1);
5031 if (bit (insn2
, 12)) /* Encoding T4 */
5033 offset
|= (bits (insn1
, 0, 9) << 12)
5039 else /* Encoding T3 */
5041 offset
|= (bits (insn1
, 0, 5) << 12)
5045 cond
= bits (insn1
, 6, 9);
5050 offset
= (bits (insn1
, 0, 9) << 12);
5051 offset
|= ((i2
<< 22) | (i1
<< 23) | (s
<< 24));
5052 offset
|= exchange
?
5053 (bits (insn2
, 1, 10) << 2) : (bits (insn2
, 0, 10) << 1);
5056 if (debug_displaced
)
5057 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s insn "
5058 "%.4x %.4x with offset %.8lx\n",
5059 link
? (exchange
) ? "blx" : "bl" : "b",
5060 insn1
, insn2
, offset
);
5062 dsc
->modinsn
[0] = THUMB_NOP
;
5064 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
5068 /* Copy B Thumb instructions. */
5070 thumb_copy_b (struct gdbarch
*gdbarch
, uint16_t insn
,
5071 struct displaced_step_closure
*dsc
)
5073 unsigned int cond
= 0;
5075 unsigned short bit_12_15
= bits (insn
, 12, 15);
5076 CORE_ADDR from
= dsc
->insn_addr
;
5078 if (bit_12_15
== 0xd)
5080 /* offset = SignExtend (imm8:0, 32) */
5081 offset
= sbits ((insn
<< 1), 0, 8);
5082 cond
= bits (insn
, 8, 11);
5084 else if (bit_12_15
== 0xe) /* Encoding T2 */
5086 offset
= sbits ((insn
<< 1), 0, 11);
5090 if (debug_displaced
)
5091 fprintf_unfiltered (gdb_stdlog
,
5092 "displaced: copying b immediate insn %.4x "
5093 "with offset %d\n", insn
, offset
);
5095 dsc
->u
.branch
.cond
= cond
;
5096 dsc
->u
.branch
.link
= 0;
5097 dsc
->u
.branch
.exchange
= 0;
5098 dsc
->u
.branch
.dest
= from
+ 4 + offset
;
5100 dsc
->modinsn
[0] = THUMB_NOP
;
5102 dsc
->cleanup
= &cleanup_branch
;
5107 /* Copy BX/BLX with register-specified destinations. */
5110 install_bx_blx_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5111 struct displaced_step_closure
*dsc
, int link
,
5112 unsigned int cond
, unsigned int rm
)
5114 /* Implement {BX,BLX}<cond> <reg>" as:
5116 Preparation: cond <- instruction condition
5117 Insn: mov r0, r0 (nop)
5118 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
5120 Don't set r14 in cleanup for BX. */
5122 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, dsc
, rm
);
5124 dsc
->u
.branch
.cond
= cond
;
5125 dsc
->u
.branch
.link
= link
;
5127 dsc
->u
.branch
.exchange
= 1;
5129 dsc
->cleanup
= &cleanup_branch
;
5133 arm_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5134 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5136 unsigned int cond
= bits (insn
, 28, 31);
5139 int link
= bit (insn
, 5);
5140 unsigned int rm
= bits (insn
, 0, 3);
5142 if (debug_displaced
)
5143 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx",
5144 (unsigned long) insn
);
5146 dsc
->modinsn
[0] = ARM_NOP
;
5148 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, cond
, rm
);
5153 thumb_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5154 struct regcache
*regs
,
5155 struct displaced_step_closure
*dsc
)
5157 int link
= bit (insn
, 7);
5158 unsigned int rm
= bits (insn
, 3, 6);
5160 if (debug_displaced
)
5161 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x",
5162 (unsigned short) insn
);
5164 dsc
->modinsn
[0] = THUMB_NOP
;
5166 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, INST_AL
, rm
);
5172 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
5175 cleanup_alu_imm (struct gdbarch
*gdbarch
,
5176 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5178 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5179 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5180 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5181 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5185 arm_copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5186 struct displaced_step_closure
*dsc
)
5188 unsigned int rn
= bits (insn
, 16, 19);
5189 unsigned int rd
= bits (insn
, 12, 15);
5190 unsigned int op
= bits (insn
, 21, 24);
5191 int is_mov
= (op
== 0xd);
5192 ULONGEST rd_val
, rn_val
;
5194 if (!insn_references_pc (insn
, 0x000ff000ul
))
5195 return arm_copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
5197 if (debug_displaced
)
5198 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
5199 "%.8lx\n", is_mov
? "move" : "ALU",
5200 (unsigned long) insn
);
5202 /* Instruction is of form:
5204 <op><cond> rd, [rn,] #imm
5208 Preparation: tmp1, tmp2 <- r0, r1;
5210 Insn: <op><cond> r0, r1, #imm
5211 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5214 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5215 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5216 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5217 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5218 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5219 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5223 dsc
->modinsn
[0] = insn
& 0xfff00fff;
5225 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
5227 dsc
->cleanup
= &cleanup_alu_imm
;
5233 thumb2_copy_alu_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5234 uint16_t insn2
, struct regcache
*regs
,
5235 struct displaced_step_closure
*dsc
)
5237 unsigned int op
= bits (insn1
, 5, 8);
5238 unsigned int rn
, rm
, rd
;
5239 ULONGEST rd_val
, rn_val
;
5241 rn
= bits (insn1
, 0, 3); /* Rn */
5242 rm
= bits (insn2
, 0, 3); /* Rm */
5243 rd
= bits (insn2
, 8, 11); /* Rd */
5245 /* This routine is only called for instruction MOV. */
5246 gdb_assert (op
== 0x2 && rn
== 0xf);
5248 if (rm
!= ARM_PC_REGNUM
&& rd
!= ARM_PC_REGNUM
)
5249 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ALU imm", dsc
);
5251 if (debug_displaced
)
5252 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x%.4x\n",
5253 "ALU", insn1
, insn2
);
5255 /* Instruction is of form:
5257 <op><cond> rd, [rn,] #imm
5261 Preparation: tmp1, tmp2 <- r0, r1;
5263 Insn: <op><cond> r0, r1, #imm
5264 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
5267 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5268 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5269 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5270 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5271 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5272 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5275 dsc
->modinsn
[0] = insn1
;
5276 dsc
->modinsn
[1] = ((insn2
& 0xf0f0) | 0x1);
5279 dsc
->cleanup
= &cleanup_alu_imm
;
5284 /* Copy/cleanup arithmetic/logic insns with register RHS. */
5287 cleanup_alu_reg (struct gdbarch
*gdbarch
,
5288 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5293 rd_val
= displaced_read_reg (regs
, dsc
, 0);
5295 for (i
= 0; i
< 3; i
++)
5296 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5298 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5302 install_alu_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5303 struct displaced_step_closure
*dsc
,
5304 unsigned int rd
, unsigned int rn
, unsigned int rm
)
5306 ULONGEST rd_val
, rn_val
, rm_val
;
5308 /* Instruction is of form:
5310 <op><cond> rd, [rn,] rm [, <shift>]
5314 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
5315 r0, r1, r2 <- rd, rn, rm
5316 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
5317 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
5320 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5321 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5322 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5323 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5324 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5325 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5326 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5327 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5328 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5331 dsc
->cleanup
= &cleanup_alu_reg
;
5335 arm_copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5336 struct displaced_step_closure
*dsc
)
5338 unsigned int op
= bits (insn
, 21, 24);
5339 int is_mov
= (op
== 0xd);
5341 if (!insn_references_pc (insn
, 0x000ff00ful
))
5342 return arm_copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
5344 if (debug_displaced
)
5345 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
5346 is_mov
? "move" : "ALU", (unsigned long) insn
);
5349 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
5351 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
5353 install_alu_reg (gdbarch
, regs
, dsc
, bits (insn
, 12, 15), bits (insn
, 16, 19),
5359 thumb_copy_alu_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
5360 struct regcache
*regs
,
5361 struct displaced_step_closure
*dsc
)
5365 rm
= bits (insn
, 3, 6);
5366 rd
= (bit (insn
, 7) << 3) | bits (insn
, 0, 2);
5368 if (rd
!= ARM_PC_REGNUM
&& rm
!= ARM_PC_REGNUM
)
5369 return thumb_copy_unmodified_16bit (gdbarch
, insn
, "ALU reg", dsc
);
5371 if (debug_displaced
)
5372 fprintf_unfiltered (gdb_stdlog
, "displaced: copying ALU reg insn %.4x\n",
5373 (unsigned short) insn
);
5375 dsc
->modinsn
[0] = ((insn
& 0xff00) | 0x10);
5377 install_alu_reg (gdbarch
, regs
, dsc
, rd
, rd
, rm
);
5382 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
5385 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
5386 struct regcache
*regs
,
5387 struct displaced_step_closure
*dsc
)
5389 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
5392 for (i
= 0; i
< 4; i
++)
5393 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
5395 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
5399 install_alu_shifted_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5400 struct displaced_step_closure
*dsc
,
5401 unsigned int rd
, unsigned int rn
, unsigned int rm
,
5405 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
5407 /* Instruction is of form:
5409 <op><cond> rd, [rn,] rm, <shift> rs
5413 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
5414 r0, r1, r2, r3 <- rd, rn, rm, rs
5415 Insn: <op><cond> r0, r1, r2, <shift> r3
5417 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
5421 for (i
= 0; i
< 4; i
++)
5422 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
5424 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
5425 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5426 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5427 rs_val
= displaced_read_reg (regs
, dsc
, rs
);
5428 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
5429 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
5430 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
5431 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
5433 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
5437 arm_copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5438 struct regcache
*regs
,
5439 struct displaced_step_closure
*dsc
)
5441 unsigned int op
= bits (insn
, 21, 24);
5442 int is_mov
= (op
== 0xd);
5443 unsigned int rd
, rn
, rm
, rs
;
5445 if (!insn_references_pc (insn
, 0x000fff0ful
))
5446 return arm_copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
5448 if (debug_displaced
)
5449 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
5450 "%.8lx\n", is_mov
? "move" : "ALU",
5451 (unsigned long) insn
);
5453 rn
= bits (insn
, 16, 19);
5454 rm
= bits (insn
, 0, 3);
5455 rs
= bits (insn
, 8, 11);
5456 rd
= bits (insn
, 12, 15);
5459 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
5461 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
5463 install_alu_shifted_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
, rs
);
5468 /* Clean up load instructions. */
5471 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5472 struct displaced_step_closure
*dsc
)
5474 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
5476 rt_val
= displaced_read_reg (regs
, dsc
, 0);
5477 if (dsc
->u
.ldst
.xfersize
== 8)
5478 rt_val2
= displaced_read_reg (regs
, dsc
, 1);
5479 rn_val
= displaced_read_reg (regs
, dsc
, 2);
5481 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5482 if (dsc
->u
.ldst
.xfersize
> 4)
5483 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5484 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5485 if (!dsc
->u
.ldst
.immed
)
5486 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5488 /* Handle register writeback. */
5489 if (dsc
->u
.ldst
.writeback
)
5490 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5491 /* Put result in right place. */
5492 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
5493 if (dsc
->u
.ldst
.xfersize
== 8)
5494 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
5497 /* Clean up store instructions. */
5500 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5501 struct displaced_step_closure
*dsc
)
5503 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 2);
5505 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5506 if (dsc
->u
.ldst
.xfersize
> 4)
5507 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5508 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
5509 if (!dsc
->u
.ldst
.immed
)
5510 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
5511 if (!dsc
->u
.ldst
.restore_r4
)
5512 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
5515 if (dsc
->u
.ldst
.writeback
)
5516 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
5519 /* Copy "extra" load/store instructions. These are halfword/doubleword
5520 transfers, which have a different encoding to byte/word transfers. */
5523 arm_copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unprivileged
,
5524 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5526 unsigned int op1
= bits (insn
, 20, 24);
5527 unsigned int op2
= bits (insn
, 5, 6);
5528 unsigned int rt
= bits (insn
, 12, 15);
5529 unsigned int rn
= bits (insn
, 16, 19);
5530 unsigned int rm
= bits (insn
, 0, 3);
5531 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
5532 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
5533 int immed
= (op1
& 0x4) != 0;
5535 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
5537 if (!insn_references_pc (insn
, 0x000ff00ful
))
5538 return arm_copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
5540 if (debug_displaced
)
5541 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
5542 "insn %.8lx\n", unprivileged
? "unprivileged " : "",
5543 (unsigned long) insn
);
5545 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
5548 internal_error (__FILE__
, __LINE__
,
5549 _("copy_extra_ld_st: instruction decode error"));
5551 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5552 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5553 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5555 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5557 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5558 if (bytesize
[opcode
] == 8)
5559 rt_val2
= displaced_read_reg (regs
, dsc
, rt
+ 1);
5560 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5562 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5564 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5565 if (bytesize
[opcode
] == 8)
5566 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
5567 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5569 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5572 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
5573 dsc
->u
.ldst
.rn
= rn
;
5574 dsc
->u
.ldst
.immed
= immed
;
5575 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
5576 dsc
->u
.ldst
.restore_r4
= 0;
5579 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
5581 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
5582 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5584 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
5586 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
5587 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5589 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
5594 /* Copy byte/half word/word loads and stores. */
5597 install_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5598 struct displaced_step_closure
*dsc
, int load
,
5599 int immed
, int writeback
, int size
, int usermode
,
5600 int rt
, int rm
, int rn
)
5602 ULONGEST rt_val
, rn_val
, rm_val
= 0;
5604 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5605 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5607 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5609 dsc
->tmp
[4] = displaced_read_reg (regs
, dsc
, 4);
5611 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
5612 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5614 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5616 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
5617 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
5619 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
5621 dsc
->u
.ldst
.xfersize
= size
;
5622 dsc
->u
.ldst
.rn
= rn
;
5623 dsc
->u
.ldst
.immed
= immed
;
5624 dsc
->u
.ldst
.writeback
= writeback
;
5626 /* To write PC we can do:
5628 Before this sequence of instructions:
5629 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
5630 r2 is the Rn value got from dispalced_read_reg.
5632 Insn1: push {pc} Write address of STR instruction + offset on stack
5633 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
5634 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
5635 = addr(Insn1) + offset - addr(Insn3) - 8
5637 Insn4: add r4, r4, #8 r4 = offset - 8
5638 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
5640 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
5642 Otherwise we don't know what value to write for PC, since the offset is
5643 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
5644 of this can be found in Section "Saving from r15" in
5645 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
5647 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5652 thumb2_copy_load_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
5653 uint16_t insn2
, struct regcache
*regs
,
5654 struct displaced_step_closure
*dsc
, int size
)
5656 unsigned int u_bit
= bit (insn1
, 7);
5657 unsigned int rt
= bits (insn2
, 12, 15);
5658 int imm12
= bits (insn2
, 0, 11);
5661 if (debug_displaced
)
5662 fprintf_unfiltered (gdb_stdlog
,
5663 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
5664 (unsigned int) dsc
->insn_addr
, rt
, u_bit
? '+' : '-',
5670 /* Rewrite instruction LDR Rt imm12 into:
5672 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
5676 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
5679 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5680 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
5681 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
5683 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
5685 pc_val
= pc_val
& 0xfffffffc;
5687 displaced_write_reg (regs
, dsc
, 2, pc_val
, CANNOT_WRITE_PC
);
5688 displaced_write_reg (regs
, dsc
, 3, imm12
, CANNOT_WRITE_PC
);
5692 dsc
->u
.ldst
.xfersize
= size
;
5693 dsc
->u
.ldst
.immed
= 0;
5694 dsc
->u
.ldst
.writeback
= 0;
5695 dsc
->u
.ldst
.restore_r4
= 0;
5697 /* LDR R0, R2, R3 */
5698 dsc
->modinsn
[0] = 0xf852;
5699 dsc
->modinsn
[1] = 0x3;
5702 dsc
->cleanup
= &cleanup_load
;
5708 thumb2_copy_load_reg_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
5709 uint16_t insn2
, struct regcache
*regs
,
5710 struct displaced_step_closure
*dsc
,
5711 int writeback
, int immed
)
5713 unsigned int rt
= bits (insn2
, 12, 15);
5714 unsigned int rn
= bits (insn1
, 0, 3);
5715 unsigned int rm
= bits (insn2
, 0, 3); /* Only valid if !immed. */
5716 /* In LDR (register), there is also a register Rm, which is not allowed to
5717 be PC, so we don't have to check it. */
5719 if (rt
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
5720 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "load",
5723 if (debug_displaced
)
5724 fprintf_unfiltered (gdb_stdlog
,
5725 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
5726 rt
, rn
, insn1
, insn2
);
5728 install_load_store (gdbarch
, regs
, dsc
, 1, immed
, writeback
, 4,
5731 dsc
->u
.ldst
.restore_r4
= 0;
5734 /* ldr[b]<cond> rt, [rn, #imm], etc.
5736 ldr[b]<cond> r0, [r2, #imm]. */
5738 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5739 dsc
->modinsn
[1] = insn2
& 0x0fff;
5742 /* ldr[b]<cond> rt, [rn, rm], etc.
5744 ldr[b]<cond> r0, [r2, r3]. */
5746 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
5747 dsc
->modinsn
[1] = (insn2
& 0x0ff0) | 0x3;
5757 arm_copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
5758 struct regcache
*regs
,
5759 struct displaced_step_closure
*dsc
,
5760 int load
, int size
, int usermode
)
5762 int immed
= !bit (insn
, 25);
5763 int writeback
= (bit (insn
, 24) == 0 || bit (insn
, 21) != 0);
5764 unsigned int rt
= bits (insn
, 12, 15);
5765 unsigned int rn
= bits (insn
, 16, 19);
5766 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
5768 if (!insn_references_pc (insn
, 0x000ff00ful
))
5769 return arm_copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
5771 if (debug_displaced
)
5772 fprintf_unfiltered (gdb_stdlog
,
5773 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
5774 load
? (size
== 1 ? "ldrb" : "ldr")
5775 : (size
== 1 ? "strb" : "str"), usermode
? "t" : "",
5777 (unsigned long) insn
);
5779 install_load_store (gdbarch
, regs
, dsc
, load
, immed
, writeback
, size
,
5780 usermode
, rt
, rm
, rn
);
5782 if (load
|| rt
!= ARM_PC_REGNUM
)
5784 dsc
->u
.ldst
.restore_r4
= 0;
5787 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
5789 {ldr,str}[b]<cond> r0, [r2, #imm]. */
5790 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
5792 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
5794 {ldr,str}[b]<cond> r0, [r2, r3]. */
5795 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
5799 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
5800 dsc
->u
.ldst
.restore_r4
= 1;
5801 dsc
->modinsn
[0] = 0xe92d8000; /* push {pc} */
5802 dsc
->modinsn
[1] = 0xe8bd0010; /* pop {r4} */
5803 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
5804 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
5805 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
5809 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
5811 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
5816 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
5821 /* Cleanup LDM instructions with fully-populated register list. This is an
5822 unfortunate corner case: it's impossible to implement correctly by modifying
5823 the instruction. The issue is as follows: we have an instruction,
5827 which we must rewrite to avoid loading PC. A possible solution would be to
5828 do the load in two halves, something like (with suitable cleanup
5832 ldm[id][ab] r8!, {r0-r7}
5834 ldm[id][ab] r8, {r7-r14}
5837 but at present there's no suitable place for <temp>, since the scratch space
5838 is overwritten before the cleanup routine is called. For now, we simply
5839 emulate the instruction. */
5842 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5843 struct displaced_step_closure
*dsc
)
5845 int inc
= dsc
->u
.block
.increment
;
5846 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
5847 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
5848 uint32_t regmask
= dsc
->u
.block
.regmask
;
5849 int regno
= inc
? 0 : 15;
5850 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
5851 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
5852 && (regmask
& 0x8000) != 0;
5853 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5854 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
5855 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5860 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
5861 sensible we can do here. Complain loudly. */
5862 if (exception_return
)
5863 error (_("Cannot single-step exception return"));
5865 /* We don't handle any stores here for now. */
5866 gdb_assert (dsc
->u
.block
.load
!= 0);
5868 if (debug_displaced
)
5869 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
5870 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
5871 dsc
->u
.block
.increment
? "inc" : "dec",
5872 dsc
->u
.block
.before
? "before" : "after");
5879 while (regno
<= ARM_PC_REGNUM
&& (regmask
& (1 << regno
)) == 0)
5882 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
5885 xfer_addr
+= bump_before
;
5887 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
5888 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
5890 xfer_addr
+= bump_after
;
5892 regmask
&= ~(1 << regno
);
5895 if (dsc
->u
.block
.writeback
)
5896 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
5900 /* Clean up an STM which included the PC in the register list. */
5903 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5904 struct displaced_step_closure
*dsc
)
5906 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5907 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
5908 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
5909 CORE_ADDR stm_insn_addr
;
5912 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5914 /* If condition code fails, there's nothing else to do. */
5915 if (!store_executed
)
5918 if (dsc
->u
.block
.increment
)
5920 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
5922 if (dsc
->u
.block
.before
)
5927 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
5929 if (dsc
->u
.block
.before
)
5933 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
5934 stm_insn_addr
= dsc
->scratch_base
;
5935 offset
= pc_val
- stm_insn_addr
;
5937 if (debug_displaced
)
5938 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
5939 "STM instruction\n", offset
);
5941 /* Rewrite the stored PC to the proper value for the non-displaced original
5943 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
5944 dsc
->insn_addr
+ offset
);
5947 /* Clean up an LDM which includes the PC in the register list. We clumped all
5948 the registers in the transferred list into a contiguous range r0...rX (to
5949 avoid loading PC directly and losing control of the debugged program), so we
5950 must undo that here. */
5953 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
5954 struct regcache
*regs
,
5955 struct displaced_step_closure
*dsc
)
5957 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5958 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
);
5959 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= ARM_PC_REGNUM
;
5960 unsigned int regs_loaded
= bitcount (mask
);
5961 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
5963 /* The method employed here will fail if the register list is fully populated
5964 (we need to avoid loading PC directly). */
5965 gdb_assert (num_to_shuffle
< 16);
5970 clobbered
= (1 << num_to_shuffle
) - 1;
5972 while (num_to_shuffle
> 0)
5974 if ((mask
& (1 << write_reg
)) != 0)
5976 unsigned int read_reg
= num_to_shuffle
- 1;
5978 if (read_reg
!= write_reg
)
5980 ULONGEST rval
= displaced_read_reg (regs
, dsc
, read_reg
);
5981 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
5982 if (debug_displaced
)
5983 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
5984 "loaded register r%d to r%d\n"), read_reg
,
5987 else if (debug_displaced
)
5988 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
5989 "r%d already in the right place\n"),
5992 clobbered
&= ~(1 << write_reg
);
6000 /* Restore any registers we scribbled over. */
6001 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
6003 if ((clobbered
& (1 << write_reg
)) != 0)
6005 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
6007 if (debug_displaced
)
6008 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
6009 "clobbered register r%d\n"), write_reg
);
6010 clobbered
&= ~(1 << write_reg
);
6014 /* Perform register writeback manually. */
6015 if (dsc
->u
.block
.writeback
)
6017 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
6019 if (dsc
->u
.block
.increment
)
6020 new_rn_val
+= regs_loaded
* 4;
6022 new_rn_val
-= regs_loaded
* 4;
6024 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
6029 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
6030 in user-level code (in particular exception return, ldm rn, {...pc}^). */
6033 arm_copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
,
6034 struct regcache
*regs
,
6035 struct displaced_step_closure
*dsc
)
6037 int load
= bit (insn
, 20);
6038 int user
= bit (insn
, 22);
6039 int increment
= bit (insn
, 23);
6040 int before
= bit (insn
, 24);
6041 int writeback
= bit (insn
, 21);
6042 int rn
= bits (insn
, 16, 19);
6044 /* Block transfers which don't mention PC can be run directly
6046 if (rn
!= ARM_PC_REGNUM
&& (insn
& 0x8000) == 0)
6047 return arm_copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
6049 if (rn
== ARM_PC_REGNUM
)
6051 warning (_("displaced: Unpredictable LDM or STM with "
6052 "base register r15"));
6053 return arm_copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
6056 if (debug_displaced
)
6057 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6058 "%.8lx\n", (unsigned long) insn
);
6060 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6061 dsc
->u
.block
.rn
= rn
;
6063 dsc
->u
.block
.load
= load
;
6064 dsc
->u
.block
.user
= user
;
6065 dsc
->u
.block
.increment
= increment
;
6066 dsc
->u
.block
.before
= before
;
6067 dsc
->u
.block
.writeback
= writeback
;
6068 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
6070 dsc
->u
.block
.regmask
= insn
& 0xffff;
6074 if ((insn
& 0xffff) == 0xffff)
6076 /* LDM with a fully-populated register list. This case is
6077 particularly tricky. Implement for now by fully emulating the
6078 instruction (which might not behave perfectly in all cases, but
6079 these instructions should be rare enough for that not to matter
6081 dsc
->modinsn
[0] = ARM_NOP
;
6083 dsc
->cleanup
= &cleanup_block_load_all
;
6087 /* LDM of a list of registers which includes PC. Implement by
6088 rewriting the list of registers to be transferred into a
6089 contiguous chunk r0...rX before doing the transfer, then shuffling
6090 registers into the correct places in the cleanup routine. */
6091 unsigned int regmask
= insn
& 0xffff;
6092 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
6095 for (i
= 0; i
< num_in_list
; i
++)
6096 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6098 /* Writeback makes things complicated. We need to avoid clobbering
6099 the base register with one of the registers in our modified
6100 register list, but just using a different register can't work in
6103 ldm r14!, {r0-r13,pc}
6105 which would need to be rewritten as:
6109 but that can't work, because there's no free register for N.
6111 Solve this by turning off the writeback bit, and emulating
6112 writeback manually in the cleanup routine. */
6117 new_regmask
= (1 << num_in_list
) - 1;
6119 if (debug_displaced
)
6120 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6121 "{..., pc}: original reg list %.4x, modified "
6122 "list %.4x\n"), rn
, writeback
? "!" : "",
6123 (int) insn
& 0xffff, new_regmask
);
6125 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
6127 dsc
->cleanup
= &cleanup_block_load_pc
;
6132 /* STM of a list of registers which includes PC. Run the instruction
6133 as-is, but out of line: this will store the wrong value for the PC,
6134 so we must manually fix up the memory in the cleanup routine.
6135 Doing things this way has the advantage that we can auto-detect
6136 the offset of the PC write (which is architecture-dependent) in
6137 the cleanup routine. */
6138 dsc
->modinsn
[0] = insn
;
6140 dsc
->cleanup
= &cleanup_block_store_pc
;
6147 thumb2_copy_block_xfer (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6148 struct regcache
*regs
,
6149 struct displaced_step_closure
*dsc
)
6151 int rn
= bits (insn1
, 0, 3);
6152 int load
= bit (insn1
, 4);
6153 int writeback
= bit (insn1
, 5);
6155 /* Block transfers which don't mention PC can be run directly
6157 if (rn
!= ARM_PC_REGNUM
&& (insn2
& 0x8000) == 0)
6158 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ldm/stm", dsc
);
6160 if (rn
== ARM_PC_REGNUM
)
6162 warning (_("displaced: Unpredictable LDM or STM with "
6163 "base register r15"));
6164 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6165 "unpredictable ldm/stm", dsc
);
6168 if (debug_displaced
)
6169 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
6170 "%.4x%.4x\n", insn1
, insn2
);
6172 /* Clear bit 13, since it should be always zero. */
6173 dsc
->u
.block
.regmask
= (insn2
& 0xdfff);
6174 dsc
->u
.block
.rn
= rn
;
6176 dsc
->u
.block
.load
= load
;
6177 dsc
->u
.block
.user
= 0;
6178 dsc
->u
.block
.increment
= bit (insn1
, 7);
6179 dsc
->u
.block
.before
= bit (insn1
, 8);
6180 dsc
->u
.block
.writeback
= writeback
;
6181 dsc
->u
.block
.cond
= INST_AL
;
6182 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
6186 if (dsc
->u
.block
.regmask
== 0xffff)
6188 /* This branch is impossible to happen. */
6193 unsigned int regmask
= dsc
->u
.block
.regmask
;
6194 unsigned int num_in_list
= bitcount (regmask
), new_regmask
;
6197 for (i
= 0; i
< num_in_list
; i
++)
6198 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6203 new_regmask
= (1 << num_in_list
) - 1;
6205 if (debug_displaced
)
6206 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
6207 "{..., pc}: original reg list %.4x, modified "
6208 "list %.4x\n"), rn
, writeback
? "!" : "",
6209 (int) dsc
->u
.block
.regmask
, new_regmask
);
6211 dsc
->modinsn
[0] = insn1
;
6212 dsc
->modinsn
[1] = (new_regmask
& 0xffff);
6215 dsc
->cleanup
= &cleanup_block_load_pc
;
6220 dsc
->modinsn
[0] = insn1
;
6221 dsc
->modinsn
[1] = insn2
;
6223 dsc
->cleanup
= &cleanup_block_store_pc
;
6228 /* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs.
6229 This is used to avoid a dependency on BFD's bfd_endian enum. */
6232 arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr
, int len
,
6235 return read_memory_unsigned_integer (memaddr
, len
,
6236 (enum bfd_endian
) byte_order
);
6239 /* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */
6242 arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs
*self
,
6245 return gdbarch_addr_bits_remove (get_regcache_arch (self
->regcache
), val
);
6248 /* Wrapper over syscall_next_pc for use in get_next_pcs. */
6251 arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs
*self
)
6256 /* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */
6259 arm_get_next_pcs_is_thumb (struct arm_get_next_pcs
*self
)
6261 return arm_is_thumb (self
->regcache
);
6264 /* single_step() is called just before we want to resume the inferior,
6265 if we want to single-step it but there is no hardware or kernel
6266 single-step support. We find the target of the coming instructions
6267 and breakpoint them. */
6270 arm_software_single_step (struct frame_info
*frame
)
6272 struct regcache
*regcache
= get_current_regcache ();
6273 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
6274 struct address_space
*aspace
= get_regcache_aspace (regcache
);
6275 struct arm_get_next_pcs next_pcs_ctx
;
6278 VEC (CORE_ADDR
) *next_pcs
= NULL
;
6279 struct cleanup
*old_chain
= make_cleanup (VEC_cleanup (CORE_ADDR
), &next_pcs
);
6281 arm_get_next_pcs_ctor (&next_pcs_ctx
,
6282 &arm_get_next_pcs_ops
,
6283 gdbarch_byte_order (gdbarch
),
6284 gdbarch_byte_order_for_code (gdbarch
),
6288 next_pcs
= arm_get_next_pcs (&next_pcs_ctx
);
6290 for (i
= 0; VEC_iterate (CORE_ADDR
, next_pcs
, i
, pc
); i
++)
6291 arm_insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
6293 do_cleanups (old_chain
);
6298 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
6299 for Linux, where some SVC instructions must be treated specially. */
6302 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6303 struct displaced_step_closure
*dsc
)
6305 CORE_ADDR resume_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
6307 if (debug_displaced
)
6308 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
6309 "%.8lx\n", (unsigned long) resume_addr
);
6311 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
6315 /* Common copy routine for svc instruciton. */
6318 install_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6319 struct displaced_step_closure
*dsc
)
6321 /* Preparation: none.
6322 Insn: unmodified svc.
6323 Cleanup: pc <- insn_addr + insn_size. */
6325 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
6327 dsc
->wrote_to_pc
= 1;
6329 /* Allow OS-specific code to override SVC handling. */
6330 if (dsc
->u
.svc
.copy_svc_os
)
6331 return dsc
->u
.svc
.copy_svc_os (gdbarch
, regs
, dsc
);
6334 dsc
->cleanup
= &cleanup_svc
;
6340 arm_copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
,
6341 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6344 if (debug_displaced
)
6345 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
6346 (unsigned long) insn
);
6348 dsc
->modinsn
[0] = insn
;
6350 return install_svc (gdbarch
, regs
, dsc
);
6354 thumb_copy_svc (struct gdbarch
*gdbarch
, uint16_t insn
,
6355 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6358 if (debug_displaced
)
6359 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.4x\n",
6362 dsc
->modinsn
[0] = insn
;
6364 return install_svc (gdbarch
, regs
, dsc
);
6367 /* Copy undefined instructions. */
6370 arm_copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
6371 struct displaced_step_closure
*dsc
)
6373 if (debug_displaced
)
6374 fprintf_unfiltered (gdb_stdlog
,
6375 "displaced: copying undefined insn %.8lx\n",
6376 (unsigned long) insn
);
6378 dsc
->modinsn
[0] = insn
;
6384 thumb_32bit_copy_undef (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
6385 struct displaced_step_closure
*dsc
)
6388 if (debug_displaced
)
6389 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn "
6390 "%.4x %.4x\n", (unsigned short) insn1
,
6391 (unsigned short) insn2
);
6393 dsc
->modinsn
[0] = insn1
;
6394 dsc
->modinsn
[1] = insn2
;
6400 /* Copy unpredictable instructions. */
6403 arm_copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
6404 struct displaced_step_closure
*dsc
)
6406 if (debug_displaced
)
6407 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
6408 "%.8lx\n", (unsigned long) insn
);
6410 dsc
->modinsn
[0] = insn
;
6415 /* The decode_* functions are instruction decoding helpers. They mostly follow
6416 the presentation in the ARM ARM. */
6419 arm_decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
6420 struct regcache
*regs
,
6421 struct displaced_step_closure
*dsc
)
6423 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
6424 unsigned int rn
= bits (insn
, 16, 19);
6426 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
6427 return arm_copy_unmodified (gdbarch
, insn
, "cps", dsc
);
6428 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
6429 return arm_copy_unmodified (gdbarch
, insn
, "setend", dsc
);
6430 else if ((op1
& 0x60) == 0x20)
6431 return arm_copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
6432 else if ((op1
& 0x71) == 0x40)
6433 return arm_copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store",
6435 else if ((op1
& 0x77) == 0x41)
6436 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6437 else if ((op1
& 0x77) == 0x45)
6438 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
6439 else if ((op1
& 0x77) == 0x51)
6442 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6444 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6446 else if ((op1
& 0x77) == 0x55)
6447 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
6448 else if (op1
== 0x57)
6451 case 0x1: return arm_copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
6452 case 0x4: return arm_copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
6453 case 0x5: return arm_copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
6454 case 0x6: return arm_copy_unmodified (gdbarch
, insn
, "isb", dsc
);
6455 default: return arm_copy_unpred (gdbarch
, insn
, dsc
);
6457 else if ((op1
& 0x63) == 0x43)
6458 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6459 else if ((op2
& 0x1) == 0x0)
6460 switch (op1
& ~0x80)
6463 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
6465 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
6466 case 0x71: case 0x75:
6468 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
6469 case 0x63: case 0x67: case 0x73: case 0x77:
6470 return arm_copy_unpred (gdbarch
, insn
, dsc
);
6472 return arm_copy_undef (gdbarch
, insn
, dsc
);
6475 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
6479 arm_decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
6480 struct regcache
*regs
,
6481 struct displaced_step_closure
*dsc
)
6483 if (bit (insn
, 27) == 0)
6484 return arm_decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
6485 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
6486 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
6489 return arm_copy_unmodified (gdbarch
, insn
, "srs", dsc
);
6492 return arm_copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
6494 case 0x4: case 0x5: case 0x6: case 0x7:
6495 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6498 switch ((insn
& 0xe00000) >> 21)
6500 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
6502 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6505 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6508 return arm_copy_undef (gdbarch
, insn
, dsc
);
6513 int rn_f
= (bits (insn
, 16, 19) == 0xf);
6514 switch ((insn
& 0xe00000) >> 21)
6517 /* ldc/ldc2 imm (undefined for rn == pc). */
6518 return rn_f
? arm_copy_undef (gdbarch
, insn
, dsc
)
6519 : arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6522 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6524 case 0x4: case 0x5: case 0x6: case 0x7:
6525 /* ldc/ldc2 lit (undefined for rn != pc). */
6526 return rn_f
? arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
6527 : arm_copy_undef (gdbarch
, insn
, dsc
);
6530 return arm_copy_undef (gdbarch
, insn
, dsc
);
6535 return arm_copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
6538 if (bits (insn
, 16, 19) == 0xf)
6540 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6542 return arm_copy_undef (gdbarch
, insn
, dsc
);
6546 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6548 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6552 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6554 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6557 return arm_copy_undef (gdbarch
, insn
, dsc
);
6561 /* Decode miscellaneous instructions in dp/misc encoding space. */
6564 arm_decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
6565 struct regcache
*regs
,
6566 struct displaced_step_closure
*dsc
)
6568 unsigned int op2
= bits (insn
, 4, 6);
6569 unsigned int op
= bits (insn
, 21, 22);
6574 return arm_copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
6577 if (op
== 0x1) /* bx. */
6578 return arm_copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
6580 return arm_copy_unmodified (gdbarch
, insn
, "clz", dsc
);
6582 return arm_copy_undef (gdbarch
, insn
, dsc
);
6586 /* Not really supported. */
6587 return arm_copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
6589 return arm_copy_undef (gdbarch
, insn
, dsc
);
6593 return arm_copy_bx_blx_reg (gdbarch
, insn
,
6594 regs
, dsc
); /* blx register. */
6596 return arm_copy_undef (gdbarch
, insn
, dsc
);
6599 return arm_copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
6603 return arm_copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
6605 /* Not really supported. */
6606 return arm_copy_unmodified (gdbarch
, insn
, "smc", dsc
);
6609 return arm_copy_undef (gdbarch
, insn
, dsc
);
6614 arm_decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
,
6615 struct regcache
*regs
,
6616 struct displaced_step_closure
*dsc
)
6619 switch (bits (insn
, 20, 24))
6622 return arm_copy_unmodified (gdbarch
, insn
, "movw", dsc
);
6625 return arm_copy_unmodified (gdbarch
, insn
, "movt", dsc
);
6627 case 0x12: case 0x16:
6628 return arm_copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
6631 return arm_copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
6635 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
6637 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
6638 return arm_copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
6639 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
6640 return arm_copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
6641 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
6642 return arm_decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
6643 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
6644 return arm_copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
6645 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
6646 return arm_copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
6647 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
6648 return arm_copy_unmodified (gdbarch
, insn
, "synch", dsc
);
6649 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
6650 /* 2nd arg means "unprivileged". */
6651 return arm_copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
6655 /* Should be unreachable. */
6660 arm_decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
6661 struct regcache
*regs
,
6662 struct displaced_step_closure
*dsc
)
6664 int a
= bit (insn
, 25), b
= bit (insn
, 4);
6665 uint32_t op1
= bits (insn
, 20, 24);
6667 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
6668 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
6669 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 0);
6670 else if ((!a
&& (op1
& 0x17) == 0x02)
6671 || (a
&& (op1
& 0x17) == 0x02 && !b
))
6672 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 1);
6673 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
6674 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
6675 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 0);
6676 else if ((!a
&& (op1
& 0x17) == 0x03)
6677 || (a
&& (op1
& 0x17) == 0x03 && !b
))
6678 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 1);
6679 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
6680 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
6681 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
6682 else if ((!a
&& (op1
& 0x17) == 0x06)
6683 || (a
&& (op1
& 0x17) == 0x06 && !b
))
6684 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
6685 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
6686 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
6687 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
6688 else if ((!a
&& (op1
& 0x17) == 0x07)
6689 || (a
&& (op1
& 0x17) == 0x07 && !b
))
6690 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
6692 /* Should be unreachable. */
6697 arm_decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
6698 struct displaced_step_closure
*dsc
)
6700 switch (bits (insn
, 20, 24))
6702 case 0x00: case 0x01: case 0x02: case 0x03:
6703 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
6705 case 0x04: case 0x05: case 0x06: case 0x07:
6706 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
6708 case 0x08: case 0x09: case 0x0a: case 0x0b:
6709 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
6710 return arm_copy_unmodified (gdbarch
, insn
,
6711 "decode/pack/unpack/saturate/reverse", dsc
);
6714 if (bits (insn
, 5, 7) == 0) /* op2. */
6716 if (bits (insn
, 12, 15) == 0xf)
6717 return arm_copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
6719 return arm_copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
6722 return arm_copy_undef (gdbarch
, insn
, dsc
);
6724 case 0x1a: case 0x1b:
6725 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6726 return arm_copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
6728 return arm_copy_undef (gdbarch
, insn
, dsc
);
6730 case 0x1c: case 0x1d:
6731 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
6733 if (bits (insn
, 0, 3) == 0xf)
6734 return arm_copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
6736 return arm_copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
6739 return arm_copy_undef (gdbarch
, insn
, dsc
);
6741 case 0x1e: case 0x1f:
6742 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
6743 return arm_copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
6745 return arm_copy_undef (gdbarch
, insn
, dsc
);
6748 /* Should be unreachable. */
6753 arm_decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, uint32_t insn
,
6754 struct regcache
*regs
,
6755 struct displaced_step_closure
*dsc
)
6758 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
6760 return arm_copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
6764 arm_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
6765 struct regcache
*regs
,
6766 struct displaced_step_closure
*dsc
)
6768 unsigned int opcode
= bits (insn
, 20, 24);
6772 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
6773 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
6775 case 0x08: case 0x0a: case 0x0c: case 0x0e:
6776 case 0x12: case 0x16:
6777 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
6779 case 0x09: case 0x0b: case 0x0d: case 0x0f:
6780 case 0x13: case 0x17:
6781 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
6783 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6784 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6785 /* Note: no writeback for these instructions. Bit 25 will always be
6786 zero though (via caller), so the following works OK. */
6787 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6790 /* Should be unreachable. */
6794 /* Decode shifted register instructions. */
6797 thumb2_decode_dp_shift_reg (struct gdbarch
*gdbarch
, uint16_t insn1
,
6798 uint16_t insn2
, struct regcache
*regs
,
6799 struct displaced_step_closure
*dsc
)
6801 /* PC is only allowed to be used in instruction MOV. */
6803 unsigned int op
= bits (insn1
, 5, 8);
6804 unsigned int rn
= bits (insn1
, 0, 3);
6806 if (op
== 0x2 && rn
== 0xf) /* MOV */
6807 return thumb2_copy_alu_imm (gdbarch
, insn1
, insn2
, regs
, dsc
);
6809 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6810 "dp (shift reg)", dsc
);
6814 /* Decode extension register load/store. Exactly the same as
6815 arm_decode_ext_reg_ld_st. */
6818 thumb2_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint16_t insn1
,
6819 uint16_t insn2
, struct regcache
*regs
,
6820 struct displaced_step_closure
*dsc
)
6822 unsigned int opcode
= bits (insn1
, 4, 8);
6826 case 0x04: case 0x05:
6827 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6828 "vfp/neon vmov", dsc
);
6830 case 0x08: case 0x0c: /* 01x00 */
6831 case 0x0a: case 0x0e: /* 01x10 */
6832 case 0x12: case 0x16: /* 10x10 */
6833 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6834 "vfp/neon vstm/vpush", dsc
);
6836 case 0x09: case 0x0d: /* 01x01 */
6837 case 0x0b: case 0x0f: /* 01x11 */
6838 case 0x13: case 0x17: /* 10x11 */
6839 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6840 "vfp/neon vldm/vpop", dsc
);
6842 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
6843 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6845 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
6846 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
, regs
, dsc
);
6849 /* Should be unreachable. */
6854 arm_decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
,
6855 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6857 unsigned int op1
= bits (insn
, 20, 25);
6858 int op
= bit (insn
, 4);
6859 unsigned int coproc
= bits (insn
, 8, 11);
6861 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
6862 return arm_decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
6863 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
6864 && (coproc
& 0xe) != 0xa)
6866 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6867 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
6868 && (coproc
& 0xe) != 0xa)
6869 /* ldc/ldc2 imm/lit. */
6870 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
6871 else if ((op1
& 0x3e) == 0x00)
6872 return arm_copy_undef (gdbarch
, insn
, dsc
);
6873 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
6874 return arm_copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
6875 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
6876 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
6877 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
6878 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
6879 else if ((op1
& 0x30) == 0x20 && !op
)
6881 if ((coproc
& 0xe) == 0xa)
6882 return arm_copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
6884 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
6886 else if ((op1
& 0x30) == 0x20 && op
)
6887 return arm_copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
6888 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
6889 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
6890 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
6891 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
6892 else if ((op1
& 0x30) == 0x30)
6893 return arm_copy_svc (gdbarch
, insn
, regs
, dsc
);
6895 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
6899 thumb2_decode_svc_copro (struct gdbarch
*gdbarch
, uint16_t insn1
,
6900 uint16_t insn2
, struct regcache
*regs
,
6901 struct displaced_step_closure
*dsc
)
6903 unsigned int coproc
= bits (insn2
, 8, 11);
6904 unsigned int bit_5_8
= bits (insn1
, 5, 8);
6905 unsigned int bit_9
= bit (insn1
, 9);
6906 unsigned int bit_4
= bit (insn1
, 4);
6911 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6912 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
6914 else if (bit_5_8
== 0) /* UNDEFINED. */
6915 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
6918 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
6919 if ((coproc
& 0xe) == 0xa)
6920 return thumb2_decode_ext_reg_ld_st (gdbarch
, insn1
, insn2
, regs
,
6922 else /* coproc is not 101x. */
6924 if (bit_4
== 0) /* STC/STC2. */
6925 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
6927 else /* LDC/LDC2 {literal, immeidate}. */
6928 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
,
6934 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "coproc", dsc
);
6940 install_pc_relative (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6941 struct displaced_step_closure
*dsc
, int rd
)
6947 Preparation: Rd <- PC
6953 int val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
6954 displaced_write_reg (regs
, dsc
, rd
, val
, CANNOT_WRITE_PC
);
6958 thumb_copy_pc_relative_16bit (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6959 struct displaced_step_closure
*dsc
,
6960 int rd
, unsigned int imm
)
6963 /* Encoding T2: ADDS Rd, #imm */
6964 dsc
->modinsn
[0] = (0x3000 | (rd
<< 8) | imm
);
6966 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
6972 thumb_decode_pc_relative_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
6973 struct regcache
*regs
,
6974 struct displaced_step_closure
*dsc
)
6976 unsigned int rd
= bits (insn
, 8, 10);
6977 unsigned int imm8
= bits (insn
, 0, 7);
6979 if (debug_displaced
)
6980 fprintf_unfiltered (gdb_stdlog
,
6981 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
6984 return thumb_copy_pc_relative_16bit (gdbarch
, regs
, dsc
, rd
, imm8
);
6988 thumb_copy_pc_relative_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
6989 uint16_t insn2
, struct regcache
*regs
,
6990 struct displaced_step_closure
*dsc
)
6992 unsigned int rd
= bits (insn2
, 8, 11);
6993 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
6994 extract raw immediate encoding rather than computing immediate. When
6995 generating ADD or SUB instruction, we can simply perform OR operation to
6996 set immediate into ADD. */
6997 unsigned int imm_3_8
= insn2
& 0x70ff;
6998 unsigned int imm_i
= insn1
& 0x0400; /* Clear all bits except bit 10. */
7000 if (debug_displaced
)
7001 fprintf_unfiltered (gdb_stdlog
,
7002 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
7003 rd
, imm_i
, imm_3_8
, insn1
, insn2
);
7005 if (bit (insn1
, 7)) /* Encoding T2 */
7007 /* Encoding T3: SUB Rd, Rd, #imm */
7008 dsc
->modinsn
[0] = (0xf1a0 | rd
| imm_i
);
7009 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7011 else /* Encoding T3 */
7013 /* Encoding T3: ADD Rd, Rd, #imm */
7014 dsc
->modinsn
[0] = (0xf100 | rd
| imm_i
);
7015 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7019 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
7025 thumb_copy_16bit_ldr_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
7026 struct regcache
*regs
,
7027 struct displaced_step_closure
*dsc
)
7029 unsigned int rt
= bits (insn1
, 8, 10);
7031 int imm8
= (bits (insn1
, 0, 7) << 2);
7037 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
7039 Insn: LDR R0, [R2, R3];
7040 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
7042 if (debug_displaced
)
7043 fprintf_unfiltered (gdb_stdlog
,
7044 "displaced: copying thumb ldr r%d [pc #%d]\n"
7047 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
7048 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
7049 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
7050 pc
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
7051 /* The assembler calculates the required value of the offset from the
7052 Align(PC,4) value of this instruction to the label. */
7053 pc
= pc
& 0xfffffffc;
7055 displaced_write_reg (regs
, dsc
, 2, pc
, CANNOT_WRITE_PC
);
7056 displaced_write_reg (regs
, dsc
, 3, imm8
, CANNOT_WRITE_PC
);
7059 dsc
->u
.ldst
.xfersize
= 4;
7061 dsc
->u
.ldst
.immed
= 0;
7062 dsc
->u
.ldst
.writeback
= 0;
7063 dsc
->u
.ldst
.restore_r4
= 0;
7065 dsc
->modinsn
[0] = 0x58d0; /* ldr r0, [r2, r3]*/
7067 dsc
->cleanup
= &cleanup_load
;
7072 /* Copy Thumb cbnz/cbz insruction. */
7075 thumb_copy_cbnz_cbz (struct gdbarch
*gdbarch
, uint16_t insn1
,
7076 struct regcache
*regs
,
7077 struct displaced_step_closure
*dsc
)
7079 int non_zero
= bit (insn1
, 11);
7080 unsigned int imm5
= (bit (insn1
, 9) << 6) | (bits (insn1
, 3, 7) << 1);
7081 CORE_ADDR from
= dsc
->insn_addr
;
7082 int rn
= bits (insn1
, 0, 2);
7083 int rn_val
= displaced_read_reg (regs
, dsc
, rn
);
7085 dsc
->u
.branch
.cond
= (rn_val
&& non_zero
) || (!rn_val
&& !non_zero
);
7086 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
7087 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
7088 condition is false, let it be, cleanup_branch will do nothing. */
7089 if (dsc
->u
.branch
.cond
)
7091 dsc
->u
.branch
.cond
= INST_AL
;
7092 dsc
->u
.branch
.dest
= from
+ 4 + imm5
;
7095 dsc
->u
.branch
.dest
= from
+ 2;
7097 dsc
->u
.branch
.link
= 0;
7098 dsc
->u
.branch
.exchange
= 0;
7100 if (debug_displaced
)
7101 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s [r%d = 0x%x]"
7102 " insn %.4x to %.8lx\n", non_zero
? "cbnz" : "cbz",
7103 rn
, rn_val
, insn1
, dsc
->u
.branch
.dest
);
7105 dsc
->modinsn
[0] = THUMB_NOP
;
7107 dsc
->cleanup
= &cleanup_branch
;
7111 /* Copy Table Branch Byte/Halfword */
7113 thumb2_copy_table_branch (struct gdbarch
*gdbarch
, uint16_t insn1
,
7114 uint16_t insn2
, struct regcache
*regs
,
7115 struct displaced_step_closure
*dsc
)
7117 ULONGEST rn_val
, rm_val
;
7118 int is_tbh
= bit (insn2
, 4);
7119 CORE_ADDR halfwords
= 0;
7120 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7122 rn_val
= displaced_read_reg (regs
, dsc
, bits (insn1
, 0, 3));
7123 rm_val
= displaced_read_reg (regs
, dsc
, bits (insn2
, 0, 3));
7129 target_read_memory (rn_val
+ 2 * rm_val
, buf
, 2);
7130 halfwords
= extract_unsigned_integer (buf
, 2, byte_order
);
7136 target_read_memory (rn_val
+ rm_val
, buf
, 1);
7137 halfwords
= extract_unsigned_integer (buf
, 1, byte_order
);
7140 if (debug_displaced
)
7141 fprintf_unfiltered (gdb_stdlog
, "displaced: %s base 0x%x offset 0x%x"
7142 " offset 0x%x\n", is_tbh
? "tbh" : "tbb",
7143 (unsigned int) rn_val
, (unsigned int) rm_val
,
7144 (unsigned int) halfwords
);
7146 dsc
->u
.branch
.cond
= INST_AL
;
7147 dsc
->u
.branch
.link
= 0;
7148 dsc
->u
.branch
.exchange
= 0;
7149 dsc
->u
.branch
.dest
= dsc
->insn_addr
+ 4 + 2 * halfwords
;
7151 dsc
->cleanup
= &cleanup_branch
;
7157 cleanup_pop_pc_16bit_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7158 struct displaced_step_closure
*dsc
)
7161 int val
= displaced_read_reg (regs
, dsc
, 7);
7162 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, val
, BX_WRITE_PC
);
7165 val
= displaced_read_reg (regs
, dsc
, 8);
7166 displaced_write_reg (regs
, dsc
, 7, val
, CANNOT_WRITE_PC
);
7169 displaced_write_reg (regs
, dsc
, 8, dsc
->tmp
[0], CANNOT_WRITE_PC
);
7174 thumb_copy_pop_pc_16bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
7175 struct regcache
*regs
,
7176 struct displaced_step_closure
*dsc
)
7178 dsc
->u
.block
.regmask
= insn1
& 0x00ff;
7180 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
7183 (1) register list is full, that is, r0-r7 are used.
7184 Prepare: tmp[0] <- r8
7186 POP {r0, r1, ...., r6, r7}; remove PC from reglist
7187 MOV r8, r7; Move value of r7 to r8;
7188 POP {r7}; Store PC value into r7.
7190 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
7192 (2) register list is not full, supposing there are N registers in
7193 register list (except PC, 0 <= N <= 7).
7194 Prepare: for each i, 0 - N, tmp[i] <- ri.
7196 POP {r0, r1, ...., rN};
7198 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
7199 from tmp[] properly.
7201 if (debug_displaced
)
7202 fprintf_unfiltered (gdb_stdlog
,
7203 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
7204 dsc
->u
.block
.regmask
, insn1
);
7206 if (dsc
->u
.block
.regmask
== 0xff)
7208 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 8);
7210 dsc
->modinsn
[0] = (insn1
& 0xfeff); /* POP {r0,r1,...,r6, r7} */
7211 dsc
->modinsn
[1] = 0x46b8; /* MOV r8, r7 */
7212 dsc
->modinsn
[2] = 0xbc80; /* POP {r7} */
7215 dsc
->cleanup
= &cleanup_pop_pc_16bit_all
;
7219 unsigned int num_in_list
= bitcount (dsc
->u
.block
.regmask
);
7221 unsigned int new_regmask
;
7223 for (i
= 0; i
< num_in_list
+ 1; i
++)
7224 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7226 new_regmask
= (1 << (num_in_list
+ 1)) - 1;
7228 if (debug_displaced
)
7229 fprintf_unfiltered (gdb_stdlog
, _("displaced: POP "
7230 "{..., pc}: original reg list %.4x,"
7231 " modified list %.4x\n"),
7232 (int) dsc
->u
.block
.regmask
, new_regmask
);
7234 dsc
->u
.block
.regmask
|= 0x8000;
7235 dsc
->u
.block
.writeback
= 0;
7236 dsc
->u
.block
.cond
= INST_AL
;
7238 dsc
->modinsn
[0] = (insn1
& ~0x1ff) | (new_regmask
& 0xff);
7240 dsc
->cleanup
= &cleanup_block_load_pc
;
7247 thumb_process_displaced_16bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7248 struct regcache
*regs
,
7249 struct displaced_step_closure
*dsc
)
7251 unsigned short op_bit_12_15
= bits (insn1
, 12, 15);
7252 unsigned short op_bit_10_11
= bits (insn1
, 10, 11);
7255 /* 16-bit thumb instructions. */
7256 switch (op_bit_12_15
)
7258 /* Shift (imme), add, subtract, move and compare. */
7259 case 0: case 1: case 2: case 3:
7260 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7261 "shift/add/sub/mov/cmp",
7265 switch (op_bit_10_11
)
7267 case 0: /* Data-processing */
7268 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
7272 case 1: /* Special data instructions and branch and exchange. */
7274 unsigned short op
= bits (insn1
, 7, 9);
7275 if (op
== 6 || op
== 7) /* BX or BLX */
7276 err
= thumb_copy_bx_blx_reg (gdbarch
, insn1
, regs
, dsc
);
7277 else if (bits (insn1
, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
7278 err
= thumb_copy_alu_reg (gdbarch
, insn1
, regs
, dsc
);
7280 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "special data",
7284 default: /* LDR (literal) */
7285 err
= thumb_copy_16bit_ldr_literal (gdbarch
, insn1
, regs
, dsc
);
7288 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
7289 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldr/str", dsc
);
7292 if (op_bit_10_11
< 2) /* Generate PC-relative address */
7293 err
= thumb_decode_pc_relative_16bit (gdbarch
, insn1
, regs
, dsc
);
7294 else /* Generate SP-relative address */
7295 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "sp-relative", dsc
);
7297 case 11: /* Misc 16-bit instructions */
7299 switch (bits (insn1
, 8, 11))
7301 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
7302 err
= thumb_copy_cbnz_cbz (gdbarch
, insn1
, regs
, dsc
);
7304 case 12: case 13: /* POP */
7305 if (bit (insn1
, 8)) /* PC is in register list. */
7306 err
= thumb_copy_pop_pc_16bit (gdbarch
, insn1
, regs
, dsc
);
7308 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "pop", dsc
);
7310 case 15: /* If-Then, and hints */
7311 if (bits (insn1
, 0, 3))
7312 /* If-Then makes up to four following instructions conditional.
7313 IT instruction itself is not conditional, so handle it as a
7314 common unmodified instruction. */
7315 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "If-Then",
7318 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "hints", dsc
);
7321 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "misc", dsc
);
7326 if (op_bit_10_11
< 2) /* Store multiple registers */
7327 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "stm", dsc
);
7328 else /* Load multiple registers */
7329 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldm", dsc
);
7331 case 13: /* Conditional branch and supervisor call */
7332 if (bits (insn1
, 9, 11) != 7) /* conditional branch */
7333 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7335 err
= thumb_copy_svc (gdbarch
, insn1
, regs
, dsc
);
7337 case 14: /* Unconditional branch */
7338 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
7345 internal_error (__FILE__
, __LINE__
,
7346 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
7350 decode_thumb_32bit_ld_mem_hints (struct gdbarch
*gdbarch
,
7351 uint16_t insn1
, uint16_t insn2
,
7352 struct regcache
*regs
,
7353 struct displaced_step_closure
*dsc
)
7355 int rt
= bits (insn2
, 12, 15);
7356 int rn
= bits (insn1
, 0, 3);
7357 int op1
= bits (insn1
, 7, 8);
7359 switch (bits (insn1
, 5, 6))
7361 case 0: /* Load byte and memory hints */
7362 if (rt
== 0xf) /* PLD/PLI */
7365 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
7366 return thumb2_copy_preload (gdbarch
, insn1
, insn2
, regs
, dsc
);
7368 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7373 if (rn
== 0xf) /* LDRB/LDRSB (literal) */
7374 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7377 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7378 "ldrb{reg, immediate}/ldrbt",
7383 case 1: /* Load halfword and memory hints. */
7384 if (rt
== 0xf) /* PLD{W} and Unalloc memory hint. */
7385 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7386 "pld/unalloc memhint", dsc
);
7390 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
7393 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7397 case 2: /* Load word */
7399 int insn2_bit_8_11
= bits (insn2
, 8, 11);
7402 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
, 4);
7403 else if (op1
== 0x1) /* Encoding T3 */
7404 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
, dsc
,
7406 else /* op1 == 0x0 */
7408 if (insn2_bit_8_11
== 0xc || (insn2_bit_8_11
& 0x9) == 0x9)
7409 /* LDR (immediate) */
7410 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7411 dsc
, bit (insn2
, 8), 1);
7412 else if (insn2_bit_8_11
== 0xe) /* LDRT */
7413 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7416 /* LDR (register) */
7417 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
7423 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
7430 thumb_process_displaced_32bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
7431 uint16_t insn2
, struct regcache
*regs
,
7432 struct displaced_step_closure
*dsc
)
7435 unsigned short op
= bit (insn2
, 15);
7436 unsigned int op1
= bits (insn1
, 11, 12);
7442 switch (bits (insn1
, 9, 10))
7447 /* Load/store {dual, execlusive}, table branch. */
7448 if (bits (insn1
, 7, 8) == 1 && bits (insn1
, 4, 5) == 1
7449 && bits (insn2
, 5, 7) == 0)
7450 err
= thumb2_copy_table_branch (gdbarch
, insn1
, insn2
, regs
,
7453 /* PC is not allowed to use in load/store {dual, exclusive}
7455 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7456 "load/store dual/ex", dsc
);
7458 else /* load/store multiple */
7460 switch (bits (insn1
, 7, 8))
7462 case 0: case 3: /* SRS, RFE */
7463 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7466 case 1: case 2: /* LDM/STM/PUSH/POP */
7467 err
= thumb2_copy_block_xfer (gdbarch
, insn1
, insn2
, regs
, dsc
);
7474 /* Data-processing (shift register). */
7475 err
= thumb2_decode_dp_shift_reg (gdbarch
, insn1
, insn2
, regs
,
7478 default: /* Coprocessor instructions. */
7479 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7484 case 2: /* op1 = 2 */
7485 if (op
) /* Branch and misc control. */
7487 if (bit (insn2
, 14) /* BLX/BL */
7488 || bit (insn2
, 12) /* Unconditional branch */
7489 || (bits (insn1
, 7, 9) != 0x7)) /* Conditional branch */
7490 err
= thumb2_copy_b_bl_blx (gdbarch
, insn1
, insn2
, regs
, dsc
);
7492 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7497 if (bit (insn1
, 9)) /* Data processing (plain binary imm). */
7499 int op
= bits (insn1
, 4, 8);
7500 int rn
= bits (insn1
, 0, 3);
7501 if ((op
== 0 || op
== 0xa) && rn
== 0xf)
7502 err
= thumb_copy_pc_relative_32bit (gdbarch
, insn1
, insn2
,
7505 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7508 else /* Data processing (modified immeidate) */
7509 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7513 case 3: /* op1 = 3 */
7514 switch (bits (insn1
, 9, 10))
7518 err
= decode_thumb_32bit_ld_mem_hints (gdbarch
, insn1
, insn2
,
7520 else /* NEON Load/Store and Store single data item */
7521 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7522 "neon elt/struct load/store",
7525 case 1: /* op1 = 3, bits (9, 10) == 1 */
7526 switch (bits (insn1
, 7, 8))
7528 case 0: case 1: /* Data processing (register) */
7529 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7532 case 2: /* Multiply and absolute difference */
7533 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7534 "mul/mua/diff", dsc
);
7536 case 3: /* Long multiply and divide */
7537 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7542 default: /* Coprocessor instructions */
7543 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
7552 internal_error (__FILE__
, __LINE__
,
7553 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
7558 thumb_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7559 struct regcache
*regs
,
7560 struct displaced_step_closure
*dsc
)
7562 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7564 = read_memory_unsigned_integer (from
, 2, byte_order_for_code
);
7566 if (debug_displaced
)
7567 fprintf_unfiltered (gdb_stdlog
, "displaced: process thumb insn %.4x "
7568 "at %.8lx\n", insn1
, (unsigned long) from
);
7571 dsc
->insn_size
= thumb_insn_size (insn1
);
7572 if (thumb_insn_size (insn1
) == 4)
7575 = read_memory_unsigned_integer (from
+ 2, 2, byte_order_for_code
);
7576 thumb_process_displaced_32bit_insn (gdbarch
, insn1
, insn2
, regs
, dsc
);
7579 thumb_process_displaced_16bit_insn (gdbarch
, insn1
, regs
, dsc
);
7583 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7584 CORE_ADDR to
, struct regcache
*regs
,
7585 struct displaced_step_closure
*dsc
)
7588 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7591 /* Most displaced instructions use a 1-instruction scratch space, so set this
7592 here and override below if/when necessary. */
7594 dsc
->insn_addr
= from
;
7595 dsc
->scratch_base
= to
;
7596 dsc
->cleanup
= NULL
;
7597 dsc
->wrote_to_pc
= 0;
7599 if (!displaced_in_arm_mode (regs
))
7600 return thumb_process_displaced_insn (gdbarch
, from
, regs
, dsc
);
7604 insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
7605 if (debug_displaced
)
7606 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
7607 "at %.8lx\n", (unsigned long) insn
,
7608 (unsigned long) from
);
7610 if ((insn
& 0xf0000000) == 0xf0000000)
7611 err
= arm_decode_unconditional (gdbarch
, insn
, regs
, dsc
);
7612 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
7614 case 0x0: case 0x1: case 0x2: case 0x3:
7615 err
= arm_decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
7618 case 0x4: case 0x5: case 0x6:
7619 err
= arm_decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
7623 err
= arm_decode_media (gdbarch
, insn
, dsc
);
7626 case 0x8: case 0x9: case 0xa: case 0xb:
7627 err
= arm_decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
7630 case 0xc: case 0xd: case 0xe: case 0xf:
7631 err
= arm_decode_svc_copro (gdbarch
, insn
, regs
, dsc
);
7636 internal_error (__FILE__
, __LINE__
,
7637 _("arm_process_displaced_insn: Instruction decode error"));
7640 /* Actually set up the scratch space for a displaced instruction. */
7643 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
7644 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
7646 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7647 unsigned int i
, len
, offset
;
7648 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7649 int size
= dsc
->is_thumb
? 2 : 4;
7650 const gdb_byte
*bkp_insn
;
7653 /* Poke modified instruction(s). */
7654 for (i
= 0; i
< dsc
->numinsns
; i
++)
7656 if (debug_displaced
)
7658 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn ");
7660 fprintf_unfiltered (gdb_stdlog
, "%.8lx",
7663 fprintf_unfiltered (gdb_stdlog
, "%.4x",
7664 (unsigned short)dsc
->modinsn
[i
]);
7666 fprintf_unfiltered (gdb_stdlog
, " at %.8lx\n",
7667 (unsigned long) to
+ offset
);
7670 write_memory_unsigned_integer (to
+ offset
, size
,
7671 byte_order_for_code
,
7676 /* Choose the correct breakpoint instruction. */
7679 bkp_insn
= tdep
->thumb_breakpoint
;
7680 len
= tdep
->thumb_breakpoint_size
;
7684 bkp_insn
= tdep
->arm_breakpoint
;
7685 len
= tdep
->arm_breakpoint_size
;
7688 /* Put breakpoint afterwards. */
7689 write_memory (to
+ offset
, bkp_insn
, len
);
7691 if (debug_displaced
)
7692 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
7693 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
7696 /* Entry point for cleaning things up after a displaced instruction has been
7700 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
7701 struct displaced_step_closure
*dsc
,
7702 CORE_ADDR from
, CORE_ADDR to
,
7703 struct regcache
*regs
)
7706 dsc
->cleanup (gdbarch
, regs
, dsc
);
7708 if (!dsc
->wrote_to_pc
)
7709 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
7710 dsc
->insn_addr
+ dsc
->insn_size
);
7714 #include "bfd-in2.h"
7715 #include "libcoff.h"
7718 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
7720 struct gdbarch
*gdbarch
= (struct gdbarch
*) info
->application_data
;
7722 if (arm_pc_is_thumb (gdbarch
, memaddr
))
7724 static asymbol
*asym
;
7725 static combined_entry_type ce
;
7726 static struct coff_symbol_struct csym
;
7727 static struct bfd fake_bfd
;
7728 static bfd_target fake_target
;
7730 if (csym
.native
== NULL
)
7732 /* Create a fake symbol vector containing a Thumb symbol.
7733 This is solely so that the code in print_insn_little_arm()
7734 and print_insn_big_arm() in opcodes/arm-dis.c will detect
7735 the presence of a Thumb symbol and switch to decoding
7736 Thumb instructions. */
7738 fake_target
.flavour
= bfd_target_coff_flavour
;
7739 fake_bfd
.xvec
= &fake_target
;
7740 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
7742 csym
.symbol
.the_bfd
= &fake_bfd
;
7743 csym
.symbol
.name
= "fake";
7744 asym
= (asymbol
*) & csym
;
7747 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
7748 info
->symbols
= &asym
;
7751 info
->symbols
= NULL
;
7753 if (info
->endian
== BFD_ENDIAN_BIG
)
7754 return print_insn_big_arm (memaddr
, info
);
7756 return print_insn_little_arm (memaddr
, info
);
7759 /* The following define instruction sequences that will cause ARM
7760 cpu's to take an undefined instruction trap. These are used to
7761 signal a breakpoint to GDB.
7763 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
7764 modes. A different instruction is required for each mode. The ARM
7765 cpu's can also be big or little endian. Thus four different
7766 instructions are needed to support all cases.
7768 Note: ARMv4 defines several new instructions that will take the
7769 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
7770 not in fact add the new instructions. The new undefined
7771 instructions in ARMv4 are all instructions that had no defined
7772 behaviour in earlier chips. There is no guarantee that they will
7773 raise an exception, but may be treated as NOP's. In practice, it
7774 may only safe to rely on instructions matching:
7776 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
7777 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
7778 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
7780 Even this may only true if the condition predicate is true. The
7781 following use a condition predicate of ALWAYS so it is always TRUE.
7783 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
7784 and NetBSD all use a software interrupt rather than an undefined
7785 instruction to force a trap. This can be handled by by the
7786 abi-specific code during establishment of the gdbarch vector. */
7788 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
7789 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
7790 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
7791 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
7793 static const gdb_byte arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
7794 static const gdb_byte arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
7795 static const gdb_byte arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
7796 static const gdb_byte arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
7798 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
7799 the program counter value to determine whether a 16-bit or 32-bit
7800 breakpoint should be used. It returns a pointer to a string of
7801 bytes that encode a breakpoint instruction, stores the length of
7802 the string to *lenptr, and adjusts the program counter (if
7803 necessary) to point to the actual memory location where the
7804 breakpoint should be inserted. */
7806 static const unsigned char *
7807 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
7809 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7810 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7812 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
7814 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
7816 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
7817 check whether we are replacing a 32-bit instruction. */
7818 if (tdep
->thumb2_breakpoint
!= NULL
)
7821 if (target_read_memory (*pcptr
, buf
, 2) == 0)
7823 unsigned short inst1
;
7824 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
7825 if (thumb_insn_size (inst1
) == 4)
7827 *lenptr
= tdep
->thumb2_breakpoint_size
;
7828 return tdep
->thumb2_breakpoint
;
7833 *lenptr
= tdep
->thumb_breakpoint_size
;
7834 return tdep
->thumb_breakpoint
;
7838 *lenptr
= tdep
->arm_breakpoint_size
;
7839 return tdep
->arm_breakpoint
;
7844 arm_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
7847 arm_breakpoint_from_pc (gdbarch
, pcptr
, kindptr
);
7849 if (arm_pc_is_thumb (gdbarch
, *pcptr
) && *kindptr
== 4)
7850 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
7851 that this is not confused with a 32-bit ARM breakpoint. */
7855 /* Extract from an array REGBUF containing the (raw) register state a
7856 function return value of type TYPE, and copy that, in virtual
7857 format, into VALBUF. */
7860 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
7863 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
7864 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7866 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
7868 switch (gdbarch_tdep (gdbarch
)->fp_model
)
7872 /* The value is in register F0 in internal format. We need to
7873 extract the raw value and then convert it to the desired
7875 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
7877 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
7878 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
7879 valbuf
, gdbarch_byte_order (gdbarch
));
7883 case ARM_FLOAT_SOFT_FPA
:
7884 case ARM_FLOAT_SOFT_VFP
:
7885 /* ARM_FLOAT_VFP can arise if this is a variadic function so
7886 not using the VFP ABI code. */
7888 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
7889 if (TYPE_LENGTH (type
) > 4)
7890 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
7891 valbuf
+ INT_REGISTER_SIZE
);
7895 internal_error (__FILE__
, __LINE__
,
7896 _("arm_extract_return_value: "
7897 "Floating point model not supported"));
7901 else if (TYPE_CODE (type
) == TYPE_CODE_INT
7902 || TYPE_CODE (type
) == TYPE_CODE_CHAR
7903 || TYPE_CODE (type
) == TYPE_CODE_BOOL
7904 || TYPE_CODE (type
) == TYPE_CODE_PTR
7905 || TYPE_CODE (type
) == TYPE_CODE_REF
7906 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
7908 /* If the type is a plain integer, then the access is
7909 straight-forward. Otherwise we have to play around a bit
7911 int len
= TYPE_LENGTH (type
);
7912 int regno
= ARM_A1_REGNUM
;
7917 /* By using store_unsigned_integer we avoid having to do
7918 anything special for small big-endian values. */
7919 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
7920 store_unsigned_integer (valbuf
,
7921 (len
> INT_REGISTER_SIZE
7922 ? INT_REGISTER_SIZE
: len
),
7924 len
-= INT_REGISTER_SIZE
;
7925 valbuf
+= INT_REGISTER_SIZE
;
7930 /* For a structure or union the behaviour is as if the value had
7931 been stored to word-aligned memory and then loaded into
7932 registers with 32-bit load instruction(s). */
7933 int len
= TYPE_LENGTH (type
);
7934 int regno
= ARM_A1_REGNUM
;
7935 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
7939 regcache_cooked_read (regs
, regno
++, tmpbuf
);
7940 memcpy (valbuf
, tmpbuf
,
7941 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
7942 len
-= INT_REGISTER_SIZE
;
7943 valbuf
+= INT_REGISTER_SIZE
;
7949 /* Will a function return an aggregate type in memory or in a
7950 register? Return 0 if an aggregate type can be returned in a
7951 register, 1 if it must be returned in memory. */
7954 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
7956 enum type_code code
;
7958 type
= check_typedef (type
);
7960 /* Simple, non-aggregate types (ie not including vectors and
7961 complex) are always returned in a register (or registers). */
7962 code
= TYPE_CODE (type
);
7963 if (TYPE_CODE_STRUCT
!= code
&& TYPE_CODE_UNION
!= code
7964 && TYPE_CODE_ARRAY
!= code
&& TYPE_CODE_COMPLEX
!= code
)
7967 if (TYPE_CODE_ARRAY
== code
&& TYPE_VECTOR (type
))
7969 /* Vector values should be returned using ARM registers if they
7970 are not over 16 bytes. */
7971 return (TYPE_LENGTH (type
) > 16);
7974 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
7976 /* The AAPCS says all aggregates not larger than a word are returned
7978 if (TYPE_LENGTH (type
) <= INT_REGISTER_SIZE
)
7987 /* All aggregate types that won't fit in a register must be returned
7989 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
7992 /* In the ARM ABI, "integer" like aggregate types are returned in
7993 registers. For an aggregate type to be integer like, its size
7994 must be less than or equal to INT_REGISTER_SIZE and the
7995 offset of each addressable subfield must be zero. Note that bit
7996 fields are not addressable, and all addressable subfields of
7997 unions always start at offset zero.
7999 This function is based on the behaviour of GCC 2.95.1.
8000 See: gcc/arm.c: arm_return_in_memory() for details.
8002 Note: All versions of GCC before GCC 2.95.2 do not set up the
8003 parameters correctly for a function returning the following
8004 structure: struct { float f;}; This should be returned in memory,
8005 not a register. Richard Earnshaw sent me a patch, but I do not
8006 know of any way to detect if a function like the above has been
8007 compiled with the correct calling convention. */
8009 /* Assume all other aggregate types can be returned in a register.
8010 Run a check for structures, unions and arrays. */
8013 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
8016 /* Need to check if this struct/union is "integer" like. For
8017 this to be true, its size must be less than or equal to
8018 INT_REGISTER_SIZE and the offset of each addressable
8019 subfield must be zero. Note that bit fields are not
8020 addressable, and unions always start at offset zero. If any
8021 of the subfields is a floating point type, the struct/union
8022 cannot be an integer type. */
8024 /* For each field in the object, check:
8025 1) Is it FP? --> yes, nRc = 1;
8026 2) Is it addressable (bitpos != 0) and
8027 not packed (bitsize == 0)?
8031 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
8033 enum type_code field_type_code
;
8036 = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
,
8039 /* Is it a floating point type field? */
8040 if (field_type_code
== TYPE_CODE_FLT
)
8046 /* If bitpos != 0, then we have to care about it. */
8047 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
8049 /* Bitfields are not addressable. If the field bitsize is
8050 zero, then the field is not packed. Hence it cannot be
8051 a bitfield or any other packed type. */
8052 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
8065 /* Write into appropriate registers a function return value of type
8066 TYPE, given in virtual format. */
8069 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
8070 const gdb_byte
*valbuf
)
8072 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
8073 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8075 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
8077 gdb_byte buf
[MAX_REGISTER_SIZE
];
8079 switch (gdbarch_tdep (gdbarch
)->fp_model
)
8083 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
8084 gdbarch_byte_order (gdbarch
));
8085 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
8088 case ARM_FLOAT_SOFT_FPA
:
8089 case ARM_FLOAT_SOFT_VFP
:
8090 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8091 not using the VFP ABI code. */
8093 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
8094 if (TYPE_LENGTH (type
) > 4)
8095 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
8096 valbuf
+ INT_REGISTER_SIZE
);
8100 internal_error (__FILE__
, __LINE__
,
8101 _("arm_store_return_value: Floating "
8102 "point model not supported"));
8106 else if (TYPE_CODE (type
) == TYPE_CODE_INT
8107 || TYPE_CODE (type
) == TYPE_CODE_CHAR
8108 || TYPE_CODE (type
) == TYPE_CODE_BOOL
8109 || TYPE_CODE (type
) == TYPE_CODE_PTR
8110 || TYPE_CODE (type
) == TYPE_CODE_REF
8111 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
8113 if (TYPE_LENGTH (type
) <= 4)
8115 /* Values of one word or less are zero/sign-extended and
8117 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8118 LONGEST val
= unpack_long (type
, valbuf
);
8120 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
8121 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
8125 /* Integral values greater than one word are stored in consecutive
8126 registers starting with r0. This will always be a multiple of
8127 the regiser size. */
8128 int len
= TYPE_LENGTH (type
);
8129 int regno
= ARM_A1_REGNUM
;
8133 regcache_cooked_write (regs
, regno
++, valbuf
);
8134 len
-= INT_REGISTER_SIZE
;
8135 valbuf
+= INT_REGISTER_SIZE
;
8141 /* For a structure or union the behaviour is as if the value had
8142 been stored to word-aligned memory and then loaded into
8143 registers with 32-bit load instruction(s). */
8144 int len
= TYPE_LENGTH (type
);
8145 int regno
= ARM_A1_REGNUM
;
8146 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8150 memcpy (tmpbuf
, valbuf
,
8151 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
8152 regcache_cooked_write (regs
, regno
++, tmpbuf
);
8153 len
-= INT_REGISTER_SIZE
;
8154 valbuf
+= INT_REGISTER_SIZE
;
8160 /* Handle function return values. */
8162 static enum return_value_convention
8163 arm_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
8164 struct type
*valtype
, struct regcache
*regcache
,
8165 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
8167 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8168 struct type
*func_type
= function
? value_type (function
) : NULL
;
8169 enum arm_vfp_cprc_base_type vfp_base_type
;
8172 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
8173 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
8175 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
8176 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
8178 for (i
= 0; i
< vfp_base_count
; i
++)
8180 if (reg_char
== 'q')
8183 arm_neon_quad_write (gdbarch
, regcache
, i
,
8184 writebuf
+ i
* unit_length
);
8187 arm_neon_quad_read (gdbarch
, regcache
, i
,
8188 readbuf
+ i
* unit_length
);
8195 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d", reg_char
, i
);
8196 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8199 regcache_cooked_write (regcache
, regnum
,
8200 writebuf
+ i
* unit_length
);
8202 regcache_cooked_read (regcache
, regnum
,
8203 readbuf
+ i
* unit_length
);
8206 return RETURN_VALUE_REGISTER_CONVENTION
;
8209 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
8210 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
8211 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
8213 if (tdep
->struct_return
== pcc_struct_return
8214 || arm_return_in_memory (gdbarch
, valtype
))
8215 return RETURN_VALUE_STRUCT_CONVENTION
;
8217 else if (TYPE_CODE (valtype
) == TYPE_CODE_COMPLEX
)
8219 if (arm_return_in_memory (gdbarch
, valtype
))
8220 return RETURN_VALUE_STRUCT_CONVENTION
;
8224 arm_store_return_value (valtype
, regcache
, writebuf
);
8227 arm_extract_return_value (valtype
, regcache
, readbuf
);
8229 return RETURN_VALUE_REGISTER_CONVENTION
;
8234 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
8236 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
8237 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8238 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8240 gdb_byte buf
[INT_REGISTER_SIZE
];
8242 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
8244 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
8248 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
8252 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
8253 return the target PC. Otherwise return 0. */
8256 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
8260 CORE_ADDR start_addr
;
8262 /* Find the starting address and name of the function containing the PC. */
8263 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
8265 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
8267 start_addr
= arm_skip_bx_reg (frame
, pc
);
8268 if (start_addr
!= 0)
8274 /* If PC is in a Thumb call or return stub, return the address of the
8275 target PC, which is in a register. The thunk functions are called
8276 _call_via_xx, where x is the register name. The possible names
8277 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
8278 functions, named __ARM_call_via_r[0-7]. */
8279 if (startswith (name
, "_call_via_")
8280 || startswith (name
, "__ARM_call_via_"))
8282 /* Use the name suffix to determine which register contains the
8284 static char *table
[15] =
8285 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8286 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
8289 int offset
= strlen (name
) - 2;
8291 for (regno
= 0; regno
<= 14; regno
++)
8292 if (strcmp (&name
[offset
], table
[regno
]) == 0)
8293 return get_frame_register_unsigned (frame
, regno
);
8296 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
8297 non-interworking calls to foo. We could decode the stubs
8298 to find the target but it's easier to use the symbol table. */
8299 namelen
= strlen (name
);
8300 if (name
[0] == '_' && name
[1] == '_'
8301 && ((namelen
> 2 + strlen ("_from_thumb")
8302 && startswith (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb"))
8303 || (namelen
> 2 + strlen ("_from_arm")
8304 && startswith (name
+ namelen
- strlen ("_from_arm"), "_from_arm"))))
8307 int target_len
= namelen
- 2;
8308 struct bound_minimal_symbol minsym
;
8309 struct objfile
*objfile
;
8310 struct obj_section
*sec
;
8312 if (name
[namelen
- 1] == 'b')
8313 target_len
-= strlen ("_from_thumb");
8315 target_len
-= strlen ("_from_arm");
8317 target_name
= (char *) alloca (target_len
+ 1);
8318 memcpy (target_name
, name
+ 2, target_len
);
8319 target_name
[target_len
] = '\0';
8321 sec
= find_pc_section (pc
);
8322 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
8323 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
8324 if (minsym
.minsym
!= NULL
)
8325 return BMSYMBOL_VALUE_ADDRESS (minsym
);
8330 return 0; /* not a stub */
8334 set_arm_command (char *args
, int from_tty
)
8336 printf_unfiltered (_("\
8337 \"set arm\" must be followed by an apporpriate subcommand.\n"));
8338 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
8342 show_arm_command (char *args
, int from_tty
)
8344 cmd_show_list (showarmcmdlist
, from_tty
, "");
8348 arm_update_current_architecture (void)
8350 struct gdbarch_info info
;
8352 /* If the current architecture is not ARM, we have nothing to do. */
8353 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_arm
)
8356 /* Update the architecture. */
8357 gdbarch_info_init (&info
);
8359 if (!gdbarch_update_p (info
))
8360 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
8364 set_fp_model_sfunc (char *args
, int from_tty
,
8365 struct cmd_list_element
*c
)
8369 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
8370 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
8372 arm_fp_model
= (enum arm_float_model
) fp_model
;
8376 if (fp_model
== ARM_FLOAT_LAST
)
8377 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
8380 arm_update_current_architecture ();
8384 show_fp_model (struct ui_file
*file
, int from_tty
,
8385 struct cmd_list_element
*c
, const char *value
)
8387 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8389 if (arm_fp_model
== ARM_FLOAT_AUTO
8390 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8391 fprintf_filtered (file
, _("\
8392 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
8393 fp_model_strings
[tdep
->fp_model
]);
8395 fprintf_filtered (file
, _("\
8396 The current ARM floating point model is \"%s\".\n"),
8397 fp_model_strings
[arm_fp_model
]);
8401 arm_set_abi (char *args
, int from_tty
,
8402 struct cmd_list_element
*c
)
8406 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
8407 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
8409 arm_abi_global
= (enum arm_abi_kind
) arm_abi
;
8413 if (arm_abi
== ARM_ABI_LAST
)
8414 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
8417 arm_update_current_architecture ();
8421 arm_show_abi (struct ui_file
*file
, int from_tty
,
8422 struct cmd_list_element
*c
, const char *value
)
8424 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
8426 if (arm_abi_global
== ARM_ABI_AUTO
8427 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
8428 fprintf_filtered (file
, _("\
8429 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
8430 arm_abi_strings
[tdep
->arm_abi
]);
8432 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
8437 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
8438 struct cmd_list_element
*c
, const char *value
)
8440 fprintf_filtered (file
,
8441 _("The current execution mode assumed "
8442 "(when symbols are unavailable) is \"%s\".\n"),
8443 arm_fallback_mode_string
);
8447 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
8448 struct cmd_list_element
*c
, const char *value
)
8450 fprintf_filtered (file
,
8451 _("The current execution mode assumed "
8452 "(even when symbols are available) is \"%s\".\n"),
8453 arm_force_mode_string
);
8456 /* If the user changes the register disassembly style used for info
8457 register and other commands, we have to also switch the style used
8458 in opcodes for disassembly output. This function is run in the "set
8459 arm disassembly" command, and does that. */
8462 set_disassembly_style_sfunc (char *args
, int from_tty
,
8463 struct cmd_list_element
*c
)
8465 set_disassembly_style ();
8468 /* Return the ARM register name corresponding to register I. */
8470 arm_register_name (struct gdbarch
*gdbarch
, int i
)
8472 const int num_regs
= gdbarch_num_regs (gdbarch
);
8474 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
8475 && i
>= num_regs
&& i
< num_regs
+ 32)
8477 static const char *const vfp_pseudo_names
[] = {
8478 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
8479 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
8480 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
8481 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
8484 return vfp_pseudo_names
[i
- num_regs
];
8487 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
8488 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
8490 static const char *const neon_pseudo_names
[] = {
8491 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
8492 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
8495 return neon_pseudo_names
[i
- num_regs
- 32];
8498 if (i
>= ARRAY_SIZE (arm_register_names
))
8499 /* These registers are only supported on targets which supply
8500 an XML description. */
8503 return arm_register_names
[i
];
8507 set_disassembly_style (void)
8511 /* Find the style that the user wants. */
8512 for (current
= 0; current
< num_disassembly_options
; current
++)
8513 if (disassembly_style
== valid_disassembly_styles
[current
])
8515 gdb_assert (current
< num_disassembly_options
);
8517 /* Synchronize the disassembler. */
8518 set_arm_regname_option (current
);
8521 /* Test whether the coff symbol specific value corresponds to a Thumb
8525 coff_sym_is_thumb (int val
)
8527 return (val
== C_THUMBEXT
8528 || val
== C_THUMBSTAT
8529 || val
== C_THUMBEXTFUNC
8530 || val
== C_THUMBSTATFUNC
8531 || val
== C_THUMBLABEL
);
8534 /* arm_coff_make_msymbol_special()
8535 arm_elf_make_msymbol_special()
8537 These functions test whether the COFF or ELF symbol corresponds to
8538 an address in thumb code, and set a "special" bit in a minimal
8539 symbol to indicate that it does. */
8542 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
8544 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
8546 if (ARM_GET_SYM_BRANCH_TYPE (elfsym
->internal_elf_sym
.st_target_internal
)
8547 == ST_BRANCH_TO_THUMB
)
8548 MSYMBOL_SET_SPECIAL (msym
);
8552 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
8554 if (coff_sym_is_thumb (val
))
8555 MSYMBOL_SET_SPECIAL (msym
);
8559 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
8561 struct arm_per_objfile
*data
= (struct arm_per_objfile
*) arg
;
8564 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
8565 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
8569 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
8572 const char *name
= bfd_asymbol_name (sym
);
8573 struct arm_per_objfile
*data
;
8574 VEC(arm_mapping_symbol_s
) **map_p
;
8575 struct arm_mapping_symbol new_map_sym
;
8577 gdb_assert (name
[0] == '$');
8578 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
8581 data
= (struct arm_per_objfile
*) objfile_data (objfile
,
8582 arm_objfile_data_key
);
8585 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
8586 struct arm_per_objfile
);
8587 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
8588 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
8589 objfile
->obfd
->section_count
,
8590 VEC(arm_mapping_symbol_s
) *);
8592 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
8594 new_map_sym
.value
= sym
->value
;
8595 new_map_sym
.type
= name
[1];
8597 /* Assume that most mapping symbols appear in order of increasing
8598 value. If they were randomly distributed, it would be faster to
8599 always push here and then sort at first use. */
8600 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
8602 struct arm_mapping_symbol
*prev_map_sym
;
8604 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
8605 if (prev_map_sym
->value
>= sym
->value
)
8608 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
8609 arm_compare_mapping_symbols
);
8610 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
8615 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
8619 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
8621 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
8622 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
8624 /* If necessary, set the T bit. */
8627 ULONGEST val
, t_bit
;
8628 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
8629 t_bit
= arm_psr_thumb_bit (gdbarch
);
8630 if (arm_pc_is_thumb (gdbarch
, pc
))
8631 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8634 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
8639 /* Read the contents of a NEON quad register, by reading from two
8640 double registers. This is used to implement the quad pseudo
8641 registers, and for argument passing in case the quad registers are
8642 missing; vectors are passed in quad registers when using the VFP
8643 ABI, even if a NEON unit is not present. REGNUM is the index of
8644 the quad register, in [0, 15]. */
8646 static enum register_status
8647 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8648 int regnum
, gdb_byte
*buf
)
8651 gdb_byte reg_buf
[8];
8652 int offset
, double_regnum
;
8653 enum register_status status
;
8655 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8656 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8659 /* d0 is always the least significant half of q0. */
8660 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8665 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8666 if (status
!= REG_VALID
)
8668 memcpy (buf
+ offset
, reg_buf
, 8);
8670 offset
= 8 - offset
;
8671 status
= regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
8672 if (status
!= REG_VALID
)
8674 memcpy (buf
+ offset
, reg_buf
, 8);
8679 static enum register_status
8680 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8681 int regnum
, gdb_byte
*buf
)
8683 const int num_regs
= gdbarch_num_regs (gdbarch
);
8685 gdb_byte reg_buf
[8];
8686 int offset
, double_regnum
;
8688 gdb_assert (regnum
>= num_regs
);
8691 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8692 /* Quad-precision register. */
8693 return arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
8696 enum register_status status
;
8698 /* Single-precision register. */
8699 gdb_assert (regnum
< 32);
8701 /* s0 is always the least significant half of d0. */
8702 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8703 offset
= (regnum
& 1) ? 0 : 4;
8705 offset
= (regnum
& 1) ? 4 : 0;
8707 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8708 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8711 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8712 if (status
== REG_VALID
)
8713 memcpy (buf
, reg_buf
+ offset
, 4);
8718 /* Store the contents of BUF to a NEON quad register, by writing to
8719 two double registers. This is used to implement the quad pseudo
8720 registers, and for argument passing in case the quad registers are
8721 missing; vectors are passed in quad registers when using the VFP
8722 ABI, even if a NEON unit is not present. REGNUM is the index
8723 of the quad register, in [0, 15]. */
8726 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8727 int regnum
, const gdb_byte
*buf
)
8730 int offset
, double_regnum
;
8732 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
8733 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8736 /* d0 is always the least significant half of q0. */
8737 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8742 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
8743 offset
= 8 - offset
;
8744 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
8748 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
8749 int regnum
, const gdb_byte
*buf
)
8751 const int num_regs
= gdbarch_num_regs (gdbarch
);
8753 gdb_byte reg_buf
[8];
8754 int offset
, double_regnum
;
8756 gdb_assert (regnum
>= num_regs
);
8759 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
8760 /* Quad-precision register. */
8761 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
8764 /* Single-precision register. */
8765 gdb_assert (regnum
< 32);
8767 /* s0 is always the least significant half of d0. */
8768 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
8769 offset
= (regnum
& 1) ? 0 : 4;
8771 offset
= (regnum
& 1) ? 4 : 0;
8773 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
8774 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
8777 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
8778 memcpy (reg_buf
+ offset
, buf
, 4);
8779 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
8783 static struct value
*
8784 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
8786 const int *reg_p
= (const int *) baton
;
8787 return value_of_register (*reg_p
, frame
);
8790 static enum gdb_osabi
8791 arm_elf_osabi_sniffer (bfd
*abfd
)
8793 unsigned int elfosabi
;
8794 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
8796 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
8798 if (elfosabi
== ELFOSABI_ARM
)
8799 /* GNU tools use this value. Check note sections in this case,
8801 bfd_map_over_sections (abfd
,
8802 generic_elf_osabi_sniff_abi_tag_sections
,
8805 /* Anything else will be handled by the generic ELF sniffer. */
8810 arm_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
8811 struct reggroup
*group
)
8813 /* FPS register's type is INT, but belongs to float_reggroup. Beside
8814 this, FPS register belongs to save_regroup, restore_reggroup, and
8815 all_reggroup, of course. */
8816 if (regnum
== ARM_FPS_REGNUM
)
8817 return (group
== float_reggroup
8818 || group
== save_reggroup
8819 || group
== restore_reggroup
8820 || group
== all_reggroup
);
8822 return default_register_reggroup_p (gdbarch
, regnum
, group
);
8826 /* For backward-compatibility we allow two 'g' packet lengths with
8827 the remote protocol depending on whether FPA registers are
8828 supplied. M-profile targets do not have FPA registers, but some
8829 stubs already exist in the wild which use a 'g' packet which
8830 supplies them albeit with dummy values. The packet format which
8831 includes FPA registers should be considered deprecated for
8832 M-profile targets. */
8835 arm_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8837 if (gdbarch_tdep (gdbarch
)->is_m
)
8839 /* If we know from the executable this is an M-profile target,
8840 cater for remote targets whose register set layout is the
8841 same as the FPA layout. */
8842 register_remote_g_packet_guess (gdbarch
,
8843 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
8844 (16 * INT_REGISTER_SIZE
)
8845 + (8 * FP_REGISTER_SIZE
)
8846 + (2 * INT_REGISTER_SIZE
),
8847 tdesc_arm_with_m_fpa_layout
);
8849 /* The regular M-profile layout. */
8850 register_remote_g_packet_guess (gdbarch
,
8851 /* r0-r12,sp,lr,pc; xpsr */
8852 (16 * INT_REGISTER_SIZE
)
8853 + INT_REGISTER_SIZE
,
8856 /* M-profile plus M4F VFP. */
8857 register_remote_g_packet_guess (gdbarch
,
8858 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
8859 (16 * INT_REGISTER_SIZE
)
8860 + (16 * VFP_REGISTER_SIZE
)
8861 + (2 * INT_REGISTER_SIZE
),
8862 tdesc_arm_with_m_vfp_d16
);
8865 /* Otherwise we don't have a useful guess. */
8868 /* Implement the code_of_frame_writable gdbarch method. */
8871 arm_code_of_frame_writable (struct gdbarch
*gdbarch
, struct frame_info
*frame
)
8873 if (gdbarch_tdep (gdbarch
)->is_m
8874 && get_frame_type (frame
) == SIGTRAMP_FRAME
)
8876 /* M-profile exception frames return to some magic PCs, where
8877 isn't writable at all. */
8885 /* Initialize the current architecture based on INFO. If possible,
8886 re-use an architecture from ARCHES, which is a list of
8887 architectures already created during this debugging session.
8889 Called e.g. at program startup, when reading a core file, and when
8890 reading a binary file. */
8892 static struct gdbarch
*
8893 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8895 struct gdbarch_tdep
*tdep
;
8896 struct gdbarch
*gdbarch
;
8897 struct gdbarch_list
*best_arch
;
8898 enum arm_abi_kind arm_abi
= arm_abi_global
;
8899 enum arm_float_model fp_model
= arm_fp_model
;
8900 struct tdesc_arch_data
*tdesc_data
= NULL
;
8902 int vfp_register_count
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
8903 int have_wmmx_registers
= 0;
8905 int have_fpa_registers
= 1;
8906 const struct target_desc
*tdesc
= info
.target_desc
;
8908 /* If we have an object to base this architecture on, try to determine
8911 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
8913 int ei_osabi
, e_flags
;
8915 switch (bfd_get_flavour (info
.abfd
))
8917 case bfd_target_aout_flavour
:
8918 /* Assume it's an old APCS-style ABI. */
8919 arm_abi
= ARM_ABI_APCS
;
8922 case bfd_target_coff_flavour
:
8923 /* Assume it's an old APCS-style ABI. */
8925 arm_abi
= ARM_ABI_APCS
;
8928 case bfd_target_elf_flavour
:
8929 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
8930 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8932 if (ei_osabi
== ELFOSABI_ARM
)
8934 /* GNU tools used to use this value, but do not for EABI
8935 objects. There's nowhere to tag an EABI version
8936 anyway, so assume APCS. */
8937 arm_abi
= ARM_ABI_APCS
;
8939 else if (ei_osabi
== ELFOSABI_NONE
|| ei_osabi
== ELFOSABI_GNU
)
8941 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
8942 int attr_arch
, attr_profile
;
8946 case EF_ARM_EABI_UNKNOWN
:
8947 /* Assume GNU tools. */
8948 arm_abi
= ARM_ABI_APCS
;
8951 case EF_ARM_EABI_VER4
:
8952 case EF_ARM_EABI_VER5
:
8953 arm_abi
= ARM_ABI_AAPCS
;
8954 /* EABI binaries default to VFP float ordering.
8955 They may also contain build attributes that can
8956 be used to identify if the VFP argument-passing
8958 if (fp_model
== ARM_FLOAT_AUTO
)
8961 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
8965 case AEABI_VFP_args_base
:
8966 /* "The user intended FP parameter/result
8967 passing to conform to AAPCS, base
8969 fp_model
= ARM_FLOAT_SOFT_VFP
;
8971 case AEABI_VFP_args_vfp
:
8972 /* "The user intended FP parameter/result
8973 passing to conform to AAPCS, VFP
8975 fp_model
= ARM_FLOAT_VFP
;
8977 case AEABI_VFP_args_toolchain
:
8978 /* "The user intended FP parameter/result
8979 passing to conform to tool chain-specific
8980 conventions" - we don't know any such
8981 conventions, so leave it as "auto". */
8983 case AEABI_VFP_args_compatible
:
8984 /* "Code is compatible with both the base
8985 and VFP variants; the user did not permit
8986 non-variadic functions to pass FP
8987 parameters/results" - leave it as
8991 /* Attribute value not mentioned in the
8992 November 2012 ABI, so leave it as
8997 fp_model
= ARM_FLOAT_SOFT_VFP
;
9003 /* Leave it as "auto". */
9004 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
9009 /* Detect M-profile programs. This only works if the
9010 executable file includes build attributes; GCC does
9011 copy them to the executable, but e.g. RealView does
9013 attr_arch
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
9015 attr_profile
= bfd_elf_get_obj_attr_int (info
.abfd
,
9017 Tag_CPU_arch_profile
);
9018 /* GCC specifies the profile for v6-M; RealView only
9019 specifies the profile for architectures starting with
9020 V7 (as opposed to architectures with a tag
9021 numerically greater than TAG_CPU_ARCH_V7). */
9022 if (!tdesc_has_registers (tdesc
)
9023 && (attr_arch
== TAG_CPU_ARCH_V6_M
9024 || attr_arch
== TAG_CPU_ARCH_V6S_M
9025 || attr_profile
== 'M'))
9030 if (fp_model
== ARM_FLOAT_AUTO
)
9032 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9034 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
9037 /* Leave it as "auto". Strictly speaking this case
9038 means FPA, but almost nobody uses that now, and
9039 many toolchains fail to set the appropriate bits
9040 for the floating-point model they use. */
9042 case EF_ARM_SOFT_FLOAT
:
9043 fp_model
= ARM_FLOAT_SOFT_FPA
;
9045 case EF_ARM_VFP_FLOAT
:
9046 fp_model
= ARM_FLOAT_VFP
;
9048 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
9049 fp_model
= ARM_FLOAT_SOFT_VFP
;
9054 if (e_flags
& EF_ARM_BE8
)
9055 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
9060 /* Leave it as "auto". */
9065 /* Check any target description for validity. */
9066 if (tdesc_has_registers (tdesc
))
9068 /* For most registers we require GDB's default names; but also allow
9069 the numeric names for sp / lr / pc, as a convenience. */
9070 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
9071 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
9072 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
9074 const struct tdesc_feature
*feature
;
9077 feature
= tdesc_find_feature (tdesc
,
9078 "org.gnu.gdb.arm.core");
9079 if (feature
== NULL
)
9081 feature
= tdesc_find_feature (tdesc
,
9082 "org.gnu.gdb.arm.m-profile");
9083 if (feature
== NULL
)
9089 tdesc_data
= tdesc_data_alloc ();
9092 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
9093 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9094 arm_register_names
[i
]);
9095 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9098 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9101 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
9105 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9106 ARM_PS_REGNUM
, "xpsr");
9108 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9109 ARM_PS_REGNUM
, "cpsr");
9113 tdesc_data_cleanup (tdesc_data
);
9117 feature
= tdesc_find_feature (tdesc
,
9118 "org.gnu.gdb.arm.fpa");
9119 if (feature
!= NULL
)
9122 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
9123 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
9124 arm_register_names
[i
]);
9127 tdesc_data_cleanup (tdesc_data
);
9132 have_fpa_registers
= 0;
9134 feature
= tdesc_find_feature (tdesc
,
9135 "org.gnu.gdb.xscale.iwmmxt");
9136 if (feature
!= NULL
)
9138 static const char *const iwmmxt_names
[] = {
9139 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
9140 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
9141 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
9142 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
9146 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
9148 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9149 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9151 /* Check for the control registers, but do not fail if they
9153 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
9154 tdesc_numbered_register (feature
, tdesc_data
, i
,
9155 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9157 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
9159 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
9160 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
9164 tdesc_data_cleanup (tdesc_data
);
9168 have_wmmx_registers
= 1;
9171 /* If we have a VFP unit, check whether the single precision registers
9172 are present. If not, then we will synthesize them as pseudo
9174 feature
= tdesc_find_feature (tdesc
,
9175 "org.gnu.gdb.arm.vfp");
9176 if (feature
!= NULL
)
9178 static const char *const vfp_double_names
[] = {
9179 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
9180 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
9181 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
9182 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
9185 /* Require the double precision registers. There must be either
9188 for (i
= 0; i
< 32; i
++)
9190 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9192 vfp_double_names
[i
]);
9196 if (!valid_p
&& i
== 16)
9199 /* Also require FPSCR. */
9200 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
9201 ARM_FPSCR_REGNUM
, "fpscr");
9204 tdesc_data_cleanup (tdesc_data
);
9208 if (tdesc_unnumbered_register (feature
, "s0") == 0)
9209 have_vfp_pseudos
= 1;
9211 vfp_register_count
= i
;
9213 /* If we have VFP, also check for NEON. The architecture allows
9214 NEON without VFP (integer vector operations only), but GDB
9215 does not support that. */
9216 feature
= tdesc_find_feature (tdesc
,
9217 "org.gnu.gdb.arm.neon");
9218 if (feature
!= NULL
)
9220 /* NEON requires 32 double-precision registers. */
9223 tdesc_data_cleanup (tdesc_data
);
9227 /* If there are quad registers defined by the stub, use
9228 their type; otherwise (normally) provide them with
9229 the default type. */
9230 if (tdesc_unnumbered_register (feature
, "q0") == 0)
9231 have_neon_pseudos
= 1;
9238 /* If there is already a candidate, use it. */
9239 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
9241 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
9243 if (arm_abi
!= ARM_ABI_AUTO
9244 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
9247 if (fp_model
!= ARM_FLOAT_AUTO
9248 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
9251 /* There are various other properties in tdep that we do not
9252 need to check here: those derived from a target description,
9253 since gdbarches with a different target description are
9254 automatically disqualified. */
9256 /* Do check is_m, though, since it might come from the binary. */
9257 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
9260 /* Found a match. */
9264 if (best_arch
!= NULL
)
9266 if (tdesc_data
!= NULL
)
9267 tdesc_data_cleanup (tdesc_data
);
9268 return best_arch
->gdbarch
;
9271 tdep
= XCNEW (struct gdbarch_tdep
);
9272 gdbarch
= gdbarch_alloc (&info
, tdep
);
9274 /* Record additional information about the architecture we are defining.
9275 These are gdbarch discriminators, like the OSABI. */
9276 tdep
->arm_abi
= arm_abi
;
9277 tdep
->fp_model
= fp_model
;
9279 tdep
->have_fpa_registers
= have_fpa_registers
;
9280 tdep
->have_wmmx_registers
= have_wmmx_registers
;
9281 gdb_assert (vfp_register_count
== 0
9282 || vfp_register_count
== 16
9283 || vfp_register_count
== 32);
9284 tdep
->vfp_register_count
= vfp_register_count
;
9285 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
9286 tdep
->have_neon_pseudos
= have_neon_pseudos
;
9287 tdep
->have_neon
= have_neon
;
9289 arm_register_g_packet_guesses (gdbarch
);
9292 switch (info
.byte_order_for_code
)
9294 case BFD_ENDIAN_BIG
:
9295 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
9296 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
9297 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
9298 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
9302 case BFD_ENDIAN_LITTLE
:
9303 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
9304 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
9305 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
9306 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
9311 internal_error (__FILE__
, __LINE__
,
9312 _("arm_gdbarch_init: bad byte order for float format"));
9315 /* On ARM targets char defaults to unsigned. */
9316 set_gdbarch_char_signed (gdbarch
, 0);
9318 /* Note: for displaced stepping, this includes the breakpoint, and one word
9319 of additional scratch space. This setting isn't used for anything beside
9320 displaced stepping at present. */
9321 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
9323 /* This should be low enough for everything. */
9324 tdep
->lowest_pc
= 0x20;
9325 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
9327 /* The default, for both APCS and AAPCS, is to return small
9328 structures in registers. */
9329 tdep
->struct_return
= reg_struct_return
;
9331 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
9332 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
9335 set_gdbarch_code_of_frame_writable (gdbarch
, arm_code_of_frame_writable
);
9337 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
9339 /* Frame handling. */
9340 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
9341 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
9342 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
9344 frame_base_set_default (gdbarch
, &arm_normal_base
);
9346 /* Address manipulation. */
9347 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
9349 /* Advance PC across function entry code. */
9350 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
9352 /* Detect whether PC is at a point where the stack has been destroyed. */
9353 set_gdbarch_stack_frame_destroyed_p (gdbarch
, arm_stack_frame_destroyed_p
);
9355 /* Skip trampolines. */
9356 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
9358 /* The stack grows downward. */
9359 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
9361 /* Breakpoint manipulation. */
9362 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
9363 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
9364 arm_remote_breakpoint_from_pc
);
9366 /* Information about registers, etc. */
9367 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
9368 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
9369 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
9370 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9371 set_gdbarch_register_reggroup_p (gdbarch
, arm_register_reggroup_p
);
9373 /* This "info float" is FPA-specific. Use the generic version if we
9375 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
9376 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
9378 /* Internal <-> external register number maps. */
9379 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
9380 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
9382 set_gdbarch_register_name (gdbarch
, arm_register_name
);
9384 /* Returning results. */
9385 set_gdbarch_return_value (gdbarch
, arm_return_value
);
9388 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
9390 /* Minsymbol frobbing. */
9391 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
9392 set_gdbarch_coff_make_msymbol_special (gdbarch
,
9393 arm_coff_make_msymbol_special
);
9394 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
9396 /* Thumb-2 IT block support. */
9397 set_gdbarch_adjust_breakpoint_address (gdbarch
,
9398 arm_adjust_breakpoint_address
);
9400 /* Virtual tables. */
9401 set_gdbarch_vbit_in_delta (gdbarch
, 1);
9403 /* Hook in the ABI-specific overrides, if they have been registered. */
9404 gdbarch_init_osabi (info
, gdbarch
);
9406 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
9408 /* Add some default predicates. */
9410 frame_unwind_append_unwinder (gdbarch
, &arm_m_exception_unwind
);
9411 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
9412 dwarf2_append_unwinders (gdbarch
);
9413 frame_unwind_append_unwinder (gdbarch
, &arm_exidx_unwind
);
9414 frame_unwind_append_unwinder (gdbarch
, &arm_epilogue_frame_unwind
);
9415 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
9417 /* Now we have tuned the configuration, set a few final things,
9418 based on what the OS ABI has told us. */
9420 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
9421 binaries are always marked. */
9422 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
9423 tdep
->arm_abi
= ARM_ABI_APCS
;
9425 /* Watchpoints are not steppable. */
9426 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
9428 /* We used to default to FPA for generic ARM, but almost nobody
9429 uses that now, and we now provide a way for the user to force
9430 the model. So default to the most useful variant. */
9431 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
9432 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
9434 if (tdep
->jb_pc
>= 0)
9435 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
9437 /* Floating point sizes and format. */
9438 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
9439 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
9441 set_gdbarch_double_format
9442 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9443 set_gdbarch_long_double_format
9444 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
9448 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
9449 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
9452 if (have_vfp_pseudos
)
9454 /* NOTE: These are the only pseudo registers used by
9455 the ARM target at the moment. If more are added, a
9456 little more care in numbering will be needed. */
9458 int num_pseudos
= 32;
9459 if (have_neon_pseudos
)
9461 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
9462 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
9463 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
9468 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
9470 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
9472 /* Override tdesc_register_type to adjust the types of VFP
9473 registers for NEON. */
9474 set_gdbarch_register_type (gdbarch
, arm_register_type
);
9477 /* Add standard register aliases. We add aliases even for those
9478 nanes which are used by the current architecture - it's simpler,
9479 and does no harm, since nothing ever lists user registers. */
9480 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
9481 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
9482 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
9488 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
9490 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9495 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
9496 (unsigned long) tdep
->lowest_pc
);
9499 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
9502 _initialize_arm_tdep (void)
9504 struct ui_file
*stb
;
9506 const char *setname
;
9507 const char *setdesc
;
9508 const char *const *regnames
;
9510 static char *helptext
;
9511 char regdesc
[1024], *rdptr
= regdesc
;
9512 size_t rest
= sizeof (regdesc
);
9514 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
9516 arm_objfile_data_key
9517 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
9519 /* Add ourselves to objfile event chain. */
9520 observer_attach_new_objfile (arm_exidx_new_objfile
);
9522 = register_objfile_data_with_cleanup (NULL
, arm_exidx_data_free
);
9524 /* Register an ELF OS ABI sniffer for ARM binaries. */
9525 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
9526 bfd_target_elf_flavour
,
9527 arm_elf_osabi_sniffer
);
9529 /* Initialize the standard target descriptions. */
9530 initialize_tdesc_arm_with_m ();
9531 initialize_tdesc_arm_with_m_fpa_layout ();
9532 initialize_tdesc_arm_with_m_vfp_d16 ();
9533 initialize_tdesc_arm_with_iwmmxt ();
9534 initialize_tdesc_arm_with_vfpv2 ();
9535 initialize_tdesc_arm_with_vfpv3 ();
9536 initialize_tdesc_arm_with_neon ();
9538 /* Get the number of possible sets of register names defined in opcodes. */
9539 num_disassembly_options
= get_arm_regname_num_options ();
9541 /* Add root prefix command for all "set arm"/"show arm" commands. */
9542 add_prefix_cmd ("arm", no_class
, set_arm_command
,
9543 _("Various ARM-specific commands."),
9544 &setarmcmdlist
, "set arm ", 0, &setlist
);
9546 add_prefix_cmd ("arm", no_class
, show_arm_command
,
9547 _("Various ARM-specific commands."),
9548 &showarmcmdlist
, "show arm ", 0, &showlist
);
9550 /* Sync the opcode insn printer with our register viewer. */
9551 parse_arm_disassembler_option ("reg-names-std");
9553 /* Initialize the array that will be passed to
9554 add_setshow_enum_cmd(). */
9555 valid_disassembly_styles
= XNEWVEC (const char *,
9556 num_disassembly_options
+ 1);
9557 for (i
= 0; i
< num_disassembly_options
; i
++)
9559 get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
9560 valid_disassembly_styles
[i
] = setname
;
9561 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
9564 /* When we find the default names, tell the disassembler to use
9566 if (!strcmp (setname
, "std"))
9568 disassembly_style
= setname
;
9569 set_arm_regname_option (i
);
9572 /* Mark the end of valid options. */
9573 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
9575 /* Create the help text. */
9576 stb
= mem_fileopen ();
9577 fprintf_unfiltered (stb
, "%s%s%s",
9578 _("The valid values are:\n"),
9580 _("The default is \"std\"."));
9581 helptext
= ui_file_xstrdup (stb
, NULL
);
9582 ui_file_delete (stb
);
9584 add_setshow_enum_cmd("disassembler", no_class
,
9585 valid_disassembly_styles
, &disassembly_style
,
9586 _("Set the disassembly style."),
9587 _("Show the disassembly style."),
9589 set_disassembly_style_sfunc
,
9590 NULL
, /* FIXME: i18n: The disassembly style is
9592 &setarmcmdlist
, &showarmcmdlist
);
9594 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
9595 _("Set usage of ARM 32-bit mode."),
9596 _("Show usage of ARM 32-bit mode."),
9597 _("When off, a 26-bit PC will be used."),
9599 NULL
, /* FIXME: i18n: Usage of ARM 32-bit
9601 &setarmcmdlist
, &showarmcmdlist
);
9603 /* Add a command to allow the user to force the FPU model. */
9604 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
9605 _("Set the floating point type."),
9606 _("Show the floating point type."),
9607 _("auto - Determine the FP typefrom the OS-ABI.\n\
9608 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
9609 fpa - FPA co-processor (GCC compiled).\n\
9610 softvfp - Software FP with pure-endian doubles.\n\
9611 vfp - VFP co-processor."),
9612 set_fp_model_sfunc
, show_fp_model
,
9613 &setarmcmdlist
, &showarmcmdlist
);
9615 /* Add a command to allow the user to force the ABI. */
9616 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
9619 NULL
, arm_set_abi
, arm_show_abi
,
9620 &setarmcmdlist
, &showarmcmdlist
);
9622 /* Add two commands to allow the user to force the assumed
9624 add_setshow_enum_cmd ("fallback-mode", class_support
,
9625 arm_mode_strings
, &arm_fallback_mode_string
,
9626 _("Set the mode assumed when symbols are unavailable."),
9627 _("Show the mode assumed when symbols are unavailable."),
9628 NULL
, NULL
, arm_show_fallback_mode
,
9629 &setarmcmdlist
, &showarmcmdlist
);
9630 add_setshow_enum_cmd ("force-mode", class_support
,
9631 arm_mode_strings
, &arm_force_mode_string
,
9632 _("Set the mode assumed even when symbols are available."),
9633 _("Show the mode assumed even when symbols are available."),
9634 NULL
, NULL
, arm_show_force_mode
,
9635 &setarmcmdlist
, &showarmcmdlist
);
9637 /* Debugging flag. */
9638 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
9639 _("Set ARM debugging."),
9640 _("Show ARM debugging."),
9641 _("When on, arm-specific debugging is enabled."),
9643 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
9644 &setdebuglist
, &showdebuglist
);
9647 /* ARM-reversible process record data structures. */
9649 #define ARM_INSN_SIZE_BYTES 4
9650 #define THUMB_INSN_SIZE_BYTES 2
9651 #define THUMB2_INSN_SIZE_BYTES 4
9654 /* Position of the bit within a 32-bit ARM instruction
9655 that defines whether the instruction is a load or store. */
9656 #define INSN_S_L_BIT_NUM 20
9658 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
9661 unsigned int reg_len = LENGTH; \
9664 REGS = XNEWVEC (uint32_t, reg_len); \
9665 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
9670 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
9673 unsigned int mem_len = LENGTH; \
9676 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
9677 memcpy(&MEMS->len, &RECORD_BUF[0], \
9678 sizeof(struct arm_mem_r) * LENGTH); \
9683 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
9684 #define INSN_RECORDED(ARM_RECORD) \
9685 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
9687 /* ARM memory record structure. */
9690 uint32_t len
; /* Record length. */
9691 uint32_t addr
; /* Memory address. */
9694 /* ARM instruction record contains opcode of current insn
9695 and execution state (before entry to decode_insn()),
9696 contains list of to-be-modified registers and
9697 memory blocks (on return from decode_insn()). */
9699 typedef struct insn_decode_record_t
9701 struct gdbarch
*gdbarch
;
9702 struct regcache
*regcache
;
9703 CORE_ADDR this_addr
; /* Address of the insn being decoded. */
9704 uint32_t arm_insn
; /* Should accommodate thumb. */
9705 uint32_t cond
; /* Condition code. */
9706 uint32_t opcode
; /* Insn opcode. */
9707 uint32_t decode
; /* Insn decode bits. */
9708 uint32_t mem_rec_count
; /* No of mem records. */
9709 uint32_t reg_rec_count
; /* No of reg records. */
9710 uint32_t *arm_regs
; /* Registers to be saved for this record. */
9711 struct arm_mem_r
*arm_mems
; /* Memory to be saved for this record. */
9712 } insn_decode_record
;
9715 /* Checks ARM SBZ and SBO mandatory fields. */
9718 sbo_sbz (uint32_t insn
, uint32_t bit_num
, uint32_t len
, uint32_t sbo
)
9720 uint32_t ones
= bits (insn
, bit_num
- 1, (bit_num
-1) + (len
- 1));
9739 enum arm_record_result
9741 ARM_RECORD_SUCCESS
= 0,
9742 ARM_RECORD_FAILURE
= 1
9749 } arm_record_strx_t
;
9760 arm_record_strx (insn_decode_record
*arm_insn_r
, uint32_t *record_buf
,
9761 uint32_t *record_buf_mem
, arm_record_strx_t str_type
)
9764 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
9765 ULONGEST u_regval
[2]= {0};
9767 uint32_t reg_src1
= 0, reg_src2
= 0;
9768 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
9770 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
9771 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
9773 if (14 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
9775 /* 1) Handle misc store, immediate offset. */
9776 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9777 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9778 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9779 regcache_raw_read_unsigned (reg_cache
, reg_src1
,
9781 if (ARM_PC_REGNUM
== reg_src1
)
9783 /* If R15 was used as Rn, hence current PC+8. */
9784 u_regval
[0] = u_regval
[0] + 8;
9786 offset_8
= (immed_high
<< 4) | immed_low
;
9787 /* Calculate target store address. */
9788 if (14 == arm_insn_r
->opcode
)
9790 tgt_mem_addr
= u_regval
[0] + offset_8
;
9794 tgt_mem_addr
= u_regval
[0] - offset_8
;
9796 if (ARM_RECORD_STRH
== str_type
)
9798 record_buf_mem
[0] = 2;
9799 record_buf_mem
[1] = tgt_mem_addr
;
9800 arm_insn_r
->mem_rec_count
= 1;
9802 else if (ARM_RECORD_STRD
== str_type
)
9804 record_buf_mem
[0] = 4;
9805 record_buf_mem
[1] = tgt_mem_addr
;
9806 record_buf_mem
[2] = 4;
9807 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9808 arm_insn_r
->mem_rec_count
= 2;
9811 else if (12 == arm_insn_r
->opcode
|| 8 == arm_insn_r
->opcode
)
9813 /* 2) Store, register offset. */
9815 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9817 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9818 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9819 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9822 /* If R15 was used as Rn, hence current PC+8. */
9823 u_regval
[0] = u_regval
[0] + 8;
9825 /* Calculate target store address, Rn +/- Rm, register offset. */
9826 if (12 == arm_insn_r
->opcode
)
9828 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9832 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9834 if (ARM_RECORD_STRH
== str_type
)
9836 record_buf_mem
[0] = 2;
9837 record_buf_mem
[1] = tgt_mem_addr
;
9838 arm_insn_r
->mem_rec_count
= 1;
9840 else if (ARM_RECORD_STRD
== str_type
)
9842 record_buf_mem
[0] = 4;
9843 record_buf_mem
[1] = tgt_mem_addr
;
9844 record_buf_mem
[2] = 4;
9845 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9846 arm_insn_r
->mem_rec_count
= 2;
9849 else if (11 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
9850 || 2 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9852 /* 3) Store, immediate pre-indexed. */
9853 /* 5) Store, immediate post-indexed. */
9854 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
9855 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
9856 offset_8
= (immed_high
<< 4) | immed_low
;
9857 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
9858 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9859 /* Calculate target store address, Rn +/- Rm, register offset. */
9860 if (15 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
9862 tgt_mem_addr
= u_regval
[0] + offset_8
;
9866 tgt_mem_addr
= u_regval
[0] - offset_8
;
9868 if (ARM_RECORD_STRH
== str_type
)
9870 record_buf_mem
[0] = 2;
9871 record_buf_mem
[1] = tgt_mem_addr
;
9872 arm_insn_r
->mem_rec_count
= 1;
9874 else if (ARM_RECORD_STRD
== str_type
)
9876 record_buf_mem
[0] = 4;
9877 record_buf_mem
[1] = tgt_mem_addr
;
9878 record_buf_mem
[2] = 4;
9879 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9880 arm_insn_r
->mem_rec_count
= 2;
9882 /* Record Rn also as it changes. */
9883 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
9884 arm_insn_r
->reg_rec_count
= 1;
9886 else if (9 == arm_insn_r
->opcode
|| 13 == arm_insn_r
->opcode
9887 || 0 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9889 /* 4) Store, register pre-indexed. */
9890 /* 6) Store, register post -indexed. */
9891 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
9892 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
9893 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
9894 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
9895 /* Calculate target store address, Rn +/- Rm, register offset. */
9896 if (13 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
9898 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
9902 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
9904 if (ARM_RECORD_STRH
== str_type
)
9906 record_buf_mem
[0] = 2;
9907 record_buf_mem
[1] = tgt_mem_addr
;
9908 arm_insn_r
->mem_rec_count
= 1;
9910 else if (ARM_RECORD_STRD
== str_type
)
9912 record_buf_mem
[0] = 4;
9913 record_buf_mem
[1] = tgt_mem_addr
;
9914 record_buf_mem
[2] = 4;
9915 record_buf_mem
[3] = tgt_mem_addr
+ 4;
9916 arm_insn_r
->mem_rec_count
= 2;
9918 /* Record Rn also as it changes. */
9919 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
9920 arm_insn_r
->reg_rec_count
= 1;
9925 /* Handling ARM extension space insns. */
9928 arm_record_extension_space (insn_decode_record
*arm_insn_r
)
9930 uint32_t ret
= 0; /* Return value: -1:record failure ; 0:success */
9931 uint32_t opcode1
= 0, opcode2
= 0, insn_op1
= 0;
9932 uint32_t record_buf
[8], record_buf_mem
[8];
9933 uint32_t reg_src1
= 0;
9934 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
9935 ULONGEST u_regval
= 0;
9937 gdb_assert (!INSN_RECORDED(arm_insn_r
));
9938 /* Handle unconditional insn extension space. */
9940 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 27);
9941 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
9942 if (arm_insn_r
->cond
)
9944 /* PLD has no affect on architectural state, it just affects
9946 if (5 == ((opcode1
& 0xE0) >> 5))
9949 record_buf
[0] = ARM_PS_REGNUM
;
9950 record_buf
[1] = ARM_LR_REGNUM
;
9951 arm_insn_r
->reg_rec_count
= 2;
9953 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
9957 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
9958 if (3 == opcode1
&& bit (arm_insn_r
->arm_insn
, 4))
9961 /* Undefined instruction on ARM V5; need to handle if later
9962 versions define it. */
9965 opcode1
= bits (arm_insn_r
->arm_insn
, 24, 27);
9966 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
9967 insn_op1
= bits (arm_insn_r
->arm_insn
, 20, 23);
9969 /* Handle arithmetic insn extension space. */
9970 if (!opcode1
&& 9 == opcode2
&& 1 != arm_insn_r
->cond
9971 && !INSN_RECORDED(arm_insn_r
))
9973 /* Handle MLA(S) and MUL(S). */
9974 if (0 <= insn_op1
&& 3 >= insn_op1
)
9976 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
9977 record_buf
[1] = ARM_PS_REGNUM
;
9978 arm_insn_r
->reg_rec_count
= 2;
9980 else if (4 <= insn_op1
&& 15 >= insn_op1
)
9982 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
9983 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
9984 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
9985 record_buf
[2] = ARM_PS_REGNUM
;
9986 arm_insn_r
->reg_rec_count
= 3;
9990 opcode1
= bits (arm_insn_r
->arm_insn
, 26, 27);
9991 opcode2
= bits (arm_insn_r
->arm_insn
, 23, 24);
9992 insn_op1
= bits (arm_insn_r
->arm_insn
, 21, 22);
9994 /* Handle control insn extension space. */
9996 if (!opcode1
&& 2 == opcode2
&& !bit (arm_insn_r
->arm_insn
, 20)
9997 && 1 != arm_insn_r
->cond
&& !INSN_RECORDED(arm_insn_r
))
9999 if (!bit (arm_insn_r
->arm_insn
,25))
10001 if (!bits (arm_insn_r
->arm_insn
, 4, 7))
10003 if ((0 == insn_op1
) || (2 == insn_op1
))
10006 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10007 arm_insn_r
->reg_rec_count
= 1;
10009 else if (1 == insn_op1
)
10011 /* CSPR is going to be changed. */
10012 record_buf
[0] = ARM_PS_REGNUM
;
10013 arm_insn_r
->reg_rec_count
= 1;
10015 else if (3 == insn_op1
)
10017 /* SPSR is going to be changed. */
10018 /* We need to get SPSR value, which is yet to be done. */
10022 else if (1 == bits (arm_insn_r
->arm_insn
, 4, 7))
10027 record_buf
[0] = ARM_PS_REGNUM
;
10028 arm_insn_r
->reg_rec_count
= 1;
10030 else if (3 == insn_op1
)
10033 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10034 arm_insn_r
->reg_rec_count
= 1;
10037 else if (3 == bits (arm_insn_r
->arm_insn
, 4, 7))
10040 record_buf
[0] = ARM_PS_REGNUM
;
10041 record_buf
[1] = ARM_LR_REGNUM
;
10042 arm_insn_r
->reg_rec_count
= 2;
10044 else if (5 == bits (arm_insn_r
->arm_insn
, 4, 7))
10046 /* QADD, QSUB, QDADD, QDSUB */
10047 record_buf
[0] = ARM_PS_REGNUM
;
10048 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10049 arm_insn_r
->reg_rec_count
= 2;
10051 else if (7 == bits (arm_insn_r
->arm_insn
, 4, 7))
10054 record_buf
[0] = ARM_PS_REGNUM
;
10055 record_buf
[1] = ARM_LR_REGNUM
;
10056 arm_insn_r
->reg_rec_count
= 2;
10058 /* Save SPSR also;how? */
10061 else if(8 == bits (arm_insn_r
->arm_insn
, 4, 7)
10062 || 10 == bits (arm_insn_r
->arm_insn
, 4, 7)
10063 || 12 == bits (arm_insn_r
->arm_insn
, 4, 7)
10064 || 14 == bits (arm_insn_r
->arm_insn
, 4, 7)
10067 if (0 == insn_op1
|| 1 == insn_op1
)
10069 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
10070 /* We dont do optimization for SMULW<y> where we
10072 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10073 record_buf
[1] = ARM_PS_REGNUM
;
10074 arm_insn_r
->reg_rec_count
= 2;
10076 else if (2 == insn_op1
)
10079 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10080 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
10081 arm_insn_r
->reg_rec_count
= 2;
10083 else if (3 == insn_op1
)
10086 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10087 arm_insn_r
->reg_rec_count
= 1;
10093 /* MSR : immediate form. */
10096 /* CSPR is going to be changed. */
10097 record_buf
[0] = ARM_PS_REGNUM
;
10098 arm_insn_r
->reg_rec_count
= 1;
10100 else if (3 == insn_op1
)
10102 /* SPSR is going to be changed. */
10103 /* we need to get SPSR value, which is yet to be done */
10109 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10110 opcode2
= bits (arm_insn_r
->arm_insn
, 20, 24);
10111 insn_op1
= bits (arm_insn_r
->arm_insn
, 5, 6);
10113 /* Handle load/store insn extension space. */
10115 if (!opcode1
&& bit (arm_insn_r
->arm_insn
, 7)
10116 && bit (arm_insn_r
->arm_insn
, 4) && 1 != arm_insn_r
->cond
10117 && !INSN_RECORDED(arm_insn_r
))
10122 /* These insn, changes register and memory as well. */
10123 /* SWP or SWPB insn. */
10124 /* Get memory address given by Rn. */
10125 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10126 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
10127 /* SWP insn ?, swaps word. */
10128 if (8 == arm_insn_r
->opcode
)
10130 record_buf_mem
[0] = 4;
10134 /* SWPB insn, swaps only byte. */
10135 record_buf_mem
[0] = 1;
10137 record_buf_mem
[1] = u_regval
;
10138 arm_insn_r
->mem_rec_count
= 1;
10139 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10140 arm_insn_r
->reg_rec_count
= 1;
10142 else if (1 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10145 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10148 else if (2 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10151 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10152 record_buf
[1] = record_buf
[0] + 1;
10153 arm_insn_r
->reg_rec_count
= 2;
10155 else if (3 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
10158 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10161 else if (bit (arm_insn_r
->arm_insn
, 20) && insn_op1
<= 3)
10163 /* LDRH, LDRSB, LDRSH. */
10164 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10165 arm_insn_r
->reg_rec_count
= 1;
10170 opcode1
= bits (arm_insn_r
->arm_insn
, 23, 27);
10171 if (24 == opcode1
&& bit (arm_insn_r
->arm_insn
, 21)
10172 && !INSN_RECORDED(arm_insn_r
))
10175 /* Handle coprocessor insn extension space. */
10178 /* To be done for ARMv5 and later; as of now we return -1. */
10182 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10183 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10188 /* Handling opcode 000 insns. */
10191 arm_record_data_proc_misc_ld_str (insn_decode_record
*arm_insn_r
)
10193 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10194 uint32_t record_buf
[8], record_buf_mem
[8];
10195 ULONGEST u_regval
[2] = {0};
10197 uint32_t reg_src1
= 0, reg_dest
= 0;
10198 uint32_t opcode1
= 0;
10200 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10201 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10202 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
10204 /* Data processing insn /multiply insn. */
10205 if (9 == arm_insn_r
->decode
10206 && ((4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
10207 || (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)))
10209 /* Handle multiply instructions. */
10210 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
10211 if (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)
10213 /* Handle MLA and MUL. */
10214 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10215 record_buf
[1] = ARM_PS_REGNUM
;
10216 arm_insn_r
->reg_rec_count
= 2;
10218 else if (4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
10220 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
10221 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10222 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10223 record_buf
[2] = ARM_PS_REGNUM
;
10224 arm_insn_r
->reg_rec_count
= 3;
10227 else if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
10228 && (11 == arm_insn_r
->decode
|| 13 == arm_insn_r
->decode
))
10230 /* Handle misc load insns, as 20th bit (L = 1). */
10231 /* LDR insn has a capability to do branching, if
10232 MOV LR, PC is precceded by LDR insn having Rn as R15
10233 in that case, it emulates branch and link insn, and hence we
10234 need to save CSPR and PC as well. I am not sure this is right
10235 place; as opcode = 010 LDR insn make this happen, if R15 was
10237 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10238 if (15 != reg_dest
)
10240 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10241 arm_insn_r
->reg_rec_count
= 1;
10245 record_buf
[0] = reg_dest
;
10246 record_buf
[1] = ARM_PS_REGNUM
;
10247 arm_insn_r
->reg_rec_count
= 2;
10250 else if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
10251 && sbo_sbz (arm_insn_r
->arm_insn
, 5, 12, 0)
10252 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
10253 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21))
10255 /* Handle MSR insn. */
10256 if (9 == arm_insn_r
->opcode
)
10258 /* CSPR is going to be changed. */
10259 record_buf
[0] = ARM_PS_REGNUM
;
10260 arm_insn_r
->reg_rec_count
= 1;
10264 /* SPSR is going to be changed. */
10265 /* How to read SPSR value? */
10269 else if (9 == arm_insn_r
->decode
10270 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10271 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10273 /* Handling SWP, SWPB. */
10274 /* These insn, changes register and memory as well. */
10275 /* SWP or SWPB insn. */
10277 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10278 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10279 /* SWP insn ?, swaps word. */
10280 if (8 == arm_insn_r
->opcode
)
10282 record_buf_mem
[0] = 4;
10286 /* SWPB insn, swaps only byte. */
10287 record_buf_mem
[0] = 1;
10289 record_buf_mem
[1] = u_regval
[0];
10290 arm_insn_r
->mem_rec_count
= 1;
10291 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10292 arm_insn_r
->reg_rec_count
= 1;
10294 else if (3 == arm_insn_r
->decode
&& 0x12 == opcode1
10295 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10297 /* Handle BLX, branch and link/exchange. */
10298 if (9 == arm_insn_r
->opcode
)
10300 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
10301 and R14 stores the return address. */
10302 record_buf
[0] = ARM_PS_REGNUM
;
10303 record_buf
[1] = ARM_LR_REGNUM
;
10304 arm_insn_r
->reg_rec_count
= 2;
10307 else if (7 == arm_insn_r
->decode
&& 0x12 == opcode1
)
10309 /* Handle enhanced software breakpoint insn, BKPT. */
10310 /* CPSR is changed to be executed in ARM state, disabling normal
10311 interrupts, entering abort mode. */
10312 /* According to high vector configuration PC is set. */
10313 /* user hit breakpoint and type reverse, in
10314 that case, we need to go back with previous CPSR and
10315 Program Counter. */
10316 record_buf
[0] = ARM_PS_REGNUM
;
10317 record_buf
[1] = ARM_LR_REGNUM
;
10318 arm_insn_r
->reg_rec_count
= 2;
10320 /* Save SPSR also; how? */
10323 else if (11 == arm_insn_r
->decode
10324 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10326 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
10328 /* Handle str(x) insn */
10329 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
10332 else if (1 == arm_insn_r
->decode
&& 0x12 == opcode1
10333 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
10335 /* Handle BX, branch and link/exchange. */
10336 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
10337 record_buf
[0] = ARM_PS_REGNUM
;
10338 arm_insn_r
->reg_rec_count
= 1;
10340 else if (1 == arm_insn_r
->decode
&& 0x16 == opcode1
10341 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 4, 1)
10342 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1))
10344 /* Count leading zeros: CLZ. */
10345 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10346 arm_insn_r
->reg_rec_count
= 1;
10348 else if (!bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
10349 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10350 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1)
10351 && sbo_sbz (arm_insn_r
->arm_insn
, 1, 12, 0)
10354 /* Handle MRS insn. */
10355 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10356 arm_insn_r
->reg_rec_count
= 1;
10358 else if (arm_insn_r
->opcode
<= 15)
10360 /* Normal data processing insns. */
10361 /* Out of 11 shifter operands mode, all the insn modifies destination
10362 register, which is specified by 13-16 decode. */
10363 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10364 record_buf
[1] = ARM_PS_REGNUM
;
10365 arm_insn_r
->reg_rec_count
= 2;
10372 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10373 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10377 /* Handling opcode 001 insns. */
10380 arm_record_data_proc_imm (insn_decode_record
*arm_insn_r
)
10382 uint32_t record_buf
[8], record_buf_mem
[8];
10384 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10385 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10387 if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
10388 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21)
10389 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
10392 /* Handle MSR insn. */
10393 if (9 == arm_insn_r
->opcode
)
10395 /* CSPR is going to be changed. */
10396 record_buf
[0] = ARM_PS_REGNUM
;
10397 arm_insn_r
->reg_rec_count
= 1;
10401 /* SPSR is going to be changed. */
10404 else if (arm_insn_r
->opcode
<= 15)
10406 /* Normal data processing insns. */
10407 /* Out of 11 shifter operands mode, all the insn modifies destination
10408 register, which is specified by 13-16 decode. */
10409 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10410 record_buf
[1] = ARM_PS_REGNUM
;
10411 arm_insn_r
->reg_rec_count
= 2;
10418 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10419 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10424 arm_record_media (insn_decode_record
*arm_insn_r
)
10426 uint32_t record_buf
[8];
10428 switch (bits (arm_insn_r
->arm_insn
, 22, 24))
10431 /* Parallel addition and subtraction, signed */
10433 /* Parallel addition and subtraction, unsigned */
10436 /* Packing, unpacking, saturation and reversal */
10438 int rd
= bits (arm_insn_r
->arm_insn
, 12, 15);
10440 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10446 /* Signed multiplies */
10448 int rd
= bits (arm_insn_r
->arm_insn
, 16, 19);
10449 unsigned int op1
= bits (arm_insn_r
->arm_insn
, 20, 22);
10451 record_buf
[arm_insn_r
->reg_rec_count
++] = rd
;
10453 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10454 else if (op1
== 0x4)
10455 record_buf
[arm_insn_r
->reg_rec_count
++]
10456 = bits (arm_insn_r
->arm_insn
, 12, 15);
10462 if (bit (arm_insn_r
->arm_insn
, 21)
10463 && bits (arm_insn_r
->arm_insn
, 5, 6) == 0x2)
10466 record_buf
[arm_insn_r
->reg_rec_count
++]
10467 = bits (arm_insn_r
->arm_insn
, 12, 15);
10469 else if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x0
10470 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x0)
10472 /* USAD8 and USADA8 */
10473 record_buf
[arm_insn_r
->reg_rec_count
++]
10474 = bits (arm_insn_r
->arm_insn
, 16, 19);
10481 if (bits (arm_insn_r
->arm_insn
, 20, 21) == 0x3
10482 && bits (arm_insn_r
->arm_insn
, 5, 7) == 0x7)
10484 /* Permanently UNDEFINED */
10489 /* BFC, BFI and UBFX */
10490 record_buf
[arm_insn_r
->reg_rec_count
++]
10491 = bits (arm_insn_r
->arm_insn
, 12, 15);
10500 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10505 /* Handle ARM mode instructions with opcode 010. */
10508 arm_record_ld_st_imm_offset (insn_decode_record
*arm_insn_r
)
10510 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10512 uint32_t reg_base
, reg_dest
;
10513 uint32_t offset_12
, tgt_mem_addr
;
10514 uint32_t record_buf
[8], record_buf_mem
[8];
10515 unsigned char wback
;
10518 /* Calculate wback. */
10519 wback
= (bit (arm_insn_r
->arm_insn
, 24) == 0)
10520 || (bit (arm_insn_r
->arm_insn
, 21) == 1);
10522 arm_insn_r
->reg_rec_count
= 0;
10523 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
10525 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10527 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
10530 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10531 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_dest
;
10533 /* The LDR instruction is capable of doing branching. If MOV LR, PC
10534 preceeds a LDR instruction having R15 as reg_base, it
10535 emulates a branch and link instruction, and hence we need to save
10536 CPSR and PC as well. */
10537 if (ARM_PC_REGNUM
== reg_dest
)
10538 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10540 /* If wback is true, also save the base register, which is going to be
10543 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10547 /* STR (immediate), STRB (immediate), STRBT and STRT. */
10549 offset_12
= bits (arm_insn_r
->arm_insn
, 0, 11);
10550 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
10552 /* Handle bit U. */
10553 if (bit (arm_insn_r
->arm_insn
, 23))
10555 /* U == 1: Add the offset. */
10556 tgt_mem_addr
= (uint32_t) u_regval
+ offset_12
;
10560 /* U == 0: subtract the offset. */
10561 tgt_mem_addr
= (uint32_t) u_regval
- offset_12
;
10564 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
10566 if (bit (arm_insn_r
->arm_insn
, 22))
10568 /* STRB and STRBT: 1 byte. */
10569 record_buf_mem
[0] = 1;
10573 /* STR and STRT: 4 bytes. */
10574 record_buf_mem
[0] = 4;
10577 /* Handle bit P. */
10578 if (bit (arm_insn_r
->arm_insn
, 24))
10579 record_buf_mem
[1] = tgt_mem_addr
;
10581 record_buf_mem
[1] = (uint32_t) u_regval
;
10583 arm_insn_r
->mem_rec_count
= 1;
10585 /* If wback is true, also save the base register, which is going to be
10588 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10591 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10592 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10596 /* Handling opcode 011 insns. */
10599 arm_record_ld_st_reg_offset (insn_decode_record
*arm_insn_r
)
10601 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10603 uint32_t shift_imm
= 0;
10604 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
10605 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
10606 uint32_t record_buf
[8], record_buf_mem
[8];
10609 ULONGEST u_regval
[2];
10611 if (bit (arm_insn_r
->arm_insn
, 4))
10612 return arm_record_media (arm_insn_r
);
10614 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10615 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10617 /* Handle enhanced store insns and LDRD DSP insn,
10618 order begins according to addressing modes for store insns
10622 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10624 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
10625 /* LDR insn has a capability to do branching, if
10626 MOV LR, PC is precedded by LDR insn having Rn as R15
10627 in that case, it emulates branch and link insn, and hence we
10628 need to save CSPR and PC as well. */
10629 if (15 != reg_dest
)
10631 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10632 arm_insn_r
->reg_rec_count
= 1;
10636 record_buf
[0] = reg_dest
;
10637 record_buf
[1] = ARM_PS_REGNUM
;
10638 arm_insn_r
->reg_rec_count
= 2;
10643 if (! bits (arm_insn_r
->arm_insn
, 4, 11))
10645 /* Store insn, register offset and register pre-indexed,
10646 register post-indexed. */
10648 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10650 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10651 regcache_raw_read_unsigned (reg_cache
, reg_src1
10653 regcache_raw_read_unsigned (reg_cache
, reg_src2
10655 if (15 == reg_src2
)
10657 /* If R15 was used as Rn, hence current PC+8. */
10658 /* Pre-indexed mode doesnt reach here ; illegal insn. */
10659 u_regval
[0] = u_regval
[0] + 8;
10661 /* Calculate target store address, Rn +/- Rm, register offset. */
10663 if (bit (arm_insn_r
->arm_insn
, 23))
10665 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10669 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10672 switch (arm_insn_r
->opcode
)
10686 record_buf_mem
[0] = 4;
10701 record_buf_mem
[0] = 1;
10705 gdb_assert_not_reached ("no decoding pattern found");
10708 record_buf_mem
[1] = tgt_mem_addr
;
10709 arm_insn_r
->mem_rec_count
= 1;
10711 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10712 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10713 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10714 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10715 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10716 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10719 /* Rn is going to be changed in pre-indexed mode and
10720 post-indexed mode as well. */
10721 record_buf
[0] = reg_src2
;
10722 arm_insn_r
->reg_rec_count
= 1;
10727 /* Store insn, scaled register offset; scaled pre-indexed. */
10728 offset_12
= bits (arm_insn_r
->arm_insn
, 5, 6);
10730 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10732 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10733 /* Get shift_imm. */
10734 shift_imm
= bits (arm_insn_r
->arm_insn
, 7, 11);
10735 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10736 regcache_raw_read_signed (reg_cache
, reg_src1
, &s_word
);
10737 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10738 /* Offset_12 used as shift. */
10742 /* Offset_12 used as index. */
10743 offset_12
= u_regval
[0] << shift_imm
;
10747 offset_12
= (!shift_imm
)?0:u_regval
[0] >> shift_imm
;
10753 if (bit (u_regval
[0], 31))
10755 offset_12
= 0xFFFFFFFF;
10764 /* This is arithmetic shift. */
10765 offset_12
= s_word
>> shift_imm
;
10772 regcache_raw_read_unsigned (reg_cache
, ARM_PS_REGNUM
,
10774 /* Get C flag value and shift it by 31. */
10775 offset_12
= (((bit (u_regval
[1], 29)) << 31) \
10776 | (u_regval
[0]) >> 1);
10780 offset_12
= (u_regval
[0] >> shift_imm
) \
10782 (sizeof(uint32_t) - shift_imm
));
10787 gdb_assert_not_reached ("no decoding pattern found");
10791 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10793 if (bit (arm_insn_r
->arm_insn
, 23))
10795 tgt_mem_addr
= u_regval
[1] + offset_12
;
10799 tgt_mem_addr
= u_regval
[1] - offset_12
;
10802 switch (arm_insn_r
->opcode
)
10816 record_buf_mem
[0] = 4;
10831 record_buf_mem
[0] = 1;
10835 gdb_assert_not_reached ("no decoding pattern found");
10838 record_buf_mem
[1] = tgt_mem_addr
;
10839 arm_insn_r
->mem_rec_count
= 1;
10841 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
10842 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10843 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
10844 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
10845 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
10846 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
10849 /* Rn is going to be changed in register scaled pre-indexed
10850 mode,and scaled post indexed mode. */
10851 record_buf
[0] = reg_src2
;
10852 arm_insn_r
->reg_rec_count
= 1;
10857 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10858 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10862 /* Handle ARM mode instructions with opcode 100. */
10865 arm_record_ld_st_multiple (insn_decode_record
*arm_insn_r
)
10867 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10868 uint32_t register_count
= 0, register_bits
;
10869 uint32_t reg_base
, addr_mode
;
10870 uint32_t record_buf
[24], record_buf_mem
[48];
10874 /* Fetch the list of registers. */
10875 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
10876 arm_insn_r
->reg_rec_count
= 0;
10878 /* Fetch the base register that contains the address we are loading data
10880 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
10882 /* Calculate wback. */
10883 wback
= (bit (arm_insn_r
->arm_insn
, 21) == 1);
10885 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
10887 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
10889 /* Find out which registers are going to be loaded from memory. */
10890 while (register_bits
)
10892 if (register_bits
& 0x00000001)
10893 record_buf
[arm_insn_r
->reg_rec_count
++] = register_count
;
10894 register_bits
= register_bits
>> 1;
10899 /* If wback is true, also save the base register, which is going to be
10902 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10904 /* Save the CPSR register. */
10905 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
10909 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
10911 addr_mode
= bits (arm_insn_r
->arm_insn
, 23, 24);
10913 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
10915 /* Find out how many registers are going to be stored to memory. */
10916 while (register_bits
)
10918 if (register_bits
& 0x00000001)
10920 register_bits
= register_bits
>> 1;
10925 /* STMDA (STMED): Decrement after. */
10927 record_buf_mem
[1] = (uint32_t) u_regval
10928 - register_count
* INT_REGISTER_SIZE
+ 4;
10930 /* STM (STMIA, STMEA): Increment after. */
10932 record_buf_mem
[1] = (uint32_t) u_regval
;
10934 /* STMDB (STMFD): Decrement before. */
10936 record_buf_mem
[1] = (uint32_t) u_regval
10937 - register_count
* INT_REGISTER_SIZE
;
10939 /* STMIB (STMFA): Increment before. */
10941 record_buf_mem
[1] = (uint32_t) u_regval
+ INT_REGISTER_SIZE
;
10944 gdb_assert_not_reached ("no decoding pattern found");
10948 record_buf_mem
[0] = register_count
* INT_REGISTER_SIZE
;
10949 arm_insn_r
->mem_rec_count
= 1;
10951 /* If wback is true, also save the base register, which is going to be
10954 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
10957 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10958 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
10962 /* Handling opcode 101 insns. */
10965 arm_record_b_bl (insn_decode_record
*arm_insn_r
)
10967 uint32_t record_buf
[8];
10969 /* Handle B, BL, BLX(1) insns. */
10970 /* B simply branches so we do nothing here. */
10971 /* Note: BLX(1) doesnt fall here but instead it falls into
10972 extension space. */
10973 if (bit (arm_insn_r
->arm_insn
, 24))
10975 record_buf
[0] = ARM_LR_REGNUM
;
10976 arm_insn_r
->reg_rec_count
= 1;
10979 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
10985 arm_record_unsupported_insn (insn_decode_record
*arm_insn_r
)
10987 printf_unfiltered (_("Process record does not support instruction "
10988 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
10989 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
10994 /* Record handler for vector data transfer instructions. */
10997 arm_record_vdata_transfer_insn (insn_decode_record
*arm_insn_r
)
10999 uint32_t bits_a
, bit_c
, bit_l
, reg_t
, reg_v
;
11000 uint32_t record_buf
[4];
11002 reg_t
= bits (arm_insn_r
->arm_insn
, 12, 15);
11003 reg_v
= bits (arm_insn_r
->arm_insn
, 21, 23);
11004 bits_a
= bits (arm_insn_r
->arm_insn
, 21, 23);
11005 bit_l
= bit (arm_insn_r
->arm_insn
, 20);
11006 bit_c
= bit (arm_insn_r
->arm_insn
, 8);
11008 /* Handle VMOV instruction. */
11009 if (bit_l
&& bit_c
)
11011 record_buf
[0] = reg_t
;
11012 arm_insn_r
->reg_rec_count
= 1;
11014 else if (bit_l
&& !bit_c
)
11016 /* Handle VMOV instruction. */
11017 if (bits_a
== 0x00)
11019 record_buf
[0] = reg_t
;
11020 arm_insn_r
->reg_rec_count
= 1;
11022 /* Handle VMRS instruction. */
11023 else if (bits_a
== 0x07)
11026 reg_t
= ARM_PS_REGNUM
;
11028 record_buf
[0] = reg_t
;
11029 arm_insn_r
->reg_rec_count
= 1;
11032 else if (!bit_l
&& !bit_c
)
11034 /* Handle VMOV instruction. */
11035 if (bits_a
== 0x00)
11037 record_buf
[0] = ARM_D0_REGNUM
+ reg_v
;
11039 arm_insn_r
->reg_rec_count
= 1;
11041 /* Handle VMSR instruction. */
11042 else if (bits_a
== 0x07)
11044 record_buf
[0] = ARM_FPSCR_REGNUM
;
11045 arm_insn_r
->reg_rec_count
= 1;
11048 else if (!bit_l
&& bit_c
)
11050 /* Handle VMOV instruction. */
11051 if (!(bits_a
& 0x04))
11053 record_buf
[0] = (reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4))
11055 arm_insn_r
->reg_rec_count
= 1;
11057 /* Handle VDUP instruction. */
11060 if (bit (arm_insn_r
->arm_insn
, 21))
11062 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11063 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11064 record_buf
[1] = reg_v
+ ARM_D0_REGNUM
+ 1;
11065 arm_insn_r
->reg_rec_count
= 2;
11069 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
11070 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
11071 arm_insn_r
->reg_rec_count
= 1;
11076 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11080 /* Record handler for extension register load/store instructions. */
11083 arm_record_exreg_ld_st_insn (insn_decode_record
*arm_insn_r
)
11085 uint32_t opcode
, single_reg
;
11086 uint8_t op_vldm_vstm
;
11087 uint32_t record_buf
[8], record_buf_mem
[128];
11088 ULONGEST u_regval
= 0;
11090 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11092 opcode
= bits (arm_insn_r
->arm_insn
, 20, 24);
11093 single_reg
= !bit (arm_insn_r
->arm_insn
, 8);
11094 op_vldm_vstm
= opcode
& 0x1b;
11096 /* Handle VMOV instructions. */
11097 if ((opcode
& 0x1e) == 0x04)
11099 if (bit (arm_insn_r
->arm_insn
, 20)) /* to_arm_registers bit 20? */
11101 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11102 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11103 arm_insn_r
->reg_rec_count
= 2;
11107 uint8_t reg_m
= bits (arm_insn_r
->arm_insn
, 0, 3);
11108 uint8_t bit_m
= bit (arm_insn_r
->arm_insn
, 5);
11112 /* The first S register number m is REG_M:M (M is bit 5),
11113 the corresponding D register number is REG_M:M / 2, which
11115 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_D0_REGNUM
+ reg_m
;
11116 /* The second S register number is REG_M:M + 1, the
11117 corresponding D register number is (REG_M:M + 1) / 2.
11118 IOW, if bit M is 1, the first and second S registers
11119 are mapped to different D registers, otherwise, they are
11120 in the same D register. */
11123 record_buf
[arm_insn_r
->reg_rec_count
++]
11124 = ARM_D0_REGNUM
+ reg_m
+ 1;
11129 record_buf
[0] = ((bit_m
<< 4) + reg_m
+ ARM_D0_REGNUM
);
11130 arm_insn_r
->reg_rec_count
= 1;
11134 /* Handle VSTM and VPUSH instructions. */
11135 else if (op_vldm_vstm
== 0x08 || op_vldm_vstm
== 0x0a
11136 || op_vldm_vstm
== 0x12)
11138 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
11139 uint32_t memory_index
= 0;
11141 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11142 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11143 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11144 imm_off32
= imm_off8
<< 2;
11145 memory_count
= imm_off8
;
11147 if (bit (arm_insn_r
->arm_insn
, 23))
11148 start_address
= u_regval
;
11150 start_address
= u_regval
- imm_off32
;
11152 if (bit (arm_insn_r
->arm_insn
, 21))
11154 record_buf
[0] = reg_rn
;
11155 arm_insn_r
->reg_rec_count
= 1;
11158 while (memory_count
> 0)
11162 record_buf_mem
[memory_index
] = 4;
11163 record_buf_mem
[memory_index
+ 1] = start_address
;
11164 start_address
= start_address
+ 4;
11165 memory_index
= memory_index
+ 2;
11169 record_buf_mem
[memory_index
] = 4;
11170 record_buf_mem
[memory_index
+ 1] = start_address
;
11171 record_buf_mem
[memory_index
+ 2] = 4;
11172 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11173 start_address
= start_address
+ 8;
11174 memory_index
= memory_index
+ 4;
11178 arm_insn_r
->mem_rec_count
= (memory_index
>> 1);
11180 /* Handle VLDM instructions. */
11181 else if (op_vldm_vstm
== 0x09 || op_vldm_vstm
== 0x0b
11182 || op_vldm_vstm
== 0x13)
11184 uint32_t reg_count
, reg_vd
;
11185 uint32_t reg_index
= 0;
11186 uint32_t bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11188 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11189 reg_count
= bits (arm_insn_r
->arm_insn
, 0, 7);
11191 /* REG_VD is the first D register number. If the instruction
11192 loads memory to S registers (SINGLE_REG is TRUE), the register
11193 number is (REG_VD << 1 | bit D), so the corresponding D
11194 register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */
11196 reg_vd
= reg_vd
| (bit_d
<< 4);
11198 if (bit (arm_insn_r
->arm_insn
, 21) /* write back */)
11199 record_buf
[reg_index
++] = bits (arm_insn_r
->arm_insn
, 16, 19);
11201 /* If the instruction loads memory to D register, REG_COUNT should
11202 be divided by 2, according to the ARM Architecture Reference
11203 Manual. If the instruction loads memory to S register, divide by
11204 2 as well because two S registers are mapped to D register. */
11205 reg_count
= reg_count
/ 2;
11206 if (single_reg
&& bit_d
)
11208 /* Increase the register count if S register list starts from
11209 an odd number (bit d is one). */
11213 while (reg_count
> 0)
11215 record_buf
[reg_index
++] = ARM_D0_REGNUM
+ reg_vd
+ reg_count
- 1;
11218 arm_insn_r
->reg_rec_count
= reg_index
;
11220 /* VSTR Vector store register. */
11221 else if ((opcode
& 0x13) == 0x10)
11223 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
;
11224 uint32_t memory_index
= 0;
11226 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
11227 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
11228 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
11229 imm_off32
= imm_off8
<< 2;
11231 if (bit (arm_insn_r
->arm_insn
, 23))
11232 start_address
= u_regval
+ imm_off32
;
11234 start_address
= u_regval
- imm_off32
;
11238 record_buf_mem
[memory_index
] = 4;
11239 record_buf_mem
[memory_index
+ 1] = start_address
;
11240 arm_insn_r
->mem_rec_count
= 1;
11244 record_buf_mem
[memory_index
] = 4;
11245 record_buf_mem
[memory_index
+ 1] = start_address
;
11246 record_buf_mem
[memory_index
+ 2] = 4;
11247 record_buf_mem
[memory_index
+ 3] = start_address
+ 4;
11248 arm_insn_r
->mem_rec_count
= 2;
11251 /* VLDR Vector load register. */
11252 else if ((opcode
& 0x13) == 0x11)
11254 uint32_t reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11258 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
11259 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
;
11263 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
11264 /* Record register D rather than pseudo register S. */
11265 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
/ 2;
11267 arm_insn_r
->reg_rec_count
= 1;
11270 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11271 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11275 /* Record handler for arm/thumb mode VFP data processing instructions. */
11278 arm_record_vfp_data_proc_insn (insn_decode_record
*arm_insn_r
)
11280 uint32_t opc1
, opc2
, opc3
, dp_op_sz
, bit_d
, reg_vd
;
11281 uint32_t record_buf
[4];
11282 enum insn_types
{INSN_T0
, INSN_T1
, INSN_T2
, INSN_T3
, INSN_INV
};
11283 enum insn_types curr_insn_type
= INSN_INV
;
11285 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
11286 opc1
= bits (arm_insn_r
->arm_insn
, 20, 23);
11287 opc2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11288 opc3
= bits (arm_insn_r
->arm_insn
, 6, 7);
11289 dp_op_sz
= bit (arm_insn_r
->arm_insn
, 8);
11290 bit_d
= bit (arm_insn_r
->arm_insn
, 22);
11291 opc1
= opc1
& 0x04;
11293 /* Handle VMLA, VMLS. */
11296 if (bit (arm_insn_r
->arm_insn
, 10))
11298 if (bit (arm_insn_r
->arm_insn
, 6))
11299 curr_insn_type
= INSN_T0
;
11301 curr_insn_type
= INSN_T1
;
11306 curr_insn_type
= INSN_T1
;
11308 curr_insn_type
= INSN_T2
;
11311 /* Handle VNMLA, VNMLS, VNMUL. */
11312 else if (opc1
== 0x01)
11315 curr_insn_type
= INSN_T1
;
11317 curr_insn_type
= INSN_T2
;
11320 else if (opc1
== 0x02 && !(opc3
& 0x01))
11322 if (bit (arm_insn_r
->arm_insn
, 10))
11324 if (bit (arm_insn_r
->arm_insn
, 6))
11325 curr_insn_type
= INSN_T0
;
11327 curr_insn_type
= INSN_T1
;
11332 curr_insn_type
= INSN_T1
;
11334 curr_insn_type
= INSN_T2
;
11337 /* Handle VADD, VSUB. */
11338 else if (opc1
== 0x03)
11340 if (!bit (arm_insn_r
->arm_insn
, 9))
11342 if (bit (arm_insn_r
->arm_insn
, 6))
11343 curr_insn_type
= INSN_T0
;
11345 curr_insn_type
= INSN_T1
;
11350 curr_insn_type
= INSN_T1
;
11352 curr_insn_type
= INSN_T2
;
11356 else if (opc1
== 0x0b)
11359 curr_insn_type
= INSN_T1
;
11361 curr_insn_type
= INSN_T2
;
11363 /* Handle all other vfp data processing instructions. */
11364 else if (opc1
== 0x0b)
11367 if (!(opc3
& 0x01) || (opc2
== 0x00 && opc3
== 0x01))
11369 if (bit (arm_insn_r
->arm_insn
, 4))
11371 if (bit (arm_insn_r
->arm_insn
, 6))
11372 curr_insn_type
= INSN_T0
;
11374 curr_insn_type
= INSN_T1
;
11379 curr_insn_type
= INSN_T1
;
11381 curr_insn_type
= INSN_T2
;
11384 /* Handle VNEG and VABS. */
11385 else if ((opc2
== 0x01 && opc3
== 0x01)
11386 || (opc2
== 0x00 && opc3
== 0x03))
11388 if (!bit (arm_insn_r
->arm_insn
, 11))
11390 if (bit (arm_insn_r
->arm_insn
, 6))
11391 curr_insn_type
= INSN_T0
;
11393 curr_insn_type
= INSN_T1
;
11398 curr_insn_type
= INSN_T1
;
11400 curr_insn_type
= INSN_T2
;
11403 /* Handle VSQRT. */
11404 else if (opc2
== 0x01 && opc3
== 0x03)
11407 curr_insn_type
= INSN_T1
;
11409 curr_insn_type
= INSN_T2
;
11412 else if (opc2
== 0x07 && opc3
== 0x03)
11415 curr_insn_type
= INSN_T1
;
11417 curr_insn_type
= INSN_T2
;
11419 else if (opc3
& 0x01)
11422 if ((opc2
== 0x08) || (opc2
& 0x0e) == 0x0c)
11424 if (!bit (arm_insn_r
->arm_insn
, 18))
11425 curr_insn_type
= INSN_T2
;
11429 curr_insn_type
= INSN_T1
;
11431 curr_insn_type
= INSN_T2
;
11435 else if ((opc2
& 0x0e) == 0x0a || (opc2
& 0x0e) == 0x0e)
11438 curr_insn_type
= INSN_T1
;
11440 curr_insn_type
= INSN_T2
;
11442 /* Handle VCVTB, VCVTT. */
11443 else if ((opc2
& 0x0e) == 0x02)
11444 curr_insn_type
= INSN_T2
;
11445 /* Handle VCMP, VCMPE. */
11446 else if ((opc2
& 0x0e) == 0x04)
11447 curr_insn_type
= INSN_T3
;
11451 switch (curr_insn_type
)
11454 reg_vd
= reg_vd
| (bit_d
<< 4);
11455 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11456 record_buf
[1] = reg_vd
+ ARM_D0_REGNUM
+ 1;
11457 arm_insn_r
->reg_rec_count
= 2;
11461 reg_vd
= reg_vd
| (bit_d
<< 4);
11462 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11463 arm_insn_r
->reg_rec_count
= 1;
11467 reg_vd
= (reg_vd
<< 1) | bit_d
;
11468 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
11469 arm_insn_r
->reg_rec_count
= 1;
11473 record_buf
[0] = ARM_FPSCR_REGNUM
;
11474 arm_insn_r
->reg_rec_count
= 1;
11478 gdb_assert_not_reached ("no decoding pattern found");
11482 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11486 /* Handling opcode 110 insns. */
11489 arm_record_asimd_vfp_coproc (insn_decode_record
*arm_insn_r
)
11491 uint32_t op1
, op1_ebit
, coproc
;
11493 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11494 op1
= bits (arm_insn_r
->arm_insn
, 20, 25);
11495 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11497 if ((coproc
& 0x0e) == 0x0a)
11499 /* Handle extension register ld/st instructions. */
11501 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11503 /* 64-bit transfers between arm core and extension registers. */
11504 if ((op1
& 0x3e) == 0x04)
11505 return arm_record_exreg_ld_st_insn (arm_insn_r
);
11509 /* Handle coprocessor ld/st instructions. */
11514 return arm_record_unsupported_insn (arm_insn_r
);
11517 return arm_record_unsupported_insn (arm_insn_r
);
11520 /* Move to coprocessor from two arm core registers. */
11522 return arm_record_unsupported_insn (arm_insn_r
);
11524 /* Move to two arm core registers from coprocessor. */
11529 reg_t
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11530 reg_t
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11531 arm_insn_r
->reg_rec_count
= 2;
11533 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, reg_t
);
11537 return arm_record_unsupported_insn (arm_insn_r
);
11540 /* Handling opcode 111 insns. */
11543 arm_record_coproc_data_proc (insn_decode_record
*arm_insn_r
)
11545 uint32_t op
, op1_sbit
, op1_ebit
, coproc
;
11546 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arm_insn_r
->gdbarch
);
11547 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11549 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 24, 27);
11550 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
11551 op1_sbit
= bit (arm_insn_r
->arm_insn
, 24);
11552 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
11553 op
= bit (arm_insn_r
->arm_insn
, 4);
11555 /* Handle arm SWI/SVC system call instructions. */
11558 if (tdep
->arm_syscall_record
!= NULL
)
11560 ULONGEST svc_operand
, svc_number
;
11562 svc_operand
= (0x00ffffff & arm_insn_r
->arm_insn
);
11564 if (svc_operand
) /* OABI. */
11565 svc_number
= svc_operand
- 0x900000;
11567 regcache_raw_read_unsigned (reg_cache
, 7, &svc_number
);
11569 return tdep
->arm_syscall_record (reg_cache
, svc_number
);
11573 printf_unfiltered (_("no syscall record support\n"));
11578 if ((coproc
& 0x0e) == 0x0a)
11580 /* VFP data-processing instructions. */
11581 if (!op1_sbit
&& !op
)
11582 return arm_record_vfp_data_proc_insn (arm_insn_r
);
11584 /* Advanced SIMD, VFP instructions. */
11585 if (!op1_sbit
&& op
)
11586 return arm_record_vdata_transfer_insn (arm_insn_r
);
11590 /* Coprocessor data operations. */
11591 if (!op1_sbit
&& !op
)
11592 return arm_record_unsupported_insn (arm_insn_r
);
11594 /* Move to Coprocessor from ARM core register. */
11595 if (!op1_sbit
&& !op1_ebit
&& op
)
11596 return arm_record_unsupported_insn (arm_insn_r
);
11598 /* Move to arm core register from coprocessor. */
11599 if (!op1_sbit
&& op1_ebit
&& op
)
11601 uint32_t record_buf
[1];
11603 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11604 if (record_buf
[0] == 15)
11605 record_buf
[0] = ARM_PS_REGNUM
;
11607 arm_insn_r
->reg_rec_count
= 1;
11608 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
,
11614 return arm_record_unsupported_insn (arm_insn_r
);
11617 /* Handling opcode 000 insns. */
11620 thumb_record_shift_add_sub (insn_decode_record
*thumb_insn_r
)
11622 uint32_t record_buf
[8];
11623 uint32_t reg_src1
= 0;
11625 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11627 record_buf
[0] = ARM_PS_REGNUM
;
11628 record_buf
[1] = reg_src1
;
11629 thumb_insn_r
->reg_rec_count
= 2;
11631 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11637 /* Handling opcode 001 insns. */
11640 thumb_record_add_sub_cmp_mov (insn_decode_record
*thumb_insn_r
)
11642 uint32_t record_buf
[8];
11643 uint32_t reg_src1
= 0;
11645 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11647 record_buf
[0] = ARM_PS_REGNUM
;
11648 record_buf
[1] = reg_src1
;
11649 thumb_insn_r
->reg_rec_count
= 2;
11651 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11656 /* Handling opcode 010 insns. */
11659 thumb_record_ld_st_reg_offset (insn_decode_record
*thumb_insn_r
)
11661 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11662 uint32_t record_buf
[8], record_buf_mem
[8];
11664 uint32_t reg_src1
= 0, reg_src2
= 0;
11665 uint32_t opcode1
= 0, opcode2
= 0, opcode3
= 0;
11667 ULONGEST u_regval
[2] = {0};
11669 opcode1
= bits (thumb_insn_r
->arm_insn
, 10, 12);
11671 if (bit (thumb_insn_r
->arm_insn
, 12))
11673 /* Handle load/store register offset. */
11674 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 10);
11675 if (opcode2
>= 12 && opcode2
<= 15)
11677 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
11678 reg_src1
= bits (thumb_insn_r
->arm_insn
,0, 2);
11679 record_buf
[0] = reg_src1
;
11680 thumb_insn_r
->reg_rec_count
= 1;
11682 else if (opcode2
>= 8 && opcode2
<= 10)
11684 /* STR(2), STRB(2), STRH(2) . */
11685 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11686 reg_src2
= bits (thumb_insn_r
->arm_insn
, 6, 8);
11687 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11688 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11690 record_buf_mem
[0] = 4; /* STR (2). */
11691 else if (10 == opcode2
)
11692 record_buf_mem
[0] = 1; /* STRB (2). */
11693 else if (9 == opcode2
)
11694 record_buf_mem
[0] = 2; /* STRH (2). */
11695 record_buf_mem
[1] = u_regval
[0] + u_regval
[1];
11696 thumb_insn_r
->mem_rec_count
= 1;
11699 else if (bit (thumb_insn_r
->arm_insn
, 11))
11701 /* Handle load from literal pool. */
11703 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11704 record_buf
[0] = reg_src1
;
11705 thumb_insn_r
->reg_rec_count
= 1;
11709 opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 9);
11710 opcode3
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11711 if ((3 == opcode2
) && (!opcode3
))
11713 /* Branch with exchange. */
11714 record_buf
[0] = ARM_PS_REGNUM
;
11715 thumb_insn_r
->reg_rec_count
= 1;
11719 /* Format 8; special data processing insns. */
11720 record_buf
[0] = ARM_PS_REGNUM
;
11721 record_buf
[1] = (bit (thumb_insn_r
->arm_insn
, 7) << 3
11722 | bits (thumb_insn_r
->arm_insn
, 0, 2));
11723 thumb_insn_r
->reg_rec_count
= 2;
11728 /* Format 5; data processing insns. */
11729 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11730 if (bit (thumb_insn_r
->arm_insn
, 7))
11732 reg_src1
= reg_src1
+ 8;
11734 record_buf
[0] = ARM_PS_REGNUM
;
11735 record_buf
[1] = reg_src1
;
11736 thumb_insn_r
->reg_rec_count
= 2;
11739 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11740 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11746 /* Handling opcode 001 insns. */
11749 thumb_record_ld_st_imm_offset (insn_decode_record
*thumb_insn_r
)
11751 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11752 uint32_t record_buf
[8], record_buf_mem
[8];
11754 uint32_t reg_src1
= 0;
11755 uint32_t opcode
= 0, immed_5
= 0;
11757 ULONGEST u_regval
= 0;
11759 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11764 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11765 record_buf
[0] = reg_src1
;
11766 thumb_insn_r
->reg_rec_count
= 1;
11771 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11772 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11773 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11774 record_buf_mem
[0] = 4;
11775 record_buf_mem
[1] = u_regval
+ (immed_5
* 4);
11776 thumb_insn_r
->mem_rec_count
= 1;
11779 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11780 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11786 /* Handling opcode 100 insns. */
11789 thumb_record_ld_st_stack (insn_decode_record
*thumb_insn_r
)
11791 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11792 uint32_t record_buf
[8], record_buf_mem
[8];
11794 uint32_t reg_src1
= 0;
11795 uint32_t opcode
= 0, immed_8
= 0, immed_5
= 0;
11797 ULONGEST u_regval
= 0;
11799 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11804 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11805 record_buf
[0] = reg_src1
;
11806 thumb_insn_r
->reg_rec_count
= 1;
11808 else if (1 == opcode
)
11811 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11812 record_buf
[0] = reg_src1
;
11813 thumb_insn_r
->reg_rec_count
= 1;
11815 else if (2 == opcode
)
11818 immed_8
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11819 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
11820 record_buf_mem
[0] = 4;
11821 record_buf_mem
[1] = u_regval
+ (immed_8
* 4);
11822 thumb_insn_r
->mem_rec_count
= 1;
11824 else if (0 == opcode
)
11827 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
11828 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
11829 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11830 record_buf_mem
[0] = 2;
11831 record_buf_mem
[1] = u_regval
+ (immed_5
* 2);
11832 thumb_insn_r
->mem_rec_count
= 1;
11835 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11836 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11842 /* Handling opcode 101 insns. */
11845 thumb_record_misc (insn_decode_record
*thumb_insn_r
)
11847 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11849 uint32_t opcode
= 0, opcode1
= 0, opcode2
= 0;
11850 uint32_t register_bits
= 0, register_count
= 0;
11851 uint32_t index
= 0, start_address
= 0;
11852 uint32_t record_buf
[24], record_buf_mem
[48];
11855 ULONGEST u_regval
= 0;
11857 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11858 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
11859 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 12);
11864 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11865 while (register_bits
)
11867 if (register_bits
& 0x00000001)
11868 record_buf
[index
++] = register_count
;
11869 register_bits
= register_bits
>> 1;
11872 record_buf
[index
++] = ARM_PS_REGNUM
;
11873 record_buf
[index
++] = ARM_SP_REGNUM
;
11874 thumb_insn_r
->reg_rec_count
= index
;
11876 else if (10 == opcode2
)
11879 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11880 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
11881 while (register_bits
)
11883 if (register_bits
& 0x00000001)
11885 register_bits
= register_bits
>> 1;
11887 start_address
= u_regval
- \
11888 (4 * (bit (thumb_insn_r
->arm_insn
, 8) + register_count
));
11889 thumb_insn_r
->mem_rec_count
= register_count
;
11890 while (register_count
)
11892 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11893 record_buf_mem
[(register_count
* 2) - 2] = 4;
11894 start_address
= start_address
+ 4;
11897 record_buf
[0] = ARM_SP_REGNUM
;
11898 thumb_insn_r
->reg_rec_count
= 1;
11900 else if (0x1E == opcode1
)
11903 /* Handle enhanced software breakpoint insn, BKPT. */
11904 /* CPSR is changed to be executed in ARM state, disabling normal
11905 interrupts, entering abort mode. */
11906 /* According to high vector configuration PC is set. */
11907 /* User hits breakpoint and type reverse, in that case, we need to go back with
11908 previous CPSR and Program Counter. */
11909 record_buf
[0] = ARM_PS_REGNUM
;
11910 record_buf
[1] = ARM_LR_REGNUM
;
11911 thumb_insn_r
->reg_rec_count
= 2;
11912 /* We need to save SPSR value, which is not yet done. */
11913 printf_unfiltered (_("Process record does not support instruction "
11914 "0x%0x at address %s.\n"),
11915 thumb_insn_r
->arm_insn
,
11916 paddress (thumb_insn_r
->gdbarch
,
11917 thumb_insn_r
->this_addr
));
11920 else if ((0 == opcode
) || (1 == opcode
))
11922 /* ADD(5), ADD(6). */
11923 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11924 record_buf
[0] = reg_src1
;
11925 thumb_insn_r
->reg_rec_count
= 1;
11927 else if (2 == opcode
)
11929 /* ADD(7), SUB(4). */
11930 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11931 record_buf
[0] = ARM_SP_REGNUM
;
11932 thumb_insn_r
->reg_rec_count
= 1;
11935 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11936 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
11942 /* Handling opcode 110 insns. */
11945 thumb_record_ldm_stm_swi (insn_decode_record
*thumb_insn_r
)
11947 struct gdbarch_tdep
*tdep
= gdbarch_tdep (thumb_insn_r
->gdbarch
);
11948 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
11950 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
11951 uint32_t reg_src1
= 0;
11952 uint32_t opcode1
= 0, opcode2
= 0, register_bits
= 0, register_count
= 0;
11953 uint32_t index
= 0, start_address
= 0;
11954 uint32_t record_buf
[24], record_buf_mem
[48];
11956 ULONGEST u_regval
= 0;
11958 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
11959 opcode2
= bits (thumb_insn_r
->arm_insn
, 11, 12);
11965 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11967 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11968 while (register_bits
)
11970 if (register_bits
& 0x00000001)
11971 record_buf
[index
++] = register_count
;
11972 register_bits
= register_bits
>> 1;
11975 record_buf
[index
++] = reg_src1
;
11976 thumb_insn_r
->reg_rec_count
= index
;
11978 else if (0 == opcode2
)
11980 /* It handles both STMIA. */
11981 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
11983 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11984 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11985 while (register_bits
)
11987 if (register_bits
& 0x00000001)
11989 register_bits
= register_bits
>> 1;
11991 start_address
= u_regval
;
11992 thumb_insn_r
->mem_rec_count
= register_count
;
11993 while (register_count
)
11995 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11996 record_buf_mem
[(register_count
* 2) - 2] = 4;
11997 start_address
= start_address
+ 4;
12001 else if (0x1F == opcode1
)
12003 /* Handle arm syscall insn. */
12004 if (tdep
->arm_syscall_record
!= NULL
)
12006 regcache_raw_read_unsigned (reg_cache
, 7, &u_regval
);
12007 ret
= tdep
->arm_syscall_record (reg_cache
, u_regval
);
12011 printf_unfiltered (_("no syscall record support\n"));
12016 /* B (1), conditional branch is automatically taken care in process_record,
12017 as PC is saved there. */
12019 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12020 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12026 /* Handling opcode 111 insns. */
12029 thumb_record_branch (insn_decode_record
*thumb_insn_r
)
12031 uint32_t record_buf
[8];
12032 uint32_t bits_h
= 0;
12034 bits_h
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12036 if (2 == bits_h
|| 3 == bits_h
)
12039 record_buf
[0] = ARM_LR_REGNUM
;
12040 thumb_insn_r
->reg_rec_count
= 1;
12042 else if (1 == bits_h
)
12045 record_buf
[0] = ARM_PS_REGNUM
;
12046 record_buf
[1] = ARM_LR_REGNUM
;
12047 thumb_insn_r
->reg_rec_count
= 2;
12050 /* B(2) is automatically taken care in process_record, as PC is
12053 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12058 /* Handler for thumb2 load/store multiple instructions. */
12061 thumb2_record_ld_st_multiple (insn_decode_record
*thumb2_insn_r
)
12063 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12065 uint32_t reg_rn
, op
;
12066 uint32_t register_bits
= 0, register_count
= 0;
12067 uint32_t index
= 0, start_address
= 0;
12068 uint32_t record_buf
[24], record_buf_mem
[48];
12070 ULONGEST u_regval
= 0;
12072 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12073 op
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12075 if (0 == op
|| 3 == op
)
12077 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12079 /* Handle RFE instruction. */
12080 record_buf
[0] = ARM_PS_REGNUM
;
12081 thumb2_insn_r
->reg_rec_count
= 1;
12085 /* Handle SRS instruction after reading banked SP. */
12086 return arm_record_unsupported_insn (thumb2_insn_r
);
12089 else if (1 == op
|| 2 == op
)
12091 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12093 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
12094 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12095 while (register_bits
)
12097 if (register_bits
& 0x00000001)
12098 record_buf
[index
++] = register_count
;
12101 register_bits
= register_bits
>> 1;
12103 record_buf
[index
++] = reg_rn
;
12104 record_buf
[index
++] = ARM_PS_REGNUM
;
12105 thumb2_insn_r
->reg_rec_count
= index
;
12109 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
12110 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
12111 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12112 while (register_bits
)
12114 if (register_bits
& 0x00000001)
12117 register_bits
= register_bits
>> 1;
12122 /* Start address calculation for LDMDB/LDMEA. */
12123 start_address
= u_regval
;
12127 /* Start address calculation for LDMDB/LDMEA. */
12128 start_address
= u_regval
- register_count
* 4;
12131 thumb2_insn_r
->mem_rec_count
= register_count
;
12132 while (register_count
)
12134 record_buf_mem
[register_count
* 2 - 1] = start_address
;
12135 record_buf_mem
[register_count
* 2 - 2] = 4;
12136 start_address
= start_address
+ 4;
12139 record_buf
[0] = reg_rn
;
12140 record_buf
[1] = ARM_PS_REGNUM
;
12141 thumb2_insn_r
->reg_rec_count
= 2;
12145 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12147 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12149 return ARM_RECORD_SUCCESS
;
12152 /* Handler for thumb2 load/store (dual/exclusive) and table branch
12156 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record
*thumb2_insn_r
)
12158 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12160 uint32_t reg_rd
, reg_rn
, offset_imm
;
12161 uint32_t reg_dest1
, reg_dest2
;
12162 uint32_t address
, offset_addr
;
12163 uint32_t record_buf
[8], record_buf_mem
[8];
12164 uint32_t op1
, op2
, op3
;
12166 ULONGEST u_regval
[2];
12168 op1
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
12169 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 21);
12170 op3
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12172 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
12174 if(!(1 == op1
&& 1 == op2
&& (0 == op3
|| 1 == op3
)))
12176 reg_dest1
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12177 record_buf
[0] = reg_dest1
;
12178 record_buf
[1] = ARM_PS_REGNUM
;
12179 thumb2_insn_r
->reg_rec_count
= 2;
12182 if (3 == op2
|| (op1
& 2) || (1 == op1
&& 1 == op2
&& 7 == op3
))
12184 reg_dest2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12185 record_buf
[2] = reg_dest2
;
12186 thumb2_insn_r
->reg_rec_count
= 3;
12191 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12192 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12194 if (0 == op1
&& 0 == op2
)
12196 /* Handle STREX. */
12197 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12198 address
= u_regval
[0] + (offset_imm
* 4);
12199 record_buf_mem
[0] = 4;
12200 record_buf_mem
[1] = address
;
12201 thumb2_insn_r
->mem_rec_count
= 1;
12202 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12203 record_buf
[0] = reg_rd
;
12204 thumb2_insn_r
->reg_rec_count
= 1;
12206 else if (1 == op1
&& 0 == op2
)
12208 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12209 record_buf
[0] = reg_rd
;
12210 thumb2_insn_r
->reg_rec_count
= 1;
12211 address
= u_regval
[0];
12212 record_buf_mem
[1] = address
;
12216 /* Handle STREXB. */
12217 record_buf_mem
[0] = 1;
12218 thumb2_insn_r
->mem_rec_count
= 1;
12222 /* Handle STREXH. */
12223 record_buf_mem
[0] = 2 ;
12224 thumb2_insn_r
->mem_rec_count
= 1;
12228 /* Handle STREXD. */
12229 address
= u_regval
[0];
12230 record_buf_mem
[0] = 4;
12231 record_buf_mem
[2] = 4;
12232 record_buf_mem
[3] = address
+ 4;
12233 thumb2_insn_r
->mem_rec_count
= 2;
12238 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12240 if (bit (thumb2_insn_r
->arm_insn
, 24))
12242 if (bit (thumb2_insn_r
->arm_insn
, 23))
12243 offset_addr
= u_regval
[0] + (offset_imm
* 4);
12245 offset_addr
= u_regval
[0] - (offset_imm
* 4);
12247 address
= offset_addr
;
12250 address
= u_regval
[0];
12252 record_buf_mem
[0] = 4;
12253 record_buf_mem
[1] = address
;
12254 record_buf_mem
[2] = 4;
12255 record_buf_mem
[3] = address
+ 4;
12256 thumb2_insn_r
->mem_rec_count
= 2;
12257 record_buf
[0] = reg_rn
;
12258 thumb2_insn_r
->reg_rec_count
= 1;
12262 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12264 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12266 return ARM_RECORD_SUCCESS
;
12269 /* Handler for thumb2 data processing (shift register and modified immediate)
12273 thumb2_record_data_proc_sreg_mimm (insn_decode_record
*thumb2_insn_r
)
12275 uint32_t reg_rd
, op
;
12276 uint32_t record_buf
[8];
12278 op
= bits (thumb2_insn_r
->arm_insn
, 21, 24);
12279 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12281 if ((0 == op
|| 4 == op
|| 8 == op
|| 13 == op
) && 15 == reg_rd
)
12283 record_buf
[0] = ARM_PS_REGNUM
;
12284 thumb2_insn_r
->reg_rec_count
= 1;
12288 record_buf
[0] = reg_rd
;
12289 record_buf
[1] = ARM_PS_REGNUM
;
12290 thumb2_insn_r
->reg_rec_count
= 2;
12293 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12295 return ARM_RECORD_SUCCESS
;
12298 /* Generic handler for thumb2 instructions which effect destination and PS
12302 thumb2_record_ps_dest_generic (insn_decode_record
*thumb2_insn_r
)
12305 uint32_t record_buf
[8];
12307 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12309 record_buf
[0] = reg_rd
;
12310 record_buf
[1] = ARM_PS_REGNUM
;
12311 thumb2_insn_r
->reg_rec_count
= 2;
12313 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12315 return ARM_RECORD_SUCCESS
;
12318 /* Handler for thumb2 branch and miscellaneous control instructions. */
12321 thumb2_record_branch_misc_cntrl (insn_decode_record
*thumb2_insn_r
)
12323 uint32_t op
, op1
, op2
;
12324 uint32_t record_buf
[8];
12326 op
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12327 op1
= bits (thumb2_insn_r
->arm_insn
, 12, 14);
12328 op2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12330 /* Handle MSR insn. */
12331 if (!(op1
& 0x2) && 0x38 == op
)
12335 /* CPSR is going to be changed. */
12336 record_buf
[0] = ARM_PS_REGNUM
;
12337 thumb2_insn_r
->reg_rec_count
= 1;
12341 arm_record_unsupported_insn(thumb2_insn_r
);
12345 else if (4 == (op1
& 0x5) || 5 == (op1
& 0x5))
12348 record_buf
[0] = ARM_PS_REGNUM
;
12349 record_buf
[1] = ARM_LR_REGNUM
;
12350 thumb2_insn_r
->reg_rec_count
= 2;
12353 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12355 return ARM_RECORD_SUCCESS
;
12358 /* Handler for thumb2 store single data item instructions. */
12361 thumb2_record_str_single_data (insn_decode_record
*thumb2_insn_r
)
12363 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12365 uint32_t reg_rn
, reg_rm
, offset_imm
, shift_imm
;
12366 uint32_t address
, offset_addr
;
12367 uint32_t record_buf
[8], record_buf_mem
[8];
12370 ULONGEST u_regval
[2];
12372 op1
= bits (thumb2_insn_r
->arm_insn
, 21, 23);
12373 op2
= bits (thumb2_insn_r
->arm_insn
, 6, 11);
12374 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12375 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
12377 if (bit (thumb2_insn_r
->arm_insn
, 23))
12380 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 11);
12381 offset_addr
= u_regval
[0] + offset_imm
;
12382 address
= offset_addr
;
12387 if ((0 == op1
|| 1 == op1
|| 2 == op1
) && !(op2
& 0x20))
12389 /* Handle STRB (register). */
12390 reg_rm
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
12391 regcache_raw_read_unsigned (reg_cache
, reg_rm
, &u_regval
[1]);
12392 shift_imm
= bits (thumb2_insn_r
->arm_insn
, 4, 5);
12393 offset_addr
= u_regval
[1] << shift_imm
;
12394 address
= u_regval
[0] + offset_addr
;
12398 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
12399 if (bit (thumb2_insn_r
->arm_insn
, 10))
12401 if (bit (thumb2_insn_r
->arm_insn
, 9))
12402 offset_addr
= u_regval
[0] + offset_imm
;
12404 offset_addr
= u_regval
[0] - offset_imm
;
12406 address
= offset_addr
;
12409 address
= u_regval
[0];
12415 /* Store byte instructions. */
12418 record_buf_mem
[0] = 1;
12420 /* Store half word instructions. */
12423 record_buf_mem
[0] = 2;
12425 /* Store word instructions. */
12428 record_buf_mem
[0] = 4;
12432 gdb_assert_not_reached ("no decoding pattern found");
12436 record_buf_mem
[1] = address
;
12437 thumb2_insn_r
->mem_rec_count
= 1;
12438 record_buf
[0] = reg_rn
;
12439 thumb2_insn_r
->reg_rec_count
= 1;
12441 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12443 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12445 return ARM_RECORD_SUCCESS
;
12448 /* Handler for thumb2 load memory hints instructions. */
12451 thumb2_record_ld_mem_hints (insn_decode_record
*thumb2_insn_r
)
12453 uint32_t record_buf
[8];
12454 uint32_t reg_rt
, reg_rn
;
12456 reg_rt
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12457 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12459 if (ARM_PC_REGNUM
!= reg_rt
)
12461 record_buf
[0] = reg_rt
;
12462 record_buf
[1] = reg_rn
;
12463 record_buf
[2] = ARM_PS_REGNUM
;
12464 thumb2_insn_r
->reg_rec_count
= 3;
12466 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12468 return ARM_RECORD_SUCCESS
;
12471 return ARM_RECORD_FAILURE
;
12474 /* Handler for thumb2 load word instructions. */
12477 thumb2_record_ld_word (insn_decode_record
*thumb2_insn_r
)
12479 uint32_t record_buf
[8];
12481 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12482 record_buf
[1] = ARM_PS_REGNUM
;
12483 thumb2_insn_r
->reg_rec_count
= 2;
12485 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12487 return ARM_RECORD_SUCCESS
;
12490 /* Handler for thumb2 long multiply, long multiply accumulate, and
12491 divide instructions. */
12494 thumb2_record_lmul_lmla_div (insn_decode_record
*thumb2_insn_r
)
12496 uint32_t opcode1
= 0, opcode2
= 0;
12497 uint32_t record_buf
[8];
12499 opcode1
= bits (thumb2_insn_r
->arm_insn
, 20, 22);
12500 opcode2
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
12502 if (0 == opcode1
|| 2 == opcode1
|| (opcode1
>= 4 && opcode1
<= 6))
12504 /* Handle SMULL, UMULL, SMULAL. */
12505 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
12506 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12507 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12508 record_buf
[2] = ARM_PS_REGNUM
;
12509 thumb2_insn_r
->reg_rec_count
= 3;
12511 else if (1 == opcode1
|| 3 == opcode2
)
12513 /* Handle SDIV and UDIV. */
12514 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
12515 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
12516 record_buf
[2] = ARM_PS_REGNUM
;
12517 thumb2_insn_r
->reg_rec_count
= 3;
12520 return ARM_RECORD_FAILURE
;
12522 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12524 return ARM_RECORD_SUCCESS
;
12527 /* Record handler for thumb32 coprocessor instructions. */
12530 thumb2_record_coproc_insn (insn_decode_record
*thumb2_insn_r
)
12532 if (bit (thumb2_insn_r
->arm_insn
, 25))
12533 return arm_record_coproc_data_proc (thumb2_insn_r
);
12535 return arm_record_asimd_vfp_coproc (thumb2_insn_r
);
12538 /* Record handler for advance SIMD structure load/store instructions. */
12541 thumb2_record_asimd_struct_ld_st (insn_decode_record
*thumb2_insn_r
)
12543 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
12544 uint32_t l_bit
, a_bit
, b_bits
;
12545 uint32_t record_buf
[128], record_buf_mem
[128];
12546 uint32_t reg_rn
, reg_vd
, address
, f_elem
;
12547 uint32_t index_r
= 0, index_e
= 0, bf_regs
= 0, index_m
= 0, loop_t
= 0;
12550 l_bit
= bit (thumb2_insn_r
->arm_insn
, 21);
12551 a_bit
= bit (thumb2_insn_r
->arm_insn
, 23);
12552 b_bits
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
12553 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
12554 reg_vd
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
12555 reg_vd
= (bit (thumb2_insn_r
->arm_insn
, 22) << 4) | reg_vd
;
12556 f_ebytes
= (1 << bits (thumb2_insn_r
->arm_insn
, 6, 7));
12557 f_elem
= 8 / f_ebytes
;
12561 ULONGEST u_regval
= 0;
12562 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12563 address
= u_regval
;
12568 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12570 if (b_bits
== 0x07)
12572 else if (b_bits
== 0x0a)
12574 else if (b_bits
== 0x06)
12576 else if (b_bits
== 0x02)
12581 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12583 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12585 record_buf_mem
[index_m
++] = f_ebytes
;
12586 record_buf_mem
[index_m
++] = address
;
12587 address
= address
+ f_ebytes
;
12588 thumb2_insn_r
->mem_rec_count
+= 1;
12593 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12595 if (b_bits
== 0x09 || b_bits
== 0x08)
12597 else if (b_bits
== 0x03)
12602 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
12603 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12605 for (loop_t
= 0; loop_t
< 2; loop_t
++)
12607 record_buf_mem
[index_m
++] = f_ebytes
;
12608 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12609 thumb2_insn_r
->mem_rec_count
+= 1;
12611 address
= address
+ (2 * f_ebytes
);
12615 else if ((b_bits
& 0x0e) == 0x04)
12617 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12619 for (loop_t
= 0; loop_t
< 3; loop_t
++)
12621 record_buf_mem
[index_m
++] = f_ebytes
;
12622 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12623 thumb2_insn_r
->mem_rec_count
+= 1;
12625 address
= address
+ (3 * f_ebytes
);
12629 else if (!(b_bits
& 0x0e))
12631 for (index_e
= 0; index_e
< f_elem
; index_e
++)
12633 for (loop_t
= 0; loop_t
< 4; loop_t
++)
12635 record_buf_mem
[index_m
++] = f_ebytes
;
12636 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
12637 thumb2_insn_r
->mem_rec_count
+= 1;
12639 address
= address
+ (4 * f_ebytes
);
12645 uint8_t bft_size
= bits (thumb2_insn_r
->arm_insn
, 10, 11);
12647 if (bft_size
== 0x00)
12649 else if (bft_size
== 0x01)
12651 else if (bft_size
== 0x02)
12657 if (!(b_bits
& 0x0b) || b_bits
== 0x08)
12658 thumb2_insn_r
->mem_rec_count
= 1;
12660 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09)
12661 thumb2_insn_r
->mem_rec_count
= 2;
12663 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a)
12664 thumb2_insn_r
->mem_rec_count
= 3;
12666 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b)
12667 thumb2_insn_r
->mem_rec_count
= 4;
12669 for (index_m
= 0; index_m
< thumb2_insn_r
->mem_rec_count
; index_m
++)
12671 record_buf_mem
[index_m
] = f_ebytes
;
12672 record_buf_mem
[index_m
] = address
+ (index_m
* f_ebytes
);
12681 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
12682 thumb2_insn_r
->reg_rec_count
= 1;
12684 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
12685 thumb2_insn_r
->reg_rec_count
= 2;
12687 else if ((b_bits
& 0x0e) == 0x04)
12688 thumb2_insn_r
->reg_rec_count
= 3;
12690 else if (!(b_bits
& 0x0e))
12691 thumb2_insn_r
->reg_rec_count
= 4;
12696 if (!(b_bits
& 0x0b) || b_bits
== 0x08 || b_bits
== 0x0c)
12697 thumb2_insn_r
->reg_rec_count
= 1;
12699 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09 || b_bits
== 0x0d)
12700 thumb2_insn_r
->reg_rec_count
= 2;
12702 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a || b_bits
== 0x0e)
12703 thumb2_insn_r
->reg_rec_count
= 3;
12705 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b || b_bits
== 0x0f)
12706 thumb2_insn_r
->reg_rec_count
= 4;
12708 for (index_r
= 0; index_r
< thumb2_insn_r
->reg_rec_count
; index_r
++)
12709 record_buf
[index_r
] = reg_vd
+ ARM_D0_REGNUM
+ index_r
;
12713 if (bits (thumb2_insn_r
->arm_insn
, 0, 3) != 15)
12715 record_buf
[index_r
] = reg_rn
;
12716 thumb2_insn_r
->reg_rec_count
+= 1;
12719 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
12721 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
12726 /* Decodes thumb2 instruction type and invokes its record handler. */
12728 static unsigned int
12729 thumb2_record_decode_insn_handler (insn_decode_record
*thumb2_insn_r
)
12731 uint32_t op
, op1
, op2
;
12733 op
= bit (thumb2_insn_r
->arm_insn
, 15);
12734 op1
= bits (thumb2_insn_r
->arm_insn
, 27, 28);
12735 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
12739 if (!(op2
& 0x64 ))
12741 /* Load/store multiple instruction. */
12742 return thumb2_record_ld_st_multiple (thumb2_insn_r
);
12744 else if (!((op2
& 0x64) ^ 0x04))
12746 /* Load/store (dual/exclusive) and table branch instruction. */
12747 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r
);
12749 else if (!((op2
& 0x20) ^ 0x20))
12751 /* Data-processing (shifted register). */
12752 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12754 else if (op2
& 0x40)
12756 /* Co-processor instructions. */
12757 return thumb2_record_coproc_insn (thumb2_insn_r
);
12760 else if (op1
== 0x02)
12764 /* Branches and miscellaneous control instructions. */
12765 return thumb2_record_branch_misc_cntrl (thumb2_insn_r
);
12767 else if (op2
& 0x20)
12769 /* Data-processing (plain binary immediate) instruction. */
12770 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12774 /* Data-processing (modified immediate). */
12775 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
12778 else if (op1
== 0x03)
12780 if (!(op2
& 0x71 ))
12782 /* Store single data item. */
12783 return thumb2_record_str_single_data (thumb2_insn_r
);
12785 else if (!((op2
& 0x71) ^ 0x10))
12787 /* Advanced SIMD or structure load/store instructions. */
12788 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r
);
12790 else if (!((op2
& 0x67) ^ 0x01))
12792 /* Load byte, memory hints instruction. */
12793 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
12795 else if (!((op2
& 0x67) ^ 0x03))
12797 /* Load halfword, memory hints instruction. */
12798 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
12800 else if (!((op2
& 0x67) ^ 0x05))
12802 /* Load word instruction. */
12803 return thumb2_record_ld_word (thumb2_insn_r
);
12805 else if (!((op2
& 0x70) ^ 0x20))
12807 /* Data-processing (register) instruction. */
12808 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12810 else if (!((op2
& 0x78) ^ 0x30))
12812 /* Multiply, multiply accumulate, abs diff instruction. */
12813 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
12815 else if (!((op2
& 0x78) ^ 0x38))
12817 /* Long multiply, long multiply accumulate, and divide. */
12818 return thumb2_record_lmul_lmla_div (thumb2_insn_r
);
12820 else if (op2
& 0x40)
12822 /* Co-processor instructions. */
12823 return thumb2_record_coproc_insn (thumb2_insn_r
);
12830 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12831 and positive val on fauilure. */
12834 extract_arm_insn (insn_decode_record
*insn_record
, uint32_t insn_size
)
12836 gdb_byte buf
[insn_size
];
12838 memset (&buf
[0], 0, insn_size
);
12840 if (target_read_memory (insn_record
->this_addr
, &buf
[0], insn_size
))
12842 insn_record
->arm_insn
= (uint32_t) extract_unsigned_integer (&buf
[0],
12844 gdbarch_byte_order_for_code (insn_record
->gdbarch
));
12848 typedef int (*sti_arm_hdl_fp_t
) (insn_decode_record
*);
12850 /* Decode arm/thumb insn depending on condition cods and opcodes; and
12854 decode_insn (insn_decode_record
*arm_record
, record_type_t record_type
,
12855 uint32_t insn_size
)
12858 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm
12860 static const sti_arm_hdl_fp_t arm_handle_insn
[8] =
12862 arm_record_data_proc_misc_ld_str
, /* 000. */
12863 arm_record_data_proc_imm
, /* 001. */
12864 arm_record_ld_st_imm_offset
, /* 010. */
12865 arm_record_ld_st_reg_offset
, /* 011. */
12866 arm_record_ld_st_multiple
, /* 100. */
12867 arm_record_b_bl
, /* 101. */
12868 arm_record_asimd_vfp_coproc
, /* 110. */
12869 arm_record_coproc_data_proc
/* 111. */
12872 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb
12874 static const sti_arm_hdl_fp_t thumb_handle_insn
[8] =
12876 thumb_record_shift_add_sub
, /* 000. */
12877 thumb_record_add_sub_cmp_mov
, /* 001. */
12878 thumb_record_ld_st_reg_offset
, /* 010. */
12879 thumb_record_ld_st_imm_offset
, /* 011. */
12880 thumb_record_ld_st_stack
, /* 100. */
12881 thumb_record_misc
, /* 101. */
12882 thumb_record_ldm_stm_swi
, /* 110. */
12883 thumb_record_branch
/* 111. */
12886 uint32_t ret
= 0; /* return value: negative:failure 0:success. */
12887 uint32_t insn_id
= 0;
12889 if (extract_arm_insn (arm_record
, insn_size
))
12893 printf_unfiltered (_("Process record: error reading memory at "
12894 "addr %s len = %d.\n"),
12895 paddress (arm_record
->gdbarch
,
12896 arm_record
->this_addr
), insn_size
);
12900 else if (ARM_RECORD
== record_type
)
12902 arm_record
->cond
= bits (arm_record
->arm_insn
, 28, 31);
12903 insn_id
= bits (arm_record
->arm_insn
, 25, 27);
12905 if (arm_record
->cond
== 0xf)
12906 ret
= arm_record_extension_space (arm_record
);
12909 /* If this insn has fallen into extension space
12910 then we need not decode it anymore. */
12911 ret
= arm_handle_insn
[insn_id
] (arm_record
);
12913 if (ret
!= ARM_RECORD_SUCCESS
)
12915 arm_record_unsupported_insn (arm_record
);
12919 else if (THUMB_RECORD
== record_type
)
12921 /* As thumb does not have condition codes, we set negative. */
12922 arm_record
->cond
= -1;
12923 insn_id
= bits (arm_record
->arm_insn
, 13, 15);
12924 ret
= thumb_handle_insn
[insn_id
] (arm_record
);
12925 if (ret
!= ARM_RECORD_SUCCESS
)
12927 arm_record_unsupported_insn (arm_record
);
12931 else if (THUMB2_RECORD
== record_type
)
12933 /* As thumb does not have condition codes, we set negative. */
12934 arm_record
->cond
= -1;
12936 /* Swap first half of 32bit thumb instruction with second half. */
12937 arm_record
->arm_insn
12938 = (arm_record
->arm_insn
>> 16) | (arm_record
->arm_insn
<< 16);
12940 ret
= thumb2_record_decode_insn_handler (arm_record
);
12942 if (ret
!= ARM_RECORD_SUCCESS
)
12944 arm_record_unsupported_insn (arm_record
);
12950 /* Throw assertion. */
12951 gdb_assert_not_reached ("not a valid instruction, could not decode");
12958 /* Cleans up local record registers and memory allocations. */
12961 deallocate_reg_mem (insn_decode_record
*record
)
12963 xfree (record
->arm_regs
);
12964 xfree (record
->arm_mems
);
12968 /* Parse the current instruction and record the values of the registers and
12969 memory that will be changed in current instruction to record_arch_list".
12970 Return -1 if something is wrong. */
12973 arm_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
12974 CORE_ADDR insn_addr
)
12977 uint32_t no_of_rec
= 0;
12978 uint32_t ret
= 0; /* return value: -1:record failure ; 0:success */
12979 ULONGEST t_bit
= 0, insn_id
= 0;
12981 ULONGEST u_regval
= 0;
12983 insn_decode_record arm_record
;
12985 memset (&arm_record
, 0, sizeof (insn_decode_record
));
12986 arm_record
.regcache
= regcache
;
12987 arm_record
.this_addr
= insn_addr
;
12988 arm_record
.gdbarch
= gdbarch
;
12991 if (record_debug
> 1)
12993 fprintf_unfiltered (gdb_stdlog
, "Process record: arm_process_record "
12995 paddress (gdbarch
, arm_record
.this_addr
));
12998 if (extract_arm_insn (&arm_record
, 2))
13002 printf_unfiltered (_("Process record: error reading memory at "
13003 "addr %s len = %d.\n"),
13004 paddress (arm_record
.gdbarch
,
13005 arm_record
.this_addr
), 2);
13010 /* Check the insn, whether it is thumb or arm one. */
13012 t_bit
= arm_psr_thumb_bit (arm_record
.gdbarch
);
13013 regcache_raw_read_unsigned (arm_record
.regcache
, ARM_PS_REGNUM
, &u_regval
);
13016 if (!(u_regval
& t_bit
))
13018 /* We are decoding arm insn. */
13019 ret
= decode_insn (&arm_record
, ARM_RECORD
, ARM_INSN_SIZE_BYTES
);
13023 insn_id
= bits (arm_record
.arm_insn
, 11, 15);
13024 /* is it thumb2 insn? */
13025 if ((0x1D == insn_id
) || (0x1E == insn_id
) || (0x1F == insn_id
))
13027 ret
= decode_insn (&arm_record
, THUMB2_RECORD
,
13028 THUMB2_INSN_SIZE_BYTES
);
13032 /* We are decoding thumb insn. */
13033 ret
= decode_insn (&arm_record
, THUMB_RECORD
, THUMB_INSN_SIZE_BYTES
);
13039 /* Record registers. */
13040 record_full_arch_list_add_reg (arm_record
.regcache
, ARM_PC_REGNUM
);
13041 if (arm_record
.arm_regs
)
13043 for (no_of_rec
= 0; no_of_rec
< arm_record
.reg_rec_count
; no_of_rec
++)
13045 if (record_full_arch_list_add_reg
13046 (arm_record
.regcache
, arm_record
.arm_regs
[no_of_rec
]))
13050 /* Record memories. */
13051 if (arm_record
.arm_mems
)
13053 for (no_of_rec
= 0; no_of_rec
< arm_record
.mem_rec_count
; no_of_rec
++)
13055 if (record_full_arch_list_add_mem
13056 ((CORE_ADDR
)arm_record
.arm_mems
[no_of_rec
].addr
,
13057 arm_record
.arm_mems
[no_of_rec
].len
))
13062 if (record_full_arch_list_add_end ())
13067 deallocate_reg_mem (&arm_record
);