1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "coff/internal.h" /* Internal format of COFF symbols in BFD */
30 #include "dis-asm.h" /* For register flavors. */
31 #include <ctype.h> /* for isupper () */
35 #include "solib-svr4.h"
37 /* Each OS has a different mechanism for accessing the various
38 registers stored in the sigcontext structure.
40 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
41 function pointer) which may be used to determine the addresses
42 of the various saved registers in the sigcontext structure.
44 For the ARM target, there are three parameters to this function.
45 The first is the pc value of the frame under consideration, the
46 second the stack pointer of this frame, and the last is the
47 register number to fetch.
49 If the tm.h file does not define this macro, then it's assumed that
50 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
53 When it comes time to multi-arching this code, see the identically
54 named machinery in ia64-tdep.c for an example of how it could be
55 done. It should not be necessary to modify the code below where
56 this macro is used. */
58 #ifdef SIGCONTEXT_REGISTER_ADDRESS
59 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
60 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
63 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
64 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
67 extern void _initialize_arm_tdep (void);
69 /* Number of different reg name sets (options). */
70 static int num_flavor_options
;
72 /* We have more registers than the disassembler as gdb can print the value
73 of special registers as well.
74 The general register names are overwritten by whatever is being used by
75 the disassembler at the moment. We also adjust the case of cpsr and fps. */
77 /* Initial value: Register names used in ARM's ISA documentation. */
78 static char * arm_register_name_strings
[] =
79 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
80 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
81 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
82 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
83 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
84 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
85 "fps", "cpsr" }; /* 24 25 */
86 char **arm_register_names
= arm_register_name_strings
;
88 /* Valid register name flavors. */
89 static const char **valid_flavors
;
91 /* Disassembly flavor to use. Default to "std" register names. */
92 static const char *disassembly_flavor
;
93 static int current_option
; /* Index to that option in the opcodes table. */
95 /* This is used to keep the bfd arch_info in sync with the disassembly
97 static void set_disassembly_flavor_sfunc(char *, int,
98 struct cmd_list_element
*);
99 static void set_disassembly_flavor (void);
101 static void convert_from_extended (void *ptr
, void *dbl
);
103 /* Define other aspects of the stack frame. We keep the offsets of
104 all saved registers, 'cause we need 'em a lot! We also keep the
105 current size of the stack frame, and the offset of the frame
106 pointer from the stack pointer (for frameless functions, and when
107 we're still in the prologue of a function with a frame) */
109 struct frame_extra_info
111 struct frame_saved_regs fsr
;
117 /* Addresses for calling Thumb functions have the bit 0 set.
118 Here are some macros to test, set, or clear bit 0 of addresses. */
119 #define IS_THUMB_ADDR(addr) ((addr) & 1)
120 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
121 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
123 /* Will a function return an aggregate type in memory or in a
124 register? Return 0 if an aggregate type can be returned in a
125 register, 1 if it must be returned in memory. */
128 arm_use_struct_convention (int gcc_p
, struct type
*type
)
131 register enum type_code code
;
133 /* In the ARM ABI, "integer" like aggregate types are returned in
134 registers. For an aggregate type to be integer like, its size
135 must be less than or equal to REGISTER_SIZE and the offset of
136 each addressable subfield must be zero. Note that bit fields are
137 not addressable, and all addressable subfields of unions always
138 start at offset zero.
140 This function is based on the behaviour of GCC 2.95.1.
141 See: gcc/arm.c: arm_return_in_memory() for details.
143 Note: All versions of GCC before GCC 2.95.2 do not set up the
144 parameters correctly for a function returning the following
145 structure: struct { float f;}; This should be returned in memory,
146 not a register. Richard Earnshaw sent me a patch, but I do not
147 know of any way to detect if a function like the above has been
148 compiled with the correct calling convention. */
150 /* All aggregate types that won't fit in a register must be returned
152 if (TYPE_LENGTH (type
) > REGISTER_SIZE
)
157 /* The only aggregate types that can be returned in a register are
158 structs and unions. Arrays must be returned in memory. */
159 code
= TYPE_CODE (type
);
160 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
165 /* Assume all other aggregate types can be returned in a register.
166 Run a check for structures, unions and arrays. */
169 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
172 /* Need to check if this struct/union is "integer" like. For
173 this to be true, its size must be less than or equal to
174 REGISTER_SIZE and the offset of each addressable subfield
175 must be zero. Note that bit fields are not addressable, and
176 unions always start at offset zero. If any of the subfields
177 is a floating point type, the struct/union cannot be an
180 /* For each field in the object, check:
181 1) Is it FP? --> yes, nRc = 1;
182 2) Is it addressable (bitpos != 0) and
183 not packed (bitsize == 0)?
187 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
189 enum type_code field_type_code
;
190 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
192 /* Is it a floating point type field? */
193 if (field_type_code
== TYPE_CODE_FLT
)
199 /* If bitpos != 0, then we have to care about it. */
200 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
202 /* Bitfields are not addressable. If the field bitsize is
203 zero, then the field is not packed. Hence it cannot be
204 a bitfield or any other packed type. */
205 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
218 arm_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*thisframe
)
220 return (chain
!= 0 && (FRAME_SAVED_PC (thisframe
) >= LOWEST_PC
));
223 /* Set to true if the 32-bit mode is in use. */
227 /* Flag set by arm_fix_call_dummy that tells whether the target
228 function is a Thumb function. This flag is checked by
229 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
230 its use in valops.c) to pass the function address as an additional
233 static int target_is_thumb
;
235 /* Flag set by arm_fix_call_dummy that tells whether the calling
236 function is a Thumb function. This flag is checked by
237 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
239 static int caller_is_thumb
;
241 /* Determine if the program counter specified in MEMADDR is in a Thumb
245 arm_pc_is_thumb (CORE_ADDR memaddr
)
247 struct minimal_symbol
*sym
;
249 /* If bit 0 of the address is set, assume this is a Thumb address. */
250 if (IS_THUMB_ADDR (memaddr
))
253 /* Thumb functions have a "special" bit set in minimal symbols. */
254 sym
= lookup_minimal_symbol_by_pc (memaddr
);
257 return (MSYMBOL_IS_SPECIAL (sym
));
265 /* Determine if the program counter specified in MEMADDR is in a call
266 dummy being called from a Thumb function. */
269 arm_pc_is_thumb_dummy (CORE_ADDR memaddr
)
271 CORE_ADDR sp
= read_sp ();
273 /* FIXME: Until we switch for the new call dummy macros, this heuristic
274 is the best we can do. We are trying to determine if the pc is on
275 the stack, which (hopefully) will only happen in a call dummy.
276 We hope the current stack pointer is not so far alway from the dummy
277 frame location (true if we have not pushed large data structures or
278 gone too many levels deep) and that our 1024 is not enough to consider
279 code regions as part of the stack (true for most practical purposes) */
280 if (PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 1024))
281 return caller_is_thumb
;
287 arm_addr_bits_remove (CORE_ADDR val
)
289 if (arm_pc_is_thumb (val
))
290 return (val
& (arm_apcs_32
? 0xfffffffe : 0x03fffffe));
292 return (val
& (arm_apcs_32
? 0xfffffffc : 0x03fffffc));
296 arm_saved_pc_after_call (struct frame_info
*frame
)
298 return ADDR_BITS_REMOVE (read_register (LR_REGNUM
));
302 arm_frameless_function_invocation (struct frame_info
*fi
)
304 CORE_ADDR func_start
, after_prologue
;
307 func_start
= (get_pc_function_start ((fi
)->pc
) + FUNCTION_START_OFFSET
);
308 after_prologue
= SKIP_PROLOGUE (func_start
);
310 /* There are some frameless functions whose first two instructions
311 follow the standard APCS form, in which case after_prologue will
312 be func_start + 8. */
314 frameless
= (after_prologue
< func_start
+ 12);
318 /* A typical Thumb prologue looks like this:
322 Sometimes the latter instruction may be replaced by:
330 or, on tpcs, like this:
337 There is always one instruction of three classes:
342 When we have found at least one of each class we are done with the prolog.
343 Note that the "sub sp, #NN" before the push does not count.
347 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
349 CORE_ADDR current_pc
;
350 int findmask
= 0; /* findmask:
351 bit 0 - push { rlist }
352 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
353 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
356 for (current_pc
= pc
; current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40; current_pc
+= 2)
358 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
360 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
362 findmask
|= 1; /* push found */
364 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
366 if ((findmask
& 1) == 0) /* before push ? */
369 findmask
|= 4; /* add/sub sp found */
371 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
373 findmask
|= 2; /* setting of r7 found */
375 else if (insn
== 0x466f) /* mov r7, sp */
377 findmask
|= 2; /* setting of r7 found */
380 continue; /* something in the prolog that we don't care about or some
381 instruction from outside the prolog scheduled here for optimization */
387 /* The APCS (ARM Procedure Call Standard) defines the following
391 [stmfd sp!, {a1,a2,a3,a4}]
392 stmfd sp!, {...,fp,ip,lr,pc}
393 [stfe f7, [sp, #-12]!]
394 [stfe f6, [sp, #-12]!]
395 [stfe f5, [sp, #-12]!]
396 [stfe f4, [sp, #-12]!]
397 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
400 arm_skip_prologue (CORE_ADDR pc
)
404 CORE_ADDR func_addr
, func_end
;
406 struct symtab_and_line sal
;
408 /* See what the symbol table says. */
410 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
414 /* Found a function. */
415 sym
= lookup_symbol (func_name
, NULL
, VAR_NAMESPACE
, NULL
, NULL
);
416 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
418 /* Don't use this trick for assembly source files. */
419 sal
= find_pc_line (func_addr
, 0);
420 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
425 /* Check if this is Thumb code. */
426 if (arm_pc_is_thumb (pc
))
427 return thumb_skip_prologue (pc
, func_end
);
429 /* Can't find the prologue end in the symbol table, try it the hard way
430 by disassembling the instructions. */
432 inst
= read_memory_integer (skip_pc
, 4);
433 if (inst
!= 0xe1a0c00d) /* mov ip, sp */
437 inst
= read_memory_integer (skip_pc
, 4);
438 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
441 inst
= read_memory_integer (skip_pc
, 4);
444 if ((inst
& 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */
448 inst
= read_memory_integer (skip_pc
, 4);
450 /* Any insns after this point may float into the code, if it makes
451 for better instruction scheduling, so we skip them only if we
452 find them, but still consdier the function to be frame-ful. */
454 /* We may have either one sfmfd instruction here, or several stfe
455 insns, depending on the version of floating point code we
457 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
460 inst
= read_memory_integer (skip_pc
, 4);
464 while ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
467 inst
= read_memory_integer (skip_pc
, 4);
471 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
477 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
478 This function decodes a Thumb function prologue to determine:
479 1) the size of the stack frame
480 2) which registers are saved on it
481 3) the offsets of saved regs
482 4) the offset from the stack pointer to the frame pointer
483 This information is stored in the "extra" fields of the frame_info.
485 A typical Thumb function prologue would create this stack frame
486 (offsets relative to FP)
487 old SP -> 24 stack parameters
490 R7 -> 0 local variables (16 bytes)
491 SP -> -12 additional stack space (12 bytes)
492 The frame size would thus be 36 bytes, and the frame offset would be
493 12 bytes. The frame register is R7.
495 The comments for thumb_skip_prolog() describe the algorithm we use to detect
496 the end of the prolog */
500 thumb_scan_prologue (struct frame_info
*fi
)
502 CORE_ADDR prologue_start
;
503 CORE_ADDR prologue_end
;
504 CORE_ADDR current_pc
;
505 int saved_reg
[16]; /* which register has been copied to register n? */
506 int findmask
= 0; /* findmask:
507 bit 0 - push { rlist }
508 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
509 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
513 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
515 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
517 if (sal
.line
== 0) /* no line info, use current PC */
518 prologue_end
= fi
->pc
;
519 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
520 prologue_end
= sal
.end
; /* (probably means no prologue) */
523 prologue_end
= prologue_start
+ 40; /* We're in the boondocks: allow for */
524 /* 16 pushes, an add, and "mv fp,sp" */
526 prologue_end
= min (prologue_end
, fi
->pc
);
528 /* Initialize the saved register map. When register H is copied to
529 register L, we will put H in saved_reg[L]. */
530 for (i
= 0; i
< 16; i
++)
533 /* Search the prologue looking for instructions that set up the
534 frame pointer, adjust the stack pointer, and save registers.
535 Do this until all basic prolog instructions are found. */
538 for (current_pc
= prologue_start
;
539 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
546 insn
= read_memory_unsigned_integer (current_pc
, 2);
548 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
551 findmask
|= 1; /* push found */
552 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
553 whether to save LR (R14). */
554 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
556 /* Calculate offsets of saved R0-R7 and LR. */
557 for (regno
= LR_REGNUM
; regno
>= 0; regno
--)
558 if (mask
& (1 << regno
))
561 fi
->fsr
.regs
[saved_reg
[regno
]] = -(fi
->framesize
);
562 saved_reg
[regno
] = regno
; /* reset saved register map */
565 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
567 if ((findmask
& 1) == 0) /* before push ? */
570 findmask
|= 4; /* add/sub sp found */
572 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
573 if (insn
& 0x80) /* is it signed? (==subtracting) */
575 fi
->frameoffset
+= offset
;
578 fi
->framesize
-= offset
;
580 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
582 findmask
|= 2; /* setting of r7 found */
583 fi
->framereg
= THUMB_FP_REGNUM
;
584 fi
->frameoffset
= (insn
& 0xff) << 2; /* get scaled offset */
586 else if (insn
== 0x466f) /* mov r7, sp */
588 findmask
|= 2; /* setting of r7 found */
589 fi
->framereg
= THUMB_FP_REGNUM
;
591 saved_reg
[THUMB_FP_REGNUM
] = SP_REGNUM
;
593 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
595 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
596 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
597 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
600 continue; /* something in the prolog that we don't care about or some
601 instruction from outside the prolog scheduled here for optimization */
605 /* Check if prologue for this frame's PC has already been scanned. If
606 it has, copy the relevant information about that prologue and
607 return non-zero. Otherwise do not copy anything and return zero.
609 The information saved in the cache includes:
610 * the frame register number;
611 * the size of the stack frame;
612 * the offsets of saved regs (relative to the old SP); and
613 * the offset from the stack pointer to the frame pointer
615 The cache contains only one entry, since this is adequate for the
616 typical sequence of prologue scan requests we get. When performing
617 a backtrace, GDB will usually ask to scan the same function twice
618 in a row (once to get the frame chain, and once to fill in the
619 extra frame information). */
621 static struct frame_info prologue_cache
;
624 check_prologue_cache (struct frame_info
*fi
)
628 if (fi
->pc
== prologue_cache
.pc
)
630 fi
->framereg
= prologue_cache
.framereg
;
631 fi
->framesize
= prologue_cache
.framesize
;
632 fi
->frameoffset
= prologue_cache
.frameoffset
;
633 for (i
= 0; i
< NUM_REGS
; i
++)
634 fi
->fsr
.regs
[i
] = prologue_cache
.fsr
.regs
[i
];
642 /* Copy the prologue information from fi to the prologue cache. */
645 save_prologue_cache (struct frame_info
*fi
)
649 prologue_cache
.pc
= fi
->pc
;
650 prologue_cache
.framereg
= fi
->framereg
;
651 prologue_cache
.framesize
= fi
->framesize
;
652 prologue_cache
.frameoffset
= fi
->frameoffset
;
654 for (i
= 0; i
< NUM_REGS
; i
++)
655 prologue_cache
.fsr
.regs
[i
] = fi
->fsr
.regs
[i
];
659 /* This function decodes an ARM function prologue to determine:
660 1) the size of the stack frame
661 2) which registers are saved on it
662 3) the offsets of saved regs
663 4) the offset from the stack pointer to the frame pointer
664 This information is stored in the "extra" fields of the frame_info.
666 There are two basic forms for the ARM prologue. The fixed argument
667 function call will look like:
670 stmfd sp!, {fp, ip, lr, pc}
674 Which would create this stack frame (offsets relative to FP):
675 IP -> 4 (caller's stack)
676 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
677 -4 LR (return address in caller)
678 -8 IP (copy of caller's SP)
680 SP -> -28 Local variables
682 The frame size would thus be 32 bytes, and the frame offset would be
683 28 bytes. The stmfd call can also save any of the vN registers it
684 plans to use, which increases the frame size accordingly.
686 Note: The stored PC is 8 off of the STMFD instruction that stored it
687 because the ARM Store instructions always store PC + 8 when you read
690 A variable argument function call will look like:
693 stmfd sp!, {a1, a2, a3, a4}
694 stmfd sp!, {fp, ip, lr, pc}
697 Which would create this stack frame (offsets relative to FP):
698 IP -> 20 (caller's stack)
703 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
704 -4 LR (return address in caller)
705 -8 IP (copy of caller's SP)
707 SP -> -28 Local variables
709 The frame size would thus be 48 bytes, and the frame offset would be
712 There is another potential complication, which is that the optimizer
713 will try to separate the store of fp in the "stmfd" instruction from
714 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
715 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
717 Also, note, the original version of the ARM toolchain claimed that there
720 instruction at the end of the prologue. I have never seen GCC produce
721 this, and the ARM docs don't mention it. We still test for it below in
727 arm_scan_prologue (struct frame_info
*fi
)
729 int regno
, sp_offset
, fp_offset
;
730 LONGEST return_value
;
731 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
733 /* Check if this function is already in the cache of frame information. */
734 if (check_prologue_cache (fi
))
737 /* Assume there is no frame until proven otherwise. */
738 fi
->framereg
= SP_REGNUM
;
742 /* Check for Thumb prologue. */
743 if (arm_pc_is_thumb (fi
->pc
))
745 thumb_scan_prologue (fi
);
746 save_prologue_cache (fi
);
750 /* Find the function prologue. If we can't find the function in
751 the symbol table, peek in the stack frame to find the PC. */
752 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
754 /* One way to find the end of the prologue (which works well
755 for unoptimized code) is to do the following:
757 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
760 prologue_end = fi->pc;
761 else if (sal.end < prologue_end)
762 prologue_end = sal.end;
764 This mechanism is very accurate so long as the optimizer
765 doesn't move any instructions from the function body into the
766 prologue. If this happens, sal.end will be the last
767 instruction in the first hunk of prologue code just before
768 the first instruction that the scheduler has moved from
769 the body to the prologue.
771 In order to make sure that we scan all of the prologue
772 instructions, we use a slightly less accurate mechanism which
773 may scan more than necessary. To help compensate for this
774 lack of accuracy, the prologue scanning loop below contains
775 several clauses which'll cause the loop to terminate early if
776 an implausible prologue instruction is encountered.
782 is a suitable endpoint since it accounts for the largest
783 possible prologue plus up to five instructions inserted by
786 if (prologue_end
> prologue_start
+ 64)
788 prologue_end
= prologue_start
+ 64; /* See above. */
793 /* Get address of the stmfd in the prologue of the callee; the saved
794 PC is the address of the stmfd + 8. */
795 if (!safe_read_memory_integer (fi
->frame
, 4, &return_value
))
799 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
800 prologue_end
= prologue_start
+ 64; /* See above. */
804 /* Now search the prologue looking for instructions that set up the
805 frame pointer, adjust the stack pointer, and save registers.
807 Be careful, however, and if it doesn't look like a prologue,
808 don't try to scan it. If, for instance, a frameless function
809 begins with stmfd sp!, then we will tell ourselves there is
810 a frame, which will confuse stack traceback, as well ad"finish"
811 and other operations that rely on a knowledge of the stack
814 In the APCS, the prologue should start with "mov ip, sp" so
815 if we don't see this as the first insn, we will stop. */
817 sp_offset
= fp_offset
= 0;
819 if (read_memory_unsigned_integer (prologue_start
, 4)
820 == 0xe1a0c00d) /* mov ip, sp */
822 for (current_pc
= prologue_start
+ 4; current_pc
< prologue_end
;
825 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
827 if ((insn
& 0xffff0000) == 0xe92d0000)
828 /* stmfd sp!, {..., fp, ip, lr, pc}
830 stmfd sp!, {a1, a2, a3, a4} */
832 int mask
= insn
& 0xffff;
834 /* Calculate offsets of saved registers. */
835 for (regno
= PC_REGNUM
; regno
>= 0; regno
--)
836 if (mask
& (1 << regno
))
839 fi
->fsr
.regs
[regno
] = sp_offset
;
842 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
844 unsigned imm
= insn
& 0xff; /* immediate value */
845 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
846 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
848 fi
->framereg
= FP_REGNUM
;
850 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
852 unsigned imm
= insn
& 0xff; /* immediate value */
853 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
854 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
857 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
860 regno
= F0_REGNUM
+ ((insn
>> 12) & 0x07);
861 fi
->fsr
.regs
[regno
] = sp_offset
;
863 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
866 unsigned int fp_start_reg
, fp_bound_reg
;
868 if ((insn
& 0x800) == 0x800) /* N0 is set */
870 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
877 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
883 fp_start_reg
= F0_REGNUM
+ ((insn
>> 12) & 0x7);
884 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
885 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
888 fi
->fsr
.regs
[fp_start_reg
++] = sp_offset
;
891 else if ((insn
& 0xf0000000) != 0xe0000000)
892 break; /* Condition not true, exit early */
893 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
894 break; /* Don't scan past a block load */
896 /* The optimizer might shove anything into the prologue,
897 so we just skip what we don't recognize. */
902 /* The frame size is just the negative of the offset (from the original SP)
903 of the last thing thing we pushed on the stack. The frame offset is
904 [new FP] - [new SP]. */
905 fi
->framesize
= -sp_offset
;
906 fi
->frameoffset
= fp_offset
- sp_offset
;
908 save_prologue_cache (fi
);
911 /* Find REGNUM on the stack. Otherwise, it's in an active register.
912 One thing we might want to do here is to check REGNUM against the
913 clobber mask, and somehow flag it as invalid if it isn't saved on
914 the stack somewhere. This would provide a graceful failure mode
915 when trying to get the value of caller-saves registers for an inner
919 arm_find_callers_reg (struct frame_info
*fi
, int regnum
)
921 for (; fi
; fi
= fi
->next
)
923 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
924 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
925 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
928 if (fi
->fsr
.regs
[regnum
] != 0)
929 return read_memory_integer (fi
->fsr
.regs
[regnum
],
930 REGISTER_RAW_SIZE (regnum
));
931 return read_register (regnum
);
934 /* Function: frame_chain
935 Given a GDB frame, determine the address of the calling function's frame.
936 This will be used to create a new GDB frame struct, and then
937 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
938 For ARM, we save the frame size when we initialize the frame_info.
940 The original definition of this function was a macro in tm-arm.h:
941 { In the case of the ARM, the frame's nominal address is the FP value,
942 and 12 bytes before comes the saved previous FP value as a 4-byte word. }
944 #define FRAME_CHAIN(thisframe) \
945 ((thisframe)->pc >= LOWEST_PC ? \
946 read_memory_integer ((thisframe)->frame - 12, 4) :\
952 arm_frame_chain (struct frame_info
*fi
)
954 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
955 CORE_ADDR fn_start
, callers_pc
, fp
;
957 /* is this a dummy frame? */
958 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
959 return fi
->frame
; /* dummy frame same as caller's frame */
961 /* is caller-of-this a dummy frame? */
962 callers_pc
= FRAME_SAVED_PC (fi
); /* find out who called us: */
963 fp
= arm_find_callers_reg (fi
, FP_REGNUM
);
964 if (PC_IN_CALL_DUMMY (callers_pc
, fp
, fp
))
965 return fp
; /* dummy frame's frame may bear no relation to ours */
967 if (find_pc_partial_function (fi
->pc
, 0, &fn_start
, 0))
968 if (fn_start
== entry_point_address ())
969 return 0; /* in _start fn, don't chain further */
971 CORE_ADDR caller_pc
, fn_start
;
972 struct frame_info caller_fi
;
973 int framereg
= fi
->framereg
;
975 if (fi
->pc
< LOWEST_PC
)
978 /* If the caller is the startup code, we're at the end of the chain. */
979 caller_pc
= FRAME_SAVED_PC (fi
);
980 if (find_pc_partial_function (caller_pc
, 0, &fn_start
, 0))
981 if (fn_start
== entry_point_address ())
984 /* If the caller is Thumb and the caller is ARM, or vice versa,
985 the frame register of the caller is different from ours.
986 So we must scan the prologue of the caller to determine its
987 frame register number. */
988 if (arm_pc_is_thumb (caller_pc
) != arm_pc_is_thumb (fi
->pc
))
990 memset (&caller_fi
, 0, sizeof (caller_fi
));
991 caller_fi
.pc
= caller_pc
;
992 arm_scan_prologue (&caller_fi
);
993 framereg
= caller_fi
.framereg
;
996 /* If the caller used a frame register, return its value.
997 Otherwise, return the caller's stack pointer. */
998 if (framereg
== FP_REGNUM
|| framereg
== THUMB_FP_REGNUM
)
999 return arm_find_callers_reg (fi
, framereg
);
1001 return fi
->frame
+ fi
->framesize
;
1004 /* This function actually figures out the frame address for a given pc
1005 and sp. This is tricky because we sometimes don't use an explicit
1006 frame pointer, and the previous stack pointer isn't necessarily
1007 recorded on the stack. The only reliable way to get this info is
1008 to examine the prologue. FROMLEAF is a little confusing, it means
1009 this is the next frame up the chain AFTER a frameless function. If
1010 this is true, then the frame value for this frame is still in the
1014 arm_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1019 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1021 memset (fi
->fsr
.regs
, '\000', sizeof fi
->fsr
.regs
);
1023 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1024 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1026 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1027 by assuming it's always FP. */
1028 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
, SP_REGNUM
);
1030 fi
->frameoffset
= 0;
1036 /* Determine whether or not we're in a sigtramp frame.
1037 Unfortunately, it isn't sufficient to test
1038 fi->signal_handler_caller because this value is sometimes set
1039 after invoking INIT_EXTRA_FRAME_INFO. So we test *both*
1040 fi->signal_handler_caller and IN_SIGTRAMP to determine if we need
1041 to use the sigcontext addresses for the saved registers.
1043 Note: If an ARM IN_SIGTRAMP method ever needs to compare against
1044 the name of the function, the code below will have to be changed
1045 to first fetch the name of the function and then pass this name
1048 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1049 && (fi
->signal_handler_caller
|| IN_SIGTRAMP (fi
->pc
, 0)))
1056 sp
= fi
->next
->frame
- fi
->next
->frameoffset
+ fi
->next
->framesize
;
1058 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1059 fi
->fsr
.regs
[reg
] = SIGCONTEXT_REGISTER_ADDRESS (sp
, fi
->pc
, reg
);
1061 /* FIXME: What about thumb mode? */
1062 fi
->framereg
= SP_REGNUM
;
1063 fi
->frame
= read_memory_integer (fi
->fsr
.regs
[fi
->framereg
], 4);
1065 fi
->frameoffset
= 0;
1070 arm_scan_prologue (fi
);
1073 /* this is the innermost frame? */
1074 fi
->frame
= read_register (fi
->framereg
);
1075 else if (fi
->framereg
== FP_REGNUM
|| fi
->framereg
== THUMB_FP_REGNUM
)
1077 /* not the innermost frame */
1078 /* If we have an FP, the callee saved it. */
1079 if (fi
->next
->fsr
.regs
[fi
->framereg
] != 0)
1081 read_memory_integer (fi
->next
->fsr
.regs
[fi
->framereg
], 4);
1083 /* If we were called by a frameless fn. then our frame is
1084 still in the frame pointer register on the board... */
1085 fi
->frame
= read_fp ();
1088 /* Calculate actual addresses of saved registers using offsets
1089 determined by arm_scan_prologue. */
1090 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1091 if (fi
->fsr
.regs
[reg
] != 0)
1092 fi
->fsr
.regs
[reg
] += fi
->frame
+ fi
->framesize
- fi
->frameoffset
;
1097 /* Find the caller of this frame. We do this by seeing if LR_REGNUM
1098 is saved in the stack anywhere, otherwise we get it from the
1101 The old definition of this function was a macro:
1102 #define FRAME_SAVED_PC(FRAME) \
1103 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1106 arm_frame_saved_pc (struct frame_info
*fi
)
1108 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1109 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1110 return generic_read_register_dummy (fi
->pc
, fi
->frame
, PC_REGNUM
);
1114 CORE_ADDR pc
= arm_find_callers_reg (fi
, LR_REGNUM
);
1115 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1119 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1120 Examine the Program Status Register to decide which state we're in. */
1123 arm_target_read_fp (void)
1125 if (read_register (PS_REGNUM
) & 0x20) /* Bit 5 is Thumb state bit */
1126 return read_register (THUMB_FP_REGNUM
); /* R7 if Thumb */
1128 return read_register (FP_REGNUM
); /* R11 if ARM */
1131 /* Calculate the frame offsets of the saved registers (ARM version). */
1134 arm_frame_find_saved_regs (struct frame_info
*fi
,
1135 struct frame_saved_regs
*regaddr
)
1137 memcpy (regaddr
, &fi
->fsr
, sizeof (struct frame_saved_regs
));
1141 arm_push_dummy_frame (void)
1143 CORE_ADDR old_sp
= read_register (SP_REGNUM
);
1144 CORE_ADDR sp
= old_sp
;
1145 CORE_ADDR fp
, prologue_start
;
1148 /* Push the two dummy prologue instructions in reverse order,
1149 so that they'll be in the correct low-to-high order in memory. */
1150 /* sub fp, ip, #4 */
1151 sp
= push_word (sp
, 0xe24cb004);
1152 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1153 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
1155 /* Push a pointer to the dummy prologue + 12, because when stm
1156 instruction stores the PC, it stores the address of the stm
1157 instruction itself plus 12. */
1158 fp
= sp
= push_word (sp
, prologue_start
+ 12);
1159 sp
= push_word (sp
, read_register (PC_REGNUM
)); /* FIXME: was PS_REGNUM */
1160 sp
= push_word (sp
, old_sp
);
1161 sp
= push_word (sp
, read_register (FP_REGNUM
));
1163 for (regnum
= 10; regnum
>= 0; regnum
--)
1164 sp
= push_word (sp
, read_register (regnum
));
1166 write_register (FP_REGNUM
, fp
);
1167 write_register (THUMB_FP_REGNUM
, fp
);
1168 write_register (SP_REGNUM
, sp
);
1171 /* Fix up the call dummy, based on whether the processor is currently
1172 in Thumb or ARM mode, and whether the target function is Thumb or
1173 ARM. There are three different situations requiring three
1176 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1177 been copied into the dummy parameter to this function.
1178 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1179 "mov pc,r4" instruction patched to be a "bx r4" instead.
1180 * Thumb calling anything: uses the Thumb dummy defined below, which
1181 works for calling both ARM and Thumb functions.
1183 All three call dummies expect to receive the target function
1184 address in R4, with the low bit set if it's a Thumb function. */
1187 arm_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
1188 struct value
**args
, struct type
*type
, int gcc_p
)
1190 static short thumb_dummy
[4] =
1192 0xf000, 0xf801, /* bl label */
1193 0xdf18, /* swi 24 */
1194 0x4720, /* label: bx r4 */
1196 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
1198 /* Set flag indicating whether the current PC is in a Thumb function. */
1199 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
1201 /* If the target function is Thumb, set the low bit of the function
1202 address. And if the CPU is currently in ARM mode, patch the
1203 second instruction of call dummy to use a BX instruction to
1204 switch to Thumb mode. */
1205 target_is_thumb
= arm_pc_is_thumb (fun
);
1206 if (target_is_thumb
)
1209 if (!caller_is_thumb
)
1210 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
1213 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1214 instead of the ARM one that's already been copied. This will
1215 work for both Thumb and ARM target functions. */
1216 if (caller_is_thumb
)
1220 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
1222 for (i
= 0; i
< len
; i
++)
1224 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1225 p
+= sizeof (thumb_dummy
[0]);
1229 /* Put the target address in r4; the call dummy will copy this to
1231 write_register (4, fun
);
1234 /* Return the offset in the call dummy of the instruction that needs
1235 to have a breakpoint placed on it. This is the offset of the 'swi
1236 24' instruction, which is no longer actually used, but simply acts
1237 as a place-holder now.
1239 This implements the CALL_DUMMY_BREAK_OFFSET macro. */
1242 arm_call_dummy_breakpoint_offset (void)
1244 if (caller_is_thumb
)
1252 This function does not support passing parameters using the FPA
1253 variant of the APCS. It passes any floating point arguments in the
1254 general registers and/or on the stack. */
1257 arm_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
1258 int struct_return
, CORE_ADDR struct_addr
)
1261 int argnum
, argreg
, nstack_size
;
1263 /* Walk through the list of args and determine how large a temporary
1264 stack is required. Need to take care here as structs may be
1265 passed on the stack, and we have to to push them. */
1266 nstack_size
= -4 * REGISTER_SIZE
; /* Some arguments go into A1-A4. */
1267 if (struct_return
) /* The struct address goes in A1. */
1268 nstack_size
+= REGISTER_SIZE
;
1270 /* Walk through the arguments and add their size to nstack_size. */
1271 for (argnum
= 0; argnum
< nargs
; argnum
++)
1274 struct type
*arg_type
;
1276 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1277 len
= TYPE_LENGTH (arg_type
);
1279 /* ANSI C code passes float arguments as integers, K&R code
1280 passes float arguments as doubles. Correct for this here. */
1281 if (TYPE_CODE_FLT
== TYPE_CODE (arg_type
) && REGISTER_SIZE
== len
)
1282 nstack_size
+= FP_REGISTER_VIRTUAL_SIZE
;
1287 /* Allocate room on the stack, and initialize our stack frame
1290 if (nstack_size
> 0)
1296 /* Initialize the integer argument register pointer. */
1299 /* The struct_return pointer occupies the first parameter passing
1302 write_register (argreg
++, struct_addr
);
1304 /* Process arguments from left to right. Store as many as allowed
1305 in the parameter passing registers (A1-A4), and save the rest on
1306 the temporary stack. */
1307 for (argnum
= 0; argnum
< nargs
; argnum
++)
1312 enum type_code typecode
;
1313 struct type
*arg_type
, *target_type
;
1315 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1316 target_type
= TYPE_TARGET_TYPE (arg_type
);
1317 len
= TYPE_LENGTH (arg_type
);
1318 typecode
= TYPE_CODE (arg_type
);
1319 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
1321 /* ANSI C code passes float arguments as integers, K&R code
1322 passes float arguments as doubles. The .stabs record for
1323 for ANSI prototype floating point arguments records the
1324 type as FP_INTEGER, while a K&R style (no prototype)
1325 .stabs records the type as FP_FLOAT. In this latter case
1326 the compiler converts the float arguments to double before
1327 calling the function. */
1328 if (TYPE_CODE_FLT
== typecode
&& REGISTER_SIZE
== len
)
1331 dblval
= extract_floating (val
, len
);
1332 len
= TARGET_DOUBLE_BIT
/ TARGET_CHAR_BIT
;
1334 store_floating (val
, len
, dblval
);
1337 /* I don't know why this code was disable. The only logical use
1338 for a function pointer is to call that function, so setting
1339 the mode bit is perfectly fine. FN */
1340 /* If the argument is a pointer to a function, and it is a Thumb
1341 function, set the low bit of the pointer. */
1342 if (TYPE_CODE_PTR
== typecode
1343 && NULL
!= target_type
1344 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1346 CORE_ADDR regval
= extract_address (val
, len
);
1347 if (arm_pc_is_thumb (regval
))
1348 store_address (val
, len
, MAKE_THUMB_ADDR (regval
));
1351 /* Copy the argument to general registers or the stack in
1352 register-sized pieces. Large arguments are split between
1353 registers and stack. */
1356 int partial_len
= len
< REGISTER_SIZE
? len
: REGISTER_SIZE
;
1358 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1360 /* It's an argument being passed in a general register. */
1361 regval
= extract_address (val
, partial_len
);
1362 write_register (argreg
++, regval
);
1366 /* Push the arguments onto the stack. */
1367 write_memory ((CORE_ADDR
) fp
, val
, REGISTER_SIZE
);
1368 fp
+= REGISTER_SIZE
;
1376 /* Return adjusted stack pointer. */
1381 arm_pop_frame (void)
1384 struct frame_info
*frame
= get_current_frame ();
1386 if (!PC_IN_CALL_DUMMY(frame
->pc
, frame
->frame
, read_fp()))
1390 old_SP
= read_register (frame
->framereg
);
1391 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1392 if (frame
->fsr
.regs
[regnum
] != 0)
1393 write_register (regnum
,
1394 read_memory_integer (frame
->fsr
.regs
[regnum
], 4));
1396 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
1397 write_register (SP_REGNUM
, old_SP
);
1403 sp
= read_register (FP_REGNUM
);
1404 sp
-= sizeof(CORE_ADDR
); /* we don't care about this first word */
1406 write_register (PC_REGNUM
, read_memory_integer (sp
, 4));
1407 sp
-= sizeof(CORE_ADDR
);
1408 write_register (SP_REGNUM
, read_memory_integer (sp
, 4));
1409 sp
-= sizeof(CORE_ADDR
);
1410 write_register (FP_REGNUM
, read_memory_integer (sp
, 4));
1411 sp
-= sizeof(CORE_ADDR
);
1413 for (regnum
= 10; regnum
>= 0; regnum
--)
1415 write_register (regnum
, read_memory_integer (sp
, 4));
1416 sp
-= sizeof(CORE_ADDR
);
1420 flush_cached_frames ();
1424 print_fpu_flags (int flags
)
1426 if (flags
& (1 << 0))
1427 fputs ("IVO ", stdout
);
1428 if (flags
& (1 << 1))
1429 fputs ("DVZ ", stdout
);
1430 if (flags
& (1 << 2))
1431 fputs ("OFL ", stdout
);
1432 if (flags
& (1 << 3))
1433 fputs ("UFL ", stdout
);
1434 if (flags
& (1 << 4))
1435 fputs ("INX ", stdout
);
1440 arm_float_info (void)
1442 register unsigned long status
= read_register (FPS_REGNUM
);
1445 type
= (status
>> 24) & 127;
1446 printf ("%s FPU type %d\n",
1447 (status
& (1 << 31)) ? "Hardware" : "Software",
1449 fputs ("mask: ", stdout
);
1450 print_fpu_flags (status
>> 16);
1451 fputs ("flags: ", stdout
);
1452 print_fpu_flags (status
);
1456 arm_register_type (int regnum
)
1458 if (regnum
>= F0_REGNUM
&& regnum
< F0_REGNUM
+ NUM_FREGS
)
1460 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1461 return builtin_type_arm_ext_big
;
1463 return builtin_type_arm_ext_littlebyte_bigword
;
1466 return builtin_type_int32
;
1469 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1470 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1471 It is thought that this is is the floating-point register format on
1472 little-endian systems. */
1475 convert_from_extended (void *ptr
, void *dbl
)
1478 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1479 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1481 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1483 floatformat_from_doublest (TARGET_DOUBLE_FORMAT
, &d
, dbl
);
1487 convert_to_extended (void *dbl
, void *ptr
)
1490 floatformat_to_doublest (TARGET_DOUBLE_FORMAT
, ptr
, &d
);
1491 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1492 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1494 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1499 condition_true (unsigned long cond
, unsigned long status_reg
)
1501 if (cond
== INST_AL
|| cond
== INST_NV
)
1507 return ((status_reg
& FLAG_Z
) != 0);
1509 return ((status_reg
& FLAG_Z
) == 0);
1511 return ((status_reg
& FLAG_C
) != 0);
1513 return ((status_reg
& FLAG_C
) == 0);
1515 return ((status_reg
& FLAG_N
) != 0);
1517 return ((status_reg
& FLAG_N
) == 0);
1519 return ((status_reg
& FLAG_V
) != 0);
1521 return ((status_reg
& FLAG_V
) == 0);
1523 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1525 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1527 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1529 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1531 return (((status_reg
& FLAG_Z
) == 0) &&
1532 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1534 return (((status_reg
& FLAG_Z
) != 0) ||
1535 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1540 /* Support routines for single stepping. Calculate the next PC value. */
1541 #define submask(x) ((1L << ((x) + 1)) - 1)
1542 #define bit(obj,st) (((obj) >> (st)) & 1)
1543 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1544 #define sbits(obj,st,fn) \
1545 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1546 #define BranchDest(addr,instr) \
1547 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1550 static unsigned long
1551 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1552 unsigned long status_reg
)
1554 unsigned long res
, shift
;
1555 int rm
= bits (inst
, 0, 3);
1556 unsigned long shifttype
= bits (inst
, 5, 6);
1560 int rs
= bits (inst
, 8, 11);
1561 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1564 shift
= bits (inst
, 7, 11);
1567 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1568 + (bit (inst
, 4) ? 12 : 8))
1569 : read_register (rm
));
1574 res
= shift
>= 32 ? 0 : res
<< shift
;
1578 res
= shift
>= 32 ? 0 : res
>> shift
;
1584 res
= ((res
& 0x80000000L
)
1585 ? ~((~res
) >> shift
) : res
>> shift
);
1588 case 3: /* ROR/RRX */
1591 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1593 res
= (res
>> shift
) | (res
<< (32 - shift
));
1597 return res
& 0xffffffff;
1600 /* Return number of 1-bits in VAL. */
1603 bitcount (unsigned long val
)
1606 for (nbits
= 0; val
!= 0; nbits
++)
1607 val
&= val
- 1; /* delete rightmost 1-bit in val */
1612 thumb_get_next_pc (CORE_ADDR pc
)
1614 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1615 unsigned short inst1
= read_memory_integer (pc
, 2);
1616 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1617 unsigned long offset
;
1619 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1623 /* Fetch the saved PC from the stack. It's stored above
1624 all of the other registers. */
1625 offset
= bitcount (bits (inst1
, 0, 7)) * REGISTER_SIZE
;
1626 sp
= read_register (SP_REGNUM
);
1627 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1628 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1630 error ("Infinite loop detected");
1632 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1634 unsigned long status
= read_register (PS_REGNUM
);
1635 unsigned long cond
= bits (inst1
, 8, 11);
1636 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1637 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1639 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1641 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1643 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1645 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1646 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1647 nextpc
= pc_val
+ offset
;
1654 arm_get_next_pc (CORE_ADDR pc
)
1656 unsigned long pc_val
;
1657 unsigned long this_instr
;
1658 unsigned long status
;
1661 if (arm_pc_is_thumb (pc
))
1662 return thumb_get_next_pc (pc
);
1664 pc_val
= (unsigned long) pc
;
1665 this_instr
= read_memory_integer (pc
, 4);
1666 status
= read_register (PS_REGNUM
);
1667 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1669 if (condition_true (bits (this_instr
, 28, 31), status
))
1671 switch (bits (this_instr
, 24, 27))
1674 case 0x1: /* data processing */
1678 unsigned long operand1
, operand2
, result
= 0;
1682 if (bits (this_instr
, 12, 15) != 15)
1685 if (bits (this_instr
, 22, 25) == 0
1686 && bits (this_instr
, 4, 7) == 9) /* multiply */
1687 error ("Illegal update to pc in instruction");
1689 /* Multiply into PC */
1690 c
= (status
& FLAG_C
) ? 1 : 0;
1691 rn
= bits (this_instr
, 16, 19);
1692 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1694 if (bit (this_instr
, 25))
1696 unsigned long immval
= bits (this_instr
, 0, 7);
1697 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1698 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1701 else /* operand 2 is a shifted register */
1702 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1704 switch (bits (this_instr
, 21, 24))
1707 result
= operand1
& operand2
;
1711 result
= operand1
^ operand2
;
1715 result
= operand1
- operand2
;
1719 result
= operand2
- operand1
;
1723 result
= operand1
+ operand2
;
1727 result
= operand1
+ operand2
+ c
;
1731 result
= operand1
- operand2
+ c
;
1735 result
= operand2
- operand1
+ c
;
1741 case 0xb: /* tst, teq, cmp, cmn */
1742 result
= (unsigned long) nextpc
;
1746 result
= operand1
| operand2
;
1750 /* Always step into a function. */
1755 result
= operand1
& ~operand2
;
1762 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1765 error ("Infinite loop detected");
1770 case 0x5: /* data transfer */
1773 if (bit (this_instr
, 20))
1776 if (bits (this_instr
, 12, 15) == 15)
1782 if (bit (this_instr
, 22))
1783 error ("Illegal update to pc in instruction");
1785 /* byte write to PC */
1786 rn
= bits (this_instr
, 16, 19);
1787 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1788 if (bit (this_instr
, 24))
1791 int c
= (status
& FLAG_C
) ? 1 : 0;
1792 unsigned long offset
=
1793 (bit (this_instr
, 25)
1794 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1795 : bits (this_instr
, 0, 11));
1797 if (bit (this_instr
, 23))
1802 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1805 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1808 error ("Infinite loop detected");
1814 case 0x9: /* block transfer */
1815 if (bit (this_instr
, 20))
1818 if (bit (this_instr
, 15))
1823 if (bit (this_instr
, 23))
1826 unsigned long reglist
= bits (this_instr
, 0, 14);
1827 offset
= bitcount (reglist
) * 4;
1828 if (bit (this_instr
, 24)) /* pre */
1831 else if (bit (this_instr
, 24))
1835 unsigned long rn_val
=
1836 read_register (bits (this_instr
, 16, 19));
1838 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1842 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1844 error ("Infinite loop detected");
1849 case 0xb: /* branch & link */
1850 case 0xa: /* branch */
1852 nextpc
= BranchDest (pc
, this_instr
);
1854 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1856 error ("Infinite loop detected");
1862 case 0xe: /* coproc ops */
1867 fprintf (stderr
, "Bad bit-field extraction\n");
1875 /* single_step() is called just before we want to resume the inferior,
1876 if we want to single-step it but there is no hardware or kernel
1877 single-step support. We find the target of the coming instruction
1880 single_step is also called just after the inferior stops. If we had
1881 set up a simulated single-step, we undo our damage. */
1884 arm_software_single_step (ignore
, insert_bpt
)
1885 int ignore
; /* Signal, not needed */
1888 static int next_pc
; /* State between setting and unsetting. */
1889 static char break_mem
[BREAKPOINT_MAX
]; /* Temporary storage for mem@bpt */
1893 next_pc
= arm_get_next_pc (read_register (PC_REGNUM
));
1894 target_insert_breakpoint (next_pc
, break_mem
);
1897 target_remove_breakpoint (next_pc
, break_mem
);
1900 #include "bfd-in2.h"
1901 #include "libcoff.h"
1904 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
1906 if (arm_pc_is_thumb (memaddr
))
1908 static asymbol
*asym
;
1909 static combined_entry_type ce
;
1910 static struct coff_symbol_struct csym
;
1911 static struct _bfd fake_bfd
;
1912 static bfd_target fake_target
;
1914 if (csym
.native
== NULL
)
1916 /* Create a fake symbol vector containing a Thumb symbol. This is
1917 solely so that the code in print_insn_little_arm() and
1918 print_insn_big_arm() in opcodes/arm-dis.c will detect the presence
1919 of a Thumb symbol and switch to decoding Thumb instructions. */
1921 fake_target
.flavour
= bfd_target_coff_flavour
;
1922 fake_bfd
.xvec
= &fake_target
;
1923 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
1925 csym
.symbol
.the_bfd
= &fake_bfd
;
1926 csym
.symbol
.name
= "fake";
1927 asym
= (asymbol
*) & csym
;
1930 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
1931 info
->symbols
= &asym
;
1934 info
->symbols
= NULL
;
1936 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1937 return print_insn_big_arm (memaddr
, info
);
1939 return print_insn_little_arm (memaddr
, info
);
1942 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the
1943 program counter value to determine whether a 16-bit or 32-bit
1944 breakpoint should be used. It returns a pointer to a string of
1945 bytes that encode a breakpoint instruction, stores the length of
1946 the string to *lenptr, and adjusts the program counter (if
1947 necessary) to point to the actual memory location where the
1948 breakpoint should be inserted. */
1951 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1953 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
1955 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1957 static char thumb_breakpoint
[] = THUMB_BE_BREAKPOINT
;
1958 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1959 *lenptr
= sizeof (thumb_breakpoint
);
1960 return thumb_breakpoint
;
1964 static char thumb_breakpoint
[] = THUMB_LE_BREAKPOINT
;
1965 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1966 *lenptr
= sizeof (thumb_breakpoint
);
1967 return thumb_breakpoint
;
1972 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1974 static char arm_breakpoint
[] = ARM_BE_BREAKPOINT
;
1975 *lenptr
= sizeof (arm_breakpoint
);
1976 return arm_breakpoint
;
1980 static char arm_breakpoint
[] = ARM_LE_BREAKPOINT
;
1981 *lenptr
= sizeof (arm_breakpoint
);
1982 return arm_breakpoint
;
1987 /* Extract from an array REGBUF containing the (raw) register state a
1988 function return value of type TYPE, and copy that, in virtual
1989 format, into VALBUF. */
1992 arm_extract_return_value (struct type
*type
,
1993 char regbuf
[REGISTER_BYTES
],
1996 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
1997 convert_from_extended (®buf
[REGISTER_BYTE (F0_REGNUM
)], valbuf
);
1999 memcpy (valbuf
, ®buf
[REGISTER_BYTE (A1_REGNUM
)], TYPE_LENGTH (type
));
2002 /* Return non-zero if the PC is inside a thumb call thunk. */
2005 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2007 CORE_ADDR start_addr
;
2009 /* Find the starting address of the function containing the PC. If
2010 the caller didn't give us a name, look it up at the same time. */
2011 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
2014 return strncmp (name
, "_call_via_r", 11) == 0;
2017 /* If PC is in a Thumb call or return stub, return the address of the
2018 target PC, which is in a register. The thunk functions are called
2019 _called_via_xx, where x is the register name. The possible names
2020 are r0-r9, sl, fp, ip, sp, and lr. */
2023 arm_skip_stub (CORE_ADDR pc
)
2026 CORE_ADDR start_addr
;
2028 /* Find the starting address and name of the function containing the PC. */
2029 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2032 /* Call thunks always start with "_call_via_". */
2033 if (strncmp (name
, "_call_via_", 10) == 0)
2035 /* Use the name suffix to determine which register contains the
2037 static char *table
[15] =
2038 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2039 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2043 for (regno
= 0; regno
<= 14; regno
++)
2044 if (strcmp (&name
[10], table
[regno
]) == 0)
2045 return read_register (regno
);
2048 return 0; /* not a stub */
2051 /* If the user changes the register disassembly flavor used for info register
2052 and other commands, we have to also switch the flavor used in opcodes
2053 for disassembly output.
2054 This function is run in the set disassembly_flavor command, and does that. */
2057 set_disassembly_flavor_sfunc (char *args
, int from_tty
,
2058 struct cmd_list_element
*c
)
2060 set_disassembly_flavor ();
2064 set_disassembly_flavor (void)
2066 const char *setname
, *setdesc
, **regnames
;
2069 /* Find the flavor that the user wants in the opcodes table. */
2071 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2072 while ((disassembly_flavor
!= setname
)
2073 && (current
< num_flavor_options
))
2074 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2075 current_option
= current
;
2077 /* Fill our copy. */
2078 for (j
= 0; j
< numregs
; j
++)
2079 arm_register_names
[j
] = (char *) regnames
[j
];
2082 if (isupper (*regnames
[PC_REGNUM
]))
2084 arm_register_names
[FPS_REGNUM
] = "FPS";
2085 arm_register_names
[PS_REGNUM
] = "CPSR";
2089 arm_register_names
[FPS_REGNUM
] = "fps";
2090 arm_register_names
[PS_REGNUM
] = "cpsr";
2093 /* Synchronize the disassembler. */
2094 set_arm_regname_option (current
);
2097 /* arm_othernames implements the "othernames" command. This is kind
2098 of hacky, and I prefer the set-show disassembly-flavor which is
2099 also used for the x86 gdb. I will keep this around, however, in
2100 case anyone is actually using it. */
2103 arm_othernames (char *names
, int n
)
2105 /* Circle through the various flavors. */
2106 current_option
= (current_option
+ 1) % num_flavor_options
;
2108 disassembly_flavor
= valid_flavors
[current_option
];
2109 set_disassembly_flavor ();
2112 /* Fetch, and possibly build, an appropriate link_map_offsets structure
2113 for ARM linux targets using the struct offsets defined in <link.h>.
2114 Note, however, that link.h is not actually referred to in this file.
2115 Instead, the relevant structs offsets were obtained from examining
2116 link.h. (We can't refer to link.h from this file because the host
2117 system won't necessarily have it, or if it does, the structs which
2118 it defines will refer to the host system, not the target.) */
2120 struct link_map_offsets
*
2121 arm_linux_svr4_fetch_link_map_offsets (void)
2123 static struct link_map_offsets lmo
;
2124 static struct link_map_offsets
*lmp
= 0;
2130 lmo
.r_debug_size
= 8; /* Actual size is 20, but this is all we
2133 lmo
.r_map_offset
= 4;
2136 lmo
.link_map_size
= 20; /* Actual size is 552, but this is all we
2139 lmo
.l_addr_offset
= 0;
2140 lmo
.l_addr_size
= 4;
2142 lmo
.l_name_offset
= 4;
2143 lmo
.l_name_size
= 4;
2145 lmo
.l_next_offset
= 12;
2146 lmo
.l_next_size
= 4;
2148 lmo
.l_prev_offset
= 16;
2149 lmo
.l_prev_size
= 4;
2156 _initialize_arm_tdep (void)
2158 struct ui_file
*stb
;
2160 struct cmd_list_element
*new_cmd
;
2161 const char *setname
;
2162 const char *setdesc
;
2163 const char **regnames
;
2165 static char *helptext
;
2167 tm_print_insn
= gdb_print_insn_arm
;
2169 /* Get the number of possible sets of register names defined in opcodes. */
2170 num_flavor_options
= get_arm_regname_num_options ();
2172 /* Sync the opcode insn printer with our register viewer: */
2173 parse_arm_disassembler_option ("reg-names-std");
2175 /* Begin creating the help text. */
2176 stb
= mem_fileopen ();
2177 fprintf_unfiltered (stb
, "Set the disassembly flavor.\n\
2178 The valid values are:\n");
2180 /* Initialize the array that will be passed to add_set_enum_cmd(). */
2181 valid_flavors
= xmalloc ((num_flavor_options
+ 1) * sizeof (char *));
2182 for (i
= 0; i
< num_flavor_options
; i
++)
2184 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
2185 valid_flavors
[i
] = setname
;
2186 fprintf_unfiltered (stb
, "%s - %s\n", setname
,
2188 /* Copy the default names (if found) and synchronize disassembler. */
2189 if (!strcmp (setname
, "std"))
2191 disassembly_flavor
= setname
;
2193 for (j
= 0; j
< numregs
; j
++)
2194 arm_register_names
[j
] = (char *) regnames
[j
];
2195 set_arm_regname_option (i
);
2198 /* Mark the end of valid options. */
2199 valid_flavors
[num_flavor_options
] = NULL
;
2201 /* Finish the creation of the help text. */
2202 fprintf_unfiltered (stb
, "The default is \"std\".");
2203 helptext
= ui_file_xstrdup (stb
, &length
);
2204 ui_file_delete (stb
);
2206 /* Add the disassembly-flavor command */
2207 new_cmd
= add_set_enum_cmd ("disassembly-flavor", no_class
,
2209 &disassembly_flavor
,
2212 new_cmd
->function
.sfunc
= set_disassembly_flavor_sfunc
;
2213 add_show_from_set (new_cmd
, &showlist
);
2215 /* ??? Maybe this should be a boolean. */
2216 add_show_from_set (add_set_cmd ("apcs32", no_class
,
2217 var_zinteger
, (char *) &arm_apcs_32
,
2218 "Set usage of ARM 32-bit mode.\n", &setlist
),
2221 /* Add the deprecated "othernames" command */
2223 add_com ("othernames", class_obscure
, arm_othernames
,
2224 "Switch to the next set of register names.");
2227 /* Test whether the coff symbol specific value corresponds to a Thumb
2231 coff_sym_is_thumb (int val
)
2233 return (val
== C_THUMBEXT
||
2234 val
== C_THUMBSTAT
||
2235 val
== C_THUMBEXTFUNC
||
2236 val
== C_THUMBSTATFUNC
||
2237 val
== C_THUMBLABEL
);