1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper () */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
43 #include "target-descriptions.h"
44 #include "user-regs.h"
47 #include "gdb/sim-arm.h"
50 #include "coff/internal.h"
53 #include "gdb_assert.h"
58 /* Macros for setting and testing a bit in a minimal symbol that marks
59 it as Thumb function. The MSB of the minimal symbol's "info" field
60 is used for this purpose.
62 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
63 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
65 #define MSYMBOL_SET_SPECIAL(msym) \
66 MSYMBOL_TARGET_FLAG_1 (msym) = 1
68 #define MSYMBOL_IS_SPECIAL(msym) \
69 MSYMBOL_TARGET_FLAG_1 (msym)
71 /* Per-objfile data used for mapping symbols. */
72 static const struct objfile_data
*arm_objfile_data_key
;
74 struct arm_mapping_symbol
79 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
80 DEF_VEC_O(arm_mapping_symbol_s
);
82 struct arm_per_objfile
84 VEC(arm_mapping_symbol_s
) **section_maps
;
87 /* The list of available "set arm ..." and "show arm ..." commands. */
88 static struct cmd_list_element
*setarmcmdlist
= NULL
;
89 static struct cmd_list_element
*showarmcmdlist
= NULL
;
91 /* The type of floating-point to use. Keep this in sync with enum
92 arm_float_model, and the help string in _initialize_arm_tdep. */
93 static const char *fp_model_strings
[] =
103 /* A variable that can be configured by the user. */
104 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
105 static const char *current_fp_model
= "auto";
107 /* The ABI to use. Keep this in sync with arm_abi_kind. */
108 static const char *arm_abi_strings
[] =
116 /* A variable that can be configured by the user. */
117 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
118 static const char *arm_abi_string
= "auto";
120 /* The execution mode to assume. */
121 static const char *arm_mode_strings
[] =
128 static const char *arm_fallback_mode_string
= "auto";
129 static const char *arm_force_mode_string
= "auto";
131 /* Number of different reg name sets (options). */
132 static int num_disassembly_options
;
134 /* The standard register names, and all the valid aliases for them. */
139 } arm_register_aliases
[] = {
140 /* Basic register numbers. */
157 /* Synonyms (argument and variable registers). */
170 /* Other platform-specific names for r9. */
178 /* Names used by GCC (not listed in the ARM EABI). */
181 /* A special name from the older ATPCS. */
185 static const char *const arm_register_names
[] =
186 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
187 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
188 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
189 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
190 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
191 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
192 "fps", "cpsr" }; /* 24 25 */
194 /* Valid register name styles. */
195 static const char **valid_disassembly_styles
;
197 /* Disassembly style to use. Default to "std" register names. */
198 static const char *disassembly_style
;
200 /* This is used to keep the bfd arch_info in sync with the disassembly
202 static void set_disassembly_style_sfunc(char *, int,
203 struct cmd_list_element
*);
204 static void set_disassembly_style (void);
206 static void convert_from_extended (const struct floatformat
*, const void *,
208 static void convert_to_extended (const struct floatformat
*, void *,
211 static void arm_neon_quad_read (struct gdbarch
*gdbarch
,
212 struct regcache
*regcache
,
213 int regnum
, gdb_byte
*buf
);
214 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
215 struct regcache
*regcache
,
216 int regnum
, const gdb_byte
*buf
);
218 struct arm_prologue_cache
220 /* The stack pointer at the time this frame was created; i.e. the
221 caller's stack pointer when this function was called. It is used
222 to identify this frame. */
225 /* The frame base for this frame is just prev_sp - frame size.
226 FRAMESIZE is the distance from the frame pointer to the
227 initial stack pointer. */
231 /* The register used to hold the frame pointer for this frame. */
234 /* Saved register offsets. */
235 struct trad_frame_saved_reg
*saved_regs
;
238 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
239 CORE_ADDR prologue_start
,
240 CORE_ADDR prologue_end
,
241 struct arm_prologue_cache
*cache
);
243 /* Architecture version for displaced stepping. This effects the behaviour of
244 certain instructions, and really should not be hard-wired. */
246 #define DISPLACED_STEPPING_ARCH_VERSION 5
248 /* Addresses for calling Thumb functions have the bit 0 set.
249 Here are some macros to test, set, or clear bit 0 of addresses. */
250 #define IS_THUMB_ADDR(addr) ((addr) & 1)
251 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
252 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
254 /* Set to true if the 32-bit mode is in use. */
258 /* Determine if FRAME is executing in Thumb mode. */
261 arm_frame_is_thumb (struct frame_info
*frame
)
265 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
266 directly (from a signal frame or dummy frame) or by interpreting
267 the saved LR (from a prologue or DWARF frame). So consult it and
268 trust the unwinders. */
269 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
271 return (cpsr
& CPSR_T
) != 0;
274 /* Callback for VEC_lower_bound. */
277 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
278 const struct arm_mapping_symbol
*rhs
)
280 return lhs
->value
< rhs
->value
;
283 /* Search for the mapping symbol covering MEMADDR. If one is found,
284 return its type. Otherwise, return 0. If START is non-NULL,
285 set *START to the location of the mapping symbol. */
288 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
290 struct obj_section
*sec
;
292 /* If there are mapping symbols, consult them. */
293 sec
= find_pc_section (memaddr
);
296 struct arm_per_objfile
*data
;
297 VEC(arm_mapping_symbol_s
) *map
;
298 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
302 data
= objfile_data (sec
->objfile
, arm_objfile_data_key
);
305 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
306 if (!VEC_empty (arm_mapping_symbol_s
, map
))
308 struct arm_mapping_symbol
*map_sym
;
310 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
311 arm_compare_mapping_symbols
);
313 /* VEC_lower_bound finds the earliest ordered insertion
314 point. If the following symbol starts at this exact
315 address, we use that; otherwise, the preceding
316 mapping symbol covers this address. */
317 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
319 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
320 if (map_sym
->value
== map_key
.value
)
323 *start
= map_sym
->value
+ obj_section_addr (sec
);
324 return map_sym
->type
;
330 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
332 *start
= map_sym
->value
+ obj_section_addr (sec
);
333 return map_sym
->type
;
342 static CORE_ADDR
arm_get_next_pc_raw (struct frame_info
*frame
,
343 CORE_ADDR pc
, int insert_bkpt
);
345 /* Determine if the program counter specified in MEMADDR is in a Thumb
346 function. This function should be called for addresses unrelated to
347 any executing frame; otherwise, prefer arm_frame_is_thumb. */
350 arm_pc_is_thumb (CORE_ADDR memaddr
)
352 struct obj_section
*sec
;
353 struct minimal_symbol
*sym
;
356 /* If bit 0 of the address is set, assume this is a Thumb address. */
357 if (IS_THUMB_ADDR (memaddr
))
360 /* If the user wants to override the symbol table, let him. */
361 if (strcmp (arm_force_mode_string
, "arm") == 0)
363 if (strcmp (arm_force_mode_string
, "thumb") == 0)
366 /* If there are mapping symbols, consult them. */
367 type
= arm_find_mapping_symbol (memaddr
, NULL
);
371 /* Thumb functions have a "special" bit set in minimal symbols. */
372 sym
= lookup_minimal_symbol_by_pc (memaddr
);
374 return (MSYMBOL_IS_SPECIAL (sym
));
376 /* If the user wants to override the fallback mode, let them. */
377 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
379 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
382 /* If we couldn't find any symbol, but we're talking to a running
383 target, then trust the current value of $cpsr. This lets
384 "display/i $pc" always show the correct mode (though if there is
385 a symbol table we will not reach here, so it still may not be
386 displayed in the mode it will be executed).
388 As a further heuristic if we detect that we are doing a single-step we
389 see what state executing the current instruction ends up with us being
391 if (target_has_registers
)
393 struct frame_info
*current_frame
= get_current_frame ();
394 CORE_ADDR current_pc
= get_frame_pc (current_frame
);
395 int is_thumb
= arm_frame_is_thumb (current_frame
);
397 if (memaddr
== current_pc
)
401 struct gdbarch
*gdbarch
= get_frame_arch (current_frame
);
402 next_pc
= arm_get_next_pc_raw (current_frame
, current_pc
, FALSE
);
403 if (memaddr
== gdbarch_addr_bits_remove (gdbarch
, next_pc
))
404 return IS_THUMB_ADDR (next_pc
);
410 /* Otherwise we're out of luck; we assume ARM. */
414 /* Remove useless bits from addresses in a running program. */
416 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
419 return UNMAKE_THUMB_ADDR (val
);
421 return (val
& 0x03fffffc);
424 /* When reading symbols, we need to zap the low bit of the address,
425 which may be set to 1 for Thumb functions. */
427 arm_smash_text_address (struct gdbarch
*gdbarch
, CORE_ADDR val
)
432 /* Return 1 if PC is the start of a compiler helper function which
433 can be safely ignored during prologue skipping. */
435 skip_prologue_function (CORE_ADDR pc
)
437 struct minimal_symbol
*msym
;
440 msym
= lookup_minimal_symbol_by_pc (pc
);
441 if (msym
== NULL
|| SYMBOL_VALUE_ADDRESS (msym
) != pc
)
444 name
= SYMBOL_LINKAGE_NAME (msym
);
448 /* The GNU linker's Thumb call stub to foo is named
450 if (strstr (name
, "_from_thumb") != NULL
)
453 /* On soft-float targets, __truncdfsf2 is called to convert promoted
454 arguments to their argument types in non-prototyped
456 if (strncmp (name
, "__truncdfsf2", strlen ("__truncdfsf2")) == 0)
458 if (strncmp (name
, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
464 /* Support routines for instruction parsing. */
465 #define submask(x) ((1L << ((x) + 1)) - 1)
466 #define bit(obj,st) (((obj) >> (st)) & 1)
467 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
468 #define sbits(obj,st,fn) \
469 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
470 #define BranchDest(addr,instr) \
471 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
473 /* Analyze a Thumb prologue, looking for a recognizable stack frame
474 and frame pointer. Scan until we encounter a store that could
475 clobber the stack frame unexpectedly, or an unknown instruction.
476 Return the last address which is definitely safe to skip for an
477 initial breakpoint. */
480 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
481 CORE_ADDR start
, CORE_ADDR limit
,
482 struct arm_prologue_cache
*cache
)
484 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
485 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
488 struct pv_area
*stack
;
489 struct cleanup
*back_to
;
492 for (i
= 0; i
< 16; i
++)
493 regs
[i
] = pv_register (i
, 0);
494 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
495 back_to
= make_cleanup_free_pv_area (stack
);
497 while (start
< limit
)
501 insn
= read_memory_unsigned_integer (start
, 2, byte_order_for_code
);
503 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
508 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
511 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
512 whether to save LR (R14). */
513 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
515 /* Calculate offsets of saved R0-R7 and LR. */
516 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
517 if (mask
& (1 << regno
))
519 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
521 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
524 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
527 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
528 if (insn
& 0x80) /* Check for SUB. */
529 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
532 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
535 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
536 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
538 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
539 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
540 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
542 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
543 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
544 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
546 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
547 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
548 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
549 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
550 regs
[bits (insn
, 6, 8)]);
551 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
552 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
554 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
555 int rm
= bits (insn
, 3, 6);
556 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
558 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
560 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
561 int src_reg
= (insn
& 0x78) >> 3;
562 regs
[dst_reg
] = regs
[src_reg
];
564 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
566 /* Handle stores to the stack. Normally pushes are used,
567 but with GCC -mtpcs-frame, there may be other stores
568 in the prologue to create the frame. */
569 int regno
= (insn
>> 8) & 0x7;
572 offset
= (insn
& 0xff) << 2;
573 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
575 if (pv_area_store_would_trash (stack
, addr
))
578 pv_area_store (stack
, addr
, 4, regs
[regno
]);
580 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
582 int rd
= bits (insn
, 0, 2);
583 int rn
= bits (insn
, 3, 5);
586 offset
= bits (insn
, 6, 10) << 2;
587 addr
= pv_add_constant (regs
[rn
], offset
);
589 if (pv_area_store_would_trash (stack
, addr
))
592 pv_area_store (stack
, addr
, 4, regs
[rd
]);
594 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
595 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
596 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
597 /* Ignore stores of argument registers to the stack. */
599 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
600 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
601 /* Ignore block loads from the stack, potentially copying
602 parameters from memory. */
604 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
605 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
606 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
607 /* Similarly ignore single loads from the stack. */
609 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
610 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
611 /* Skip register copies, i.e. saves to another register
612 instead of the stack. */
614 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
615 /* Recognize constant loads; even with small stacks these are necessary
617 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
618 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
620 /* Constant pool loads, for the same reason. */
621 unsigned int constant
;
624 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
625 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
626 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
628 else if ((insn
& 0xe000) == 0xe000 && cache
== NULL
)
630 /* Only recognize 32-bit instructions for prologue skipping. */
631 unsigned short inst2
;
633 inst2
= read_memory_unsigned_integer (start
+ 2, 2,
634 byte_order_for_code
);
636 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
638 /* BL, BLX. Allow some special function calls when
639 skipping the prologue; GCC generates these before
640 storing arguments to the stack. */
642 int j1
, j2
, imm1
, imm2
;
644 imm1
= sbits (insn
, 0, 10);
645 imm2
= bits (inst2
, 0, 10);
646 j1
= bit (inst2
, 13);
647 j2
= bit (inst2
, 11);
649 offset
= ((imm1
<< 12) + (imm2
<< 1));
650 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
652 nextpc
= start
+ 4 + offset
;
653 /* For BLX make sure to clear the low bits. */
654 if (bit (inst2
, 12) == 0)
655 nextpc
= nextpc
& 0xfffffffc;
657 if (!skip_prologue_function (nextpc
))
660 else if ((insn
& 0xfe50) == 0xe800 /* stm{db,ia} Rn[!], { registers } */
661 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
663 else if ((insn
& 0xfe50) == 0xe840 /* strd Rt, Rt2, [Rn, #imm] */
664 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
666 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!], { registers } */
667 && (inst2
& 0x8000) == 0x0000
668 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
670 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
671 && (inst2
& 0x8000) == 0x0000)
672 /* Since we only recognize this for prologue skipping, do not bother
673 to compute the constant. */
674 regs
[bits (inst2
, 8, 11)] = regs
[bits (insn
, 0, 3)];
675 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm12 */
676 && (inst2
& 0x8000) == 0x0000)
677 /* Since we only recognize this for prologue skipping, do not bother
678 to compute the constant. */
679 regs
[bits (inst2
, 8, 11)] = regs
[bits (insn
, 0, 3)];
680 else if ((insn
& 0xfbf0) == 0xf2a0 /* sub.w Rd, Rn, #imm8 */
681 && (inst2
& 0x8000) == 0x0000)
682 /* Since we only recognize this for prologue skipping, do not bother
683 to compute the constant. */
684 regs
[bits (inst2
, 8, 11)] = regs
[bits (insn
, 0, 3)];
685 else if ((insn
& 0xff50) == 0xf850 /* ldr.w Rd, [Rn, #imm]{!} */
686 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
688 else if ((insn
& 0xff50) == 0xe950 /* ldrd Rt, Rt2, [Rn, #imm]{!} */
689 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
691 else if ((insn
& 0xff50) == 0xf800 /* strb.w or strh.w */
692 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
696 /* We don't know what this instruction is. We're finished
697 scanning. NOTE: Recognizing more safe-to-ignore
698 instructions here will improve support for optimized
707 /* We don't know what this instruction is. We're finished
708 scanning. NOTE: Recognizing more safe-to-ignore
709 instructions here will improve support for optimized
718 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
719 paddress (gdbarch
, start
));
723 do_cleanups (back_to
);
727 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
729 /* Frame pointer is fp. Frame size is constant. */
730 cache
->framereg
= ARM_FP_REGNUM
;
731 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
733 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
735 /* Frame pointer is r7. Frame size is constant. */
736 cache
->framereg
= THUMB_FP_REGNUM
;
737 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
739 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
741 /* Try the stack pointer... this is a bit desperate. */
742 cache
->framereg
= ARM_SP_REGNUM
;
743 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
747 /* We're just out of luck. We don't know where the frame is. */
748 cache
->framereg
= -1;
749 cache
->framesize
= 0;
752 for (i
= 0; i
< 16; i
++)
753 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
754 cache
->saved_regs
[i
].addr
= offset
;
756 do_cleanups (back_to
);
760 /* Advance the PC across any function entry prologue instructions to
761 reach some "real" code.
763 The APCS (ARM Procedure Call Standard) defines the following
767 [stmfd sp!, {a1,a2,a3,a4}]
768 stmfd sp!, {...,fp,ip,lr,pc}
769 [stfe f7, [sp, #-12]!]
770 [stfe f6, [sp, #-12]!]
771 [stfe f5, [sp, #-12]!]
772 [stfe f4, [sp, #-12]!]
773 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
776 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
778 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
781 CORE_ADDR func_addr
, limit_pc
;
782 struct symtab_and_line sal
;
784 /* See if we can determine the end of the prologue via the symbol table.
785 If so, then return either PC, or the PC after the prologue, whichever
787 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
789 CORE_ADDR post_prologue_pc
790 = skip_prologue_using_sal (gdbarch
, func_addr
);
791 struct symtab
*s
= find_pc_symtab (func_addr
);
793 /* GCC always emits a line note before the prologue and another
794 one after, even if the two are at the same address or on the
795 same line. Take advantage of this so that we do not need to
796 know every instruction that might appear in the prologue. We
797 will have producer information for most binaries; if it is
798 missing (e.g. for -gstabs), assuming the GNU tools. */
801 || s
->producer
== NULL
802 || strncmp (s
->producer
, "GNU ", sizeof ("GNU ") - 1) == 0))
803 return post_prologue_pc
;
805 if (post_prologue_pc
!= 0)
807 CORE_ADDR analyzed_limit
;
809 /* For non-GCC compilers, make sure the entire line is an
810 acceptable prologue; GDB will round this function's
811 return value up to the end of the following line so we
812 can not skip just part of a line (and we do not want to).
814 RealView does not treat the prologue specially, but does
815 associate prologue code with the opening brace; so this
816 lets us skip the first line if we think it is the opening
818 if (arm_pc_is_thumb (func_addr
))
819 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
820 post_prologue_pc
, NULL
);
822 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
823 post_prologue_pc
, NULL
);
825 if (analyzed_limit
!= post_prologue_pc
)
828 return post_prologue_pc
;
832 /* Can't determine prologue from the symbol table, need to examine
835 /* Find an upper limit on the function prologue using the debug
836 information. If the debug information could not be used to provide
837 that bound, then use an arbitrary large number as the upper bound. */
838 /* Like arm_scan_prologue, stop no later than pc + 64. */
839 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
841 limit_pc
= pc
+ 64; /* Magic. */
844 /* Check if this is Thumb code. */
845 if (arm_pc_is_thumb (pc
))
846 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
848 for (skip_pc
= pc
; skip_pc
< limit_pc
; skip_pc
+= 4)
850 inst
= read_memory_unsigned_integer (skip_pc
, 4, byte_order_for_code
);
852 /* "mov ip, sp" is no longer a required part of the prologue. */
853 if (inst
== 0xe1a0c00d) /* mov ip, sp */
856 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
859 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
862 /* Some prologues begin with "str lr, [sp, #-4]!". */
863 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
866 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
869 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
872 /* Any insns after this point may float into the code, if it makes
873 for better instruction scheduling, so we skip them only if we
874 find them, but still consider the function to be frame-ful. */
876 /* We may have either one sfmfd instruction here, or several stfe
877 insns, depending on the version of floating point code we
879 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
882 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
885 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
888 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
891 if ((inst
& 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */
892 || (inst
& 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */
893 || (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
896 if ((inst
& 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */
897 || (inst
& 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */
898 || (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
901 /* Un-recognized instruction; stop scanning. */
905 return skip_pc
; /* End of prologue */
909 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
910 This function decodes a Thumb function prologue to determine:
911 1) the size of the stack frame
912 2) which registers are saved on it
913 3) the offsets of saved regs
914 4) the offset from the stack pointer to the frame pointer
916 A typical Thumb function prologue would create this stack frame
917 (offsets relative to FP)
918 old SP -> 24 stack parameters
921 R7 -> 0 local variables (16 bytes)
922 SP -> -12 additional stack space (12 bytes)
923 The frame size would thus be 36 bytes, and the frame offset would be
924 12 bytes. The frame register is R7.
926 The comments for thumb_skip_prolog() describe the algorithm we use
927 to detect the end of the prolog. */
931 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
932 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
934 CORE_ADDR prologue_start
;
935 CORE_ADDR prologue_end
;
936 CORE_ADDR current_pc
;
938 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
941 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
943 if (sal
.line
== 0) /* no line info, use current PC */
944 prologue_end
= prev_pc
;
945 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
946 prologue_end
= sal
.end
; /* (probably means no prologue) */
949 /* We're in the boondocks: we have no idea where the start of the
953 prologue_end
= min (prologue_end
, prev_pc
);
955 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
958 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
961 arm_instruction_changes_pc (uint32_t this_instr
)
963 if (bits (this_instr
, 28, 31) == INST_NV
)
964 /* Unconditional instructions. */
965 switch (bits (this_instr
, 24, 27))
969 /* Branch with Link and change to Thumb. */
974 /* Coprocessor register transfer. */
975 if (bits (this_instr
, 12, 15) == 15)
976 error (_("Invalid update to pc in instruction"));
982 switch (bits (this_instr
, 25, 27))
985 if (bits (this_instr
, 23, 24) == 2 && bit (this_instr
, 20) == 0)
987 /* Multiplies and extra load/stores. */
988 if (bit (this_instr
, 4) == 1 && bit (this_instr
, 7) == 1)
989 /* Neither multiplies nor extension load/stores are allowed
993 /* Otherwise, miscellaneous instructions. */
995 /* BX <reg>, BXJ <reg>, BLX <reg> */
996 if (bits (this_instr
, 4, 27) == 0x12fff1
997 || bits (this_instr
, 4, 27) == 0x12fff2
998 || bits (this_instr
, 4, 27) == 0x12fff3)
1001 /* Other miscellaneous instructions are unpredictable if they
1005 /* Data processing instruction. Fall through. */
1008 if (bits (this_instr
, 12, 15) == 15)
1015 /* Media instructions and architecturally undefined instructions. */
1016 if (bits (this_instr
, 25, 27) == 3 && bit (this_instr
, 4) == 1)
1020 if (bit (this_instr
, 20) == 0)
1024 if (bits (this_instr
, 12, 15) == ARM_PC_REGNUM
)
1030 /* Load/store multiple. */
1031 if (bit (this_instr
, 20) == 1 && bit (this_instr
, 15) == 1)
1037 /* Branch and branch with link. */
1042 /* Coprocessor transfers or SWIs can not affect PC. */
1046 internal_error (__FILE__
, __LINE__
, "bad value in switch");
1050 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1051 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1052 fill it in. Return the first address not recognized as a prologue
1055 We recognize all the instructions typically found in ARM prologues,
1056 plus harmless instructions which can be skipped (either for analysis
1057 purposes, or a more restrictive set that can be skipped when finding
1058 the end of the prologue). */
1061 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1062 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1063 struct arm_prologue_cache
*cache
)
1065 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1066 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1068 CORE_ADDR offset
, current_pc
;
1069 pv_t regs
[ARM_FPS_REGNUM
];
1070 struct pv_area
*stack
;
1071 struct cleanup
*back_to
;
1072 int framereg
, framesize
;
1073 CORE_ADDR unrecognized_pc
= 0;
1075 /* Search the prologue looking for instructions that set up the
1076 frame pointer, adjust the stack pointer, and save registers.
1078 Be careful, however, and if it doesn't look like a prologue,
1079 don't try to scan it. If, for instance, a frameless function
1080 begins with stmfd sp!, then we will tell ourselves there is
1081 a frame, which will confuse stack traceback, as well as "finish"
1082 and other operations that rely on a knowledge of the stack
1085 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1086 regs
[regno
] = pv_register (regno
, 0);
1087 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1088 back_to
= make_cleanup_free_pv_area (stack
);
1090 for (current_pc
= prologue_start
;
1091 current_pc
< prologue_end
;
1095 = read_memory_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1097 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1099 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1102 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1103 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1105 unsigned imm
= insn
& 0xff; /* immediate value */
1106 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1107 int rd
= bits (insn
, 12, 15);
1108 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1109 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1112 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1113 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1115 unsigned imm
= insn
& 0xff; /* immediate value */
1116 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1117 int rd
= bits (insn
, 12, 15);
1118 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1119 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1122 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd, [sp, #-4]! */
1124 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1126 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1127 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4,
1128 regs
[bits (insn
, 12, 15)]);
1131 else if ((insn
& 0xffff0000) == 0xe92d0000)
1132 /* stmfd sp!, {..., fp, ip, lr, pc}
1134 stmfd sp!, {a1, a2, a3, a4} */
1136 int mask
= insn
& 0xffff;
1138 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1141 /* Calculate offsets of saved registers. */
1142 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1143 if (mask
& (1 << regno
))
1145 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1146 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1149 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1150 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1151 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1153 /* No need to add this to saved_regs -- it's just an arg reg. */
1156 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1157 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1158 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1160 /* No need to add this to saved_regs -- it's just an arg reg. */
1163 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn, { registers } */
1164 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1166 /* No need to add this to saved_regs -- it's just arg regs. */
1169 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1171 unsigned imm
= insn
& 0xff; /* immediate value */
1172 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1173 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1174 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1176 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1178 unsigned imm
= insn
& 0xff; /* immediate value */
1179 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1180 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1181 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1183 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
1184 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1186 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1189 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1190 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1191 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1193 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
1194 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1196 int n_saved_fp_regs
;
1197 unsigned int fp_start_reg
, fp_bound_reg
;
1199 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1202 if ((insn
& 0x800) == 0x800) /* N0 is set */
1204 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1205 n_saved_fp_regs
= 3;
1207 n_saved_fp_regs
= 1;
1211 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1212 n_saved_fp_regs
= 2;
1214 n_saved_fp_regs
= 4;
1217 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1218 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1219 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1221 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1222 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
1223 regs
[fp_start_reg
++]);
1226 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1228 /* Allow some special function calls when skipping the
1229 prologue; GCC generates these before storing arguments to
1231 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1233 if (skip_prologue_function (dest
))
1238 else if ((insn
& 0xf0000000) != 0xe0000000)
1239 break; /* Condition not true, exit early */
1240 else if (arm_instruction_changes_pc (insn
))
1241 /* Don't scan past anything that might change control flow. */
1243 else if ((insn
& 0xfe500000) == 0xe8100000) /* ldm */
1245 /* Ignore block loads from the stack, potentially copying
1246 parameters from memory. */
1247 if (pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1252 else if ((insn
& 0xfc500000) == 0xe4100000)
1254 /* Similarly ignore single loads from the stack. */
1255 if (pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1260 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1261 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1262 register instead of the stack. */
1266 /* The optimizer might shove anything into the prologue,
1267 so we just skip what we don't recognize. */
1268 unrecognized_pc
= current_pc
;
1273 if (unrecognized_pc
== 0)
1274 unrecognized_pc
= current_pc
;
1276 /* The frame size is just the distance from the frame register
1277 to the original stack pointer. */
1278 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1280 /* Frame pointer is fp. */
1281 framereg
= ARM_FP_REGNUM
;
1282 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1284 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
1286 /* Try the stack pointer... this is a bit desperate. */
1287 framereg
= ARM_SP_REGNUM
;
1288 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1292 /* We're just out of luck. We don't know where the frame is. */
1299 cache
->framereg
= framereg
;
1300 cache
->framesize
= framesize
;
1302 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1303 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1304 cache
->saved_regs
[regno
].addr
= offset
;
1308 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1309 paddress (gdbarch
, unrecognized_pc
));
1311 do_cleanups (back_to
);
1312 return unrecognized_pc
;
1316 arm_scan_prologue (struct frame_info
*this_frame
,
1317 struct arm_prologue_cache
*cache
)
1319 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1320 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1322 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
1323 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1324 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1325 pv_t regs
[ARM_FPS_REGNUM
];
1326 struct pv_area
*stack
;
1327 struct cleanup
*back_to
;
1330 /* Assume there is no frame until proven otherwise. */
1331 cache
->framereg
= ARM_SP_REGNUM
;
1332 cache
->framesize
= 0;
1334 /* Check for Thumb prologue. */
1335 if (arm_frame_is_thumb (this_frame
))
1337 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1341 /* Find the function prologue. If we can't find the function in
1342 the symbol table, peek in the stack frame to find the PC. */
1343 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1346 /* One way to find the end of the prologue (which works well
1347 for unoptimized code) is to do the following:
1349 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1352 prologue_end = prev_pc;
1353 else if (sal.end < prologue_end)
1354 prologue_end = sal.end;
1356 This mechanism is very accurate so long as the optimizer
1357 doesn't move any instructions from the function body into the
1358 prologue. If this happens, sal.end will be the last
1359 instruction in the first hunk of prologue code just before
1360 the first instruction that the scheduler has moved from
1361 the body to the prologue.
1363 In order to make sure that we scan all of the prologue
1364 instructions, we use a slightly less accurate mechanism which
1365 may scan more than necessary. To help compensate for this
1366 lack of accuracy, the prologue scanning loop below contains
1367 several clauses which'll cause the loop to terminate early if
1368 an implausible prologue instruction is encountered.
1374 is a suitable endpoint since it accounts for the largest
1375 possible prologue plus up to five instructions inserted by
1378 if (prologue_end
> prologue_start
+ 64)
1380 prologue_end
= prologue_start
+ 64; /* See above. */
1385 /* We have no symbol information. Our only option is to assume this
1386 function has a standard stack frame and the normal frame register.
1387 Then, we can find the value of our frame pointer on entrance to
1388 the callee (or at the present moment if this is the innermost frame).
1389 The value stored there should be the address of the stmfd + 8. */
1390 CORE_ADDR frame_loc
;
1391 LONGEST return_value
;
1393 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
1394 if (!safe_read_memory_integer (frame_loc
, 4, byte_order
, &return_value
))
1398 prologue_start
= gdbarch_addr_bits_remove
1399 (gdbarch
, return_value
) - 8;
1400 prologue_end
= prologue_start
+ 64; /* See above. */
1404 if (prev_pc
< prologue_end
)
1405 prologue_end
= prev_pc
;
1407 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1410 static struct arm_prologue_cache
*
1411 arm_make_prologue_cache (struct frame_info
*this_frame
)
1414 struct arm_prologue_cache
*cache
;
1415 CORE_ADDR unwound_fp
;
1417 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1418 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1420 arm_scan_prologue (this_frame
, cache
);
1422 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
1423 if (unwound_fp
== 0)
1426 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
1428 /* Calculate actual addresses of saved registers using offsets
1429 determined by arm_scan_prologue. */
1430 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
1431 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
1432 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
1437 /* Our frame ID for a normal frame is the current function's starting PC
1438 and the caller's SP when we were called. */
1441 arm_prologue_this_id (struct frame_info
*this_frame
,
1443 struct frame_id
*this_id
)
1445 struct arm_prologue_cache
*cache
;
1449 if (*this_cache
== NULL
)
1450 *this_cache
= arm_make_prologue_cache (this_frame
);
1451 cache
= *this_cache
;
1453 /* This is meant to halt the backtrace at "_start". */
1454 pc
= get_frame_pc (this_frame
);
1455 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1458 /* If we've hit a wall, stop. */
1459 if (cache
->prev_sp
== 0)
1462 func
= get_frame_func (this_frame
);
1463 id
= frame_id_build (cache
->prev_sp
, func
);
1467 static struct value
*
1468 arm_prologue_prev_register (struct frame_info
*this_frame
,
1472 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1473 struct arm_prologue_cache
*cache
;
1475 if (*this_cache
== NULL
)
1476 *this_cache
= arm_make_prologue_cache (this_frame
);
1477 cache
= *this_cache
;
1479 /* If we are asked to unwind the PC, then we need to return the LR
1480 instead. The prologue may save PC, but it will point into this
1481 frame's prologue, not the next frame's resume location. Also
1482 strip the saved T bit. A valid LR may have the low bit set, but
1483 a valid PC never does. */
1484 if (prev_regnum
== ARM_PC_REGNUM
)
1488 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1489 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1490 arm_addr_bits_remove (gdbarch
, lr
));
1493 /* SP is generally not saved to the stack, but this frame is
1494 identified by the next frame's stack pointer at the time of the call.
1495 The value was already reconstructed into PREV_SP. */
1496 if (prev_regnum
== ARM_SP_REGNUM
)
1497 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1499 /* The CPSR may have been changed by the call instruction and by the
1500 called function. The only bit we can reconstruct is the T bit,
1501 by checking the low bit of LR as of the call. This is a reliable
1502 indicator of Thumb-ness except for some ARM v4T pre-interworking
1503 Thumb code, which could get away with a clear low bit as long as
1504 the called function did not use bx. Guess that all other
1505 bits are unchanged; the condition flags are presumably lost,
1506 but the processor status is likely valid. */
1507 if (prev_regnum
== ARM_PS_REGNUM
)
1511 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1512 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1513 if (IS_THUMB_ADDR (lr
))
1517 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1520 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1524 struct frame_unwind arm_prologue_unwind
= {
1526 arm_prologue_this_id
,
1527 arm_prologue_prev_register
,
1529 default_frame_sniffer
1532 static struct arm_prologue_cache
*
1533 arm_make_stub_cache (struct frame_info
*this_frame
)
1535 struct arm_prologue_cache
*cache
;
1537 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1538 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1540 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1545 /* Our frame ID for a stub frame is the current SP and LR. */
1548 arm_stub_this_id (struct frame_info
*this_frame
,
1550 struct frame_id
*this_id
)
1552 struct arm_prologue_cache
*cache
;
1554 if (*this_cache
== NULL
)
1555 *this_cache
= arm_make_stub_cache (this_frame
);
1556 cache
= *this_cache
;
1558 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
1562 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
1563 struct frame_info
*this_frame
,
1564 void **this_prologue_cache
)
1566 CORE_ADDR addr_in_block
;
1569 addr_in_block
= get_frame_address_in_block (this_frame
);
1570 if (in_plt_section (addr_in_block
, NULL
)
1571 /* We also use the stub winder if the target memory is unreadable
1572 to avoid having the prologue unwinder trying to read it. */
1573 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
1579 struct frame_unwind arm_stub_unwind
= {
1582 arm_prologue_prev_register
,
1584 arm_stub_unwind_sniffer
1588 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
1590 struct arm_prologue_cache
*cache
;
1592 if (*this_cache
== NULL
)
1593 *this_cache
= arm_make_prologue_cache (this_frame
);
1594 cache
= *this_cache
;
1596 return cache
->prev_sp
- cache
->framesize
;
1599 struct frame_base arm_normal_base
= {
1600 &arm_prologue_unwind
,
1601 arm_normal_frame_base
,
1602 arm_normal_frame_base
,
1603 arm_normal_frame_base
1606 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1607 dummy frame. The frame ID's base needs to match the TOS value
1608 saved by save_dummy_frame_tos() and returned from
1609 arm_push_dummy_call, and the PC needs to match the dummy frame's
1612 static struct frame_id
1613 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1615 return frame_id_build (get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
),
1616 get_frame_pc (this_frame
));
1619 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1620 be used to construct the previous frame's ID, after looking up the
1621 containing function). */
1624 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1627 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1628 return arm_addr_bits_remove (gdbarch
, pc
);
1632 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1634 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1637 static struct value
*
1638 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1641 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
1647 /* The PC is normally copied from the return column, which
1648 describes saves of LR. However, that version may have an
1649 extra bit set to indicate Thumb state. The bit is not
1651 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1652 return frame_unwind_got_constant (this_frame
, regnum
,
1653 arm_addr_bits_remove (gdbarch
, lr
));
1656 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
1657 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
1658 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1659 if (IS_THUMB_ADDR (lr
))
1663 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
1666 internal_error (__FILE__
, __LINE__
,
1667 _("Unexpected register %d"), regnum
);
1672 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1673 struct dwarf2_frame_state_reg
*reg
,
1674 struct frame_info
*this_frame
)
1680 reg
->how
= DWARF2_FRAME_REG_FN
;
1681 reg
->loc
.fn
= arm_dwarf2_prev_register
;
1684 reg
->how
= DWARF2_FRAME_REG_CFA
;
1689 /* When arguments must be pushed onto the stack, they go on in reverse
1690 order. The code below implements a FILO (stack) to do this. */
1695 struct stack_item
*prev
;
1699 static struct stack_item
*
1700 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1702 struct stack_item
*si
;
1703 si
= xmalloc (sizeof (struct stack_item
));
1704 si
->data
= xmalloc (len
);
1707 memcpy (si
->data
, contents
, len
);
1711 static struct stack_item
*
1712 pop_stack_item (struct stack_item
*si
)
1714 struct stack_item
*dead
= si
;
1722 /* Return the alignment (in bytes) of the given type. */
1725 arm_type_align (struct type
*t
)
1731 t
= check_typedef (t
);
1732 switch (TYPE_CODE (t
))
1735 /* Should never happen. */
1736 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1740 case TYPE_CODE_ENUM
:
1744 case TYPE_CODE_RANGE
:
1745 case TYPE_CODE_BITSTRING
:
1747 case TYPE_CODE_CHAR
:
1748 case TYPE_CODE_BOOL
:
1749 return TYPE_LENGTH (t
);
1751 case TYPE_CODE_ARRAY
:
1752 case TYPE_CODE_COMPLEX
:
1753 /* TODO: What about vector types? */
1754 return arm_type_align (TYPE_TARGET_TYPE (t
));
1756 case TYPE_CODE_STRUCT
:
1757 case TYPE_CODE_UNION
:
1759 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1761 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
1769 /* Possible base types for a candidate for passing and returning in
1772 enum arm_vfp_cprc_base_type
1781 /* The length of one element of base type B. */
1784 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
1788 case VFP_CPRC_SINGLE
:
1790 case VFP_CPRC_DOUBLE
:
1792 case VFP_CPRC_VEC64
:
1794 case VFP_CPRC_VEC128
:
1797 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
1802 /* The character ('s', 'd' or 'q') for the type of VFP register used
1803 for passing base type B. */
1806 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
1810 case VFP_CPRC_SINGLE
:
1812 case VFP_CPRC_DOUBLE
:
1814 case VFP_CPRC_VEC64
:
1816 case VFP_CPRC_VEC128
:
1819 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
1824 /* Determine whether T may be part of a candidate for passing and
1825 returning in VFP registers, ignoring the limit on the total number
1826 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
1827 classification of the first valid component found; if it is not
1828 VFP_CPRC_UNKNOWN, all components must have the same classification
1829 as *BASE_TYPE. If it is found that T contains a type not permitted
1830 for passing and returning in VFP registers, a type differently
1831 classified from *BASE_TYPE, or two types differently classified
1832 from each other, return -1, otherwise return the total number of
1833 base-type elements found (possibly 0 in an empty structure or
1834 array). Vectors and complex types are not currently supported,
1835 matching the generic AAPCS support. */
1838 arm_vfp_cprc_sub_candidate (struct type
*t
,
1839 enum arm_vfp_cprc_base_type
*base_type
)
1841 t
= check_typedef (t
);
1842 switch (TYPE_CODE (t
))
1845 switch (TYPE_LENGTH (t
))
1848 if (*base_type
== VFP_CPRC_UNKNOWN
)
1849 *base_type
= VFP_CPRC_SINGLE
;
1850 else if (*base_type
!= VFP_CPRC_SINGLE
)
1855 if (*base_type
== VFP_CPRC_UNKNOWN
)
1856 *base_type
= VFP_CPRC_DOUBLE
;
1857 else if (*base_type
!= VFP_CPRC_DOUBLE
)
1866 case TYPE_CODE_ARRAY
:
1870 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
), base_type
);
1873 if (TYPE_LENGTH (t
) == 0)
1875 gdb_assert (count
== 0);
1878 else if (count
== 0)
1880 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
1881 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
1882 return TYPE_LENGTH (t
) / unitlen
;
1886 case TYPE_CODE_STRUCT
:
1891 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
1893 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
1895 if (sub_count
== -1)
1899 if (TYPE_LENGTH (t
) == 0)
1901 gdb_assert (count
== 0);
1904 else if (count
== 0)
1906 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
1907 if (TYPE_LENGTH (t
) != unitlen
* count
)
1912 case TYPE_CODE_UNION
:
1917 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
1919 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
1921 if (sub_count
== -1)
1923 count
= (count
> sub_count
? count
: sub_count
);
1925 if (TYPE_LENGTH (t
) == 0)
1927 gdb_assert (count
== 0);
1930 else if (count
== 0)
1932 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
1933 if (TYPE_LENGTH (t
) != unitlen
* count
)
1945 /* Determine whether T is a VFP co-processor register candidate (CPRC)
1946 if passed to or returned from a non-variadic function with the VFP
1947 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
1948 *BASE_TYPE to the base type for T and *COUNT to the number of
1949 elements of that base type before returning. */
1952 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
1955 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
1956 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
1957 if (c
<= 0 || c
> 4)
1964 /* Return 1 if the VFP ABI should be used for passing arguments to and
1965 returning values from a function of type FUNC_TYPE, 0
1969 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
1971 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1972 /* Variadic functions always use the base ABI. Assume that functions
1973 without debug info are not variadic. */
1974 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
1976 /* The VFP ABI is only supported as a variant of AAPCS. */
1977 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
1979 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
1982 /* We currently only support passing parameters in integer registers, which
1983 conforms with GCC's default model, and VFP argument passing following
1984 the VFP variant of AAPCS. Several other variants exist and
1985 we should probably support some of them based on the selected ABI. */
1988 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1989 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1990 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1991 CORE_ADDR struct_addr
)
1993 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1997 struct stack_item
*si
= NULL
;
2000 unsigned vfp_regs_free
= (1 << 16) - 1;
2002 /* Determine the type of this function and whether the VFP ABI
2004 ftype
= check_typedef (value_type (function
));
2005 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
2006 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
2007 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
2009 /* Set the return address. For the ARM, the return breakpoint is
2010 always at BP_ADDR. */
2011 if (arm_pc_is_thumb (bp_addr
))
2013 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
2015 /* Walk through the list of args and determine how large a temporary
2016 stack is required. Need to take care here as structs may be
2017 passed on the stack, and we have to to push them. */
2020 argreg
= ARM_A1_REGNUM
;
2023 /* The struct_return pointer occupies the first parameter
2024 passing register. */
2028 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
2029 gdbarch_register_name (gdbarch
, argreg
),
2030 paddress (gdbarch
, struct_addr
));
2031 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
2035 for (argnum
= 0; argnum
< nargs
; argnum
++)
2038 struct type
*arg_type
;
2039 struct type
*target_type
;
2040 enum type_code typecode
;
2043 enum arm_vfp_cprc_base_type vfp_base_type
;
2045 int may_use_core_reg
= 1;
2047 arg_type
= check_typedef (value_type (args
[argnum
]));
2048 len
= TYPE_LENGTH (arg_type
);
2049 target_type
= TYPE_TARGET_TYPE (arg_type
);
2050 typecode
= TYPE_CODE (arg_type
);
2051 val
= value_contents_writeable (args
[argnum
]);
2053 align
= arm_type_align (arg_type
);
2054 /* Round alignment up to a whole number of words. */
2055 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
2056 /* Different ABIs have different maximum alignments. */
2057 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
2059 /* The APCS ABI only requires word alignment. */
2060 align
= INT_REGISTER_SIZE
;
2064 /* The AAPCS requires at most doubleword alignment. */
2065 if (align
> INT_REGISTER_SIZE
* 2)
2066 align
= INT_REGISTER_SIZE
* 2;
2070 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
2078 /* Because this is a CPRC it cannot go in a core register or
2079 cause a core register to be skipped for alignment.
2080 Either it goes in VFP registers and the rest of this loop
2081 iteration is skipped for this argument, or it goes on the
2082 stack (and the stack alignment code is correct for this
2084 may_use_core_reg
= 0;
2086 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
2087 shift
= unit_length
/ 4;
2088 mask
= (1 << (shift
* vfp_base_count
)) - 1;
2089 for (regno
= 0; regno
< 16; regno
+= shift
)
2090 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
2099 vfp_regs_free
&= ~(mask
<< regno
);
2100 reg_scaled
= regno
/ shift
;
2101 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
2102 for (i
= 0; i
< vfp_base_count
; i
++)
2106 if (reg_char
== 'q')
2107 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
2108 val
+ i
* unit_length
);
2111 sprintf (name_buf
, "%c%d", reg_char
, reg_scaled
+ i
);
2112 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
2114 regcache_cooked_write (regcache
, regnum
,
2115 val
+ i
* unit_length
);
2122 /* This CPRC could not go in VFP registers, so all VFP
2123 registers are now marked as used. */
2128 /* Push stack padding for dowubleword alignment. */
2129 if (nstack
& (align
- 1))
2131 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
2132 nstack
+= INT_REGISTER_SIZE
;
2135 /* Doubleword aligned quantities must go in even register pairs. */
2136 if (may_use_core_reg
2137 && argreg
<= ARM_LAST_ARG_REGNUM
2138 && align
> INT_REGISTER_SIZE
2142 /* If the argument is a pointer to a function, and it is a
2143 Thumb function, create a LOCAL copy of the value and set
2144 the THUMB bit in it. */
2145 if (TYPE_CODE_PTR
== typecode
2146 && target_type
!= NULL
2147 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
2149 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
2150 if (arm_pc_is_thumb (regval
))
2153 store_unsigned_integer (val
, len
, byte_order
,
2154 MAKE_THUMB_ADDR (regval
));
2158 /* Copy the argument to general registers or the stack in
2159 register-sized pieces. Large arguments are split between
2160 registers and stack. */
2163 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
2165 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
2167 /* The argument is being passed in a general purpose
2170 = extract_unsigned_integer (val
, partial_len
, byte_order
);
2171 if (byte_order
== BFD_ENDIAN_BIG
)
2172 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
2174 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
2176 gdbarch_register_name
2178 phex (regval
, INT_REGISTER_SIZE
));
2179 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2184 /* Push the arguments onto the stack. */
2186 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
2188 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
2189 nstack
+= INT_REGISTER_SIZE
;
2196 /* If we have an odd number of words to push, then decrement the stack
2197 by one word now, so first stack argument will be dword aligned. */
2204 write_memory (sp
, si
->data
, si
->len
);
2205 si
= pop_stack_item (si
);
2208 /* Finally, update teh SP register. */
2209 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
2215 /* Always align the frame to an 8-byte boundary. This is required on
2216 some platforms and harmless on the rest. */
2219 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2221 /* Align the stack to eight bytes. */
2222 return sp
& ~ (CORE_ADDR
) 7;
2226 print_fpu_flags (int flags
)
2228 if (flags
& (1 << 0))
2229 fputs ("IVO ", stdout
);
2230 if (flags
& (1 << 1))
2231 fputs ("DVZ ", stdout
);
2232 if (flags
& (1 << 2))
2233 fputs ("OFL ", stdout
);
2234 if (flags
& (1 << 3))
2235 fputs ("UFL ", stdout
);
2236 if (flags
& (1 << 4))
2237 fputs ("INX ", stdout
);
2241 /* Print interesting information about the floating point processor
2242 (if present) or emulator. */
2244 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2245 struct frame_info
*frame
, const char *args
)
2247 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
2250 type
= (status
>> 24) & 127;
2251 if (status
& (1 << 31))
2252 printf (_("Hardware FPU type %d\n"), type
);
2254 printf (_("Software FPU type %d\n"), type
);
2255 /* i18n: [floating point unit] mask */
2256 fputs (_("mask: "), stdout
);
2257 print_fpu_flags (status
>> 16);
2258 /* i18n: [floating point unit] flags */
2259 fputs (_("flags: "), stdout
);
2260 print_fpu_flags (status
);
2263 /* Construct the ARM extended floating point type. */
2264 static struct type
*
2265 arm_ext_type (struct gdbarch
*gdbarch
)
2267 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2269 if (!tdep
->arm_ext_type
)
2271 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
2272 floatformats_arm_ext
);
2274 return tdep
->arm_ext_type
;
2277 static struct type
*
2278 arm_neon_double_type (struct gdbarch
*gdbarch
)
2280 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2282 if (tdep
->neon_double_type
== NULL
)
2284 struct type
*t
, *elem
;
2286 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
2288 elem
= builtin_type (gdbarch
)->builtin_uint8
;
2289 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
2290 elem
= builtin_type (gdbarch
)->builtin_uint16
;
2291 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
2292 elem
= builtin_type (gdbarch
)->builtin_uint32
;
2293 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
2294 elem
= builtin_type (gdbarch
)->builtin_uint64
;
2295 append_composite_type_field (t
, "u64", elem
);
2296 elem
= builtin_type (gdbarch
)->builtin_float
;
2297 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
2298 elem
= builtin_type (gdbarch
)->builtin_double
;
2299 append_composite_type_field (t
, "f64", elem
);
2301 TYPE_VECTOR (t
) = 1;
2302 TYPE_NAME (t
) = "neon_d";
2303 tdep
->neon_double_type
= t
;
2306 return tdep
->neon_double_type
;
2309 /* FIXME: The vector types are not correctly ordered on big-endian
2310 targets. Just as s0 is the low bits of d0, d0[0] is also the low
2311 bits of d0 - regardless of what unit size is being held in d0. So
2312 the offset of the first uint8 in d0 is 7, but the offset of the
2313 first float is 4. This code works as-is for little-endian
2316 static struct type
*
2317 arm_neon_quad_type (struct gdbarch
*gdbarch
)
2319 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2321 if (tdep
->neon_quad_type
== NULL
)
2323 struct type
*t
, *elem
;
2325 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
2327 elem
= builtin_type (gdbarch
)->builtin_uint8
;
2328 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
2329 elem
= builtin_type (gdbarch
)->builtin_uint16
;
2330 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
2331 elem
= builtin_type (gdbarch
)->builtin_uint32
;
2332 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
2333 elem
= builtin_type (gdbarch
)->builtin_uint64
;
2334 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
2335 elem
= builtin_type (gdbarch
)->builtin_float
;
2336 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
2337 elem
= builtin_type (gdbarch
)->builtin_double
;
2338 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
2340 TYPE_VECTOR (t
) = 1;
2341 TYPE_NAME (t
) = "neon_q";
2342 tdep
->neon_quad_type
= t
;
2345 return tdep
->neon_quad_type
;
2348 /* Return the GDB type object for the "standard" data type of data in
2351 static struct type
*
2352 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
2354 int num_regs
= gdbarch_num_regs (gdbarch
);
2356 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
2357 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
2358 return builtin_type (gdbarch
)->builtin_float
;
2360 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
2361 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
2362 return arm_neon_quad_type (gdbarch
);
2364 /* If the target description has register information, we are only
2365 in this function so that we can override the types of
2366 double-precision registers for NEON. */
2367 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
2369 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
2371 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
2372 && TYPE_CODE (t
) == TYPE_CODE_FLT
2373 && gdbarch_tdep (gdbarch
)->have_neon
)
2374 return arm_neon_double_type (gdbarch
);
2379 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
2381 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
2382 return builtin_type (gdbarch
)->builtin_void
;
2384 return arm_ext_type (gdbarch
);
2386 else if (regnum
== ARM_SP_REGNUM
)
2387 return builtin_type (gdbarch
)->builtin_data_ptr
;
2388 else if (regnum
== ARM_PC_REGNUM
)
2389 return builtin_type (gdbarch
)->builtin_func_ptr
;
2390 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
2391 /* These registers are only supported on targets which supply
2392 an XML description. */
2393 return builtin_type (gdbarch
)->builtin_int0
;
2395 return builtin_type (gdbarch
)->builtin_uint32
;
2398 /* Map a DWARF register REGNUM onto the appropriate GDB register
2402 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
2404 /* Core integer regs. */
2405 if (reg
>= 0 && reg
<= 15)
2408 /* Legacy FPA encoding. These were once used in a way which
2409 overlapped with VFP register numbering, so their use is
2410 discouraged, but GDB doesn't support the ARM toolchain
2411 which used them for VFP. */
2412 if (reg
>= 16 && reg
<= 23)
2413 return ARM_F0_REGNUM
+ reg
- 16;
2415 /* New assignments for the FPA registers. */
2416 if (reg
>= 96 && reg
<= 103)
2417 return ARM_F0_REGNUM
+ reg
- 96;
2419 /* WMMX register assignments. */
2420 if (reg
>= 104 && reg
<= 111)
2421 return ARM_WCGR0_REGNUM
+ reg
- 104;
2423 if (reg
>= 112 && reg
<= 127)
2424 return ARM_WR0_REGNUM
+ reg
- 112;
2426 if (reg
>= 192 && reg
<= 199)
2427 return ARM_WC0_REGNUM
+ reg
- 192;
2429 /* VFP v2 registers. A double precision value is actually
2430 in d1 rather than s2, but the ABI only defines numbering
2431 for the single precision registers. This will "just work"
2432 in GDB for little endian targets (we'll read eight bytes,
2433 starting in s0 and then progressing to s1), but will be
2434 reversed on big endian targets with VFP. This won't
2435 be a problem for the new Neon quad registers; you're supposed
2436 to use DW_OP_piece for those. */
2437 if (reg
>= 64 && reg
<= 95)
2441 sprintf (name_buf
, "s%d", reg
- 64);
2442 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
2446 /* VFP v3 / Neon registers. This range is also used for VFP v2
2447 registers, except that it now describes d0 instead of s0. */
2448 if (reg
>= 256 && reg
<= 287)
2452 sprintf (name_buf
, "d%d", reg
- 256);
2453 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
2460 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
2462 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
2465 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
2467 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
2468 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
2470 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
2471 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
2473 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
2474 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
2476 if (reg
< NUM_GREGS
)
2477 return SIM_ARM_R0_REGNUM
+ reg
;
2480 if (reg
< NUM_FREGS
)
2481 return SIM_ARM_FP0_REGNUM
+ reg
;
2484 if (reg
< NUM_SREGS
)
2485 return SIM_ARM_FPS_REGNUM
+ reg
;
2488 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
2491 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
2492 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
2493 It is thought that this is is the floating-point register format on
2494 little-endian systems. */
2497 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
2498 void *dbl
, int endianess
)
2502 if (endianess
== BFD_ENDIAN_BIG
)
2503 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
2505 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
2507 floatformat_from_doublest (fmt
, &d
, dbl
);
2511 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
2516 floatformat_to_doublest (fmt
, ptr
, &d
);
2517 if (endianess
== BFD_ENDIAN_BIG
)
2518 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
2520 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
2525 condition_true (unsigned long cond
, unsigned long status_reg
)
2527 if (cond
== INST_AL
|| cond
== INST_NV
)
2533 return ((status_reg
& FLAG_Z
) != 0);
2535 return ((status_reg
& FLAG_Z
) == 0);
2537 return ((status_reg
& FLAG_C
) != 0);
2539 return ((status_reg
& FLAG_C
) == 0);
2541 return ((status_reg
& FLAG_N
) != 0);
2543 return ((status_reg
& FLAG_N
) == 0);
2545 return ((status_reg
& FLAG_V
) != 0);
2547 return ((status_reg
& FLAG_V
) == 0);
2549 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
2551 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
2553 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
2555 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
2557 return (((status_reg
& FLAG_Z
) == 0)
2558 && (((status_reg
& FLAG_N
) == 0)
2559 == ((status_reg
& FLAG_V
) == 0)));
2561 return (((status_reg
& FLAG_Z
) != 0)
2562 || (((status_reg
& FLAG_N
) == 0)
2563 != ((status_reg
& FLAG_V
) == 0)));
2568 static unsigned long
2569 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
2570 unsigned long pc_val
, unsigned long status_reg
)
2572 unsigned long res
, shift
;
2573 int rm
= bits (inst
, 0, 3);
2574 unsigned long shifttype
= bits (inst
, 5, 6);
2578 int rs
= bits (inst
, 8, 11);
2579 shift
= (rs
== 15 ? pc_val
+ 8
2580 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
2583 shift
= bits (inst
, 7, 11);
2586 ? (pc_val
+ (bit (inst
, 4) ? 12 : 8))
2587 : get_frame_register_unsigned (frame
, rm
));
2592 res
= shift
>= 32 ? 0 : res
<< shift
;
2596 res
= shift
>= 32 ? 0 : res
>> shift
;
2602 res
= ((res
& 0x80000000L
)
2603 ? ~((~res
) >> shift
) : res
>> shift
);
2606 case 3: /* ROR/RRX */
2609 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
2611 res
= (res
>> shift
) | (res
<< (32 - shift
));
2615 return res
& 0xffffffff;
2618 /* Return number of 1-bits in VAL. */
2621 bitcount (unsigned long val
)
2624 for (nbits
= 0; val
!= 0; nbits
++)
2625 val
&= val
- 1; /* delete rightmost 1-bit in val */
2629 /* Return the size in bytes of the complete Thumb instruction whose
2630 first halfword is INST1. */
2633 thumb_insn_size (unsigned short inst1
)
2635 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
2642 thumb_advance_itstate (unsigned int itstate
)
2644 /* Preserve IT[7:5], the first three bits of the condition. Shift
2645 the upcoming condition flags left by one bit. */
2646 itstate
= (itstate
& 0xe0) | ((itstate
<< 1) & 0x1f);
2648 /* If we have finished the IT block, clear the state. */
2649 if ((itstate
& 0x0f) == 0)
2655 /* Find the next PC after the current instruction executes. In some
2656 cases we can not statically determine the answer (see the IT state
2657 handling in this function); in that case, a breakpoint may be
2658 inserted in addition to the returned PC, which will be used to set
2659 another breakpoint by our caller. */
2662 thumb_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
, int insert_bkpt
)
2664 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2665 struct address_space
*aspace
= get_frame_address_space (frame
);
2666 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2667 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2668 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
2669 unsigned short inst1
;
2670 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
2671 unsigned long offset
;
2672 ULONGEST status
, itstate
;
2674 nextpc
= MAKE_THUMB_ADDR (nextpc
);
2675 pc_val
= MAKE_THUMB_ADDR (pc_val
);
2677 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
2679 /* Thumb-2 conditional execution support. There are eight bits in
2680 the CPSR which describe conditional execution state. Once
2681 reconstructed (they're in a funny order), the low five bits
2682 describe the low bit of the condition for each instruction and
2683 how many instructions remain. The high three bits describe the
2684 base condition. One of the low four bits will be set if an IT
2685 block is active. These bits read as zero on earlier
2687 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
2688 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
2690 /* If-Then handling. On GNU/Linux, where this routine is used, we
2691 use an undefined instruction as a breakpoint. Unlike BKPT, IT
2692 can disable execution of the undefined instruction. So we might
2693 miss the breakpoint if we set it on a skipped conditional
2694 instruction. Because conditional instructions can change the
2695 flags, affecting the execution of further instructions, we may
2696 need to set two breakpoints. */
2698 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
!= NULL
)
2700 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
2702 /* An IT instruction. Because this instruction does not
2703 modify the flags, we can accurately predict the next
2704 executed instruction. */
2705 itstate
= inst1
& 0x00ff;
2706 pc
+= thumb_insn_size (inst1
);
2708 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
2710 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
2711 pc
+= thumb_insn_size (inst1
);
2712 itstate
= thumb_advance_itstate (itstate
);
2715 return MAKE_THUMB_ADDR (pc
);
2717 else if (itstate
!= 0)
2719 /* We are in a conditional block. Check the condition. */
2720 if (! condition_true (itstate
>> 4, status
))
2722 /* Advance to the next executed instruction. */
2723 pc
+= thumb_insn_size (inst1
);
2724 itstate
= thumb_advance_itstate (itstate
);
2726 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
2728 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
2729 pc
+= thumb_insn_size (inst1
);
2730 itstate
= thumb_advance_itstate (itstate
);
2733 return MAKE_THUMB_ADDR (pc
);
2735 else if ((itstate
& 0x0f) == 0x08)
2737 /* This is the last instruction of the conditional
2738 block, and it is executed. We can handle it normally
2739 because the following instruction is not conditional,
2740 and we must handle it normally because it is
2741 permitted to branch. Fall through. */
2747 /* There are conditional instructions after this one.
2748 If this instruction modifies the flags, then we can
2749 not predict what the next executed instruction will
2750 be. Fortunately, this instruction is architecturally
2751 forbidden to branch; we know it will fall through.
2752 Start by skipping past it. */
2753 pc
+= thumb_insn_size (inst1
);
2754 itstate
= thumb_advance_itstate (itstate
);
2756 /* Set a breakpoint on the following instruction. */
2757 gdb_assert ((itstate
& 0x0f) != 0);
2759 insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
2760 cond_negated
= (itstate
>> 4) & 1;
2762 /* Skip all following instructions with the same
2763 condition. If there is a later instruction in the IT
2764 block with the opposite condition, set the other
2765 breakpoint there. If not, then set a breakpoint on
2766 the instruction after the IT block. */
2769 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
2770 pc
+= thumb_insn_size (inst1
);
2771 itstate
= thumb_advance_itstate (itstate
);
2773 while (itstate
!= 0 && ((itstate
>> 4) & 1) == cond_negated
);
2775 return MAKE_THUMB_ADDR (pc
);
2779 else if (itstate
& 0x0f)
2781 /* We are in a conditional block. Check the condition. */
2782 int cond
= itstate
>> 4;
2784 if (! condition_true (cond
, status
))
2786 /* Advance to the next instruction. All the 32-bit
2787 instructions share a common prefix. */
2788 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
2789 return MAKE_THUMB_ADDR (pc
+ 4);
2791 return MAKE_THUMB_ADDR (pc
+ 2);
2794 /* Otherwise, handle the instruction normally. */
2797 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
2801 /* Fetch the saved PC from the stack. It's stored above
2802 all of the other registers. */
2803 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
2804 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
2805 nextpc
= read_memory_unsigned_integer (sp
+ offset
, 4, byte_order
);
2807 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
2809 unsigned long cond
= bits (inst1
, 8, 11);
2810 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
2811 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
2813 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
2815 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
2817 else if ((inst1
& 0xe000) == 0xe000) /* 32-bit instruction */
2819 unsigned short inst2
;
2820 inst2
= read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
2822 /* Default to the next instruction. */
2824 nextpc
= MAKE_THUMB_ADDR (nextpc
);
2826 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
2828 /* Branches and miscellaneous control instructions. */
2830 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
2833 int j1
, j2
, imm1
, imm2
;
2835 imm1
= sbits (inst1
, 0, 10);
2836 imm2
= bits (inst2
, 0, 10);
2837 j1
= bit (inst2
, 13);
2838 j2
= bit (inst2
, 11);
2840 offset
= ((imm1
<< 12) + (imm2
<< 1));
2841 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
2843 nextpc
= pc_val
+ offset
;
2844 /* For BLX make sure to clear the low bits. */
2845 if (bit (inst2
, 12) == 0)
2846 nextpc
= nextpc
& 0xfffffffc;
2848 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
2850 /* SUBS PC, LR, #imm8. */
2851 nextpc
= get_frame_register_unsigned (frame
, ARM_LR_REGNUM
);
2852 nextpc
-= inst2
& 0x00ff;
2854 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
2856 /* Conditional branch. */
2857 if (condition_true (bits (inst1
, 6, 9), status
))
2859 int sign
, j1
, j2
, imm1
, imm2
;
2861 sign
= sbits (inst1
, 10, 10);
2862 imm1
= bits (inst1
, 0, 5);
2863 imm2
= bits (inst2
, 0, 10);
2864 j1
= bit (inst2
, 13);
2865 j2
= bit (inst2
, 11);
2867 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
2868 offset
+= (imm1
<< 12) + (imm2
<< 1);
2870 nextpc
= pc_val
+ offset
;
2874 else if ((inst1
& 0xfe50) == 0xe810)
2876 /* Load multiple or RFE. */
2877 int rn
, offset
, load_pc
= 1;
2879 rn
= bits (inst1
, 0, 3);
2880 if (bit (inst1
, 7) && !bit (inst1
, 8))
2883 if (!bit (inst2
, 15))
2885 offset
= bitcount (inst2
) * 4 - 4;
2887 else if (!bit (inst1
, 7) && bit (inst1
, 8))
2890 if (!bit (inst2
, 15))
2894 else if (bit (inst1
, 7) && bit (inst1
, 8))
2899 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
2909 CORE_ADDR addr
= get_frame_register_unsigned (frame
, rn
);
2910 nextpc
= get_frame_memory_unsigned (frame
, addr
+ offset
, 4);
2913 else if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
2915 /* MOV PC or MOVS PC. */
2916 nextpc
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
2917 nextpc
= MAKE_THUMB_ADDR (nextpc
);
2919 else if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
2923 int rn
, load_pc
= 1;
2925 rn
= bits (inst1
, 0, 3);
2926 base
= get_frame_register_unsigned (frame
, rn
);
2929 base
= (base
+ 4) & ~(CORE_ADDR
) 0x3;
2931 base
+= bits (inst2
, 0, 11);
2933 base
-= bits (inst2
, 0, 11);
2935 else if (bit (inst1
, 7))
2936 base
+= bits (inst2
, 0, 11);
2937 else if (bit (inst2
, 11))
2939 if (bit (inst2
, 10))
2942 base
+= bits (inst2
, 0, 7);
2944 base
-= bits (inst2
, 0, 7);
2947 else if ((inst2
& 0x0fc0) == 0x0000)
2949 int shift
= bits (inst2
, 4, 5), rm
= bits (inst2
, 0, 3);
2950 base
+= get_frame_register_unsigned (frame
, rm
) << shift
;
2957 nextpc
= get_frame_memory_unsigned (frame
, base
, 4);
2959 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
2962 CORE_ADDR tbl_reg
, table
, offset
, length
;
2964 tbl_reg
= bits (inst1
, 0, 3);
2965 if (tbl_reg
== 0x0f)
2966 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
2968 table
= get_frame_register_unsigned (frame
, tbl_reg
);
2970 offset
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
2971 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 1);
2972 nextpc
= pc_val
+ length
;
2974 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
2977 CORE_ADDR tbl_reg
, table
, offset
, length
;
2979 tbl_reg
= bits (inst1
, 0, 3);
2980 if (tbl_reg
== 0x0f)
2981 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
2983 table
= get_frame_register_unsigned (frame
, tbl_reg
);
2985 offset
= 2 * get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
2986 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 2);
2987 nextpc
= pc_val
+ length
;
2990 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
2992 if (bits (inst1
, 3, 6) == 0x0f)
2995 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
2997 else if ((inst1
& 0xf500) == 0xb100)
3000 int imm
= (bit (inst1
, 9) << 6) + (bits (inst1
, 3, 7) << 1);
3001 ULONGEST reg
= get_frame_register_unsigned (frame
, bits (inst1
, 0, 2));
3003 if (bit (inst1
, 11) && reg
!= 0)
3004 nextpc
= pc_val
+ imm
;
3005 else if (!bit (inst1
, 11) && reg
== 0)
3006 nextpc
= pc_val
+ imm
;
3011 /* Get the raw next address. PC is the current program counter, in
3012 FRAME. INSERT_BKPT should be TRUE if we want a breakpoint set on
3013 the alternative next instruction if there are two options.
3015 The value returned has the execution state of the next instruction
3016 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
3017 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
3021 arm_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
, int insert_bkpt
)
3023 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3024 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3025 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3026 unsigned long pc_val
;
3027 unsigned long this_instr
;
3028 unsigned long status
;
3031 if (arm_frame_is_thumb (frame
))
3032 return thumb_get_next_pc_raw (frame
, pc
, insert_bkpt
);
3034 pc_val
= (unsigned long) pc
;
3035 this_instr
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3037 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
3038 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
3040 if (bits (this_instr
, 28, 31) == INST_NV
)
3041 switch (bits (this_instr
, 24, 27))
3046 /* Branch with Link and change to Thumb. */
3047 nextpc
= BranchDest (pc
, this_instr
);
3048 nextpc
|= bit (this_instr
, 24) << 1;
3049 nextpc
= MAKE_THUMB_ADDR (nextpc
);
3055 /* Coprocessor register transfer. */
3056 if (bits (this_instr
, 12, 15) == 15)
3057 error (_("Invalid update to pc in instruction"));
3060 else if (condition_true (bits (this_instr
, 28, 31), status
))
3062 switch (bits (this_instr
, 24, 27))
3065 case 0x1: /* data processing */
3069 unsigned long operand1
, operand2
, result
= 0;
3073 if (bits (this_instr
, 12, 15) != 15)
3076 if (bits (this_instr
, 22, 25) == 0
3077 && bits (this_instr
, 4, 7) == 9) /* multiply */
3078 error (_("Invalid update to pc in instruction"));
3080 /* BX <reg>, BLX <reg> */
3081 if (bits (this_instr
, 4, 27) == 0x12fff1
3082 || bits (this_instr
, 4, 27) == 0x12fff3)
3084 rn
= bits (this_instr
, 0, 3);
3085 nextpc
= (rn
== 15) ? pc_val
+ 8
3086 : get_frame_register_unsigned (frame
, rn
);
3090 /* Multiply into PC */
3091 c
= (status
& FLAG_C
) ? 1 : 0;
3092 rn
= bits (this_instr
, 16, 19);
3093 operand1
= (rn
== 15) ? pc_val
+ 8
3094 : get_frame_register_unsigned (frame
, rn
);
3096 if (bit (this_instr
, 25))
3098 unsigned long immval
= bits (this_instr
, 0, 7);
3099 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
3100 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
3103 else /* operand 2 is a shifted register */
3104 operand2
= shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
);
3106 switch (bits (this_instr
, 21, 24))
3109 result
= operand1
& operand2
;
3113 result
= operand1
^ operand2
;
3117 result
= operand1
- operand2
;
3121 result
= operand2
- operand1
;
3125 result
= operand1
+ operand2
;
3129 result
= operand1
+ operand2
+ c
;
3133 result
= operand1
- operand2
+ c
;
3137 result
= operand2
- operand1
+ c
;
3143 case 0xb: /* tst, teq, cmp, cmn */
3144 result
= (unsigned long) nextpc
;
3148 result
= operand1
| operand2
;
3152 /* Always step into a function. */
3157 result
= operand1
& ~operand2
;
3165 /* In 26-bit APCS the bottom two bits of the result are
3166 ignored, and we always end up in ARM state. */
3168 nextpc
= arm_addr_bits_remove (gdbarch
, result
);
3176 case 0x5: /* data transfer */
3179 if (bit (this_instr
, 20))
3182 if (bits (this_instr
, 12, 15) == 15)
3188 if (bit (this_instr
, 22))
3189 error (_("Invalid update to pc in instruction"));
3191 /* byte write to PC */
3192 rn
= bits (this_instr
, 16, 19);
3193 base
= (rn
== 15) ? pc_val
+ 8
3194 : get_frame_register_unsigned (frame
, rn
);
3195 if (bit (this_instr
, 24))
3198 int c
= (status
& FLAG_C
) ? 1 : 0;
3199 unsigned long offset
=
3200 (bit (this_instr
, 25)
3201 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
3202 : bits (this_instr
, 0, 11));
3204 if (bit (this_instr
, 23))
3209 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
3216 case 0x9: /* block transfer */
3217 if (bit (this_instr
, 20))
3220 if (bit (this_instr
, 15))
3225 if (bit (this_instr
, 23))
3228 unsigned long reglist
= bits (this_instr
, 0, 14);
3229 offset
= bitcount (reglist
) * 4;
3230 if (bit (this_instr
, 24)) /* pre */
3233 else if (bit (this_instr
, 24))
3237 unsigned long rn_val
=
3238 get_frame_register_unsigned (frame
,
3239 bits (this_instr
, 16, 19));
3241 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
3249 case 0xb: /* branch & link */
3250 case 0xa: /* branch */
3252 nextpc
= BranchDest (pc
, this_instr
);
3258 case 0xe: /* coproc ops */
3263 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
3272 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
3274 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3276 gdbarch_addr_bits_remove (gdbarch
,
3277 arm_get_next_pc_raw (frame
, pc
, TRUE
));
3279 error (_("Infinite loop detected"));
3283 /* single_step() is called just before we want to resume the inferior,
3284 if we want to single-step it but there is no hardware or kernel
3285 single-step support. We find the target of the coming instruction
3286 and breakpoint it. */
3289 arm_software_single_step (struct frame_info
*frame
)
3291 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3292 struct address_space
*aspace
= get_frame_address_space (frame
);
3294 /* NOTE: This may insert the wrong breakpoint instruction when
3295 single-stepping over a mode-changing instruction, if the
3296 CPSR heuristics are used. */
3298 CORE_ADDR next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
3299 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
3304 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
3305 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
3306 NULL if an error occurs. BUF is freed. */
3309 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
3310 int old_len
, int new_len
)
3312 gdb_byte
*new_buf
, *middle
;
3313 int bytes_to_read
= new_len
- old_len
;
3315 new_buf
= xmalloc (new_len
);
3316 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
3318 if (target_read_memory (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
3326 /* An IT block is at most the 2-byte IT instruction followed by
3327 four 4-byte instructions. The furthest back we must search to
3328 find an IT block that affects the current instruction is thus
3329 2 + 3 * 4 == 14 bytes. */
3330 #define MAX_IT_BLOCK_PREFIX 14
3332 /* Use a quick scan if there are more than this many bytes of
3334 #define IT_SCAN_THRESHOLD 32
3336 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
3337 A breakpoint in an IT block may not be hit, depending on the
3340 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
3344 CORE_ADDR boundary
, func_start
;
3345 int buf_len
, buf2_len
;
3346 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
3347 int i
, any
, last_it
, last_it_count
;
3349 /* If we are using BKPT breakpoints, none of this is necessary. */
3350 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
3353 /* ARM mode does not have this problem. */
3354 if (!arm_pc_is_thumb (bpaddr
))
3357 /* We are setting a breakpoint in Thumb code that could potentially
3358 contain an IT block. The first step is to find how much Thumb
3359 code there is; we do not need to read outside of known Thumb
3361 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
3363 /* Thumb-2 code must have mapping symbols to have a chance. */
3366 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
3368 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
3369 && func_start
> boundary
)
3370 boundary
= func_start
;
3372 /* Search for a candidate IT instruction. We have to do some fancy
3373 footwork to distinguish a real IT instruction from the second
3374 half of a 32-bit instruction, but there is no need for that if
3375 there's no candidate. */
3376 buf_len
= min (bpaddr
- boundary
, MAX_IT_BLOCK_PREFIX
);
3378 /* No room for an IT instruction. */
3381 buf
= xmalloc (buf_len
);
3382 if (target_read_memory (bpaddr
- buf_len
, buf
, buf_len
) != 0)
3385 for (i
= 0; i
< buf_len
; i
+= 2)
3387 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
3388 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
3400 /* OK, the code bytes before this instruction contain at least one
3401 halfword which resembles an IT instruction. We know that it's
3402 Thumb code, but there are still two possibilities. Either the
3403 halfword really is an IT instruction, or it is the second half of
3404 a 32-bit Thumb instruction. The only way we can tell is to
3405 scan forwards from a known instruction boundary. */
3406 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
3410 /* There's a lot of code before this instruction. Start with an
3411 optimistic search; it's easy to recognize halfwords that can
3412 not be the start of a 32-bit instruction, and use that to
3413 lock on to the instruction boundaries. */
3414 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
3417 buf_len
= IT_SCAN_THRESHOLD
;
3420 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
3422 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
3423 if (thumb_insn_size (inst1
) == 2)
3430 /* At this point, if DEFINITE, BUF[I] is the first place we
3431 are sure that we know the instruction boundaries, and it is far
3432 enough from BPADDR that we could not miss an IT instruction
3433 affecting BPADDR. If ! DEFINITE, give up - start from a
3437 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
3440 buf_len
= bpaddr
- boundary
;
3446 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
3449 buf_len
= bpaddr
- boundary
;
3453 /* Scan forwards. Find the last IT instruction before BPADDR. */
3458 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
3460 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
3465 else if (inst1
& 0x0002)
3467 else if (inst1
& 0x0004)
3472 i
+= thumb_insn_size (inst1
);
3478 /* There wasn't really an IT instruction after all. */
3481 if (last_it_count
< 1)
3482 /* It was too far away. */
3485 /* This really is a trouble spot. Move the breakpoint to the IT
3487 return bpaddr
- buf_len
+ last_it
;
3490 /* ARM displaced stepping support.
3492 Generally ARM displaced stepping works as follows:
3494 1. When an instruction is to be single-stepped, it is first decoded by
3495 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
3496 Depending on the type of instruction, it is then copied to a scratch
3497 location, possibly in a modified form. The copy_* set of functions
3498 performs such modification, as necessary. A breakpoint is placed after
3499 the modified instruction in the scratch space to return control to GDB.
3500 Note in particular that instructions which modify the PC will no longer
3501 do so after modification.
3503 2. The instruction is single-stepped, by setting the PC to the scratch
3504 location address, and resuming. Control returns to GDB when the
3507 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
3508 function used for the current instruction. This function's job is to
3509 put the CPU/memory state back to what it would have been if the
3510 instruction had been executed unmodified in its original location. */
3512 /* NOP instruction (mov r0, r0). */
3513 #define ARM_NOP 0xe1a00000
3515 /* Helper for register reads for displaced stepping. In particular, this
3516 returns the PC as it would be seen by the instruction at its original
3520 displaced_read_reg (struct regcache
*regs
, CORE_ADDR from
, int regno
)
3526 if (debug_displaced
)
3527 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
3528 (unsigned long) from
+ 8);
3529 return (ULONGEST
) from
+ 8; /* Pipeline offset. */
3533 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
3534 if (debug_displaced
)
3535 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
3536 regno
, (unsigned long) ret
);
3542 displaced_in_arm_mode (struct regcache
*regs
)
3546 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
3548 return (ps
& CPSR_T
) == 0;
3551 /* Write to the PC as from a branch instruction. */
3554 branch_write_pc (struct regcache
*regs
, ULONGEST val
)
3556 if (displaced_in_arm_mode (regs
))
3557 /* Note: If bits 0/1 are set, this branch would be unpredictable for
3558 architecture versions < 6. */
3559 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& ~(ULONGEST
) 0x3);
3561 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& ~(ULONGEST
) 0x1);
3564 /* Write to the PC as from a branch-exchange instruction. */
3567 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
3571 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
3575 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| CPSR_T
);
3576 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
3578 else if ((val
& 2) == 0)
3580 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
,
3581 ps
& ~(ULONGEST
) CPSR_T
);
3582 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
3586 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
3587 mode, align dest to 4 bytes). */
3588 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
3589 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
,
3590 ps
& ~(ULONGEST
) CPSR_T
);
3591 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
3595 /* Write to the PC as if from a load instruction. */
3598 load_write_pc (struct regcache
*regs
, ULONGEST val
)
3600 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
3601 bx_write_pc (regs
, val
);
3603 branch_write_pc (regs
, val
);
3606 /* Write to the PC as if from an ALU instruction. */
3609 alu_write_pc (struct regcache
*regs
, ULONGEST val
)
3611 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && displaced_in_arm_mode (regs
))
3612 bx_write_pc (regs
, val
);
3614 branch_write_pc (regs
, val
);
3617 /* Helper for writing to registers for displaced stepping. Writing to the PC
3618 has a varying effects depending on the instruction which does the write:
3619 this is controlled by the WRITE_PC argument. */
3622 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
3623 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
3627 if (debug_displaced
)
3628 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
3629 (unsigned long) val
);
3632 case BRANCH_WRITE_PC
:
3633 branch_write_pc (regs
, val
);
3637 bx_write_pc (regs
, val
);
3641 load_write_pc (regs
, val
);
3645 alu_write_pc (regs
, val
);
3648 case CANNOT_WRITE_PC
:
3649 warning (_("Instruction wrote to PC in an unexpected way when "
3650 "single-stepping"));
3654 internal_error (__FILE__
, __LINE__
,
3655 _("Invalid argument to displaced_write_reg"));
3658 dsc
->wrote_to_pc
= 1;
3662 if (debug_displaced
)
3663 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
3664 regno
, (unsigned long) val
);
3665 regcache_cooked_write_unsigned (regs
, regno
, val
);
3669 /* This function is used to concisely determine if an instruction INSN
3670 references PC. Register fields of interest in INSN should have the
3671 corresponding fields of BITMASK set to 0b1111. The function returns return 1
3672 if any of these fields in INSN reference the PC (also 0b1111, r15), else it
3676 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
3678 uint32_t lowbit
= 1;
3680 while (bitmask
!= 0)
3684 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
3690 mask
= lowbit
* 0xf;
3692 if ((insn
& mask
) == mask
)
3701 /* The simplest copy function. Many instructions have the same effect no
3702 matter what address they are executed at: in those cases, use this. */
3705 copy_unmodified (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, uint32_t insn
,
3706 const char *iname
, struct displaced_step_closure
*dsc
)
3708 if (debug_displaced
)
3709 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
3710 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
3713 dsc
->modinsn
[0] = insn
;
3718 /* Preload instructions with immediate offset. */
3721 cleanup_preload (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
3722 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3724 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
3725 if (!dsc
->u
.preload
.immed
)
3726 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
3730 copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
3731 struct displaced_step_closure
*dsc
)
3733 unsigned int rn
= bits (insn
, 16, 19);
3735 CORE_ADDR from
= dsc
->insn_addr
;
3737 if (!insn_references_pc (insn
, 0x000f0000ul
))
3738 return copy_unmodified (gdbarch
, insn
, "preload", dsc
);
3740 if (debug_displaced
)
3741 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
3742 (unsigned long) insn
);
3744 /* Preload instructions:
3746 {pli/pld} [rn, #+/-imm]
3748 {pli/pld} [r0, #+/-imm]. */
3750 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3751 rn_val
= displaced_read_reg (regs
, from
, rn
);
3752 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
3754 dsc
->u
.preload
.immed
= 1;
3756 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
3758 dsc
->cleanup
= &cleanup_preload
;
3763 /* Preload instructions with register offset. */
3766 copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
3767 struct displaced_step_closure
*dsc
)
3769 unsigned int rn
= bits (insn
, 16, 19);
3770 unsigned int rm
= bits (insn
, 0, 3);
3771 ULONGEST rn_val
, rm_val
;
3772 CORE_ADDR from
= dsc
->insn_addr
;
3774 if (!insn_references_pc (insn
, 0x000f000ful
))
3775 return copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
3777 if (debug_displaced
)
3778 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
3779 (unsigned long) insn
);
3781 /* Preload register-offset instructions:
3783 {pli/pld} [rn, rm {, shift}]
3785 {pli/pld} [r0, r1 {, shift}]. */
3787 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3788 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
3789 rn_val
= displaced_read_reg (regs
, from
, rn
);
3790 rm_val
= displaced_read_reg (regs
, from
, rm
);
3791 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
3792 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
3794 dsc
->u
.preload
.immed
= 0;
3796 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
3798 dsc
->cleanup
= &cleanup_preload
;
3803 /* Copy/cleanup coprocessor load and store instructions. */
3806 cleanup_copro_load_store (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
3807 struct regcache
*regs
,
3808 struct displaced_step_closure
*dsc
)
3810 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
3812 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
3814 if (dsc
->u
.ldst
.writeback
)
3815 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
3819 copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
3820 struct regcache
*regs
,
3821 struct displaced_step_closure
*dsc
)
3823 unsigned int rn
= bits (insn
, 16, 19);
3825 CORE_ADDR from
= dsc
->insn_addr
;
3827 if (!insn_references_pc (insn
, 0x000f0000ul
))
3828 return copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
3830 if (debug_displaced
)
3831 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
3832 "load/store insn %.8lx\n", (unsigned long) insn
);
3834 /* Coprocessor load/store instructions:
3836 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
3838 {stc/stc2} [r0, #+/-imm].
3840 ldc/ldc2 are handled identically. */
3842 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
3843 rn_val
= displaced_read_reg (regs
, from
, rn
);
3844 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
3846 dsc
->u
.ldst
.writeback
= bit (insn
, 25);
3847 dsc
->u
.ldst
.rn
= rn
;
3849 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
3851 dsc
->cleanup
= &cleanup_copro_load_store
;
3856 /* Clean up branch instructions (actually perform the branch, by setting
3860 cleanup_branch (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, struct regcache
*regs
,
3861 struct displaced_step_closure
*dsc
)
3863 ULONGEST from
= dsc
->insn_addr
;
3864 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
3865 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
3866 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
3867 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
3872 if (dsc
->u
.branch
.link
)
3874 ULONGEST pc
= displaced_read_reg (regs
, from
, 15);
3875 displaced_write_reg (regs
, dsc
, 14, pc
- 4, CANNOT_WRITE_PC
);
3878 displaced_write_reg (regs
, dsc
, 15, dsc
->u
.branch
.dest
, write_pc
);
3881 /* Copy B/BL/BLX instructions with immediate destinations. */
3884 copy_b_bl_blx (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, uint32_t insn
,
3885 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3887 unsigned int cond
= bits (insn
, 28, 31);
3888 int exchange
= (cond
== 0xf);
3889 int link
= exchange
|| bit (insn
, 24);
3890 CORE_ADDR from
= dsc
->insn_addr
;
3893 if (debug_displaced
)
3894 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
3895 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
3896 (unsigned long) insn
);
3898 /* Implement "BL<cond> <label>" as:
3900 Preparation: cond <- instruction condition
3901 Insn: mov r0, r0 (nop)
3902 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
3904 B<cond> similar, but don't set r14 in cleanup. */
3907 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
3908 then arrange the switch into Thumb mode. */
3909 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
3911 offset
= bits (insn
, 0, 23) << 2;
3913 if (bit (offset
, 25))
3914 offset
= offset
| ~0x3ffffff;
3916 dsc
->u
.branch
.cond
= cond
;
3917 dsc
->u
.branch
.link
= link
;
3918 dsc
->u
.branch
.exchange
= exchange
;
3919 dsc
->u
.branch
.dest
= from
+ 8 + offset
;
3921 dsc
->modinsn
[0] = ARM_NOP
;
3923 dsc
->cleanup
= &cleanup_branch
;
3928 /* Copy BX/BLX with register-specified destinations. */
3931 copy_bx_blx_reg (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, uint32_t insn
,
3932 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3934 unsigned int cond
= bits (insn
, 28, 31);
3937 int link
= bit (insn
, 5);
3938 unsigned int rm
= bits (insn
, 0, 3);
3939 CORE_ADDR from
= dsc
->insn_addr
;
3941 if (debug_displaced
)
3942 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s register insn "
3943 "%.8lx\n", (link
) ? "blx" : "bx", (unsigned long) insn
);
3945 /* Implement {BX,BLX}<cond> <reg>" as:
3947 Preparation: cond <- instruction condition
3948 Insn: mov r0, r0 (nop)
3949 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
3951 Don't set r14 in cleanup for BX. */
3953 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, from
, rm
);
3955 dsc
->u
.branch
.cond
= cond
;
3956 dsc
->u
.branch
.link
= link
;
3957 dsc
->u
.branch
.exchange
= 1;
3959 dsc
->modinsn
[0] = ARM_NOP
;
3961 dsc
->cleanup
= &cleanup_branch
;
3966 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
3969 cleanup_alu_imm (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
3970 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
3972 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
3973 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
3974 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
3975 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
3979 copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
3980 struct displaced_step_closure
*dsc
)
3982 unsigned int rn
= bits (insn
, 16, 19);
3983 unsigned int rd
= bits (insn
, 12, 15);
3984 unsigned int op
= bits (insn
, 21, 24);
3985 int is_mov
= (op
== 0xd);
3986 ULONGEST rd_val
, rn_val
;
3987 CORE_ADDR from
= dsc
->insn_addr
;
3989 if (!insn_references_pc (insn
, 0x000ff000ul
))
3990 return copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
3992 if (debug_displaced
)
3993 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
3994 "%.8lx\n", is_mov
? "move" : "ALU",
3995 (unsigned long) insn
);
3997 /* Instruction is of form:
3999 <op><cond> rd, [rn,] #imm
4003 Preparation: tmp1, tmp2 <- r0, r1;
4005 Insn: <op><cond> r0, r1, #imm
4006 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
4009 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
4010 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
4011 rn_val
= displaced_read_reg (regs
, from
, rn
);
4012 rd_val
= displaced_read_reg (regs
, from
, rd
);
4013 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
4014 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
4018 dsc
->modinsn
[0] = insn
& 0xfff00fff;
4020 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
4022 dsc
->cleanup
= &cleanup_alu_imm
;
4027 /* Copy/cleanup arithmetic/logic insns with register RHS. */
4030 cleanup_alu_reg (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
4031 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4036 rd_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
4038 for (i
= 0; i
< 3; i
++)
4039 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
4041 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
4045 copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4046 struct displaced_step_closure
*dsc
)
4048 unsigned int rn
= bits (insn
, 16, 19);
4049 unsigned int rm
= bits (insn
, 0, 3);
4050 unsigned int rd
= bits (insn
, 12, 15);
4051 unsigned int op
= bits (insn
, 21, 24);
4052 int is_mov
= (op
== 0xd);
4053 ULONGEST rd_val
, rn_val
, rm_val
;
4054 CORE_ADDR from
= dsc
->insn_addr
;
4056 if (!insn_references_pc (insn
, 0x000ff00ful
))
4057 return copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
4059 if (debug_displaced
)
4060 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
4061 is_mov
? "move" : "ALU", (unsigned long) insn
);
4063 /* Instruction is of form:
4065 <op><cond> rd, [rn,] rm [, <shift>]
4069 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
4070 r0, r1, r2 <- rd, rn, rm
4071 Insn: <op><cond> r0, r1, r2 [, <shift>]
4072 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
4075 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
4076 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
4077 dsc
->tmp
[2] = displaced_read_reg (regs
, from
, 2);
4078 rd_val
= displaced_read_reg (regs
, from
, rd
);
4079 rn_val
= displaced_read_reg (regs
, from
, rn
);
4080 rm_val
= displaced_read_reg (regs
, from
, rm
);
4081 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
4082 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
4083 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
4087 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
4089 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
4091 dsc
->cleanup
= &cleanup_alu_reg
;
4096 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
4099 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
4100 struct regcache
*regs
,
4101 struct displaced_step_closure
*dsc
)
4103 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
->insn_addr
, 0);
4106 for (i
= 0; i
< 4; i
++)
4107 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
4109 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
4113 copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
4114 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4116 unsigned int rn
= bits (insn
, 16, 19);
4117 unsigned int rm
= bits (insn
, 0, 3);
4118 unsigned int rd
= bits (insn
, 12, 15);
4119 unsigned int rs
= bits (insn
, 8, 11);
4120 unsigned int op
= bits (insn
, 21, 24);
4121 int is_mov
= (op
== 0xd), i
;
4122 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
4123 CORE_ADDR from
= dsc
->insn_addr
;
4125 if (!insn_references_pc (insn
, 0x000fff0ful
))
4126 return copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
4128 if (debug_displaced
)
4129 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
4130 "%.8lx\n", is_mov
? "move" : "ALU",
4131 (unsigned long) insn
);
4133 /* Instruction is of form:
4135 <op><cond> rd, [rn,] rm, <shift> rs
4139 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
4140 r0, r1, r2, r3 <- rd, rn, rm, rs
4141 Insn: <op><cond> r0, r1, r2, <shift> r3
4143 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
4147 for (i
= 0; i
< 4; i
++)
4148 dsc
->tmp
[i
] = displaced_read_reg (regs
, from
, i
);
4150 rd_val
= displaced_read_reg (regs
, from
, rd
);
4151 rn_val
= displaced_read_reg (regs
, from
, rn
);
4152 rm_val
= displaced_read_reg (regs
, from
, rm
);
4153 rs_val
= displaced_read_reg (regs
, from
, rs
);
4154 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
4155 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
4156 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
4157 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
4161 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
4163 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
4165 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
4170 /* Clean up load instructions. */
4173 cleanup_load (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, struct regcache
*regs
,
4174 struct displaced_step_closure
*dsc
)
4176 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
4177 CORE_ADDR from
= dsc
->insn_addr
;
4179 rt_val
= displaced_read_reg (regs
, from
, 0);
4180 if (dsc
->u
.ldst
.xfersize
== 8)
4181 rt_val2
= displaced_read_reg (regs
, from
, 1);
4182 rn_val
= displaced_read_reg (regs
, from
, 2);
4184 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4185 if (dsc
->u
.ldst
.xfersize
> 4)
4186 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
4187 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
4188 if (!dsc
->u
.ldst
.immed
)
4189 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
4191 /* Handle register writeback. */
4192 if (dsc
->u
.ldst
.writeback
)
4193 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
4194 /* Put result in right place. */
4195 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
4196 if (dsc
->u
.ldst
.xfersize
== 8)
4197 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
4200 /* Clean up store instructions. */
4203 cleanup_store (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, struct regcache
*regs
,
4204 struct displaced_step_closure
*dsc
)
4206 CORE_ADDR from
= dsc
->insn_addr
;
4207 ULONGEST rn_val
= displaced_read_reg (regs
, from
, 2);
4209 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
4210 if (dsc
->u
.ldst
.xfersize
> 4)
4211 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
4212 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
4213 if (!dsc
->u
.ldst
.immed
)
4214 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
4215 if (!dsc
->u
.ldst
.restore_r4
)
4216 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
4219 if (dsc
->u
.ldst
.writeback
)
4220 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
4223 /* Copy "extra" load/store instructions. These are halfword/doubleword
4224 transfers, which have a different encoding to byte/word transfers. */
4227 copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unpriveleged
,
4228 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4230 unsigned int op1
= bits (insn
, 20, 24);
4231 unsigned int op2
= bits (insn
, 5, 6);
4232 unsigned int rt
= bits (insn
, 12, 15);
4233 unsigned int rn
= bits (insn
, 16, 19);
4234 unsigned int rm
= bits (insn
, 0, 3);
4235 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
4236 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
4237 int immed
= (op1
& 0x4) != 0;
4239 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
4240 CORE_ADDR from
= dsc
->insn_addr
;
4242 if (!insn_references_pc (insn
, 0x000ff00ful
))
4243 return copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
4245 if (debug_displaced
)
4246 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
4247 "insn %.8lx\n", unpriveleged
? "unpriveleged " : "",
4248 (unsigned long) insn
);
4250 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
4253 internal_error (__FILE__
, __LINE__
,
4254 _("copy_extra_ld_st: instruction decode error"));
4256 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
4257 dsc
->tmp
[1] = displaced_read_reg (regs
, from
, 1);
4258 dsc
->tmp
[2] = displaced_read_reg (regs
, from
, 2);
4260 dsc
->tmp
[3] = displaced_read_reg (regs
, from
, 3);
4262 rt_val
= displaced_read_reg (regs
, from
, rt
);
4263 if (bytesize
[opcode
] == 8)
4264 rt_val2
= displaced_read_reg (regs
, from
, rt
+ 1);
4265 rn_val
= displaced_read_reg (regs
, from
, rn
);
4267 rm_val
= displaced_read_reg (regs
, from
, rm
);
4269 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
4270 if (bytesize
[opcode
] == 8)
4271 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
4272 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
4274 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
4277 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
4278 dsc
->u
.ldst
.rn
= rn
;
4279 dsc
->u
.ldst
.immed
= immed
;
4280 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
4281 dsc
->u
.ldst
.restore_r4
= 0;
4284 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
4286 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
4287 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
4289 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
4291 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
4292 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
4294 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
4299 /* Copy byte/word loads and stores. */
4302 copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
4303 struct regcache
*regs
,
4304 struct displaced_step_closure
*dsc
, int load
, int byte
,
4307 int immed
= !bit (insn
, 25);
4308 unsigned int rt
= bits (insn
, 12, 15);
4309 unsigned int rn
= bits (insn
, 16, 19);
4310 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
4311 ULONGEST rt_val
, rn_val
, rm_val
= 0;
4312 CORE_ADDR from
= dsc
->insn_addr
;
4314 if (!insn_references_pc (insn
, 0x000ff00ful
))
4315 return copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
4317 if (debug_displaced
)
4318 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s%s insn %.8lx\n",
4319 load
? (byte
? "ldrb" : "ldr")
4320 : (byte
? "strb" : "str"), usermode
? "t" : "",
4321 (unsigned long) insn
);
4323 dsc
->tmp
[0] = displaced_read_reg (regs
, from
, 0);
4324 dsc
->tmp
[2] = displaced_read_reg (regs
, from
, 2);
4326 dsc
->tmp
[3] = displaced_read_reg (regs
, from
, 3);
4328 dsc
->tmp
[4] = displaced_read_reg (regs
, from
, 4);
4330 rt_val
= displaced_read_reg (regs
, from
, rt
);
4331 rn_val
= displaced_read_reg (regs
, from
, rn
);
4333 rm_val
= displaced_read_reg (regs
, from
, rm
);
4335 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
4336 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
4338 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
4341 dsc
->u
.ldst
.xfersize
= byte
? 1 : 4;
4342 dsc
->u
.ldst
.rn
= rn
;
4343 dsc
->u
.ldst
.immed
= immed
;
4344 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
4346 /* To write PC we can do:
4348 scratch+0: str pc, temp (*temp = scratch + 8 + offset)
4349 scratch+4: ldr r4, temp
4350 scratch+8: sub r4, r4, pc (r4 = scratch + 8 + offset - scratch - 8 - 8)
4351 scratch+12: add r4, r4, #8 (r4 = offset)
4352 scratch+16: add r0, r0, r4
4353 scratch+20: str r0, [r2, #imm] (or str r0, [r2, r3])
4356 Otherwise we don't know what value to write for PC, since the offset is
4357 architecture-dependent (sometimes PC+8, sometimes PC+12). */
4359 if (load
|| rt
!= 15)
4361 dsc
->u
.ldst
.restore_r4
= 0;
4364 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
4366 {ldr,str}[b]<cond> r0, [r2, #imm]. */
4367 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
4369 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
4371 {ldr,str}[b]<cond> r0, [r2, r3]. */
4372 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
4376 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
4377 dsc
->u
.ldst
.restore_r4
= 1;
4379 dsc
->modinsn
[0] = 0xe58ff014; /* str pc, [pc, #20]. */
4380 dsc
->modinsn
[1] = 0xe59f4010; /* ldr r4, [pc, #16]. */
4381 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
4382 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
4383 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
4387 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
4389 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
4391 dsc
->modinsn
[6] = 0x0; /* breakpoint location. */
4392 dsc
->modinsn
[7] = 0x0; /* scratch space. */
4397 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
4402 /* Cleanup LDM instructions with fully-populated register list. This is an
4403 unfortunate corner case: it's impossible to implement correctly by modifying
4404 the instruction. The issue is as follows: we have an instruction,
4408 which we must rewrite to avoid loading PC. A possible solution would be to
4409 do the load in two halves, something like (with suitable cleanup
4413 ldm[id][ab] r8!, {r0-r7}
4415 ldm[id][ab] r8, {r7-r14}
4418 but at present there's no suitable place for <temp>, since the scratch space
4419 is overwritten before the cleanup routine is called. For now, we simply
4420 emulate the instruction. */
4423 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4424 struct displaced_step_closure
*dsc
)
4426 ULONGEST from
= dsc
->insn_addr
;
4427 int inc
= dsc
->u
.block
.increment
;
4428 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
4429 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
4430 uint32_t regmask
= dsc
->u
.block
.regmask
;
4431 int regno
= inc
? 0 : 15;
4432 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
4433 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
4434 && (regmask
& 0x8000) != 0;
4435 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
4436 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
4437 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4442 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
4443 sensible we can do here. Complain loudly. */
4444 if (exception_return
)
4445 error (_("Cannot single-step exception return"));
4447 /* We don't handle any stores here for now. */
4448 gdb_assert (dsc
->u
.block
.load
!= 0);
4450 if (debug_displaced
)
4451 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
4452 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
4453 dsc
->u
.block
.increment
? "inc" : "dec",
4454 dsc
->u
.block
.before
? "before" : "after");
4461 while (regno
<= 15 && (regmask
& (1 << regno
)) == 0)
4464 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
4467 xfer_addr
+= bump_before
;
4469 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
4470 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
4472 xfer_addr
+= bump_after
;
4474 regmask
&= ~(1 << regno
);
4477 if (dsc
->u
.block
.writeback
)
4478 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
4482 /* Clean up an STM which included the PC in the register list. */
4485 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
4486 struct displaced_step_closure
*dsc
)
4488 ULONGEST from
= dsc
->insn_addr
;
4489 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
4490 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
4491 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
4492 CORE_ADDR stm_insn_addr
;
4495 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4497 /* If condition code fails, there's nothing else to do. */
4498 if (!store_executed
)
4501 if (dsc
->u
.block
.increment
)
4503 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
4505 if (dsc
->u
.block
.before
)
4510 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
4512 if (dsc
->u
.block
.before
)
4516 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
4517 stm_insn_addr
= dsc
->scratch_base
;
4518 offset
= pc_val
- stm_insn_addr
;
4520 if (debug_displaced
)
4521 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
4522 "STM instruction\n", offset
);
4524 /* Rewrite the stored PC to the proper value for the non-displaced original
4526 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
4527 dsc
->insn_addr
+ offset
);
4530 /* Clean up an LDM which includes the PC in the register list. We clumped all
4531 the registers in the transferred list into a contiguous range r0...rX (to
4532 avoid loading PC directly and losing control of the debugged program), so we
4533 must undo that here. */
4536 cleanup_block_load_pc (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
,
4537 struct regcache
*regs
,
4538 struct displaced_step_closure
*dsc
)
4540 ULONGEST from
= dsc
->insn_addr
;
4541 uint32_t status
= displaced_read_reg (regs
, from
, ARM_PS_REGNUM
);
4542 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
), i
;
4543 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= 15;
4544 unsigned int regs_loaded
= bitcount (mask
);
4545 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
4547 /* The method employed here will fail if the register list is fully populated
4548 (we need to avoid loading PC directly). */
4549 gdb_assert (num_to_shuffle
< 16);
4554 clobbered
= (1 << num_to_shuffle
) - 1;
4556 while (num_to_shuffle
> 0)
4558 if ((mask
& (1 << write_reg
)) != 0)
4560 unsigned int read_reg
= num_to_shuffle
- 1;
4562 if (read_reg
!= write_reg
)
4564 ULONGEST rval
= displaced_read_reg (regs
, from
, read_reg
);
4565 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
4566 if (debug_displaced
)
4567 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
4568 "loaded register r%d to r%d\n"), read_reg
,
4571 else if (debug_displaced
)
4572 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
4573 "r%d already in the right place\n"),
4576 clobbered
&= ~(1 << write_reg
);
4584 /* Restore any registers we scribbled over. */
4585 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
4587 if ((clobbered
& (1 << write_reg
)) != 0)
4589 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
4591 if (debug_displaced
)
4592 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
4593 "clobbered register r%d\n"), write_reg
);
4594 clobbered
&= ~(1 << write_reg
);
4598 /* Perform register writeback manually. */
4599 if (dsc
->u
.block
.writeback
)
4601 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
4603 if (dsc
->u
.block
.increment
)
4604 new_rn_val
+= regs_loaded
* 4;
4606 new_rn_val
-= regs_loaded
* 4;
4608 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
4613 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
4614 in user-level code (in particular exception return, ldm rn, {...pc}^). */
4617 copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
4618 struct displaced_step_closure
*dsc
)
4620 int load
= bit (insn
, 20);
4621 int user
= bit (insn
, 22);
4622 int increment
= bit (insn
, 23);
4623 int before
= bit (insn
, 24);
4624 int writeback
= bit (insn
, 21);
4625 int rn
= bits (insn
, 16, 19);
4626 CORE_ADDR from
= dsc
->insn_addr
;
4628 /* Block transfers which don't mention PC can be run directly out-of-line. */
4629 if (rn
!= 15 && (insn
& 0x8000) == 0)
4630 return copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
4634 warning (_("displaced: Unpredictable LDM or STM with base register r15"));
4635 return copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
4638 if (debug_displaced
)
4639 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
4640 "%.8lx\n", (unsigned long) insn
);
4642 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, from
, rn
);
4643 dsc
->u
.block
.rn
= rn
;
4645 dsc
->u
.block
.load
= load
;
4646 dsc
->u
.block
.user
= user
;
4647 dsc
->u
.block
.increment
= increment
;
4648 dsc
->u
.block
.before
= before
;
4649 dsc
->u
.block
.writeback
= writeback
;
4650 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
4652 dsc
->u
.block
.regmask
= insn
& 0xffff;
4656 if ((insn
& 0xffff) == 0xffff)
4658 /* LDM with a fully-populated register list. This case is
4659 particularly tricky. Implement for now by fully emulating the
4660 instruction (which might not behave perfectly in all cases, but
4661 these instructions should be rare enough for that not to matter
4663 dsc
->modinsn
[0] = ARM_NOP
;
4665 dsc
->cleanup
= &cleanup_block_load_all
;
4669 /* LDM of a list of registers which includes PC. Implement by
4670 rewriting the list of registers to be transferred into a
4671 contiguous chunk r0...rX before doing the transfer, then shuffling
4672 registers into the correct places in the cleanup routine. */
4673 unsigned int regmask
= insn
& 0xffff;
4674 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
4675 unsigned int to
= 0, from
= 0, i
, new_rn
;
4677 for (i
= 0; i
< num_in_list
; i
++)
4678 dsc
->tmp
[i
] = displaced_read_reg (regs
, from
, i
);
4680 /* Writeback makes things complicated. We need to avoid clobbering
4681 the base register with one of the registers in our modified
4682 register list, but just using a different register can't work in
4685 ldm r14!, {r0-r13,pc}
4687 which would need to be rewritten as:
4691 but that can't work, because there's no free register for N.
4693 Solve this by turning off the writeback bit, and emulating
4694 writeback manually in the cleanup routine. */
4699 new_regmask
= (1 << num_in_list
) - 1;
4701 if (debug_displaced
)
4702 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
4703 "{..., pc}: original reg list %.4x, modified "
4704 "list %.4x\n"), rn
, writeback
? "!" : "",
4705 (int) insn
& 0xffff, new_regmask
);
4707 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
4709 dsc
->cleanup
= &cleanup_block_load_pc
;
4714 /* STM of a list of registers which includes PC. Run the instruction
4715 as-is, but out of line: this will store the wrong value for the PC,
4716 so we must manually fix up the memory in the cleanup routine.
4717 Doing things this way has the advantage that we can auto-detect
4718 the offset of the PC write (which is architecture-dependent) in
4719 the cleanup routine. */
4720 dsc
->modinsn
[0] = insn
;
4722 dsc
->cleanup
= &cleanup_block_store_pc
;
4728 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
4729 for Linux, where some SVC instructions must be treated specially. */
4732 cleanup_svc (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, struct regcache
*regs
,
4733 struct displaced_step_closure
*dsc
)
4735 CORE_ADDR from
= dsc
->insn_addr
;
4736 CORE_ADDR resume_addr
= from
+ 4;
4738 if (debug_displaced
)
4739 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
4740 "%.8lx\n", (unsigned long) resume_addr
);
4742 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
4746 copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
4747 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4749 CORE_ADDR from
= dsc
->insn_addr
;
4751 /* Allow OS-specific code to override SVC handling. */
4752 if (dsc
->u
.svc
.copy_svc_os
)
4753 return dsc
->u
.svc
.copy_svc_os (gdbarch
, insn
, to
, regs
, dsc
);
4755 if (debug_displaced
)
4756 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
4757 (unsigned long) insn
);
4759 /* Preparation: none.
4760 Insn: unmodified svc.
4761 Cleanup: pc <- insn_addr + 4. */
4763 dsc
->modinsn
[0] = insn
;
4765 dsc
->cleanup
= &cleanup_svc
;
4766 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
4768 dsc
->wrote_to_pc
= 1;
4773 /* Copy undefined instructions. */
4776 copy_undef (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, uint32_t insn
,
4777 struct displaced_step_closure
*dsc
)
4779 if (debug_displaced
)
4780 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn %.8lx\n",
4781 (unsigned long) insn
);
4783 dsc
->modinsn
[0] = insn
;
4788 /* Copy unpredictable instructions. */
4791 copy_unpred (struct gdbarch
*gdbarch ATTRIBUTE_UNUSED
, uint32_t insn
,
4792 struct displaced_step_closure
*dsc
)
4794 if (debug_displaced
)
4795 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
4796 "%.8lx\n", (unsigned long) insn
);
4798 dsc
->modinsn
[0] = insn
;
4803 /* The decode_* functions are instruction decoding helpers. They mostly follow
4804 the presentation in the ARM ARM. */
4807 decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
4808 struct regcache
*regs
,
4809 struct displaced_step_closure
*dsc
)
4811 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
4812 unsigned int rn
= bits (insn
, 16, 19);
4814 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
4815 return copy_unmodified (gdbarch
, insn
, "cps", dsc
);
4816 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
4817 return copy_unmodified (gdbarch
, insn
, "setend", dsc
);
4818 else if ((op1
& 0x60) == 0x20)
4819 return copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
4820 else if ((op1
& 0x71) == 0x40)
4821 return copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store", dsc
);
4822 else if ((op1
& 0x77) == 0x41)
4823 return copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
4824 else if ((op1
& 0x77) == 0x45)
4825 return copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
4826 else if ((op1
& 0x77) == 0x51)
4829 return copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
4831 return copy_unpred (gdbarch
, insn
, dsc
);
4833 else if ((op1
& 0x77) == 0x55)
4834 return copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
4835 else if (op1
== 0x57)
4838 case 0x1: return copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
4839 case 0x4: return copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
4840 case 0x5: return copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
4841 case 0x6: return copy_unmodified (gdbarch
, insn
, "isb", dsc
);
4842 default: return copy_unpred (gdbarch
, insn
, dsc
);
4844 else if ((op1
& 0x63) == 0x43)
4845 return copy_unpred (gdbarch
, insn
, dsc
);
4846 else if ((op2
& 0x1) == 0x0)
4847 switch (op1
& ~0x80)
4850 return copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
4852 return copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
4853 case 0x71: case 0x75:
4855 return copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
4856 case 0x63: case 0x67: case 0x73: case 0x77:
4857 return copy_unpred (gdbarch
, insn
, dsc
);
4859 return copy_undef (gdbarch
, insn
, dsc
);
4862 return copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
4866 decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
4867 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4869 if (bit (insn
, 27) == 0)
4870 return decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
4871 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
4872 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
4875 return copy_unmodified (gdbarch
, insn
, "srs", dsc
);
4878 return copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
4880 case 0x4: case 0x5: case 0x6: case 0x7:
4881 return copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
4884 switch ((insn
& 0xe00000) >> 21)
4886 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
4888 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4891 return copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
4894 return copy_undef (gdbarch
, insn
, dsc
);
4899 int rn_f
= (bits (insn
, 16, 19) == 0xf);
4900 switch ((insn
& 0xe00000) >> 21)
4903 /* ldc/ldc2 imm (undefined for rn == pc). */
4904 return rn_f
? copy_undef (gdbarch
, insn
, dsc
)
4905 : copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4908 return copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
4910 case 0x4: case 0x5: case 0x6: case 0x7:
4911 /* ldc/ldc2 lit (undefined for rn != pc). */
4912 return rn_f
? copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
4913 : copy_undef (gdbarch
, insn
, dsc
);
4916 return copy_undef (gdbarch
, insn
, dsc
);
4921 return copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
4924 if (bits (insn
, 16, 19) == 0xf)
4926 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
4928 return copy_undef (gdbarch
, insn
, dsc
);
4932 return copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
4934 return copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
4938 return copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
4940 return copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
4943 return copy_undef (gdbarch
, insn
, dsc
);
4947 /* Decode miscellaneous instructions in dp/misc encoding space. */
4950 decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
4951 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
4953 unsigned int op2
= bits (insn
, 4, 6);
4954 unsigned int op
= bits (insn
, 21, 22);
4955 unsigned int op1
= bits (insn
, 16, 19);
4960 return copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
4963 if (op
== 0x1) /* bx. */
4964 return copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
4966 return copy_unmodified (gdbarch
, insn
, "clz", dsc
);
4968 return copy_undef (gdbarch
, insn
, dsc
);
4972 /* Not really supported. */
4973 return copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
4975 return copy_undef (gdbarch
, insn
, dsc
);
4979 return copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
); /* blx register. */
4981 return copy_undef (gdbarch
, insn
, dsc
);
4984 return copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
4988 return copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
4990 /* Not really supported. */
4991 return copy_unmodified (gdbarch
, insn
, "smc", dsc
);
4994 return copy_undef (gdbarch
, insn
, dsc
);
4999 decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5000 struct displaced_step_closure
*dsc
)
5003 switch (bits (insn
, 20, 24))
5006 return copy_unmodified (gdbarch
, insn
, "movw", dsc
);
5009 return copy_unmodified (gdbarch
, insn
, "movt", dsc
);
5011 case 0x12: case 0x16:
5012 return copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
5015 return copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
5019 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
5021 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
5022 return copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
5023 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
5024 return copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
5025 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
5026 return decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
5027 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
5028 return copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
5029 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
5030 return copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
5031 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
5032 return copy_unmodified (gdbarch
, insn
, "synch", dsc
);
5033 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
5034 /* 2nd arg means "unpriveleged". */
5035 return copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
5039 /* Should be unreachable. */
5044 decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
5045 struct regcache
*regs
,
5046 struct displaced_step_closure
*dsc
)
5048 int a
= bit (insn
, 25), b
= bit (insn
, 4);
5049 uint32_t op1
= bits (insn
, 20, 24);
5050 int rn_f
= bits (insn
, 16, 19) == 0xf;
5052 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
5053 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
5054 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 0, 0);
5055 else if ((!a
&& (op1
& 0x17) == 0x02)
5056 || (a
&& (op1
& 0x17) == 0x02 && !b
))
5057 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 0, 1);
5058 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
5059 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
5060 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 0, 0);
5061 else if ((!a
&& (op1
& 0x17) == 0x03)
5062 || (a
&& (op1
& 0x17) == 0x03 && !b
))
5063 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 0, 1);
5064 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
5065 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
5066 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
5067 else if ((!a
&& (op1
& 0x17) == 0x06)
5068 || (a
&& (op1
& 0x17) == 0x06 && !b
))
5069 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
5070 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
5071 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
5072 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
5073 else if ((!a
&& (op1
& 0x17) == 0x07)
5074 || (a
&& (op1
& 0x17) == 0x07 && !b
))
5075 return copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
5077 /* Should be unreachable. */
5082 decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
5083 struct displaced_step_closure
*dsc
)
5085 switch (bits (insn
, 20, 24))
5087 case 0x00: case 0x01: case 0x02: case 0x03:
5088 return copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
5090 case 0x04: case 0x05: case 0x06: case 0x07:
5091 return copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
5093 case 0x08: case 0x09: case 0x0a: case 0x0b:
5094 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
5095 return copy_unmodified (gdbarch
, insn
,
5096 "decode/pack/unpack/saturate/reverse", dsc
);
5099 if (bits (insn
, 5, 7) == 0) /* op2. */
5101 if (bits (insn
, 12, 15) == 0xf)
5102 return copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
5104 return copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
5107 return copy_undef (gdbarch
, insn
, dsc
);
5109 case 0x1a: case 0x1b:
5110 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
5111 return copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
5113 return copy_undef (gdbarch
, insn
, dsc
);
5115 case 0x1c: case 0x1d:
5116 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
5118 if (bits (insn
, 0, 3) == 0xf)
5119 return copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
5121 return copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
5124 return copy_undef (gdbarch
, insn
, dsc
);
5126 case 0x1e: case 0x1f:
5127 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
5128 return copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
5130 return copy_undef (gdbarch
, insn
, dsc
);
5133 /* Should be unreachable. */
5138 decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, int32_t insn
,
5139 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5142 return copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
5144 return copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
5148 decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
5149 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5151 unsigned int opcode
= bits (insn
, 20, 24);
5155 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
5156 return copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
5158 case 0x08: case 0x0a: case 0x0c: case 0x0e:
5159 case 0x12: case 0x16:
5160 return copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
5162 case 0x09: case 0x0b: case 0x0d: case 0x0f:
5163 case 0x13: case 0x17:
5164 return copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
5166 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
5167 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
5168 /* Note: no writeback for these instructions. Bit 25 will always be
5169 zero though (via caller), so the following works OK. */
5170 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
5173 /* Should be unreachable. */
5178 decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
5179 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5181 unsigned int op1
= bits (insn
, 20, 25);
5182 int op
= bit (insn
, 4);
5183 unsigned int coproc
= bits (insn
, 8, 11);
5184 unsigned int rn
= bits (insn
, 16, 19);
5186 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
5187 return decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
5188 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
5189 && (coproc
& 0xe) != 0xa)
5191 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
5192 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
5193 && (coproc
& 0xe) != 0xa)
5194 /* ldc/ldc2 imm/lit. */
5195 return copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
5196 else if ((op1
& 0x3e) == 0x00)
5197 return copy_undef (gdbarch
, insn
, dsc
);
5198 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
5199 return copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
5200 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
5201 return copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
5202 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
5203 return copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
5204 else if ((op1
& 0x30) == 0x20 && !op
)
5206 if ((coproc
& 0xe) == 0xa)
5207 return copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
5209 return copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
5211 else if ((op1
& 0x30) == 0x20 && op
)
5212 return copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
5213 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
5214 return copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
5215 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
5216 return copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
5217 else if ((op1
& 0x30) == 0x30)
5218 return copy_svc (gdbarch
, insn
, to
, regs
, dsc
);
5220 return copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
5224 arm_process_displaced_insn (struct gdbarch
*gdbarch
, uint32_t insn
,
5225 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
,
5226 struct displaced_step_closure
*dsc
)
5230 if (!displaced_in_arm_mode (regs
))
5231 error (_("Displaced stepping is only supported in ARM mode"));
5233 /* Most displaced instructions use a 1-instruction scratch space, so set this
5234 here and override below if/when necessary. */
5236 dsc
->insn_addr
= from
;
5237 dsc
->scratch_base
= to
;
5238 dsc
->cleanup
= NULL
;
5239 dsc
->wrote_to_pc
= 0;
5241 if ((insn
& 0xf0000000) == 0xf0000000)
5242 err
= decode_unconditional (gdbarch
, insn
, regs
, dsc
);
5243 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
5245 case 0x0: case 0x1: case 0x2: case 0x3:
5246 err
= decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
5249 case 0x4: case 0x5: case 0x6:
5250 err
= decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
5254 err
= decode_media (gdbarch
, insn
, dsc
);
5257 case 0x8: case 0x9: case 0xa: case 0xb:
5258 err
= decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
5261 case 0xc: case 0xd: case 0xe: case 0xf:
5262 err
= decode_svc_copro (gdbarch
, insn
, to
, regs
, dsc
);
5267 internal_error (__FILE__
, __LINE__
,
5268 _("arm_process_displaced_insn: Instruction decode error"));
5271 /* Actually set up the scratch space for a displaced instruction. */
5274 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
5275 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
5277 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5279 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5281 /* Poke modified instruction(s). */
5282 for (i
= 0; i
< dsc
->numinsns
; i
++)
5284 if (debug_displaced
)
5285 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn %.8lx at "
5286 "%.8lx\n", (unsigned long) dsc
->modinsn
[i
],
5287 (unsigned long) to
+ i
* 4);
5288 write_memory_unsigned_integer (to
+ i
* 4, 4, byte_order_for_code
,
5292 /* Put breakpoint afterwards. */
5293 write_memory (to
+ dsc
->numinsns
* 4, tdep
->arm_breakpoint
,
5294 tdep
->arm_breakpoint_size
);
5296 if (debug_displaced
)
5297 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
5298 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
5301 /* Entry point for copying an instruction into scratch space for displaced
5304 struct displaced_step_closure
*
5305 arm_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
5306 CORE_ADDR from
, CORE_ADDR to
,
5307 struct regcache
*regs
)
5309 struct displaced_step_closure
*dsc
5310 = xmalloc (sizeof (struct displaced_step_closure
));
5311 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5312 uint32_t insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
5314 if (debug_displaced
)
5315 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
5316 "at %.8lx\n", (unsigned long) insn
,
5317 (unsigned long) from
);
5319 arm_process_displaced_insn (gdbarch
, insn
, from
, to
, regs
, dsc
);
5320 arm_displaced_init_closure (gdbarch
, from
, to
, dsc
);
5325 /* Entry point for cleaning things up after a displaced instruction has been
5329 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
5330 struct displaced_step_closure
*dsc
,
5331 CORE_ADDR from
, CORE_ADDR to
,
5332 struct regcache
*regs
)
5335 dsc
->cleanup (gdbarch
, regs
, dsc
);
5337 if (!dsc
->wrote_to_pc
)
5338 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, dsc
->insn_addr
+ 4);
5341 #include "bfd-in2.h"
5342 #include "libcoff.h"
5345 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
5347 if (arm_pc_is_thumb (memaddr
))
5349 static asymbol
*asym
;
5350 static combined_entry_type ce
;
5351 static struct coff_symbol_struct csym
;
5352 static struct bfd fake_bfd
;
5353 static bfd_target fake_target
;
5355 if (csym
.native
== NULL
)
5357 /* Create a fake symbol vector containing a Thumb symbol.
5358 This is solely so that the code in print_insn_little_arm()
5359 and print_insn_big_arm() in opcodes/arm-dis.c will detect
5360 the presence of a Thumb symbol and switch to decoding
5361 Thumb instructions. */
5363 fake_target
.flavour
= bfd_target_coff_flavour
;
5364 fake_bfd
.xvec
= &fake_target
;
5365 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
5367 csym
.symbol
.the_bfd
= &fake_bfd
;
5368 csym
.symbol
.name
= "fake";
5369 asym
= (asymbol
*) & csym
;
5372 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
5373 info
->symbols
= &asym
;
5376 info
->symbols
= NULL
;
5378 if (info
->endian
== BFD_ENDIAN_BIG
)
5379 return print_insn_big_arm (memaddr
, info
);
5381 return print_insn_little_arm (memaddr
, info
);
5384 /* The following define instruction sequences that will cause ARM
5385 cpu's to take an undefined instruction trap. These are used to
5386 signal a breakpoint to GDB.
5388 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
5389 modes. A different instruction is required for each mode. The ARM
5390 cpu's can also be big or little endian. Thus four different
5391 instructions are needed to support all cases.
5393 Note: ARMv4 defines several new instructions that will take the
5394 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
5395 not in fact add the new instructions. The new undefined
5396 instructions in ARMv4 are all instructions that had no defined
5397 behaviour in earlier chips. There is no guarantee that they will
5398 raise an exception, but may be treated as NOP's. In practice, it
5399 may only safe to rely on instructions matching:
5401 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
5402 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
5403 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
5405 Even this may only true if the condition predicate is true. The
5406 following use a condition predicate of ALWAYS so it is always TRUE.
5408 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
5409 and NetBSD all use a software interrupt rather than an undefined
5410 instruction to force a trap. This can be handled by by the
5411 abi-specific code during establishment of the gdbarch vector. */
5413 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
5414 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
5415 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
5416 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
5418 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
5419 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
5420 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
5421 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
5423 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
5424 the program counter value to determine whether a 16-bit or 32-bit
5425 breakpoint should be used. It returns a pointer to a string of
5426 bytes that encode a breakpoint instruction, stores the length of
5427 the string to *lenptr, and adjusts the program counter (if
5428 necessary) to point to the actual memory location where the
5429 breakpoint should be inserted. */
5431 static const unsigned char *
5432 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
5434 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5435 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5437 if (arm_pc_is_thumb (*pcptr
))
5439 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
5441 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
5442 check whether we are replacing a 32-bit instruction. */
5443 if (tdep
->thumb2_breakpoint
!= NULL
)
5446 if (target_read_memory (*pcptr
, buf
, 2) == 0)
5448 unsigned short inst1
;
5449 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
5450 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
5452 *lenptr
= tdep
->thumb2_breakpoint_size
;
5453 return tdep
->thumb2_breakpoint
;
5458 *lenptr
= tdep
->thumb_breakpoint_size
;
5459 return tdep
->thumb_breakpoint
;
5463 *lenptr
= tdep
->arm_breakpoint_size
;
5464 return tdep
->arm_breakpoint
;
5469 arm_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
5472 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5474 arm_breakpoint_from_pc (gdbarch
, pcptr
, kindptr
);
5476 if (arm_pc_is_thumb (*pcptr
) && *kindptr
== 4)
5477 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
5478 that this is not confused with a 32-bit ARM breakpoint. */
5482 /* Extract from an array REGBUF containing the (raw) register state a
5483 function return value of type TYPE, and copy that, in virtual
5484 format, into VALBUF. */
5487 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
5490 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
5491 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5493 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
5495 switch (gdbarch_tdep (gdbarch
)->fp_model
)
5499 /* The value is in register F0 in internal format. We need to
5500 extract the raw value and then convert it to the desired
5502 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
5504 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
5505 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
5506 valbuf
, gdbarch_byte_order (gdbarch
));
5510 case ARM_FLOAT_SOFT_FPA
:
5511 case ARM_FLOAT_SOFT_VFP
:
5512 /* ARM_FLOAT_VFP can arise if this is a variadic function so
5513 not using the VFP ABI code. */
5515 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
5516 if (TYPE_LENGTH (type
) > 4)
5517 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
5518 valbuf
+ INT_REGISTER_SIZE
);
5523 (__FILE__
, __LINE__
,
5524 _("arm_extract_return_value: Floating point model not supported"));
5528 else if (TYPE_CODE (type
) == TYPE_CODE_INT
5529 || TYPE_CODE (type
) == TYPE_CODE_CHAR
5530 || TYPE_CODE (type
) == TYPE_CODE_BOOL
5531 || TYPE_CODE (type
) == TYPE_CODE_PTR
5532 || TYPE_CODE (type
) == TYPE_CODE_REF
5533 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
5535 /* If the the type is a plain integer, then the access is
5536 straight-forward. Otherwise we have to play around a bit more. */
5537 int len
= TYPE_LENGTH (type
);
5538 int regno
= ARM_A1_REGNUM
;
5543 /* By using store_unsigned_integer we avoid having to do
5544 anything special for small big-endian values. */
5545 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
5546 store_unsigned_integer (valbuf
,
5547 (len
> INT_REGISTER_SIZE
5548 ? INT_REGISTER_SIZE
: len
),
5550 len
-= INT_REGISTER_SIZE
;
5551 valbuf
+= INT_REGISTER_SIZE
;
5556 /* For a structure or union the behaviour is as if the value had
5557 been stored to word-aligned memory and then loaded into
5558 registers with 32-bit load instruction(s). */
5559 int len
= TYPE_LENGTH (type
);
5560 int regno
= ARM_A1_REGNUM
;
5561 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
5565 regcache_cooked_read (regs
, regno
++, tmpbuf
);
5566 memcpy (valbuf
, tmpbuf
,
5567 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
5568 len
-= INT_REGISTER_SIZE
;
5569 valbuf
+= INT_REGISTER_SIZE
;
5575 /* Will a function return an aggregate type in memory or in a
5576 register? Return 0 if an aggregate type can be returned in a
5577 register, 1 if it must be returned in memory. */
5580 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
5583 enum type_code code
;
5585 CHECK_TYPEDEF (type
);
5587 /* In the ARM ABI, "integer" like aggregate types are returned in
5588 registers. For an aggregate type to be integer like, its size
5589 must be less than or equal to INT_REGISTER_SIZE and the
5590 offset of each addressable subfield must be zero. Note that bit
5591 fields are not addressable, and all addressable subfields of
5592 unions always start at offset zero.
5594 This function is based on the behaviour of GCC 2.95.1.
5595 See: gcc/arm.c: arm_return_in_memory() for details.
5597 Note: All versions of GCC before GCC 2.95.2 do not set up the
5598 parameters correctly for a function returning the following
5599 structure: struct { float f;}; This should be returned in memory,
5600 not a register. Richard Earnshaw sent me a patch, but I do not
5601 know of any way to detect if a function like the above has been
5602 compiled with the correct calling convention. */
5604 /* All aggregate types that won't fit in a register must be returned
5606 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
5611 /* The AAPCS says all aggregates not larger than a word are returned
5613 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
5616 /* The only aggregate types that can be returned in a register are
5617 structs and unions. Arrays must be returned in memory. */
5618 code
= TYPE_CODE (type
);
5619 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
5624 /* Assume all other aggregate types can be returned in a register.
5625 Run a check for structures, unions and arrays. */
5628 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
5631 /* Need to check if this struct/union is "integer" like. For
5632 this to be true, its size must be less than or equal to
5633 INT_REGISTER_SIZE and the offset of each addressable
5634 subfield must be zero. Note that bit fields are not
5635 addressable, and unions always start at offset zero. If any
5636 of the subfields is a floating point type, the struct/union
5637 cannot be an integer type. */
5639 /* For each field in the object, check:
5640 1) Is it FP? --> yes, nRc = 1;
5641 2) Is it addressable (bitpos != 0) and
5642 not packed (bitsize == 0)?
5646 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
5648 enum type_code field_type_code
;
5649 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, i
)));
5651 /* Is it a floating point type field? */
5652 if (field_type_code
== TYPE_CODE_FLT
)
5658 /* If bitpos != 0, then we have to care about it. */
5659 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
5661 /* Bitfields are not addressable. If the field bitsize is
5662 zero, then the field is not packed. Hence it cannot be
5663 a bitfield or any other packed type. */
5664 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
5676 /* Write into appropriate registers a function return value of type
5677 TYPE, given in virtual format. */
5680 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
5681 const gdb_byte
*valbuf
)
5683 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
5684 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5686 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
5688 char buf
[MAX_REGISTER_SIZE
];
5690 switch (gdbarch_tdep (gdbarch
)->fp_model
)
5694 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
5695 gdbarch_byte_order (gdbarch
));
5696 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
5699 case ARM_FLOAT_SOFT_FPA
:
5700 case ARM_FLOAT_SOFT_VFP
:
5701 /* ARM_FLOAT_VFP can arise if this is a variadic function so
5702 not using the VFP ABI code. */
5704 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
5705 if (TYPE_LENGTH (type
) > 4)
5706 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
5707 valbuf
+ INT_REGISTER_SIZE
);
5712 (__FILE__
, __LINE__
,
5713 _("arm_store_return_value: Floating point model not supported"));
5717 else if (TYPE_CODE (type
) == TYPE_CODE_INT
5718 || TYPE_CODE (type
) == TYPE_CODE_CHAR
5719 || TYPE_CODE (type
) == TYPE_CODE_BOOL
5720 || TYPE_CODE (type
) == TYPE_CODE_PTR
5721 || TYPE_CODE (type
) == TYPE_CODE_REF
5722 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
5724 if (TYPE_LENGTH (type
) <= 4)
5726 /* Values of one word or less are zero/sign-extended and
5728 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
5729 LONGEST val
= unpack_long (type
, valbuf
);
5731 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
5732 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
5736 /* Integral values greater than one word are stored in consecutive
5737 registers starting with r0. This will always be a multiple of
5738 the regiser size. */
5739 int len
= TYPE_LENGTH (type
);
5740 int regno
= ARM_A1_REGNUM
;
5744 regcache_cooked_write (regs
, regno
++, valbuf
);
5745 len
-= INT_REGISTER_SIZE
;
5746 valbuf
+= INT_REGISTER_SIZE
;
5752 /* For a structure or union the behaviour is as if the value had
5753 been stored to word-aligned memory and then loaded into
5754 registers with 32-bit load instruction(s). */
5755 int len
= TYPE_LENGTH (type
);
5756 int regno
= ARM_A1_REGNUM
;
5757 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
5761 memcpy (tmpbuf
, valbuf
,
5762 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
5763 regcache_cooked_write (regs
, regno
++, tmpbuf
);
5764 len
-= INT_REGISTER_SIZE
;
5765 valbuf
+= INT_REGISTER_SIZE
;
5771 /* Handle function return values. */
5773 static enum return_value_convention
5774 arm_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
5775 struct type
*valtype
, struct regcache
*regcache
,
5776 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5778 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5779 enum arm_vfp_cprc_base_type vfp_base_type
;
5782 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
5783 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
5785 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
5786 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
5788 for (i
= 0; i
< vfp_base_count
; i
++)
5790 if (reg_char
== 'q')
5793 arm_neon_quad_write (gdbarch
, regcache
, i
,
5794 writebuf
+ i
* unit_length
);
5797 arm_neon_quad_read (gdbarch
, regcache
, i
,
5798 readbuf
+ i
* unit_length
);
5805 sprintf (name_buf
, "%c%d", reg_char
, i
);
5806 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
5809 regcache_cooked_write (regcache
, regnum
,
5810 writebuf
+ i
* unit_length
);
5812 regcache_cooked_read (regcache
, regnum
,
5813 readbuf
+ i
* unit_length
);
5816 return RETURN_VALUE_REGISTER_CONVENTION
;
5819 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
5820 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
5821 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
5823 if (tdep
->struct_return
== pcc_struct_return
5824 || arm_return_in_memory (gdbarch
, valtype
))
5825 return RETURN_VALUE_STRUCT_CONVENTION
;
5829 arm_store_return_value (valtype
, regcache
, writebuf
);
5832 arm_extract_return_value (valtype
, regcache
, readbuf
);
5834 return RETURN_VALUE_REGISTER_CONVENTION
;
5839 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
5841 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5842 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5843 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5845 char buf
[INT_REGISTER_SIZE
];
5847 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
5849 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
5853 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
5857 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
5858 return the target PC. Otherwise return 0. */
5861 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
5865 CORE_ADDR start_addr
;
5867 /* Find the starting address and name of the function containing the PC. */
5868 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5871 /* If PC is in a Thumb call or return stub, return the address of the
5872 target PC, which is in a register. The thunk functions are called
5873 _call_via_xx, where x is the register name. The possible names
5874 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
5875 functions, named __ARM_call_via_r[0-7]. */
5876 if (strncmp (name
, "_call_via_", 10) == 0
5877 || strncmp (name
, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0)
5879 /* Use the name suffix to determine which register contains the
5881 static char *table
[15] =
5882 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5883 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
5886 int offset
= strlen (name
) - 2;
5888 for (regno
= 0; regno
<= 14; regno
++)
5889 if (strcmp (&name
[offset
], table
[regno
]) == 0)
5890 return get_frame_register_unsigned (frame
, regno
);
5893 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
5894 non-interworking calls to foo. We could decode the stubs
5895 to find the target but it's easier to use the symbol table. */
5896 namelen
= strlen (name
);
5897 if (name
[0] == '_' && name
[1] == '_'
5898 && ((namelen
> 2 + strlen ("_from_thumb")
5899 && strncmp (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb",
5900 strlen ("_from_thumb")) == 0)
5901 || (namelen
> 2 + strlen ("_from_arm")
5902 && strncmp (name
+ namelen
- strlen ("_from_arm"), "_from_arm",
5903 strlen ("_from_arm")) == 0)))
5906 int target_len
= namelen
- 2;
5907 struct minimal_symbol
*minsym
;
5908 struct objfile
*objfile
;
5909 struct obj_section
*sec
;
5911 if (name
[namelen
- 1] == 'b')
5912 target_len
-= strlen ("_from_thumb");
5914 target_len
-= strlen ("_from_arm");
5916 target_name
= alloca (target_len
+ 1);
5917 memcpy (target_name
, name
+ 2, target_len
);
5918 target_name
[target_len
] = '\0';
5920 sec
= find_pc_section (pc
);
5921 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
5922 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
5924 return SYMBOL_VALUE_ADDRESS (minsym
);
5929 return 0; /* not a stub */
5933 set_arm_command (char *args
, int from_tty
)
5935 printf_unfiltered (_("\
5936 \"set arm\" must be followed by an apporpriate subcommand.\n"));
5937 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
5941 show_arm_command (char *args
, int from_tty
)
5943 cmd_show_list (showarmcmdlist
, from_tty
, "");
5947 arm_update_current_architecture (void)
5949 struct gdbarch_info info
;
5951 /* If the current architecture is not ARM, we have nothing to do. */
5952 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_arm
)
5955 /* Update the architecture. */
5956 gdbarch_info_init (&info
);
5958 if (!gdbarch_update_p (info
))
5959 internal_error (__FILE__
, __LINE__
, "could not update architecture");
5963 set_fp_model_sfunc (char *args
, int from_tty
,
5964 struct cmd_list_element
*c
)
5966 enum arm_float_model fp_model
;
5968 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
5969 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
5971 arm_fp_model
= fp_model
;
5975 if (fp_model
== ARM_FLOAT_LAST
)
5976 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
5979 arm_update_current_architecture ();
5983 show_fp_model (struct ui_file
*file
, int from_tty
,
5984 struct cmd_list_element
*c
, const char *value
)
5986 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
5988 if (arm_fp_model
== ARM_FLOAT_AUTO
5989 && gdbarch_bfd_arch_info (target_gdbarch
)->arch
== bfd_arch_arm
)
5990 fprintf_filtered (file
, _("\
5991 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
5992 fp_model_strings
[tdep
->fp_model
]);
5994 fprintf_filtered (file
, _("\
5995 The current ARM floating point model is \"%s\".\n"),
5996 fp_model_strings
[arm_fp_model
]);
6000 arm_set_abi (char *args
, int from_tty
,
6001 struct cmd_list_element
*c
)
6003 enum arm_abi_kind arm_abi
;
6005 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
6006 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
6008 arm_abi_global
= arm_abi
;
6012 if (arm_abi
== ARM_ABI_LAST
)
6013 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
6016 arm_update_current_architecture ();
6020 arm_show_abi (struct ui_file
*file
, int from_tty
,
6021 struct cmd_list_element
*c
, const char *value
)
6023 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
6025 if (arm_abi_global
== ARM_ABI_AUTO
6026 && gdbarch_bfd_arch_info (target_gdbarch
)->arch
== bfd_arch_arm
)
6027 fprintf_filtered (file
, _("\
6028 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
6029 arm_abi_strings
[tdep
->arm_abi
]);
6031 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
6036 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
6037 struct cmd_list_element
*c
, const char *value
)
6039 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
6041 fprintf_filtered (file
, _("\
6042 The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"),
6043 arm_fallback_mode_string
);
6047 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
6048 struct cmd_list_element
*c
, const char *value
)
6050 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
6052 fprintf_filtered (file
, _("\
6053 The current execution mode assumed (even when symbols are available) is \"%s\".\n"),
6054 arm_force_mode_string
);
6057 /* If the user changes the register disassembly style used for info
6058 register and other commands, we have to also switch the style used
6059 in opcodes for disassembly output. This function is run in the "set
6060 arm disassembly" command, and does that. */
6063 set_disassembly_style_sfunc (char *args
, int from_tty
,
6064 struct cmd_list_element
*c
)
6066 set_disassembly_style ();
6069 /* Return the ARM register name corresponding to register I. */
6071 arm_register_name (struct gdbarch
*gdbarch
, int i
)
6073 const int num_regs
= gdbarch_num_regs (gdbarch
);
6075 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
6076 && i
>= num_regs
&& i
< num_regs
+ 32)
6078 static const char *const vfp_pseudo_names
[] = {
6079 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
6080 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
6081 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
6082 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
6085 return vfp_pseudo_names
[i
- num_regs
];
6088 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
6089 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
6091 static const char *const neon_pseudo_names
[] = {
6092 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
6093 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
6096 return neon_pseudo_names
[i
- num_regs
- 32];
6099 if (i
>= ARRAY_SIZE (arm_register_names
))
6100 /* These registers are only supported on targets which supply
6101 an XML description. */
6104 return arm_register_names
[i
];
6108 set_disassembly_style (void)
6112 /* Find the style that the user wants. */
6113 for (current
= 0; current
< num_disassembly_options
; current
++)
6114 if (disassembly_style
== valid_disassembly_styles
[current
])
6116 gdb_assert (current
< num_disassembly_options
);
6118 /* Synchronize the disassembler. */
6119 set_arm_regname_option (current
);
6122 /* Test whether the coff symbol specific value corresponds to a Thumb
6126 coff_sym_is_thumb (int val
)
6128 return (val
== C_THUMBEXT
6129 || val
== C_THUMBSTAT
6130 || val
== C_THUMBEXTFUNC
6131 || val
== C_THUMBSTATFUNC
6132 || val
== C_THUMBLABEL
);
6135 /* arm_coff_make_msymbol_special()
6136 arm_elf_make_msymbol_special()
6138 These functions test whether the COFF or ELF symbol corresponds to
6139 an address in thumb code, and set a "special" bit in a minimal
6140 symbol to indicate that it does. */
6143 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
6145 /* Thumb symbols are of type STT_LOPROC, (synonymous with
6147 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
6149 MSYMBOL_SET_SPECIAL (msym
);
6153 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
6155 if (coff_sym_is_thumb (val
))
6156 MSYMBOL_SET_SPECIAL (msym
);
6160 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
6162 struct arm_per_objfile
*data
= arg
;
6165 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
6166 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
6170 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
6173 const char *name
= bfd_asymbol_name (sym
);
6174 struct arm_per_objfile
*data
;
6175 VEC(arm_mapping_symbol_s
) **map_p
;
6176 struct arm_mapping_symbol new_map_sym
;
6178 gdb_assert (name
[0] == '$');
6179 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
6182 data
= objfile_data (objfile
, arm_objfile_data_key
);
6185 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
6186 struct arm_per_objfile
);
6187 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
6188 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
6189 objfile
->obfd
->section_count
,
6190 VEC(arm_mapping_symbol_s
) *);
6192 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
6194 new_map_sym
.value
= sym
->value
;
6195 new_map_sym
.type
= name
[1];
6197 /* Assume that most mapping symbols appear in order of increasing
6198 value. If they were randomly distributed, it would be faster to
6199 always push here and then sort at first use. */
6200 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
6202 struct arm_mapping_symbol
*prev_map_sym
;
6204 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
6205 if (prev_map_sym
->value
>= sym
->value
)
6208 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
6209 arm_compare_mapping_symbols
);
6210 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
6215 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
6219 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
6221 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
6223 /* If necessary, set the T bit. */
6227 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
6228 if (arm_pc_is_thumb (pc
))
6229 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
, val
| CPSR_T
);
6231 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
6232 val
& ~(ULONGEST
) CPSR_T
);
6236 /* Read the contents of a NEON quad register, by reading from two
6237 double registers. This is used to implement the quad pseudo
6238 registers, and for argument passing in case the quad registers are
6239 missing; vectors are passed in quad registers when using the VFP
6240 ABI, even if a NEON unit is not present. REGNUM is the index of
6241 the quad register, in [0, 15]. */
6244 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
6245 int regnum
, gdb_byte
*buf
)
6248 gdb_byte reg_buf
[8];
6249 int offset
, double_regnum
;
6251 sprintf (name_buf
, "d%d", regnum
<< 1);
6252 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
6255 /* d0 is always the least significant half of q0. */
6256 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6261 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
6262 memcpy (buf
+ offset
, reg_buf
, 8);
6264 offset
= 8 - offset
;
6265 regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
6266 memcpy (buf
+ offset
, reg_buf
, 8);
6270 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
6271 int regnum
, gdb_byte
*buf
)
6273 const int num_regs
= gdbarch_num_regs (gdbarch
);
6275 gdb_byte reg_buf
[8];
6276 int offset
, double_regnum
;
6278 gdb_assert (regnum
>= num_regs
);
6281 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
6282 /* Quad-precision register. */
6283 arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
6286 /* Single-precision register. */
6287 gdb_assert (regnum
< 32);
6289 /* s0 is always the least significant half of d0. */
6290 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6291 offset
= (regnum
& 1) ? 0 : 4;
6293 offset
= (regnum
& 1) ? 4 : 0;
6295 sprintf (name_buf
, "d%d", regnum
>> 1);
6296 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
6299 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
6300 memcpy (buf
, reg_buf
+ offset
, 4);
6304 /* Store the contents of BUF to a NEON quad register, by writing to
6305 two double registers. This is used to implement the quad pseudo
6306 registers, and for argument passing in case the quad registers are
6307 missing; vectors are passed in quad registers when using the VFP
6308 ABI, even if a NEON unit is not present. REGNUM is the index
6309 of the quad register, in [0, 15]. */
6312 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
6313 int regnum
, const gdb_byte
*buf
)
6316 gdb_byte reg_buf
[8];
6317 int offset
, double_regnum
;
6319 sprintf (name_buf
, "d%d", regnum
<< 1);
6320 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
6323 /* d0 is always the least significant half of q0. */
6324 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6329 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
6330 offset
= 8 - offset
;
6331 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
6335 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
6336 int regnum
, const gdb_byte
*buf
)
6338 const int num_regs
= gdbarch_num_regs (gdbarch
);
6340 gdb_byte reg_buf
[8];
6341 int offset
, double_regnum
;
6343 gdb_assert (regnum
>= num_regs
);
6346 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
6347 /* Quad-precision register. */
6348 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
6351 /* Single-precision register. */
6352 gdb_assert (regnum
< 32);
6354 /* s0 is always the least significant half of d0. */
6355 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6356 offset
= (regnum
& 1) ? 0 : 4;
6358 offset
= (regnum
& 1) ? 4 : 0;
6360 sprintf (name_buf
, "d%d", regnum
>> 1);
6361 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
6364 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
6365 memcpy (reg_buf
+ offset
, buf
, 4);
6366 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
6370 static struct value
*
6371 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
6373 const int *reg_p
= baton
;
6374 return value_of_register (*reg_p
, frame
);
6377 static enum gdb_osabi
6378 arm_elf_osabi_sniffer (bfd
*abfd
)
6380 unsigned int elfosabi
;
6381 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
6383 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
6385 if (elfosabi
== ELFOSABI_ARM
)
6386 /* GNU tools use this value. Check note sections in this case,
6388 bfd_map_over_sections (abfd
,
6389 generic_elf_osabi_sniff_abi_tag_sections
,
6392 /* Anything else will be handled by the generic ELF sniffer. */
6397 /* Initialize the current architecture based on INFO. If possible,
6398 re-use an architecture from ARCHES, which is a list of
6399 architectures already created during this debugging session.
6401 Called e.g. at program startup, when reading a core file, and when
6402 reading a binary file. */
6404 static struct gdbarch
*
6405 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6407 struct gdbarch_tdep
*tdep
;
6408 struct gdbarch
*gdbarch
;
6409 struct gdbarch_list
*best_arch
;
6410 enum arm_abi_kind arm_abi
= arm_abi_global
;
6411 enum arm_float_model fp_model
= arm_fp_model
;
6412 struct tdesc_arch_data
*tdesc_data
= NULL
;
6414 int have_vfp_registers
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
6416 int have_fpa_registers
= 1;
6418 /* Check any target description for validity. */
6419 if (tdesc_has_registers (info
.target_desc
))
6421 /* For most registers we require GDB's default names; but also allow
6422 the numeric names for sp / lr / pc, as a convenience. */
6423 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
6424 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
6425 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
6427 const struct tdesc_feature
*feature
;
6430 feature
= tdesc_find_feature (info
.target_desc
,
6431 "org.gnu.gdb.arm.core");
6432 if (feature
== NULL
)
6435 tdesc_data
= tdesc_data_alloc ();
6438 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
6439 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
6440 arm_register_names
[i
]);
6441 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6444 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6447 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6450 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6451 ARM_PS_REGNUM
, "cpsr");
6455 tdesc_data_cleanup (tdesc_data
);
6459 feature
= tdesc_find_feature (info
.target_desc
,
6460 "org.gnu.gdb.arm.fpa");
6461 if (feature
!= NULL
)
6464 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
6465 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
6466 arm_register_names
[i
]);
6469 tdesc_data_cleanup (tdesc_data
);
6474 have_fpa_registers
= 0;
6476 feature
= tdesc_find_feature (info
.target_desc
,
6477 "org.gnu.gdb.xscale.iwmmxt");
6478 if (feature
!= NULL
)
6480 static const char *const iwmmxt_names
[] = {
6481 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
6482 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
6483 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
6484 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
6488 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
6490 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
6491 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
6493 /* Check for the control registers, but do not fail if they
6495 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
6496 tdesc_numbered_register (feature
, tdesc_data
, i
,
6497 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
6499 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
6501 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
6502 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
6506 tdesc_data_cleanup (tdesc_data
);
6511 /* If we have a VFP unit, check whether the single precision registers
6512 are present. If not, then we will synthesize them as pseudo
6514 feature
= tdesc_find_feature (info
.target_desc
,
6515 "org.gnu.gdb.arm.vfp");
6516 if (feature
!= NULL
)
6518 static const char *const vfp_double_names
[] = {
6519 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
6520 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
6521 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
6522 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
6525 /* Require the double precision registers. There must be either
6528 for (i
= 0; i
< 32; i
++)
6530 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6532 vfp_double_names
[i
]);
6537 if (!valid_p
&& i
!= 16)
6539 tdesc_data_cleanup (tdesc_data
);
6543 if (tdesc_unnumbered_register (feature
, "s0") == 0)
6544 have_vfp_pseudos
= 1;
6546 have_vfp_registers
= 1;
6548 /* If we have VFP, also check for NEON. The architecture allows
6549 NEON without VFP (integer vector operations only), but GDB
6550 does not support that. */
6551 feature
= tdesc_find_feature (info
.target_desc
,
6552 "org.gnu.gdb.arm.neon");
6553 if (feature
!= NULL
)
6555 /* NEON requires 32 double-precision registers. */
6558 tdesc_data_cleanup (tdesc_data
);
6562 /* If there are quad registers defined by the stub, use
6563 their type; otherwise (normally) provide them with
6564 the default type. */
6565 if (tdesc_unnumbered_register (feature
, "q0") == 0)
6566 have_neon_pseudos
= 1;
6573 /* If we have an object to base this architecture on, try to determine
6576 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
6578 int ei_osabi
, e_flags
;
6580 switch (bfd_get_flavour (info
.abfd
))
6582 case bfd_target_aout_flavour
:
6583 /* Assume it's an old APCS-style ABI. */
6584 arm_abi
= ARM_ABI_APCS
;
6587 case bfd_target_coff_flavour
:
6588 /* Assume it's an old APCS-style ABI. */
6590 arm_abi
= ARM_ABI_APCS
;
6593 case bfd_target_elf_flavour
:
6594 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
6595 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6597 if (ei_osabi
== ELFOSABI_ARM
)
6599 /* GNU tools used to use this value, but do not for EABI
6600 objects. There's nowhere to tag an EABI version
6601 anyway, so assume APCS. */
6602 arm_abi
= ARM_ABI_APCS
;
6604 else if (ei_osabi
== ELFOSABI_NONE
)
6606 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
6610 case EF_ARM_EABI_UNKNOWN
:
6611 /* Assume GNU tools. */
6612 arm_abi
= ARM_ABI_APCS
;
6615 case EF_ARM_EABI_VER4
:
6616 case EF_ARM_EABI_VER5
:
6617 arm_abi
= ARM_ABI_AAPCS
;
6618 /* EABI binaries default to VFP float ordering.
6619 They may also contain build attributes that can
6620 be used to identify if the VFP argument-passing
6622 if (fp_model
== ARM_FLOAT_AUTO
)
6625 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
6630 /* "The user intended FP parameter/result
6631 passing to conform to AAPCS, base
6633 fp_model
= ARM_FLOAT_SOFT_VFP
;
6636 /* "The user intended FP parameter/result
6637 passing to conform to AAPCS, VFP
6639 fp_model
= ARM_FLOAT_VFP
;
6642 /* "The user intended FP parameter/result
6643 passing to conform to tool chain-specific
6644 conventions" - we don't know any such
6645 conventions, so leave it as "auto". */
6648 /* Attribute value not mentioned in the
6649 October 2008 ABI, so leave it as
6654 fp_model
= ARM_FLOAT_SOFT_VFP
;
6660 /* Leave it as "auto". */
6661 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
6666 if (fp_model
== ARM_FLOAT_AUTO
)
6668 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6670 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
6673 /* Leave it as "auto". Strictly speaking this case
6674 means FPA, but almost nobody uses that now, and
6675 many toolchains fail to set the appropriate bits
6676 for the floating-point model they use. */
6678 case EF_ARM_SOFT_FLOAT
:
6679 fp_model
= ARM_FLOAT_SOFT_FPA
;
6681 case EF_ARM_VFP_FLOAT
:
6682 fp_model
= ARM_FLOAT_VFP
;
6684 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
6685 fp_model
= ARM_FLOAT_SOFT_VFP
;
6690 if (e_flags
& EF_ARM_BE8
)
6691 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
6696 /* Leave it as "auto". */
6701 /* If there is already a candidate, use it. */
6702 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
6704 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
6706 if (arm_abi
!= ARM_ABI_AUTO
6707 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
6710 if (fp_model
!= ARM_FLOAT_AUTO
6711 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
6714 /* There are various other properties in tdep that we do not
6715 need to check here: those derived from a target description,
6716 since gdbarches with a different target description are
6717 automatically disqualified. */
6719 /* Found a match. */
6723 if (best_arch
!= NULL
)
6725 if (tdesc_data
!= NULL
)
6726 tdesc_data_cleanup (tdesc_data
);
6727 return best_arch
->gdbarch
;
6730 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
6731 gdbarch
= gdbarch_alloc (&info
, tdep
);
6733 /* Record additional information about the architecture we are defining.
6734 These are gdbarch discriminators, like the OSABI. */
6735 tdep
->arm_abi
= arm_abi
;
6736 tdep
->fp_model
= fp_model
;
6737 tdep
->have_fpa_registers
= have_fpa_registers
;
6738 tdep
->have_vfp_registers
= have_vfp_registers
;
6739 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
6740 tdep
->have_neon_pseudos
= have_neon_pseudos
;
6741 tdep
->have_neon
= have_neon
;
6744 switch (info
.byte_order_for_code
)
6746 case BFD_ENDIAN_BIG
:
6747 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
6748 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
6749 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
6750 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
6754 case BFD_ENDIAN_LITTLE
:
6755 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
6756 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
6757 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
6758 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
6763 internal_error (__FILE__
, __LINE__
,
6764 _("arm_gdbarch_init: bad byte order for float format"));
6767 /* On ARM targets char defaults to unsigned. */
6768 set_gdbarch_char_signed (gdbarch
, 0);
6770 /* Note: for displaced stepping, this includes the breakpoint, and one word
6771 of additional scratch space. This setting isn't used for anything beside
6772 displaced stepping at present. */
6773 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
6775 /* This should be low enough for everything. */
6776 tdep
->lowest_pc
= 0x20;
6777 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
6779 /* The default, for both APCS and AAPCS, is to return small
6780 structures in registers. */
6781 tdep
->struct_return
= reg_struct_return
;
6783 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
6784 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
6786 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
6788 /* Frame handling. */
6789 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
6790 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
6791 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
6793 frame_base_set_default (gdbarch
, &arm_normal_base
);
6795 /* Address manipulation. */
6796 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
6797 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
6799 /* Advance PC across function entry code. */
6800 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
6802 /* Skip trampolines. */
6803 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
6805 /* The stack grows downward. */
6806 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6808 /* Breakpoint manipulation. */
6809 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
6810 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
6811 arm_remote_breakpoint_from_pc
);
6813 /* Information about registers, etc. */
6814 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
6815 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
6816 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
6817 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
6818 set_gdbarch_register_type (gdbarch
, arm_register_type
);
6820 /* This "info float" is FPA-specific. Use the generic version if we
6822 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
6823 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
6825 /* Internal <-> external register number maps. */
6826 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
6827 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
6829 set_gdbarch_register_name (gdbarch
, arm_register_name
);
6831 /* Returning results. */
6832 set_gdbarch_return_value (gdbarch
, arm_return_value
);
6835 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
6837 /* Minsymbol frobbing. */
6838 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
6839 set_gdbarch_coff_make_msymbol_special (gdbarch
,
6840 arm_coff_make_msymbol_special
);
6841 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
6843 /* Thumb-2 IT block support. */
6844 set_gdbarch_adjust_breakpoint_address (gdbarch
,
6845 arm_adjust_breakpoint_address
);
6847 /* Virtual tables. */
6848 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6850 /* Hook in the ABI-specific overrides, if they have been registered. */
6851 gdbarch_init_osabi (info
, gdbarch
);
6853 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
6855 /* Add some default predicates. */
6856 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
6857 dwarf2_append_unwinders (gdbarch
);
6858 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
6860 /* Now we have tuned the configuration, set a few final things,
6861 based on what the OS ABI has told us. */
6863 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
6864 binaries are always marked. */
6865 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
6866 tdep
->arm_abi
= ARM_ABI_APCS
;
6868 /* We used to default to FPA for generic ARM, but almost nobody
6869 uses that now, and we now provide a way for the user to force
6870 the model. So default to the most useful variant. */
6871 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
6872 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
6874 if (tdep
->jb_pc
>= 0)
6875 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
6877 /* Floating point sizes and format. */
6878 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
6879 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
6881 set_gdbarch_double_format
6882 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
6883 set_gdbarch_long_double_format
6884 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
6888 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
6889 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
6892 if (have_vfp_pseudos
)
6894 /* NOTE: These are the only pseudo registers used by
6895 the ARM target at the moment. If more are added, a
6896 little more care in numbering will be needed. */
6898 int num_pseudos
= 32;
6899 if (have_neon_pseudos
)
6901 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
6902 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
6903 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
6908 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
6910 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
6912 /* Override tdesc_register_type to adjust the types of VFP
6913 registers for NEON. */
6914 set_gdbarch_register_type (gdbarch
, arm_register_type
);
6917 /* Add standard register aliases. We add aliases even for those
6918 nanes which are used by the current architecture - it's simpler,
6919 and does no harm, since nothing ever lists user registers. */
6920 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
6921 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
6922 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
6928 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6930 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6935 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
6936 (unsigned long) tdep
->lowest_pc
);
6939 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
6942 _initialize_arm_tdep (void)
6944 struct ui_file
*stb
;
6946 struct cmd_list_element
*new_set
, *new_show
;
6947 const char *setname
;
6948 const char *setdesc
;
6949 const char *const *regnames
;
6951 static char *helptext
;
6952 char regdesc
[1024], *rdptr
= regdesc
;
6953 size_t rest
= sizeof (regdesc
);
6955 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
6957 arm_objfile_data_key
6958 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
6960 /* Register an ELF OS ABI sniffer for ARM binaries. */
6961 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
6962 bfd_target_elf_flavour
,
6963 arm_elf_osabi_sniffer
);
6965 /* Get the number of possible sets of register names defined in opcodes. */
6966 num_disassembly_options
= get_arm_regname_num_options ();
6968 /* Add root prefix command for all "set arm"/"show arm" commands. */
6969 add_prefix_cmd ("arm", no_class
, set_arm_command
,
6970 _("Various ARM-specific commands."),
6971 &setarmcmdlist
, "set arm ", 0, &setlist
);
6973 add_prefix_cmd ("arm", no_class
, show_arm_command
,
6974 _("Various ARM-specific commands."),
6975 &showarmcmdlist
, "show arm ", 0, &showlist
);
6977 /* Sync the opcode insn printer with our register viewer. */
6978 parse_arm_disassembler_option ("reg-names-std");
6980 /* Initialize the array that will be passed to
6981 add_setshow_enum_cmd(). */
6982 valid_disassembly_styles
6983 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
6984 for (i
= 0; i
< num_disassembly_options
; i
++)
6986 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
6987 valid_disassembly_styles
[i
] = setname
;
6988 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
6991 /* When we find the default names, tell the disassembler to use
6993 if (!strcmp (setname
, "std"))
6995 disassembly_style
= setname
;
6996 set_arm_regname_option (i
);
6999 /* Mark the end of valid options. */
7000 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
7002 /* Create the help text. */
7003 stb
= mem_fileopen ();
7004 fprintf_unfiltered (stb
, "%s%s%s",
7005 _("The valid values are:\n"),
7007 _("The default is \"std\"."));
7008 helptext
= ui_file_xstrdup (stb
, NULL
);
7009 ui_file_delete (stb
);
7011 add_setshow_enum_cmd("disassembler", no_class
,
7012 valid_disassembly_styles
, &disassembly_style
,
7013 _("Set the disassembly style."),
7014 _("Show the disassembly style."),
7016 set_disassembly_style_sfunc
,
7017 NULL
, /* FIXME: i18n: The disassembly style is \"%s\". */
7018 &setarmcmdlist
, &showarmcmdlist
);
7020 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
7021 _("Set usage of ARM 32-bit mode."),
7022 _("Show usage of ARM 32-bit mode."),
7023 _("When off, a 26-bit PC will be used."),
7025 NULL
, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
7026 &setarmcmdlist
, &showarmcmdlist
);
7028 /* Add a command to allow the user to force the FPU model. */
7029 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
7030 _("Set the floating point type."),
7031 _("Show the floating point type."),
7032 _("auto - Determine the FP typefrom the OS-ABI.\n\
7033 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
7034 fpa - FPA co-processor (GCC compiled).\n\
7035 softvfp - Software FP with pure-endian doubles.\n\
7036 vfp - VFP co-processor."),
7037 set_fp_model_sfunc
, show_fp_model
,
7038 &setarmcmdlist
, &showarmcmdlist
);
7040 /* Add a command to allow the user to force the ABI. */
7041 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
7044 NULL
, arm_set_abi
, arm_show_abi
,
7045 &setarmcmdlist
, &showarmcmdlist
);
7047 /* Add two commands to allow the user to force the assumed
7049 add_setshow_enum_cmd ("fallback-mode", class_support
,
7050 arm_mode_strings
, &arm_fallback_mode_string
,
7051 _("Set the mode assumed when symbols are unavailable."),
7052 _("Show the mode assumed when symbols are unavailable."),
7053 NULL
, NULL
, arm_show_fallback_mode
,
7054 &setarmcmdlist
, &showarmcmdlist
);
7055 add_setshow_enum_cmd ("force-mode", class_support
,
7056 arm_mode_strings
, &arm_force_mode_string
,
7057 _("Set the mode assumed even when symbols are available."),
7058 _("Show the mode assumed even when symbols are available."),
7059 NULL
, NULL
, arm_show_force_mode
,
7060 &setarmcmdlist
, &showarmcmdlist
);
7062 /* Debugging flag. */
7063 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
7064 _("Set ARM debugging."),
7065 _("Show ARM debugging."),
7066 _("When on, arm-specific debugging is enabled."),
7068 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
7069 &setdebuglist
, &showdebuglist
);