1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 #include <ctype.h> /* XXX for isupper () */
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register flavors. */
35 #include "arch-utils.h"
36 #include "solib-svr4.h"
41 #include "coff/internal.h"
44 /* Each OS has a different mechanism for accessing the various
45 registers stored in the sigcontext structure.
47 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
48 function pointer) which may be used to determine the addresses
49 of the various saved registers in the sigcontext structure.
51 For the ARM target, there are three parameters to this function.
52 The first is the pc value of the frame under consideration, the
53 second the stack pointer of this frame, and the last is the
54 register number to fetch.
56 If the tm.h file does not define this macro, then it's assumed that
57 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
60 When it comes time to multi-arching this code, see the identically
61 named machinery in ia64-tdep.c for an example of how it could be
62 done. It should not be necessary to modify the code below where
63 this macro is used. */
65 #ifdef SIGCONTEXT_REGISTER_ADDRESS
66 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
67 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
70 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
71 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
74 /* Macros for setting and testing a bit in a minimal symbol that marks
75 it as Thumb function. The MSB of the minimal symbol's "info" field
76 is used for this purpose. This field is already being used to store
77 the symbol size, so the assumption is that the symbol size cannot
80 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
81 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol.
82 MSYMBOL_SIZE Returns the size of the minimal symbol,
83 i.e. the "info" field with the "special" bit
86 #define MSYMBOL_SET_SPECIAL(msym) \
87 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
90 #define MSYMBOL_IS_SPECIAL(msym) \
91 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
93 #define MSYMBOL_SIZE(msym) \
94 ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
96 /* This table matches the indices assigned to enum arm_abi.
99 static const char * const arm_abi_names
[] =
102 "ARM EABI (version 1)",
103 "ARM EABI (version 2)",
113 /* Number of different reg name sets (options). */
114 static int num_flavor_options
;
116 /* We have more registers than the disassembler as gdb can print the value
117 of special registers as well.
118 The general register names are overwritten by whatever is being used by
119 the disassembler at the moment. We also adjust the case of cpsr and fps. */
121 /* Initial value: Register names used in ARM's ISA documentation. */
122 static char * arm_register_name_strings
[] =
123 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
124 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
125 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
126 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
127 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
128 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
129 "fps", "cpsr" }; /* 24 25 */
130 static char **arm_register_names
= arm_register_name_strings
;
132 /* Valid register name flavors. */
133 static const char **valid_flavors
;
135 /* Disassembly flavor to use. Default to "std" register names. */
136 static const char *disassembly_flavor
;
137 /* Index to that option in the opcodes table. */
138 static int current_option
;
140 /* This is used to keep the bfd arch_info in sync with the disassembly
142 static void set_disassembly_flavor_sfunc(char *, int,
143 struct cmd_list_element
*);
144 static void set_disassembly_flavor (void);
146 static void convert_from_extended (void *ptr
, void *dbl
);
148 /* Define other aspects of the stack frame. We keep the offsets of
149 all saved registers, 'cause we need 'em a lot! We also keep the
150 current size of the stack frame, and the offset of the frame
151 pointer from the stack pointer (for frameless functions, and when
152 we're still in the prologue of a function with a frame). */
154 struct frame_extra_info
161 /* Addresses for calling Thumb functions have the bit 0 set.
162 Here are some macros to test, set, or clear bit 0 of addresses. */
163 #define IS_THUMB_ADDR(addr) ((addr) & 1)
164 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
165 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
168 arm_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*thisframe
)
170 return (chain
!= 0 && (FRAME_SAVED_PC (thisframe
) >= LOWEST_PC
));
173 /* Set to true if the 32-bit mode is in use. */
177 /* Flag set by arm_fix_call_dummy that tells whether the target
178 function is a Thumb function. This flag is checked by
179 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
180 its use in valops.c) to pass the function address as an additional
183 static int target_is_thumb
;
185 /* Flag set by arm_fix_call_dummy that tells whether the calling
186 function is a Thumb function. This flag is checked by
187 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
189 static int caller_is_thumb
;
191 /* Determine if the program counter specified in MEMADDR is in a Thumb
195 arm_pc_is_thumb (CORE_ADDR memaddr
)
197 struct minimal_symbol
*sym
;
199 /* If bit 0 of the address is set, assume this is a Thumb address. */
200 if (IS_THUMB_ADDR (memaddr
))
203 /* Thumb functions have a "special" bit set in minimal symbols. */
204 sym
= lookup_minimal_symbol_by_pc (memaddr
);
207 return (MSYMBOL_IS_SPECIAL (sym
));
215 /* Determine if the program counter specified in MEMADDR is in a call
216 dummy being called from a Thumb function. */
219 arm_pc_is_thumb_dummy (CORE_ADDR memaddr
)
221 CORE_ADDR sp
= read_sp ();
223 /* FIXME: Until we switch for the new call dummy macros, this heuristic
224 is the best we can do. We are trying to determine if the pc is on
225 the stack, which (hopefully) will only happen in a call dummy.
226 We hope the current stack pointer is not so far alway from the dummy
227 frame location (true if we have not pushed large data structures or
228 gone too many levels deep) and that our 1024 is not enough to consider
229 code regions as part of the stack (true for most practical purposes). */
230 if (PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 1024))
231 return caller_is_thumb
;
236 /* Remove useless bits from addresses in a running program. */
238 arm_addr_bits_remove (CORE_ADDR val
)
240 if (arm_pc_is_thumb (val
))
241 return (val
& (arm_apcs_32
? 0xfffffffe : 0x03fffffe));
243 return (val
& (arm_apcs_32
? 0xfffffffc : 0x03fffffc));
246 /* When reading symbols, we need to zap the low bit of the address,
247 which may be set to 1 for Thumb functions. */
249 arm_smash_text_address (CORE_ADDR val
)
254 /* Immediately after a function call, return the saved pc. Can't
255 always go through the frames for this because on some machines the
256 new frame is not set up until the new function executes some
260 arm_saved_pc_after_call (struct frame_info
*frame
)
262 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM
));
265 /* Determine whether the function invocation represented by FI has a
266 frame on the stack associated with it. If it does return zero,
267 otherwise return 1. */
270 arm_frameless_function_invocation (struct frame_info
*fi
)
272 CORE_ADDR func_start
, after_prologue
;
275 /* Sometimes we have functions that do a little setup (like saving the
276 vN registers with the stmdb instruction, but DO NOT set up a frame.
277 The symbol table will report this as a prologue. However, it is
278 important not to try to parse these partial frames as frames, or we
279 will get really confused.
281 So I will demand 3 instructions between the start & end of the
282 prologue before I call it a real prologue, i.e. at least
287 func_start
= (get_pc_function_start ((fi
)->pc
) + FUNCTION_START_OFFSET
);
288 after_prologue
= SKIP_PROLOGUE (func_start
);
290 /* There are some frameless functions whose first two instructions
291 follow the standard APCS form, in which case after_prologue will
292 be func_start + 8. */
294 frameless
= (after_prologue
< func_start
+ 12);
298 /* The address of the arguments in the frame. */
300 arm_frame_args_address (struct frame_info
*fi
)
305 /* The address of the local variables in the frame. */
307 arm_frame_locals_address (struct frame_info
*fi
)
312 /* The number of arguments being passed in the frame. */
314 arm_frame_num_args (struct frame_info
*fi
)
316 /* We have no way of knowing. */
320 /* A typical Thumb prologue looks like this:
324 Sometimes the latter instruction may be replaced by:
332 or, on tpcs, like this:
339 There is always one instruction of three classes:
344 When we have found at least one of each class we are done with the prolog.
345 Note that the "sub sp, #NN" before the push does not count.
349 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
351 CORE_ADDR current_pc
;
353 bit 0 - push { rlist }
354 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
355 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
359 for (current_pc
= pc
;
360 current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40;
363 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
365 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
367 findmask
|= 1; /* push found */
369 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
372 if ((findmask
& 1) == 0) /* before push ? */
375 findmask
|= 4; /* add/sub sp found */
377 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
379 findmask
|= 2; /* setting of r7 found */
381 else if (insn
== 0x466f) /* mov r7, sp */
383 findmask
|= 2; /* setting of r7 found */
385 else if (findmask
== (4+2+1))
387 /* We have found one of each type of prologue instruction */
391 /* Something in the prolog that we don't care about or some
392 instruction from outside the prolog scheduled here for
400 /* Advance the PC across any function entry prologue instructions to
401 reach some "real" code.
403 The APCS (ARM Procedure Call Standard) defines the following
407 [stmfd sp!, {a1,a2,a3,a4}]
408 stmfd sp!, {...,fp,ip,lr,pc}
409 [stfe f7, [sp, #-12]!]
410 [stfe f6, [sp, #-12]!]
411 [stfe f5, [sp, #-12]!]
412 [stfe f4, [sp, #-12]!]
413 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
416 arm_skip_prologue (CORE_ADDR pc
)
420 CORE_ADDR func_addr
, func_end
= 0;
422 struct symtab_and_line sal
;
424 /* If we're in a dummy frame, don't even try to skip the prologue. */
425 if (USE_GENERIC_DUMMY_FRAMES
426 && PC_IN_CALL_DUMMY (pc
, 0, 0))
429 /* See what the symbol table says. */
431 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
435 /* Found a function. */
436 sym
= lookup_symbol (func_name
, NULL
, VAR_NAMESPACE
, NULL
, NULL
);
437 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
439 /* Don't use this trick for assembly source files. */
440 sal
= find_pc_line (func_addr
, 0);
441 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
446 /* Check if this is Thumb code. */
447 if (arm_pc_is_thumb (pc
))
448 return thumb_skip_prologue (pc
, func_end
);
450 /* Can't find the prologue end in the symbol table, try it the hard way
451 by disassembling the instructions. */
453 /* Like arm_scan_prologue, stop no later than pc + 64. */
454 if (func_end
== 0 || func_end
> pc
+ 64)
457 for (skip_pc
= pc
; skip_pc
< func_end
; skip_pc
+= 4)
459 inst
= read_memory_integer (skip_pc
, 4);
461 /* "mov ip, sp" is no longer a required part of the prologue. */
462 if (inst
== 0xe1a0c00d) /* mov ip, sp */
465 /* Some prologues begin with "str lr, [sp, #-4]!". */
466 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
469 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
472 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
475 /* Any insns after this point may float into the code, if it makes
476 for better instruction scheduling, so we skip them only if we
477 find them, but still consider the function to be frame-ful. */
479 /* We may have either one sfmfd instruction here, or several stfe
480 insns, depending on the version of floating point code we
482 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
485 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
488 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
491 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
494 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
495 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
496 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
499 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
500 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
501 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
504 /* Un-recognized instruction; stop scanning. */
508 return skip_pc
; /* End of prologue */
512 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
513 This function decodes a Thumb function prologue to determine:
514 1) the size of the stack frame
515 2) which registers are saved on it
516 3) the offsets of saved regs
517 4) the offset from the stack pointer to the frame pointer
518 This information is stored in the "extra" fields of the frame_info.
520 A typical Thumb function prologue would create this stack frame
521 (offsets relative to FP)
522 old SP -> 24 stack parameters
525 R7 -> 0 local variables (16 bytes)
526 SP -> -12 additional stack space (12 bytes)
527 The frame size would thus be 36 bytes, and the frame offset would be
528 12 bytes. The frame register is R7.
530 The comments for thumb_skip_prolog() describe the algorithm we use
531 to detect the end of the prolog. */
535 thumb_scan_prologue (struct frame_info
*fi
)
537 CORE_ADDR prologue_start
;
538 CORE_ADDR prologue_end
;
539 CORE_ADDR current_pc
;
540 /* Which register has been copied to register n? */
543 bit 0 - push { rlist }
544 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
545 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
550 /* Don't try to scan dummy frames. */
551 if (USE_GENERIC_DUMMY_FRAMES
553 && PC_IN_CALL_DUMMY (fi
->pc
, 0, 0))
556 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
558 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
560 if (sal
.line
== 0) /* no line info, use current PC */
561 prologue_end
= fi
->pc
;
562 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
563 prologue_end
= sal
.end
; /* (probably means no prologue) */
566 /* We're in the boondocks: allow for
567 16 pushes, an add, and "mv fp,sp". */
568 prologue_end
= prologue_start
+ 40;
570 prologue_end
= min (prologue_end
, fi
->pc
);
572 /* Initialize the saved register map. When register H is copied to
573 register L, we will put H in saved_reg[L]. */
574 for (i
= 0; i
< 16; i
++)
577 /* Search the prologue looking for instructions that set up the
578 frame pointer, adjust the stack pointer, and save registers.
579 Do this until all basic prolog instructions are found. */
581 fi
->extra_info
->framesize
= 0;
582 for (current_pc
= prologue_start
;
583 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
590 insn
= read_memory_unsigned_integer (current_pc
, 2);
592 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
595 findmask
|= 1; /* push found */
596 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
597 whether to save LR (R14). */
598 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
600 /* Calculate offsets of saved R0-R7 and LR. */
601 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
602 if (mask
& (1 << regno
))
604 fi
->extra_info
->framesize
+= 4;
605 fi
->saved_regs
[saved_reg
[regno
]] =
606 -(fi
->extra_info
->framesize
);
607 /* Reset saved register map. */
608 saved_reg
[regno
] = regno
;
611 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
614 if ((findmask
& 1) == 0) /* before push? */
617 findmask
|= 4; /* add/sub sp found */
619 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
620 if (insn
& 0x80) /* is it signed? (==subtracting) */
622 fi
->extra_info
->frameoffset
+= offset
;
625 fi
->extra_info
->framesize
-= offset
;
627 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
629 findmask
|= 2; /* setting of r7 found */
630 fi
->extra_info
->framereg
= THUMB_FP_REGNUM
;
631 /* get scaled offset */
632 fi
->extra_info
->frameoffset
= (insn
& 0xff) << 2;
634 else if (insn
== 0x466f) /* mov r7, sp */
636 findmask
|= 2; /* setting of r7 found */
637 fi
->extra_info
->framereg
= THUMB_FP_REGNUM
;
638 fi
->extra_info
->frameoffset
= 0;
639 saved_reg
[THUMB_FP_REGNUM
] = ARM_SP_REGNUM
;
641 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
643 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
644 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
645 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
648 /* Something in the prolog that we don't care about or some
649 instruction from outside the prolog scheduled here for
655 /* Check if prologue for this frame's PC has already been scanned. If
656 it has, copy the relevant information about that prologue and
657 return non-zero. Otherwise do not copy anything and return zero.
659 The information saved in the cache includes:
660 * the frame register number;
661 * the size of the stack frame;
662 * the offsets of saved regs (relative to the old SP); and
663 * the offset from the stack pointer to the frame pointer
665 The cache contains only one entry, since this is adequate for the
666 typical sequence of prologue scan requests we get. When performing
667 a backtrace, GDB will usually ask to scan the same function twice
668 in a row (once to get the frame chain, and once to fill in the
669 extra frame information). */
671 static struct frame_info prologue_cache
;
674 check_prologue_cache (struct frame_info
*fi
)
678 if (fi
->pc
== prologue_cache
.pc
)
680 fi
->extra_info
->framereg
= prologue_cache
.extra_info
->framereg
;
681 fi
->extra_info
->framesize
= prologue_cache
.extra_info
->framesize
;
682 fi
->extra_info
->frameoffset
= prologue_cache
.extra_info
->frameoffset
;
683 for (i
= 0; i
< NUM_REGS
+ NUM_PSEUDO_REGS
; i
++)
684 fi
->saved_regs
[i
] = prologue_cache
.saved_regs
[i
];
692 /* Copy the prologue information from fi to the prologue cache. */
695 save_prologue_cache (struct frame_info
*fi
)
699 prologue_cache
.pc
= fi
->pc
;
700 prologue_cache
.extra_info
->framereg
= fi
->extra_info
->framereg
;
701 prologue_cache
.extra_info
->framesize
= fi
->extra_info
->framesize
;
702 prologue_cache
.extra_info
->frameoffset
= fi
->extra_info
->frameoffset
;
704 for (i
= 0; i
< NUM_REGS
+ NUM_PSEUDO_REGS
; i
++)
705 prologue_cache
.saved_regs
[i
] = fi
->saved_regs
[i
];
709 /* This function decodes an ARM function prologue to determine:
710 1) the size of the stack frame
711 2) which registers are saved on it
712 3) the offsets of saved regs
713 4) the offset from the stack pointer to the frame pointer
714 This information is stored in the "extra" fields of the frame_info.
716 There are two basic forms for the ARM prologue. The fixed argument
717 function call will look like:
720 stmfd sp!, {fp, ip, lr, pc}
724 Which would create this stack frame (offsets relative to FP):
725 IP -> 4 (caller's stack)
726 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
727 -4 LR (return address in caller)
728 -8 IP (copy of caller's SP)
730 SP -> -28 Local variables
732 The frame size would thus be 32 bytes, and the frame offset would be
733 28 bytes. The stmfd call can also save any of the vN registers it
734 plans to use, which increases the frame size accordingly.
736 Note: The stored PC is 8 off of the STMFD instruction that stored it
737 because the ARM Store instructions always store PC + 8 when you read
740 A variable argument function call will look like:
743 stmfd sp!, {a1, a2, a3, a4}
744 stmfd sp!, {fp, ip, lr, pc}
747 Which would create this stack frame (offsets relative to FP):
748 IP -> 20 (caller's stack)
753 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
754 -4 LR (return address in caller)
755 -8 IP (copy of caller's SP)
757 SP -> -28 Local variables
759 The frame size would thus be 48 bytes, and the frame offset would be
762 There is another potential complication, which is that the optimizer
763 will try to separate the store of fp in the "stmfd" instruction from
764 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
765 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
767 Also, note, the original version of the ARM toolchain claimed that there
770 instruction at the end of the prologue. I have never seen GCC produce
771 this, and the ARM docs don't mention it. We still test for it below in
777 arm_scan_prologue (struct frame_info
*fi
)
779 int regno
, sp_offset
, fp_offset
;
780 LONGEST return_value
;
781 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
783 /* Check if this function is already in the cache of frame information. */
784 if (check_prologue_cache (fi
))
787 /* Assume there is no frame until proven otherwise. */
788 fi
->extra_info
->framereg
= ARM_SP_REGNUM
;
789 fi
->extra_info
->framesize
= 0;
790 fi
->extra_info
->frameoffset
= 0;
792 /* Check for Thumb prologue. */
793 if (arm_pc_is_thumb (fi
->pc
))
795 thumb_scan_prologue (fi
);
796 save_prologue_cache (fi
);
800 /* Find the function prologue. If we can't find the function in
801 the symbol table, peek in the stack frame to find the PC. */
802 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
804 /* One way to find the end of the prologue (which works well
805 for unoptimized code) is to do the following:
807 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
810 prologue_end = fi->pc;
811 else if (sal.end < prologue_end)
812 prologue_end = sal.end;
814 This mechanism is very accurate so long as the optimizer
815 doesn't move any instructions from the function body into the
816 prologue. If this happens, sal.end will be the last
817 instruction in the first hunk of prologue code just before
818 the first instruction that the scheduler has moved from
819 the body to the prologue.
821 In order to make sure that we scan all of the prologue
822 instructions, we use a slightly less accurate mechanism which
823 may scan more than necessary. To help compensate for this
824 lack of accuracy, the prologue scanning loop below contains
825 several clauses which'll cause the loop to terminate early if
826 an implausible prologue instruction is encountered.
832 is a suitable endpoint since it accounts for the largest
833 possible prologue plus up to five instructions inserted by
836 if (prologue_end
> prologue_start
+ 64)
838 prologue_end
= prologue_start
+ 64; /* See above. */
843 /* Get address of the stmfd in the prologue of the callee;
844 the saved PC is the address of the stmfd + 8. */
845 if (!safe_read_memory_integer (fi
->frame
, 4, &return_value
))
849 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
850 prologue_end
= prologue_start
+ 64; /* See above. */
854 /* Now search the prologue looking for instructions that set up the
855 frame pointer, adjust the stack pointer, and save registers.
857 Be careful, however, and if it doesn't look like a prologue,
858 don't try to scan it. If, for instance, a frameless function
859 begins with stmfd sp!, then we will tell ourselves there is
860 a frame, which will confuse stack traceback, as well as "finish"
861 and other operations that rely on a knowledge of the stack
864 In the APCS, the prologue should start with "mov ip, sp" so
865 if we don't see this as the first insn, we will stop.
867 [Note: This doesn't seem to be true any longer, so it's now an
868 optional part of the prologue. - Kevin Buettner, 2001-11-20]
870 [Note further: The "mov ip,sp" only seems to be missing in
871 frameless functions at optimization level "-O2" or above,
872 in which case it is often (but not always) replaced by
873 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
875 sp_offset
= fp_offset
= 0;
877 for (current_pc
= prologue_start
;
878 current_pc
< prologue_end
;
881 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
883 if (insn
== 0xe1a0c00d) /* mov ip, sp */
887 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
889 /* Function is frameless: extra_info defaults OK? */
892 else if ((insn
& 0xffff0000) == 0xe92d0000)
893 /* stmfd sp!, {..., fp, ip, lr, pc}
895 stmfd sp!, {a1, a2, a3, a4} */
897 int mask
= insn
& 0xffff;
899 /* Calculate offsets of saved registers. */
900 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
901 if (mask
& (1 << regno
))
904 fi
->saved_regs
[regno
] = sp_offset
;
907 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
908 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
909 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
911 /* No need to add this to saved_regs -- it's just an arg reg. */
914 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
915 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
916 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
918 /* No need to add this to saved_regs -- it's just an arg reg. */
921 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
923 unsigned imm
= insn
& 0xff; /* immediate value */
924 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
925 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
927 fi
->extra_info
->framereg
= ARM_FP_REGNUM
;
929 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
931 unsigned imm
= insn
& 0xff; /* immediate value */
932 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
933 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
936 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
939 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
940 fi
->saved_regs
[regno
] = sp_offset
;
942 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
945 unsigned int fp_start_reg
, fp_bound_reg
;
947 if ((insn
& 0x800) == 0x800) /* N0 is set */
949 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
956 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
962 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
963 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
964 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
967 fi
->saved_regs
[fp_start_reg
++] = sp_offset
;
970 else if ((insn
& 0xf0000000) != 0xe0000000)
971 break; /* Condition not true, exit early */
972 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
973 break; /* Don't scan past a block load */
975 /* The optimizer might shove anything into the prologue,
976 so we just skip what we don't recognize. */
980 /* The frame size is just the negative of the offset (from the
981 original SP) of the last thing thing we pushed on the stack.
982 The frame offset is [new FP] - [new SP]. */
983 fi
->extra_info
->framesize
= -sp_offset
;
984 if (fi
->extra_info
->framereg
== ARM_FP_REGNUM
)
985 fi
->extra_info
->frameoffset
= fp_offset
- sp_offset
;
987 fi
->extra_info
->frameoffset
= 0;
989 save_prologue_cache (fi
);
992 /* Find REGNUM on the stack. Otherwise, it's in an active register.
993 One thing we might want to do here is to check REGNUM against the
994 clobber mask, and somehow flag it as invalid if it isn't saved on
995 the stack somewhere. This would provide a graceful failure mode
996 when trying to get the value of caller-saves registers for an inner
1000 arm_find_callers_reg (struct frame_info
*fi
, int regnum
)
1002 /* NOTE: cagney/2002-05-03: This function really shouldn't be
1003 needed. Instead the (still being written) register unwind
1004 function could be called directly. */
1005 for (; fi
; fi
= fi
->next
)
1007 if (USE_GENERIC_DUMMY_FRAMES
1008 && PC_IN_CALL_DUMMY (fi
->pc
, 0, 0))
1010 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
1012 else if (fi
->saved_regs
[regnum
] != 0)
1014 /* NOTE: cagney/2002-05-03: This would normally need to
1015 handle ARM_SP_REGNUM as a special case as, according to
1016 the frame.h comments, saved_regs[SP_REGNUM] contains the
1017 SP value not its address. It appears that the ARM isn't
1018 doing this though. */
1019 return read_memory_integer (fi
->saved_regs
[regnum
],
1020 REGISTER_RAW_SIZE (regnum
));
1023 return read_register (regnum
);
1025 /* Function: frame_chain Given a GDB frame, determine the address of
1026 the calling function's frame. This will be used to create a new
1027 GDB frame struct, and then INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC
1028 will be called for the new frame. For ARM, we save the frame size
1029 when we initialize the frame_info. */
1032 arm_frame_chain (struct frame_info
*fi
)
1034 CORE_ADDR caller_pc
;
1035 int framereg
= fi
->extra_info
->framereg
;
1037 if (USE_GENERIC_DUMMY_FRAMES
1038 && PC_IN_CALL_DUMMY (fi
->pc
, 0, 0))
1039 /* A generic call dummy's frame is the same as caller's. */
1042 if (fi
->pc
< LOWEST_PC
)
1045 /* If the caller is the startup code, we're at the end of the chain. */
1046 caller_pc
= FRAME_SAVED_PC (fi
);
1048 /* If the caller is Thumb and the caller is ARM, or vice versa,
1049 the frame register of the caller is different from ours.
1050 So we must scan the prologue of the caller to determine its
1051 frame register number. */
1052 /* XXX Fixme, we should try to do this without creating a temporary
1054 if (arm_pc_is_thumb (caller_pc
) != arm_pc_is_thumb (fi
->pc
))
1056 struct frame_info caller_fi
;
1057 struct cleanup
*old_chain
;
1059 /* Create a temporary frame suitable for scanning the caller's
1061 memset (&caller_fi
, 0, sizeof (caller_fi
));
1062 caller_fi
.extra_info
= (struct frame_extra_info
*)
1063 xcalloc (1, sizeof (struct frame_extra_info
));
1064 old_chain
= make_cleanup (xfree
, caller_fi
.extra_info
);
1065 caller_fi
.saved_regs
= (CORE_ADDR
*)
1066 xcalloc (1, SIZEOF_FRAME_SAVED_REGS
);
1067 make_cleanup (xfree
, caller_fi
.saved_regs
);
1069 /* Now, scan the prologue and obtain the frame register. */
1070 caller_fi
.pc
= caller_pc
;
1071 arm_scan_prologue (&caller_fi
);
1072 framereg
= caller_fi
.extra_info
->framereg
;
1074 /* Deallocate the storage associated with the temporary frame
1076 do_cleanups (old_chain
);
1079 /* If the caller used a frame register, return its value.
1080 Otherwise, return the caller's stack pointer. */
1081 if (framereg
== ARM_FP_REGNUM
|| framereg
== THUMB_FP_REGNUM
)
1082 return arm_find_callers_reg (fi
, framereg
);
1084 return fi
->frame
+ fi
->extra_info
->framesize
;
1087 /* This function actually figures out the frame address for a given pc
1088 and sp. This is tricky because we sometimes don't use an explicit
1089 frame pointer, and the previous stack pointer isn't necessarily
1090 recorded on the stack. The only reliable way to get this info is
1091 to examine the prologue. FROMLEAF is a little confusing, it means
1092 this is the next frame up the chain AFTER a frameless function. If
1093 this is true, then the frame value for this frame is still in the
1097 arm_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1102 if (fi
->saved_regs
== NULL
)
1103 frame_saved_regs_zalloc (fi
);
1105 fi
->extra_info
= (struct frame_extra_info
*)
1106 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1108 fi
->extra_info
->framesize
= 0;
1109 fi
->extra_info
->frameoffset
= 0;
1110 fi
->extra_info
->framereg
= 0;
1113 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1115 memset (fi
->saved_regs
, '\000', sizeof fi
->saved_regs
);
1117 /* Compute stack pointer for this frame. We use this value for both
1118 the sigtramp and call dummy cases. */
1121 else if (USE_GENERIC_DUMMY_FRAMES
1122 && PC_IN_CALL_DUMMY (fi
->next
->pc
, 0, 0))
1123 /* For generic dummy frames, pull the value direct from the frame.
1124 Having an unwind function to do this would be nice. */
1125 sp
= generic_read_register_dummy (fi
->next
->pc
, fi
->next
->frame
,
1128 sp
= (fi
->next
->frame
- fi
->next
->extra_info
->frameoffset
1129 + fi
->next
->extra_info
->framesize
);
1131 /* Determine whether or not we're in a sigtramp frame.
1132 Unfortunately, it isn't sufficient to test
1133 fi->signal_handler_caller because this value is sometimes set
1134 after invoking INIT_EXTRA_FRAME_INFO. So we test *both*
1135 fi->signal_handler_caller and PC_IN_SIGTRAMP to determine if we
1136 need to use the sigcontext addresses for the saved registers.
1138 Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare
1139 against the name of the function, the code below will have to be
1140 changed to first fetch the name of the function and then pass
1141 this name to PC_IN_SIGTRAMP. */
1143 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1144 && (fi
->signal_handler_caller
|| PC_IN_SIGTRAMP (fi
->pc
, (char *)0)))
1146 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1147 fi
->saved_regs
[reg
] = SIGCONTEXT_REGISTER_ADDRESS (sp
, fi
->pc
, reg
);
1149 /* FIXME: What about thumb mode? */
1150 fi
->extra_info
->framereg
= ARM_SP_REGNUM
;
1152 read_memory_integer (fi
->saved_regs
[fi
->extra_info
->framereg
],
1153 REGISTER_RAW_SIZE (fi
->extra_info
->framereg
));
1154 fi
->extra_info
->framesize
= 0;
1155 fi
->extra_info
->frameoffset
= 0;
1158 else if (PC_IN_CALL_DUMMY (fi
->pc
, sp
, fi
->frame
))
1161 CORE_ADDR callers_sp
;
1163 /* Set rp point at the high end of the saved registers. */
1164 rp
= fi
->frame
- REGISTER_SIZE
;
1166 /* Fill in addresses of saved registers. */
1167 fi
->saved_regs
[ARM_PS_REGNUM
] = rp
;
1168 rp
-= REGISTER_RAW_SIZE (ARM_PS_REGNUM
);
1169 for (reg
= ARM_PC_REGNUM
; reg
>= 0; reg
--)
1171 fi
->saved_regs
[reg
] = rp
;
1172 rp
-= REGISTER_RAW_SIZE (reg
);
1175 callers_sp
= read_memory_integer (fi
->saved_regs
[ARM_SP_REGNUM
],
1176 REGISTER_RAW_SIZE (ARM_SP_REGNUM
));
1177 fi
->extra_info
->framereg
= ARM_FP_REGNUM
;
1178 fi
->extra_info
->framesize
= callers_sp
- sp
;
1179 fi
->extra_info
->frameoffset
= fi
->frame
- sp
;
1183 arm_scan_prologue (fi
);
1186 /* This is the innermost frame? */
1187 fi
->frame
= read_register (fi
->extra_info
->framereg
);
1188 else if (USE_GENERIC_DUMMY_FRAMES
1189 && PC_IN_CALL_DUMMY (fi
->next
->pc
, 0, 0))
1190 /* Next inner most frame is a dummy, just grab its frame.
1191 Dummy frames always have the same FP as their caller. */
1192 fi
->frame
= fi
->next
->frame
;
1193 else if (fi
->extra_info
->framereg
== ARM_FP_REGNUM
1194 || fi
->extra_info
->framereg
== THUMB_FP_REGNUM
)
1196 /* not the innermost frame */
1197 /* If we have an FP, the callee saved it. */
1198 if (fi
->next
->saved_regs
[fi
->extra_info
->framereg
] != 0)
1200 read_memory_integer (fi
->next
1201 ->saved_regs
[fi
->extra_info
->framereg
], 4);
1203 /* If we were called by a frameless fn. then our frame is
1204 still in the frame pointer register on the board... */
1205 fi
->frame
= read_fp ();
1208 /* Calculate actual addresses of saved registers using offsets
1209 determined by arm_scan_prologue. */
1210 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1211 if (fi
->saved_regs
[reg
] != 0)
1212 fi
->saved_regs
[reg
] += (fi
->frame
+ fi
->extra_info
->framesize
1213 - fi
->extra_info
->frameoffset
);
1218 /* Find the caller of this frame. We do this by seeing if ARM_LR_REGNUM
1219 is saved in the stack anywhere, otherwise we get it from the
1222 The old definition of this function was a macro:
1223 #define FRAME_SAVED_PC(FRAME) \
1224 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1227 arm_frame_saved_pc (struct frame_info
*fi
)
1229 /* If a dummy frame, pull the PC out of the frame's register buffer. */
1230 if (USE_GENERIC_DUMMY_FRAMES
1231 && PC_IN_CALL_DUMMY (fi
->pc
, 0, 0))
1232 return generic_read_register_dummy (fi
->pc
, fi
->frame
, ARM_PC_REGNUM
);
1234 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
- fi
->extra_info
->frameoffset
,
1237 return read_memory_integer (fi
->saved_regs
[ARM_PC_REGNUM
],
1238 REGISTER_RAW_SIZE (ARM_PC_REGNUM
));
1242 CORE_ADDR pc
= arm_find_callers_reg (fi
, ARM_LR_REGNUM
);
1243 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1247 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1248 Examine the Program Status Register to decide which state we're in. */
1253 if (read_register (ARM_PS_REGNUM
) & 0x20) /* Bit 5 is Thumb state bit */
1254 return read_register (THUMB_FP_REGNUM
); /* R7 if Thumb */
1256 return read_register (ARM_FP_REGNUM
); /* R11 if ARM */
1259 /* Store into a struct frame_saved_regs the addresses of the saved
1260 registers of frame described by FRAME_INFO. This includes special
1261 registers such as PC and FP saved in special ways in the stack
1262 frame. SP is even more special: the address we return for it IS
1263 the sp for the next frame. */
1266 arm_frame_init_saved_regs (struct frame_info
*fip
)
1269 if (fip
->saved_regs
)
1272 arm_init_extra_frame_info (0, fip
);
1275 /* Set the return address for a generic dummy frame. ARM uses the
1279 arm_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
1281 write_register (ARM_LR_REGNUM
, CALL_DUMMY_ADDRESS ());
1285 /* Push an empty stack frame, to record the current PC, etc. */
1288 arm_push_dummy_frame (void)
1290 CORE_ADDR old_sp
= read_register (ARM_SP_REGNUM
);
1291 CORE_ADDR sp
= old_sp
;
1292 CORE_ADDR fp
, prologue_start
;
1295 /* Push the two dummy prologue instructions in reverse order,
1296 so that they'll be in the correct low-to-high order in memory. */
1297 /* sub fp, ip, #4 */
1298 sp
= push_word (sp
, 0xe24cb004);
1299 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1300 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
1302 /* Push a pointer to the dummy prologue + 12, because when stm
1303 instruction stores the PC, it stores the address of the stm
1304 instruction itself plus 12. */
1305 fp
= sp
= push_word (sp
, prologue_start
+ 12);
1307 /* Push the processor status. */
1308 sp
= push_word (sp
, read_register (ARM_PS_REGNUM
));
1310 /* Push all 16 registers starting with r15. */
1311 for (regnum
= ARM_PC_REGNUM
; regnum
>= 0; regnum
--)
1312 sp
= push_word (sp
, read_register (regnum
));
1314 /* Update fp (for both Thumb and ARM) and sp. */
1315 write_register (ARM_FP_REGNUM
, fp
);
1316 write_register (THUMB_FP_REGNUM
, fp
);
1317 write_register (ARM_SP_REGNUM
, sp
);
1320 /* CALL_DUMMY_WORDS:
1321 This sequence of words is the instructions
1327 Note this is 12 bytes. */
1329 static LONGEST arm_call_dummy_words
[] =
1331 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
1334 /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy
1335 breakpoint to the proper address in the call dummy, so that
1336 `finish' after a stop in a call dummy works.
1338 FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an
1339 optimal solution, but the call to arm_fix_call_dummy is immediately
1340 followed by a call to run_stack_dummy, which is the only function
1341 where call_dummy_breakpoint_offset is actually used. */
1345 arm_set_call_dummy_breakpoint_offset (void)
1347 if (caller_is_thumb
)
1348 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch
, 4);
1350 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch
, 8);
1353 /* Fix up the call dummy, based on whether the processor is currently
1354 in Thumb or ARM mode, and whether the target function is Thumb or
1355 ARM. There are three different situations requiring three
1358 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1359 been copied into the dummy parameter to this function.
1360 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1361 "mov pc,r4" instruction patched to be a "bx r4" instead.
1362 * Thumb calling anything: uses the Thumb dummy defined below, which
1363 works for calling both ARM and Thumb functions.
1365 All three call dummies expect to receive the target function
1366 address in R4, with the low bit set if it's a Thumb function. */
1369 arm_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
1370 struct value
**args
, struct type
*type
, int gcc_p
)
1372 static short thumb_dummy
[4] =
1374 0xf000, 0xf801, /* bl label */
1375 0xdf18, /* swi 24 */
1376 0x4720, /* label: bx r4 */
1378 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
1380 /* Set flag indicating whether the current PC is in a Thumb function. */
1381 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
1382 arm_set_call_dummy_breakpoint_offset ();
1384 /* If the target function is Thumb, set the low bit of the function
1385 address. And if the CPU is currently in ARM mode, patch the
1386 second instruction of call dummy to use a BX instruction to
1387 switch to Thumb mode. */
1388 target_is_thumb
= arm_pc_is_thumb (fun
);
1389 if (target_is_thumb
)
1392 if (!caller_is_thumb
)
1393 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
1396 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1397 instead of the ARM one that's already been copied. This will
1398 work for both Thumb and ARM target functions. */
1399 if (caller_is_thumb
)
1403 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
1405 for (i
= 0; i
< len
; i
++)
1407 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1408 p
+= sizeof (thumb_dummy
[0]);
1412 /* Put the target address in r4; the call dummy will copy this to
1414 write_register (4, fun
);
1419 This function does not support passing parameters using the FPA
1420 variant of the APCS. It passes any floating point arguments in the
1421 general registers and/or on the stack. */
1424 arm_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
1425 int struct_return
, CORE_ADDR struct_addr
)
1428 int argnum
, argreg
, nstack_size
;
1430 /* Walk through the list of args and determine how large a temporary
1431 stack is required. Need to take care here as structs may be
1432 passed on the stack, and we have to to push them. */
1433 nstack_size
= -4 * REGISTER_SIZE
; /* Some arguments go into A1-A4. */
1434 if (struct_return
) /* The struct address goes in A1. */
1435 nstack_size
+= REGISTER_SIZE
;
1437 /* Walk through the arguments and add their size to nstack_size. */
1438 for (argnum
= 0; argnum
< nargs
; argnum
++)
1441 struct type
*arg_type
;
1443 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1444 len
= TYPE_LENGTH (arg_type
);
1449 /* Allocate room on the stack, and initialize our stack frame
1452 if (nstack_size
> 0)
1458 /* Initialize the integer argument register pointer. */
1459 argreg
= ARM_A1_REGNUM
;
1461 /* The struct_return pointer occupies the first parameter passing
1464 write_register (argreg
++, struct_addr
);
1466 /* Process arguments from left to right. Store as many as allowed
1467 in the parameter passing registers (A1-A4), and save the rest on
1468 the temporary stack. */
1469 for (argnum
= 0; argnum
< nargs
; argnum
++)
1474 enum type_code typecode
;
1475 struct type
*arg_type
, *target_type
;
1477 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1478 target_type
= TYPE_TARGET_TYPE (arg_type
);
1479 len
= TYPE_LENGTH (arg_type
);
1480 typecode
= TYPE_CODE (arg_type
);
1481 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
1484 /* I don't know why this code was disable. The only logical use
1485 for a function pointer is to call that function, so setting
1486 the mode bit is perfectly fine. FN */
1487 /* If the argument is a pointer to a function, and it is a Thumb
1488 function, set the low bit of the pointer. */
1489 if (TYPE_CODE_PTR
== typecode
1490 && NULL
!= target_type
1491 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1493 CORE_ADDR regval
= extract_address (val
, len
);
1494 if (arm_pc_is_thumb (regval
))
1495 store_address (val
, len
, MAKE_THUMB_ADDR (regval
));
1498 /* Copy the argument to general registers or the stack in
1499 register-sized pieces. Large arguments are split between
1500 registers and stack. */
1503 int partial_len
= len
< REGISTER_SIZE
? len
: REGISTER_SIZE
;
1505 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1507 /* It's an argument being passed in a general register. */
1508 regval
= extract_address (val
, partial_len
);
1509 write_register (argreg
++, regval
);
1513 /* Push the arguments onto the stack. */
1514 write_memory ((CORE_ADDR
) fp
, val
, REGISTER_SIZE
);
1515 fp
+= REGISTER_SIZE
;
1523 /* Return adjusted stack pointer. */
1527 /* Pop the current frame. So long as the frame info has been
1528 initialized properly (see arm_init_extra_frame_info), this code
1529 works for dummy frames as well as regular frames. I.e, there's no
1530 need to have a special case for dummy frames. */
1532 arm_pop_frame (void)
1535 struct frame_info
*frame
= get_current_frame ();
1536 CORE_ADDR old_SP
= (frame
->frame
- frame
->extra_info
->frameoffset
1537 + frame
->extra_info
->framesize
);
1539 if (USE_GENERIC_DUMMY_FRAMES
1540 && PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
1542 generic_pop_dummy_frame ();
1543 flush_cached_frames ();
1547 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1548 if (frame
->saved_regs
[regnum
] != 0)
1549 write_register (regnum
,
1550 read_memory_integer (frame
->saved_regs
[regnum
],
1551 REGISTER_RAW_SIZE (regnum
)));
1553 write_register (ARM_PC_REGNUM
, FRAME_SAVED_PC (frame
));
1554 write_register (ARM_SP_REGNUM
, old_SP
);
1556 flush_cached_frames ();
1560 print_fpu_flags (int flags
)
1562 if (flags
& (1 << 0))
1563 fputs ("IVO ", stdout
);
1564 if (flags
& (1 << 1))
1565 fputs ("DVZ ", stdout
);
1566 if (flags
& (1 << 2))
1567 fputs ("OFL ", stdout
);
1568 if (flags
& (1 << 3))
1569 fputs ("UFL ", stdout
);
1570 if (flags
& (1 << 4))
1571 fputs ("INX ", stdout
);
1575 /* Print interesting information about the floating point processor
1576 (if present) or emulator. */
1578 arm_print_float_info (void)
1580 register unsigned long status
= read_register (ARM_FPS_REGNUM
);
1583 type
= (status
>> 24) & 127;
1584 printf ("%s FPU type %d\n",
1585 (status
& (1 << 31)) ? "Hardware" : "Software",
1587 fputs ("mask: ", stdout
);
1588 print_fpu_flags (status
>> 16);
1589 fputs ("flags: ", stdout
);
1590 print_fpu_flags (status
);
1593 /* Return the GDB type object for the "standard" data type of data in
1596 static struct type
*
1597 arm_register_type (int regnum
)
1599 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1601 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1602 return builtin_type_arm_ext_big
;
1604 return builtin_type_arm_ext_littlebyte_bigword
;
1607 return builtin_type_int32
;
1610 /* Index within `registers' of the first byte of the space for
1614 arm_register_byte (int regnum
)
1616 if (regnum
< ARM_F0_REGNUM
)
1617 return regnum
* INT_REGISTER_RAW_SIZE
;
1618 else if (regnum
< ARM_PS_REGNUM
)
1619 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1620 + (regnum
- ARM_F0_REGNUM
) * FP_REGISTER_RAW_SIZE
);
1622 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1623 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
1624 + (regnum
- ARM_FPS_REGNUM
) * STATUS_REGISTER_SIZE
);
1627 /* Number of bytes of storage in the actual machine representation for
1628 register N. All registers are 4 bytes, except fp0 - fp7, which are
1629 12 bytes in length. */
1632 arm_register_raw_size (int regnum
)
1634 if (regnum
< ARM_F0_REGNUM
)
1635 return INT_REGISTER_RAW_SIZE
;
1636 else if (regnum
< ARM_FPS_REGNUM
)
1637 return FP_REGISTER_RAW_SIZE
;
1639 return STATUS_REGISTER_SIZE
;
1642 /* Number of bytes of storage in a program's representation
1645 arm_register_virtual_size (int regnum
)
1647 if (regnum
< ARM_F0_REGNUM
)
1648 return INT_REGISTER_VIRTUAL_SIZE
;
1649 else if (regnum
< ARM_FPS_REGNUM
)
1650 return FP_REGISTER_VIRTUAL_SIZE
;
1652 return STATUS_REGISTER_SIZE
;
1656 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1657 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1658 It is thought that this is is the floating-point register format on
1659 little-endian systems. */
1662 convert_from_extended (void *ptr
, void *dbl
)
1665 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1666 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1668 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1670 floatformat_from_doublest (TARGET_DOUBLE_FORMAT
, &d
, dbl
);
1674 convert_to_extended (void *dbl
, void *ptr
)
1677 floatformat_to_doublest (TARGET_DOUBLE_FORMAT
, ptr
, &d
);
1678 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1679 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1681 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1686 condition_true (unsigned long cond
, unsigned long status_reg
)
1688 if (cond
== INST_AL
|| cond
== INST_NV
)
1694 return ((status_reg
& FLAG_Z
) != 0);
1696 return ((status_reg
& FLAG_Z
) == 0);
1698 return ((status_reg
& FLAG_C
) != 0);
1700 return ((status_reg
& FLAG_C
) == 0);
1702 return ((status_reg
& FLAG_N
) != 0);
1704 return ((status_reg
& FLAG_N
) == 0);
1706 return ((status_reg
& FLAG_V
) != 0);
1708 return ((status_reg
& FLAG_V
) == 0);
1710 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1712 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1714 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1716 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1718 return (((status_reg
& FLAG_Z
) == 0) &&
1719 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1721 return (((status_reg
& FLAG_Z
) != 0) ||
1722 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1727 /* Support routines for single stepping. Calculate the next PC value. */
1728 #define submask(x) ((1L << ((x) + 1)) - 1)
1729 #define bit(obj,st) (((obj) >> (st)) & 1)
1730 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1731 #define sbits(obj,st,fn) \
1732 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1733 #define BranchDest(addr,instr) \
1734 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1737 static unsigned long
1738 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1739 unsigned long status_reg
)
1741 unsigned long res
, shift
;
1742 int rm
= bits (inst
, 0, 3);
1743 unsigned long shifttype
= bits (inst
, 5, 6);
1747 int rs
= bits (inst
, 8, 11);
1748 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1751 shift
= bits (inst
, 7, 11);
1754 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1755 + (bit (inst
, 4) ? 12 : 8))
1756 : read_register (rm
));
1761 res
= shift
>= 32 ? 0 : res
<< shift
;
1765 res
= shift
>= 32 ? 0 : res
>> shift
;
1771 res
= ((res
& 0x80000000L
)
1772 ? ~((~res
) >> shift
) : res
>> shift
);
1775 case 3: /* ROR/RRX */
1778 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1780 res
= (res
>> shift
) | (res
<< (32 - shift
));
1784 return res
& 0xffffffff;
1787 /* Return number of 1-bits in VAL. */
1790 bitcount (unsigned long val
)
1793 for (nbits
= 0; val
!= 0; nbits
++)
1794 val
&= val
- 1; /* delete rightmost 1-bit in val */
1799 thumb_get_next_pc (CORE_ADDR pc
)
1801 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1802 unsigned short inst1
= read_memory_integer (pc
, 2);
1803 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1804 unsigned long offset
;
1806 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1810 /* Fetch the saved PC from the stack. It's stored above
1811 all of the other registers. */
1812 offset
= bitcount (bits (inst1
, 0, 7)) * REGISTER_SIZE
;
1813 sp
= read_register (ARM_SP_REGNUM
);
1814 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1815 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1817 error ("Infinite loop detected");
1819 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1821 unsigned long status
= read_register (ARM_PS_REGNUM
);
1822 unsigned long cond
= bits (inst1
, 8, 11);
1823 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1824 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1826 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1828 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1830 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1832 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1833 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1834 nextpc
= pc_val
+ offset
;
1841 arm_get_next_pc (CORE_ADDR pc
)
1843 unsigned long pc_val
;
1844 unsigned long this_instr
;
1845 unsigned long status
;
1848 if (arm_pc_is_thumb (pc
))
1849 return thumb_get_next_pc (pc
);
1851 pc_val
= (unsigned long) pc
;
1852 this_instr
= read_memory_integer (pc
, 4);
1853 status
= read_register (ARM_PS_REGNUM
);
1854 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1856 if (condition_true (bits (this_instr
, 28, 31), status
))
1858 switch (bits (this_instr
, 24, 27))
1861 case 0x1: /* data processing */
1865 unsigned long operand1
, operand2
, result
= 0;
1869 if (bits (this_instr
, 12, 15) != 15)
1872 if (bits (this_instr
, 22, 25) == 0
1873 && bits (this_instr
, 4, 7) == 9) /* multiply */
1874 error ("Illegal update to pc in instruction");
1876 /* Multiply into PC */
1877 c
= (status
& FLAG_C
) ? 1 : 0;
1878 rn
= bits (this_instr
, 16, 19);
1879 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1881 if (bit (this_instr
, 25))
1883 unsigned long immval
= bits (this_instr
, 0, 7);
1884 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1885 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1888 else /* operand 2 is a shifted register */
1889 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1891 switch (bits (this_instr
, 21, 24))
1894 result
= operand1
& operand2
;
1898 result
= operand1
^ operand2
;
1902 result
= operand1
- operand2
;
1906 result
= operand2
- operand1
;
1910 result
= operand1
+ operand2
;
1914 result
= operand1
+ operand2
+ c
;
1918 result
= operand1
- operand2
+ c
;
1922 result
= operand2
- operand1
+ c
;
1928 case 0xb: /* tst, teq, cmp, cmn */
1929 result
= (unsigned long) nextpc
;
1933 result
= operand1
| operand2
;
1937 /* Always step into a function. */
1942 result
= operand1
& ~operand2
;
1949 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1952 error ("Infinite loop detected");
1957 case 0x5: /* data transfer */
1960 if (bit (this_instr
, 20))
1963 if (bits (this_instr
, 12, 15) == 15)
1969 if (bit (this_instr
, 22))
1970 error ("Illegal update to pc in instruction");
1972 /* byte write to PC */
1973 rn
= bits (this_instr
, 16, 19);
1974 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1975 if (bit (this_instr
, 24))
1978 int c
= (status
& FLAG_C
) ? 1 : 0;
1979 unsigned long offset
=
1980 (bit (this_instr
, 25)
1981 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1982 : bits (this_instr
, 0, 11));
1984 if (bit (this_instr
, 23))
1989 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1992 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1995 error ("Infinite loop detected");
2001 case 0x9: /* block transfer */
2002 if (bit (this_instr
, 20))
2005 if (bit (this_instr
, 15))
2010 if (bit (this_instr
, 23))
2013 unsigned long reglist
= bits (this_instr
, 0, 14);
2014 offset
= bitcount (reglist
) * 4;
2015 if (bit (this_instr
, 24)) /* pre */
2018 else if (bit (this_instr
, 24))
2022 unsigned long rn_val
=
2023 read_register (bits (this_instr
, 16, 19));
2025 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
2029 nextpc
= ADDR_BITS_REMOVE (nextpc
);
2031 error ("Infinite loop detected");
2036 case 0xb: /* branch & link */
2037 case 0xa: /* branch */
2039 nextpc
= BranchDest (pc
, this_instr
);
2041 nextpc
= ADDR_BITS_REMOVE (nextpc
);
2043 error ("Infinite loop detected");
2049 case 0xe: /* coproc ops */
2054 fprintf_filtered (gdb_stderr
, "Bad bit-field extraction\n");
2062 /* single_step() is called just before we want to resume the inferior,
2063 if we want to single-step it but there is no hardware or kernel
2064 single-step support. We find the target of the coming instruction
2067 single_step() is also called just after the inferior stops. If we
2068 had set up a simulated single-step, we undo our damage. */
2071 arm_software_single_step (enum target_signal sig
, int insert_bpt
)
2073 static int next_pc
; /* State between setting and unsetting. */
2074 static char break_mem
[BREAKPOINT_MAX
]; /* Temporary storage for mem@bpt */
2078 next_pc
= arm_get_next_pc (read_register (ARM_PC_REGNUM
));
2079 target_insert_breakpoint (next_pc
, break_mem
);
2082 target_remove_breakpoint (next_pc
, break_mem
);
2085 #include "bfd-in2.h"
2086 #include "libcoff.h"
2089 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
2091 if (arm_pc_is_thumb (memaddr
))
2093 static asymbol
*asym
;
2094 static combined_entry_type ce
;
2095 static struct coff_symbol_struct csym
;
2096 static struct _bfd fake_bfd
;
2097 static bfd_target fake_target
;
2099 if (csym
.native
== NULL
)
2101 /* Create a fake symbol vector containing a Thumb symbol.
2102 This is solely so that the code in print_insn_little_arm()
2103 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2104 the presence of a Thumb symbol and switch to decoding
2105 Thumb instructions. */
2107 fake_target
.flavour
= bfd_target_coff_flavour
;
2108 fake_bfd
.xvec
= &fake_target
;
2109 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
2111 csym
.symbol
.the_bfd
= &fake_bfd
;
2112 csym
.symbol
.name
= "fake";
2113 asym
= (asymbol
*) & csym
;
2116 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
2117 info
->symbols
= &asym
;
2120 info
->symbols
= NULL
;
2122 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2123 return print_insn_big_arm (memaddr
, info
);
2125 return print_insn_little_arm (memaddr
, info
);
2128 /* The following define instruction sequences that will cause ARM
2129 cpu's to take an undefined instruction trap. These are used to
2130 signal a breakpoint to GDB.
2132 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2133 modes. A different instruction is required for each mode. The ARM
2134 cpu's can also be big or little endian. Thus four different
2135 instructions are needed to support all cases.
2137 Note: ARMv4 defines several new instructions that will take the
2138 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2139 not in fact add the new instructions. The new undefined
2140 instructions in ARMv4 are all instructions that had no defined
2141 behaviour in earlier chips. There is no guarantee that they will
2142 raise an exception, but may be treated as NOP's. In practice, it
2143 may only safe to rely on instructions matching:
2145 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2146 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2147 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2149 Even this may only true if the condition predicate is true. The
2150 following use a condition predicate of ALWAYS so it is always TRUE.
2152 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2153 and NetBSD all use a software interrupt rather than an undefined
2154 instruction to force a trap. This can be handled by by the
2155 abi-specific code during establishment of the gdbarch vector. */
2158 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
2159 override these definitions. */
2160 #ifndef ARM_LE_BREAKPOINT
2161 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2163 #ifndef ARM_BE_BREAKPOINT
2164 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2166 #ifndef THUMB_LE_BREAKPOINT
2167 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
2169 #ifndef THUMB_BE_BREAKPOINT
2170 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
2173 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
2174 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
2175 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2176 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2178 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2179 the program counter value to determine whether a 16-bit or 32-bit
2180 breakpoint should be used. It returns a pointer to a string of
2181 bytes that encode a breakpoint instruction, stores the length of
2182 the string to *lenptr, and adjusts the program counter (if
2183 necessary) to point to the actual memory location where the
2184 breakpoint should be inserted. */
2186 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
2187 breakpoints and storing their handles instread of what was in
2188 memory. It is nice that this is the same size as a handle -
2189 otherwise remote-rdp will have to change. */
2191 static const unsigned char *
2192 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
2194 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2196 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
2198 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2199 *lenptr
= tdep
->thumb_breakpoint_size
;
2200 return tdep
->thumb_breakpoint
;
2204 *lenptr
= tdep
->arm_breakpoint_size
;
2205 return tdep
->arm_breakpoint
;
2209 /* Extract from an array REGBUF containing the (raw) register state a
2210 function return value of type TYPE, and copy that, in virtual
2211 format, into VALBUF. */
2214 arm_extract_return_value (struct type
*type
,
2215 char regbuf
[REGISTER_BYTES
],
2218 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2220 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2222 switch (tdep
->fp_model
)
2225 convert_from_extended (®buf
[REGISTER_BYTE (ARM_F0_REGNUM
)],
2229 case ARM_FLOAT_SOFT
:
2230 case ARM_FLOAT_SOFT_VFP
:
2231 memcpy (valbuf
, ®buf
[REGISTER_BYTE (ARM_A1_REGNUM
)],
2232 TYPE_LENGTH (type
));
2237 (__FILE__
, __LINE__
,
2238 "arm_extract_return_value: Floating point model not supported");
2243 memcpy (valbuf
, ®buf
[REGISTER_BYTE (ARM_A1_REGNUM
)],
2244 TYPE_LENGTH (type
));
2247 /* Extract from an array REGBUF containing the (raw) register state
2248 the address in which a function should return its structure value. */
2251 arm_extract_struct_value_address (char *regbuf
)
2253 return extract_address (regbuf
, REGISTER_RAW_SIZE(ARM_A1_REGNUM
));
2256 /* Will a function return an aggregate type in memory or in a
2257 register? Return 0 if an aggregate type can be returned in a
2258 register, 1 if it must be returned in memory. */
2261 arm_use_struct_convention (int gcc_p
, struct type
*type
)
2264 register enum type_code code
;
2266 /* In the ARM ABI, "integer" like aggregate types are returned in
2267 registers. For an aggregate type to be integer like, its size
2268 must be less than or equal to REGISTER_SIZE and the offset of
2269 each addressable subfield must be zero. Note that bit fields are
2270 not addressable, and all addressable subfields of unions always
2271 start at offset zero.
2273 This function is based on the behaviour of GCC 2.95.1.
2274 See: gcc/arm.c: arm_return_in_memory() for details.
2276 Note: All versions of GCC before GCC 2.95.2 do not set up the
2277 parameters correctly for a function returning the following
2278 structure: struct { float f;}; This should be returned in memory,
2279 not a register. Richard Earnshaw sent me a patch, but I do not
2280 know of any way to detect if a function like the above has been
2281 compiled with the correct calling convention. */
2283 /* All aggregate types that won't fit in a register must be returned
2285 if (TYPE_LENGTH (type
) > REGISTER_SIZE
)
2290 /* The only aggregate types that can be returned in a register are
2291 structs and unions. Arrays must be returned in memory. */
2292 code
= TYPE_CODE (type
);
2293 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2298 /* Assume all other aggregate types can be returned in a register.
2299 Run a check for structures, unions and arrays. */
2302 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2305 /* Need to check if this struct/union is "integer" like. For
2306 this to be true, its size must be less than or equal to
2307 REGISTER_SIZE and the offset of each addressable subfield
2308 must be zero. Note that bit fields are not addressable, and
2309 unions always start at offset zero. If any of the subfields
2310 is a floating point type, the struct/union cannot be an
2313 /* For each field in the object, check:
2314 1) Is it FP? --> yes, nRc = 1;
2315 2) Is it addressable (bitpos != 0) and
2316 not packed (bitsize == 0)?
2320 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2322 enum type_code field_type_code
;
2323 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
2325 /* Is it a floating point type field? */
2326 if (field_type_code
== TYPE_CODE_FLT
)
2332 /* If bitpos != 0, then we have to care about it. */
2333 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2335 /* Bitfields are not addressable. If the field bitsize is
2336 zero, then the field is not packed. Hence it cannot be
2337 a bitfield or any other packed type. */
2338 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2350 /* Write into appropriate registers a function return value of type
2351 TYPE, given in virtual format. */
2354 arm_store_return_value (struct type
*type
, char *valbuf
)
2356 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2358 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2359 char buf
[ARM_MAX_REGISTER_RAW_SIZE
];
2361 switch (tdep
->fp_model
)
2365 convert_to_extended (valbuf
, buf
);
2366 write_register_bytes (REGISTER_BYTE (ARM_F0_REGNUM
), buf
,
2367 FP_REGISTER_RAW_SIZE
);
2370 case ARM_FLOAT_SOFT
:
2371 case ARM_FLOAT_SOFT_VFP
:
2372 write_register_bytes (ARM_A1_REGNUM
, valbuf
, TYPE_LENGTH (type
));
2377 (__FILE__
, __LINE__
,
2378 "arm_store_return_value: Floating point model not supported");
2383 write_register_bytes (ARM_A1_REGNUM
, valbuf
, TYPE_LENGTH (type
));
2386 /* Store the address of the place in which to copy the structure the
2387 subroutine will return. This is called from call_function. */
2390 arm_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
2392 write_register (ARM_A1_REGNUM
, addr
);
2396 arm_get_longjmp_target (CORE_ADDR
*pc
)
2399 char buf
[INT_REGISTER_RAW_SIZE
];
2400 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2402 jb_addr
= read_register (ARM_A1_REGNUM
);
2404 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2405 INT_REGISTER_RAW_SIZE
))
2408 *pc
= extract_address (buf
, INT_REGISTER_RAW_SIZE
);
2412 /* Return non-zero if the PC is inside a thumb call thunk. */
2415 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2417 CORE_ADDR start_addr
;
2419 /* Find the starting address of the function containing the PC. If
2420 the caller didn't give us a name, look it up at the same time. */
2421 if (0 == find_pc_partial_function (pc
, name
? NULL
: &name
,
2425 return strncmp (name
, "_call_via_r", 11) == 0;
2428 /* If PC is in a Thumb call or return stub, return the address of the
2429 target PC, which is in a register. The thunk functions are called
2430 _called_via_xx, where x is the register name. The possible names
2431 are r0-r9, sl, fp, ip, sp, and lr. */
2434 arm_skip_stub (CORE_ADDR pc
)
2437 CORE_ADDR start_addr
;
2439 /* Find the starting address and name of the function containing the PC. */
2440 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2443 /* Call thunks always start with "_call_via_". */
2444 if (strncmp (name
, "_call_via_", 10) == 0)
2446 /* Use the name suffix to determine which register contains the
2448 static char *table
[15] =
2449 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2450 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2454 for (regno
= 0; regno
<= 14; regno
++)
2455 if (strcmp (&name
[10], table
[regno
]) == 0)
2456 return read_register (regno
);
2459 return 0; /* not a stub */
2462 /* If the user changes the register disassembly flavor used for info
2463 register and other commands, we have to also switch the flavor used
2464 in opcodes for disassembly output. This function is run in the set
2465 disassembly_flavor command, and does that. */
2468 set_disassembly_flavor_sfunc (char *args
, int from_tty
,
2469 struct cmd_list_element
*c
)
2471 set_disassembly_flavor ();
2474 /* Return the ARM register name corresponding to register I. */
2476 arm_register_name (int i
)
2478 return arm_register_names
[i
];
2482 set_disassembly_flavor (void)
2484 const char *setname
, *setdesc
, **regnames
;
2487 /* Find the flavor that the user wants in the opcodes table. */
2489 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2490 while ((disassembly_flavor
!= setname
)
2491 && (current
< num_flavor_options
))
2492 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2493 current_option
= current
;
2495 /* Fill our copy. */
2496 for (j
= 0; j
< numregs
; j
++)
2497 arm_register_names
[j
] = (char *) regnames
[j
];
2500 if (isupper (*regnames
[ARM_PC_REGNUM
]))
2502 arm_register_names
[ARM_FPS_REGNUM
] = "FPS";
2503 arm_register_names
[ARM_PS_REGNUM
] = "CPSR";
2507 arm_register_names
[ARM_FPS_REGNUM
] = "fps";
2508 arm_register_names
[ARM_PS_REGNUM
] = "cpsr";
2511 /* Synchronize the disassembler. */
2512 set_arm_regname_option (current
);
2515 /* arm_othernames implements the "othernames" command. This is kind
2516 of hacky, and I prefer the set-show disassembly-flavor which is
2517 also used for the x86 gdb. I will keep this around, however, in
2518 case anyone is actually using it. */
2521 arm_othernames (char *names
, int n
)
2523 /* Circle through the various flavors. */
2524 current_option
= (current_option
+ 1) % num_flavor_options
;
2526 disassembly_flavor
= valid_flavors
[current_option
];
2527 set_disassembly_flavor ();
2530 /* Fetch, and possibly build, an appropriate link_map_offsets structure
2531 for ARM linux targets using the struct offsets defined in <link.h>.
2532 Note, however, that link.h is not actually referred to in this file.
2533 Instead, the relevant structs offsets were obtained from examining
2534 link.h. (We can't refer to link.h from this file because the host
2535 system won't necessarily have it, or if it does, the structs which
2536 it defines will refer to the host system, not the target). */
2538 struct link_map_offsets
*
2539 arm_linux_svr4_fetch_link_map_offsets (void)
2541 static struct link_map_offsets lmo
;
2542 static struct link_map_offsets
*lmp
= 0;
2548 lmo
.r_debug_size
= 8; /* Actual size is 20, but this is all we
2551 lmo
.r_map_offset
= 4;
2554 lmo
.link_map_size
= 20; /* Actual size is 552, but this is all we
2557 lmo
.l_addr_offset
= 0;
2558 lmo
.l_addr_size
= 4;
2560 lmo
.l_name_offset
= 4;
2561 lmo
.l_name_size
= 4;
2563 lmo
.l_next_offset
= 12;
2564 lmo
.l_next_size
= 4;
2566 lmo
.l_prev_offset
= 16;
2567 lmo
.l_prev_size
= 4;
2573 /* Test whether the coff symbol specific value corresponds to a Thumb
2577 coff_sym_is_thumb (int val
)
2579 return (val
== C_THUMBEXT
||
2580 val
== C_THUMBSTAT
||
2581 val
== C_THUMBEXTFUNC
||
2582 val
== C_THUMBSTATFUNC
||
2583 val
== C_THUMBLABEL
);
2586 /* arm_coff_make_msymbol_special()
2587 arm_elf_make_msymbol_special()
2589 These functions test whether the COFF or ELF symbol corresponds to
2590 an address in thumb code, and set a "special" bit in a minimal
2591 symbol to indicate that it does. */
2594 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2596 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2598 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2600 MSYMBOL_SET_SPECIAL (msym
);
2604 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2606 if (coff_sym_is_thumb (val
))
2607 MSYMBOL_SET_SPECIAL (msym
);
2612 process_note_abi_tag_sections (bfd
*abfd
, asection
*sect
, void *obj
)
2614 enum arm_abi
*os_ident_ptr
= obj
;
2616 unsigned int sectsize
;
2618 name
= bfd_get_section_name (abfd
, sect
);
2619 sectsize
= bfd_section_size (abfd
, sect
);
2621 if (strcmp (name
, ".note.ABI-tag") == 0 && sectsize
> 0)
2623 unsigned int name_length
, data_length
, note_type
;
2626 /* If the section is larger than this, it's probably not what we are
2631 note
= alloca (sectsize
);
2633 bfd_get_section_contents (abfd
, sect
, note
,
2634 (file_ptr
) 0, (bfd_size_type
) sectsize
);
2636 name_length
= bfd_h_get_32 (abfd
, note
);
2637 data_length
= bfd_h_get_32 (abfd
, note
+ 4);
2638 note_type
= bfd_h_get_32 (abfd
, note
+ 8);
2640 if (name_length
== 4 && data_length
== 16 && note_type
== 1
2641 && strcmp (note
+ 12, "GNU") == 0)
2643 int os_number
= bfd_h_get_32 (abfd
, note
+ 16);
2645 /* The case numbers are from abi-tags in glibc. */
2649 *os_ident_ptr
= ARM_ABI_LINUX
;
2654 (__FILE__
, __LINE__
,
2655 "process_note_abi_sections: Hurd objects not supported");
2660 (__FILE__
, __LINE__
,
2661 "process_note_abi_sections: Solaris objects not supported");
2666 (__FILE__
, __LINE__
,
2667 "process_note_abi_sections: unknown OS number %d",
2673 /* NetBSD uses a similar trick. */
2674 else if (strcmp (name
, ".note.netbsd.ident") == 0 && sectsize
> 0)
2676 unsigned int name_length
, desc_length
, note_type
;
2679 /* If the section is larger than this, it's probably not what we are
2684 note
= alloca (sectsize
);
2686 bfd_get_section_contents (abfd
, sect
, note
,
2687 (file_ptr
) 0, (bfd_size_type
) sectsize
);
2689 name_length
= bfd_h_get_32 (abfd
, note
);
2690 desc_length
= bfd_h_get_32 (abfd
, note
+ 4);
2691 note_type
= bfd_h_get_32 (abfd
, note
+ 8);
2693 if (name_length
== 7 && desc_length
== 4 && note_type
== 1
2694 && strcmp (note
+ 12, "NetBSD") == 0)
2695 /* XXX Should we check the version here?
2696 Probably not necessary yet. */
2697 *os_ident_ptr
= ARM_ABI_NETBSD_ELF
;
2701 /* Return one of the ELFOSABI_ constants for BFDs representing ELF
2702 executables. If it's not an ELF executable or if the OS/ABI couldn't
2703 be determined, simply return -1. */
2706 get_elfosabi (bfd
*abfd
)
2709 enum arm_abi arm_abi
= ARM_ABI_UNKNOWN
;
2711 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2713 /* When elfosabi is 0 (ELFOSABI_NONE), this is supposed to indicate
2714 that we're on a SYSV system. However, GNU/Linux uses a note section
2715 to record OS/ABI info, but leaves e_ident[EI_OSABI] zero. So we
2716 have to check the note sections too.
2718 GNU/ARM tools set the EI_OSABI field to ELFOSABI_ARM, so handle that
2720 if (elfosabi
== 0 || elfosabi
== ELFOSABI_ARM
)
2722 bfd_map_over_sections (abfd
,
2723 process_note_abi_tag_sections
,
2727 if (arm_abi
!= ARM_ABI_UNKNOWN
)
2733 /* Existing ARM Tools don't set this field, so look at the EI_FLAGS
2734 field for more information. */
2736 switch (EF_ARM_EABI_VERSION(elf_elfheader(abfd
)->e_flags
))
2738 case EF_ARM_EABI_VER1
:
2739 return ARM_ABI_EABI_V1
;
2741 case EF_ARM_EABI_VER2
:
2742 return ARM_ABI_EABI_V2
;
2744 case EF_ARM_EABI_UNKNOWN
:
2745 /* Assume GNU tools. */
2746 return ARM_ABI_APCS
;
2749 internal_error (__FILE__
, __LINE__
,
2750 "get_elfosabi: Unknown ARM EABI version 0x%lx",
2751 EF_ARM_EABI_VERSION(elf_elfheader(abfd
)->e_flags
));
2756 case ELFOSABI_NETBSD
:
2757 return ARM_ABI_NETBSD_ELF
;
2759 case ELFOSABI_FREEBSD
:
2760 return ARM_ABI_FREEBSD
;
2762 case ELFOSABI_LINUX
:
2763 return ARM_ABI_LINUX
;
2766 /* Assume GNU tools with the old APCS abi. */
2767 return ARM_ABI_APCS
;
2772 return ARM_ABI_UNKNOWN
;
2775 struct arm_abi_handler
2777 struct arm_abi_handler
*next
;
2779 void (*init_abi
)(struct gdbarch_info
, struct gdbarch
*);
2782 struct arm_abi_handler
*arm_abi_handler_list
= NULL
;
2785 arm_gdbarch_register_os_abi (enum arm_abi abi
,
2786 void (*init_abi
)(struct gdbarch_info
,
2789 struct arm_abi_handler
**handler_p
;
2791 for (handler_p
= &arm_abi_handler_list
; *handler_p
!= NULL
;
2792 handler_p
= &(*handler_p
)->next
)
2794 if ((*handler_p
)->abi
== abi
)
2797 (__FILE__
, __LINE__
,
2798 "arm_gdbarch_register_os_abi: A handler for this ABI variant (%d)"
2799 " has already been registered", (int)abi
);
2800 /* If user wants to continue, override previous definition. */
2801 (*handler_p
)->init_abi
= init_abi
;
2807 = (struct arm_abi_handler
*) xmalloc (sizeof (struct arm_abi_handler
));
2808 (*handler_p
)->next
= NULL
;
2809 (*handler_p
)->abi
= abi
;
2810 (*handler_p
)->init_abi
= init_abi
;
2813 /* Initialize the current architecture based on INFO. If possible,
2814 re-use an architecture from ARCHES, which is a list of
2815 architectures already created during this debugging session.
2817 Called e.g. at program startup, when reading a core file, and when
2818 reading a binary file. */
2820 static struct gdbarch
*
2821 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2823 struct gdbarch_tdep
*tdep
;
2824 struct gdbarch
*gdbarch
;
2825 enum arm_abi arm_abi
= ARM_ABI_UNKNOWN
;
2826 struct arm_abi_handler
*abi_handler
;
2828 /* Try to deterimine the ABI of the object we are loading. */
2830 if (info
.abfd
!= NULL
)
2832 switch (bfd_get_flavour (info
.abfd
))
2834 case bfd_target_elf_flavour
:
2835 arm_abi
= get_elfosabi (info
.abfd
);
2838 case bfd_target_aout_flavour
:
2839 if (strcmp (bfd_get_target(info
.abfd
), "a.out-arm-netbsd") == 0)
2840 arm_abi
= ARM_ABI_NETBSD_AOUT
;
2842 /* Assume it's an old APCS-style ABI. */
2843 arm_abi
= ARM_ABI_APCS
;
2846 case bfd_target_coff_flavour
:
2847 /* Assume it's an old APCS-style ABI. */
2849 arm_abi
= ARM_ABI_APCS
;
2853 /* Not sure what to do here, leave the ABI as unknown. */
2858 /* Find a candidate among extant architectures. */
2859 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2861 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
2863 /* Make sure the ABI selection matches. */
2864 tdep
= gdbarch_tdep (arches
->gdbarch
);
2865 if (tdep
&& tdep
->arm_abi
== arm_abi
)
2866 return arches
->gdbarch
;
2869 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
2870 gdbarch
= gdbarch_alloc (&info
, tdep
);
2872 tdep
->arm_abi
= arm_abi
;
2873 if (arm_abi
< ARM_ABI_INVALID
)
2874 tdep
->abi_name
= arm_abi_names
[arm_abi
];
2877 internal_error (__FILE__
, __LINE__
, "Invalid setting of arm_abi %d",
2879 tdep
->abi_name
= "<invalid>";
2882 /* This is the way it has always defaulted. */
2883 tdep
->fp_model
= ARM_FLOAT_FPA
;
2886 switch (info
.byte_order
)
2888 case BFD_ENDIAN_BIG
:
2889 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
2890 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
2891 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
2892 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
2896 case BFD_ENDIAN_LITTLE
:
2897 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
2898 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
2899 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
2900 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
2905 internal_error (__FILE__
, __LINE__
,
2906 "arm_gdbarch_init: bad byte order for float format");
2909 /* On ARM targets char defaults to unsigned. */
2910 set_gdbarch_char_signed (gdbarch
, 0);
2912 /* This should be low enough for everything. */
2913 tdep
->lowest_pc
= 0x20;
2914 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
2916 #if OLD_STYLE_ARM_DUMMY_FRAMES
2917 /* NOTE: cagney/2002-05-07: Enable the below to restore the old ARM
2918 specific (non-generic) dummy frame code. Might be useful if
2919 there appears to be a problem with the generic dummy frame
2920 mechanism that replaced it. */
2921 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
2923 /* Call dummy code. */
2924 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
2925 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
2926 /* We have to give this a value now, even though we will re-set it
2927 during each call to arm_fix_call_dummy. */
2928 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 8);
2929 set_gdbarch_call_dummy_p (gdbarch
, 1);
2930 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
2932 set_gdbarch_call_dummy_words (gdbarch
, arm_call_dummy_words
);
2933 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (arm_call_dummy_words
));
2934 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
2935 set_gdbarch_call_dummy_length (gdbarch
, 0);
2937 set_gdbarch_fix_call_dummy (gdbarch
, arm_fix_call_dummy
);
2939 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_on_stack
);
2941 set_gdbarch_use_generic_dummy_frames (gdbarch
, 1);
2942 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
2944 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
2945 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
2947 set_gdbarch_call_dummy_p (gdbarch
, 1);
2948 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
2950 set_gdbarch_call_dummy_words (gdbarch
, arm_call_dummy_words
);
2951 set_gdbarch_sizeof_call_dummy_words (gdbarch
, 0);
2952 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
2953 set_gdbarch_call_dummy_length (gdbarch
, 0);
2955 set_gdbarch_fix_call_dummy (gdbarch
, generic_fix_call_dummy
);
2956 set_gdbarch_pc_in_call_dummy (gdbarch
, generic_pc_in_call_dummy
);
2958 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
2959 set_gdbarch_push_return_address (gdbarch
, arm_push_return_address
);
2962 set_gdbarch_get_saved_register (gdbarch
, generic_get_saved_register
);
2963 set_gdbarch_push_arguments (gdbarch
, arm_push_arguments
);
2964 set_gdbarch_coerce_float_to_double (gdbarch
,
2965 standard_coerce_float_to_double
);
2967 /* Frame handling. */
2968 set_gdbarch_frame_chain_valid (gdbarch
, arm_frame_chain_valid
);
2969 set_gdbarch_init_extra_frame_info (gdbarch
, arm_init_extra_frame_info
);
2970 set_gdbarch_read_fp (gdbarch
, arm_read_fp
);
2971 set_gdbarch_frame_chain (gdbarch
, arm_frame_chain
);
2972 set_gdbarch_frameless_function_invocation
2973 (gdbarch
, arm_frameless_function_invocation
);
2974 set_gdbarch_frame_saved_pc (gdbarch
, arm_frame_saved_pc
);
2975 set_gdbarch_frame_args_address (gdbarch
, arm_frame_args_address
);
2976 set_gdbarch_frame_locals_address (gdbarch
, arm_frame_locals_address
);
2977 set_gdbarch_frame_num_args (gdbarch
, arm_frame_num_args
);
2978 set_gdbarch_frame_args_skip (gdbarch
, 0);
2979 set_gdbarch_frame_init_saved_regs (gdbarch
, arm_frame_init_saved_regs
);
2980 #if OLD_STYLE_ARM_DUMMY_FRAMES
2981 /* NOTE: cagney/2002-05-07: Enable the below to restore the old ARM
2982 specific (non-generic) dummy frame code. Might be useful if
2983 there appears to be a problem with the generic dummy frame
2984 mechanism that replaced it. */
2985 set_gdbarch_push_dummy_frame (gdbarch
, arm_push_dummy_frame
);
2987 set_gdbarch_push_dummy_frame (gdbarch
, generic_push_dummy_frame
);
2989 set_gdbarch_pop_frame (gdbarch
, arm_pop_frame
);
2991 /* Address manipulation. */
2992 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
2993 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
2995 /* Offset from address of function to start of its code. */
2996 set_gdbarch_function_start_offset (gdbarch
, 0);
2998 /* Advance PC across function entry code. */
2999 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
3001 /* Get the PC when a frame might not be available. */
3002 set_gdbarch_saved_pc_after_call (gdbarch
, arm_saved_pc_after_call
);
3004 /* The stack grows downward. */
3005 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3007 /* Breakpoint manipulation. */
3008 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
3009 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
3011 /* Information about registers, etc. */
3012 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
3013 set_gdbarch_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
3014 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
3015 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
3016 set_gdbarch_register_byte (gdbarch
, arm_register_byte
);
3017 set_gdbarch_register_bytes (gdbarch
,
3018 (NUM_GREGS
* INT_REGISTER_RAW_SIZE
3019 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
3020 + NUM_SREGS
* STATUS_REGISTER_SIZE
));
3021 set_gdbarch_num_regs (gdbarch
, NUM_GREGS
+ NUM_FREGS
+ NUM_SREGS
);
3022 set_gdbarch_register_raw_size (gdbarch
, arm_register_raw_size
);
3023 set_gdbarch_register_virtual_size (gdbarch
, arm_register_virtual_size
);
3024 set_gdbarch_max_register_raw_size (gdbarch
, FP_REGISTER_RAW_SIZE
);
3025 set_gdbarch_max_register_virtual_size (gdbarch
, FP_REGISTER_VIRTUAL_SIZE
);
3026 set_gdbarch_register_virtual_type (gdbarch
, arm_register_type
);
3028 /* Integer registers are 4 bytes. */
3029 set_gdbarch_register_size (gdbarch
, 4);
3030 set_gdbarch_register_name (gdbarch
, arm_register_name
);
3032 /* Returning results. */
3033 set_gdbarch_extract_return_value (gdbarch
, arm_extract_return_value
);
3034 set_gdbarch_store_return_value (gdbarch
, arm_store_return_value
);
3035 set_gdbarch_store_struct_return (gdbarch
, arm_store_struct_return
);
3036 set_gdbarch_use_struct_convention (gdbarch
, arm_use_struct_convention
);
3037 set_gdbarch_extract_struct_value_address (gdbarch
,
3038 arm_extract_struct_value_address
);
3040 /* Single stepping. */
3041 /* XXX For an RDI target we should ask the target if it can single-step. */
3042 set_gdbarch_software_single_step (gdbarch
, arm_software_single_step
);
3044 /* Minsymbol frobbing. */
3045 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
3046 set_gdbarch_coff_make_msymbol_special (gdbarch
,
3047 arm_coff_make_msymbol_special
);
3049 /* Hook in the ABI-specific overrides, if they have been registered. */
3050 if (arm_abi
== ARM_ABI_UNKNOWN
)
3052 /* Don't complain about not knowing the ABI variant if we don't
3053 have an inferior. */
3056 (gdb_stderr
, "GDB doesn't recognize the ABI of the inferior. "
3057 "Attempting to continue with the default ARM settings");
3061 for (abi_handler
= arm_abi_handler_list
; abi_handler
!= NULL
;
3062 abi_handler
= abi_handler
->next
)
3063 if (abi_handler
->abi
== arm_abi
)
3067 abi_handler
->init_abi (info
, gdbarch
);
3070 /* We assume that if GDB_MULTI_ARCH is less than
3071 GDB_MULTI_ARCH_TM that an ABI variant can be supported by
3072 overriding definitions in this file. */
3073 if (GDB_MULTI_ARCH
> GDB_MULTI_ARCH_PARTIAL
)
3076 "A handler for the ABI variant \"%s\" is not built into this "
3077 "configuration of GDB. "
3078 "Attempting to continue with the default ARM settings",
3079 arm_abi_names
[arm_abi
]);
3083 /* Now we have tuned the configuration, set a few final things,
3084 based on what the OS ABI has told us. */
3086 if (tdep
->jb_pc
>= 0)
3087 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
3089 /* Floating point sizes and format. */
3090 switch (info
.byte_order
)
3092 case BFD_ENDIAN_BIG
:
3093 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
3094 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_big
);
3095 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
3099 case BFD_ENDIAN_LITTLE
:
3100 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
3101 if (tdep
->fp_model
== ARM_FLOAT_VFP
3102 || tdep
->fp_model
== ARM_FLOAT_SOFT_VFP
)
3104 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_little
);
3105 set_gdbarch_long_double_format (gdbarch
,
3106 &floatformat_ieee_double_little
);
3110 set_gdbarch_double_format
3111 (gdbarch
, &floatformat_ieee_double_littlebyte_bigword
);
3112 set_gdbarch_long_double_format
3113 (gdbarch
, &floatformat_ieee_double_littlebyte_bigword
);
3118 internal_error (__FILE__
, __LINE__
,
3119 "arm_gdbarch_init: bad byte order for float format");
3122 /* We can't use SIZEOF_FRAME_SAVED_REGS here, since that still
3123 references the old architecture vector, not the one we are
3125 if (prologue_cache
.saved_regs
!= NULL
)
3126 xfree (prologue_cache
.saved_regs
);
3128 /* We can't use NUM_REGS nor NUM_PSEUDO_REGS here, since that still
3129 references the old architecture vector, not the one we are
3131 prologue_cache
.saved_regs
= (CORE_ADDR
*)
3132 xcalloc (1, (sizeof (CORE_ADDR
)
3133 * (gdbarch_num_regs (gdbarch
)
3134 + gdbarch_num_pseudo_regs (gdbarch
))));
3140 arm_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
3142 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3147 if (tdep
->abi_name
!= NULL
)
3148 fprintf_unfiltered (file
, "arm_dump_tdep: ABI = %s\n", tdep
->abi_name
);
3150 internal_error (__FILE__
, __LINE__
,
3151 "arm_dump_tdep: illegal setting of tdep->arm_abi (%d)",
3152 (int) tdep
->arm_abi
);
3154 fprintf_unfiltered (file
, "arm_dump_tdep: Lowest pc = 0x%lx",
3155 (unsigned long) tdep
->lowest_pc
);
3159 arm_init_abi_eabi_v1 (struct gdbarch_info info
,
3160 struct gdbarch
*gdbarch
)
3166 arm_init_abi_eabi_v2 (struct gdbarch_info info
,
3167 struct gdbarch
*gdbarch
)
3173 arm_init_abi_apcs (struct gdbarch_info info
,
3174 struct gdbarch
*gdbarch
)
3180 _initialize_arm_tdep (void)
3182 struct ui_file
*stb
;
3184 struct cmd_list_element
*new_cmd
;
3185 const char *setname
;
3186 const char *setdesc
;
3187 const char **regnames
;
3189 static char *helptext
;
3192 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
3194 /* Register some ABI variants for embedded systems. */
3195 arm_gdbarch_register_os_abi (ARM_ABI_EABI_V1
, arm_init_abi_eabi_v1
);
3196 arm_gdbarch_register_os_abi (ARM_ABI_EABI_V2
, arm_init_abi_eabi_v2
);
3197 arm_gdbarch_register_os_abi (ARM_ABI_APCS
, arm_init_abi_apcs
);
3199 tm_print_insn
= gdb_print_insn_arm
;
3201 /* Get the number of possible sets of register names defined in opcodes. */
3202 num_flavor_options
= get_arm_regname_num_options ();
3204 /* Sync the opcode insn printer with our register viewer. */
3205 parse_arm_disassembler_option ("reg-names-std");
3207 /* Begin creating the help text. */
3208 stb
= mem_fileopen ();
3209 fprintf_unfiltered (stb
, "Set the disassembly flavor.\n\
3210 The valid values are:\n");
3212 /* Initialize the array that will be passed to add_set_enum_cmd(). */
3213 valid_flavors
= xmalloc ((num_flavor_options
+ 1) * sizeof (char *));
3214 for (i
= 0; i
< num_flavor_options
; i
++)
3216 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
3217 valid_flavors
[i
] = setname
;
3218 fprintf_unfiltered (stb
, "%s - %s\n", setname
,
3220 /* Copy the default names (if found) and synchronize disassembler. */
3221 if (!strcmp (setname
, "std"))
3223 disassembly_flavor
= setname
;
3225 for (j
= 0; j
< numregs
; j
++)
3226 arm_register_names
[j
] = (char *) regnames
[j
];
3227 set_arm_regname_option (i
);
3230 /* Mark the end of valid options. */
3231 valid_flavors
[num_flavor_options
] = NULL
;
3233 /* Finish the creation of the help text. */
3234 fprintf_unfiltered (stb
, "The default is \"std\".");
3235 helptext
= ui_file_xstrdup (stb
, &length
);
3236 ui_file_delete (stb
);
3238 /* Add the disassembly-flavor command. */
3239 new_cmd
= add_set_enum_cmd ("disassembly-flavor", no_class
,
3241 &disassembly_flavor
,
3244 set_cmd_sfunc (new_cmd
, set_disassembly_flavor_sfunc
);
3245 add_show_from_set (new_cmd
, &showlist
);
3247 /* ??? Maybe this should be a boolean. */
3248 add_show_from_set (add_set_cmd ("apcs32", no_class
,
3249 var_zinteger
, (char *) &arm_apcs_32
,
3250 "Set usage of ARM 32-bit mode.\n", &setlist
),
3253 /* Add the deprecated "othernames" command. */
3255 add_com ("othernames", class_obscure
, arm_othernames
,
3256 "Switch to the next set of register names.");
3258 /* Fill in the prologue_cache fields. */
3259 prologue_cache
.saved_regs
= NULL
;
3260 prologue_cache
.extra_info
= (struct frame_extra_info
*)
3261 xcalloc (1, sizeof (struct frame_extra_info
));