1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "coff/internal.h" /* Internal format of COFF symbols in BFD */
30 #include "dis-asm.h" /* For register flavors. */
31 #include <ctype.h> /* for isupper () */
35 /* Each OS has a different mechanism for accessing the various
36 registers stored in the sigcontext structure.
38 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
39 function pointer) which may be used to determine the addresses
40 of the various saved registers in the sigcontext structure.
42 For the ARM target, there are three parameters to this function.
43 The first is the pc value of the frame under consideration, the
44 second the stack pointer of this frame, and the last is the
45 register number to fetch.
47 If the tm.h file does not define this macro, then it's assumed that
48 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
51 When it comes time to multi-arching this code, see the identically
52 named machinery in ia64-tdep.c for an example of how it could be
53 done. It should not be necessary to modify the code below where
54 this macro is used. */
56 #ifdef SIGCONTEXT_REGISTER_ADDRESS
57 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
58 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
61 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
62 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
65 extern void _initialize_arm_tdep (void);
67 /* Number of different reg name sets (options). */
68 static int num_flavor_options
;
70 /* We have more registers than the disassembler as gdb can print the value
71 of special registers as well.
72 The general register names are overwritten by whatever is being used by
73 the disassembler at the moment. We also adjust the case of cpsr and fps. */
75 /* Initial value: Register names used in ARM's ISA documentation. */
76 static char * arm_register_name_strings
[] =
77 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
78 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
79 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
80 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
81 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
82 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
83 "fps", "cpsr" }; /* 24 25 */
84 char **arm_register_names
= arm_register_name_strings
;
86 /* Valid register name flavors. */
87 static const char **valid_flavors
;
89 /* Disassembly flavor to use. Default to "std" register names. */
90 static const char *disassembly_flavor
;
91 static int current_option
; /* Index to that option in the opcodes table. */
93 /* This is used to keep the bfd arch_info in sync with the disassembly
95 static void set_disassembly_flavor_sfunc(char *, int,
96 struct cmd_list_element
*);
97 static void set_disassembly_flavor (void);
99 static void convert_from_extended (void *ptr
, void *dbl
);
101 /* Define other aspects of the stack frame. We keep the offsets of
102 all saved registers, 'cause we need 'em a lot! We also keep the
103 current size of the stack frame, and the offset of the frame
104 pointer from the stack pointer (for frameless functions, and when
105 we're still in the prologue of a function with a frame) */
107 struct frame_extra_info
109 struct frame_saved_regs fsr
;
115 /* Addresses for calling Thumb functions have the bit 0 set.
116 Here are some macros to test, set, or clear bit 0 of addresses. */
117 #define IS_THUMB_ADDR(addr) ((addr) & 1)
118 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
119 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
121 #define SWAP_TARGET_AND_HOST(buffer,len) \
124 if (TARGET_BYTE_ORDER != HOST_BYTE_ORDER) \
127 char *p = (char *)(buffer); \
128 char *q = ((char *)(buffer)) + len - 1; \
129 for (; p < q; p++, q--) \
139 /* Will a function return an aggregate type in memory or in a
140 register? Return 0 if an aggregate type can be returned in a
141 register, 1 if it must be returned in memory. */
144 arm_use_struct_convention (int gcc_p
, struct type
*type
)
147 register enum type_code code
;
149 /* In the ARM ABI, "integer" like aggregate types are returned in
150 registers. For an aggregate type to be integer like, its size
151 must be less than or equal to REGISTER_SIZE and the offset of
152 each addressable subfield must be zero. Note that bit fields are
153 not addressable, and all addressable subfields of unions always
154 start at offset zero.
156 This function is based on the behaviour of GCC 2.95.1.
157 See: gcc/arm.c: arm_return_in_memory() for details.
159 Note: All versions of GCC before GCC 2.95.2 do not set up the
160 parameters correctly for a function returning the following
161 structure: struct { float f;}; This should be returned in memory,
162 not a register. Richard Earnshaw sent me a patch, but I do not
163 know of any way to detect if a function like the above has been
164 compiled with the correct calling convention. */
166 /* All aggregate types that won't fit in a register must be returned
168 if (TYPE_LENGTH (type
) > REGISTER_SIZE
)
173 /* The only aggregate types that can be returned in a register are
174 structs and unions. Arrays must be returned in memory. */
175 code
= TYPE_CODE (type
);
176 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
181 /* Assume all other aggregate types can be returned in a register.
182 Run a check for structures, unions and arrays. */
185 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
188 /* Need to check if this struct/union is "integer" like. For
189 this to be true, its size must be less than or equal to
190 REGISTER_SIZE and the offset of each addressable subfield
191 must be zero. Note that bit fields are not addressable, and
192 unions always start at offset zero. If any of the subfields
193 is a floating point type, the struct/union cannot be an
196 /* For each field in the object, check:
197 1) Is it FP? --> yes, nRc = 1;
198 2) Is it addressable (bitpos != 0) and
199 not packed (bitsize == 0)?
203 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
205 enum type_code field_type_code
;
206 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
208 /* Is it a floating point type field? */
209 if (field_type_code
== TYPE_CODE_FLT
)
215 /* If bitpos != 0, then we have to care about it. */
216 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
218 /* Bitfields are not addressable. If the field bitsize is
219 zero, then the field is not packed. Hence it cannot be
220 a bitfield or any other packed type. */
221 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
234 arm_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*thisframe
)
236 return (chain
!= 0 && (FRAME_SAVED_PC (thisframe
) >= LOWEST_PC
));
239 /* Set to true if the 32-bit mode is in use. */
243 /* Flag set by arm_fix_call_dummy that tells whether the target
244 function is a Thumb function. This flag is checked by
245 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
246 its use in valops.c) to pass the function address as an additional
249 static int target_is_thumb
;
251 /* Flag set by arm_fix_call_dummy that tells whether the calling
252 function is a Thumb function. This flag is checked by
253 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
255 static int caller_is_thumb
;
257 /* Determine if the program counter specified in MEMADDR is in a Thumb
261 arm_pc_is_thumb (CORE_ADDR memaddr
)
263 struct minimal_symbol
*sym
;
265 /* If bit 0 of the address is set, assume this is a Thumb address. */
266 if (IS_THUMB_ADDR (memaddr
))
269 /* Thumb functions have a "special" bit set in minimal symbols. */
270 sym
= lookup_minimal_symbol_by_pc (memaddr
);
273 return (MSYMBOL_IS_SPECIAL (sym
));
281 /* Determine if the program counter specified in MEMADDR is in a call
282 dummy being called from a Thumb function. */
285 arm_pc_is_thumb_dummy (CORE_ADDR memaddr
)
287 CORE_ADDR sp
= read_sp ();
289 /* FIXME: Until we switch for the new call dummy macros, this heuristic
290 is the best we can do. We are trying to determine if the pc is on
291 the stack, which (hopefully) will only happen in a call dummy.
292 We hope the current stack pointer is not so far alway from the dummy
293 frame location (true if we have not pushed large data structures or
294 gone too many levels deep) and that our 1024 is not enough to consider
295 code regions as part of the stack (true for most practical purposes) */
296 if (PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 1024))
297 return caller_is_thumb
;
303 arm_addr_bits_remove (CORE_ADDR val
)
305 if (arm_pc_is_thumb (val
))
306 return (val
& (arm_apcs_32
? 0xfffffffe : 0x03fffffe));
308 return (val
& (arm_apcs_32
? 0xfffffffc : 0x03fffffc));
312 arm_saved_pc_after_call (struct frame_info
*frame
)
314 return ADDR_BITS_REMOVE (read_register (LR_REGNUM
));
318 arm_frameless_function_invocation (struct frame_info
*fi
)
320 CORE_ADDR func_start
, after_prologue
;
323 func_start
= (get_pc_function_start ((fi
)->pc
) + FUNCTION_START_OFFSET
);
324 after_prologue
= SKIP_PROLOGUE (func_start
);
326 /* There are some frameless functions whose first two instructions
327 follow the standard APCS form, in which case after_prologue will
328 be func_start + 8. */
330 frameless
= (after_prologue
< func_start
+ 12);
334 /* A typical Thumb prologue looks like this:
338 Sometimes the latter instruction may be replaced by:
346 or, on tpcs, like this:
353 There is always one instruction of three classes:
358 When we have found at least one of each class we are done with the prolog.
359 Note that the "sub sp, #NN" before the push does not count.
363 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
365 CORE_ADDR current_pc
;
366 int findmask
= 0; /* findmask:
367 bit 0 - push { rlist }
368 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
369 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
372 for (current_pc
= pc
; current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40; current_pc
+= 2)
374 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
376 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
378 findmask
|= 1; /* push found */
380 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
382 if ((findmask
& 1) == 0) /* before push ? */
385 findmask
|= 4; /* add/sub sp found */
387 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
389 findmask
|= 2; /* setting of r7 found */
391 else if (insn
== 0x466f) /* mov r7, sp */
393 findmask
|= 2; /* setting of r7 found */
396 continue; /* something in the prolog that we don't care about or some
397 instruction from outside the prolog scheduled here for optimization */
403 /* The APCS (ARM Procedure Call Standard) defines the following
407 [stmfd sp!, {a1,a2,a3,a4}]
408 stmfd sp!, {...,fp,ip,lr,pc}
409 [stfe f7, [sp, #-12]!]
410 [stfe f6, [sp, #-12]!]
411 [stfe f5, [sp, #-12]!]
412 [stfe f4, [sp, #-12]!]
413 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
416 arm_skip_prologue (CORE_ADDR pc
)
420 CORE_ADDR func_addr
, func_end
;
421 struct symtab_and_line sal
;
423 /* See what the symbol table says. */
425 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
427 sal
= find_pc_line (func_addr
, 0);
428 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
432 /* Check if this is Thumb code. */
433 if (arm_pc_is_thumb (pc
))
434 return thumb_skip_prologue (pc
, func_end
);
436 /* Can't find the prologue end in the symbol table, try it the hard way
437 by disassembling the instructions. */
439 inst
= read_memory_integer (skip_pc
, 4);
440 if (inst
!= 0xe1a0c00d) /* mov ip, sp */
444 inst
= read_memory_integer (skip_pc
, 4);
445 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
448 inst
= read_memory_integer (skip_pc
, 4);
451 if ((inst
& 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */
455 inst
= read_memory_integer (skip_pc
, 4);
457 /* Any insns after this point may float into the code, if it makes
458 for better instruction scheduling, so we skip them only if we
459 find them, but still consdier the function to be frame-ful. */
461 /* We may have either one sfmfd instruction here, or several stfe
462 insns, depending on the version of floating point code we
464 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
467 inst
= read_memory_integer (skip_pc
, 4);
471 while ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
474 inst
= read_memory_integer (skip_pc
, 4);
478 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
484 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
485 This function decodes a Thumb function prologue to determine:
486 1) the size of the stack frame
487 2) which registers are saved on it
488 3) the offsets of saved regs
489 4) the offset from the stack pointer to the frame pointer
490 This information is stored in the "extra" fields of the frame_info.
492 A typical Thumb function prologue would create this stack frame
493 (offsets relative to FP)
494 old SP -> 24 stack parameters
497 R7 -> 0 local variables (16 bytes)
498 SP -> -12 additional stack space (12 bytes)
499 The frame size would thus be 36 bytes, and the frame offset would be
500 12 bytes. The frame register is R7.
502 The comments for thumb_skip_prolog() describe the algorithm we use to detect
503 the end of the prolog */
507 thumb_scan_prologue (struct frame_info
*fi
)
509 CORE_ADDR prologue_start
;
510 CORE_ADDR prologue_end
;
511 CORE_ADDR current_pc
;
512 int saved_reg
[16]; /* which register has been copied to register n? */
513 int findmask
= 0; /* findmask:
514 bit 0 - push { rlist }
515 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
516 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
520 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
522 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
524 if (sal
.line
== 0) /* no line info, use current PC */
525 prologue_end
= fi
->pc
;
526 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
527 prologue_end
= sal
.end
; /* (probably means no prologue) */
530 prologue_end
= prologue_start
+ 40; /* We're in the boondocks: allow for */
531 /* 16 pushes, an add, and "mv fp,sp" */
533 prologue_end
= min (prologue_end
, fi
->pc
);
535 /* Initialize the saved register map. When register H is copied to
536 register L, we will put H in saved_reg[L]. */
537 for (i
= 0; i
< 16; i
++)
540 /* Search the prologue looking for instructions that set up the
541 frame pointer, adjust the stack pointer, and save registers.
542 Do this until all basic prolog instructions are found. */
545 for (current_pc
= prologue_start
;
546 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
553 insn
= read_memory_unsigned_integer (current_pc
, 2);
555 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
558 findmask
|= 1; /* push found */
559 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
560 whether to save LR (R14). */
561 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
563 /* Calculate offsets of saved R0-R7 and LR. */
564 for (regno
= LR_REGNUM
; regno
>= 0; regno
--)
565 if (mask
& (1 << regno
))
568 fi
->fsr
.regs
[saved_reg
[regno
]] = -(fi
->framesize
);
569 saved_reg
[regno
] = regno
; /* reset saved register map */
572 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
574 if ((findmask
& 1) == 0) /* before push ? */
577 findmask
|= 4; /* add/sub sp found */
579 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
580 if (insn
& 0x80) /* is it signed? (==subtracting) */
582 fi
->frameoffset
+= offset
;
585 fi
->framesize
-= offset
;
587 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
589 findmask
|= 2; /* setting of r7 found */
590 fi
->framereg
= THUMB_FP_REGNUM
;
591 fi
->frameoffset
= (insn
& 0xff) << 2; /* get scaled offset */
593 else if (insn
== 0x466f) /* mov r7, sp */
595 findmask
|= 2; /* setting of r7 found */
596 fi
->framereg
= THUMB_FP_REGNUM
;
598 saved_reg
[THUMB_FP_REGNUM
] = SP_REGNUM
;
600 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
602 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
603 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
604 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
607 continue; /* something in the prolog that we don't care about or some
608 instruction from outside the prolog scheduled here for optimization */
612 /* Check if prologue for this frame's PC has already been scanned. If
613 it has, copy the relevant information about that prologue and
614 return non-zero. Otherwise do not copy anything and return zero.
616 The information saved in the cache includes:
617 * the frame register number;
618 * the size of the stack frame;
619 * the offsets of saved regs (relative to the old SP); and
620 * the offset from the stack pointer to the frame pointer
622 The cache contains only one entry, since this is adequate for the
623 typical sequence of prologue scan requests we get. When performing
624 a backtrace, GDB will usually ask to scan the same function twice
625 in a row (once to get the frame chain, and once to fill in the
626 extra frame information). */
628 static struct frame_info prologue_cache
;
631 check_prologue_cache (struct frame_info
*fi
)
635 if (fi
->pc
== prologue_cache
.pc
)
637 fi
->framereg
= prologue_cache
.framereg
;
638 fi
->framesize
= prologue_cache
.framesize
;
639 fi
->frameoffset
= prologue_cache
.frameoffset
;
640 for (i
= 0; i
< NUM_REGS
; i
++)
641 fi
->fsr
.regs
[i
] = prologue_cache
.fsr
.regs
[i
];
649 /* Copy the prologue information from fi to the prologue cache. */
652 save_prologue_cache (struct frame_info
*fi
)
656 prologue_cache
.pc
= fi
->pc
;
657 prologue_cache
.framereg
= fi
->framereg
;
658 prologue_cache
.framesize
= fi
->framesize
;
659 prologue_cache
.frameoffset
= fi
->frameoffset
;
661 for (i
= 0; i
< NUM_REGS
; i
++)
662 prologue_cache
.fsr
.regs
[i
] = fi
->fsr
.regs
[i
];
666 /* This function decodes an ARM function prologue to determine:
667 1) the size of the stack frame
668 2) which registers are saved on it
669 3) the offsets of saved regs
670 4) the offset from the stack pointer to the frame pointer
671 This information is stored in the "extra" fields of the frame_info.
673 There are two basic forms for the ARM prologue. The fixed argument
674 function call will look like:
677 stmfd sp!, {fp, ip, lr, pc}
681 Which would create this stack frame (offsets relative to FP):
682 IP -> 4 (caller's stack)
683 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
684 -4 LR (return address in caller)
685 -8 IP (copy of caller's SP)
687 SP -> -28 Local variables
689 The frame size would thus be 32 bytes, and the frame offset would be
690 28 bytes. The stmfd call can also save any of the vN registers it
691 plans to use, which increases the frame size accordingly.
693 Note: The stored PC is 8 off of the STMFD instruction that stored it
694 because the ARM Store instructions always store PC + 8 when you read
697 A variable argument function call will look like:
700 stmfd sp!, {a1, a2, a3, a4}
701 stmfd sp!, {fp, ip, lr, pc}
704 Which would create this stack frame (offsets relative to FP):
705 IP -> 20 (caller's stack)
710 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
711 -4 LR (return address in caller)
712 -8 IP (copy of caller's SP)
714 SP -> -28 Local variables
716 The frame size would thus be 48 bytes, and the frame offset would be
719 There is another potential complication, which is that the optimizer
720 will try to separate the store of fp in the "stmfd" instruction from
721 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
722 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
724 Also, note, the original version of the ARM toolchain claimed that there
727 instruction at the end of the prologue. I have never seen GCC produce
728 this, and the ARM docs don't mention it. We still test for it below in
734 arm_scan_prologue (struct frame_info
*fi
)
736 int regno
, sp_offset
, fp_offset
;
737 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
739 /* Check if this function is already in the cache of frame information. */
740 if (check_prologue_cache (fi
))
743 /* Assume there is no frame until proven otherwise. */
744 fi
->framereg
= SP_REGNUM
;
748 /* Check for Thumb prologue. */
749 if (arm_pc_is_thumb (fi
->pc
))
751 thumb_scan_prologue (fi
);
752 save_prologue_cache (fi
);
756 /* Find the function prologue. If we can't find the function in
757 the symbol table, peek in the stack frame to find the PC. */
758 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
760 /* One way to find the end of the prologue (which works well
761 for unoptimized code) is to do the following:
763 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
766 prologue_end = fi->pc;
767 else if (sal.end < prologue_end)
768 prologue_end = sal.end;
770 This mechanism is very accurate so long as the optimizer
771 doesn't move any instructions from the function body into the
772 prologue. If this happens, sal.end will be the last
773 instruction in the first hunk of prologue code just before
774 the first instruction that the scheduler has moved from
775 the body to the prologue.
777 In order to make sure that we scan all of the prologue
778 instructions, we use a slightly less accurate mechanism which
779 may scan more than necessary. To help compensate for this
780 lack of accuracy, the prologue scanning loop below contains
781 several clauses which'll cause the loop to terminate early if
782 an implausible prologue instruction is encountered.
788 is a suitable endpoint since it accounts for the largest
789 possible prologue plus up to five instructions inserted by
792 if (prologue_end
> prologue_start
+ 64)
794 prologue_end
= prologue_start
+ 64; /* See above. */
799 /* Get address of the stmfd in the prologue of the callee; the saved
800 PC is the address of the stmfd + 8. */
801 prologue_start
= ADDR_BITS_REMOVE (read_memory_integer (fi
->frame
, 4))
803 prologue_end
= prologue_start
+ 64; /* See above. */
806 /* Now search the prologue looking for instructions that set up the
807 frame pointer, adjust the stack pointer, and save registers.
809 Be careful, however, and if it doesn't look like a prologue,
810 don't try to scan it. If, for instance, a frameless function
811 begins with stmfd sp!, then we will tell ourselves there is
812 a frame, which will confuse stack traceback, as well ad"finish"
813 and other operations that rely on a knowledge of the stack
816 In the APCS, the prologue should start with "mov ip, sp" so
817 if we don't see this as the first insn, we will stop. */
819 sp_offset
= fp_offset
= 0;
821 if (read_memory_unsigned_integer (prologue_start
, 4)
822 == 0xe1a0c00d) /* mov ip, sp */
824 for (current_pc
= prologue_start
+ 4; current_pc
< prologue_end
;
827 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
829 if ((insn
& 0xffff0000) == 0xe92d0000)
830 /* stmfd sp!, {..., fp, ip, lr, pc}
832 stmfd sp!, {a1, a2, a3, a4} */
834 int mask
= insn
& 0xffff;
836 /* Calculate offsets of saved registers. */
837 for (regno
= PC_REGNUM
; regno
>= 0; regno
--)
838 if (mask
& (1 << regno
))
841 fi
->fsr
.regs
[regno
] = sp_offset
;
844 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
846 unsigned imm
= insn
& 0xff; /* immediate value */
847 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
848 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
850 fi
->framereg
= FP_REGNUM
;
852 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
854 unsigned imm
= insn
& 0xff; /* immediate value */
855 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
856 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
859 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
862 regno
= F0_REGNUM
+ ((insn
>> 12) & 0x07);
863 fi
->fsr
.regs
[regno
] = sp_offset
;
865 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
868 unsigned int fp_start_reg
, fp_bound_reg
;
870 if ((insn
& 0x800) == 0x800) /* N0 is set */
872 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
879 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
885 fp_start_reg
= F0_REGNUM
+ ((insn
>> 12) & 0x7);
886 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
887 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
890 fi
->fsr
.regs
[fp_start_reg
++] = sp_offset
;
893 else if ((insn
& 0xf0000000) != 0xe0000000)
894 break; /* Condition not true, exit early */
895 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
896 break; /* Don't scan past a block load */
898 /* The optimizer might shove anything into the prologue,
899 so we just skip what we don't recognize. */
904 /* The frame size is just the negative of the offset (from the original SP)
905 of the last thing thing we pushed on the stack. The frame offset is
906 [new FP] - [new SP]. */
907 fi
->framesize
= -sp_offset
;
908 fi
->frameoffset
= fp_offset
- sp_offset
;
910 save_prologue_cache (fi
);
913 /* Find REGNUM on the stack. Otherwise, it's in an active register.
914 One thing we might want to do here is to check REGNUM against the
915 clobber mask, and somehow flag it as invalid if it isn't saved on
916 the stack somewhere. This would provide a graceful failure mode
917 when trying to get the value of caller-saves registers for an inner
921 arm_find_callers_reg (struct frame_info
*fi
, int regnum
)
923 for (; fi
; fi
= fi
->next
)
925 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
926 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
927 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
930 if (fi
->fsr
.regs
[regnum
] != 0)
931 return read_memory_integer (fi
->fsr
.regs
[regnum
],
932 REGISTER_RAW_SIZE (regnum
));
933 return read_register (regnum
);
936 /* Function: frame_chain
937 Given a GDB frame, determine the address of the calling function's frame.
938 This will be used to create a new GDB frame struct, and then
939 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
940 For ARM, we save the frame size when we initialize the frame_info.
942 The original definition of this function was a macro in tm-arm.h:
943 { In the case of the ARM, the frame's nominal address is the FP value,
944 and 12 bytes before comes the saved previous FP value as a 4-byte word. }
946 #define FRAME_CHAIN(thisframe) \
947 ((thisframe)->pc >= LOWEST_PC ? \
948 read_memory_integer ((thisframe)->frame - 12, 4) :\
954 arm_frame_chain (struct frame_info
*fi
)
956 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
957 CORE_ADDR fn_start
, callers_pc
, fp
;
959 /* is this a dummy frame? */
960 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
961 return fi
->frame
; /* dummy frame same as caller's frame */
963 /* is caller-of-this a dummy frame? */
964 callers_pc
= FRAME_SAVED_PC (fi
); /* find out who called us: */
965 fp
= arm_find_callers_reg (fi
, FP_REGNUM
);
966 if (PC_IN_CALL_DUMMY (callers_pc
, fp
, fp
))
967 return fp
; /* dummy frame's frame may bear no relation to ours */
969 if (find_pc_partial_function (fi
->pc
, 0, &fn_start
, 0))
970 if (fn_start
== entry_point_address ())
971 return 0; /* in _start fn, don't chain further */
973 CORE_ADDR caller_pc
, fn_start
;
974 struct frame_info caller_fi
;
975 int framereg
= fi
->framereg
;
977 if (fi
->pc
< LOWEST_PC
)
980 /* If the caller is the startup code, we're at the end of the chain. */
981 caller_pc
= FRAME_SAVED_PC (fi
);
982 if (find_pc_partial_function (caller_pc
, 0, &fn_start
, 0))
983 if (fn_start
== entry_point_address ())
986 /* If the caller is Thumb and the caller is ARM, or vice versa,
987 the frame register of the caller is different from ours.
988 So we must scan the prologue of the caller to determine its
989 frame register number. */
990 if (arm_pc_is_thumb (caller_pc
) != arm_pc_is_thumb (fi
->pc
))
992 memset (&caller_fi
, 0, sizeof (caller_fi
));
993 caller_fi
.pc
= caller_pc
;
994 arm_scan_prologue (&caller_fi
);
995 framereg
= caller_fi
.framereg
;
998 /* If the caller used a frame register, return its value.
999 Otherwise, return the caller's stack pointer. */
1000 if (framereg
== FP_REGNUM
|| framereg
== THUMB_FP_REGNUM
)
1001 return arm_find_callers_reg (fi
, framereg
);
1003 return fi
->frame
+ fi
->framesize
;
1006 /* This function actually figures out the frame address for a given pc
1007 and sp. This is tricky because we sometimes don't use an explicit
1008 frame pointer, and the previous stack pointer isn't necessarily
1009 recorded on the stack. The only reliable way to get this info is
1010 to examine the prologue. FROMLEAF is a little confusing, it means
1011 this is the next frame up the chain AFTER a frameless function. If
1012 this is true, then the frame value for this frame is still in the
1016 arm_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1021 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1023 memset (fi
->fsr
.regs
, '\000', sizeof fi
->fsr
.regs
);
1025 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1026 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1028 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1029 by assuming it's always FP. */
1030 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
, SP_REGNUM
);
1032 fi
->frameoffset
= 0;
1038 /* Determine whether or not we're in a sigtramp frame.
1039 Unfortunately, it isn't sufficient to test
1040 fi->signal_handler_caller because this value is sometimes set
1041 after invoking INIT_EXTRA_FRAME_INFO. So we test *both*
1042 fi->signal_handler_caller and IN_SIGTRAMP to determine if we need
1043 to use the sigcontext addresses for the saved registers.
1045 Note: If an ARM IN_SIGTRAMP method ever needs to compare against
1046 the name of the function, the code below will have to be changed
1047 to first fetch the name of the function and then pass this name
1050 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1051 && (fi
->signal_handler_caller
|| IN_SIGTRAMP (fi
->pc
, 0)))
1058 sp
= fi
->next
->frame
- fi
->next
->frameoffset
+ fi
->next
->framesize
;
1060 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1061 fi
->fsr
.regs
[reg
] = SIGCONTEXT_REGISTER_ADDRESS (sp
, fi
->pc
, reg
);
1063 /* FIXME: What about thumb mode? */
1064 fi
->framereg
= SP_REGNUM
;
1065 fi
->frame
= read_memory_integer (fi
->fsr
.regs
[fi
->framereg
], 4);
1067 fi
->frameoffset
= 0;
1072 arm_scan_prologue (fi
);
1075 /* this is the innermost frame? */
1076 fi
->frame
= read_register (fi
->framereg
);
1077 else if (fi
->framereg
== FP_REGNUM
|| fi
->framereg
== THUMB_FP_REGNUM
)
1079 /* not the innermost frame */
1080 /* If we have an FP, the callee saved it. */
1081 if (fi
->next
->fsr
.regs
[fi
->framereg
] != 0)
1083 read_memory_integer (fi
->next
->fsr
.regs
[fi
->framereg
], 4);
1085 /* If we were called by a frameless fn. then our frame is
1086 still in the frame pointer register on the board... */
1087 fi
->frame
= read_fp ();
1090 /* Calculate actual addresses of saved registers using offsets
1091 determined by arm_scan_prologue. */
1092 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1093 if (fi
->fsr
.regs
[reg
] != 0)
1094 fi
->fsr
.regs
[reg
] += fi
->frame
+ fi
->framesize
- fi
->frameoffset
;
1099 /* Find the caller of this frame. We do this by seeing if LR_REGNUM
1100 is saved in the stack anywhere, otherwise we get it from the
1103 The old definition of this function was a macro:
1104 #define FRAME_SAVED_PC(FRAME) \
1105 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1108 arm_frame_saved_pc (struct frame_info
*fi
)
1110 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1111 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1112 return generic_read_register_dummy (fi
->pc
, fi
->frame
, PC_REGNUM
);
1116 CORE_ADDR pc
= arm_find_callers_reg (fi
, LR_REGNUM
);
1117 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1121 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1122 Examine the Program Status Register to decide which state we're in. */
1125 arm_target_read_fp (void)
1127 if (read_register (PS_REGNUM
) & 0x20) /* Bit 5 is Thumb state bit */
1128 return read_register (THUMB_FP_REGNUM
); /* R7 if Thumb */
1130 return read_register (FP_REGNUM
); /* R11 if ARM */
1133 /* Calculate the frame offsets of the saved registers (ARM version). */
1136 arm_frame_find_saved_regs (struct frame_info
*fi
,
1137 struct frame_saved_regs
*regaddr
)
1139 memcpy (regaddr
, &fi
->fsr
, sizeof (struct frame_saved_regs
));
1143 arm_push_dummy_frame (void)
1145 CORE_ADDR old_sp
= read_register (SP_REGNUM
);
1146 CORE_ADDR sp
= old_sp
;
1147 CORE_ADDR fp
, prologue_start
;
1150 /* Push the two dummy prologue instructions in reverse order,
1151 so that they'll be in the correct low-to-high order in memory. */
1152 /* sub fp, ip, #4 */
1153 sp
= push_word (sp
, 0xe24cb004);
1154 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1155 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
1157 /* Push a pointer to the dummy prologue + 12, because when stm
1158 instruction stores the PC, it stores the address of the stm
1159 instruction itself plus 12. */
1160 fp
= sp
= push_word (sp
, prologue_start
+ 12);
1161 sp
= push_word (sp
, read_register (PC_REGNUM
)); /* FIXME: was PS_REGNUM */
1162 sp
= push_word (sp
, old_sp
);
1163 sp
= push_word (sp
, read_register (FP_REGNUM
));
1165 for (regnum
= 10; regnum
>= 0; regnum
--)
1166 sp
= push_word (sp
, read_register (regnum
));
1168 write_register (FP_REGNUM
, fp
);
1169 write_register (THUMB_FP_REGNUM
, fp
);
1170 write_register (SP_REGNUM
, sp
);
1173 /* Fix up the call dummy, based on whether the processor is currently
1174 in Thumb or ARM mode, and whether the target function is Thumb or
1175 ARM. There are three different situations requiring three
1178 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1179 been copied into the dummy parameter to this function.
1180 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1181 "mov pc,r4" instruction patched to be a "bx r4" instead.
1182 * Thumb calling anything: uses the Thumb dummy defined below, which
1183 works for calling both ARM and Thumb functions.
1185 All three call dummies expect to receive the target function
1186 address in R4, with the low bit set if it's a Thumb function. */
1189 arm_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
1190 struct value
**args
, struct type
*type
, int gcc_p
)
1192 static short thumb_dummy
[4] =
1194 0xf000, 0xf801, /* bl label */
1195 0xdf18, /* swi 24 */
1196 0x4720, /* label: bx r4 */
1198 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
1200 /* Set flag indicating whether the current PC is in a Thumb function. */
1201 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
1203 /* If the target function is Thumb, set the low bit of the function
1204 address. And if the CPU is currently in ARM mode, patch the
1205 second instruction of call dummy to use a BX instruction to
1206 switch to Thumb mode. */
1207 target_is_thumb
= arm_pc_is_thumb (fun
);
1208 if (target_is_thumb
)
1211 if (!caller_is_thumb
)
1212 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
1215 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1216 instead of the ARM one that's already been copied. This will
1217 work for both Thumb and ARM target functions. */
1218 if (caller_is_thumb
)
1222 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
1224 for (i
= 0; i
< len
; i
++)
1226 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1227 p
+= sizeof (thumb_dummy
[0]);
1231 /* Put the target address in r4; the call dummy will copy this to
1233 write_register (4, fun
);
1236 /* Return the offset in the call dummy of the instruction that needs
1237 to have a breakpoint placed on it. This is the offset of the 'swi
1238 24' instruction, which is no longer actually used, but simply acts
1239 as a place-holder now.
1241 This implements the CALL_DUMMY_BREAK_OFFSET macro. */
1244 arm_call_dummy_breakpoint_offset (void)
1246 if (caller_is_thumb
)
1254 This function does not support passing parameters using the FPA
1255 variant of the APCS. It passes any floating point arguments in the
1256 general registers and/or on the stack. */
1259 arm_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
1260 int struct_return
, CORE_ADDR struct_addr
)
1263 int argnum
, argreg
, nstack_size
;
1265 /* Walk through the list of args and determine how large a temporary
1266 stack is required. Need to take care here as structs may be
1267 passed on the stack, and we have to to push them. */
1268 nstack_size
= -4 * REGISTER_SIZE
; /* Some arguments go into A1-A4. */
1269 if (struct_return
) /* The struct address goes in A1. */
1270 nstack_size
+= REGISTER_SIZE
;
1272 /* Walk through the arguments and add their size to nstack_size. */
1273 for (argnum
= 0; argnum
< nargs
; argnum
++)
1276 struct type
*arg_type
;
1278 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1279 len
= TYPE_LENGTH (arg_type
);
1281 /* ANSI C code passes float arguments as integers, K&R code
1282 passes float arguments as doubles. Correct for this here. */
1283 if (TYPE_CODE_FLT
== TYPE_CODE (arg_type
) && REGISTER_SIZE
== len
)
1284 nstack_size
+= FP_REGISTER_VIRTUAL_SIZE
;
1289 /* Allocate room on the stack, and initialize our stack frame
1292 if (nstack_size
> 0)
1298 /* Initialize the integer argument register pointer. */
1301 /* The struct_return pointer occupies the first parameter passing
1304 write_register (argreg
++, struct_addr
);
1306 /* Process arguments from left to right. Store as many as allowed
1307 in the parameter passing registers (A1-A4), and save the rest on
1308 the temporary stack. */
1309 for (argnum
= 0; argnum
< nargs
; argnum
++)
1315 enum type_code typecode
;
1316 struct type
*arg_type
, *target_type
;
1318 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1319 target_type
= TYPE_TARGET_TYPE (arg_type
);
1320 len
= TYPE_LENGTH (arg_type
);
1321 typecode
= TYPE_CODE (arg_type
);
1322 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
1324 /* ANSI C code passes float arguments as integers, K&R code
1325 passes float arguments as doubles. The .stabs record for
1326 for ANSI prototype floating point arguments records the
1327 type as FP_INTEGER, while a K&R style (no prototype)
1328 .stabs records the type as FP_FLOAT. In this latter case
1329 the compiler converts the float arguments to double before
1330 calling the function. */
1331 if (TYPE_CODE_FLT
== typecode
&& REGISTER_SIZE
== len
)
1335 char * bufo
= (char *) &d
;
1336 char * bufd
= (char *) &dbl_arg
;
1338 len
= sizeof (double);
1340 SWAP_TARGET_AND_HOST (&f
, sizeof (float)); /* adjust endianess */
1342 /* We must revert the longwords so they get loaded into the
1343 the right registers. */
1344 memcpy (bufd
, bufo
+ len
/ 2, len
/ 2);
1345 SWAP_TARGET_AND_HOST (bufd
, len
/ 2); /* adjust endianess */
1346 memcpy (bufd
+ len
/ 2, bufo
, len
/ 2);
1347 SWAP_TARGET_AND_HOST (bufd
+ len
/ 2, len
/ 2); /* adjust endianess */
1348 val
= (char *) &dbl_arg
;
1351 /* I don't know why this code was disable. The only logical use
1352 for a function pointer is to call that function, so setting
1353 the mode bit is perfectly fine. FN */
1354 /* If the argument is a pointer to a function, and it is a Thumb
1355 function, set the low bit of the pointer. */
1356 if (TYPE_CODE_PTR
== typecode
1357 && NULL
!= target_type
1358 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1360 CORE_ADDR regval
= extract_address (val
, len
);
1361 if (arm_pc_is_thumb (regval
))
1362 store_address (val
, len
, MAKE_THUMB_ADDR (regval
));
1365 /* Copy the argument to general registers or the stack in
1366 register-sized pieces. Large arguments are split between
1367 registers and stack. */
1370 int partial_len
= len
< REGISTER_SIZE
? len
: REGISTER_SIZE
;
1372 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1374 /* It's an argument being passed in a general register. */
1375 regval
= extract_address (val
, partial_len
);
1376 write_register (argreg
++, regval
);
1380 /* Push the arguments onto the stack. */
1381 write_memory ((CORE_ADDR
) fp
, val
, REGISTER_SIZE
);
1382 fp
+= REGISTER_SIZE
;
1390 /* Return adjusted stack pointer. */
1395 arm_pop_frame (void)
1398 struct frame_info
*frame
= get_current_frame ();
1400 if (!PC_IN_CALL_DUMMY(frame
->pc
, frame
->frame
, read_fp()))
1404 old_SP
= read_register (frame
->framereg
);
1405 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1406 if (frame
->fsr
.regs
[regnum
] != 0)
1407 write_register (regnum
,
1408 read_memory_integer (frame
->fsr
.regs
[regnum
], 4));
1410 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
1411 write_register (SP_REGNUM
, old_SP
);
1417 sp
= read_register (FP_REGNUM
);
1418 sp
-= sizeof(CORE_ADDR
); /* we don't care about this first word */
1420 write_register (PC_REGNUM
, read_memory_integer (sp
, 4));
1421 sp
-= sizeof(CORE_ADDR
);
1422 write_register (SP_REGNUM
, read_memory_integer (sp
, 4));
1423 sp
-= sizeof(CORE_ADDR
);
1424 write_register (FP_REGNUM
, read_memory_integer (sp
, 4));
1425 sp
-= sizeof(CORE_ADDR
);
1427 for (regnum
= 10; regnum
>= 0; regnum
--)
1429 write_register (regnum
, read_memory_integer (sp
, 4));
1430 sp
-= sizeof(CORE_ADDR
);
1434 flush_cached_frames ();
1438 print_fpu_flags (int flags
)
1440 if (flags
& (1 << 0))
1441 fputs ("IVO ", stdout
);
1442 if (flags
& (1 << 1))
1443 fputs ("DVZ ", stdout
);
1444 if (flags
& (1 << 2))
1445 fputs ("OFL ", stdout
);
1446 if (flags
& (1 << 3))
1447 fputs ("UFL ", stdout
);
1448 if (flags
& (1 << 4))
1449 fputs ("INX ", stdout
);
1454 arm_float_info (void)
1456 register unsigned long status
= read_register (FPS_REGNUM
);
1459 type
= (status
>> 24) & 127;
1460 printf ("%s FPU type %d\n",
1461 (status
& (1 << 31)) ? "Hardware" : "Software",
1463 fputs ("mask: ", stdout
);
1464 print_fpu_flags (status
>> 16);
1465 fputs ("flags: ", stdout
);
1466 print_fpu_flags (status
);
1470 /* FIXME: The generated assembler works but sucks. Instead of using
1471 r0, r1 it pushes them on the stack, then loads them into r3, r4 and
1472 uses those registers. I must be missing something. ScottB */
1475 convert_from_extended (void *ptr
, void *dbl
)
1481 : "r" (ptr
), "r" (dbl
));
1485 convert_to_extended (void *dbl
, void *ptr
)
1491 : "r" (dbl
), "r" (ptr
));
1495 convert_from_extended (void *ptr
, void *dbl
)
1497 *(double *) dbl
= *(double *) ptr
;
1501 convert_to_extended (void *dbl
, void *ptr
)
1503 *(double *) ptr
= *(double *) dbl
;
1507 /* Nonzero if register N requires conversion from raw format to
1511 arm_register_convertible (unsigned int regnum
)
1513 return ((regnum
- F0_REGNUM
) < 8);
1516 /* Convert data from raw format for register REGNUM in buffer FROM to
1517 virtual format with type TYPE in buffer TO. */
1520 arm_register_convert_to_virtual (unsigned int regnum
, struct type
*type
,
1521 void *from
, void *to
)
1525 convert_from_extended (from
, &val
);
1526 store_floating (to
, TYPE_LENGTH (type
), val
);
1529 /* Convert data from virtual format with type TYPE in buffer FROM to
1530 raw format for register REGNUM in buffer TO. */
1533 arm_register_convert_to_raw (unsigned int regnum
, struct type
*type
,
1534 void *from
, void *to
)
1536 double val
= extract_floating (from
, TYPE_LENGTH (type
));
1538 convert_to_extended (&val
, to
);
1542 condition_true (unsigned long cond
, unsigned long status_reg
)
1544 if (cond
== INST_AL
|| cond
== INST_NV
)
1550 return ((status_reg
& FLAG_Z
) != 0);
1552 return ((status_reg
& FLAG_Z
) == 0);
1554 return ((status_reg
& FLAG_C
) != 0);
1556 return ((status_reg
& FLAG_C
) == 0);
1558 return ((status_reg
& FLAG_N
) != 0);
1560 return ((status_reg
& FLAG_N
) == 0);
1562 return ((status_reg
& FLAG_V
) != 0);
1564 return ((status_reg
& FLAG_V
) == 0);
1566 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1568 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1570 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1572 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1574 return (((status_reg
& FLAG_Z
) == 0) &&
1575 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1577 return (((status_reg
& FLAG_Z
) != 0) ||
1578 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1583 #define submask(x) ((1L << ((x) + 1)) - 1)
1584 #define bit(obj,st) (((obj) >> (st)) & 1)
1585 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1586 #define sbits(obj,st,fn) \
1587 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1588 #define BranchDest(addr,instr) \
1589 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1592 static unsigned long
1593 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1594 unsigned long status_reg
)
1596 unsigned long res
, shift
;
1597 int rm
= bits (inst
, 0, 3);
1598 unsigned long shifttype
= bits (inst
, 5, 6);
1602 int rs
= bits (inst
, 8, 11);
1603 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1606 shift
= bits (inst
, 7, 11);
1609 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1610 + (bit (inst
, 4) ? 12 : 8))
1611 : read_register (rm
));
1616 res
= shift
>= 32 ? 0 : res
<< shift
;
1620 res
= shift
>= 32 ? 0 : res
>> shift
;
1626 res
= ((res
& 0x80000000L
)
1627 ? ~((~res
) >> shift
) : res
>> shift
);
1630 case 3: /* ROR/RRX */
1633 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1635 res
= (res
>> shift
) | (res
<< (32 - shift
));
1639 return res
& 0xffffffff;
1642 /* Return number of 1-bits in VAL. */
1645 bitcount (unsigned long val
)
1648 for (nbits
= 0; val
!= 0; nbits
++)
1649 val
&= val
- 1; /* delete rightmost 1-bit in val */
1654 thumb_get_next_pc (CORE_ADDR pc
)
1656 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1657 unsigned short inst1
= read_memory_integer (pc
, 2);
1658 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1659 unsigned long offset
;
1661 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1665 /* Fetch the saved PC from the stack. It's stored above
1666 all of the other registers. */
1667 offset
= bitcount (bits (inst1
, 0, 7)) * REGISTER_SIZE
;
1668 sp
= read_register (SP_REGNUM
);
1669 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1670 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1672 error ("Infinite loop detected");
1674 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1676 unsigned long status
= read_register (PS_REGNUM
);
1677 unsigned long cond
= bits (inst1
, 8, 11);
1678 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1679 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1681 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1683 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1685 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1687 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1688 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1689 nextpc
= pc_val
+ offset
;
1696 arm_get_next_pc (CORE_ADDR pc
)
1698 unsigned long pc_val
;
1699 unsigned long this_instr
;
1700 unsigned long status
;
1703 if (arm_pc_is_thumb (pc
))
1704 return thumb_get_next_pc (pc
);
1706 pc_val
= (unsigned long) pc
;
1707 this_instr
= read_memory_integer (pc
, 4);
1708 status
= read_register (PS_REGNUM
);
1709 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1711 if (condition_true (bits (this_instr
, 28, 31), status
))
1713 switch (bits (this_instr
, 24, 27))
1716 case 0x1: /* data processing */
1720 unsigned long operand1
, operand2
, result
= 0;
1724 if (bits (this_instr
, 12, 15) != 15)
1727 if (bits (this_instr
, 22, 25) == 0
1728 && bits (this_instr
, 4, 7) == 9) /* multiply */
1729 error ("Illegal update to pc in instruction");
1731 /* Multiply into PC */
1732 c
= (status
& FLAG_C
) ? 1 : 0;
1733 rn
= bits (this_instr
, 16, 19);
1734 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1736 if (bit (this_instr
, 25))
1738 unsigned long immval
= bits (this_instr
, 0, 7);
1739 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1740 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1743 else /* operand 2 is a shifted register */
1744 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1746 switch (bits (this_instr
, 21, 24))
1749 result
= operand1
& operand2
;
1753 result
= operand1
^ operand2
;
1757 result
= operand1
- operand2
;
1761 result
= operand2
- operand1
;
1765 result
= operand1
+ operand2
;
1769 result
= operand1
+ operand2
+ c
;
1773 result
= operand1
- operand2
+ c
;
1777 result
= operand2
- operand1
+ c
;
1783 case 0xb: /* tst, teq, cmp, cmn */
1784 result
= (unsigned long) nextpc
;
1788 result
= operand1
| operand2
;
1792 /* Always step into a function. */
1797 result
= operand1
& ~operand2
;
1804 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1807 error ("Infinite loop detected");
1812 case 0x5: /* data transfer */
1815 if (bit (this_instr
, 20))
1818 if (bits (this_instr
, 12, 15) == 15)
1824 if (bit (this_instr
, 22))
1825 error ("Illegal update to pc in instruction");
1827 /* byte write to PC */
1828 rn
= bits (this_instr
, 16, 19);
1829 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1830 if (bit (this_instr
, 24))
1833 int c
= (status
& FLAG_C
) ? 1 : 0;
1834 unsigned long offset
=
1835 (bit (this_instr
, 25)
1836 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1837 : bits (this_instr
, 0, 11));
1839 if (bit (this_instr
, 23))
1844 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1847 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1850 error ("Infinite loop detected");
1856 case 0x9: /* block transfer */
1857 if (bit (this_instr
, 20))
1860 if (bit (this_instr
, 15))
1865 if (bit (this_instr
, 23))
1868 unsigned long reglist
= bits (this_instr
, 0, 14);
1869 offset
= bitcount (reglist
) * 4;
1870 if (bit (this_instr
, 24)) /* pre */
1873 else if (bit (this_instr
, 24))
1877 unsigned long rn_val
=
1878 read_register (bits (this_instr
, 16, 19));
1880 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1884 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1886 error ("Infinite loop detected");
1891 case 0xb: /* branch & link */
1892 case 0xa: /* branch */
1894 nextpc
= BranchDest (pc
, this_instr
);
1896 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1898 error ("Infinite loop detected");
1904 case 0xe: /* coproc ops */
1909 fprintf (stderr
, "Bad bit-field extraction\n");
1917 #include "bfd-in2.h"
1918 #include "libcoff.h"
1921 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
1923 if (arm_pc_is_thumb (memaddr
))
1925 static asymbol
*asym
;
1926 static combined_entry_type ce
;
1927 static struct coff_symbol_struct csym
;
1928 static struct _bfd fake_bfd
;
1929 static bfd_target fake_target
;
1931 if (csym
.native
== NULL
)
1933 /* Create a fake symbol vector containing a Thumb symbol. This is
1934 solely so that the code in print_insn_little_arm() and
1935 print_insn_big_arm() in opcodes/arm-dis.c will detect the presence
1936 of a Thumb symbol and switch to decoding Thumb instructions. */
1938 fake_target
.flavour
= bfd_target_coff_flavour
;
1939 fake_bfd
.xvec
= &fake_target
;
1940 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
1942 csym
.symbol
.the_bfd
= &fake_bfd
;
1943 csym
.symbol
.name
= "fake";
1944 asym
= (asymbol
*) & csym
;
1947 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
1948 info
->symbols
= &asym
;
1951 info
->symbols
= NULL
;
1953 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1954 return print_insn_big_arm (memaddr
, info
);
1956 return print_insn_little_arm (memaddr
, info
);
1959 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the
1960 program counter value to determine whether a 16-bit or 32-bit
1961 breakpoint should be used. It returns a pointer to a string of
1962 bytes that encode a breakpoint instruction, stores the length of
1963 the string to *lenptr, and adjusts the program counter (if
1964 necessary) to point to the actual memory location where the
1965 breakpoint should be inserted. */
1968 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1970 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
1972 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1974 static char thumb_breakpoint
[] = THUMB_BE_BREAKPOINT
;
1975 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1976 *lenptr
= sizeof (thumb_breakpoint
);
1977 return thumb_breakpoint
;
1981 static char thumb_breakpoint
[] = THUMB_LE_BREAKPOINT
;
1982 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1983 *lenptr
= sizeof (thumb_breakpoint
);
1984 return thumb_breakpoint
;
1989 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1991 static char arm_breakpoint
[] = ARM_BE_BREAKPOINT
;
1992 *lenptr
= sizeof (arm_breakpoint
);
1993 return arm_breakpoint
;
1997 static char arm_breakpoint
[] = ARM_LE_BREAKPOINT
;
1998 *lenptr
= sizeof (arm_breakpoint
);
1999 return arm_breakpoint
;
2004 /* Extract from an array REGBUF containing the (raw) register state a
2005 function return value of type TYPE, and copy that, in virtual
2006 format, into VALBUF. */
2009 arm_extract_return_value (struct type
*type
,
2010 char regbuf
[REGISTER_BYTES
],
2013 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2014 convert_from_extended (®buf
[REGISTER_BYTE (F0_REGNUM
)], valbuf
);
2016 memcpy (valbuf
, ®buf
[REGISTER_BYTE (A1_REGNUM
)], TYPE_LENGTH (type
));
2019 /* Return non-zero if the PC is inside a thumb call thunk. */
2022 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2024 CORE_ADDR start_addr
;
2026 /* Find the starting address of the function containing the PC. If
2027 the caller didn't give us a name, look it up at the same time. */
2028 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
2031 return strncmp (name
, "_call_via_r", 11) == 0;
2034 /* If PC is in a Thumb call or return stub, return the address of the
2035 target PC, which is in a register. The thunk functions are called
2036 _called_via_xx, where x is the register name. The possible names
2037 are r0-r9, sl, fp, ip, sp, and lr. */
2040 arm_skip_stub (CORE_ADDR pc
)
2043 CORE_ADDR start_addr
;
2045 /* Find the starting address and name of the function containing the PC. */
2046 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2049 /* Call thunks always start with "_call_via_". */
2050 if (strncmp (name
, "_call_via_", 10) == 0)
2052 /* Use the name suffix to determine which register contains the
2054 static char *table
[15] =
2055 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2056 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2060 for (regno
= 0; regno
<= 14; regno
++)
2061 if (strcmp (&name
[10], table
[regno
]) == 0)
2062 return read_register (regno
);
2065 return 0; /* not a stub */
2068 /* If the user changes the register disassembly flavor used for info register
2069 and other commands, we have to also switch the flavor used in opcodes
2070 for disassembly output.
2071 This function is run in the set disassembly_flavor command, and does that. */
2074 set_disassembly_flavor_sfunc (char *args
, int from_tty
,
2075 struct cmd_list_element
*c
)
2077 set_disassembly_flavor ();
2081 set_disassembly_flavor (void)
2083 const char *setname
, *setdesc
, **regnames
;
2086 /* Find the flavor that the user wants in the opcodes table. */
2088 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2089 while ((disassembly_flavor
!= setname
)
2090 && (current
< num_flavor_options
))
2091 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2092 current_option
= current
;
2094 /* Fill our copy. */
2095 for (j
= 0; j
< numregs
; j
++)
2096 arm_register_names
[j
] = (char *) regnames
[j
];
2099 if (isupper (*regnames
[PC_REGNUM
]))
2101 arm_register_names
[FPS_REGNUM
] = "FPS";
2102 arm_register_names
[PS_REGNUM
] = "CPSR";
2106 arm_register_names
[FPS_REGNUM
] = "fps";
2107 arm_register_names
[PS_REGNUM
] = "cpsr";
2110 /* Synchronize the disassembler. */
2111 set_arm_regname_option (current
);
2114 /* arm_othernames implements the "othernames" command. This is kind
2115 of hacky, and I prefer the set-show disassembly-flavor which is
2116 also used for the x86 gdb. I will keep this around, however, in
2117 case anyone is actually using it. */
2120 arm_othernames (char *names
, int n
)
2122 /* Circle through the various flavors. */
2123 current_option
= (current_option
+ 1) % num_flavor_options
;
2125 disassembly_flavor
= valid_flavors
[current_option
];
2126 set_disassembly_flavor ();
2130 _initialize_arm_tdep (void)
2132 struct ui_file
*stb
;
2134 struct cmd_list_element
*new_cmd
;
2135 const char *setname
;
2136 const char *setdesc
;
2137 const char **regnames
;
2139 static char *helptext
;
2141 tm_print_insn
= gdb_print_insn_arm
;
2143 /* Get the number of possible sets of register names defined in opcodes. */
2144 num_flavor_options
= get_arm_regname_num_options ();
2146 /* Sync the opcode insn printer with our register viewer: */
2147 parse_arm_disassembler_option ("reg-names-std");
2149 /* Begin creating the help text. */
2150 stb
= mem_fileopen ();
2151 fprintf_unfiltered (stb
, "Set the disassembly flavor.\n\
2152 The valid values are:\n");
2154 /* Initialize the array that will be passed to add_set_enum_cmd(). */
2155 valid_flavors
= xmalloc ((num_flavor_options
+ 1) * sizeof (char *));
2156 for (i
= 0; i
< num_flavor_options
; i
++)
2158 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
2159 valid_flavors
[i
] = setname
;
2160 fprintf_unfiltered (stb
, "%s - %s\n", setname
,
2162 /* Copy the default names (if found) and synchronize disassembler. */
2163 if (!strcmp (setname
, "std"))
2165 disassembly_flavor
= setname
;
2167 for (j
= 0; j
< numregs
; j
++)
2168 arm_register_names
[j
] = (char *) regnames
[j
];
2169 set_arm_regname_option (i
);
2172 /* Mark the end of valid options. */
2173 valid_flavors
[num_flavor_options
] = NULL
;
2175 /* Finish the creation of the help text. */
2176 fprintf_unfiltered (stb
, "The default is \"std\".");
2177 helptext
= ui_file_xstrdup (stb
, &length
);
2178 ui_file_delete (stb
);
2180 /* Add the disassembly-flavor command */
2181 new_cmd
= add_set_enum_cmd ("disassembly-flavor", no_class
,
2183 &disassembly_flavor
,
2186 new_cmd
->function
.sfunc
= set_disassembly_flavor_sfunc
;
2187 add_show_from_set (new_cmd
, &showlist
);
2189 /* ??? Maybe this should be a boolean. */
2190 add_show_from_set (add_set_cmd ("apcs32", no_class
,
2191 var_zinteger
, (char *) &arm_apcs_32
,
2192 "Set usage of ARM 32-bit mode.\n", &setlist
),
2195 /* Add the deprecated "othernames" command */
2197 add_com ("othernames", class_obscure
, arm_othernames
,
2198 "Switch to the next set of register names.");
2201 /* Test whether the coff symbol specific value corresponds to a Thumb
2205 coff_sym_is_thumb (int val
)
2207 return (val
== C_THUMBEXT
||
2208 val
== C_THUMBSTAT
||
2209 val
== C_THUMBEXTFUNC
||
2210 val
== C_THUMBSTATFUNC
||
2211 val
== C_THUMBLABEL
);