1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2013 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
28 #include "gdb_string.h"
29 #include "dis-asm.h" /* For register styles. */
31 #include "reggroups.h"
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
49 #include "gdb/sim-arm.h"
52 #include "coff/internal.h"
55 #include "gdb_assert.h"
60 #include "features/arm-with-m.c"
61 #include "features/arm-with-m-fpa-layout.c"
62 #include "features/arm-with-m-vfp-d16.c"
63 #include "features/arm-with-iwmmxt.c"
64 #include "features/arm-with-vfpv2.c"
65 #include "features/arm-with-vfpv3.c"
66 #include "features/arm-with-neon.c"
70 /* Macros for setting and testing a bit in a minimal symbol that marks
71 it as Thumb function. The MSB of the minimal symbol's "info" field
72 is used for this purpose.
74 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
75 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
77 #define MSYMBOL_SET_SPECIAL(msym) \
78 MSYMBOL_TARGET_FLAG_1 (msym) = 1
80 #define MSYMBOL_IS_SPECIAL(msym) \
81 MSYMBOL_TARGET_FLAG_1 (msym)
83 /* Per-objfile data used for mapping symbols. */
84 static const struct objfile_data
*arm_objfile_data_key
;
86 struct arm_mapping_symbol
91 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
92 DEF_VEC_O(arm_mapping_symbol_s
);
94 struct arm_per_objfile
96 VEC(arm_mapping_symbol_s
) **section_maps
;
99 /* The list of available "set arm ..." and "show arm ..." commands. */
100 static struct cmd_list_element
*setarmcmdlist
= NULL
;
101 static struct cmd_list_element
*showarmcmdlist
= NULL
;
103 /* The type of floating-point to use. Keep this in sync with enum
104 arm_float_model, and the help string in _initialize_arm_tdep. */
105 static const char *const fp_model_strings
[] =
115 /* A variable that can be configured by the user. */
116 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
117 static const char *current_fp_model
= "auto";
119 /* The ABI to use. Keep this in sync with arm_abi_kind. */
120 static const char *const arm_abi_strings
[] =
128 /* A variable that can be configured by the user. */
129 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
130 static const char *arm_abi_string
= "auto";
132 /* The execution mode to assume. */
133 static const char *const arm_mode_strings
[] =
141 static const char *arm_fallback_mode_string
= "auto";
142 static const char *arm_force_mode_string
= "auto";
144 /* Internal override of the execution mode. -1 means no override,
145 0 means override to ARM mode, 1 means override to Thumb mode.
146 The effect is the same as if arm_force_mode has been set by the
147 user (except the internal override has precedence over a user's
148 arm_force_mode override). */
149 static int arm_override_mode
= -1;
151 /* Number of different reg name sets (options). */
152 static int num_disassembly_options
;
154 /* The standard register names, and all the valid aliases for them. Note
155 that `fp', `sp' and `pc' are not added in this alias list, because they
156 have been added as builtin user registers in
157 std-regs.c:_initialize_frame_reg. */
162 } arm_register_aliases
[] = {
163 /* Basic register numbers. */
180 /* Synonyms (argument and variable registers). */
193 /* Other platform-specific names for r9. */
199 /* Names used by GCC (not listed in the ARM EABI). */
201 /* A special name from the older ATPCS. */
205 static const char *const arm_register_names
[] =
206 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
207 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
208 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
209 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
210 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
211 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
212 "fps", "cpsr" }; /* 24 25 */
214 /* Valid register name styles. */
215 static const char **valid_disassembly_styles
;
217 /* Disassembly style to use. Default to "std" register names. */
218 static const char *disassembly_style
;
220 /* This is used to keep the bfd arch_info in sync with the disassembly
222 static void set_disassembly_style_sfunc(char *, int,
223 struct cmd_list_element
*);
224 static void set_disassembly_style (void);
226 static void convert_from_extended (const struct floatformat
*, const void *,
228 static void convert_to_extended (const struct floatformat
*, void *,
231 static enum register_status
arm_neon_quad_read (struct gdbarch
*gdbarch
,
232 struct regcache
*regcache
,
233 int regnum
, gdb_byte
*buf
);
234 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
235 struct regcache
*regcache
,
236 int regnum
, const gdb_byte
*buf
);
238 static int thumb_insn_size (unsigned short inst1
);
240 struct arm_prologue_cache
242 /* The stack pointer at the time this frame was created; i.e. the
243 caller's stack pointer when this function was called. It is used
244 to identify this frame. */
247 /* The frame base for this frame is just prev_sp - frame size.
248 FRAMESIZE is the distance from the frame pointer to the
249 initial stack pointer. */
253 /* The register used to hold the frame pointer for this frame. */
256 /* Saved register offsets. */
257 struct trad_frame_saved_reg
*saved_regs
;
260 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
261 CORE_ADDR prologue_start
,
262 CORE_ADDR prologue_end
,
263 struct arm_prologue_cache
*cache
);
265 /* Architecture version for displaced stepping. This effects the behaviour of
266 certain instructions, and really should not be hard-wired. */
268 #define DISPLACED_STEPPING_ARCH_VERSION 5
270 /* Addresses for calling Thumb functions have the bit 0 set.
271 Here are some macros to test, set, or clear bit 0 of addresses. */
272 #define IS_THUMB_ADDR(addr) ((addr) & 1)
273 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
274 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
276 /* Set to true if the 32-bit mode is in use. */
280 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
283 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
285 if (gdbarch_tdep (gdbarch
)->is_m
)
291 /* Determine if FRAME is executing in Thumb mode. */
294 arm_frame_is_thumb (struct frame_info
*frame
)
297 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
299 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
300 directly (from a signal frame or dummy frame) or by interpreting
301 the saved LR (from a prologue or DWARF frame). So consult it and
302 trust the unwinders. */
303 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
305 return (cpsr
& t_bit
) != 0;
308 /* Callback for VEC_lower_bound. */
311 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
312 const struct arm_mapping_symbol
*rhs
)
314 return lhs
->value
< rhs
->value
;
317 /* Search for the mapping symbol covering MEMADDR. If one is found,
318 return its type. Otherwise, return 0. If START is non-NULL,
319 set *START to the location of the mapping symbol. */
322 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
324 struct obj_section
*sec
;
326 /* If there are mapping symbols, consult them. */
327 sec
= find_pc_section (memaddr
);
330 struct arm_per_objfile
*data
;
331 VEC(arm_mapping_symbol_s
) *map
;
332 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
336 data
= objfile_data (sec
->objfile
, arm_objfile_data_key
);
339 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
340 if (!VEC_empty (arm_mapping_symbol_s
, map
))
342 struct arm_mapping_symbol
*map_sym
;
344 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
345 arm_compare_mapping_symbols
);
347 /* VEC_lower_bound finds the earliest ordered insertion
348 point. If the following symbol starts at this exact
349 address, we use that; otherwise, the preceding
350 mapping symbol covers this address. */
351 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
353 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
354 if (map_sym
->value
== map_key
.value
)
357 *start
= map_sym
->value
+ obj_section_addr (sec
);
358 return map_sym
->type
;
364 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
366 *start
= map_sym
->value
+ obj_section_addr (sec
);
367 return map_sym
->type
;
376 /* Determine if the program counter specified in MEMADDR is in a Thumb
377 function. This function should be called for addresses unrelated to
378 any executing frame; otherwise, prefer arm_frame_is_thumb. */
381 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
383 struct minimal_symbol
*sym
;
385 struct displaced_step_closure
* dsc
386 = get_displaced_step_closure_by_addr(memaddr
);
388 /* If checking the mode of displaced instruction in copy area, the mode
389 should be determined by instruction on the original address. */
393 fprintf_unfiltered (gdb_stdlog
,
394 "displaced: check mode of %.8lx instead of %.8lx\n",
395 (unsigned long) dsc
->insn_addr
,
396 (unsigned long) memaddr
);
397 memaddr
= dsc
->insn_addr
;
400 /* If bit 0 of the address is set, assume this is a Thumb address. */
401 if (IS_THUMB_ADDR (memaddr
))
404 /* Respect internal mode override if active. */
405 if (arm_override_mode
!= -1)
406 return arm_override_mode
;
408 /* If the user wants to override the symbol table, let him. */
409 if (strcmp (arm_force_mode_string
, "arm") == 0)
411 if (strcmp (arm_force_mode_string
, "thumb") == 0)
414 /* ARM v6-M and v7-M are always in Thumb mode. */
415 if (gdbarch_tdep (gdbarch
)->is_m
)
418 /* If there are mapping symbols, consult them. */
419 type
= arm_find_mapping_symbol (memaddr
, NULL
);
423 /* Thumb functions have a "special" bit set in minimal symbols. */
424 sym
= lookup_minimal_symbol_by_pc (memaddr
);
426 return (MSYMBOL_IS_SPECIAL (sym
));
428 /* If the user wants to override the fallback mode, let them. */
429 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
431 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
434 /* If we couldn't find any symbol, but we're talking to a running
435 target, then trust the current value of $cpsr. This lets
436 "display/i $pc" always show the correct mode (though if there is
437 a symbol table we will not reach here, so it still may not be
438 displayed in the mode it will be executed). */
439 if (target_has_registers
)
440 return arm_frame_is_thumb (get_current_frame ());
442 /* Otherwise we're out of luck; we assume ARM. */
446 /* Remove useless bits from addresses in a running program. */
448 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
450 /* On M-profile devices, do not strip the low bit from EXC_RETURN
451 (the magic exception return address). */
452 if (gdbarch_tdep (gdbarch
)->is_m
453 && (val
& 0xfffffff0) == 0xfffffff0)
457 return UNMAKE_THUMB_ADDR (val
);
459 return (val
& 0x03fffffc);
462 /* Return 1 if PC is the start of a compiler helper function which
463 can be safely ignored during prologue skipping. IS_THUMB is true
464 if the function is known to be a Thumb function due to the way it
467 skip_prologue_function (struct gdbarch
*gdbarch
, CORE_ADDR pc
, int is_thumb
)
469 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
470 struct minimal_symbol
*msym
;
472 msym
= lookup_minimal_symbol_by_pc (pc
);
474 && SYMBOL_VALUE_ADDRESS (msym
) == pc
475 && SYMBOL_LINKAGE_NAME (msym
) != NULL
)
477 const char *name
= SYMBOL_LINKAGE_NAME (msym
);
479 /* The GNU linker's Thumb call stub to foo is named
481 if (strstr (name
, "_from_thumb") != NULL
)
484 /* On soft-float targets, __truncdfsf2 is called to convert promoted
485 arguments to their argument types in non-prototyped
487 if (strncmp (name
, "__truncdfsf2", strlen ("__truncdfsf2")) == 0)
489 if (strncmp (name
, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
492 /* Internal functions related to thread-local storage. */
493 if (strncmp (name
, "__tls_get_addr", strlen ("__tls_get_addr")) == 0)
495 if (strncmp (name
, "__aeabi_read_tp", strlen ("__aeabi_read_tp")) == 0)
500 /* If we run against a stripped glibc, we may be unable to identify
501 special functions by name. Check for one important case,
502 __aeabi_read_tp, by comparing the *code* against the default
503 implementation (this is hand-written ARM assembler in glibc). */
506 && read_memory_unsigned_integer (pc
, 4, byte_order_for_code
)
507 == 0xe3e00a0f /* mov r0, #0xffff0fff */
508 && read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
)
509 == 0xe240f01f) /* sub pc, r0, #31 */
516 /* Support routines for instruction parsing. */
517 #define submask(x) ((1L << ((x) + 1)) - 1)
518 #define bit(obj,st) (((obj) >> (st)) & 1)
519 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
520 #define sbits(obj,st,fn) \
521 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
522 #define BranchDest(addr,instr) \
523 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
525 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
526 the first 16-bit of instruction, and INSN2 is the second 16-bit of
528 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
529 ((bits ((insn1), 0, 3) << 12) \
530 | (bits ((insn1), 10, 10) << 11) \
531 | (bits ((insn2), 12, 14) << 8) \
532 | bits ((insn2), 0, 7))
534 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
535 the 32-bit instruction. */
536 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
537 ((bits ((insn), 16, 19) << 12) \
538 | bits ((insn), 0, 11))
540 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
543 thumb_expand_immediate (unsigned int imm
)
545 unsigned int count
= imm
>> 7;
553 return (imm
& 0xff) | ((imm
& 0xff) << 16);
555 return ((imm
& 0xff) << 8) | ((imm
& 0xff) << 24);
557 return (imm
& 0xff) | ((imm
& 0xff) << 8)
558 | ((imm
& 0xff) << 16) | ((imm
& 0xff) << 24);
561 return (0x80 | (imm
& 0x7f)) << (32 - count
);
564 /* Return 1 if the 16-bit Thumb instruction INST might change
565 control flow, 0 otherwise. */
568 thumb_instruction_changes_pc (unsigned short inst
)
570 if ((inst
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
573 if ((inst
& 0xf000) == 0xd000) /* conditional branch */
576 if ((inst
& 0xf800) == 0xe000) /* unconditional branch */
579 if ((inst
& 0xff00) == 0x4700) /* bx REG, blx REG */
582 if ((inst
& 0xff87) == 0x4687) /* mov pc, REG */
585 if ((inst
& 0xf500) == 0xb100) /* CBNZ or CBZ. */
591 /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
592 might change control flow, 0 otherwise. */
595 thumb2_instruction_changes_pc (unsigned short inst1
, unsigned short inst2
)
597 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
599 /* Branches and miscellaneous control instructions. */
601 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
606 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
608 /* SUBS PC, LR, #imm8. */
611 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
613 /* Conditional branch. */
620 if ((inst1
& 0xfe50) == 0xe810)
622 /* Load multiple or RFE. */
624 if (bit (inst1
, 7) && !bit (inst1
, 8))
630 else if (!bit (inst1
, 7) && bit (inst1
, 8))
636 else if (bit (inst1
, 7) && bit (inst1
, 8))
641 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
650 if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
652 /* MOV PC or MOVS PC. */
656 if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
659 if (bits (inst1
, 0, 3) == 15)
665 if ((inst2
& 0x0fc0) == 0x0000)
671 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
677 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
686 /* Analyze a Thumb prologue, looking for a recognizable stack frame
687 and frame pointer. Scan until we encounter a store that could
688 clobber the stack frame unexpectedly, or an unknown instruction.
689 Return the last address which is definitely safe to skip for an
690 initial breakpoint. */
693 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
694 CORE_ADDR start
, CORE_ADDR limit
,
695 struct arm_prologue_cache
*cache
)
697 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
698 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
701 struct pv_area
*stack
;
702 struct cleanup
*back_to
;
704 CORE_ADDR unrecognized_pc
= 0;
706 for (i
= 0; i
< 16; i
++)
707 regs
[i
] = pv_register (i
, 0);
708 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
709 back_to
= make_cleanup_free_pv_area (stack
);
711 while (start
< limit
)
715 insn
= read_memory_unsigned_integer (start
, 2, byte_order_for_code
);
717 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
722 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
725 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
726 whether to save LR (R14). */
727 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
729 /* Calculate offsets of saved R0-R7 and LR. */
730 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
731 if (mask
& (1 << regno
))
733 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
735 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
738 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
741 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
742 if (insn
& 0x80) /* Check for SUB. */
743 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
746 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
749 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
750 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
752 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
753 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
754 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
756 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
757 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
758 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
760 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
761 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
762 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
763 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
764 regs
[bits (insn
, 6, 8)]);
765 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
766 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
768 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
769 int rm
= bits (insn
, 3, 6);
770 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
772 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
774 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
775 int src_reg
= (insn
& 0x78) >> 3;
776 regs
[dst_reg
] = regs
[src_reg
];
778 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
780 /* Handle stores to the stack. Normally pushes are used,
781 but with GCC -mtpcs-frame, there may be other stores
782 in the prologue to create the frame. */
783 int regno
= (insn
>> 8) & 0x7;
786 offset
= (insn
& 0xff) << 2;
787 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
789 if (pv_area_store_would_trash (stack
, addr
))
792 pv_area_store (stack
, addr
, 4, regs
[regno
]);
794 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
796 int rd
= bits (insn
, 0, 2);
797 int rn
= bits (insn
, 3, 5);
800 offset
= bits (insn
, 6, 10) << 2;
801 addr
= pv_add_constant (regs
[rn
], offset
);
803 if (pv_area_store_would_trash (stack
, addr
))
806 pv_area_store (stack
, addr
, 4, regs
[rd
]);
808 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
809 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
810 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
811 /* Ignore stores of argument registers to the stack. */
813 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
814 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
815 /* Ignore block loads from the stack, potentially copying
816 parameters from memory. */
818 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
819 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
820 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
821 /* Similarly ignore single loads from the stack. */
823 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
824 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
825 /* Skip register copies, i.e. saves to another register
826 instead of the stack. */
828 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
829 /* Recognize constant loads; even with small stacks these are necessary
831 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
832 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
834 /* Constant pool loads, for the same reason. */
835 unsigned int constant
;
838 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
839 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
840 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
842 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instructions. */
844 unsigned short inst2
;
846 inst2
= read_memory_unsigned_integer (start
+ 2, 2,
847 byte_order_for_code
);
849 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
851 /* BL, BLX. Allow some special function calls when
852 skipping the prologue; GCC generates these before
853 storing arguments to the stack. */
855 int j1
, j2
, imm1
, imm2
;
857 imm1
= sbits (insn
, 0, 10);
858 imm2
= bits (inst2
, 0, 10);
859 j1
= bit (inst2
, 13);
860 j2
= bit (inst2
, 11);
862 offset
= ((imm1
<< 12) + (imm2
<< 1));
863 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
865 nextpc
= start
+ 4 + offset
;
866 /* For BLX make sure to clear the low bits. */
867 if (bit (inst2
, 12) == 0)
868 nextpc
= nextpc
& 0xfffffffc;
870 if (!skip_prologue_function (gdbarch
, nextpc
,
871 bit (inst2
, 12) != 0))
875 else if ((insn
& 0xffd0) == 0xe900 /* stmdb Rn{!},
877 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
879 pv_t addr
= regs
[bits (insn
, 0, 3)];
882 if (pv_area_store_would_trash (stack
, addr
))
885 /* Calculate offsets of saved registers. */
886 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
887 if (inst2
& (1 << regno
))
889 addr
= pv_add_constant (addr
, -4);
890 pv_area_store (stack
, addr
, 4, regs
[regno
]);
894 regs
[bits (insn
, 0, 3)] = addr
;
897 else if ((insn
& 0xff50) == 0xe940 /* strd Rt, Rt2,
899 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
901 int regno1
= bits (inst2
, 12, 15);
902 int regno2
= bits (inst2
, 8, 11);
903 pv_t addr
= regs
[bits (insn
, 0, 3)];
905 offset
= inst2
& 0xff;
907 addr
= pv_add_constant (addr
, offset
);
909 addr
= pv_add_constant (addr
, -offset
);
911 if (pv_area_store_would_trash (stack
, addr
))
914 pv_area_store (stack
, addr
, 4, regs
[regno1
]);
915 pv_area_store (stack
, pv_add_constant (addr
, 4),
919 regs
[bits (insn
, 0, 3)] = addr
;
922 else if ((insn
& 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
923 && (inst2
& 0x0c00) == 0x0c00
924 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
926 int regno
= bits (inst2
, 12, 15);
927 pv_t addr
= regs
[bits (insn
, 0, 3)];
929 offset
= inst2
& 0xff;
931 addr
= pv_add_constant (addr
, offset
);
933 addr
= pv_add_constant (addr
, -offset
);
935 if (pv_area_store_would_trash (stack
, addr
))
938 pv_area_store (stack
, addr
, 4, regs
[regno
]);
941 regs
[bits (insn
, 0, 3)] = addr
;
944 else if ((insn
& 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
945 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
947 int regno
= bits (inst2
, 12, 15);
950 offset
= inst2
& 0xfff;
951 addr
= pv_add_constant (regs
[bits (insn
, 0, 3)], offset
);
953 if (pv_area_store_would_trash (stack
, addr
))
956 pv_area_store (stack
, addr
, 4, regs
[regno
]);
959 else if ((insn
& 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
960 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
961 /* Ignore stores of argument registers to the stack. */
964 else if ((insn
& 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
965 && (inst2
& 0x0d00) == 0x0c00
966 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
967 /* Ignore stores of argument registers to the stack. */
970 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!],
972 && (inst2
& 0x8000) == 0x0000
973 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
974 /* Ignore block loads from the stack, potentially copying
975 parameters from memory. */
978 else if ((insn
& 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
980 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
981 /* Similarly ignore dual loads from the stack. */
984 else if ((insn
& 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
985 && (inst2
& 0x0d00) == 0x0c00
986 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
987 /* Similarly ignore single loads from the stack. */
990 else if ((insn
& 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
991 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
992 /* Similarly ignore single loads from the stack. */
995 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
996 && (inst2
& 0x8000) == 0x0000)
998 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
999 | (bits (inst2
, 12, 14) << 8)
1000 | bits (inst2
, 0, 7));
1002 regs
[bits (inst2
, 8, 11)]
1003 = pv_add_constant (regs
[bits (insn
, 0, 3)],
1004 thumb_expand_immediate (imm
));
1007 else if ((insn
& 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
1008 && (inst2
& 0x8000) == 0x0000)
1010 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1011 | (bits (inst2
, 12, 14) << 8)
1012 | bits (inst2
, 0, 7));
1014 regs
[bits (inst2
, 8, 11)]
1015 = pv_add_constant (regs
[bits (insn
, 0, 3)], imm
);
1018 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
1019 && (inst2
& 0x8000) == 0x0000)
1021 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1022 | (bits (inst2
, 12, 14) << 8)
1023 | bits (inst2
, 0, 7));
1025 regs
[bits (inst2
, 8, 11)]
1026 = pv_add_constant (regs
[bits (insn
, 0, 3)],
1027 - (CORE_ADDR
) thumb_expand_immediate (imm
));
1030 else if ((insn
& 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
1031 && (inst2
& 0x8000) == 0x0000)
1033 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1034 | (bits (inst2
, 12, 14) << 8)
1035 | bits (inst2
, 0, 7));
1037 regs
[bits (inst2
, 8, 11)]
1038 = pv_add_constant (regs
[bits (insn
, 0, 3)], - (CORE_ADDR
) imm
);
1041 else if ((insn
& 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1043 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1044 | (bits (inst2
, 12, 14) << 8)
1045 | bits (inst2
, 0, 7));
1047 regs
[bits (inst2
, 8, 11)]
1048 = pv_constant (thumb_expand_immediate (imm
));
1051 else if ((insn
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1054 = EXTRACT_MOVW_MOVT_IMM_T (insn
, inst2
);
1056 regs
[bits (inst2
, 8, 11)] = pv_constant (imm
);
1059 else if (insn
== 0xea5f /* mov.w Rd,Rm */
1060 && (inst2
& 0xf0f0) == 0)
1062 int dst_reg
= (inst2
& 0x0f00) >> 8;
1063 int src_reg
= inst2
& 0xf;
1064 regs
[dst_reg
] = regs
[src_reg
];
1067 else if ((insn
& 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1069 /* Constant pool loads. */
1070 unsigned int constant
;
1073 offset
= bits (insn
, 0, 11);
1075 loc
= start
+ 4 + offset
;
1077 loc
= start
+ 4 - offset
;
1079 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1080 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1083 else if ((insn
& 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1085 /* Constant pool loads. */
1086 unsigned int constant
;
1089 offset
= bits (insn
, 0, 7) << 2;
1091 loc
= start
+ 4 + offset
;
1093 loc
= start
+ 4 - offset
;
1095 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1096 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1098 constant
= read_memory_unsigned_integer (loc
+ 4, 4, byte_order
);
1099 regs
[bits (inst2
, 8, 11)] = pv_constant (constant
);
1102 else if (thumb2_instruction_changes_pc (insn
, inst2
))
1104 /* Don't scan past anything that might change control flow. */
1109 /* The optimizer might shove anything into the prologue,
1110 so we just skip what we don't recognize. */
1111 unrecognized_pc
= start
;
1116 else if (thumb_instruction_changes_pc (insn
))
1118 /* Don't scan past anything that might change control flow. */
1123 /* The optimizer might shove anything into the prologue,
1124 so we just skip what we don't recognize. */
1125 unrecognized_pc
= start
;
1132 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1133 paddress (gdbarch
, start
));
1135 if (unrecognized_pc
== 0)
1136 unrecognized_pc
= start
;
1140 do_cleanups (back_to
);
1141 return unrecognized_pc
;
1144 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1146 /* Frame pointer is fp. Frame size is constant. */
1147 cache
->framereg
= ARM_FP_REGNUM
;
1148 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1150 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
1152 /* Frame pointer is r7. Frame size is constant. */
1153 cache
->framereg
= THUMB_FP_REGNUM
;
1154 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
1158 /* Try the stack pointer... this is a bit desperate. */
1159 cache
->framereg
= ARM_SP_REGNUM
;
1160 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1163 for (i
= 0; i
< 16; i
++)
1164 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
1165 cache
->saved_regs
[i
].addr
= offset
;
1167 do_cleanups (back_to
);
1168 return unrecognized_pc
;
1172 /* Try to analyze the instructions starting from PC, which load symbol
1173 __stack_chk_guard. Return the address of instruction after loading this
1174 symbol, set the dest register number to *BASEREG, and set the size of
1175 instructions for loading symbol in OFFSET. Return 0 if instructions are
1179 arm_analyze_load_stack_chk_guard(CORE_ADDR pc
, struct gdbarch
*gdbarch
,
1180 unsigned int *destreg
, int *offset
)
1182 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1183 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1184 unsigned int low
, high
, address
;
1189 unsigned short insn1
1190 = read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
1192 if ((insn1
& 0xf800) == 0x4800) /* ldr Rd, #immed */
1194 *destreg
= bits (insn1
, 8, 10);
1196 address
= bits (insn1
, 0, 7);
1198 else if ((insn1
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1200 unsigned short insn2
1201 = read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1203 low
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1206 = read_memory_unsigned_integer (pc
+ 4, 2, byte_order_for_code
);
1208 = read_memory_unsigned_integer (pc
+ 6, 2, byte_order_for_code
);
1210 /* movt Rd, #const */
1211 if ((insn1
& 0xfbc0) == 0xf2c0)
1213 high
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1214 *destreg
= bits (insn2
, 8, 11);
1216 address
= (high
<< 16 | low
);
1223 = read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
1225 if ((insn
& 0x0e5f0000) == 0x041f0000) /* ldr Rd, #immed */
1227 address
= bits (insn
, 0, 11);
1228 *destreg
= bits (insn
, 12, 15);
1231 else if ((insn
& 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1233 low
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1236 = read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
);
1238 if ((insn
& 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1240 high
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1241 *destreg
= bits (insn
, 12, 15);
1243 address
= (high
<< 16 | low
);
1251 /* Try to skip a sequence of instructions used for stack protector. If PC
1252 points to the first instruction of this sequence, return the address of
1253 first instruction after this sequence, otherwise, return original PC.
1255 On arm, this sequence of instructions is composed of mainly three steps,
1256 Step 1: load symbol __stack_chk_guard,
1257 Step 2: load from address of __stack_chk_guard,
1258 Step 3: store it to somewhere else.
1260 Usually, instructions on step 2 and step 3 are the same on various ARM
1261 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1262 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1263 instructions in step 1 vary from different ARM architectures. On ARMv7,
1266 movw Rn, #:lower16:__stack_chk_guard
1267 movt Rn, #:upper16:__stack_chk_guard
1274 .word __stack_chk_guard
1276 Since ldr/str is a very popular instruction, we can't use them as
1277 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1278 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1279 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1282 arm_skip_stack_protector(CORE_ADDR pc
, struct gdbarch
*gdbarch
)
1284 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1285 unsigned int basereg
;
1286 struct minimal_symbol
*stack_chk_guard
;
1288 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1291 /* Try to parse the instructions in Step 1. */
1292 addr
= arm_analyze_load_stack_chk_guard (pc
, gdbarch
,
1297 stack_chk_guard
= lookup_minimal_symbol_by_pc (addr
);
1298 /* If name of symbol doesn't start with '__stack_chk_guard', this
1299 instruction sequence is not for stack protector. If symbol is
1300 removed, we conservatively think this sequence is for stack protector. */
1302 && strncmp (SYMBOL_LINKAGE_NAME (stack_chk_guard
), "__stack_chk_guard",
1303 strlen ("__stack_chk_guard")) != 0)
1308 unsigned int destreg
;
1310 = read_memory_unsigned_integer (pc
+ offset
, 2, byte_order_for_code
);
1312 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1313 if ((insn
& 0xf800) != 0x6800)
1315 if (bits (insn
, 3, 5) != basereg
)
1317 destreg
= bits (insn
, 0, 2);
1319 insn
= read_memory_unsigned_integer (pc
+ offset
+ 2, 2,
1320 byte_order_for_code
);
1321 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1322 if ((insn
& 0xf800) != 0x6000)
1324 if (destreg
!= bits (insn
, 0, 2))
1329 unsigned int destreg
;
1331 = read_memory_unsigned_integer (pc
+ offset
, 4, byte_order_for_code
);
1333 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1334 if ((insn
& 0x0e500000) != 0x04100000)
1336 if (bits (insn
, 16, 19) != basereg
)
1338 destreg
= bits (insn
, 12, 15);
1339 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1340 insn
= read_memory_unsigned_integer (pc
+ offset
+ 4,
1341 4, byte_order_for_code
);
1342 if ((insn
& 0x0e500000) != 0x04000000)
1344 if (bits (insn
, 12, 15) != destreg
)
1347 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1350 return pc
+ offset
+ 4;
1352 return pc
+ offset
+ 8;
1355 /* Advance the PC across any function entry prologue instructions to
1356 reach some "real" code.
1358 The APCS (ARM Procedure Call Standard) defines the following
1362 [stmfd sp!, {a1,a2,a3,a4}]
1363 stmfd sp!, {...,fp,ip,lr,pc}
1364 [stfe f7, [sp, #-12]!]
1365 [stfe f6, [sp, #-12]!]
1366 [stfe f5, [sp, #-12]!]
1367 [stfe f4, [sp, #-12]!]
1368 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1371 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1373 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1376 CORE_ADDR func_addr
, limit_pc
;
1378 /* See if we can determine the end of the prologue via the symbol table.
1379 If so, then return either PC, or the PC after the prologue, whichever
1381 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1383 CORE_ADDR post_prologue_pc
1384 = skip_prologue_using_sal (gdbarch
, func_addr
);
1385 struct symtab
*s
= find_pc_symtab (func_addr
);
1387 if (post_prologue_pc
)
1389 = arm_skip_stack_protector (post_prologue_pc
, gdbarch
);
1392 /* GCC always emits a line note before the prologue and another
1393 one after, even if the two are at the same address or on the
1394 same line. Take advantage of this so that we do not need to
1395 know every instruction that might appear in the prologue. We
1396 will have producer information for most binaries; if it is
1397 missing (e.g. for -gstabs), assuming the GNU tools. */
1398 if (post_prologue_pc
1400 || s
->producer
== NULL
1401 || strncmp (s
->producer
, "GNU ", sizeof ("GNU ") - 1) == 0
1402 || strncmp (s
->producer
, "clang ", sizeof ("clang ") - 1) == 0))
1403 return post_prologue_pc
;
1405 if (post_prologue_pc
!= 0)
1407 CORE_ADDR analyzed_limit
;
1409 /* For non-GCC compilers, make sure the entire line is an
1410 acceptable prologue; GDB will round this function's
1411 return value up to the end of the following line so we
1412 can not skip just part of a line (and we do not want to).
1414 RealView does not treat the prologue specially, but does
1415 associate prologue code with the opening brace; so this
1416 lets us skip the first line if we think it is the opening
1418 if (arm_pc_is_thumb (gdbarch
, func_addr
))
1419 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
1420 post_prologue_pc
, NULL
);
1422 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
1423 post_prologue_pc
, NULL
);
1425 if (analyzed_limit
!= post_prologue_pc
)
1428 return post_prologue_pc
;
1432 /* Can't determine prologue from the symbol table, need to examine
1435 /* Find an upper limit on the function prologue using the debug
1436 information. If the debug information could not be used to provide
1437 that bound, then use an arbitrary large number as the upper bound. */
1438 /* Like arm_scan_prologue, stop no later than pc + 64. */
1439 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1441 limit_pc
= pc
+ 64; /* Magic. */
1444 /* Check if this is Thumb code. */
1445 if (arm_pc_is_thumb (gdbarch
, pc
))
1446 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1448 for (skip_pc
= pc
; skip_pc
< limit_pc
; skip_pc
+= 4)
1450 inst
= read_memory_unsigned_integer (skip_pc
, 4, byte_order_for_code
);
1452 /* "mov ip, sp" is no longer a required part of the prologue. */
1453 if (inst
== 0xe1a0c00d) /* mov ip, sp */
1456 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
1459 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
1462 /* Some prologues begin with "str lr, [sp, #-4]!". */
1463 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
1466 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
1469 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
1472 /* Any insns after this point may float into the code, if it makes
1473 for better instruction scheduling, so we skip them only if we
1474 find them, but still consider the function to be frame-ful. */
1476 /* We may have either one sfmfd instruction here, or several stfe
1477 insns, depending on the version of floating point code we
1479 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
1482 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
1485 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
1488 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
1491 if ((inst
& 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */
1492 || (inst
& 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */
1493 || (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
1496 if ((inst
& 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */
1497 || (inst
& 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */
1498 || (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
1501 /* Un-recognized instruction; stop scanning. */
1505 return skip_pc
; /* End of prologue. */
1509 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1510 This function decodes a Thumb function prologue to determine:
1511 1) the size of the stack frame
1512 2) which registers are saved on it
1513 3) the offsets of saved regs
1514 4) the offset from the stack pointer to the frame pointer
1516 A typical Thumb function prologue would create this stack frame
1517 (offsets relative to FP)
1518 old SP -> 24 stack parameters
1521 R7 -> 0 local variables (16 bytes)
1522 SP -> -12 additional stack space (12 bytes)
1523 The frame size would thus be 36 bytes, and the frame offset would be
1524 12 bytes. The frame register is R7.
1526 The comments for thumb_skip_prolog() describe the algorithm we use
1527 to detect the end of the prolog. */
1531 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
1532 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
1534 CORE_ADDR prologue_start
;
1535 CORE_ADDR prologue_end
;
1537 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1540 /* See comment in arm_scan_prologue for an explanation of
1542 if (prologue_end
> prologue_start
+ 64)
1544 prologue_end
= prologue_start
+ 64;
1548 /* We're in the boondocks: we have no idea where the start of the
1552 prologue_end
= min (prologue_end
, prev_pc
);
1554 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1557 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
1560 arm_instruction_changes_pc (uint32_t this_instr
)
1562 if (bits (this_instr
, 28, 31) == INST_NV
)
1563 /* Unconditional instructions. */
1564 switch (bits (this_instr
, 24, 27))
1568 /* Branch with Link and change to Thumb. */
1573 /* Coprocessor register transfer. */
1574 if (bits (this_instr
, 12, 15) == 15)
1575 error (_("Invalid update to pc in instruction"));
1581 switch (bits (this_instr
, 25, 27))
1584 if (bits (this_instr
, 23, 24) == 2 && bit (this_instr
, 20) == 0)
1586 /* Multiplies and extra load/stores. */
1587 if (bit (this_instr
, 4) == 1 && bit (this_instr
, 7) == 1)
1588 /* Neither multiplies nor extension load/stores are allowed
1592 /* Otherwise, miscellaneous instructions. */
1594 /* BX <reg>, BXJ <reg>, BLX <reg> */
1595 if (bits (this_instr
, 4, 27) == 0x12fff1
1596 || bits (this_instr
, 4, 27) == 0x12fff2
1597 || bits (this_instr
, 4, 27) == 0x12fff3)
1600 /* Other miscellaneous instructions are unpredictable if they
1604 /* Data processing instruction. Fall through. */
1607 if (bits (this_instr
, 12, 15) == 15)
1614 /* Media instructions and architecturally undefined instructions. */
1615 if (bits (this_instr
, 25, 27) == 3 && bit (this_instr
, 4) == 1)
1619 if (bit (this_instr
, 20) == 0)
1623 if (bits (this_instr
, 12, 15) == ARM_PC_REGNUM
)
1629 /* Load/store multiple. */
1630 if (bit (this_instr
, 20) == 1 && bit (this_instr
, 15) == 1)
1636 /* Branch and branch with link. */
1641 /* Coprocessor transfers or SWIs can not affect PC. */
1645 internal_error (__FILE__
, __LINE__
, _("bad value in switch"));
1649 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1650 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1651 fill it in. Return the first address not recognized as a prologue
1654 We recognize all the instructions typically found in ARM prologues,
1655 plus harmless instructions which can be skipped (either for analysis
1656 purposes, or a more restrictive set that can be skipped when finding
1657 the end of the prologue). */
1660 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1661 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1662 struct arm_prologue_cache
*cache
)
1664 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1665 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1667 CORE_ADDR offset
, current_pc
;
1668 pv_t regs
[ARM_FPS_REGNUM
];
1669 struct pv_area
*stack
;
1670 struct cleanup
*back_to
;
1671 int framereg
, framesize
;
1672 CORE_ADDR unrecognized_pc
= 0;
1674 /* Search the prologue looking for instructions that set up the
1675 frame pointer, adjust the stack pointer, and save registers.
1677 Be careful, however, and if it doesn't look like a prologue,
1678 don't try to scan it. If, for instance, a frameless function
1679 begins with stmfd sp!, then we will tell ourselves there is
1680 a frame, which will confuse stack traceback, as well as "finish"
1681 and other operations that rely on a knowledge of the stack
1684 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1685 regs
[regno
] = pv_register (regno
, 0);
1686 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1687 back_to
= make_cleanup_free_pv_area (stack
);
1689 for (current_pc
= prologue_start
;
1690 current_pc
< prologue_end
;
1694 = read_memory_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1696 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1698 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1701 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1702 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1704 unsigned imm
= insn
& 0xff; /* immediate value */
1705 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1706 int rd
= bits (insn
, 12, 15);
1707 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1708 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1711 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1712 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1714 unsigned imm
= insn
& 0xff; /* immediate value */
1715 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1716 int rd
= bits (insn
, 12, 15);
1717 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1718 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1721 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd,
1724 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1726 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1727 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4,
1728 regs
[bits (insn
, 12, 15)]);
1731 else if ((insn
& 0xffff0000) == 0xe92d0000)
1732 /* stmfd sp!, {..., fp, ip, lr, pc}
1734 stmfd sp!, {a1, a2, a3, a4} */
1736 int mask
= insn
& 0xffff;
1738 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1741 /* Calculate offsets of saved registers. */
1742 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1743 if (mask
& (1 << regno
))
1746 = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1747 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1750 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1751 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1752 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1754 /* No need to add this to saved_regs -- it's just an arg reg. */
1757 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1758 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1759 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1761 /* No need to add this to saved_regs -- it's just an arg reg. */
1764 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn,
1766 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1768 /* No need to add this to saved_regs -- it's just arg regs. */
1771 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1773 unsigned imm
= insn
& 0xff; /* immediate value */
1774 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1775 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1776 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1778 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1780 unsigned imm
= insn
& 0xff; /* immediate value */
1781 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1782 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1783 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1785 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?,
1787 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1789 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1792 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1793 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1794 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1796 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1798 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1800 int n_saved_fp_regs
;
1801 unsigned int fp_start_reg
, fp_bound_reg
;
1803 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1806 if ((insn
& 0x800) == 0x800) /* N0 is set */
1808 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1809 n_saved_fp_regs
= 3;
1811 n_saved_fp_regs
= 1;
1815 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1816 n_saved_fp_regs
= 2;
1818 n_saved_fp_regs
= 4;
1821 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1822 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1823 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1825 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1826 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
1827 regs
[fp_start_reg
++]);
1830 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1832 /* Allow some special function calls when skipping the
1833 prologue; GCC generates these before storing arguments to
1835 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1837 if (skip_prologue_function (gdbarch
, dest
, 0))
1842 else if ((insn
& 0xf0000000) != 0xe0000000)
1843 break; /* Condition not true, exit early. */
1844 else if (arm_instruction_changes_pc (insn
))
1845 /* Don't scan past anything that might change control flow. */
1847 else if ((insn
& 0xfe500000) == 0xe8100000 /* ldm */
1848 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1849 /* Ignore block loads from the stack, potentially copying
1850 parameters from memory. */
1852 else if ((insn
& 0xfc500000) == 0xe4100000
1853 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1854 /* Similarly ignore single loads from the stack. */
1856 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1857 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1858 register instead of the stack. */
1862 /* The optimizer might shove anything into the prologue,
1863 so we just skip what we don't recognize. */
1864 unrecognized_pc
= current_pc
;
1869 if (unrecognized_pc
== 0)
1870 unrecognized_pc
= current_pc
;
1872 /* The frame size is just the distance from the frame register
1873 to the original stack pointer. */
1874 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1876 /* Frame pointer is fp. */
1877 framereg
= ARM_FP_REGNUM
;
1878 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1882 /* Try the stack pointer... this is a bit desperate. */
1883 framereg
= ARM_SP_REGNUM
;
1884 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1889 cache
->framereg
= framereg
;
1890 cache
->framesize
= framesize
;
1892 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1893 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1894 cache
->saved_regs
[regno
].addr
= offset
;
1898 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1899 paddress (gdbarch
, unrecognized_pc
));
1901 do_cleanups (back_to
);
1902 return unrecognized_pc
;
1906 arm_scan_prologue (struct frame_info
*this_frame
,
1907 struct arm_prologue_cache
*cache
)
1909 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1910 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1912 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
1913 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1914 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1915 pv_t regs
[ARM_FPS_REGNUM
];
1916 struct pv_area
*stack
;
1917 struct cleanup
*back_to
;
1920 /* Assume there is no frame until proven otherwise. */
1921 cache
->framereg
= ARM_SP_REGNUM
;
1922 cache
->framesize
= 0;
1924 /* Check for Thumb prologue. */
1925 if (arm_frame_is_thumb (this_frame
))
1927 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1931 /* Find the function prologue. If we can't find the function in
1932 the symbol table, peek in the stack frame to find the PC. */
1933 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1936 /* One way to find the end of the prologue (which works well
1937 for unoptimized code) is to do the following:
1939 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1942 prologue_end = prev_pc;
1943 else if (sal.end < prologue_end)
1944 prologue_end = sal.end;
1946 This mechanism is very accurate so long as the optimizer
1947 doesn't move any instructions from the function body into the
1948 prologue. If this happens, sal.end will be the last
1949 instruction in the first hunk of prologue code just before
1950 the first instruction that the scheduler has moved from
1951 the body to the prologue.
1953 In order to make sure that we scan all of the prologue
1954 instructions, we use a slightly less accurate mechanism which
1955 may scan more than necessary. To help compensate for this
1956 lack of accuracy, the prologue scanning loop below contains
1957 several clauses which'll cause the loop to terminate early if
1958 an implausible prologue instruction is encountered.
1964 is a suitable endpoint since it accounts for the largest
1965 possible prologue plus up to five instructions inserted by
1968 if (prologue_end
> prologue_start
+ 64)
1970 prologue_end
= prologue_start
+ 64; /* See above. */
1975 /* We have no symbol information. Our only option is to assume this
1976 function has a standard stack frame and the normal frame register.
1977 Then, we can find the value of our frame pointer on entrance to
1978 the callee (or at the present moment if this is the innermost frame).
1979 The value stored there should be the address of the stmfd + 8. */
1980 CORE_ADDR frame_loc
;
1981 LONGEST return_value
;
1983 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
1984 if (!safe_read_memory_integer (frame_loc
, 4, byte_order
, &return_value
))
1988 prologue_start
= gdbarch_addr_bits_remove
1989 (gdbarch
, return_value
) - 8;
1990 prologue_end
= prologue_start
+ 64; /* See above. */
1994 if (prev_pc
< prologue_end
)
1995 prologue_end
= prev_pc
;
1997 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
2000 static struct arm_prologue_cache
*
2001 arm_make_prologue_cache (struct frame_info
*this_frame
)
2004 struct arm_prologue_cache
*cache
;
2005 CORE_ADDR unwound_fp
;
2007 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2008 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2010 arm_scan_prologue (this_frame
, cache
);
2012 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
2013 if (unwound_fp
== 0)
2016 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
2018 /* Calculate actual addresses of saved registers using offsets
2019 determined by arm_scan_prologue. */
2020 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
2021 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
2022 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
2027 /* Our frame ID for a normal frame is the current function's starting PC
2028 and the caller's SP when we were called. */
2031 arm_prologue_this_id (struct frame_info
*this_frame
,
2033 struct frame_id
*this_id
)
2035 struct arm_prologue_cache
*cache
;
2039 if (*this_cache
== NULL
)
2040 *this_cache
= arm_make_prologue_cache (this_frame
);
2041 cache
= *this_cache
;
2043 /* This is meant to halt the backtrace at "_start". */
2044 pc
= get_frame_pc (this_frame
);
2045 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
2048 /* If we've hit a wall, stop. */
2049 if (cache
->prev_sp
== 0)
2052 /* Use function start address as part of the frame ID. If we cannot
2053 identify the start address (due to missing symbol information),
2054 fall back to just using the current PC. */
2055 func
= get_frame_func (this_frame
);
2059 id
= frame_id_build (cache
->prev_sp
, func
);
2063 static struct value
*
2064 arm_prologue_prev_register (struct frame_info
*this_frame
,
2068 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2069 struct arm_prologue_cache
*cache
;
2071 if (*this_cache
== NULL
)
2072 *this_cache
= arm_make_prologue_cache (this_frame
);
2073 cache
= *this_cache
;
2075 /* If we are asked to unwind the PC, then we need to return the LR
2076 instead. The prologue may save PC, but it will point into this
2077 frame's prologue, not the next frame's resume location. Also
2078 strip the saved T bit. A valid LR may have the low bit set, but
2079 a valid PC never does. */
2080 if (prev_regnum
== ARM_PC_REGNUM
)
2084 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2085 return frame_unwind_got_constant (this_frame
, prev_regnum
,
2086 arm_addr_bits_remove (gdbarch
, lr
));
2089 /* SP is generally not saved to the stack, but this frame is
2090 identified by the next frame's stack pointer at the time of the call.
2091 The value was already reconstructed into PREV_SP. */
2092 if (prev_regnum
== ARM_SP_REGNUM
)
2093 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
2095 /* The CPSR may have been changed by the call instruction and by the
2096 called function. The only bit we can reconstruct is the T bit,
2097 by checking the low bit of LR as of the call. This is a reliable
2098 indicator of Thumb-ness except for some ARM v4T pre-interworking
2099 Thumb code, which could get away with a clear low bit as long as
2100 the called function did not use bx. Guess that all other
2101 bits are unchanged; the condition flags are presumably lost,
2102 but the processor status is likely valid. */
2103 if (prev_regnum
== ARM_PS_REGNUM
)
2106 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
2108 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
2109 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2110 if (IS_THUMB_ADDR (lr
))
2114 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
2117 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
2121 struct frame_unwind arm_prologue_unwind
= {
2123 default_frame_unwind_stop_reason
,
2124 arm_prologue_this_id
,
2125 arm_prologue_prev_register
,
2127 default_frame_sniffer
2130 /* Maintain a list of ARM exception table entries per objfile, similar to the
2131 list of mapping symbols. We only cache entries for standard ARM-defined
2132 personality routines; the cache will contain only the frame unwinding
2133 instructions associated with the entry (not the descriptors). */
2135 static const struct objfile_data
*arm_exidx_data_key
;
2137 struct arm_exidx_entry
2142 typedef struct arm_exidx_entry arm_exidx_entry_s
;
2143 DEF_VEC_O(arm_exidx_entry_s
);
2145 struct arm_exidx_data
2147 VEC(arm_exidx_entry_s
) **section_maps
;
2151 arm_exidx_data_free (struct objfile
*objfile
, void *arg
)
2153 struct arm_exidx_data
*data
= arg
;
2156 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
2157 VEC_free (arm_exidx_entry_s
, data
->section_maps
[i
]);
2161 arm_compare_exidx_entries (const struct arm_exidx_entry
*lhs
,
2162 const struct arm_exidx_entry
*rhs
)
2164 return lhs
->addr
< rhs
->addr
;
2167 static struct obj_section
*
2168 arm_obj_section_from_vma (struct objfile
*objfile
, bfd_vma vma
)
2170 struct obj_section
*osect
;
2172 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
2173 if (bfd_get_section_flags (objfile
->obfd
,
2174 osect
->the_bfd_section
) & SEC_ALLOC
)
2176 bfd_vma start
, size
;
2177 start
= bfd_get_section_vma (objfile
->obfd
, osect
->the_bfd_section
);
2178 size
= bfd_get_section_size (osect
->the_bfd_section
);
2180 if (start
<= vma
&& vma
< start
+ size
)
2187 /* Parse contents of exception table and exception index sections
2188 of OBJFILE, and fill in the exception table entry cache.
2190 For each entry that refers to a standard ARM-defined personality
2191 routine, extract the frame unwinding instructions (from either
2192 the index or the table section). The unwinding instructions
2194 - extracting them from the rest of the table data
2195 - converting to host endianness
2196 - appending the implicit 0xb0 ("Finish") code
2198 The extracted and normalized instructions are stored for later
2199 retrieval by the arm_find_exidx_entry routine. */
2202 arm_exidx_new_objfile (struct objfile
*objfile
)
2204 struct cleanup
*cleanups
;
2205 struct arm_exidx_data
*data
;
2206 asection
*exidx
, *extab
;
2207 bfd_vma exidx_vma
= 0, extab_vma
= 0;
2208 bfd_size_type exidx_size
= 0, extab_size
= 0;
2209 gdb_byte
*exidx_data
= NULL
, *extab_data
= NULL
;
2212 /* If we've already touched this file, do nothing. */
2213 if (!objfile
|| objfile_data (objfile
, arm_exidx_data_key
) != NULL
)
2215 cleanups
= make_cleanup (null_cleanup
, NULL
);
2217 /* Read contents of exception table and index. */
2218 exidx
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.exidx");
2221 exidx_vma
= bfd_section_vma (objfile
->obfd
, exidx
);
2222 exidx_size
= bfd_get_section_size (exidx
);
2223 exidx_data
= xmalloc (exidx_size
);
2224 make_cleanup (xfree
, exidx_data
);
2226 if (!bfd_get_section_contents (objfile
->obfd
, exidx
,
2227 exidx_data
, 0, exidx_size
))
2229 do_cleanups (cleanups
);
2234 extab
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.extab");
2237 extab_vma
= bfd_section_vma (objfile
->obfd
, extab
);
2238 extab_size
= bfd_get_section_size (extab
);
2239 extab_data
= xmalloc (extab_size
);
2240 make_cleanup (xfree
, extab_data
);
2242 if (!bfd_get_section_contents (objfile
->obfd
, extab
,
2243 extab_data
, 0, extab_size
))
2245 do_cleanups (cleanups
);
2250 /* Allocate exception table data structure. */
2251 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
, struct arm_exidx_data
);
2252 set_objfile_data (objfile
, arm_exidx_data_key
, data
);
2253 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2254 objfile
->obfd
->section_count
,
2255 VEC(arm_exidx_entry_s
) *);
2257 /* Fill in exception table. */
2258 for (i
= 0; i
< exidx_size
/ 8; i
++)
2260 struct arm_exidx_entry new_exidx_entry
;
2261 bfd_vma idx
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8);
2262 bfd_vma val
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8 + 4);
2263 bfd_vma addr
= 0, word
= 0;
2264 int n_bytes
= 0, n_words
= 0;
2265 struct obj_section
*sec
;
2266 gdb_byte
*entry
= NULL
;
2268 /* Extract address of start of function. */
2269 idx
= ((idx
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2270 idx
+= exidx_vma
+ i
* 8;
2272 /* Find section containing function and compute section offset. */
2273 sec
= arm_obj_section_from_vma (objfile
, idx
);
2276 idx
-= bfd_get_section_vma (objfile
->obfd
, sec
->the_bfd_section
);
2278 /* Determine address of exception table entry. */
2281 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2283 else if ((val
& 0xff000000) == 0x80000000)
2285 /* Exception table entry embedded in .ARM.exidx
2286 -- must be short form. */
2290 else if (!(val
& 0x80000000))
2292 /* Exception table entry in .ARM.extab. */
2293 addr
= ((val
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2294 addr
+= exidx_vma
+ i
* 8 + 4;
2296 if (addr
>= extab_vma
&& addr
+ 4 <= extab_vma
+ extab_size
)
2298 word
= bfd_h_get_32 (objfile
->obfd
,
2299 extab_data
+ addr
- extab_vma
);
2302 if ((word
& 0xff000000) == 0x80000000)
2307 else if ((word
& 0xff000000) == 0x81000000
2308 || (word
& 0xff000000) == 0x82000000)
2312 n_words
= ((word
>> 16) & 0xff);
2314 else if (!(word
& 0x80000000))
2317 struct obj_section
*pers_sec
;
2318 int gnu_personality
= 0;
2320 /* Custom personality routine. */
2321 pers
= ((word
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2322 pers
= UNMAKE_THUMB_ADDR (pers
+ addr
- 4);
2324 /* Check whether we've got one of the variants of the
2325 GNU personality routines. */
2326 pers_sec
= arm_obj_section_from_vma (objfile
, pers
);
2329 static const char *personality
[] =
2331 "__gcc_personality_v0",
2332 "__gxx_personality_v0",
2333 "__gcj_personality_v0",
2334 "__gnu_objc_personality_v0",
2338 CORE_ADDR pc
= pers
+ obj_section_offset (pers_sec
);
2341 for (k
= 0; personality
[k
]; k
++)
2342 if (lookup_minimal_symbol_by_pc_name
2343 (pc
, personality
[k
], objfile
))
2345 gnu_personality
= 1;
2350 /* If so, the next word contains a word count in the high
2351 byte, followed by the same unwind instructions as the
2352 pre-defined forms. */
2354 && addr
+ 4 <= extab_vma
+ extab_size
)
2356 word
= bfd_h_get_32 (objfile
->obfd
,
2357 extab_data
+ addr
- extab_vma
);
2360 n_words
= ((word
>> 24) & 0xff);
2366 /* Sanity check address. */
2368 if (addr
< extab_vma
|| addr
+ 4 * n_words
> extab_vma
+ extab_size
)
2369 n_words
= n_bytes
= 0;
2371 /* The unwind instructions reside in WORD (only the N_BYTES least
2372 significant bytes are valid), followed by N_WORDS words in the
2373 extab section starting at ADDR. */
2374 if (n_bytes
|| n_words
)
2376 gdb_byte
*p
= entry
= obstack_alloc (&objfile
->objfile_obstack
,
2377 n_bytes
+ n_words
* 4 + 1);
2380 *p
++ = (gdb_byte
) ((word
>> (8 * n_bytes
)) & 0xff);
2384 word
= bfd_h_get_32 (objfile
->obfd
,
2385 extab_data
+ addr
- extab_vma
);
2388 *p
++ = (gdb_byte
) ((word
>> 24) & 0xff);
2389 *p
++ = (gdb_byte
) ((word
>> 16) & 0xff);
2390 *p
++ = (gdb_byte
) ((word
>> 8) & 0xff);
2391 *p
++ = (gdb_byte
) (word
& 0xff);
2394 /* Implied "Finish" to terminate the list. */
2398 /* Push entry onto vector. They are guaranteed to always
2399 appear in order of increasing addresses. */
2400 new_exidx_entry
.addr
= idx
;
2401 new_exidx_entry
.entry
= entry
;
2402 VEC_safe_push (arm_exidx_entry_s
,
2403 data
->section_maps
[sec
->the_bfd_section
->index
],
2407 do_cleanups (cleanups
);
2410 /* Search for the exception table entry covering MEMADDR. If one is found,
2411 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2412 set *START to the start of the region covered by this entry. */
2415 arm_find_exidx_entry (CORE_ADDR memaddr
, CORE_ADDR
*start
)
2417 struct obj_section
*sec
;
2419 sec
= find_pc_section (memaddr
);
2422 struct arm_exidx_data
*data
;
2423 VEC(arm_exidx_entry_s
) *map
;
2424 struct arm_exidx_entry map_key
= { memaddr
- obj_section_addr (sec
), 0 };
2427 data
= objfile_data (sec
->objfile
, arm_exidx_data_key
);
2430 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
2431 if (!VEC_empty (arm_exidx_entry_s
, map
))
2433 struct arm_exidx_entry
*map_sym
;
2435 idx
= VEC_lower_bound (arm_exidx_entry_s
, map
, &map_key
,
2436 arm_compare_exidx_entries
);
2438 /* VEC_lower_bound finds the earliest ordered insertion
2439 point. If the following symbol starts at this exact
2440 address, we use that; otherwise, the preceding
2441 exception table entry covers this address. */
2442 if (idx
< VEC_length (arm_exidx_entry_s
, map
))
2444 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
);
2445 if (map_sym
->addr
== map_key
.addr
)
2448 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2449 return map_sym
->entry
;
2455 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
- 1);
2457 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2458 return map_sym
->entry
;
2467 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2468 instruction list from the ARM exception table entry ENTRY, allocate and
2469 return a prologue cache structure describing how to unwind this frame.
2471 Return NULL if the unwinding instruction list contains a "spare",
2472 "reserved" or "refuse to unwind" instruction as defined in section
2473 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2474 for the ARM Architecture" document. */
2476 static struct arm_prologue_cache
*
2477 arm_exidx_fill_cache (struct frame_info
*this_frame
, gdb_byte
*entry
)
2482 struct arm_prologue_cache
*cache
;
2483 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2484 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2490 /* Whenever we reload SP, we actually have to retrieve its
2491 actual value in the current frame. */
2494 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2496 int reg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2497 vsp
= get_frame_register_unsigned (this_frame
, reg
);
2501 CORE_ADDR addr
= cache
->saved_regs
[ARM_SP_REGNUM
].addr
;
2502 vsp
= get_frame_memory_unsigned (this_frame
, addr
, 4);
2508 /* Decode next unwind instruction. */
2511 if ((insn
& 0xc0) == 0)
2513 int offset
= insn
& 0x3f;
2514 vsp
+= (offset
<< 2) + 4;
2516 else if ((insn
& 0xc0) == 0x40)
2518 int offset
= insn
& 0x3f;
2519 vsp
-= (offset
<< 2) + 4;
2521 else if ((insn
& 0xf0) == 0x80)
2523 int mask
= ((insn
& 0xf) << 8) | *entry
++;
2526 /* The special case of an all-zero mask identifies
2527 "Refuse to unwind". We return NULL to fall back
2528 to the prologue analyzer. */
2532 /* Pop registers r4..r15 under mask. */
2533 for (i
= 0; i
< 12; i
++)
2534 if (mask
& (1 << i
))
2536 cache
->saved_regs
[4 + i
].addr
= vsp
;
2540 /* Special-case popping SP -- we need to reload vsp. */
2541 if (mask
& (1 << (ARM_SP_REGNUM
- 4)))
2544 else if ((insn
& 0xf0) == 0x90)
2546 int reg
= insn
& 0xf;
2548 /* Reserved cases. */
2549 if (reg
== ARM_SP_REGNUM
|| reg
== ARM_PC_REGNUM
)
2552 /* Set SP from another register and mark VSP for reload. */
2553 cache
->saved_regs
[ARM_SP_REGNUM
] = cache
->saved_regs
[reg
];
2556 else if ((insn
& 0xf0) == 0xa0)
2558 int count
= insn
& 0x7;
2559 int pop_lr
= (insn
& 0x8) != 0;
2562 /* Pop r4..r[4+count]. */
2563 for (i
= 0; i
<= count
; i
++)
2565 cache
->saved_regs
[4 + i
].addr
= vsp
;
2569 /* If indicated by flag, pop LR as well. */
2572 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= vsp
;
2576 else if (insn
== 0xb0)
2578 /* We could only have updated PC by popping into it; if so, it
2579 will show up as address. Otherwise, copy LR into PC. */
2580 if (!trad_frame_addr_p (cache
->saved_regs
, ARM_PC_REGNUM
))
2581 cache
->saved_regs
[ARM_PC_REGNUM
]
2582 = cache
->saved_regs
[ARM_LR_REGNUM
];
2587 else if (insn
== 0xb1)
2589 int mask
= *entry
++;
2592 /* All-zero mask and mask >= 16 is "spare". */
2593 if (mask
== 0 || mask
>= 16)
2596 /* Pop r0..r3 under mask. */
2597 for (i
= 0; i
< 4; i
++)
2598 if (mask
& (1 << i
))
2600 cache
->saved_regs
[i
].addr
= vsp
;
2604 else if (insn
== 0xb2)
2606 ULONGEST offset
= 0;
2611 offset
|= (*entry
& 0x7f) << shift
;
2614 while (*entry
++ & 0x80);
2616 vsp
+= 0x204 + (offset
<< 2);
2618 else if (insn
== 0xb3)
2620 int start
= *entry
>> 4;
2621 int count
= (*entry
++) & 0xf;
2624 /* Only registers D0..D15 are valid here. */
2625 if (start
+ count
>= 16)
2628 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2629 for (i
= 0; i
<= count
; i
++)
2631 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2635 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2638 else if ((insn
& 0xf8) == 0xb8)
2640 int count
= insn
& 0x7;
2643 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2644 for (i
= 0; i
<= count
; i
++)
2646 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2650 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2653 else if (insn
== 0xc6)
2655 int start
= *entry
>> 4;
2656 int count
= (*entry
++) & 0xf;
2659 /* Only registers WR0..WR15 are valid. */
2660 if (start
+ count
>= 16)
2663 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2664 for (i
= 0; i
<= count
; i
++)
2666 cache
->saved_regs
[ARM_WR0_REGNUM
+ start
+ i
].addr
= vsp
;
2670 else if (insn
== 0xc7)
2672 int mask
= *entry
++;
2675 /* All-zero mask and mask >= 16 is "spare". */
2676 if (mask
== 0 || mask
>= 16)
2679 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2680 for (i
= 0; i
< 4; i
++)
2681 if (mask
& (1 << i
))
2683 cache
->saved_regs
[ARM_WCGR0_REGNUM
+ i
].addr
= vsp
;
2687 else if ((insn
& 0xf8) == 0xc0)
2689 int count
= insn
& 0x7;
2692 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2693 for (i
= 0; i
<= count
; i
++)
2695 cache
->saved_regs
[ARM_WR0_REGNUM
+ 10 + i
].addr
= vsp
;
2699 else if (insn
== 0xc8)
2701 int start
= *entry
>> 4;
2702 int count
= (*entry
++) & 0xf;
2705 /* Only registers D0..D31 are valid. */
2706 if (start
+ count
>= 16)
2709 /* Pop VFP double-precision registers
2710 D[16+start]..D[16+start+count]. */
2711 for (i
= 0; i
<= count
; i
++)
2713 cache
->saved_regs
[ARM_D0_REGNUM
+ 16 + start
+ i
].addr
= vsp
;
2717 else if (insn
== 0xc9)
2719 int start
= *entry
>> 4;
2720 int count
= (*entry
++) & 0xf;
2723 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2724 for (i
= 0; i
<= count
; i
++)
2726 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2730 else if ((insn
& 0xf8) == 0xd0)
2732 int count
= insn
& 0x7;
2735 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2736 for (i
= 0; i
<= count
; i
++)
2738 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2744 /* Everything else is "spare". */
2749 /* If we restore SP from a register, assume this was the frame register.
2750 Otherwise just fall back to SP as frame register. */
2751 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2752 cache
->framereg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2754 cache
->framereg
= ARM_SP_REGNUM
;
2756 /* Determine offset to previous frame. */
2758 = vsp
- get_frame_register_unsigned (this_frame
, cache
->framereg
);
2760 /* We already got the previous SP. */
2761 cache
->prev_sp
= vsp
;
2766 /* Unwinding via ARM exception table entries. Note that the sniffer
2767 already computes a filled-in prologue cache, which is then used
2768 with the same arm_prologue_this_id and arm_prologue_prev_register
2769 routines also used for prologue-parsing based unwinding. */
2772 arm_exidx_unwind_sniffer (const struct frame_unwind
*self
,
2773 struct frame_info
*this_frame
,
2774 void **this_prologue_cache
)
2776 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2777 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2778 CORE_ADDR addr_in_block
, exidx_region
, func_start
;
2779 struct arm_prologue_cache
*cache
;
2782 /* See if we have an ARM exception table entry covering this address. */
2783 addr_in_block
= get_frame_address_in_block (this_frame
);
2784 entry
= arm_find_exidx_entry (addr_in_block
, &exidx_region
);
2788 /* The ARM exception table does not describe unwind information
2789 for arbitrary PC values, but is guaranteed to be correct only
2790 at call sites. We have to decide here whether we want to use
2791 ARM exception table information for this frame, or fall back
2792 to using prologue parsing. (Note that if we have DWARF CFI,
2793 this sniffer isn't even called -- CFI is always preferred.)
2795 Before we make this decision, however, we check whether we
2796 actually have *symbol* information for the current frame.
2797 If not, prologue parsing would not work anyway, so we might
2798 as well use the exception table and hope for the best. */
2799 if (find_pc_partial_function (addr_in_block
, NULL
, &func_start
, NULL
))
2803 /* If the next frame is "normal", we are at a call site in this
2804 frame, so exception information is guaranteed to be valid. */
2805 if (get_next_frame (this_frame
)
2806 && get_frame_type (get_next_frame (this_frame
)) == NORMAL_FRAME
)
2809 /* We also assume exception information is valid if we're currently
2810 blocked in a system call. The system library is supposed to
2811 ensure this, so that e.g. pthread cancellation works. */
2812 if (arm_frame_is_thumb (this_frame
))
2816 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 2, 2,
2817 byte_order_for_code
, &insn
)
2818 && (insn
& 0xff00) == 0xdf00 /* svc */)
2825 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 4, 4,
2826 byte_order_for_code
, &insn
)
2827 && (insn
& 0x0f000000) == 0x0f000000 /* svc */)
2831 /* Bail out if we don't know that exception information is valid. */
2835 /* The ARM exception index does not mark the *end* of the region
2836 covered by the entry, and some functions will not have any entry.
2837 To correctly recognize the end of the covered region, the linker
2838 should have inserted dummy records with a CANTUNWIND marker.
2840 Unfortunately, current versions of GNU ld do not reliably do
2841 this, and thus we may have found an incorrect entry above.
2842 As a (temporary) sanity check, we only use the entry if it
2843 lies *within* the bounds of the function. Note that this check
2844 might reject perfectly valid entries that just happen to cover
2845 multiple functions; therefore this check ought to be removed
2846 once the linker is fixed. */
2847 if (func_start
> exidx_region
)
2851 /* Decode the list of unwinding instructions into a prologue cache.
2852 Note that this may fail due to e.g. a "refuse to unwind" code. */
2853 cache
= arm_exidx_fill_cache (this_frame
, entry
);
2857 *this_prologue_cache
= cache
;
2861 struct frame_unwind arm_exidx_unwind
= {
2863 default_frame_unwind_stop_reason
,
2864 arm_prologue_this_id
,
2865 arm_prologue_prev_register
,
2867 arm_exidx_unwind_sniffer
2870 static struct arm_prologue_cache
*
2871 arm_make_stub_cache (struct frame_info
*this_frame
)
2873 struct arm_prologue_cache
*cache
;
2875 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2876 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2878 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2883 /* Our frame ID for a stub frame is the current SP and LR. */
2886 arm_stub_this_id (struct frame_info
*this_frame
,
2888 struct frame_id
*this_id
)
2890 struct arm_prologue_cache
*cache
;
2892 if (*this_cache
== NULL
)
2893 *this_cache
= arm_make_stub_cache (this_frame
);
2894 cache
= *this_cache
;
2896 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
2900 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
2901 struct frame_info
*this_frame
,
2902 void **this_prologue_cache
)
2904 CORE_ADDR addr_in_block
;
2907 addr_in_block
= get_frame_address_in_block (this_frame
);
2908 if (in_plt_section (addr_in_block
, NULL
)
2909 /* We also use the stub winder if the target memory is unreadable
2910 to avoid having the prologue unwinder trying to read it. */
2911 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2917 struct frame_unwind arm_stub_unwind
= {
2919 default_frame_unwind_stop_reason
,
2921 arm_prologue_prev_register
,
2923 arm_stub_unwind_sniffer
2926 /* Put here the code to store, into CACHE->saved_regs, the addresses
2927 of the saved registers of frame described by THIS_FRAME. CACHE is
2930 static struct arm_prologue_cache
*
2931 arm_m_exception_cache (struct frame_info
*this_frame
)
2933 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2934 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2935 struct arm_prologue_cache
*cache
;
2936 CORE_ADDR unwound_sp
;
2939 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2940 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2942 unwound_sp
= get_frame_register_unsigned (this_frame
,
2945 /* The hardware saves eight 32-bit words, comprising xPSR,
2946 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
2947 "B1.5.6 Exception entry behavior" in
2948 "ARMv7-M Architecture Reference Manual". */
2949 cache
->saved_regs
[0].addr
= unwound_sp
;
2950 cache
->saved_regs
[1].addr
= unwound_sp
+ 4;
2951 cache
->saved_regs
[2].addr
= unwound_sp
+ 8;
2952 cache
->saved_regs
[3].addr
= unwound_sp
+ 12;
2953 cache
->saved_regs
[12].addr
= unwound_sp
+ 16;
2954 cache
->saved_regs
[14].addr
= unwound_sp
+ 20;
2955 cache
->saved_regs
[15].addr
= unwound_sp
+ 24;
2956 cache
->saved_regs
[ARM_PS_REGNUM
].addr
= unwound_sp
+ 28;
2958 /* If bit 9 of the saved xPSR is set, then there is a four-byte
2959 aligner between the top of the 32-byte stack frame and the
2960 previous context's stack pointer. */
2961 cache
->prev_sp
= unwound_sp
+ 32;
2962 if (safe_read_memory_integer (unwound_sp
+ 28, 4, byte_order
, &xpsr
)
2963 && (xpsr
& (1 << 9)) != 0)
2964 cache
->prev_sp
+= 4;
2969 /* Implementation of function hook 'this_id' in
2970 'struct frame_uwnind'. */
2973 arm_m_exception_this_id (struct frame_info
*this_frame
,
2975 struct frame_id
*this_id
)
2977 struct arm_prologue_cache
*cache
;
2979 if (*this_cache
== NULL
)
2980 *this_cache
= arm_m_exception_cache (this_frame
);
2981 cache
= *this_cache
;
2983 /* Our frame ID for a stub frame is the current SP and LR. */
2984 *this_id
= frame_id_build (cache
->prev_sp
,
2985 get_frame_pc (this_frame
));
2988 /* Implementation of function hook 'prev_register' in
2989 'struct frame_uwnind'. */
2991 static struct value
*
2992 arm_m_exception_prev_register (struct frame_info
*this_frame
,
2996 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2997 struct arm_prologue_cache
*cache
;
2999 if (*this_cache
== NULL
)
3000 *this_cache
= arm_m_exception_cache (this_frame
);
3001 cache
= *this_cache
;
3003 /* The value was already reconstructed into PREV_SP. */
3004 if (prev_regnum
== ARM_SP_REGNUM
)
3005 return frame_unwind_got_constant (this_frame
, prev_regnum
,
3008 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
3012 /* Implementation of function hook 'sniffer' in
3013 'struct frame_uwnind'. */
3016 arm_m_exception_unwind_sniffer (const struct frame_unwind
*self
,
3017 struct frame_info
*this_frame
,
3018 void **this_prologue_cache
)
3020 CORE_ADDR this_pc
= get_frame_pc (this_frame
);
3022 /* No need to check is_m; this sniffer is only registered for
3023 M-profile architectures. */
3025 /* Exception frames return to one of these magic PCs. Other values
3026 are not defined as of v7-M. See details in "B1.5.8 Exception
3027 return behavior" in "ARMv7-M Architecture Reference Manual". */
3028 if (this_pc
== 0xfffffff1 || this_pc
== 0xfffffff9
3029 || this_pc
== 0xfffffffd)
3035 /* Frame unwinder for M-profile exceptions. */
3037 struct frame_unwind arm_m_exception_unwind
=
3040 default_frame_unwind_stop_reason
,
3041 arm_m_exception_this_id
,
3042 arm_m_exception_prev_register
,
3044 arm_m_exception_unwind_sniffer
3048 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
3050 struct arm_prologue_cache
*cache
;
3052 if (*this_cache
== NULL
)
3053 *this_cache
= arm_make_prologue_cache (this_frame
);
3054 cache
= *this_cache
;
3056 return cache
->prev_sp
- cache
->framesize
;
3059 struct frame_base arm_normal_base
= {
3060 &arm_prologue_unwind
,
3061 arm_normal_frame_base
,
3062 arm_normal_frame_base
,
3063 arm_normal_frame_base
3066 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3067 dummy frame. The frame ID's base needs to match the TOS value
3068 saved by save_dummy_frame_tos() and returned from
3069 arm_push_dummy_call, and the PC needs to match the dummy frame's
3072 static struct frame_id
3073 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3075 return frame_id_build (get_frame_register_unsigned (this_frame
,
3077 get_frame_pc (this_frame
));
3080 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3081 be used to construct the previous frame's ID, after looking up the
3082 containing function). */
3085 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3088 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
3089 return arm_addr_bits_remove (gdbarch
, pc
);
3093 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3095 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
3098 static struct value
*
3099 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
3102 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
3104 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
3109 /* The PC is normally copied from the return column, which
3110 describes saves of LR. However, that version may have an
3111 extra bit set to indicate Thumb state. The bit is not
3113 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3114 return frame_unwind_got_constant (this_frame
, regnum
,
3115 arm_addr_bits_remove (gdbarch
, lr
));
3118 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3119 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
3120 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3121 if (IS_THUMB_ADDR (lr
))
3125 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
3128 internal_error (__FILE__
, __LINE__
,
3129 _("Unexpected register %d"), regnum
);
3134 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3135 struct dwarf2_frame_state_reg
*reg
,
3136 struct frame_info
*this_frame
)
3142 reg
->how
= DWARF2_FRAME_REG_FN
;
3143 reg
->loc
.fn
= arm_dwarf2_prev_register
;
3146 reg
->how
= DWARF2_FRAME_REG_CFA
;
3151 /* Return true if we are in the function's epilogue, i.e. after the
3152 instruction that destroyed the function's stack frame. */
3155 thumb_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3157 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3158 unsigned int insn
, insn2
;
3159 int found_return
= 0, found_stack_adjust
= 0;
3160 CORE_ADDR func_start
, func_end
;
3164 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3167 /* The epilogue is a sequence of instructions along the following lines:
3169 - add stack frame size to SP or FP
3170 - [if frame pointer used] restore SP from FP
3171 - restore registers from SP [may include PC]
3172 - a return-type instruction [if PC wasn't already restored]
3174 In a first pass, we scan forward from the current PC and verify the
3175 instructions we find as compatible with this sequence, ending in a
3178 However, this is not sufficient to distinguish indirect function calls
3179 within a function from indirect tail calls in the epilogue in some cases.
3180 Therefore, if we didn't already find any SP-changing instruction during
3181 forward scan, we add a backward scanning heuristic to ensure we actually
3182 are in the epilogue. */
3185 while (scan_pc
< func_end
&& !found_return
)
3187 if (target_read_memory (scan_pc
, buf
, 2))
3191 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3193 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3195 else if (insn
== 0x46f7) /* mov pc, lr */
3197 else if (insn
== 0x46bd) /* mov sp, r7 */
3198 found_stack_adjust
= 1;
3199 else if ((insn
& 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3200 found_stack_adjust
= 1;
3201 else if ((insn
& 0xfe00) == 0xbc00) /* pop <registers> */
3203 found_stack_adjust
= 1;
3204 if (insn
& 0x0100) /* <registers> include PC. */
3207 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instruction */
3209 if (target_read_memory (scan_pc
, buf
, 2))
3213 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3215 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3217 found_stack_adjust
= 1;
3218 if (insn2
& 0x8000) /* <registers> include PC. */
3221 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3222 && (insn2
& 0x0fff) == 0x0b04)
3224 found_stack_adjust
= 1;
3225 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
3228 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3229 && (insn2
& 0x0e00) == 0x0a00)
3230 found_stack_adjust
= 1;
3241 /* Since any instruction in the epilogue sequence, with the possible
3242 exception of return itself, updates the stack pointer, we need to
3243 scan backwards for at most one instruction. Try either a 16-bit or
3244 a 32-bit instruction. This is just a heuristic, so we do not worry
3245 too much about false positives. */
3247 if (!found_stack_adjust
)
3249 if (pc
- 4 < func_start
)
3251 if (target_read_memory (pc
- 4, buf
, 4))
3254 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3255 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
3257 if (insn2
== 0x46bd) /* mov sp, r7 */
3258 found_stack_adjust
= 1;
3259 else if ((insn2
& 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
3260 found_stack_adjust
= 1;
3261 else if ((insn2
& 0xff00) == 0xbc00) /* pop <registers> without PC */
3262 found_stack_adjust
= 1;
3263 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3264 found_stack_adjust
= 1;
3265 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3266 && (insn2
& 0x0fff) == 0x0b04)
3267 found_stack_adjust
= 1;
3268 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3269 && (insn2
& 0x0e00) == 0x0a00)
3270 found_stack_adjust
= 1;
3273 return found_stack_adjust
;
3276 /* Return true if we are in the function's epilogue, i.e. after the
3277 instruction that destroyed the function's stack frame. */
3280 arm_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3282 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3284 int found_return
, found_stack_adjust
;
3285 CORE_ADDR func_start
, func_end
;
3287 if (arm_pc_is_thumb (gdbarch
, pc
))
3288 return thumb_in_function_epilogue_p (gdbarch
, pc
);
3290 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3293 /* We are in the epilogue if the previous instruction was a stack
3294 adjustment and the next instruction is a possible return (bx, mov
3295 pc, or pop). We could have to scan backwards to find the stack
3296 adjustment, or forwards to find the return, but this is a decent
3297 approximation. First scan forwards. */
3300 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3301 if (bits (insn
, 28, 31) != INST_NV
)
3303 if ((insn
& 0x0ffffff0) == 0x012fff10)
3306 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
3309 else if ((insn
& 0x0fff0000) == 0x08bd0000
3310 && (insn
& 0x0000c000) != 0)
3311 /* POP (LDMIA), including PC or LR. */
3318 /* Scan backwards. This is just a heuristic, so do not worry about
3319 false positives from mode changes. */
3321 if (pc
< func_start
+ 4)
3324 found_stack_adjust
= 0;
3325 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
3326 if (bits (insn
, 28, 31) != INST_NV
)
3328 if ((insn
& 0x0df0f000) == 0x0080d000)
3329 /* ADD SP (register or immediate). */
3330 found_stack_adjust
= 1;
3331 else if ((insn
& 0x0df0f000) == 0x0040d000)
3332 /* SUB SP (register or immediate). */
3333 found_stack_adjust
= 1;
3334 else if ((insn
& 0x0ffffff0) == 0x01a0d000)
3336 found_stack_adjust
= 1;
3337 else if ((insn
& 0x0fff0000) == 0x08bd0000)
3339 found_stack_adjust
= 1;
3340 else if ((insn
& 0x0fff0000) == 0x049d0000)
3341 /* POP of a single register. */
3342 found_stack_adjust
= 1;
3345 if (found_stack_adjust
)
3352 /* When arguments must be pushed onto the stack, they go on in reverse
3353 order. The code below implements a FILO (stack) to do this. */
3358 struct stack_item
*prev
;
3362 static struct stack_item
*
3363 push_stack_item (struct stack_item
*prev
, const void *contents
, int len
)
3365 struct stack_item
*si
;
3366 si
= xmalloc (sizeof (struct stack_item
));
3367 si
->data
= xmalloc (len
);
3370 memcpy (si
->data
, contents
, len
);
3374 static struct stack_item
*
3375 pop_stack_item (struct stack_item
*si
)
3377 struct stack_item
*dead
= si
;
3385 /* Return the alignment (in bytes) of the given type. */
3388 arm_type_align (struct type
*t
)
3394 t
= check_typedef (t
);
3395 switch (TYPE_CODE (t
))
3398 /* Should never happen. */
3399 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
3403 case TYPE_CODE_ENUM
:
3407 case TYPE_CODE_RANGE
:
3409 case TYPE_CODE_CHAR
:
3410 case TYPE_CODE_BOOL
:
3411 return TYPE_LENGTH (t
);
3413 case TYPE_CODE_ARRAY
:
3414 case TYPE_CODE_COMPLEX
:
3415 /* TODO: What about vector types? */
3416 return arm_type_align (TYPE_TARGET_TYPE (t
));
3418 case TYPE_CODE_STRUCT
:
3419 case TYPE_CODE_UNION
:
3421 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
3423 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
3431 /* Possible base types for a candidate for passing and returning in
3434 enum arm_vfp_cprc_base_type
3443 /* The length of one element of base type B. */
3446 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
3450 case VFP_CPRC_SINGLE
:
3452 case VFP_CPRC_DOUBLE
:
3454 case VFP_CPRC_VEC64
:
3456 case VFP_CPRC_VEC128
:
3459 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3464 /* The character ('s', 'd' or 'q') for the type of VFP register used
3465 for passing base type B. */
3468 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
3472 case VFP_CPRC_SINGLE
:
3474 case VFP_CPRC_DOUBLE
:
3476 case VFP_CPRC_VEC64
:
3478 case VFP_CPRC_VEC128
:
3481 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3486 /* Determine whether T may be part of a candidate for passing and
3487 returning in VFP registers, ignoring the limit on the total number
3488 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3489 classification of the first valid component found; if it is not
3490 VFP_CPRC_UNKNOWN, all components must have the same classification
3491 as *BASE_TYPE. If it is found that T contains a type not permitted
3492 for passing and returning in VFP registers, a type differently
3493 classified from *BASE_TYPE, or two types differently classified
3494 from each other, return -1, otherwise return the total number of
3495 base-type elements found (possibly 0 in an empty structure or
3496 array). Vectors and complex types are not currently supported,
3497 matching the generic AAPCS support. */
3500 arm_vfp_cprc_sub_candidate (struct type
*t
,
3501 enum arm_vfp_cprc_base_type
*base_type
)
3503 t
= check_typedef (t
);
3504 switch (TYPE_CODE (t
))
3507 switch (TYPE_LENGTH (t
))
3510 if (*base_type
== VFP_CPRC_UNKNOWN
)
3511 *base_type
= VFP_CPRC_SINGLE
;
3512 else if (*base_type
!= VFP_CPRC_SINGLE
)
3517 if (*base_type
== VFP_CPRC_UNKNOWN
)
3518 *base_type
= VFP_CPRC_DOUBLE
;
3519 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3528 case TYPE_CODE_ARRAY
:
3532 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
), base_type
);
3535 if (TYPE_LENGTH (t
) == 0)
3537 gdb_assert (count
== 0);
3540 else if (count
== 0)
3542 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3543 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
3544 return TYPE_LENGTH (t
) / unitlen
;
3548 case TYPE_CODE_STRUCT
:
3553 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3555 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3557 if (sub_count
== -1)
3561 if (TYPE_LENGTH (t
) == 0)
3563 gdb_assert (count
== 0);
3566 else if (count
== 0)
3568 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3569 if (TYPE_LENGTH (t
) != unitlen
* count
)
3574 case TYPE_CODE_UNION
:
3579 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3581 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3583 if (sub_count
== -1)
3585 count
= (count
> sub_count
? count
: sub_count
);
3587 if (TYPE_LENGTH (t
) == 0)
3589 gdb_assert (count
== 0);
3592 else if (count
== 0)
3594 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3595 if (TYPE_LENGTH (t
) != unitlen
* count
)
3607 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3608 if passed to or returned from a non-variadic function with the VFP
3609 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3610 *BASE_TYPE to the base type for T and *COUNT to the number of
3611 elements of that base type before returning. */
3614 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
3617 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
3618 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
3619 if (c
<= 0 || c
> 4)
3626 /* Return 1 if the VFP ABI should be used for passing arguments to and
3627 returning values from a function of type FUNC_TYPE, 0
3631 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
3633 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3634 /* Variadic functions always use the base ABI. Assume that functions
3635 without debug info are not variadic. */
3636 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
3638 /* The VFP ABI is only supported as a variant of AAPCS. */
3639 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
3641 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
3644 /* We currently only support passing parameters in integer registers, which
3645 conforms with GCC's default model, and VFP argument passing following
3646 the VFP variant of AAPCS. Several other variants exist and
3647 we should probably support some of them based on the selected ABI. */
3650 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3651 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3652 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3653 CORE_ADDR struct_addr
)
3655 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3659 struct stack_item
*si
= NULL
;
3662 unsigned vfp_regs_free
= (1 << 16) - 1;
3664 /* Determine the type of this function and whether the VFP ABI
3666 ftype
= check_typedef (value_type (function
));
3667 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
3668 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
3669 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
3671 /* Set the return address. For the ARM, the return breakpoint is
3672 always at BP_ADDR. */
3673 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
3675 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
3677 /* Walk through the list of args and determine how large a temporary
3678 stack is required. Need to take care here as structs may be
3679 passed on the stack, and we have to push them. */
3682 argreg
= ARM_A1_REGNUM
;
3685 /* The struct_return pointer occupies the first parameter
3686 passing register. */
3690 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
3691 gdbarch_register_name (gdbarch
, argreg
),
3692 paddress (gdbarch
, struct_addr
));
3693 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
3697 for (argnum
= 0; argnum
< nargs
; argnum
++)
3700 struct type
*arg_type
;
3701 struct type
*target_type
;
3702 enum type_code typecode
;
3703 const bfd_byte
*val
;
3705 enum arm_vfp_cprc_base_type vfp_base_type
;
3707 int may_use_core_reg
= 1;
3709 arg_type
= check_typedef (value_type (args
[argnum
]));
3710 len
= TYPE_LENGTH (arg_type
);
3711 target_type
= TYPE_TARGET_TYPE (arg_type
);
3712 typecode
= TYPE_CODE (arg_type
);
3713 val
= value_contents (args
[argnum
]);
3715 align
= arm_type_align (arg_type
);
3716 /* Round alignment up to a whole number of words. */
3717 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
3718 /* Different ABIs have different maximum alignments. */
3719 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
3721 /* The APCS ABI only requires word alignment. */
3722 align
= INT_REGISTER_SIZE
;
3726 /* The AAPCS requires at most doubleword alignment. */
3727 if (align
> INT_REGISTER_SIZE
* 2)
3728 align
= INT_REGISTER_SIZE
* 2;
3732 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
3740 /* Because this is a CPRC it cannot go in a core register or
3741 cause a core register to be skipped for alignment.
3742 Either it goes in VFP registers and the rest of this loop
3743 iteration is skipped for this argument, or it goes on the
3744 stack (and the stack alignment code is correct for this
3746 may_use_core_reg
= 0;
3748 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
3749 shift
= unit_length
/ 4;
3750 mask
= (1 << (shift
* vfp_base_count
)) - 1;
3751 for (regno
= 0; regno
< 16; regno
+= shift
)
3752 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
3761 vfp_regs_free
&= ~(mask
<< regno
);
3762 reg_scaled
= regno
/ shift
;
3763 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
3764 for (i
= 0; i
< vfp_base_count
; i
++)
3768 if (reg_char
== 'q')
3769 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
3770 val
+ i
* unit_length
);
3773 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d",
3774 reg_char
, reg_scaled
+ i
);
3775 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3777 regcache_cooked_write (regcache
, regnum
,
3778 val
+ i
* unit_length
);
3785 /* This CPRC could not go in VFP registers, so all VFP
3786 registers are now marked as used. */
3791 /* Push stack padding for dowubleword alignment. */
3792 if (nstack
& (align
- 1))
3794 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3795 nstack
+= INT_REGISTER_SIZE
;
3798 /* Doubleword aligned quantities must go in even register pairs. */
3799 if (may_use_core_reg
3800 && argreg
<= ARM_LAST_ARG_REGNUM
3801 && align
> INT_REGISTER_SIZE
3805 /* If the argument is a pointer to a function, and it is a
3806 Thumb function, create a LOCAL copy of the value and set
3807 the THUMB bit in it. */
3808 if (TYPE_CODE_PTR
== typecode
3809 && target_type
!= NULL
3810 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
3812 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
3813 if (arm_pc_is_thumb (gdbarch
, regval
))
3815 bfd_byte
*copy
= alloca (len
);
3816 store_unsigned_integer (copy
, len
, byte_order
,
3817 MAKE_THUMB_ADDR (regval
));
3822 /* Copy the argument to general registers or the stack in
3823 register-sized pieces. Large arguments are split between
3824 registers and stack. */
3827 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
3829 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
3831 /* The argument is being passed in a general purpose
3834 = extract_unsigned_integer (val
, partial_len
, byte_order
);
3835 if (byte_order
== BFD_ENDIAN_BIG
)
3836 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
3838 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
3840 gdbarch_register_name
3842 phex (regval
, INT_REGISTER_SIZE
));
3843 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3848 /* Push the arguments onto the stack. */
3850 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
3852 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3853 nstack
+= INT_REGISTER_SIZE
;
3860 /* If we have an odd number of words to push, then decrement the stack
3861 by one word now, so first stack argument will be dword aligned. */
3868 write_memory (sp
, si
->data
, si
->len
);
3869 si
= pop_stack_item (si
);
3872 /* Finally, update teh SP register. */
3873 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
3879 /* Always align the frame to an 8-byte boundary. This is required on
3880 some platforms and harmless on the rest. */
3883 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3885 /* Align the stack to eight bytes. */
3886 return sp
& ~ (CORE_ADDR
) 7;
3890 print_fpu_flags (int flags
)
3892 if (flags
& (1 << 0))
3893 fputs ("IVO ", stdout
);
3894 if (flags
& (1 << 1))
3895 fputs ("DVZ ", stdout
);
3896 if (flags
& (1 << 2))
3897 fputs ("OFL ", stdout
);
3898 if (flags
& (1 << 3))
3899 fputs ("UFL ", stdout
);
3900 if (flags
& (1 << 4))
3901 fputs ("INX ", stdout
);
3905 /* Print interesting information about the floating point processor
3906 (if present) or emulator. */
3908 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
3909 struct frame_info
*frame
, const char *args
)
3911 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
3914 type
= (status
>> 24) & 127;
3915 if (status
& (1 << 31))
3916 printf (_("Hardware FPU type %d\n"), type
);
3918 printf (_("Software FPU type %d\n"), type
);
3919 /* i18n: [floating point unit] mask */
3920 fputs (_("mask: "), stdout
);
3921 print_fpu_flags (status
>> 16);
3922 /* i18n: [floating point unit] flags */
3923 fputs (_("flags: "), stdout
);
3924 print_fpu_flags (status
);
3927 /* Construct the ARM extended floating point type. */
3928 static struct type
*
3929 arm_ext_type (struct gdbarch
*gdbarch
)
3931 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3933 if (!tdep
->arm_ext_type
)
3935 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
3936 floatformats_arm_ext
);
3938 return tdep
->arm_ext_type
;
3941 static struct type
*
3942 arm_neon_double_type (struct gdbarch
*gdbarch
)
3944 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3946 if (tdep
->neon_double_type
== NULL
)
3948 struct type
*t
, *elem
;
3950 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
3952 elem
= builtin_type (gdbarch
)->builtin_uint8
;
3953 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
3954 elem
= builtin_type (gdbarch
)->builtin_uint16
;
3955 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
3956 elem
= builtin_type (gdbarch
)->builtin_uint32
;
3957 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
3958 elem
= builtin_type (gdbarch
)->builtin_uint64
;
3959 append_composite_type_field (t
, "u64", elem
);
3960 elem
= builtin_type (gdbarch
)->builtin_float
;
3961 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
3962 elem
= builtin_type (gdbarch
)->builtin_double
;
3963 append_composite_type_field (t
, "f64", elem
);
3965 TYPE_VECTOR (t
) = 1;
3966 TYPE_NAME (t
) = "neon_d";
3967 tdep
->neon_double_type
= t
;
3970 return tdep
->neon_double_type
;
3973 /* FIXME: The vector types are not correctly ordered on big-endian
3974 targets. Just as s0 is the low bits of d0, d0[0] is also the low
3975 bits of d0 - regardless of what unit size is being held in d0. So
3976 the offset of the first uint8 in d0 is 7, but the offset of the
3977 first float is 4. This code works as-is for little-endian
3980 static struct type
*
3981 arm_neon_quad_type (struct gdbarch
*gdbarch
)
3983 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3985 if (tdep
->neon_quad_type
== NULL
)
3987 struct type
*t
, *elem
;
3989 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
3991 elem
= builtin_type (gdbarch
)->builtin_uint8
;
3992 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
3993 elem
= builtin_type (gdbarch
)->builtin_uint16
;
3994 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
3995 elem
= builtin_type (gdbarch
)->builtin_uint32
;
3996 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
3997 elem
= builtin_type (gdbarch
)->builtin_uint64
;
3998 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
3999 elem
= builtin_type (gdbarch
)->builtin_float
;
4000 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
4001 elem
= builtin_type (gdbarch
)->builtin_double
;
4002 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
4004 TYPE_VECTOR (t
) = 1;
4005 TYPE_NAME (t
) = "neon_q";
4006 tdep
->neon_quad_type
= t
;
4009 return tdep
->neon_quad_type
;
4012 /* Return the GDB type object for the "standard" data type of data in
4015 static struct type
*
4016 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
4018 int num_regs
= gdbarch_num_regs (gdbarch
);
4020 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
4021 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
4022 return builtin_type (gdbarch
)->builtin_float
;
4024 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
4025 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
4026 return arm_neon_quad_type (gdbarch
);
4028 /* If the target description has register information, we are only
4029 in this function so that we can override the types of
4030 double-precision registers for NEON. */
4031 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
4033 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
4035 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
4036 && TYPE_CODE (t
) == TYPE_CODE_FLT
4037 && gdbarch_tdep (gdbarch
)->have_neon
)
4038 return arm_neon_double_type (gdbarch
);
4043 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
4045 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
4046 return builtin_type (gdbarch
)->builtin_void
;
4048 return arm_ext_type (gdbarch
);
4050 else if (regnum
== ARM_SP_REGNUM
)
4051 return builtin_type (gdbarch
)->builtin_data_ptr
;
4052 else if (regnum
== ARM_PC_REGNUM
)
4053 return builtin_type (gdbarch
)->builtin_func_ptr
;
4054 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
4055 /* These registers are only supported on targets which supply
4056 an XML description. */
4057 return builtin_type (gdbarch
)->builtin_int0
;
4059 return builtin_type (gdbarch
)->builtin_uint32
;
4062 /* Map a DWARF register REGNUM onto the appropriate GDB register
4066 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
4068 /* Core integer regs. */
4069 if (reg
>= 0 && reg
<= 15)
4072 /* Legacy FPA encoding. These were once used in a way which
4073 overlapped with VFP register numbering, so their use is
4074 discouraged, but GDB doesn't support the ARM toolchain
4075 which used them for VFP. */
4076 if (reg
>= 16 && reg
<= 23)
4077 return ARM_F0_REGNUM
+ reg
- 16;
4079 /* New assignments for the FPA registers. */
4080 if (reg
>= 96 && reg
<= 103)
4081 return ARM_F0_REGNUM
+ reg
- 96;
4083 /* WMMX register assignments. */
4084 if (reg
>= 104 && reg
<= 111)
4085 return ARM_WCGR0_REGNUM
+ reg
- 104;
4087 if (reg
>= 112 && reg
<= 127)
4088 return ARM_WR0_REGNUM
+ reg
- 112;
4090 if (reg
>= 192 && reg
<= 199)
4091 return ARM_WC0_REGNUM
+ reg
- 192;
4093 /* VFP v2 registers. A double precision value is actually
4094 in d1 rather than s2, but the ABI only defines numbering
4095 for the single precision registers. This will "just work"
4096 in GDB for little endian targets (we'll read eight bytes,
4097 starting in s0 and then progressing to s1), but will be
4098 reversed on big endian targets with VFP. This won't
4099 be a problem for the new Neon quad registers; you're supposed
4100 to use DW_OP_piece for those. */
4101 if (reg
>= 64 && reg
<= 95)
4105 xsnprintf (name_buf
, sizeof (name_buf
), "s%d", reg
- 64);
4106 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4110 /* VFP v3 / Neon registers. This range is also used for VFP v2
4111 registers, except that it now describes d0 instead of s0. */
4112 if (reg
>= 256 && reg
<= 287)
4116 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", reg
- 256);
4117 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4124 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4126 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
4129 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
4131 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
4132 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
4134 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
4135 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
4137 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
4138 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
4140 if (reg
< NUM_GREGS
)
4141 return SIM_ARM_R0_REGNUM
+ reg
;
4144 if (reg
< NUM_FREGS
)
4145 return SIM_ARM_FP0_REGNUM
+ reg
;
4148 if (reg
< NUM_SREGS
)
4149 return SIM_ARM_FPS_REGNUM
+ reg
;
4152 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
4155 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4156 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4157 It is thought that this is is the floating-point register format on
4158 little-endian systems. */
4161 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
4162 void *dbl
, int endianess
)
4166 if (endianess
== BFD_ENDIAN_BIG
)
4167 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
4169 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4171 floatformat_from_doublest (fmt
, &d
, dbl
);
4175 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
4180 floatformat_to_doublest (fmt
, ptr
, &d
);
4181 if (endianess
== BFD_ENDIAN_BIG
)
4182 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
4184 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4189 condition_true (unsigned long cond
, unsigned long status_reg
)
4191 if (cond
== INST_AL
|| cond
== INST_NV
)
4197 return ((status_reg
& FLAG_Z
) != 0);
4199 return ((status_reg
& FLAG_Z
) == 0);
4201 return ((status_reg
& FLAG_C
) != 0);
4203 return ((status_reg
& FLAG_C
) == 0);
4205 return ((status_reg
& FLAG_N
) != 0);
4207 return ((status_reg
& FLAG_N
) == 0);
4209 return ((status_reg
& FLAG_V
) != 0);
4211 return ((status_reg
& FLAG_V
) == 0);
4213 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
4215 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
4217 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
4219 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
4221 return (((status_reg
& FLAG_Z
) == 0)
4222 && (((status_reg
& FLAG_N
) == 0)
4223 == ((status_reg
& FLAG_V
) == 0)));
4225 return (((status_reg
& FLAG_Z
) != 0)
4226 || (((status_reg
& FLAG_N
) == 0)
4227 != ((status_reg
& FLAG_V
) == 0)));
4232 static unsigned long
4233 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
4234 unsigned long pc_val
, unsigned long status_reg
)
4236 unsigned long res
, shift
;
4237 int rm
= bits (inst
, 0, 3);
4238 unsigned long shifttype
= bits (inst
, 5, 6);
4242 int rs
= bits (inst
, 8, 11);
4243 shift
= (rs
== 15 ? pc_val
+ 8
4244 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
4247 shift
= bits (inst
, 7, 11);
4249 res
= (rm
== ARM_PC_REGNUM
4250 ? (pc_val
+ (bit (inst
, 4) ? 12 : 8))
4251 : get_frame_register_unsigned (frame
, rm
));
4256 res
= shift
>= 32 ? 0 : res
<< shift
;
4260 res
= shift
>= 32 ? 0 : res
>> shift
;
4266 res
= ((res
& 0x80000000L
)
4267 ? ~((~res
) >> shift
) : res
>> shift
);
4270 case 3: /* ROR/RRX */
4273 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
4275 res
= (res
>> shift
) | (res
<< (32 - shift
));
4279 return res
& 0xffffffff;
4282 /* Return number of 1-bits in VAL. */
4285 bitcount (unsigned long val
)
4288 for (nbits
= 0; val
!= 0; nbits
++)
4289 val
&= val
- 1; /* Delete rightmost 1-bit in val. */
4293 /* Return the size in bytes of the complete Thumb instruction whose
4294 first halfword is INST1. */
4297 thumb_insn_size (unsigned short inst1
)
4299 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
4306 thumb_advance_itstate (unsigned int itstate
)
4308 /* Preserve IT[7:5], the first three bits of the condition. Shift
4309 the upcoming condition flags left by one bit. */
4310 itstate
= (itstate
& 0xe0) | ((itstate
<< 1) & 0x1f);
4312 /* If we have finished the IT block, clear the state. */
4313 if ((itstate
& 0x0f) == 0)
4319 /* Find the next PC after the current instruction executes. In some
4320 cases we can not statically determine the answer (see the IT state
4321 handling in this function); in that case, a breakpoint may be
4322 inserted in addition to the returned PC, which will be used to set
4323 another breakpoint by our caller. */
4326 thumb_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
)
4328 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4329 struct address_space
*aspace
= get_frame_address_space (frame
);
4330 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4331 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4332 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
4333 unsigned short inst1
;
4334 CORE_ADDR nextpc
= pc
+ 2; /* Default is next instruction. */
4335 unsigned long offset
;
4336 ULONGEST status
, itstate
;
4338 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4339 pc_val
= MAKE_THUMB_ADDR (pc_val
);
4341 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
4343 /* Thumb-2 conditional execution support. There are eight bits in
4344 the CPSR which describe conditional execution state. Once
4345 reconstructed (they're in a funny order), the low five bits
4346 describe the low bit of the condition for each instruction and
4347 how many instructions remain. The high three bits describe the
4348 base condition. One of the low four bits will be set if an IT
4349 block is active. These bits read as zero on earlier
4351 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
4352 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
4354 /* If-Then handling. On GNU/Linux, where this routine is used, we
4355 use an undefined instruction as a breakpoint. Unlike BKPT, IT
4356 can disable execution of the undefined instruction. So we might
4357 miss the breakpoint if we set it on a skipped conditional
4358 instruction. Because conditional instructions can change the
4359 flags, affecting the execution of further instructions, we may
4360 need to set two breakpoints. */
4362 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
!= NULL
)
4364 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4366 /* An IT instruction. Because this instruction does not
4367 modify the flags, we can accurately predict the next
4368 executed instruction. */
4369 itstate
= inst1
& 0x00ff;
4370 pc
+= thumb_insn_size (inst1
);
4372 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
4374 inst1
= read_memory_unsigned_integer (pc
, 2,
4375 byte_order_for_code
);
4376 pc
+= thumb_insn_size (inst1
);
4377 itstate
= thumb_advance_itstate (itstate
);
4380 return MAKE_THUMB_ADDR (pc
);
4382 else if (itstate
!= 0)
4384 /* We are in a conditional block. Check the condition. */
4385 if (! condition_true (itstate
>> 4, status
))
4387 /* Advance to the next executed instruction. */
4388 pc
+= thumb_insn_size (inst1
);
4389 itstate
= thumb_advance_itstate (itstate
);
4391 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
4393 inst1
= read_memory_unsigned_integer (pc
, 2,
4394 byte_order_for_code
);
4395 pc
+= thumb_insn_size (inst1
);
4396 itstate
= thumb_advance_itstate (itstate
);
4399 return MAKE_THUMB_ADDR (pc
);
4401 else if ((itstate
& 0x0f) == 0x08)
4403 /* This is the last instruction of the conditional
4404 block, and it is executed. We can handle it normally
4405 because the following instruction is not conditional,
4406 and we must handle it normally because it is
4407 permitted to branch. Fall through. */
4413 /* There are conditional instructions after this one.
4414 If this instruction modifies the flags, then we can
4415 not predict what the next executed instruction will
4416 be. Fortunately, this instruction is architecturally
4417 forbidden to branch; we know it will fall through.
4418 Start by skipping past it. */
4419 pc
+= thumb_insn_size (inst1
);
4420 itstate
= thumb_advance_itstate (itstate
);
4422 /* Set a breakpoint on the following instruction. */
4423 gdb_assert ((itstate
& 0x0f) != 0);
4424 arm_insert_single_step_breakpoint (gdbarch
, aspace
,
4425 MAKE_THUMB_ADDR (pc
));
4426 cond_negated
= (itstate
>> 4) & 1;
4428 /* Skip all following instructions with the same
4429 condition. If there is a later instruction in the IT
4430 block with the opposite condition, set the other
4431 breakpoint there. If not, then set a breakpoint on
4432 the instruction after the IT block. */
4435 inst1
= read_memory_unsigned_integer (pc
, 2,
4436 byte_order_for_code
);
4437 pc
+= thumb_insn_size (inst1
);
4438 itstate
= thumb_advance_itstate (itstate
);
4440 while (itstate
!= 0 && ((itstate
>> 4) & 1) == cond_negated
);
4442 return MAKE_THUMB_ADDR (pc
);
4446 else if (itstate
& 0x0f)
4448 /* We are in a conditional block. Check the condition. */
4449 int cond
= itstate
>> 4;
4451 if (! condition_true (cond
, status
))
4452 /* Advance to the next instruction. All the 32-bit
4453 instructions share a common prefix. */
4454 return MAKE_THUMB_ADDR (pc
+ thumb_insn_size (inst1
));
4456 /* Otherwise, handle the instruction normally. */
4459 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
4463 /* Fetch the saved PC from the stack. It's stored above
4464 all of the other registers. */
4465 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
4466 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
4467 nextpc
= read_memory_unsigned_integer (sp
+ offset
, 4, byte_order
);
4469 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
4471 unsigned long cond
= bits (inst1
, 8, 11);
4472 if (cond
== 0x0f) /* 0x0f = SWI */
4474 struct gdbarch_tdep
*tdep
;
4475 tdep
= gdbarch_tdep (gdbarch
);
4477 if (tdep
->syscall_next_pc
!= NULL
)
4478 nextpc
= tdep
->syscall_next_pc (frame
);
4481 else if (cond
!= 0x0f && condition_true (cond
, status
))
4482 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
4484 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
4486 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
4488 else if (thumb_insn_size (inst1
) == 4) /* 32-bit instruction */
4490 unsigned short inst2
;
4491 inst2
= read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
4493 /* Default to the next instruction. */
4495 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4497 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
4499 /* Branches and miscellaneous control instructions. */
4501 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
4504 int j1
, j2
, imm1
, imm2
;
4506 imm1
= sbits (inst1
, 0, 10);
4507 imm2
= bits (inst2
, 0, 10);
4508 j1
= bit (inst2
, 13);
4509 j2
= bit (inst2
, 11);
4511 offset
= ((imm1
<< 12) + (imm2
<< 1));
4512 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
4514 nextpc
= pc_val
+ offset
;
4515 /* For BLX make sure to clear the low bits. */
4516 if (bit (inst2
, 12) == 0)
4517 nextpc
= nextpc
& 0xfffffffc;
4519 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
4521 /* SUBS PC, LR, #imm8. */
4522 nextpc
= get_frame_register_unsigned (frame
, ARM_LR_REGNUM
);
4523 nextpc
-= inst2
& 0x00ff;
4525 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
4527 /* Conditional branch. */
4528 if (condition_true (bits (inst1
, 6, 9), status
))
4530 int sign
, j1
, j2
, imm1
, imm2
;
4532 sign
= sbits (inst1
, 10, 10);
4533 imm1
= bits (inst1
, 0, 5);
4534 imm2
= bits (inst2
, 0, 10);
4535 j1
= bit (inst2
, 13);
4536 j2
= bit (inst2
, 11);
4538 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
4539 offset
+= (imm1
<< 12) + (imm2
<< 1);
4541 nextpc
= pc_val
+ offset
;
4545 else if ((inst1
& 0xfe50) == 0xe810)
4547 /* Load multiple or RFE. */
4548 int rn
, offset
, load_pc
= 1;
4550 rn
= bits (inst1
, 0, 3);
4551 if (bit (inst1
, 7) && !bit (inst1
, 8))
4554 if (!bit (inst2
, 15))
4556 offset
= bitcount (inst2
) * 4 - 4;
4558 else if (!bit (inst1
, 7) && bit (inst1
, 8))
4561 if (!bit (inst2
, 15))
4565 else if (bit (inst1
, 7) && bit (inst1
, 8))
4570 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
4580 CORE_ADDR addr
= get_frame_register_unsigned (frame
, rn
);
4581 nextpc
= get_frame_memory_unsigned (frame
, addr
+ offset
, 4);
4584 else if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
4586 /* MOV PC or MOVS PC. */
4587 nextpc
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4588 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4590 else if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
4594 int rn
, load_pc
= 1;
4596 rn
= bits (inst1
, 0, 3);
4597 base
= get_frame_register_unsigned (frame
, rn
);
4598 if (rn
== ARM_PC_REGNUM
)
4600 base
= (base
+ 4) & ~(CORE_ADDR
) 0x3;
4602 base
+= bits (inst2
, 0, 11);
4604 base
-= bits (inst2
, 0, 11);
4606 else if (bit (inst1
, 7))
4607 base
+= bits (inst2
, 0, 11);
4608 else if (bit (inst2
, 11))
4610 if (bit (inst2
, 10))
4613 base
+= bits (inst2
, 0, 7);
4615 base
-= bits (inst2
, 0, 7);
4618 else if ((inst2
& 0x0fc0) == 0x0000)
4620 int shift
= bits (inst2
, 4, 5), rm
= bits (inst2
, 0, 3);
4621 base
+= get_frame_register_unsigned (frame
, rm
) << shift
;
4628 nextpc
= get_frame_memory_unsigned (frame
, base
, 4);
4630 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
4633 CORE_ADDR tbl_reg
, table
, offset
, length
;
4635 tbl_reg
= bits (inst1
, 0, 3);
4636 if (tbl_reg
== 0x0f)
4637 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
4639 table
= get_frame_register_unsigned (frame
, tbl_reg
);
4641 offset
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4642 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 1);
4643 nextpc
= pc_val
+ length
;
4645 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
4648 CORE_ADDR tbl_reg
, table
, offset
, length
;
4650 tbl_reg
= bits (inst1
, 0, 3);
4651 if (tbl_reg
== 0x0f)
4652 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
4654 table
= get_frame_register_unsigned (frame
, tbl_reg
);
4656 offset
= 2 * get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4657 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 2);
4658 nextpc
= pc_val
+ length
;
4661 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
4663 if (bits (inst1
, 3, 6) == 0x0f)
4664 nextpc
= UNMAKE_THUMB_ADDR (pc_val
);
4666 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
4668 else if ((inst1
& 0xff87) == 0x4687) /* mov pc, REG */
4670 if (bits (inst1
, 3, 6) == 0x0f)
4673 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
4675 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4677 else if ((inst1
& 0xf500) == 0xb100)
4680 int imm
= (bit (inst1
, 9) << 6) + (bits (inst1
, 3, 7) << 1);
4681 ULONGEST reg
= get_frame_register_unsigned (frame
, bits (inst1
, 0, 2));
4683 if (bit (inst1
, 11) && reg
!= 0)
4684 nextpc
= pc_val
+ imm
;
4685 else if (!bit (inst1
, 11) && reg
== 0)
4686 nextpc
= pc_val
+ imm
;
4691 /* Get the raw next address. PC is the current program counter, in
4692 FRAME, which is assumed to be executing in ARM mode.
4694 The value returned has the execution state of the next instruction
4695 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
4696 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
4700 arm_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
)
4702 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4703 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4704 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4705 unsigned long pc_val
;
4706 unsigned long this_instr
;
4707 unsigned long status
;
4710 pc_val
= (unsigned long) pc
;
4711 this_instr
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
4713 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
4714 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
4716 if (bits (this_instr
, 28, 31) == INST_NV
)
4717 switch (bits (this_instr
, 24, 27))
4722 /* Branch with Link and change to Thumb. */
4723 nextpc
= BranchDest (pc
, this_instr
);
4724 nextpc
|= bit (this_instr
, 24) << 1;
4725 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4731 /* Coprocessor register transfer. */
4732 if (bits (this_instr
, 12, 15) == 15)
4733 error (_("Invalid update to pc in instruction"));
4736 else if (condition_true (bits (this_instr
, 28, 31), status
))
4738 switch (bits (this_instr
, 24, 27))
4741 case 0x1: /* data processing */
4745 unsigned long operand1
, operand2
, result
= 0;
4749 if (bits (this_instr
, 12, 15) != 15)
4752 if (bits (this_instr
, 22, 25) == 0
4753 && bits (this_instr
, 4, 7) == 9) /* multiply */
4754 error (_("Invalid update to pc in instruction"));
4756 /* BX <reg>, BLX <reg> */
4757 if (bits (this_instr
, 4, 27) == 0x12fff1
4758 || bits (this_instr
, 4, 27) == 0x12fff3)
4760 rn
= bits (this_instr
, 0, 3);
4761 nextpc
= ((rn
== ARM_PC_REGNUM
)
4763 : get_frame_register_unsigned (frame
, rn
));
4768 /* Multiply into PC. */
4769 c
= (status
& FLAG_C
) ? 1 : 0;
4770 rn
= bits (this_instr
, 16, 19);
4771 operand1
= ((rn
== ARM_PC_REGNUM
)
4773 : get_frame_register_unsigned (frame
, rn
));
4775 if (bit (this_instr
, 25))
4777 unsigned long immval
= bits (this_instr
, 0, 7);
4778 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
4779 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
4782 else /* operand 2 is a shifted register. */
4783 operand2
= shifted_reg_val (frame
, this_instr
, c
,
4786 switch (bits (this_instr
, 21, 24))
4789 result
= operand1
& operand2
;
4793 result
= operand1
^ operand2
;
4797 result
= operand1
- operand2
;
4801 result
= operand2
- operand1
;
4805 result
= operand1
+ operand2
;
4809 result
= operand1
+ operand2
+ c
;
4813 result
= operand1
- operand2
+ c
;
4817 result
= operand2
- operand1
+ c
;
4823 case 0xb: /* tst, teq, cmp, cmn */
4824 result
= (unsigned long) nextpc
;
4828 result
= operand1
| operand2
;
4832 /* Always step into a function. */
4837 result
= operand1
& ~operand2
;
4845 /* In 26-bit APCS the bottom two bits of the result are
4846 ignored, and we always end up in ARM state. */
4848 nextpc
= arm_addr_bits_remove (gdbarch
, result
);
4856 case 0x5: /* data transfer */
4859 if (bit (this_instr
, 20))
4862 if (bits (this_instr
, 12, 15) == 15)
4868 if (bit (this_instr
, 22))
4869 error (_("Invalid update to pc in instruction"));
4871 /* byte write to PC */
4872 rn
= bits (this_instr
, 16, 19);
4873 base
= ((rn
== ARM_PC_REGNUM
)
4875 : get_frame_register_unsigned (frame
, rn
));
4877 if (bit (this_instr
, 24))
4880 int c
= (status
& FLAG_C
) ? 1 : 0;
4881 unsigned long offset
=
4882 (bit (this_instr
, 25)
4883 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
4884 : bits (this_instr
, 0, 11));
4886 if (bit (this_instr
, 23))
4892 (CORE_ADDR
) read_memory_unsigned_integer ((CORE_ADDR
) base
,
4899 case 0x9: /* block transfer */
4900 if (bit (this_instr
, 20))
4903 if (bit (this_instr
, 15))
4907 unsigned long rn_val
4908 = get_frame_register_unsigned (frame
,
4909 bits (this_instr
, 16, 19));
4911 if (bit (this_instr
, 23))
4914 unsigned long reglist
= bits (this_instr
, 0, 14);
4915 offset
= bitcount (reglist
) * 4;
4916 if (bit (this_instr
, 24)) /* pre */
4919 else if (bit (this_instr
, 24))
4923 (CORE_ADDR
) read_memory_unsigned_integer ((CORE_ADDR
)
4930 case 0xb: /* branch & link */
4931 case 0xa: /* branch */
4933 nextpc
= BranchDest (pc
, this_instr
);
4939 case 0xe: /* coproc ops */
4943 struct gdbarch_tdep
*tdep
;
4944 tdep
= gdbarch_tdep (gdbarch
);
4946 if (tdep
->syscall_next_pc
!= NULL
)
4947 nextpc
= tdep
->syscall_next_pc (frame
);
4953 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
4961 /* Determine next PC after current instruction executes. Will call either
4962 arm_get_next_pc_raw or thumb_get_next_pc_raw. Error out if infinite
4963 loop is detected. */
4966 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
4970 if (arm_frame_is_thumb (frame
))
4972 nextpc
= thumb_get_next_pc_raw (frame
, pc
);
4973 if (nextpc
== MAKE_THUMB_ADDR (pc
))
4974 error (_("Infinite loop detected"));
4978 nextpc
= arm_get_next_pc_raw (frame
, pc
);
4980 error (_("Infinite loop detected"));
4986 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
4987 of the appropriate mode (as encoded in the PC value), even if this
4988 differs from what would be expected according to the symbol tables. */
4991 arm_insert_single_step_breakpoint (struct gdbarch
*gdbarch
,
4992 struct address_space
*aspace
,
4995 struct cleanup
*old_chain
4996 = make_cleanup_restore_integer (&arm_override_mode
);
4998 arm_override_mode
= IS_THUMB_ADDR (pc
);
4999 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
5001 insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
5003 do_cleanups (old_chain
);
5006 /* Checks for an atomic sequence of instructions beginning with a LDREX{,B,H,D}
5007 instruction and ending with a STREX{,B,H,D} instruction. If such a sequence
5008 is found, attempt to step through it. A breakpoint is placed at the end of
5012 thumb_deal_with_atomic_sequence_raw (struct frame_info
*frame
)
5014 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5015 struct address_space
*aspace
= get_frame_address_space (frame
);
5016 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5017 CORE_ADDR pc
= get_frame_pc (frame
);
5018 CORE_ADDR breaks
[2] = {-1, -1};
5020 unsigned short insn1
, insn2
;
5023 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
5024 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
5025 ULONGEST status
, itstate
;
5027 /* We currently do not support atomic sequences within an IT block. */
5028 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
5029 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
5033 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. */
5034 insn1
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5036 if (thumb_insn_size (insn1
) != 4)
5039 insn2
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5041 if (!((insn1
& 0xfff0) == 0xe850
5042 || ((insn1
& 0xfff0) == 0xe8d0 && (insn2
& 0x00c0) == 0x0040)))
5045 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5047 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
5049 insn1
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5052 if (thumb_insn_size (insn1
) != 4)
5054 /* Assume that there is at most one conditional branch in the
5055 atomic sequence. If a conditional branch is found, put a
5056 breakpoint in its destination address. */
5057 if ((insn1
& 0xf000) == 0xd000 && bits (insn1
, 8, 11) != 0x0f)
5059 if (last_breakpoint
> 0)
5060 return 0; /* More than one conditional branch found,
5061 fallback to the standard code. */
5063 breaks
[1] = loc
+ 2 + (sbits (insn1
, 0, 7) << 1);
5067 /* We do not support atomic sequences that use any *other*
5068 instructions but conditional branches to change the PC.
5069 Fall back to standard code to avoid losing control of
5071 else if (thumb_instruction_changes_pc (insn1
))
5076 insn2
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5079 /* Assume that there is at most one conditional branch in the
5080 atomic sequence. If a conditional branch is found, put a
5081 breakpoint in its destination address. */
5082 if ((insn1
& 0xf800) == 0xf000
5083 && (insn2
& 0xd000) == 0x8000
5084 && (insn1
& 0x0380) != 0x0380)
5086 int sign
, j1
, j2
, imm1
, imm2
;
5087 unsigned int offset
;
5089 sign
= sbits (insn1
, 10, 10);
5090 imm1
= bits (insn1
, 0, 5);
5091 imm2
= bits (insn2
, 0, 10);
5092 j1
= bit (insn2
, 13);
5093 j2
= bit (insn2
, 11);
5095 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
5096 offset
+= (imm1
<< 12) + (imm2
<< 1);
5098 if (last_breakpoint
> 0)
5099 return 0; /* More than one conditional branch found,
5100 fallback to the standard code. */
5102 breaks
[1] = loc
+ offset
;
5106 /* We do not support atomic sequences that use any *other*
5107 instructions but conditional branches to change the PC.
5108 Fall back to standard code to avoid losing control of
5110 else if (thumb2_instruction_changes_pc (insn1
, insn2
))
5113 /* If we find a strex{,b,h,d}, we're done. */
5114 if ((insn1
& 0xfff0) == 0xe840
5115 || ((insn1
& 0xfff0) == 0xe8c0 && (insn2
& 0x00c0) == 0x0040))
5120 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5121 if (insn_count
== atomic_sequence_length
)
5124 /* Insert a breakpoint right after the end of the atomic sequence. */
5127 /* Check for duplicated breakpoints. Check also for a breakpoint
5128 placed (branch instruction's destination) anywhere in sequence. */
5130 && (breaks
[1] == breaks
[0]
5131 || (breaks
[1] >= pc
&& breaks
[1] < loc
)))
5132 last_breakpoint
= 0;
5134 /* Effectively inserts the breakpoints. */
5135 for (index
= 0; index
<= last_breakpoint
; index
++)
5136 arm_insert_single_step_breakpoint (gdbarch
, aspace
,
5137 MAKE_THUMB_ADDR (breaks
[index
]));
5143 arm_deal_with_atomic_sequence_raw (struct frame_info
*frame
)
5145 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5146 struct address_space
*aspace
= get_frame_address_space (frame
);
5147 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5148 CORE_ADDR pc
= get_frame_pc (frame
);
5149 CORE_ADDR breaks
[2] = {-1, -1};
5154 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
5155 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
5157 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction.
5158 Note that we do not currently support conditionally executed atomic
5160 insn
= read_memory_unsigned_integer (loc
, 4, byte_order_for_code
);
5162 if ((insn
& 0xff9000f0) != 0xe1900090)
5165 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5167 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
5169 insn
= read_memory_unsigned_integer (loc
, 4, byte_order_for_code
);
5172 /* Assume that there is at most one conditional branch in the atomic
5173 sequence. If a conditional branch is found, put a breakpoint in
5174 its destination address. */
5175 if (bits (insn
, 24, 27) == 0xa)
5177 if (last_breakpoint
> 0)
5178 return 0; /* More than one conditional branch found, fallback
5179 to the standard single-step code. */
5181 breaks
[1] = BranchDest (loc
- 4, insn
);
5185 /* We do not support atomic sequences that use any *other* instructions
5186 but conditional branches to change the PC. Fall back to standard
5187 code to avoid losing control of execution. */
5188 else if (arm_instruction_changes_pc (insn
))
5191 /* If we find a strex{,b,h,d}, we're done. */
5192 if ((insn
& 0xff9000f0) == 0xe1800090)
5196 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5197 if (insn_count
== atomic_sequence_length
)
5200 /* Insert a breakpoint right after the end of the atomic sequence. */
5203 /* Check for duplicated breakpoints. Check also for a breakpoint
5204 placed (branch instruction's destination) anywhere in sequence. */
5206 && (breaks
[1] == breaks
[0]
5207 || (breaks
[1] >= pc
&& breaks
[1] < loc
)))
5208 last_breakpoint
= 0;
5210 /* Effectively inserts the breakpoints. */
5211 for (index
= 0; index
<= last_breakpoint
; index
++)
5212 arm_insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
5218 arm_deal_with_atomic_sequence (struct frame_info
*frame
)
5220 if (arm_frame_is_thumb (frame
))
5221 return thumb_deal_with_atomic_sequence_raw (frame
);
5223 return arm_deal_with_atomic_sequence_raw (frame
);
5226 /* single_step() is called just before we want to resume the inferior,
5227 if we want to single-step it but there is no hardware or kernel
5228 single-step support. We find the target of the coming instruction
5229 and breakpoint it. */
5232 arm_software_single_step (struct frame_info
*frame
)
5234 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5235 struct address_space
*aspace
= get_frame_address_space (frame
);
5238 if (arm_deal_with_atomic_sequence (frame
))
5241 next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
5242 arm_insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
5247 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
5248 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
5249 NULL if an error occurs. BUF is freed. */
5252 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
5253 int old_len
, int new_len
)
5256 int bytes_to_read
= new_len
- old_len
;
5258 new_buf
= xmalloc (new_len
);
5259 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
5261 if (target_read_memory (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
5269 /* An IT block is at most the 2-byte IT instruction followed by
5270 four 4-byte instructions. The furthest back we must search to
5271 find an IT block that affects the current instruction is thus
5272 2 + 3 * 4 == 14 bytes. */
5273 #define MAX_IT_BLOCK_PREFIX 14
5275 /* Use a quick scan if there are more than this many bytes of
5277 #define IT_SCAN_THRESHOLD 32
5279 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
5280 A breakpoint in an IT block may not be hit, depending on the
5283 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
5287 CORE_ADDR boundary
, func_start
;
5289 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
5290 int i
, any
, last_it
, last_it_count
;
5292 /* If we are using BKPT breakpoints, none of this is necessary. */
5293 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
5296 /* ARM mode does not have this problem. */
5297 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
5300 /* We are setting a breakpoint in Thumb code that could potentially
5301 contain an IT block. The first step is to find how much Thumb
5302 code there is; we do not need to read outside of known Thumb
5304 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
5306 /* Thumb-2 code must have mapping symbols to have a chance. */
5309 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
5311 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
5312 && func_start
> boundary
)
5313 boundary
= func_start
;
5315 /* Search for a candidate IT instruction. We have to do some fancy
5316 footwork to distinguish a real IT instruction from the second
5317 half of a 32-bit instruction, but there is no need for that if
5318 there's no candidate. */
5319 buf_len
= min (bpaddr
- boundary
, MAX_IT_BLOCK_PREFIX
);
5321 /* No room for an IT instruction. */
5324 buf
= xmalloc (buf_len
);
5325 if (target_read_memory (bpaddr
- buf_len
, buf
, buf_len
) != 0)
5328 for (i
= 0; i
< buf_len
; i
+= 2)
5330 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5331 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
5343 /* OK, the code bytes before this instruction contain at least one
5344 halfword which resembles an IT instruction. We know that it's
5345 Thumb code, but there are still two possibilities. Either the
5346 halfword really is an IT instruction, or it is the second half of
5347 a 32-bit Thumb instruction. The only way we can tell is to
5348 scan forwards from a known instruction boundary. */
5349 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
5353 /* There's a lot of code before this instruction. Start with an
5354 optimistic search; it's easy to recognize halfwords that can
5355 not be the start of a 32-bit instruction, and use that to
5356 lock on to the instruction boundaries. */
5357 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
5360 buf_len
= IT_SCAN_THRESHOLD
;
5363 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
5365 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5366 if (thumb_insn_size (inst1
) == 2)
5373 /* At this point, if DEFINITE, BUF[I] is the first place we
5374 are sure that we know the instruction boundaries, and it is far
5375 enough from BPADDR that we could not miss an IT instruction
5376 affecting BPADDR. If ! DEFINITE, give up - start from a
5380 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
,
5384 buf_len
= bpaddr
- boundary
;
5390 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
5393 buf_len
= bpaddr
- boundary
;
5397 /* Scan forwards. Find the last IT instruction before BPADDR. */
5402 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5404 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
5409 else if (inst1
& 0x0002)
5411 else if (inst1
& 0x0004)
5416 i
+= thumb_insn_size (inst1
);
5422 /* There wasn't really an IT instruction after all. */
5425 if (last_it_count
< 1)
5426 /* It was too far away. */
5429 /* This really is a trouble spot. Move the breakpoint to the IT
5431 return bpaddr
- buf_len
+ last_it
;
5434 /* ARM displaced stepping support.
5436 Generally ARM displaced stepping works as follows:
5438 1. When an instruction is to be single-stepped, it is first decoded by
5439 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
5440 Depending on the type of instruction, it is then copied to a scratch
5441 location, possibly in a modified form. The copy_* set of functions
5442 performs such modification, as necessary. A breakpoint is placed after
5443 the modified instruction in the scratch space to return control to GDB.
5444 Note in particular that instructions which modify the PC will no longer
5445 do so after modification.
5447 2. The instruction is single-stepped, by setting the PC to the scratch
5448 location address, and resuming. Control returns to GDB when the
5451 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
5452 function used for the current instruction. This function's job is to
5453 put the CPU/memory state back to what it would have been if the
5454 instruction had been executed unmodified in its original location. */
5456 /* NOP instruction (mov r0, r0). */
5457 #define ARM_NOP 0xe1a00000
5458 #define THUMB_NOP 0x4600
5460 /* Helper for register reads for displaced stepping. In particular, this
5461 returns the PC as it would be seen by the instruction at its original
5465 displaced_read_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5469 CORE_ADDR from
= dsc
->insn_addr
;
5471 if (regno
== ARM_PC_REGNUM
)
5473 /* Compute pipeline offset:
5474 - When executing an ARM instruction, PC reads as the address of the
5475 current instruction plus 8.
5476 - When executing a Thumb instruction, PC reads as the address of the
5477 current instruction plus 4. */
5484 if (debug_displaced
)
5485 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
5486 (unsigned long) from
);
5487 return (ULONGEST
) from
;
5491 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
5492 if (debug_displaced
)
5493 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
5494 regno
, (unsigned long) ret
);
5500 displaced_in_arm_mode (struct regcache
*regs
)
5503 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
5505 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
5507 return (ps
& t_bit
) == 0;
5510 /* Write to the PC as from a branch instruction. */
5513 branch_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5517 /* Note: If bits 0/1 are set, this branch would be unpredictable for
5518 architecture versions < 6. */
5519 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
5520 val
& ~(ULONGEST
) 0x3);
5522 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
5523 val
& ~(ULONGEST
) 0x1);
5526 /* Write to the PC as from a branch-exchange instruction. */
5529 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
5532 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
5534 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
5538 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
5539 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
5541 else if ((val
& 2) == 0)
5543 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
5544 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
5548 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
5549 mode, align dest to 4 bytes). */
5550 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
5551 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
5552 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
5556 /* Write to the PC as if from a load instruction. */
5559 load_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5562 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
5563 bx_write_pc (regs
, val
);
5565 branch_write_pc (regs
, dsc
, val
);
5568 /* Write to the PC as if from an ALU instruction. */
5571 alu_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5574 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && !dsc
->is_thumb
)
5575 bx_write_pc (regs
, val
);
5577 branch_write_pc (regs
, dsc
, val
);
5580 /* Helper for writing to registers for displaced stepping. Writing to the PC
5581 has a varying effects depending on the instruction which does the write:
5582 this is controlled by the WRITE_PC argument. */
5585 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5586 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
5588 if (regno
== ARM_PC_REGNUM
)
5590 if (debug_displaced
)
5591 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
5592 (unsigned long) val
);
5595 case BRANCH_WRITE_PC
:
5596 branch_write_pc (regs
, dsc
, val
);
5600 bx_write_pc (regs
, val
);
5604 load_write_pc (regs
, dsc
, val
);
5608 alu_write_pc (regs
, dsc
, val
);
5611 case CANNOT_WRITE_PC
:
5612 warning (_("Instruction wrote to PC in an unexpected way when "
5613 "single-stepping"));
5617 internal_error (__FILE__
, __LINE__
,
5618 _("Invalid argument to displaced_write_reg"));
5621 dsc
->wrote_to_pc
= 1;
5625 if (debug_displaced
)
5626 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
5627 regno
, (unsigned long) val
);
5628 regcache_cooked_write_unsigned (regs
, regno
, val
);
5632 /* This function is used to concisely determine if an instruction INSN
5633 references PC. Register fields of interest in INSN should have the
5634 corresponding fields of BITMASK set to 0b1111. The function
5635 returns return 1 if any of these fields in INSN reference the PC
5636 (also 0b1111, r15), else it returns 0. */
5639 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
5641 uint32_t lowbit
= 1;
5643 while (bitmask
!= 0)
5647 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
5653 mask
= lowbit
* 0xf;
5655 if ((insn
& mask
) == mask
)
5664 /* The simplest copy function. Many instructions have the same effect no
5665 matter what address they are executed at: in those cases, use this. */
5668 arm_copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
5669 const char *iname
, struct displaced_step_closure
*dsc
)
5671 if (debug_displaced
)
5672 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
5673 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
5676 dsc
->modinsn
[0] = insn
;
5682 thumb_copy_unmodified_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
5683 uint16_t insn2
, const char *iname
,
5684 struct displaced_step_closure
*dsc
)
5686 if (debug_displaced
)
5687 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x %.4x, "
5688 "opcode/class '%s' unmodified\n", insn1
, insn2
,
5691 dsc
->modinsn
[0] = insn1
;
5692 dsc
->modinsn
[1] = insn2
;
5698 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
5701 thumb_copy_unmodified_16bit (struct gdbarch
*gdbarch
, unsigned int insn
,
5703 struct displaced_step_closure
*dsc
)
5705 if (debug_displaced
)
5706 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x, "
5707 "opcode/class '%s' unmodified\n", insn
,
5710 dsc
->modinsn
[0] = insn
;
5715 /* Preload instructions with immediate offset. */
5718 cleanup_preload (struct gdbarch
*gdbarch
,
5719 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5721 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5722 if (!dsc
->u
.preload
.immed
)
5723 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5727 install_preload (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5728 struct displaced_step_closure
*dsc
, unsigned int rn
)
5731 /* Preload instructions:
5733 {pli/pld} [rn, #+/-imm]
5735 {pli/pld} [r0, #+/-imm]. */
5737 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5738 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5739 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5740 dsc
->u
.preload
.immed
= 1;
5742 dsc
->cleanup
= &cleanup_preload
;
5746 arm_copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5747 struct displaced_step_closure
*dsc
)
5749 unsigned int rn
= bits (insn
, 16, 19);
5751 if (!insn_references_pc (insn
, 0x000f0000ul
))
5752 return arm_copy_unmodified (gdbarch
, insn
, "preload", dsc
);
5754 if (debug_displaced
)
5755 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
5756 (unsigned long) insn
);
5758 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
5760 install_preload (gdbarch
, regs
, dsc
, rn
);
5766 thumb2_copy_preload (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
5767 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5769 unsigned int rn
= bits (insn1
, 0, 3);
5770 unsigned int u_bit
= bit (insn1
, 7);
5771 int imm12
= bits (insn2
, 0, 11);
5774 if (rn
!= ARM_PC_REGNUM
)
5775 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "preload", dsc
);
5777 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
5778 PLD (literal) Encoding T1. */
5779 if (debug_displaced
)
5780 fprintf_unfiltered (gdb_stdlog
,
5781 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
5782 (unsigned int) dsc
->insn_addr
, u_bit
? '+' : '-',
5788 /* Rewrite instruction {pli/pld} PC imm12 into:
5789 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
5793 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
5795 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5796 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5798 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
5800 displaced_write_reg (regs
, dsc
, 0, pc_val
, CANNOT_WRITE_PC
);
5801 displaced_write_reg (regs
, dsc
, 1, imm12
, CANNOT_WRITE_PC
);
5802 dsc
->u
.preload
.immed
= 0;
5804 /* {pli/pld} [r0, r1] */
5805 dsc
->modinsn
[0] = insn1
& 0xfff0;
5806 dsc
->modinsn
[1] = 0xf001;
5809 dsc
->cleanup
= &cleanup_preload
;
5813 /* Preload instructions with register offset. */
5816 install_preload_reg(struct gdbarch
*gdbarch
, struct regcache
*regs
,
5817 struct displaced_step_closure
*dsc
, unsigned int rn
,
5820 ULONGEST rn_val
, rm_val
;
5822 /* Preload register-offset instructions:
5824 {pli/pld} [rn, rm {, shift}]
5826 {pli/pld} [r0, r1 {, shift}]. */
5828 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5829 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5830 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5831 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5832 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5833 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
5834 dsc
->u
.preload
.immed
= 0;
5836 dsc
->cleanup
= &cleanup_preload
;
5840 arm_copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5841 struct regcache
*regs
,
5842 struct displaced_step_closure
*dsc
)
5844 unsigned int rn
= bits (insn
, 16, 19);
5845 unsigned int rm
= bits (insn
, 0, 3);
5848 if (!insn_references_pc (insn
, 0x000f000ful
))
5849 return arm_copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
5851 if (debug_displaced
)
5852 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
5853 (unsigned long) insn
);
5855 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
5857 install_preload_reg (gdbarch
, regs
, dsc
, rn
, rm
);
5861 /* Copy/cleanup coprocessor load and store instructions. */
5864 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
5865 struct regcache
*regs
,
5866 struct displaced_step_closure
*dsc
)
5868 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 0);
5870 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5872 if (dsc
->u
.ldst
.writeback
)
5873 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
5877 install_copro_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5878 struct displaced_step_closure
*dsc
,
5879 int writeback
, unsigned int rn
)
5883 /* Coprocessor load/store instructions:
5885 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
5887 {stc/stc2} [r0, #+/-imm].
5889 ldc/ldc2 are handled identically. */
5891 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5892 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5893 /* PC should be 4-byte aligned. */
5894 rn_val
= rn_val
& 0xfffffffc;
5895 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5897 dsc
->u
.ldst
.writeback
= writeback
;
5898 dsc
->u
.ldst
.rn
= rn
;
5900 dsc
->cleanup
= &cleanup_copro_load_store
;
5904 arm_copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
5905 struct regcache
*regs
,
5906 struct displaced_step_closure
*dsc
)
5908 unsigned int rn
= bits (insn
, 16, 19);
5910 if (!insn_references_pc (insn
, 0x000f0000ul
))
5911 return arm_copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
5913 if (debug_displaced
)
5914 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
5915 "load/store insn %.8lx\n", (unsigned long) insn
);
5917 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
5919 install_copro_load_store (gdbarch
, regs
, dsc
, bit (insn
, 25), rn
);
5925 thumb2_copy_copro_load_store (struct gdbarch
*gdbarch
, uint16_t insn1
,
5926 uint16_t insn2
, struct regcache
*regs
,
5927 struct displaced_step_closure
*dsc
)
5929 unsigned int rn
= bits (insn1
, 0, 3);
5931 if (rn
!= ARM_PC_REGNUM
)
5932 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
5933 "copro load/store", dsc
);
5935 if (debug_displaced
)
5936 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
5937 "load/store insn %.4x%.4x\n", insn1
, insn2
);
5939 dsc
->modinsn
[0] = insn1
& 0xfff0;
5940 dsc
->modinsn
[1] = insn2
;
5943 /* This function is called for copying instruction LDC/LDC2/VLDR, which
5944 doesn't support writeback, so pass 0. */
5945 install_copro_load_store (gdbarch
, regs
, dsc
, 0, rn
);
5950 /* Clean up branch instructions (actually perform the branch, by setting
5954 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5955 struct displaced_step_closure
*dsc
)
5957 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
5958 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
5959 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
5960 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
5965 if (dsc
->u
.branch
.link
)
5967 /* The value of LR should be the next insn of current one. In order
5968 not to confuse logic hanlding later insn `bx lr', if current insn mode
5969 is Thumb, the bit 0 of LR value should be set to 1. */
5970 ULONGEST next_insn_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
5973 next_insn_addr
|= 0x1;
5975 displaced_write_reg (regs
, dsc
, ARM_LR_REGNUM
, next_insn_addr
,
5979 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, dsc
->u
.branch
.dest
, write_pc
);
5982 /* Copy B/BL/BLX instructions with immediate destinations. */
5985 install_b_bl_blx (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5986 struct displaced_step_closure
*dsc
,
5987 unsigned int cond
, int exchange
, int link
, long offset
)
5989 /* Implement "BL<cond> <label>" as:
5991 Preparation: cond <- instruction condition
5992 Insn: mov r0, r0 (nop)
5993 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
5995 B<cond> similar, but don't set r14 in cleanup. */
5997 dsc
->u
.branch
.cond
= cond
;
5998 dsc
->u
.branch
.link
= link
;
5999 dsc
->u
.branch
.exchange
= exchange
;
6001 dsc
->u
.branch
.dest
= dsc
->insn_addr
;
6002 if (link
&& exchange
)
6003 /* For BLX, offset is computed from the Align (PC, 4). */
6004 dsc
->u
.branch
.dest
= dsc
->u
.branch
.dest
& 0xfffffffc;
6007 dsc
->u
.branch
.dest
+= 4 + offset
;
6009 dsc
->u
.branch
.dest
+= 8 + offset
;
6011 dsc
->cleanup
= &cleanup_branch
;
6014 arm_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
6015 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6017 unsigned int cond
= bits (insn
, 28, 31);
6018 int exchange
= (cond
== 0xf);
6019 int link
= exchange
|| bit (insn
, 24);
6022 if (debug_displaced
)
6023 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
6024 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
6025 (unsigned long) insn
);
6027 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
6028 then arrange the switch into Thumb mode. */
6029 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
6031 offset
= bits (insn
, 0, 23) << 2;
6033 if (bit (offset
, 25))
6034 offset
= offset
| ~0x3ffffff;
6036 dsc
->modinsn
[0] = ARM_NOP
;
6038 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
6043 thumb2_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint16_t insn1
,
6044 uint16_t insn2
, struct regcache
*regs
,
6045 struct displaced_step_closure
*dsc
)
6047 int link
= bit (insn2
, 14);
6048 int exchange
= link
&& !bit (insn2
, 12);
6051 int j1
= bit (insn2
, 13);
6052 int j2
= bit (insn2
, 11);
6053 int s
= sbits (insn1
, 10, 10);
6054 int i1
= !(j1
^ bit (insn1
, 10));
6055 int i2
= !(j2
^ bit (insn1
, 10));
6057 if (!link
&& !exchange
) /* B */
6059 offset
= (bits (insn2
, 0, 10) << 1);
6060 if (bit (insn2
, 12)) /* Encoding T4 */
6062 offset
|= (bits (insn1
, 0, 9) << 12)
6068 else /* Encoding T3 */
6070 offset
|= (bits (insn1
, 0, 5) << 12)
6074 cond
= bits (insn1
, 6, 9);
6079 offset
= (bits (insn1
, 0, 9) << 12);
6080 offset
|= ((i2
<< 22) | (i1
<< 23) | (s
<< 24));
6081 offset
|= exchange
?
6082 (bits (insn2
, 1, 10) << 2) : (bits (insn2
, 0, 10) << 1);
6085 if (debug_displaced
)
6086 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s insn "
6087 "%.4x %.4x with offset %.8lx\n",
6088 link
? (exchange
) ? "blx" : "bl" : "b",
6089 insn1
, insn2
, offset
);
6091 dsc
->modinsn
[0] = THUMB_NOP
;
6093 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
6097 /* Copy B Thumb instructions. */
6099 thumb_copy_b (struct gdbarch
*gdbarch
, unsigned short insn
,
6100 struct displaced_step_closure
*dsc
)
6102 unsigned int cond
= 0;
6104 unsigned short bit_12_15
= bits (insn
, 12, 15);
6105 CORE_ADDR from
= dsc
->insn_addr
;
6107 if (bit_12_15
== 0xd)
6109 /* offset = SignExtend (imm8:0, 32) */
6110 offset
= sbits ((insn
<< 1), 0, 8);
6111 cond
= bits (insn
, 8, 11);
6113 else if (bit_12_15
== 0xe) /* Encoding T2 */
6115 offset
= sbits ((insn
<< 1), 0, 11);
6119 if (debug_displaced
)
6120 fprintf_unfiltered (gdb_stdlog
,
6121 "displaced: copying b immediate insn %.4x "
6122 "with offset %d\n", insn
, offset
);
6124 dsc
->u
.branch
.cond
= cond
;
6125 dsc
->u
.branch
.link
= 0;
6126 dsc
->u
.branch
.exchange
= 0;
6127 dsc
->u
.branch
.dest
= from
+ 4 + offset
;
6129 dsc
->modinsn
[0] = THUMB_NOP
;
6131 dsc
->cleanup
= &cleanup_branch
;
6136 /* Copy BX/BLX with register-specified destinations. */
6139 install_bx_blx_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6140 struct displaced_step_closure
*dsc
, int link
,
6141 unsigned int cond
, unsigned int rm
)
6143 /* Implement {BX,BLX}<cond> <reg>" as:
6145 Preparation: cond <- instruction condition
6146 Insn: mov r0, r0 (nop)
6147 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
6149 Don't set r14 in cleanup for BX. */
6151 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, dsc
, rm
);
6153 dsc
->u
.branch
.cond
= cond
;
6154 dsc
->u
.branch
.link
= link
;
6156 dsc
->u
.branch
.exchange
= 1;
6158 dsc
->cleanup
= &cleanup_branch
;
6162 arm_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
6163 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6165 unsigned int cond
= bits (insn
, 28, 31);
6168 int link
= bit (insn
, 5);
6169 unsigned int rm
= bits (insn
, 0, 3);
6171 if (debug_displaced
)
6172 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx",
6173 (unsigned long) insn
);
6175 dsc
->modinsn
[0] = ARM_NOP
;
6177 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, cond
, rm
);
6182 thumb_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
6183 struct regcache
*regs
,
6184 struct displaced_step_closure
*dsc
)
6186 int link
= bit (insn
, 7);
6187 unsigned int rm
= bits (insn
, 3, 6);
6189 if (debug_displaced
)
6190 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x",
6191 (unsigned short) insn
);
6193 dsc
->modinsn
[0] = THUMB_NOP
;
6195 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, INST_AL
, rm
);
6201 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
6204 cleanup_alu_imm (struct gdbarch
*gdbarch
,
6205 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6207 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
6208 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6209 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6210 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6214 arm_copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
6215 struct displaced_step_closure
*dsc
)
6217 unsigned int rn
= bits (insn
, 16, 19);
6218 unsigned int rd
= bits (insn
, 12, 15);
6219 unsigned int op
= bits (insn
, 21, 24);
6220 int is_mov
= (op
== 0xd);
6221 ULONGEST rd_val
, rn_val
;
6223 if (!insn_references_pc (insn
, 0x000ff000ul
))
6224 return arm_copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
6226 if (debug_displaced
)
6227 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
6228 "%.8lx\n", is_mov
? "move" : "ALU",
6229 (unsigned long) insn
);
6231 /* Instruction is of form:
6233 <op><cond> rd, [rn,] #imm
6237 Preparation: tmp1, tmp2 <- r0, r1;
6239 Insn: <op><cond> r0, r1, #imm
6240 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6243 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6244 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6245 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6246 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6247 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6248 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6252 dsc
->modinsn
[0] = insn
& 0xfff00fff;
6254 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
6256 dsc
->cleanup
= &cleanup_alu_imm
;
6262 thumb2_copy_alu_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
6263 uint16_t insn2
, struct regcache
*regs
,
6264 struct displaced_step_closure
*dsc
)
6266 unsigned int op
= bits (insn1
, 5, 8);
6267 unsigned int rn
, rm
, rd
;
6268 ULONGEST rd_val
, rn_val
;
6270 rn
= bits (insn1
, 0, 3); /* Rn */
6271 rm
= bits (insn2
, 0, 3); /* Rm */
6272 rd
= bits (insn2
, 8, 11); /* Rd */
6274 /* This routine is only called for instruction MOV. */
6275 gdb_assert (op
== 0x2 && rn
== 0xf);
6277 if (rm
!= ARM_PC_REGNUM
&& rd
!= ARM_PC_REGNUM
)
6278 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ALU imm", dsc
);
6280 if (debug_displaced
)
6281 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x%.4x\n",
6282 "ALU", insn1
, insn2
);
6284 /* Instruction is of form:
6286 <op><cond> rd, [rn,] #imm
6290 Preparation: tmp1, tmp2 <- r0, r1;
6292 Insn: <op><cond> r0, r1, #imm
6293 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6296 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6297 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6298 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6299 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6300 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6301 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6304 dsc
->modinsn
[0] = insn1
;
6305 dsc
->modinsn
[1] = ((insn2
& 0xf0f0) | 0x1);
6308 dsc
->cleanup
= &cleanup_alu_imm
;
6313 /* Copy/cleanup arithmetic/logic insns with register RHS. */
6316 cleanup_alu_reg (struct gdbarch
*gdbarch
,
6317 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6322 rd_val
= displaced_read_reg (regs
, dsc
, 0);
6324 for (i
= 0; i
< 3; i
++)
6325 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
6327 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6331 install_alu_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6332 struct displaced_step_closure
*dsc
,
6333 unsigned int rd
, unsigned int rn
, unsigned int rm
)
6335 ULONGEST rd_val
, rn_val
, rm_val
;
6337 /* Instruction is of form:
6339 <op><cond> rd, [rn,] rm [, <shift>]
6343 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
6344 r0, r1, r2 <- rd, rn, rm
6345 Insn: <op><cond> r0, r1, r2 [, <shift>]
6346 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
6349 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6350 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6351 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6352 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6353 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6354 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6355 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6356 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6357 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
6360 dsc
->cleanup
= &cleanup_alu_reg
;
6364 arm_copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
6365 struct displaced_step_closure
*dsc
)
6367 unsigned int op
= bits (insn
, 21, 24);
6368 int is_mov
= (op
== 0xd);
6370 if (!insn_references_pc (insn
, 0x000ff00ful
))
6371 return arm_copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
6373 if (debug_displaced
)
6374 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
6375 is_mov
? "move" : "ALU", (unsigned long) insn
);
6378 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
6380 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
6382 install_alu_reg (gdbarch
, regs
, dsc
, bits (insn
, 12, 15), bits (insn
, 16, 19),
6388 thumb_copy_alu_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
6389 struct regcache
*regs
,
6390 struct displaced_step_closure
*dsc
)
6392 unsigned rn
, rm
, rd
;
6394 rd
= bits (insn
, 3, 6);
6395 rn
= (bit (insn
, 7) << 3) | bits (insn
, 0, 2);
6398 if (rd
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
6399 return thumb_copy_unmodified_16bit (gdbarch
, insn
, "ALU reg", dsc
);
6401 if (debug_displaced
)
6402 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x\n",
6403 "ALU", (unsigned short) insn
);
6405 dsc
->modinsn
[0] = ((insn
& 0xff00) | 0x08);
6407 install_alu_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
);
6412 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
6415 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
6416 struct regcache
*regs
,
6417 struct displaced_step_closure
*dsc
)
6419 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
6422 for (i
= 0; i
< 4; i
++)
6423 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
6425 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6429 install_alu_shifted_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6430 struct displaced_step_closure
*dsc
,
6431 unsigned int rd
, unsigned int rn
, unsigned int rm
,
6435 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
6437 /* Instruction is of form:
6439 <op><cond> rd, [rn,] rm, <shift> rs
6443 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
6444 r0, r1, r2, r3 <- rd, rn, rm, rs
6445 Insn: <op><cond> r0, r1, r2, <shift> r3
6447 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
6451 for (i
= 0; i
< 4; i
++)
6452 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6454 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6455 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6456 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6457 rs_val
= displaced_read_reg (regs
, dsc
, rs
);
6458 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6459 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6460 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
6461 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
6463 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
6467 arm_copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
6468 struct regcache
*regs
,
6469 struct displaced_step_closure
*dsc
)
6471 unsigned int op
= bits (insn
, 21, 24);
6472 int is_mov
= (op
== 0xd);
6473 unsigned int rd
, rn
, rm
, rs
;
6475 if (!insn_references_pc (insn
, 0x000fff0ful
))
6476 return arm_copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
6478 if (debug_displaced
)
6479 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
6480 "%.8lx\n", is_mov
? "move" : "ALU",
6481 (unsigned long) insn
);
6483 rn
= bits (insn
, 16, 19);
6484 rm
= bits (insn
, 0, 3);
6485 rs
= bits (insn
, 8, 11);
6486 rd
= bits (insn
, 12, 15);
6489 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
6491 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
6493 install_alu_shifted_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
, rs
);
6498 /* Clean up load instructions. */
6501 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6502 struct displaced_step_closure
*dsc
)
6504 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
6506 rt_val
= displaced_read_reg (regs
, dsc
, 0);
6507 if (dsc
->u
.ldst
.xfersize
== 8)
6508 rt_val2
= displaced_read_reg (regs
, dsc
, 1);
6509 rn_val
= displaced_read_reg (regs
, dsc
, 2);
6511 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6512 if (dsc
->u
.ldst
.xfersize
> 4)
6513 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6514 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
6515 if (!dsc
->u
.ldst
.immed
)
6516 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
6518 /* Handle register writeback. */
6519 if (dsc
->u
.ldst
.writeback
)
6520 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
6521 /* Put result in right place. */
6522 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
6523 if (dsc
->u
.ldst
.xfersize
== 8)
6524 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
6527 /* Clean up store instructions. */
6530 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6531 struct displaced_step_closure
*dsc
)
6533 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 2);
6535 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6536 if (dsc
->u
.ldst
.xfersize
> 4)
6537 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6538 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
6539 if (!dsc
->u
.ldst
.immed
)
6540 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
6541 if (!dsc
->u
.ldst
.restore_r4
)
6542 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
6545 if (dsc
->u
.ldst
.writeback
)
6546 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
6549 /* Copy "extra" load/store instructions. These are halfword/doubleword
6550 transfers, which have a different encoding to byte/word transfers. */
6553 arm_copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unpriveleged
,
6554 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6556 unsigned int op1
= bits (insn
, 20, 24);
6557 unsigned int op2
= bits (insn
, 5, 6);
6558 unsigned int rt
= bits (insn
, 12, 15);
6559 unsigned int rn
= bits (insn
, 16, 19);
6560 unsigned int rm
= bits (insn
, 0, 3);
6561 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
6562 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
6563 int immed
= (op1
& 0x4) != 0;
6565 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
6567 if (!insn_references_pc (insn
, 0x000ff00ful
))
6568 return arm_copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
6570 if (debug_displaced
)
6571 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
6572 "insn %.8lx\n", unpriveleged
? "unpriveleged " : "",
6573 (unsigned long) insn
);
6575 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
6578 internal_error (__FILE__
, __LINE__
,
6579 _("copy_extra_ld_st: instruction decode error"));
6581 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6582 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6583 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6585 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6587 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
6588 if (bytesize
[opcode
] == 8)
6589 rt_val2
= displaced_read_reg (regs
, dsc
, rt
+ 1);
6590 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6592 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6594 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
6595 if (bytesize
[opcode
] == 8)
6596 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
6597 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
6599 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
6602 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
6603 dsc
->u
.ldst
.rn
= rn
;
6604 dsc
->u
.ldst
.immed
= immed
;
6605 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
6606 dsc
->u
.ldst
.restore_r4
= 0;
6609 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
6611 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
6612 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
6614 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
6616 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
6617 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
6619 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
6624 /* Copy byte/half word/word loads and stores. */
6627 install_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6628 struct displaced_step_closure
*dsc
, int load
,
6629 int immed
, int writeback
, int size
, int usermode
,
6630 int rt
, int rm
, int rn
)
6632 ULONGEST rt_val
, rn_val
, rm_val
= 0;
6634 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6635 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6637 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6639 dsc
->tmp
[4] = displaced_read_reg (regs
, dsc
, 4);
6641 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
6642 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6644 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6646 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
6647 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
6649 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
6651 dsc
->u
.ldst
.xfersize
= size
;
6652 dsc
->u
.ldst
.rn
= rn
;
6653 dsc
->u
.ldst
.immed
= immed
;
6654 dsc
->u
.ldst
.writeback
= writeback
;
6656 /* To write PC we can do:
6658 Before this sequence of instructions:
6659 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
6660 r2 is the Rn value got from dispalced_read_reg.
6662 Insn1: push {pc} Write address of STR instruction + offset on stack
6663 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
6664 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
6665 = addr(Insn1) + offset - addr(Insn3) - 8
6667 Insn4: add r4, r4, #8 r4 = offset - 8
6668 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
6670 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
6672 Otherwise we don't know what value to write for PC, since the offset is
6673 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
6674 of this can be found in Section "Saving from r15" in
6675 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
6677 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
6682 thumb2_copy_load_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
6683 uint16_t insn2
, struct regcache
*regs
,
6684 struct displaced_step_closure
*dsc
, int size
)
6686 unsigned int u_bit
= bit (insn1
, 7);
6687 unsigned int rt
= bits (insn2
, 12, 15);
6688 int imm12
= bits (insn2
, 0, 11);
6691 if (debug_displaced
)
6692 fprintf_unfiltered (gdb_stdlog
,
6693 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
6694 (unsigned int) dsc
->insn_addr
, rt
, u_bit
? '+' : '-',
6700 /* Rewrite instruction LDR Rt imm12 into:
6702 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
6706 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
6709 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6710 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6711 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6713 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
6715 pc_val
= pc_val
& 0xfffffffc;
6717 displaced_write_reg (regs
, dsc
, 2, pc_val
, CANNOT_WRITE_PC
);
6718 displaced_write_reg (regs
, dsc
, 3, imm12
, CANNOT_WRITE_PC
);
6722 dsc
->u
.ldst
.xfersize
= size
;
6723 dsc
->u
.ldst
.immed
= 0;
6724 dsc
->u
.ldst
.writeback
= 0;
6725 dsc
->u
.ldst
.restore_r4
= 0;
6727 /* LDR R0, R2, R3 */
6728 dsc
->modinsn
[0] = 0xf852;
6729 dsc
->modinsn
[1] = 0x3;
6732 dsc
->cleanup
= &cleanup_load
;
6738 thumb2_copy_load_reg_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
6739 uint16_t insn2
, struct regcache
*regs
,
6740 struct displaced_step_closure
*dsc
,
6741 int writeback
, int immed
)
6743 unsigned int rt
= bits (insn2
, 12, 15);
6744 unsigned int rn
= bits (insn1
, 0, 3);
6745 unsigned int rm
= bits (insn2
, 0, 3); /* Only valid if !immed. */
6746 /* In LDR (register), there is also a register Rm, which is not allowed to
6747 be PC, so we don't have to check it. */
6749 if (rt
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
6750 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "load",
6753 if (debug_displaced
)
6754 fprintf_unfiltered (gdb_stdlog
,
6755 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
6756 rt
, rn
, insn1
, insn2
);
6758 install_load_store (gdbarch
, regs
, dsc
, 1, immed
, writeback
, 4,
6761 dsc
->u
.ldst
.restore_r4
= 0;
6764 /* ldr[b]<cond> rt, [rn, #imm], etc.
6766 ldr[b]<cond> r0, [r2, #imm]. */
6768 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
6769 dsc
->modinsn
[1] = insn2
& 0x0fff;
6772 /* ldr[b]<cond> rt, [rn, rm], etc.
6774 ldr[b]<cond> r0, [r2, r3]. */
6776 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
6777 dsc
->modinsn
[1] = (insn2
& 0x0ff0) | 0x3;
6787 arm_copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
6788 struct regcache
*regs
,
6789 struct displaced_step_closure
*dsc
,
6790 int load
, int size
, int usermode
)
6792 int immed
= !bit (insn
, 25);
6793 int writeback
= (bit (insn
, 24) == 0 || bit (insn
, 21) != 0);
6794 unsigned int rt
= bits (insn
, 12, 15);
6795 unsigned int rn
= bits (insn
, 16, 19);
6796 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
6798 if (!insn_references_pc (insn
, 0x000ff00ful
))
6799 return arm_copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
6801 if (debug_displaced
)
6802 fprintf_unfiltered (gdb_stdlog
,
6803 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
6804 load
? (size
== 1 ? "ldrb" : "ldr")
6805 : (size
== 1 ? "strb" : "str"), usermode
? "t" : "",
6807 (unsigned long) insn
);
6809 install_load_store (gdbarch
, regs
, dsc
, load
, immed
, writeback
, size
,
6810 usermode
, rt
, rm
, rn
);
6812 if (load
|| rt
!= ARM_PC_REGNUM
)
6814 dsc
->u
.ldst
.restore_r4
= 0;
6817 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
6819 {ldr,str}[b]<cond> r0, [r2, #imm]. */
6820 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
6822 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
6824 {ldr,str}[b]<cond> r0, [r2, r3]. */
6825 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
6829 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
6830 dsc
->u
.ldst
.restore_r4
= 1;
6831 dsc
->modinsn
[0] = 0xe92d8000; /* push {pc} */
6832 dsc
->modinsn
[1] = 0xe8bd0010; /* pop {r4} */
6833 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
6834 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
6835 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
6839 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
6841 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
6846 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
6851 /* Cleanup LDM instructions with fully-populated register list. This is an
6852 unfortunate corner case: it's impossible to implement correctly by modifying
6853 the instruction. The issue is as follows: we have an instruction,
6857 which we must rewrite to avoid loading PC. A possible solution would be to
6858 do the load in two halves, something like (with suitable cleanup
6862 ldm[id][ab] r8!, {r0-r7}
6864 ldm[id][ab] r8, {r7-r14}
6867 but at present there's no suitable place for <temp>, since the scratch space
6868 is overwritten before the cleanup routine is called. For now, we simply
6869 emulate the instruction. */
6872 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6873 struct displaced_step_closure
*dsc
)
6875 int inc
= dsc
->u
.block
.increment
;
6876 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
6877 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
6878 uint32_t regmask
= dsc
->u
.block
.regmask
;
6879 int regno
= inc
? 0 : 15;
6880 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
6881 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
6882 && (regmask
& 0x8000) != 0;
6883 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6884 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
6885 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6890 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
6891 sensible we can do here. Complain loudly. */
6892 if (exception_return
)
6893 error (_("Cannot single-step exception return"));
6895 /* We don't handle any stores here for now. */
6896 gdb_assert (dsc
->u
.block
.load
!= 0);
6898 if (debug_displaced
)
6899 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
6900 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
6901 dsc
->u
.block
.increment
? "inc" : "dec",
6902 dsc
->u
.block
.before
? "before" : "after");
6909 while (regno
<= ARM_PC_REGNUM
&& (regmask
& (1 << regno
)) == 0)
6912 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
6915 xfer_addr
+= bump_before
;
6917 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
6918 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
6920 xfer_addr
+= bump_after
;
6922 regmask
&= ~(1 << regno
);
6925 if (dsc
->u
.block
.writeback
)
6926 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
6930 /* Clean up an STM which included the PC in the register list. */
6933 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6934 struct displaced_step_closure
*dsc
)
6936 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6937 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
6938 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
6939 CORE_ADDR stm_insn_addr
;
6942 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6944 /* If condition code fails, there's nothing else to do. */
6945 if (!store_executed
)
6948 if (dsc
->u
.block
.increment
)
6950 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
6952 if (dsc
->u
.block
.before
)
6957 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
6959 if (dsc
->u
.block
.before
)
6963 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
6964 stm_insn_addr
= dsc
->scratch_base
;
6965 offset
= pc_val
- stm_insn_addr
;
6967 if (debug_displaced
)
6968 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
6969 "STM instruction\n", offset
);
6971 /* Rewrite the stored PC to the proper value for the non-displaced original
6973 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
6974 dsc
->insn_addr
+ offset
);
6977 /* Clean up an LDM which includes the PC in the register list. We clumped all
6978 the registers in the transferred list into a contiguous range r0...rX (to
6979 avoid loading PC directly and losing control of the debugged program), so we
6980 must undo that here. */
6983 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
6984 struct regcache
*regs
,
6985 struct displaced_step_closure
*dsc
)
6987 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6988 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
);
6989 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= ARM_PC_REGNUM
;
6990 unsigned int regs_loaded
= bitcount (mask
);
6991 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
6993 /* The method employed here will fail if the register list is fully populated
6994 (we need to avoid loading PC directly). */
6995 gdb_assert (num_to_shuffle
< 16);
7000 clobbered
= (1 << num_to_shuffle
) - 1;
7002 while (num_to_shuffle
> 0)
7004 if ((mask
& (1 << write_reg
)) != 0)
7006 unsigned int read_reg
= num_to_shuffle
- 1;
7008 if (read_reg
!= write_reg
)
7010 ULONGEST rval
= displaced_read_reg (regs
, dsc
, read_reg
);
7011 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
7012 if (debug_displaced
)
7013 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
7014 "loaded register r%d to r%d\n"), read_reg
,
7017 else if (debug_displaced
)
7018 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
7019 "r%d already in the right place\n"),
7022 clobbered
&= ~(1 << write_reg
);
7030 /* Restore any registers we scribbled over. */
7031 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
7033 if ((clobbered
& (1 << write_reg
)) != 0)
7035 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
7037 if (debug_displaced
)
7038 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
7039 "clobbered register r%d\n"), write_reg
);
7040 clobbered
&= ~(1 << write_reg
);
7044 /* Perform register writeback manually. */
7045 if (dsc
->u
.block
.writeback
)
7047 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
7049 if (dsc
->u
.block
.increment
)
7050 new_rn_val
+= regs_loaded
* 4;
7052 new_rn_val
-= regs_loaded
* 4;
7054 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
7059 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
7060 in user-level code (in particular exception return, ldm rn, {...pc}^). */
7063 arm_copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
,
7064 struct regcache
*regs
,
7065 struct displaced_step_closure
*dsc
)
7067 int load
= bit (insn
, 20);
7068 int user
= bit (insn
, 22);
7069 int increment
= bit (insn
, 23);
7070 int before
= bit (insn
, 24);
7071 int writeback
= bit (insn
, 21);
7072 int rn
= bits (insn
, 16, 19);
7074 /* Block transfers which don't mention PC can be run directly
7076 if (rn
!= ARM_PC_REGNUM
&& (insn
& 0x8000) == 0)
7077 return arm_copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
7079 if (rn
== ARM_PC_REGNUM
)
7081 warning (_("displaced: Unpredictable LDM or STM with "
7082 "base register r15"));
7083 return arm_copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
7086 if (debug_displaced
)
7087 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
7088 "%.8lx\n", (unsigned long) insn
);
7090 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
7091 dsc
->u
.block
.rn
= rn
;
7093 dsc
->u
.block
.load
= load
;
7094 dsc
->u
.block
.user
= user
;
7095 dsc
->u
.block
.increment
= increment
;
7096 dsc
->u
.block
.before
= before
;
7097 dsc
->u
.block
.writeback
= writeback
;
7098 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
7100 dsc
->u
.block
.regmask
= insn
& 0xffff;
7104 if ((insn
& 0xffff) == 0xffff)
7106 /* LDM with a fully-populated register list. This case is
7107 particularly tricky. Implement for now by fully emulating the
7108 instruction (which might not behave perfectly in all cases, but
7109 these instructions should be rare enough for that not to matter
7111 dsc
->modinsn
[0] = ARM_NOP
;
7113 dsc
->cleanup
= &cleanup_block_load_all
;
7117 /* LDM of a list of registers which includes PC. Implement by
7118 rewriting the list of registers to be transferred into a
7119 contiguous chunk r0...rX before doing the transfer, then shuffling
7120 registers into the correct places in the cleanup routine. */
7121 unsigned int regmask
= insn
& 0xffff;
7122 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
7123 unsigned int to
= 0, from
= 0, i
, new_rn
;
7125 for (i
= 0; i
< num_in_list
; i
++)
7126 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7128 /* Writeback makes things complicated. We need to avoid clobbering
7129 the base register with one of the registers in our modified
7130 register list, but just using a different register can't work in
7133 ldm r14!, {r0-r13,pc}
7135 which would need to be rewritten as:
7139 but that can't work, because there's no free register for N.
7141 Solve this by turning off the writeback bit, and emulating
7142 writeback manually in the cleanup routine. */
7147 new_regmask
= (1 << num_in_list
) - 1;
7149 if (debug_displaced
)
7150 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
7151 "{..., pc}: original reg list %.4x, modified "
7152 "list %.4x\n"), rn
, writeback
? "!" : "",
7153 (int) insn
& 0xffff, new_regmask
);
7155 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
7157 dsc
->cleanup
= &cleanup_block_load_pc
;
7162 /* STM of a list of registers which includes PC. Run the instruction
7163 as-is, but out of line: this will store the wrong value for the PC,
7164 so we must manually fix up the memory in the cleanup routine.
7165 Doing things this way has the advantage that we can auto-detect
7166 the offset of the PC write (which is architecture-dependent) in
7167 the cleanup routine. */
7168 dsc
->modinsn
[0] = insn
;
7170 dsc
->cleanup
= &cleanup_block_store_pc
;
7177 thumb2_copy_block_xfer (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
7178 struct regcache
*regs
,
7179 struct displaced_step_closure
*dsc
)
7181 int rn
= bits (insn1
, 0, 3);
7182 int load
= bit (insn1
, 4);
7183 int writeback
= bit (insn1
, 5);
7185 /* Block transfers which don't mention PC can be run directly
7187 if (rn
!= ARM_PC_REGNUM
&& (insn2
& 0x8000) == 0)
7188 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ldm/stm", dsc
);
7190 if (rn
== ARM_PC_REGNUM
)
7192 warning (_("displaced: Unpredictable LDM or STM with "
7193 "base register r15"));
7194 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7195 "unpredictable ldm/stm", dsc
);
7198 if (debug_displaced
)
7199 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
7200 "%.4x%.4x\n", insn1
, insn2
);
7202 /* Clear bit 13, since it should be always zero. */
7203 dsc
->u
.block
.regmask
= (insn2
& 0xdfff);
7204 dsc
->u
.block
.rn
= rn
;
7206 dsc
->u
.block
.load
= load
;
7207 dsc
->u
.block
.user
= 0;
7208 dsc
->u
.block
.increment
= bit (insn1
, 7);
7209 dsc
->u
.block
.before
= bit (insn1
, 8);
7210 dsc
->u
.block
.writeback
= writeback
;
7211 dsc
->u
.block
.cond
= INST_AL
;
7212 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
7216 if (dsc
->u
.block
.regmask
== 0xffff)
7218 /* This branch is impossible to happen. */
7223 unsigned int regmask
= dsc
->u
.block
.regmask
;
7224 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
7225 unsigned int to
= 0, from
= 0, i
, new_rn
;
7227 for (i
= 0; i
< num_in_list
; i
++)
7228 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7233 new_regmask
= (1 << num_in_list
) - 1;
7235 if (debug_displaced
)
7236 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
7237 "{..., pc}: original reg list %.4x, modified "
7238 "list %.4x\n"), rn
, writeback
? "!" : "",
7239 (int) dsc
->u
.block
.regmask
, new_regmask
);
7241 dsc
->modinsn
[0] = insn1
;
7242 dsc
->modinsn
[1] = (new_regmask
& 0xffff);
7245 dsc
->cleanup
= &cleanup_block_load_pc
;
7250 dsc
->modinsn
[0] = insn1
;
7251 dsc
->modinsn
[1] = insn2
;
7253 dsc
->cleanup
= &cleanup_block_store_pc
;
7258 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
7259 for Linux, where some SVC instructions must be treated specially. */
7262 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7263 struct displaced_step_closure
*dsc
)
7265 CORE_ADDR resume_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
7267 if (debug_displaced
)
7268 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
7269 "%.8lx\n", (unsigned long) resume_addr
);
7271 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
7275 /* Common copy routine for svc instruciton. */
7278 install_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7279 struct displaced_step_closure
*dsc
)
7281 /* Preparation: none.
7282 Insn: unmodified svc.
7283 Cleanup: pc <- insn_addr + insn_size. */
7285 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
7287 dsc
->wrote_to_pc
= 1;
7289 /* Allow OS-specific code to override SVC handling. */
7290 if (dsc
->u
.svc
.copy_svc_os
)
7291 return dsc
->u
.svc
.copy_svc_os (gdbarch
, regs
, dsc
);
7294 dsc
->cleanup
= &cleanup_svc
;
7300 arm_copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
,
7301 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7304 if (debug_displaced
)
7305 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
7306 (unsigned long) insn
);
7308 dsc
->modinsn
[0] = insn
;
7310 return install_svc (gdbarch
, regs
, dsc
);
7314 thumb_copy_svc (struct gdbarch
*gdbarch
, uint16_t insn
,
7315 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7318 if (debug_displaced
)
7319 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.4x\n",
7322 dsc
->modinsn
[0] = insn
;
7324 return install_svc (gdbarch
, regs
, dsc
);
7327 /* Copy undefined instructions. */
7330 arm_copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
7331 struct displaced_step_closure
*dsc
)
7333 if (debug_displaced
)
7334 fprintf_unfiltered (gdb_stdlog
,
7335 "displaced: copying undefined insn %.8lx\n",
7336 (unsigned long) insn
);
7338 dsc
->modinsn
[0] = insn
;
7344 thumb_32bit_copy_undef (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
7345 struct displaced_step_closure
*dsc
)
7348 if (debug_displaced
)
7349 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn "
7350 "%.4x %.4x\n", (unsigned short) insn1
,
7351 (unsigned short) insn2
);
7353 dsc
->modinsn
[0] = insn1
;
7354 dsc
->modinsn
[1] = insn2
;
7360 /* Copy unpredictable instructions. */
7363 arm_copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
7364 struct displaced_step_closure
*dsc
)
7366 if (debug_displaced
)
7367 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
7368 "%.8lx\n", (unsigned long) insn
);
7370 dsc
->modinsn
[0] = insn
;
7375 /* The decode_* functions are instruction decoding helpers. They mostly follow
7376 the presentation in the ARM ARM. */
7379 arm_decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
7380 struct regcache
*regs
,
7381 struct displaced_step_closure
*dsc
)
7383 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
7384 unsigned int rn
= bits (insn
, 16, 19);
7386 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
7387 return arm_copy_unmodified (gdbarch
, insn
, "cps", dsc
);
7388 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
7389 return arm_copy_unmodified (gdbarch
, insn
, "setend", dsc
);
7390 else if ((op1
& 0x60) == 0x20)
7391 return arm_copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
7392 else if ((op1
& 0x71) == 0x40)
7393 return arm_copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store",
7395 else if ((op1
& 0x77) == 0x41)
7396 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
7397 else if ((op1
& 0x77) == 0x45)
7398 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
7399 else if ((op1
& 0x77) == 0x51)
7402 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
7404 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7406 else if ((op1
& 0x77) == 0x55)
7407 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
7408 else if (op1
== 0x57)
7411 case 0x1: return arm_copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
7412 case 0x4: return arm_copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
7413 case 0x5: return arm_copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
7414 case 0x6: return arm_copy_unmodified (gdbarch
, insn
, "isb", dsc
);
7415 default: return arm_copy_unpred (gdbarch
, insn
, dsc
);
7417 else if ((op1
& 0x63) == 0x43)
7418 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7419 else if ((op2
& 0x1) == 0x0)
7420 switch (op1
& ~0x80)
7423 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
7425 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
7426 case 0x71: case 0x75:
7428 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
7429 case 0x63: case 0x67: case 0x73: case 0x77:
7430 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7432 return arm_copy_undef (gdbarch
, insn
, dsc
);
7435 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
7439 arm_decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
7440 struct regcache
*regs
,
7441 struct displaced_step_closure
*dsc
)
7443 if (bit (insn
, 27) == 0)
7444 return arm_decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
7445 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
7446 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
7449 return arm_copy_unmodified (gdbarch
, insn
, "srs", dsc
);
7452 return arm_copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
7454 case 0x4: case 0x5: case 0x6: case 0x7:
7455 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
7458 switch ((insn
& 0xe00000) >> 21)
7460 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
7462 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7465 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
7468 return arm_copy_undef (gdbarch
, insn
, dsc
);
7473 int rn_f
= (bits (insn
, 16, 19) == 0xf);
7474 switch ((insn
& 0xe00000) >> 21)
7477 /* ldc/ldc2 imm (undefined for rn == pc). */
7478 return rn_f
? arm_copy_undef (gdbarch
, insn
, dsc
)
7479 : arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7482 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
7484 case 0x4: case 0x5: case 0x6: case 0x7:
7485 /* ldc/ldc2 lit (undefined for rn != pc). */
7486 return rn_f
? arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
7487 : arm_copy_undef (gdbarch
, insn
, dsc
);
7490 return arm_copy_undef (gdbarch
, insn
, dsc
);
7495 return arm_copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
7498 if (bits (insn
, 16, 19) == 0xf)
7500 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7502 return arm_copy_undef (gdbarch
, insn
, dsc
);
7506 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
7508 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7512 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
7514 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7517 return arm_copy_undef (gdbarch
, insn
, dsc
);
7521 /* Decode miscellaneous instructions in dp/misc encoding space. */
7524 arm_decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
7525 struct regcache
*regs
,
7526 struct displaced_step_closure
*dsc
)
7528 unsigned int op2
= bits (insn
, 4, 6);
7529 unsigned int op
= bits (insn
, 21, 22);
7530 unsigned int op1
= bits (insn
, 16, 19);
7535 return arm_copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
7538 if (op
== 0x1) /* bx. */
7539 return arm_copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
7541 return arm_copy_unmodified (gdbarch
, insn
, "clz", dsc
);
7543 return arm_copy_undef (gdbarch
, insn
, dsc
);
7547 /* Not really supported. */
7548 return arm_copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
7550 return arm_copy_undef (gdbarch
, insn
, dsc
);
7554 return arm_copy_bx_blx_reg (gdbarch
, insn
,
7555 regs
, dsc
); /* blx register. */
7557 return arm_copy_undef (gdbarch
, insn
, dsc
);
7560 return arm_copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
7564 return arm_copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
7566 /* Not really supported. */
7567 return arm_copy_unmodified (gdbarch
, insn
, "smc", dsc
);
7570 return arm_copy_undef (gdbarch
, insn
, dsc
);
7575 arm_decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
,
7576 struct regcache
*regs
,
7577 struct displaced_step_closure
*dsc
)
7580 switch (bits (insn
, 20, 24))
7583 return arm_copy_unmodified (gdbarch
, insn
, "movw", dsc
);
7586 return arm_copy_unmodified (gdbarch
, insn
, "movt", dsc
);
7588 case 0x12: case 0x16:
7589 return arm_copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
7592 return arm_copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
7596 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
7598 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
7599 return arm_copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
7600 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
7601 return arm_copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
7602 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
7603 return arm_decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
7604 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
7605 return arm_copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
7606 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
7607 return arm_copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
7608 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
7609 return arm_copy_unmodified (gdbarch
, insn
, "synch", dsc
);
7610 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
7611 /* 2nd arg means "unpriveleged". */
7612 return arm_copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
7616 /* Should be unreachable. */
7621 arm_decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
7622 struct regcache
*regs
,
7623 struct displaced_step_closure
*dsc
)
7625 int a
= bit (insn
, 25), b
= bit (insn
, 4);
7626 uint32_t op1
= bits (insn
, 20, 24);
7627 int rn_f
= bits (insn
, 16, 19) == 0xf;
7629 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
7630 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
7631 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 0);
7632 else if ((!a
&& (op1
& 0x17) == 0x02)
7633 || (a
&& (op1
& 0x17) == 0x02 && !b
))
7634 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 1);
7635 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
7636 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
7637 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 0);
7638 else if ((!a
&& (op1
& 0x17) == 0x03)
7639 || (a
&& (op1
& 0x17) == 0x03 && !b
))
7640 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 1);
7641 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
7642 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
7643 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
7644 else if ((!a
&& (op1
& 0x17) == 0x06)
7645 || (a
&& (op1
& 0x17) == 0x06 && !b
))
7646 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
7647 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
7648 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
7649 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
7650 else if ((!a
&& (op1
& 0x17) == 0x07)
7651 || (a
&& (op1
& 0x17) == 0x07 && !b
))
7652 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
7654 /* Should be unreachable. */
7659 arm_decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
7660 struct displaced_step_closure
*dsc
)
7662 switch (bits (insn
, 20, 24))
7664 case 0x00: case 0x01: case 0x02: case 0x03:
7665 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
7667 case 0x04: case 0x05: case 0x06: case 0x07:
7668 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
7670 case 0x08: case 0x09: case 0x0a: case 0x0b:
7671 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
7672 return arm_copy_unmodified (gdbarch
, insn
,
7673 "decode/pack/unpack/saturate/reverse", dsc
);
7676 if (bits (insn
, 5, 7) == 0) /* op2. */
7678 if (bits (insn
, 12, 15) == 0xf)
7679 return arm_copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
7681 return arm_copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
7684 return arm_copy_undef (gdbarch
, insn
, dsc
);
7686 case 0x1a: case 0x1b:
7687 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
7688 return arm_copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
7690 return arm_copy_undef (gdbarch
, insn
, dsc
);
7692 case 0x1c: case 0x1d:
7693 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
7695 if (bits (insn
, 0, 3) == 0xf)
7696 return arm_copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
7698 return arm_copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
7701 return arm_copy_undef (gdbarch
, insn
, dsc
);
7703 case 0x1e: case 0x1f:
7704 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
7705 return arm_copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
7707 return arm_copy_undef (gdbarch
, insn
, dsc
);
7710 /* Should be unreachable. */
7715 arm_decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, int32_t insn
,
7716 struct regcache
*regs
,
7717 struct displaced_step_closure
*dsc
)
7720 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
7722 return arm_copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
7726 arm_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
7727 struct regcache
*regs
,
7728 struct displaced_step_closure
*dsc
)
7730 unsigned int opcode
= bits (insn
, 20, 24);
7734 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
7735 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
7737 case 0x08: case 0x0a: case 0x0c: case 0x0e:
7738 case 0x12: case 0x16:
7739 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
7741 case 0x09: case 0x0b: case 0x0d: case 0x0f:
7742 case 0x13: case 0x17:
7743 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
7745 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7746 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7747 /* Note: no writeback for these instructions. Bit 25 will always be
7748 zero though (via caller), so the following works OK. */
7749 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7752 /* Should be unreachable. */
7756 /* Decode shifted register instructions. */
7759 thumb2_decode_dp_shift_reg (struct gdbarch
*gdbarch
, uint16_t insn1
,
7760 uint16_t insn2
, struct regcache
*regs
,
7761 struct displaced_step_closure
*dsc
)
7763 /* PC is only allowed to be used in instruction MOV. */
7765 unsigned int op
= bits (insn1
, 5, 8);
7766 unsigned int rn
= bits (insn1
, 0, 3);
7768 if (op
== 0x2 && rn
== 0xf) /* MOV */
7769 return thumb2_copy_alu_imm (gdbarch
, insn1
, insn2
, regs
, dsc
);
7771 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7772 "dp (shift reg)", dsc
);
7776 /* Decode extension register load/store. Exactly the same as
7777 arm_decode_ext_reg_ld_st. */
7780 thumb2_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint16_t insn1
,
7781 uint16_t insn2
, struct regcache
*regs
,
7782 struct displaced_step_closure
*dsc
)
7784 unsigned int opcode
= bits (insn1
, 4, 8);
7788 case 0x04: case 0x05:
7789 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7790 "vfp/neon vmov", dsc
);
7792 case 0x08: case 0x0c: /* 01x00 */
7793 case 0x0a: case 0x0e: /* 01x10 */
7794 case 0x12: case 0x16: /* 10x10 */
7795 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7796 "vfp/neon vstm/vpush", dsc
);
7798 case 0x09: case 0x0d: /* 01x01 */
7799 case 0x0b: case 0x0f: /* 01x11 */
7800 case 0x13: case 0x17: /* 10x11 */
7801 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7802 "vfp/neon vldm/vpop", dsc
);
7804 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7805 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7807 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7808 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
, regs
, dsc
);
7811 /* Should be unreachable. */
7816 arm_decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
7817 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7819 unsigned int op1
= bits (insn
, 20, 25);
7820 int op
= bit (insn
, 4);
7821 unsigned int coproc
= bits (insn
, 8, 11);
7822 unsigned int rn
= bits (insn
, 16, 19);
7824 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
7825 return arm_decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
7826 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
7827 && (coproc
& 0xe) != 0xa)
7829 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7830 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
7831 && (coproc
& 0xe) != 0xa)
7832 /* ldc/ldc2 imm/lit. */
7833 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7834 else if ((op1
& 0x3e) == 0x00)
7835 return arm_copy_undef (gdbarch
, insn
, dsc
);
7836 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
7837 return arm_copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
7838 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
7839 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
7840 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
7841 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
7842 else if ((op1
& 0x30) == 0x20 && !op
)
7844 if ((coproc
& 0xe) == 0xa)
7845 return arm_copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
7847 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7849 else if ((op1
& 0x30) == 0x20 && op
)
7850 return arm_copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
7851 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
7852 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
7853 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
7854 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
7855 else if ((op1
& 0x30) == 0x30)
7856 return arm_copy_svc (gdbarch
, insn
, regs
, dsc
);
7858 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
7862 thumb2_decode_svc_copro (struct gdbarch
*gdbarch
, uint16_t insn1
,
7863 uint16_t insn2
, struct regcache
*regs
,
7864 struct displaced_step_closure
*dsc
)
7866 unsigned int coproc
= bits (insn2
, 8, 11);
7867 unsigned int op1
= bits (insn1
, 4, 9);
7868 unsigned int bit_5_8
= bits (insn1
, 5, 8);
7869 unsigned int bit_9
= bit (insn1
, 9);
7870 unsigned int bit_4
= bit (insn1
, 4);
7871 unsigned int rn
= bits (insn1
, 0, 3);
7876 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7877 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
7879 else if (bit_5_8
== 0) /* UNDEFINED. */
7880 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
7883 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
7884 if ((coproc
& 0xe) == 0xa)
7885 return thumb2_decode_ext_reg_ld_st (gdbarch
, insn1
, insn2
, regs
,
7887 else /* coproc is not 101x. */
7889 if (bit_4
== 0) /* STC/STC2. */
7890 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7892 else /* LDC/LDC2 {literal, immeidate}. */
7893 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
,
7899 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "coproc", dsc
);
7905 install_pc_relative (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7906 struct displaced_step_closure
*dsc
, int rd
)
7912 Preparation: Rd <- PC
7918 int val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
7919 displaced_write_reg (regs
, dsc
, rd
, val
, CANNOT_WRITE_PC
);
7923 thumb_copy_pc_relative_16bit (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7924 struct displaced_step_closure
*dsc
,
7925 int rd
, unsigned int imm
)
7928 /* Encoding T2: ADDS Rd, #imm */
7929 dsc
->modinsn
[0] = (0x3000 | (rd
<< 8) | imm
);
7931 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
7937 thumb_decode_pc_relative_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
7938 struct regcache
*regs
,
7939 struct displaced_step_closure
*dsc
)
7941 unsigned int rd
= bits (insn
, 8, 10);
7942 unsigned int imm8
= bits (insn
, 0, 7);
7944 if (debug_displaced
)
7945 fprintf_unfiltered (gdb_stdlog
,
7946 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
7949 return thumb_copy_pc_relative_16bit (gdbarch
, regs
, dsc
, rd
, imm8
);
7953 thumb_copy_pc_relative_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
7954 uint16_t insn2
, struct regcache
*regs
,
7955 struct displaced_step_closure
*dsc
)
7957 unsigned int rd
= bits (insn2
, 8, 11);
7958 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
7959 extract raw immediate encoding rather than computing immediate. When
7960 generating ADD or SUB instruction, we can simply perform OR operation to
7961 set immediate into ADD. */
7962 unsigned int imm_3_8
= insn2
& 0x70ff;
7963 unsigned int imm_i
= insn1
& 0x0400; /* Clear all bits except bit 10. */
7965 if (debug_displaced
)
7966 fprintf_unfiltered (gdb_stdlog
,
7967 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
7968 rd
, imm_i
, imm_3_8
, insn1
, insn2
);
7970 if (bit (insn1
, 7)) /* Encoding T2 */
7972 /* Encoding T3: SUB Rd, Rd, #imm */
7973 dsc
->modinsn
[0] = (0xf1a0 | rd
| imm_i
);
7974 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7976 else /* Encoding T3 */
7978 /* Encoding T3: ADD Rd, Rd, #imm */
7979 dsc
->modinsn
[0] = (0xf100 | rd
| imm_i
);
7980 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
7984 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
7990 thumb_copy_16bit_ldr_literal (struct gdbarch
*gdbarch
, unsigned short insn1
,
7991 struct regcache
*regs
,
7992 struct displaced_step_closure
*dsc
)
7994 unsigned int rt
= bits (insn1
, 8, 10);
7996 int imm8
= (bits (insn1
, 0, 7) << 2);
7997 CORE_ADDR from
= dsc
->insn_addr
;
8003 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
8005 Insn: LDR R0, [R2, R3];
8006 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
8008 if (debug_displaced
)
8009 fprintf_unfiltered (gdb_stdlog
,
8010 "displaced: copying thumb ldr r%d [pc #%d]\n"
8013 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
8014 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
8015 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
8016 pc
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
8017 /* The assembler calculates the required value of the offset from the
8018 Align(PC,4) value of this instruction to the label. */
8019 pc
= pc
& 0xfffffffc;
8021 displaced_write_reg (regs
, dsc
, 2, pc
, CANNOT_WRITE_PC
);
8022 displaced_write_reg (regs
, dsc
, 3, imm8
, CANNOT_WRITE_PC
);
8025 dsc
->u
.ldst
.xfersize
= 4;
8027 dsc
->u
.ldst
.immed
= 0;
8028 dsc
->u
.ldst
.writeback
= 0;
8029 dsc
->u
.ldst
.restore_r4
= 0;
8031 dsc
->modinsn
[0] = 0x58d0; /* ldr r0, [r2, r3]*/
8033 dsc
->cleanup
= &cleanup_load
;
8038 /* Copy Thumb cbnz/cbz insruction. */
8041 thumb_copy_cbnz_cbz (struct gdbarch
*gdbarch
, uint16_t insn1
,
8042 struct regcache
*regs
,
8043 struct displaced_step_closure
*dsc
)
8045 int non_zero
= bit (insn1
, 11);
8046 unsigned int imm5
= (bit (insn1
, 9) << 6) | (bits (insn1
, 3, 7) << 1);
8047 CORE_ADDR from
= dsc
->insn_addr
;
8048 int rn
= bits (insn1
, 0, 2);
8049 int rn_val
= displaced_read_reg (regs
, dsc
, rn
);
8051 dsc
->u
.branch
.cond
= (rn_val
&& non_zero
) || (!rn_val
&& !non_zero
);
8052 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
8053 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
8054 condition is false, let it be, cleanup_branch will do nothing. */
8055 if (dsc
->u
.branch
.cond
)
8057 dsc
->u
.branch
.cond
= INST_AL
;
8058 dsc
->u
.branch
.dest
= from
+ 4 + imm5
;
8061 dsc
->u
.branch
.dest
= from
+ 2;
8063 dsc
->u
.branch
.link
= 0;
8064 dsc
->u
.branch
.exchange
= 0;
8066 if (debug_displaced
)
8067 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s [r%d = 0x%x]"
8068 " insn %.4x to %.8lx\n", non_zero
? "cbnz" : "cbz",
8069 rn
, rn_val
, insn1
, dsc
->u
.branch
.dest
);
8071 dsc
->modinsn
[0] = THUMB_NOP
;
8073 dsc
->cleanup
= &cleanup_branch
;
8077 /* Copy Table Branch Byte/Halfword */
8079 thumb2_copy_table_branch (struct gdbarch
*gdbarch
, uint16_t insn1
,
8080 uint16_t insn2
, struct regcache
*regs
,
8081 struct displaced_step_closure
*dsc
)
8083 ULONGEST rn_val
, rm_val
;
8084 int is_tbh
= bit (insn2
, 4);
8085 CORE_ADDR halfwords
= 0;
8086 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8088 rn_val
= displaced_read_reg (regs
, dsc
, bits (insn1
, 0, 3));
8089 rm_val
= displaced_read_reg (regs
, dsc
, bits (insn2
, 0, 3));
8095 target_read_memory (rn_val
+ 2 * rm_val
, buf
, 2);
8096 halfwords
= extract_unsigned_integer (buf
, 2, byte_order
);
8102 target_read_memory (rn_val
+ rm_val
, buf
, 1);
8103 halfwords
= extract_unsigned_integer (buf
, 1, byte_order
);
8106 if (debug_displaced
)
8107 fprintf_unfiltered (gdb_stdlog
, "displaced: %s base 0x%x offset 0x%x"
8108 " offset 0x%x\n", is_tbh
? "tbh" : "tbb",
8109 (unsigned int) rn_val
, (unsigned int) rm_val
,
8110 (unsigned int) halfwords
);
8112 dsc
->u
.branch
.cond
= INST_AL
;
8113 dsc
->u
.branch
.link
= 0;
8114 dsc
->u
.branch
.exchange
= 0;
8115 dsc
->u
.branch
.dest
= dsc
->insn_addr
+ 4 + 2 * halfwords
;
8117 dsc
->cleanup
= &cleanup_branch
;
8123 cleanup_pop_pc_16bit_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
8124 struct displaced_step_closure
*dsc
)
8127 int val
= displaced_read_reg (regs
, dsc
, 7);
8128 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, val
, BX_WRITE_PC
);
8131 val
= displaced_read_reg (regs
, dsc
, 8);
8132 displaced_write_reg (regs
, dsc
, 7, val
, CANNOT_WRITE_PC
);
8135 displaced_write_reg (regs
, dsc
, 8, dsc
->tmp
[0], CANNOT_WRITE_PC
);
8140 thumb_copy_pop_pc_16bit (struct gdbarch
*gdbarch
, unsigned short insn1
,
8141 struct regcache
*regs
,
8142 struct displaced_step_closure
*dsc
)
8144 dsc
->u
.block
.regmask
= insn1
& 0x00ff;
8146 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
8149 (1) register list is full, that is, r0-r7 are used.
8150 Prepare: tmp[0] <- r8
8152 POP {r0, r1, ...., r6, r7}; remove PC from reglist
8153 MOV r8, r7; Move value of r7 to r8;
8154 POP {r7}; Store PC value into r7.
8156 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
8158 (2) register list is not full, supposing there are N registers in
8159 register list (except PC, 0 <= N <= 7).
8160 Prepare: for each i, 0 - N, tmp[i] <- ri.
8162 POP {r0, r1, ...., rN};
8164 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
8165 from tmp[] properly.
8167 if (debug_displaced
)
8168 fprintf_unfiltered (gdb_stdlog
,
8169 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
8170 dsc
->u
.block
.regmask
, insn1
);
8172 if (dsc
->u
.block
.regmask
== 0xff)
8174 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 8);
8176 dsc
->modinsn
[0] = (insn1
& 0xfeff); /* POP {r0,r1,...,r6, r7} */
8177 dsc
->modinsn
[1] = 0x46b8; /* MOV r8, r7 */
8178 dsc
->modinsn
[2] = 0xbc80; /* POP {r7} */
8181 dsc
->cleanup
= &cleanup_pop_pc_16bit_all
;
8185 unsigned int num_in_list
= bitcount (dsc
->u
.block
.regmask
);
8186 unsigned int new_regmask
, bit
= 1;
8187 unsigned int to
= 0, from
= 0, i
, new_rn
;
8189 for (i
= 0; i
< num_in_list
+ 1; i
++)
8190 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
8192 new_regmask
= (1 << (num_in_list
+ 1)) - 1;
8194 if (debug_displaced
)
8195 fprintf_unfiltered (gdb_stdlog
, _("displaced: POP "
8196 "{..., pc}: original reg list %.4x,"
8197 " modified list %.4x\n"),
8198 (int) dsc
->u
.block
.regmask
, new_regmask
);
8200 dsc
->u
.block
.regmask
|= 0x8000;
8201 dsc
->u
.block
.writeback
= 0;
8202 dsc
->u
.block
.cond
= INST_AL
;
8204 dsc
->modinsn
[0] = (insn1
& ~0x1ff) | (new_regmask
& 0xff);
8206 dsc
->cleanup
= &cleanup_block_load_pc
;
8213 thumb_process_displaced_16bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
8214 struct regcache
*regs
,
8215 struct displaced_step_closure
*dsc
)
8217 unsigned short op_bit_12_15
= bits (insn1
, 12, 15);
8218 unsigned short op_bit_10_11
= bits (insn1
, 10, 11);
8221 /* 16-bit thumb instructions. */
8222 switch (op_bit_12_15
)
8224 /* Shift (imme), add, subtract, move and compare. */
8225 case 0: case 1: case 2: case 3:
8226 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
8227 "shift/add/sub/mov/cmp",
8231 switch (op_bit_10_11
)
8233 case 0: /* Data-processing */
8234 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
8238 case 1: /* Special data instructions and branch and exchange. */
8240 unsigned short op
= bits (insn1
, 7, 9);
8241 if (op
== 6 || op
== 7) /* BX or BLX */
8242 err
= thumb_copy_bx_blx_reg (gdbarch
, insn1
, regs
, dsc
);
8243 else if (bits (insn1
, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
8244 err
= thumb_copy_alu_reg (gdbarch
, insn1
, regs
, dsc
);
8246 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "special data",
8250 default: /* LDR (literal) */
8251 err
= thumb_copy_16bit_ldr_literal (gdbarch
, insn1
, regs
, dsc
);
8254 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
8255 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldr/str", dsc
);
8258 if (op_bit_10_11
< 2) /* Generate PC-relative address */
8259 err
= thumb_decode_pc_relative_16bit (gdbarch
, insn1
, regs
, dsc
);
8260 else /* Generate SP-relative address */
8261 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "sp-relative", dsc
);
8263 case 11: /* Misc 16-bit instructions */
8265 switch (bits (insn1
, 8, 11))
8267 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
8268 err
= thumb_copy_cbnz_cbz (gdbarch
, insn1
, regs
, dsc
);
8270 case 12: case 13: /* POP */
8271 if (bit (insn1
, 8)) /* PC is in register list. */
8272 err
= thumb_copy_pop_pc_16bit (gdbarch
, insn1
, regs
, dsc
);
8274 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "pop", dsc
);
8276 case 15: /* If-Then, and hints */
8277 if (bits (insn1
, 0, 3))
8278 /* If-Then makes up to four following instructions conditional.
8279 IT instruction itself is not conditional, so handle it as a
8280 common unmodified instruction. */
8281 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "If-Then",
8284 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "hints", dsc
);
8287 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "misc", dsc
);
8292 if (op_bit_10_11
< 2) /* Store multiple registers */
8293 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "stm", dsc
);
8294 else /* Load multiple registers */
8295 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldm", dsc
);
8297 case 13: /* Conditional branch and supervisor call */
8298 if (bits (insn1
, 9, 11) != 7) /* conditional branch */
8299 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
8301 err
= thumb_copy_svc (gdbarch
, insn1
, regs
, dsc
);
8303 case 14: /* Unconditional branch */
8304 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
8311 internal_error (__FILE__
, __LINE__
,
8312 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
8316 decode_thumb_32bit_ld_mem_hints (struct gdbarch
*gdbarch
,
8317 uint16_t insn1
, uint16_t insn2
,
8318 struct regcache
*regs
,
8319 struct displaced_step_closure
*dsc
)
8321 int rt
= bits (insn2
, 12, 15);
8322 int rn
= bits (insn1
, 0, 3);
8323 int op1
= bits (insn1
, 7, 8);
8326 switch (bits (insn1
, 5, 6))
8328 case 0: /* Load byte and memory hints */
8329 if (rt
== 0xf) /* PLD/PLI */
8332 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
8333 return thumb2_copy_preload (gdbarch
, insn1
, insn2
, regs
, dsc
);
8335 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8340 if (rn
== 0xf) /* LDRB/LDRSB (literal) */
8341 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
8344 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8345 "ldrb{reg, immediate}/ldrbt",
8350 case 1: /* Load halfword and memory hints. */
8351 if (rt
== 0xf) /* PLD{W} and Unalloc memory hint. */
8352 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8353 "pld/unalloc memhint", dsc
);
8357 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
8360 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8364 case 2: /* Load word */
8366 int insn2_bit_8_11
= bits (insn2
, 8, 11);
8369 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
, 4);
8370 else if (op1
== 0x1) /* Encoding T3 */
8371 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
, dsc
,
8373 else /* op1 == 0x0 */
8375 if (insn2_bit_8_11
== 0xc || (insn2_bit_8_11
& 0x9) == 0x9)
8376 /* LDR (immediate) */
8377 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
8378 dsc
, bit (insn2
, 8), 1);
8379 else if (insn2_bit_8_11
== 0xe) /* LDRT */
8380 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8383 /* LDR (register) */
8384 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
8390 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
8397 thumb_process_displaced_32bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
8398 uint16_t insn2
, struct regcache
*regs
,
8399 struct displaced_step_closure
*dsc
)
8402 unsigned short op
= bit (insn2
, 15);
8403 unsigned int op1
= bits (insn1
, 11, 12);
8409 switch (bits (insn1
, 9, 10))
8414 /* Load/store {dual, execlusive}, table branch. */
8415 if (bits (insn1
, 7, 8) == 1 && bits (insn1
, 4, 5) == 1
8416 && bits (insn2
, 5, 7) == 0)
8417 err
= thumb2_copy_table_branch (gdbarch
, insn1
, insn2
, regs
,
8420 /* PC is not allowed to use in load/store {dual, exclusive}
8422 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8423 "load/store dual/ex", dsc
);
8425 else /* load/store multiple */
8427 switch (bits (insn1
, 7, 8))
8429 case 0: case 3: /* SRS, RFE */
8430 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8433 case 1: case 2: /* LDM/STM/PUSH/POP */
8434 err
= thumb2_copy_block_xfer (gdbarch
, insn1
, insn2
, regs
, dsc
);
8441 /* Data-processing (shift register). */
8442 err
= thumb2_decode_dp_shift_reg (gdbarch
, insn1
, insn2
, regs
,
8445 default: /* Coprocessor instructions. */
8446 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
8451 case 2: /* op1 = 2 */
8452 if (op
) /* Branch and misc control. */
8454 if (bit (insn2
, 14) /* BLX/BL */
8455 || bit (insn2
, 12) /* Unconditional branch */
8456 || (bits (insn1
, 7, 9) != 0x7)) /* Conditional branch */
8457 err
= thumb2_copy_b_bl_blx (gdbarch
, insn1
, insn2
, regs
, dsc
);
8459 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8464 if (bit (insn1
, 9)) /* Data processing (plain binary imm). */
8466 int op
= bits (insn1
, 4, 8);
8467 int rn
= bits (insn1
, 0, 3);
8468 if ((op
== 0 || op
== 0xa) && rn
== 0xf)
8469 err
= thumb_copy_pc_relative_32bit (gdbarch
, insn1
, insn2
,
8472 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8475 else /* Data processing (modified immeidate) */
8476 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8480 case 3: /* op1 = 3 */
8481 switch (bits (insn1
, 9, 10))
8485 err
= decode_thumb_32bit_ld_mem_hints (gdbarch
, insn1
, insn2
,
8487 else /* NEON Load/Store and Store single data item */
8488 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8489 "neon elt/struct load/store",
8492 case 1: /* op1 = 3, bits (9, 10) == 1 */
8493 switch (bits (insn1
, 7, 8))
8495 case 0: case 1: /* Data processing (register) */
8496 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8499 case 2: /* Multiply and absolute difference */
8500 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8501 "mul/mua/diff", dsc
);
8503 case 3: /* Long multiply and divide */
8504 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8509 default: /* Coprocessor instructions */
8510 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
8519 internal_error (__FILE__
, __LINE__
,
8520 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
8525 thumb_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8526 CORE_ADDR to
, struct regcache
*regs
,
8527 struct displaced_step_closure
*dsc
)
8529 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8531 = read_memory_unsigned_integer (from
, 2, byte_order_for_code
);
8533 if (debug_displaced
)
8534 fprintf_unfiltered (gdb_stdlog
, "displaced: process thumb insn %.4x "
8535 "at %.8lx\n", insn1
, (unsigned long) from
);
8538 dsc
->insn_size
= thumb_insn_size (insn1
);
8539 if (thumb_insn_size (insn1
) == 4)
8542 = read_memory_unsigned_integer (from
+ 2, 2, byte_order_for_code
);
8543 thumb_process_displaced_32bit_insn (gdbarch
, insn1
, insn2
, regs
, dsc
);
8546 thumb_process_displaced_16bit_insn (gdbarch
, insn1
, regs
, dsc
);
8550 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8551 CORE_ADDR to
, struct regcache
*regs
,
8552 struct displaced_step_closure
*dsc
)
8555 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8558 /* Most displaced instructions use a 1-instruction scratch space, so set this
8559 here and override below if/when necessary. */
8561 dsc
->insn_addr
= from
;
8562 dsc
->scratch_base
= to
;
8563 dsc
->cleanup
= NULL
;
8564 dsc
->wrote_to_pc
= 0;
8566 if (!displaced_in_arm_mode (regs
))
8567 return thumb_process_displaced_insn (gdbarch
, from
, to
, regs
, dsc
);
8571 insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
8572 if (debug_displaced
)
8573 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
8574 "at %.8lx\n", (unsigned long) insn
,
8575 (unsigned long) from
);
8577 if ((insn
& 0xf0000000) == 0xf0000000)
8578 err
= arm_decode_unconditional (gdbarch
, insn
, regs
, dsc
);
8579 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
8581 case 0x0: case 0x1: case 0x2: case 0x3:
8582 err
= arm_decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
8585 case 0x4: case 0x5: case 0x6:
8586 err
= arm_decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
8590 err
= arm_decode_media (gdbarch
, insn
, dsc
);
8593 case 0x8: case 0x9: case 0xa: case 0xb:
8594 err
= arm_decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
8597 case 0xc: case 0xd: case 0xe: case 0xf:
8598 err
= arm_decode_svc_copro (gdbarch
, insn
, to
, regs
, dsc
);
8603 internal_error (__FILE__
, __LINE__
,
8604 _("arm_process_displaced_insn: Instruction decode error"));
8607 /* Actually set up the scratch space for a displaced instruction. */
8610 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8611 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
8613 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8614 unsigned int i
, len
, offset
;
8615 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8616 int size
= dsc
->is_thumb
? 2 : 4;
8617 const unsigned char *bkp_insn
;
8620 /* Poke modified instruction(s). */
8621 for (i
= 0; i
< dsc
->numinsns
; i
++)
8623 if (debug_displaced
)
8625 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn ");
8627 fprintf_unfiltered (gdb_stdlog
, "%.8lx",
8630 fprintf_unfiltered (gdb_stdlog
, "%.4x",
8631 (unsigned short)dsc
->modinsn
[i
]);
8633 fprintf_unfiltered (gdb_stdlog
, " at %.8lx\n",
8634 (unsigned long) to
+ offset
);
8637 write_memory_unsigned_integer (to
+ offset
, size
,
8638 byte_order_for_code
,
8643 /* Choose the correct breakpoint instruction. */
8646 bkp_insn
= tdep
->thumb_breakpoint
;
8647 len
= tdep
->thumb_breakpoint_size
;
8651 bkp_insn
= tdep
->arm_breakpoint
;
8652 len
= tdep
->arm_breakpoint_size
;
8655 /* Put breakpoint afterwards. */
8656 write_memory (to
+ offset
, bkp_insn
, len
);
8658 if (debug_displaced
)
8659 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
8660 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
8663 /* Entry point for copying an instruction into scratch space for displaced
8666 struct displaced_step_closure
*
8667 arm_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
8668 CORE_ADDR from
, CORE_ADDR to
,
8669 struct regcache
*regs
)
8671 struct displaced_step_closure
*dsc
8672 = xmalloc (sizeof (struct displaced_step_closure
));
8673 arm_process_displaced_insn (gdbarch
, from
, to
, regs
, dsc
);
8674 arm_displaced_init_closure (gdbarch
, from
, to
, dsc
);
8679 /* Entry point for cleaning things up after a displaced instruction has been
8683 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
8684 struct displaced_step_closure
*dsc
,
8685 CORE_ADDR from
, CORE_ADDR to
,
8686 struct regcache
*regs
)
8689 dsc
->cleanup (gdbarch
, regs
, dsc
);
8691 if (!dsc
->wrote_to_pc
)
8692 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
8693 dsc
->insn_addr
+ dsc
->insn_size
);
8697 #include "bfd-in2.h"
8698 #include "libcoff.h"
8701 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
8703 struct gdbarch
*gdbarch
= info
->application_data
;
8705 if (arm_pc_is_thumb (gdbarch
, memaddr
))
8707 static asymbol
*asym
;
8708 static combined_entry_type ce
;
8709 static struct coff_symbol_struct csym
;
8710 static struct bfd fake_bfd
;
8711 static bfd_target fake_target
;
8713 if (csym
.native
== NULL
)
8715 /* Create a fake symbol vector containing a Thumb symbol.
8716 This is solely so that the code in print_insn_little_arm()
8717 and print_insn_big_arm() in opcodes/arm-dis.c will detect
8718 the presence of a Thumb symbol and switch to decoding
8719 Thumb instructions. */
8721 fake_target
.flavour
= bfd_target_coff_flavour
;
8722 fake_bfd
.xvec
= &fake_target
;
8723 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
8725 csym
.symbol
.the_bfd
= &fake_bfd
;
8726 csym
.symbol
.name
= "fake";
8727 asym
= (asymbol
*) & csym
;
8730 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
8731 info
->symbols
= &asym
;
8734 info
->symbols
= NULL
;
8736 if (info
->endian
== BFD_ENDIAN_BIG
)
8737 return print_insn_big_arm (memaddr
, info
);
8739 return print_insn_little_arm (memaddr
, info
);
8742 /* The following define instruction sequences that will cause ARM
8743 cpu's to take an undefined instruction trap. These are used to
8744 signal a breakpoint to GDB.
8746 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
8747 modes. A different instruction is required for each mode. The ARM
8748 cpu's can also be big or little endian. Thus four different
8749 instructions are needed to support all cases.
8751 Note: ARMv4 defines several new instructions that will take the
8752 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
8753 not in fact add the new instructions. The new undefined
8754 instructions in ARMv4 are all instructions that had no defined
8755 behaviour in earlier chips. There is no guarantee that they will
8756 raise an exception, but may be treated as NOP's. In practice, it
8757 may only safe to rely on instructions matching:
8759 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
8760 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
8761 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
8763 Even this may only true if the condition predicate is true. The
8764 following use a condition predicate of ALWAYS so it is always TRUE.
8766 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
8767 and NetBSD all use a software interrupt rather than an undefined
8768 instruction to force a trap. This can be handled by by the
8769 abi-specific code during establishment of the gdbarch vector. */
8771 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
8772 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
8773 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
8774 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
8776 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
8777 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
8778 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
8779 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
8781 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
8782 the program counter value to determine whether a 16-bit or 32-bit
8783 breakpoint should be used. It returns a pointer to a string of
8784 bytes that encode a breakpoint instruction, stores the length of
8785 the string to *lenptr, and adjusts the program counter (if
8786 necessary) to point to the actual memory location where the
8787 breakpoint should be inserted. */
8789 static const unsigned char *
8790 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
8792 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8793 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8795 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
8797 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
8799 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
8800 check whether we are replacing a 32-bit instruction. */
8801 if (tdep
->thumb2_breakpoint
!= NULL
)
8804 if (target_read_memory (*pcptr
, buf
, 2) == 0)
8806 unsigned short inst1
;
8807 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
8808 if (thumb_insn_size (inst1
) == 4)
8810 *lenptr
= tdep
->thumb2_breakpoint_size
;
8811 return tdep
->thumb2_breakpoint
;
8816 *lenptr
= tdep
->thumb_breakpoint_size
;
8817 return tdep
->thumb_breakpoint
;
8821 *lenptr
= tdep
->arm_breakpoint_size
;
8822 return tdep
->arm_breakpoint
;
8827 arm_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
8830 arm_breakpoint_from_pc (gdbarch
, pcptr
, kindptr
);
8832 if (arm_pc_is_thumb (gdbarch
, *pcptr
) && *kindptr
== 4)
8833 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
8834 that this is not confused with a 32-bit ARM breakpoint. */
8838 /* Extract from an array REGBUF containing the (raw) register state a
8839 function return value of type TYPE, and copy that, in virtual
8840 format, into VALBUF. */
8843 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
8846 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
8847 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8849 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
8851 switch (gdbarch_tdep (gdbarch
)->fp_model
)
8855 /* The value is in register F0 in internal format. We need to
8856 extract the raw value and then convert it to the desired
8858 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
8860 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
8861 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
8862 valbuf
, gdbarch_byte_order (gdbarch
));
8866 case ARM_FLOAT_SOFT_FPA
:
8867 case ARM_FLOAT_SOFT_VFP
:
8868 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8869 not using the VFP ABI code. */
8871 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
8872 if (TYPE_LENGTH (type
) > 4)
8873 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
8874 valbuf
+ INT_REGISTER_SIZE
);
8878 internal_error (__FILE__
, __LINE__
,
8879 _("arm_extract_return_value: "
8880 "Floating point model not supported"));
8884 else if (TYPE_CODE (type
) == TYPE_CODE_INT
8885 || TYPE_CODE (type
) == TYPE_CODE_CHAR
8886 || TYPE_CODE (type
) == TYPE_CODE_BOOL
8887 || TYPE_CODE (type
) == TYPE_CODE_PTR
8888 || TYPE_CODE (type
) == TYPE_CODE_REF
8889 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
8891 /* If the type is a plain integer, then the access is
8892 straight-forward. Otherwise we have to play around a bit
8894 int len
= TYPE_LENGTH (type
);
8895 int regno
= ARM_A1_REGNUM
;
8900 /* By using store_unsigned_integer we avoid having to do
8901 anything special for small big-endian values. */
8902 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
8903 store_unsigned_integer (valbuf
,
8904 (len
> INT_REGISTER_SIZE
8905 ? INT_REGISTER_SIZE
: len
),
8907 len
-= INT_REGISTER_SIZE
;
8908 valbuf
+= INT_REGISTER_SIZE
;
8913 /* For a structure or union the behaviour is as if the value had
8914 been stored to word-aligned memory and then loaded into
8915 registers with 32-bit load instruction(s). */
8916 int len
= TYPE_LENGTH (type
);
8917 int regno
= ARM_A1_REGNUM
;
8918 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8922 regcache_cooked_read (regs
, regno
++, tmpbuf
);
8923 memcpy (valbuf
, tmpbuf
,
8924 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
8925 len
-= INT_REGISTER_SIZE
;
8926 valbuf
+= INT_REGISTER_SIZE
;
8932 /* Will a function return an aggregate type in memory or in a
8933 register? Return 0 if an aggregate type can be returned in a
8934 register, 1 if it must be returned in memory. */
8937 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
8940 enum type_code code
;
8942 CHECK_TYPEDEF (type
);
8944 /* In the ARM ABI, "integer" like aggregate types are returned in
8945 registers. For an aggregate type to be integer like, its size
8946 must be less than or equal to INT_REGISTER_SIZE and the
8947 offset of each addressable subfield must be zero. Note that bit
8948 fields are not addressable, and all addressable subfields of
8949 unions always start at offset zero.
8951 This function is based on the behaviour of GCC 2.95.1.
8952 See: gcc/arm.c: arm_return_in_memory() for details.
8954 Note: All versions of GCC before GCC 2.95.2 do not set up the
8955 parameters correctly for a function returning the following
8956 structure: struct { float f;}; This should be returned in memory,
8957 not a register. Richard Earnshaw sent me a patch, but I do not
8958 know of any way to detect if a function like the above has been
8959 compiled with the correct calling convention. */
8961 /* All aggregate types that won't fit in a register must be returned
8963 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
8968 /* The AAPCS says all aggregates not larger than a word are returned
8970 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
8973 /* The only aggregate types that can be returned in a register are
8974 structs and unions. Arrays must be returned in memory. */
8975 code
= TYPE_CODE (type
);
8976 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
8981 /* Assume all other aggregate types can be returned in a register.
8982 Run a check for structures, unions and arrays. */
8985 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
8988 /* Need to check if this struct/union is "integer" like. For
8989 this to be true, its size must be less than or equal to
8990 INT_REGISTER_SIZE and the offset of each addressable
8991 subfield must be zero. Note that bit fields are not
8992 addressable, and unions always start at offset zero. If any
8993 of the subfields is a floating point type, the struct/union
8994 cannot be an integer type. */
8996 /* For each field in the object, check:
8997 1) Is it FP? --> yes, nRc = 1;
8998 2) Is it addressable (bitpos != 0) and
8999 not packed (bitsize == 0)?
9003 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
9005 enum type_code field_type_code
;
9006 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
,
9009 /* Is it a floating point type field? */
9010 if (field_type_code
== TYPE_CODE_FLT
)
9016 /* If bitpos != 0, then we have to care about it. */
9017 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
9019 /* Bitfields are not addressable. If the field bitsize is
9020 zero, then the field is not packed. Hence it cannot be
9021 a bitfield or any other packed type. */
9022 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
9034 /* Write into appropriate registers a function return value of type
9035 TYPE, given in virtual format. */
9038 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
9039 const gdb_byte
*valbuf
)
9041 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
9042 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
9044 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
9046 char buf
[MAX_REGISTER_SIZE
];
9048 switch (gdbarch_tdep (gdbarch
)->fp_model
)
9052 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
9053 gdbarch_byte_order (gdbarch
));
9054 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
9057 case ARM_FLOAT_SOFT_FPA
:
9058 case ARM_FLOAT_SOFT_VFP
:
9059 /* ARM_FLOAT_VFP can arise if this is a variadic function so
9060 not using the VFP ABI code. */
9062 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
9063 if (TYPE_LENGTH (type
) > 4)
9064 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
9065 valbuf
+ INT_REGISTER_SIZE
);
9069 internal_error (__FILE__
, __LINE__
,
9070 _("arm_store_return_value: Floating "
9071 "point model not supported"));
9075 else if (TYPE_CODE (type
) == TYPE_CODE_INT
9076 || TYPE_CODE (type
) == TYPE_CODE_CHAR
9077 || TYPE_CODE (type
) == TYPE_CODE_BOOL
9078 || TYPE_CODE (type
) == TYPE_CODE_PTR
9079 || TYPE_CODE (type
) == TYPE_CODE_REF
9080 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
9082 if (TYPE_LENGTH (type
) <= 4)
9084 /* Values of one word or less are zero/sign-extended and
9086 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
9087 LONGEST val
= unpack_long (type
, valbuf
);
9089 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
9090 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
9094 /* Integral values greater than one word are stored in consecutive
9095 registers starting with r0. This will always be a multiple of
9096 the regiser size. */
9097 int len
= TYPE_LENGTH (type
);
9098 int regno
= ARM_A1_REGNUM
;
9102 regcache_cooked_write (regs
, regno
++, valbuf
);
9103 len
-= INT_REGISTER_SIZE
;
9104 valbuf
+= INT_REGISTER_SIZE
;
9110 /* For a structure or union the behaviour is as if the value had
9111 been stored to word-aligned memory and then loaded into
9112 registers with 32-bit load instruction(s). */
9113 int len
= TYPE_LENGTH (type
);
9114 int regno
= ARM_A1_REGNUM
;
9115 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
9119 memcpy (tmpbuf
, valbuf
,
9120 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
9121 regcache_cooked_write (regs
, regno
++, tmpbuf
);
9122 len
-= INT_REGISTER_SIZE
;
9123 valbuf
+= INT_REGISTER_SIZE
;
9129 /* Handle function return values. */
9131 static enum return_value_convention
9132 arm_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
9133 struct type
*valtype
, struct regcache
*regcache
,
9134 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
9136 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9137 struct type
*func_type
= function
? value_type (function
) : NULL
;
9138 enum arm_vfp_cprc_base_type vfp_base_type
;
9141 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
9142 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
9144 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
9145 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
9147 for (i
= 0; i
< vfp_base_count
; i
++)
9149 if (reg_char
== 'q')
9152 arm_neon_quad_write (gdbarch
, regcache
, i
,
9153 writebuf
+ i
* unit_length
);
9156 arm_neon_quad_read (gdbarch
, regcache
, i
,
9157 readbuf
+ i
* unit_length
);
9164 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d", reg_char
, i
);
9165 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9168 regcache_cooked_write (regcache
, regnum
,
9169 writebuf
+ i
* unit_length
);
9171 regcache_cooked_read (regcache
, regnum
,
9172 readbuf
+ i
* unit_length
);
9175 return RETURN_VALUE_REGISTER_CONVENTION
;
9178 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
9179 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
9180 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
9182 if (tdep
->struct_return
== pcc_struct_return
9183 || arm_return_in_memory (gdbarch
, valtype
))
9184 return RETURN_VALUE_STRUCT_CONVENTION
;
9187 /* AAPCS returns complex types longer than a register in memory. */
9188 if (tdep
->arm_abi
!= ARM_ABI_APCS
9189 && TYPE_CODE (valtype
) == TYPE_CODE_COMPLEX
9190 && TYPE_LENGTH (valtype
) > INT_REGISTER_SIZE
)
9191 return RETURN_VALUE_STRUCT_CONVENTION
;
9194 arm_store_return_value (valtype
, regcache
, writebuf
);
9197 arm_extract_return_value (valtype
, regcache
, readbuf
);
9199 return RETURN_VALUE_REGISTER_CONVENTION
;
9204 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
9206 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
9207 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9208 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
9210 char buf
[INT_REGISTER_SIZE
];
9212 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
9214 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
9218 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
9222 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
9223 return the target PC. Otherwise return 0. */
9226 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
9230 CORE_ADDR start_addr
;
9232 /* Find the starting address and name of the function containing the PC. */
9233 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
9236 /* If PC is in a Thumb call or return stub, return the address of the
9237 target PC, which is in a register. The thunk functions are called
9238 _call_via_xx, where x is the register name. The possible names
9239 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
9240 functions, named __ARM_call_via_r[0-7]. */
9241 if (strncmp (name
, "_call_via_", 10) == 0
9242 || strncmp (name
, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0)
9244 /* Use the name suffix to determine which register contains the
9246 static char *table
[15] =
9247 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
9248 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
9251 int offset
= strlen (name
) - 2;
9253 for (regno
= 0; regno
<= 14; regno
++)
9254 if (strcmp (&name
[offset
], table
[regno
]) == 0)
9255 return get_frame_register_unsigned (frame
, regno
);
9258 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
9259 non-interworking calls to foo. We could decode the stubs
9260 to find the target but it's easier to use the symbol table. */
9261 namelen
= strlen (name
);
9262 if (name
[0] == '_' && name
[1] == '_'
9263 && ((namelen
> 2 + strlen ("_from_thumb")
9264 && strncmp (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb",
9265 strlen ("_from_thumb")) == 0)
9266 || (namelen
> 2 + strlen ("_from_arm")
9267 && strncmp (name
+ namelen
- strlen ("_from_arm"), "_from_arm",
9268 strlen ("_from_arm")) == 0)))
9271 int target_len
= namelen
- 2;
9272 struct minimal_symbol
*minsym
;
9273 struct objfile
*objfile
;
9274 struct obj_section
*sec
;
9276 if (name
[namelen
- 1] == 'b')
9277 target_len
-= strlen ("_from_thumb");
9279 target_len
-= strlen ("_from_arm");
9281 target_name
= alloca (target_len
+ 1);
9282 memcpy (target_name
, name
+ 2, target_len
);
9283 target_name
[target_len
] = '\0';
9285 sec
= find_pc_section (pc
);
9286 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
9287 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
9289 return SYMBOL_VALUE_ADDRESS (minsym
);
9294 return 0; /* not a stub */
9298 set_arm_command (char *args
, int from_tty
)
9300 printf_unfiltered (_("\
9301 \"set arm\" must be followed by an apporpriate subcommand.\n"));
9302 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
9306 show_arm_command (char *args
, int from_tty
)
9308 cmd_show_list (showarmcmdlist
, from_tty
, "");
9312 arm_update_current_architecture (void)
9314 struct gdbarch_info info
;
9316 /* If the current architecture is not ARM, we have nothing to do. */
9317 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_arm
)
9320 /* Update the architecture. */
9321 gdbarch_info_init (&info
);
9323 if (!gdbarch_update_p (info
))
9324 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
9328 set_fp_model_sfunc (char *args
, int from_tty
,
9329 struct cmd_list_element
*c
)
9331 enum arm_float_model fp_model
;
9333 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
9334 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
9336 arm_fp_model
= fp_model
;
9340 if (fp_model
== ARM_FLOAT_LAST
)
9341 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
9344 arm_update_current_architecture ();
9348 show_fp_model (struct ui_file
*file
, int from_tty
,
9349 struct cmd_list_element
*c
, const char *value
)
9351 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
9353 if (arm_fp_model
== ARM_FLOAT_AUTO
9354 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
9355 fprintf_filtered (file
, _("\
9356 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
9357 fp_model_strings
[tdep
->fp_model
]);
9359 fprintf_filtered (file
, _("\
9360 The current ARM floating point model is \"%s\".\n"),
9361 fp_model_strings
[arm_fp_model
]);
9365 arm_set_abi (char *args
, int from_tty
,
9366 struct cmd_list_element
*c
)
9368 enum arm_abi_kind arm_abi
;
9370 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
9371 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
9373 arm_abi_global
= arm_abi
;
9377 if (arm_abi
== ARM_ABI_LAST
)
9378 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
9381 arm_update_current_architecture ();
9385 arm_show_abi (struct ui_file
*file
, int from_tty
,
9386 struct cmd_list_element
*c
, const char *value
)
9388 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
9390 if (arm_abi_global
== ARM_ABI_AUTO
9391 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
9392 fprintf_filtered (file
, _("\
9393 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
9394 arm_abi_strings
[tdep
->arm_abi
]);
9396 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
9401 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
9402 struct cmd_list_element
*c
, const char *value
)
9404 fprintf_filtered (file
,
9405 _("The current execution mode assumed "
9406 "(when symbols are unavailable) is \"%s\".\n"),
9407 arm_fallback_mode_string
);
9411 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
9412 struct cmd_list_element
*c
, const char *value
)
9414 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
9416 fprintf_filtered (file
,
9417 _("The current execution mode assumed "
9418 "(even when symbols are available) is \"%s\".\n"),
9419 arm_force_mode_string
);
9422 /* If the user changes the register disassembly style used for info
9423 register and other commands, we have to also switch the style used
9424 in opcodes for disassembly output. This function is run in the "set
9425 arm disassembly" command, and does that. */
9428 set_disassembly_style_sfunc (char *args
, int from_tty
,
9429 struct cmd_list_element
*c
)
9431 set_disassembly_style ();
9434 /* Return the ARM register name corresponding to register I. */
9436 arm_register_name (struct gdbarch
*gdbarch
, int i
)
9438 const int num_regs
= gdbarch_num_regs (gdbarch
);
9440 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
9441 && i
>= num_regs
&& i
< num_regs
+ 32)
9443 static const char *const vfp_pseudo_names
[] = {
9444 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
9445 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
9446 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
9447 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
9450 return vfp_pseudo_names
[i
- num_regs
];
9453 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
9454 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
9456 static const char *const neon_pseudo_names
[] = {
9457 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
9458 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
9461 return neon_pseudo_names
[i
- num_regs
- 32];
9464 if (i
>= ARRAY_SIZE (arm_register_names
))
9465 /* These registers are only supported on targets which supply
9466 an XML description. */
9469 return arm_register_names
[i
];
9473 set_disassembly_style (void)
9477 /* Find the style that the user wants. */
9478 for (current
= 0; current
< num_disassembly_options
; current
++)
9479 if (disassembly_style
== valid_disassembly_styles
[current
])
9481 gdb_assert (current
< num_disassembly_options
);
9483 /* Synchronize the disassembler. */
9484 set_arm_regname_option (current
);
9487 /* Test whether the coff symbol specific value corresponds to a Thumb
9491 coff_sym_is_thumb (int val
)
9493 return (val
== C_THUMBEXT
9494 || val
== C_THUMBSTAT
9495 || val
== C_THUMBEXTFUNC
9496 || val
== C_THUMBSTATFUNC
9497 || val
== C_THUMBLABEL
);
9500 /* arm_coff_make_msymbol_special()
9501 arm_elf_make_msymbol_special()
9503 These functions test whether the COFF or ELF symbol corresponds to
9504 an address in thumb code, and set a "special" bit in a minimal
9505 symbol to indicate that it does. */
9508 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
9510 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type
*)sym
)->internal_elf_sym
)
9511 == ST_BRANCH_TO_THUMB
)
9512 MSYMBOL_SET_SPECIAL (msym
);
9516 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
9518 if (coff_sym_is_thumb (val
))
9519 MSYMBOL_SET_SPECIAL (msym
);
9523 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
9525 struct arm_per_objfile
*data
= arg
;
9528 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
9529 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
9533 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
9536 const char *name
= bfd_asymbol_name (sym
);
9537 struct arm_per_objfile
*data
;
9538 VEC(arm_mapping_symbol_s
) **map_p
;
9539 struct arm_mapping_symbol new_map_sym
;
9541 gdb_assert (name
[0] == '$');
9542 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
9545 data
= objfile_data (objfile
, arm_objfile_data_key
);
9548 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
9549 struct arm_per_objfile
);
9550 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
9551 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
9552 objfile
->obfd
->section_count
,
9553 VEC(arm_mapping_symbol_s
) *);
9555 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
9557 new_map_sym
.value
= sym
->value
;
9558 new_map_sym
.type
= name
[1];
9560 /* Assume that most mapping symbols appear in order of increasing
9561 value. If they were randomly distributed, it would be faster to
9562 always push here and then sort at first use. */
9563 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
9565 struct arm_mapping_symbol
*prev_map_sym
;
9567 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
9568 if (prev_map_sym
->value
>= sym
->value
)
9571 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
9572 arm_compare_mapping_symbols
);
9573 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
9578 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
9582 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
9584 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
9585 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
9587 /* If necessary, set the T bit. */
9590 ULONGEST val
, t_bit
;
9591 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
9592 t_bit
= arm_psr_thumb_bit (gdbarch
);
9593 if (arm_pc_is_thumb (gdbarch
, pc
))
9594 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
9597 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
9602 /* Read the contents of a NEON quad register, by reading from two
9603 double registers. This is used to implement the quad pseudo
9604 registers, and for argument passing in case the quad registers are
9605 missing; vectors are passed in quad registers when using the VFP
9606 ABI, even if a NEON unit is not present. REGNUM is the index of
9607 the quad register, in [0, 15]. */
9609 static enum register_status
9610 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9611 int regnum
, gdb_byte
*buf
)
9614 gdb_byte reg_buf
[8];
9615 int offset
, double_regnum
;
9616 enum register_status status
;
9618 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
9619 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9622 /* d0 is always the least significant half of q0. */
9623 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9628 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9629 if (status
!= REG_VALID
)
9631 memcpy (buf
+ offset
, reg_buf
, 8);
9633 offset
= 8 - offset
;
9634 status
= regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
9635 if (status
!= REG_VALID
)
9637 memcpy (buf
+ offset
, reg_buf
, 8);
9642 static enum register_status
9643 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9644 int regnum
, gdb_byte
*buf
)
9646 const int num_regs
= gdbarch_num_regs (gdbarch
);
9648 gdb_byte reg_buf
[8];
9649 int offset
, double_regnum
;
9651 gdb_assert (regnum
>= num_regs
);
9654 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
9655 /* Quad-precision register. */
9656 return arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
9659 enum register_status status
;
9661 /* Single-precision register. */
9662 gdb_assert (regnum
< 32);
9664 /* s0 is always the least significant half of d0. */
9665 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9666 offset
= (regnum
& 1) ? 0 : 4;
9668 offset
= (regnum
& 1) ? 4 : 0;
9670 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
9671 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9674 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9675 if (status
== REG_VALID
)
9676 memcpy (buf
, reg_buf
+ offset
, 4);
9681 /* Store the contents of BUF to a NEON quad register, by writing to
9682 two double registers. This is used to implement the quad pseudo
9683 registers, and for argument passing in case the quad registers are
9684 missing; vectors are passed in quad registers when using the VFP
9685 ABI, even if a NEON unit is not present. REGNUM is the index
9686 of the quad register, in [0, 15]. */
9689 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9690 int regnum
, const gdb_byte
*buf
)
9693 int offset
, double_regnum
;
9695 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
9696 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9699 /* d0 is always the least significant half of q0. */
9700 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9705 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
9706 offset
= 8 - offset
;
9707 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
9711 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9712 int regnum
, const gdb_byte
*buf
)
9714 const int num_regs
= gdbarch_num_regs (gdbarch
);
9716 gdb_byte reg_buf
[8];
9717 int offset
, double_regnum
;
9719 gdb_assert (regnum
>= num_regs
);
9722 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
9723 /* Quad-precision register. */
9724 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
9727 /* Single-precision register. */
9728 gdb_assert (regnum
< 32);
9730 /* s0 is always the least significant half of d0. */
9731 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9732 offset
= (regnum
& 1) ? 0 : 4;
9734 offset
= (regnum
& 1) ? 4 : 0;
9736 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
9737 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9740 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9741 memcpy (reg_buf
+ offset
, buf
, 4);
9742 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
9746 static struct value
*
9747 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
9749 const int *reg_p
= baton
;
9750 return value_of_register (*reg_p
, frame
);
9753 static enum gdb_osabi
9754 arm_elf_osabi_sniffer (bfd
*abfd
)
9756 unsigned int elfosabi
;
9757 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
9759 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
9761 if (elfosabi
== ELFOSABI_ARM
)
9762 /* GNU tools use this value. Check note sections in this case,
9764 bfd_map_over_sections (abfd
,
9765 generic_elf_osabi_sniff_abi_tag_sections
,
9768 /* Anything else will be handled by the generic ELF sniffer. */
9773 arm_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
9774 struct reggroup
*group
)
9776 /* FPS register's type is INT, but belongs to float_reggroup. Beside
9777 this, FPS register belongs to save_regroup, restore_reggroup, and
9778 all_reggroup, of course. */
9779 if (regnum
== ARM_FPS_REGNUM
)
9780 return (group
== float_reggroup
9781 || group
== save_reggroup
9782 || group
== restore_reggroup
9783 || group
== all_reggroup
);
9785 return default_register_reggroup_p (gdbarch
, regnum
, group
);
9789 /* For backward-compatibility we allow two 'g' packet lengths with
9790 the remote protocol depending on whether FPA registers are
9791 supplied. M-profile targets do not have FPA registers, but some
9792 stubs already exist in the wild which use a 'g' packet which
9793 supplies them albeit with dummy values. The packet format which
9794 includes FPA registers should be considered deprecated for
9795 M-profile targets. */
9798 arm_register_g_packet_guesses (struct gdbarch
*gdbarch
)
9800 if (gdbarch_tdep (gdbarch
)->is_m
)
9802 /* If we know from the executable this is an M-profile target,
9803 cater for remote targets whose register set layout is the
9804 same as the FPA layout. */
9805 register_remote_g_packet_guess (gdbarch
,
9806 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
9807 (16 * INT_REGISTER_SIZE
)
9808 + (8 * FP_REGISTER_SIZE
)
9809 + (2 * INT_REGISTER_SIZE
),
9810 tdesc_arm_with_m_fpa_layout
);
9812 /* The regular M-profile layout. */
9813 register_remote_g_packet_guess (gdbarch
,
9814 /* r0-r12,sp,lr,pc; xpsr */
9815 (16 * INT_REGISTER_SIZE
)
9816 + INT_REGISTER_SIZE
,
9819 /* M-profile plus M4F VFP. */
9820 register_remote_g_packet_guess (gdbarch
,
9821 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
9822 (16 * INT_REGISTER_SIZE
)
9823 + (16 * VFP_REGISTER_SIZE
)
9824 + (2 * INT_REGISTER_SIZE
),
9825 tdesc_arm_with_m_vfp_d16
);
9828 /* Otherwise we don't have a useful guess. */
9832 /* Initialize the current architecture based on INFO. If possible,
9833 re-use an architecture from ARCHES, which is a list of
9834 architectures already created during this debugging session.
9836 Called e.g. at program startup, when reading a core file, and when
9837 reading a binary file. */
9839 static struct gdbarch
*
9840 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
9842 struct gdbarch_tdep
*tdep
;
9843 struct gdbarch
*gdbarch
;
9844 struct gdbarch_list
*best_arch
;
9845 enum arm_abi_kind arm_abi
= arm_abi_global
;
9846 enum arm_float_model fp_model
= arm_fp_model
;
9847 struct tdesc_arch_data
*tdesc_data
= NULL
;
9849 int have_vfp_registers
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
9851 int have_fpa_registers
= 1;
9852 const struct target_desc
*tdesc
= info
.target_desc
;
9854 /* If we have an object to base this architecture on, try to determine
9857 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
9859 int ei_osabi
, e_flags
;
9861 switch (bfd_get_flavour (info
.abfd
))
9863 case bfd_target_aout_flavour
:
9864 /* Assume it's an old APCS-style ABI. */
9865 arm_abi
= ARM_ABI_APCS
;
9868 case bfd_target_coff_flavour
:
9869 /* Assume it's an old APCS-style ABI. */
9871 arm_abi
= ARM_ABI_APCS
;
9874 case bfd_target_elf_flavour
:
9875 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
9876 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9878 if (ei_osabi
== ELFOSABI_ARM
)
9880 /* GNU tools used to use this value, but do not for EABI
9881 objects. There's nowhere to tag an EABI version
9882 anyway, so assume APCS. */
9883 arm_abi
= ARM_ABI_APCS
;
9885 else if (ei_osabi
== ELFOSABI_NONE
)
9887 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
9888 int attr_arch
, attr_profile
;
9892 case EF_ARM_EABI_UNKNOWN
:
9893 /* Assume GNU tools. */
9894 arm_abi
= ARM_ABI_APCS
;
9897 case EF_ARM_EABI_VER4
:
9898 case EF_ARM_EABI_VER5
:
9899 arm_abi
= ARM_ABI_AAPCS
;
9900 /* EABI binaries default to VFP float ordering.
9901 They may also contain build attributes that can
9902 be used to identify if the VFP argument-passing
9904 if (fp_model
== ARM_FLOAT_AUTO
)
9907 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
9912 /* "The user intended FP parameter/result
9913 passing to conform to AAPCS, base
9915 fp_model
= ARM_FLOAT_SOFT_VFP
;
9918 /* "The user intended FP parameter/result
9919 passing to conform to AAPCS, VFP
9921 fp_model
= ARM_FLOAT_VFP
;
9924 /* "The user intended FP parameter/result
9925 passing to conform to tool chain-specific
9926 conventions" - we don't know any such
9927 conventions, so leave it as "auto". */
9930 /* Attribute value not mentioned in the
9931 October 2008 ABI, so leave it as
9936 fp_model
= ARM_FLOAT_SOFT_VFP
;
9942 /* Leave it as "auto". */
9943 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
9948 /* Detect M-profile programs. This only works if the
9949 executable file includes build attributes; GCC does
9950 copy them to the executable, but e.g. RealView does
9952 attr_arch
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
9954 attr_profile
= bfd_elf_get_obj_attr_int (info
.abfd
,
9956 Tag_CPU_arch_profile
);
9957 /* GCC specifies the profile for v6-M; RealView only
9958 specifies the profile for architectures starting with
9959 V7 (as opposed to architectures with a tag
9960 numerically greater than TAG_CPU_ARCH_V7). */
9961 if (!tdesc_has_registers (tdesc
)
9962 && (attr_arch
== TAG_CPU_ARCH_V6_M
9963 || attr_arch
== TAG_CPU_ARCH_V6S_M
9964 || attr_profile
== 'M'))
9969 if (fp_model
== ARM_FLOAT_AUTO
)
9971 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9973 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
9976 /* Leave it as "auto". Strictly speaking this case
9977 means FPA, but almost nobody uses that now, and
9978 many toolchains fail to set the appropriate bits
9979 for the floating-point model they use. */
9981 case EF_ARM_SOFT_FLOAT
:
9982 fp_model
= ARM_FLOAT_SOFT_FPA
;
9984 case EF_ARM_VFP_FLOAT
:
9985 fp_model
= ARM_FLOAT_VFP
;
9987 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
9988 fp_model
= ARM_FLOAT_SOFT_VFP
;
9993 if (e_flags
& EF_ARM_BE8
)
9994 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
9999 /* Leave it as "auto". */
10004 /* Check any target description for validity. */
10005 if (tdesc_has_registers (tdesc
))
10007 /* For most registers we require GDB's default names; but also allow
10008 the numeric names for sp / lr / pc, as a convenience. */
10009 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
10010 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
10011 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
10013 const struct tdesc_feature
*feature
;
10016 feature
= tdesc_find_feature (tdesc
,
10017 "org.gnu.gdb.arm.core");
10018 if (feature
== NULL
)
10020 feature
= tdesc_find_feature (tdesc
,
10021 "org.gnu.gdb.arm.m-profile");
10022 if (feature
== NULL
)
10028 tdesc_data
= tdesc_data_alloc ();
10031 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
10032 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
10033 arm_register_names
[i
]);
10034 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
10037 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
10040 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
10044 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10045 ARM_PS_REGNUM
, "xpsr");
10047 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10048 ARM_PS_REGNUM
, "cpsr");
10052 tdesc_data_cleanup (tdesc_data
);
10056 feature
= tdesc_find_feature (tdesc
,
10057 "org.gnu.gdb.arm.fpa");
10058 if (feature
!= NULL
)
10061 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
10062 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
10063 arm_register_names
[i
]);
10066 tdesc_data_cleanup (tdesc_data
);
10071 have_fpa_registers
= 0;
10073 feature
= tdesc_find_feature (tdesc
,
10074 "org.gnu.gdb.xscale.iwmmxt");
10075 if (feature
!= NULL
)
10077 static const char *const iwmmxt_names
[] = {
10078 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
10079 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
10080 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
10081 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
10085 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
10087 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
10088 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
10090 /* Check for the control registers, but do not fail if they
10092 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
10093 tdesc_numbered_register (feature
, tdesc_data
, i
,
10094 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
10096 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
10098 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
10099 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
10103 tdesc_data_cleanup (tdesc_data
);
10108 /* If we have a VFP unit, check whether the single precision registers
10109 are present. If not, then we will synthesize them as pseudo
10111 feature
= tdesc_find_feature (tdesc
,
10112 "org.gnu.gdb.arm.vfp");
10113 if (feature
!= NULL
)
10115 static const char *const vfp_double_names
[] = {
10116 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
10117 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
10118 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
10119 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
10122 /* Require the double precision registers. There must be either
10125 for (i
= 0; i
< 32; i
++)
10127 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10129 vfp_double_names
[i
]);
10133 if (!valid_p
&& i
== 16)
10136 /* Also require FPSCR. */
10137 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10138 ARM_FPSCR_REGNUM
, "fpscr");
10141 tdesc_data_cleanup (tdesc_data
);
10145 if (tdesc_unnumbered_register (feature
, "s0") == 0)
10146 have_vfp_pseudos
= 1;
10148 have_vfp_registers
= 1;
10150 /* If we have VFP, also check for NEON. The architecture allows
10151 NEON without VFP (integer vector operations only), but GDB
10152 does not support that. */
10153 feature
= tdesc_find_feature (tdesc
,
10154 "org.gnu.gdb.arm.neon");
10155 if (feature
!= NULL
)
10157 /* NEON requires 32 double-precision registers. */
10160 tdesc_data_cleanup (tdesc_data
);
10164 /* If there are quad registers defined by the stub, use
10165 their type; otherwise (normally) provide them with
10166 the default type. */
10167 if (tdesc_unnumbered_register (feature
, "q0") == 0)
10168 have_neon_pseudos
= 1;
10175 /* If there is already a candidate, use it. */
10176 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
10178 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
10180 if (arm_abi
!= ARM_ABI_AUTO
10181 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
10184 if (fp_model
!= ARM_FLOAT_AUTO
10185 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
10188 /* There are various other properties in tdep that we do not
10189 need to check here: those derived from a target description,
10190 since gdbarches with a different target description are
10191 automatically disqualified. */
10193 /* Do check is_m, though, since it might come from the binary. */
10194 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
10197 /* Found a match. */
10201 if (best_arch
!= NULL
)
10203 if (tdesc_data
!= NULL
)
10204 tdesc_data_cleanup (tdesc_data
);
10205 return best_arch
->gdbarch
;
10208 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
10209 gdbarch
= gdbarch_alloc (&info
, tdep
);
10211 /* Record additional information about the architecture we are defining.
10212 These are gdbarch discriminators, like the OSABI. */
10213 tdep
->arm_abi
= arm_abi
;
10214 tdep
->fp_model
= fp_model
;
10216 tdep
->have_fpa_registers
= have_fpa_registers
;
10217 tdep
->have_vfp_registers
= have_vfp_registers
;
10218 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
10219 tdep
->have_neon_pseudos
= have_neon_pseudos
;
10220 tdep
->have_neon
= have_neon
;
10222 arm_register_g_packet_guesses (gdbarch
);
10225 switch (info
.byte_order_for_code
)
10227 case BFD_ENDIAN_BIG
:
10228 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
10229 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
10230 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
10231 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
10235 case BFD_ENDIAN_LITTLE
:
10236 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
10237 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
10238 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
10239 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
10244 internal_error (__FILE__
, __LINE__
,
10245 _("arm_gdbarch_init: bad byte order for float format"));
10248 /* On ARM targets char defaults to unsigned. */
10249 set_gdbarch_char_signed (gdbarch
, 0);
10251 /* Note: for displaced stepping, this includes the breakpoint, and one word
10252 of additional scratch space. This setting isn't used for anything beside
10253 displaced stepping at present. */
10254 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
10256 /* This should be low enough for everything. */
10257 tdep
->lowest_pc
= 0x20;
10258 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
10260 /* The default, for both APCS and AAPCS, is to return small
10261 structures in registers. */
10262 tdep
->struct_return
= reg_struct_return
;
10264 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
10265 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
10267 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
10269 /* Frame handling. */
10270 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
10271 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
10272 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
10274 frame_base_set_default (gdbarch
, &arm_normal_base
);
10276 /* Address manipulation. */
10277 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
10279 /* Advance PC across function entry code. */
10280 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
10282 /* Detect whether PC is in function epilogue. */
10283 set_gdbarch_in_function_epilogue_p (gdbarch
, arm_in_function_epilogue_p
);
10285 /* Skip trampolines. */
10286 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
10288 /* The stack grows downward. */
10289 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
10291 /* Breakpoint manipulation. */
10292 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
10293 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
10294 arm_remote_breakpoint_from_pc
);
10296 /* Information about registers, etc. */
10297 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
10298 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
10299 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
10300 set_gdbarch_register_type (gdbarch
, arm_register_type
);
10301 set_gdbarch_register_reggroup_p (gdbarch
, arm_register_reggroup_p
);
10303 /* This "info float" is FPA-specific. Use the generic version if we
10304 do not have FPA. */
10305 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
10306 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
10308 /* Internal <-> external register number maps. */
10309 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
10310 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
10312 set_gdbarch_register_name (gdbarch
, arm_register_name
);
10314 /* Returning results. */
10315 set_gdbarch_return_value (gdbarch
, arm_return_value
);
10318 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
10320 /* Minsymbol frobbing. */
10321 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
10322 set_gdbarch_coff_make_msymbol_special (gdbarch
,
10323 arm_coff_make_msymbol_special
);
10324 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
10326 /* Thumb-2 IT block support. */
10327 set_gdbarch_adjust_breakpoint_address (gdbarch
,
10328 arm_adjust_breakpoint_address
);
10330 /* Virtual tables. */
10331 set_gdbarch_vbit_in_delta (gdbarch
, 1);
10333 /* Hook in the ABI-specific overrides, if they have been registered. */
10334 gdbarch_init_osabi (info
, gdbarch
);
10336 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
10338 /* Add some default predicates. */
10340 frame_unwind_append_unwinder (gdbarch
, &arm_m_exception_unwind
);
10341 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
10342 dwarf2_append_unwinders (gdbarch
);
10343 frame_unwind_append_unwinder (gdbarch
, &arm_exidx_unwind
);
10344 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
10346 /* Now we have tuned the configuration, set a few final things,
10347 based on what the OS ABI has told us. */
10349 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
10350 binaries are always marked. */
10351 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
10352 tdep
->arm_abi
= ARM_ABI_APCS
;
10354 /* Watchpoints are not steppable. */
10355 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
10357 /* We used to default to FPA for generic ARM, but almost nobody
10358 uses that now, and we now provide a way for the user to force
10359 the model. So default to the most useful variant. */
10360 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
10361 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
10363 if (tdep
->jb_pc
>= 0)
10364 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
10366 /* Floating point sizes and format. */
10367 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
10368 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
10370 set_gdbarch_double_format
10371 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
10372 set_gdbarch_long_double_format
10373 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
10377 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
10378 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
10381 if (have_vfp_pseudos
)
10383 /* NOTE: These are the only pseudo registers used by
10384 the ARM target at the moment. If more are added, a
10385 little more care in numbering will be needed. */
10387 int num_pseudos
= 32;
10388 if (have_neon_pseudos
)
10390 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
10391 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
10392 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
10397 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
10399 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
10401 /* Override tdesc_register_type to adjust the types of VFP
10402 registers for NEON. */
10403 set_gdbarch_register_type (gdbarch
, arm_register_type
);
10406 /* Add standard register aliases. We add aliases even for those
10407 nanes which are used by the current architecture - it's simpler,
10408 and does no harm, since nothing ever lists user registers. */
10409 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
10410 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
10411 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
10417 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
10419 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
10424 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
10425 (unsigned long) tdep
->lowest_pc
);
10428 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
10431 _initialize_arm_tdep (void)
10433 struct ui_file
*stb
;
10435 struct cmd_list_element
*new_set
, *new_show
;
10436 const char *setname
;
10437 const char *setdesc
;
10438 const char *const *regnames
;
10440 static char *helptext
;
10441 char regdesc
[1024], *rdptr
= regdesc
;
10442 size_t rest
= sizeof (regdesc
);
10444 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
10446 arm_objfile_data_key
10447 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
10449 /* Add ourselves to objfile event chain. */
10450 observer_attach_new_objfile (arm_exidx_new_objfile
);
10452 = register_objfile_data_with_cleanup (NULL
, arm_exidx_data_free
);
10454 /* Register an ELF OS ABI sniffer for ARM binaries. */
10455 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
10456 bfd_target_elf_flavour
,
10457 arm_elf_osabi_sniffer
);
10459 /* Initialize the standard target descriptions. */
10460 initialize_tdesc_arm_with_m ();
10461 initialize_tdesc_arm_with_m_fpa_layout ();
10462 initialize_tdesc_arm_with_m_vfp_d16 ();
10463 initialize_tdesc_arm_with_iwmmxt ();
10464 initialize_tdesc_arm_with_vfpv2 ();
10465 initialize_tdesc_arm_with_vfpv3 ();
10466 initialize_tdesc_arm_with_neon ();
10468 /* Get the number of possible sets of register names defined in opcodes. */
10469 num_disassembly_options
= get_arm_regname_num_options ();
10471 /* Add root prefix command for all "set arm"/"show arm" commands. */
10472 add_prefix_cmd ("arm", no_class
, set_arm_command
,
10473 _("Various ARM-specific commands."),
10474 &setarmcmdlist
, "set arm ", 0, &setlist
);
10476 add_prefix_cmd ("arm", no_class
, show_arm_command
,
10477 _("Various ARM-specific commands."),
10478 &showarmcmdlist
, "show arm ", 0, &showlist
);
10480 /* Sync the opcode insn printer with our register viewer. */
10481 parse_arm_disassembler_option ("reg-names-std");
10483 /* Initialize the array that will be passed to
10484 add_setshow_enum_cmd(). */
10485 valid_disassembly_styles
10486 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
10487 for (i
= 0; i
< num_disassembly_options
; i
++)
10489 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
10490 valid_disassembly_styles
[i
] = setname
;
10491 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
10494 /* When we find the default names, tell the disassembler to use
10496 if (!strcmp (setname
, "std"))
10498 disassembly_style
= setname
;
10499 set_arm_regname_option (i
);
10502 /* Mark the end of valid options. */
10503 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
10505 /* Create the help text. */
10506 stb
= mem_fileopen ();
10507 fprintf_unfiltered (stb
, "%s%s%s",
10508 _("The valid values are:\n"),
10510 _("The default is \"std\"."));
10511 helptext
= ui_file_xstrdup (stb
, NULL
);
10512 ui_file_delete (stb
);
10514 add_setshow_enum_cmd("disassembler", no_class
,
10515 valid_disassembly_styles
, &disassembly_style
,
10516 _("Set the disassembly style."),
10517 _("Show the disassembly style."),
10519 set_disassembly_style_sfunc
,
10520 NULL
, /* FIXME: i18n: The disassembly style is
10522 &setarmcmdlist
, &showarmcmdlist
);
10524 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
10525 _("Set usage of ARM 32-bit mode."),
10526 _("Show usage of ARM 32-bit mode."),
10527 _("When off, a 26-bit PC will be used."),
10529 NULL
, /* FIXME: i18n: Usage of ARM 32-bit
10531 &setarmcmdlist
, &showarmcmdlist
);
10533 /* Add a command to allow the user to force the FPU model. */
10534 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
10535 _("Set the floating point type."),
10536 _("Show the floating point type."),
10537 _("auto - Determine the FP typefrom the OS-ABI.\n\
10538 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
10539 fpa - FPA co-processor (GCC compiled).\n\
10540 softvfp - Software FP with pure-endian doubles.\n\
10541 vfp - VFP co-processor."),
10542 set_fp_model_sfunc
, show_fp_model
,
10543 &setarmcmdlist
, &showarmcmdlist
);
10545 /* Add a command to allow the user to force the ABI. */
10546 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
10548 _("Show the ABI."),
10549 NULL
, arm_set_abi
, arm_show_abi
,
10550 &setarmcmdlist
, &showarmcmdlist
);
10552 /* Add two commands to allow the user to force the assumed
10554 add_setshow_enum_cmd ("fallback-mode", class_support
,
10555 arm_mode_strings
, &arm_fallback_mode_string
,
10556 _("Set the mode assumed when symbols are unavailable."),
10557 _("Show the mode assumed when symbols are unavailable."),
10558 NULL
, NULL
, arm_show_fallback_mode
,
10559 &setarmcmdlist
, &showarmcmdlist
);
10560 add_setshow_enum_cmd ("force-mode", class_support
,
10561 arm_mode_strings
, &arm_force_mode_string
,
10562 _("Set the mode assumed even when symbols are available."),
10563 _("Show the mode assumed even when symbols are available."),
10564 NULL
, NULL
, arm_show_force_mode
,
10565 &setarmcmdlist
, &showarmcmdlist
);
10567 /* Debugging flag. */
10568 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
10569 _("Set ARM debugging."),
10570 _("Show ARM debugging."),
10571 _("When on, arm-specific debugging is enabled."),
10573 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
10574 &setdebuglist
, &showdebuglist
);
10577 /* ARM-reversible process record data structures. */
10579 #define ARM_INSN_SIZE_BYTES 4
10580 #define THUMB_INSN_SIZE_BYTES 2
10581 #define THUMB2_INSN_SIZE_BYTES 4
10584 #define INSN_S_L_BIT_NUM 20
10586 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
10589 unsigned int reg_len = LENGTH; \
10592 REGS = XNEWVEC (uint32_t, reg_len); \
10593 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
10598 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
10601 unsigned int mem_len = LENGTH; \
10604 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
10605 memcpy(&MEMS->len, &RECORD_BUF[0], \
10606 sizeof(struct arm_mem_r) * LENGTH); \
10611 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
10612 #define INSN_RECORDED(ARM_RECORD) \
10613 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
10615 /* ARM memory record structure. */
10618 uint32_t len
; /* Record length. */
10619 CORE_ADDR addr
; /* Memory address. */
10622 /* ARM instruction record contains opcode of current insn
10623 and execution state (before entry to decode_insn()),
10624 contains list of to-be-modified registers and
10625 memory blocks (on return from decode_insn()). */
10627 typedef struct insn_decode_record_t
10629 struct gdbarch
*gdbarch
;
10630 struct regcache
*regcache
;
10631 CORE_ADDR this_addr
; /* Address of the insn being decoded. */
10632 uint32_t arm_insn
; /* Should accommodate thumb. */
10633 uint32_t cond
; /* Condition code. */
10634 uint32_t opcode
; /* Insn opcode. */
10635 uint32_t decode
; /* Insn decode bits. */
10636 uint32_t mem_rec_count
; /* No of mem records. */
10637 uint32_t reg_rec_count
; /* No of reg records. */
10638 uint32_t *arm_regs
; /* Registers to be saved for this record. */
10639 struct arm_mem_r
*arm_mems
; /* Memory to be saved for this record. */
10640 } insn_decode_record
;
10643 /* Checks ARM SBZ and SBO mandatory fields. */
10646 sbo_sbz (uint32_t insn
, uint32_t bit_num
, uint32_t len
, uint32_t sbo
)
10648 uint32_t ones
= bits (insn
, bit_num
- 1, (bit_num
-1) + (len
- 1));
10671 } arm_record_strx_t
;
10682 arm_record_strx (insn_decode_record
*arm_insn_r
, uint32_t *record_buf
,
10683 uint32_t *record_buf_mem
, arm_record_strx_t str_type
)
10686 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10687 ULONGEST u_regval
[2]= {0};
10689 uint32_t reg_src1
= 0, reg_src2
= 0;
10690 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
10691 uint32_t opcode1
= 0;
10693 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10694 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10695 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
10698 if (14 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10700 /* 1) Handle misc store, immediate offset. */
10701 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
10702 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
10703 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10704 regcache_raw_read_unsigned (reg_cache
, reg_src1
,
10706 if (ARM_PC_REGNUM
== reg_src1
)
10708 /* If R15 was used as Rn, hence current PC+8. */
10709 u_regval
[0] = u_regval
[0] + 8;
10711 offset_8
= (immed_high
<< 4) | immed_low
;
10712 /* Calculate target store address. */
10713 if (14 == arm_insn_r
->opcode
)
10715 tgt_mem_addr
= u_regval
[0] + offset_8
;
10719 tgt_mem_addr
= u_regval
[0] - offset_8
;
10721 if (ARM_RECORD_STRH
== str_type
)
10723 record_buf_mem
[0] = 2;
10724 record_buf_mem
[1] = tgt_mem_addr
;
10725 arm_insn_r
->mem_rec_count
= 1;
10727 else if (ARM_RECORD_STRD
== str_type
)
10729 record_buf_mem
[0] = 4;
10730 record_buf_mem
[1] = tgt_mem_addr
;
10731 record_buf_mem
[2] = 4;
10732 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10733 arm_insn_r
->mem_rec_count
= 2;
10736 else if (12 == arm_insn_r
->opcode
|| 8 == arm_insn_r
->opcode
)
10738 /* 2) Store, register offset. */
10740 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10742 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10743 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10744 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10745 if (15 == reg_src2
)
10747 /* If R15 was used as Rn, hence current PC+8. */
10748 u_regval
[0] = u_regval
[0] + 8;
10750 /* Calculate target store address, Rn +/- Rm, register offset. */
10751 if (12 == arm_insn_r
->opcode
)
10753 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10757 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10759 if (ARM_RECORD_STRH
== str_type
)
10761 record_buf_mem
[0] = 2;
10762 record_buf_mem
[1] = tgt_mem_addr
;
10763 arm_insn_r
->mem_rec_count
= 1;
10765 else if (ARM_RECORD_STRD
== str_type
)
10767 record_buf_mem
[0] = 4;
10768 record_buf_mem
[1] = tgt_mem_addr
;
10769 record_buf_mem
[2] = 4;
10770 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10771 arm_insn_r
->mem_rec_count
= 2;
10774 else if (11 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10775 || 2 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
10777 /* 3) Store, immediate pre-indexed. */
10778 /* 5) Store, immediate post-indexed. */
10779 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
10780 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
10781 offset_8
= (immed_high
<< 4) | immed_low
;
10782 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10783 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10784 /* Calculate target store address, Rn +/- Rm, register offset. */
10785 if (15 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
10787 tgt_mem_addr
= u_regval
[0] + offset_8
;
10791 tgt_mem_addr
= u_regval
[0] - offset_8
;
10793 if (ARM_RECORD_STRH
== str_type
)
10795 record_buf_mem
[0] = 2;
10796 record_buf_mem
[1] = tgt_mem_addr
;
10797 arm_insn_r
->mem_rec_count
= 1;
10799 else if (ARM_RECORD_STRD
== str_type
)
10801 record_buf_mem
[0] = 4;
10802 record_buf_mem
[1] = tgt_mem_addr
;
10803 record_buf_mem
[2] = 4;
10804 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10805 arm_insn_r
->mem_rec_count
= 2;
10807 /* Record Rn also as it changes. */
10808 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
10809 arm_insn_r
->reg_rec_count
= 1;
10811 else if (9 == arm_insn_r
->opcode
|| 13 == arm_insn_r
->opcode
10812 || 0 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
10814 /* 4) Store, register pre-indexed. */
10815 /* 6) Store, register post -indexed. */
10816 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10817 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10818 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10819 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10820 /* Calculate target store address, Rn +/- Rm, register offset. */
10821 if (13 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
10823 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10827 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10829 if (ARM_RECORD_STRH
== str_type
)
10831 record_buf_mem
[0] = 2;
10832 record_buf_mem
[1] = tgt_mem_addr
;
10833 arm_insn_r
->mem_rec_count
= 1;
10835 else if (ARM_RECORD_STRD
== str_type
)
10837 record_buf_mem
[0] = 4;
10838 record_buf_mem
[1] = tgt_mem_addr
;
10839 record_buf_mem
[2] = 4;
10840 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10841 arm_insn_r
->mem_rec_count
= 2;
10843 /* Record Rn also as it changes. */
10844 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
10845 arm_insn_r
->reg_rec_count
= 1;
10850 /* Handling ARM extension space insns. */
10853 arm_record_extension_space (insn_decode_record
*arm_insn_r
)
10855 uint32_t ret
= 0; /* Return value: -1:record failure ; 0:success */
10856 uint32_t opcode1
= 0, opcode2
= 0, insn_op1
= 0;
10857 uint32_t record_buf
[8], record_buf_mem
[8];
10858 uint32_t reg_src1
= 0;
10859 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
10860 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10861 ULONGEST u_regval
= 0;
10863 gdb_assert (!INSN_RECORDED(arm_insn_r
));
10864 /* Handle unconditional insn extension space. */
10866 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 27);
10867 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10868 if (arm_insn_r
->cond
)
10870 /* PLD has no affect on architectural state, it just affects
10872 if (5 == ((opcode1
& 0xE0) >> 5))
10875 record_buf
[0] = ARM_PS_REGNUM
;
10876 record_buf
[1] = ARM_LR_REGNUM
;
10877 arm_insn_r
->reg_rec_count
= 2;
10879 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10883 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10884 if (3 == opcode1
&& bit (arm_insn_r
->arm_insn
, 4))
10887 /* Undefined instruction on ARM V5; need to handle if later
10888 versions define it. */
10891 opcode1
= bits (arm_insn_r
->arm_insn
, 24, 27);
10892 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10893 insn_op1
= bits (arm_insn_r
->arm_insn
, 20, 23);
10895 /* Handle arithmetic insn extension space. */
10896 if (!opcode1
&& 9 == opcode2
&& 1 != arm_insn_r
->cond
10897 && !INSN_RECORDED(arm_insn_r
))
10899 /* Handle MLA(S) and MUL(S). */
10900 if (0 <= insn_op1
&& 3 >= insn_op1
)
10902 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10903 record_buf
[1] = ARM_PS_REGNUM
;
10904 arm_insn_r
->reg_rec_count
= 2;
10906 else if (4 <= insn_op1
&& 15 >= insn_op1
)
10908 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
10909 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10910 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10911 record_buf
[2] = ARM_PS_REGNUM
;
10912 arm_insn_r
->reg_rec_count
= 3;
10916 opcode1
= bits (arm_insn_r
->arm_insn
, 26, 27);
10917 opcode2
= bits (arm_insn_r
->arm_insn
, 23, 24);
10918 insn_op1
= bits (arm_insn_r
->arm_insn
, 21, 22);
10920 /* Handle control insn extension space. */
10922 if (!opcode1
&& 2 == opcode2
&& !bit (arm_insn_r
->arm_insn
, 20)
10923 && 1 != arm_insn_r
->cond
&& !INSN_RECORDED(arm_insn_r
))
10925 if (!bit (arm_insn_r
->arm_insn
,25))
10927 if (!bits (arm_insn_r
->arm_insn
, 4, 7))
10929 if ((0 == insn_op1
) || (2 == insn_op1
))
10932 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10933 arm_insn_r
->reg_rec_count
= 1;
10935 else if (1 == insn_op1
)
10937 /* CSPR is going to be changed. */
10938 record_buf
[0] = ARM_PS_REGNUM
;
10939 arm_insn_r
->reg_rec_count
= 1;
10941 else if (3 == insn_op1
)
10943 /* SPSR is going to be changed. */
10944 /* We need to get SPSR value, which is yet to be done. */
10945 printf_unfiltered (_("Process record does not support "
10946 "instruction 0x%0x at address %s.\n"),
10947 arm_insn_r
->arm_insn
,
10948 paddress (arm_insn_r
->gdbarch
,
10949 arm_insn_r
->this_addr
));
10953 else if (1 == bits (arm_insn_r
->arm_insn
, 4, 7))
10958 record_buf
[0] = ARM_PS_REGNUM
;
10959 arm_insn_r
->reg_rec_count
= 1;
10961 else if (3 == insn_op1
)
10964 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10965 arm_insn_r
->reg_rec_count
= 1;
10968 else if (3 == bits (arm_insn_r
->arm_insn
, 4, 7))
10971 record_buf
[0] = ARM_PS_REGNUM
;
10972 record_buf
[1] = ARM_LR_REGNUM
;
10973 arm_insn_r
->reg_rec_count
= 2;
10975 else if (5 == bits (arm_insn_r
->arm_insn
, 4, 7))
10977 /* QADD, QSUB, QDADD, QDSUB */
10978 record_buf
[0] = ARM_PS_REGNUM
;
10979 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
10980 arm_insn_r
->reg_rec_count
= 2;
10982 else if (7 == bits (arm_insn_r
->arm_insn
, 4, 7))
10985 record_buf
[0] = ARM_PS_REGNUM
;
10986 record_buf
[1] = ARM_LR_REGNUM
;
10987 arm_insn_r
->reg_rec_count
= 2;
10989 /* Save SPSR also;how? */
10990 printf_unfiltered (_("Process record does not support "
10991 "instruction 0x%0x at address %s.\n"),
10992 arm_insn_r
->arm_insn
,
10993 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
10996 else if(8 == bits (arm_insn_r
->arm_insn
, 4, 7)
10997 || 10 == bits (arm_insn_r
->arm_insn
, 4, 7)
10998 || 12 == bits (arm_insn_r
->arm_insn
, 4, 7)
10999 || 14 == bits (arm_insn_r
->arm_insn
, 4, 7)
11002 if (0 == insn_op1
|| 1 == insn_op1
)
11004 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
11005 /* We dont do optimization for SMULW<y> where we
11007 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11008 record_buf
[1] = ARM_PS_REGNUM
;
11009 arm_insn_r
->reg_rec_count
= 2;
11011 else if (2 == insn_op1
)
11014 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11015 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11016 arm_insn_r
->reg_rec_count
= 2;
11018 else if (3 == insn_op1
)
11021 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11022 arm_insn_r
->reg_rec_count
= 1;
11028 /* MSR : immediate form. */
11031 /* CSPR is going to be changed. */
11032 record_buf
[0] = ARM_PS_REGNUM
;
11033 arm_insn_r
->reg_rec_count
= 1;
11035 else if (3 == insn_op1
)
11037 /* SPSR is going to be changed. */
11038 /* we need to get SPSR value, which is yet to be done */
11039 printf_unfiltered (_("Process record does not support "
11040 "instruction 0x%0x at address %s.\n"),
11041 arm_insn_r
->arm_insn
,
11042 paddress (arm_insn_r
->gdbarch
,
11043 arm_insn_r
->this_addr
));
11049 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
11050 opcode2
= bits (arm_insn_r
->arm_insn
, 20, 24);
11051 insn_op1
= bits (arm_insn_r
->arm_insn
, 5, 6);
11053 /* Handle load/store insn extension space. */
11055 if (!opcode1
&& bit (arm_insn_r
->arm_insn
, 7)
11056 && bit (arm_insn_r
->arm_insn
, 4) && 1 != arm_insn_r
->cond
11057 && !INSN_RECORDED(arm_insn_r
))
11062 /* These insn, changes register and memory as well. */
11063 /* SWP or SWPB insn. */
11064 /* Get memory address given by Rn. */
11065 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11066 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11067 /* SWP insn ?, swaps word. */
11068 if (8 == arm_insn_r
->opcode
)
11070 record_buf_mem
[0] = 4;
11074 /* SWPB insn, swaps only byte. */
11075 record_buf_mem
[0] = 1;
11077 record_buf_mem
[1] = u_regval
;
11078 arm_insn_r
->mem_rec_count
= 1;
11079 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11080 arm_insn_r
->reg_rec_count
= 1;
11082 else if (1 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
11085 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11088 else if (2 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
11091 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11092 record_buf
[1] = record_buf
[0] + 1;
11093 arm_insn_r
->reg_rec_count
= 2;
11095 else if (3 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
11098 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11101 else if (bit (arm_insn_r
->arm_insn
, 20) && insn_op1
<= 3)
11103 /* LDRH, LDRSB, LDRSH. */
11104 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11105 arm_insn_r
->reg_rec_count
= 1;
11110 opcode1
= bits (arm_insn_r
->arm_insn
, 23, 27);
11111 if (24 == opcode1
&& bit (arm_insn_r
->arm_insn
, 21)
11112 && !INSN_RECORDED(arm_insn_r
))
11115 /* Handle coprocessor insn extension space. */
11118 /* To be done for ARMv5 and later; as of now we return -1. */
11120 printf_unfiltered (_("Process record does not support instruction x%0x "
11121 "at address %s.\n"),arm_insn_r
->arm_insn
,
11122 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11125 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11126 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11131 /* Handling opcode 000 insns. */
11134 arm_record_data_proc_misc_ld_str (insn_decode_record
*arm_insn_r
)
11136 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11137 uint32_t record_buf
[8], record_buf_mem
[8];
11138 ULONGEST u_regval
[2] = {0};
11140 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
11141 uint32_t immed_high
= 0, immed_low
= 0, offset_8
= 0, tgt_mem_addr
= 0;
11142 uint32_t opcode1
= 0;
11144 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11145 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11146 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
11148 /* Data processing insn /multiply insn. */
11149 if (9 == arm_insn_r
->decode
11150 && ((4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
11151 || (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)))
11153 /* Handle multiply instructions. */
11154 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
11155 if (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)
11157 /* Handle MLA and MUL. */
11158 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
11159 record_buf
[1] = ARM_PS_REGNUM
;
11160 arm_insn_r
->reg_rec_count
= 2;
11162 else if (4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
11164 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
11165 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
11166 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
11167 record_buf
[2] = ARM_PS_REGNUM
;
11168 arm_insn_r
->reg_rec_count
= 3;
11171 else if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
11172 && (11 == arm_insn_r
->decode
|| 13 == arm_insn_r
->decode
))
11174 /* Handle misc load insns, as 20th bit (L = 1). */
11175 /* LDR insn has a capability to do branching, if
11176 MOV LR, PC is precceded by LDR insn having Rn as R15
11177 in that case, it emulates branch and link insn, and hence we
11178 need to save CSPR and PC as well. I am not sure this is right
11179 place; as opcode = 010 LDR insn make this happen, if R15 was
11181 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11182 if (15 != reg_dest
)
11184 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11185 arm_insn_r
->reg_rec_count
= 1;
11189 record_buf
[0] = reg_dest
;
11190 record_buf
[1] = ARM_PS_REGNUM
;
11191 arm_insn_r
->reg_rec_count
= 2;
11194 else if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
11195 && sbo_sbz (arm_insn_r
->arm_insn
, 5, 12, 0)
11196 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
11197 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21))
11199 /* Handle MSR insn. */
11200 if (9 == arm_insn_r
->opcode
)
11202 /* CSPR is going to be changed. */
11203 record_buf
[0] = ARM_PS_REGNUM
;
11204 arm_insn_r
->reg_rec_count
= 1;
11208 /* SPSR is going to be changed. */
11209 /* How to read SPSR value? */
11210 printf_unfiltered (_("Process record does not support instruction "
11211 "0x%0x at address %s.\n"),
11212 arm_insn_r
->arm_insn
,
11213 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11217 else if (9 == arm_insn_r
->decode
11218 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
11219 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11221 /* Handling SWP, SWPB. */
11222 /* These insn, changes register and memory as well. */
11223 /* SWP or SWPB insn. */
11225 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11226 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11227 /* SWP insn ?, swaps word. */
11228 if (8 == arm_insn_r
->opcode
)
11230 record_buf_mem
[0] = 4;
11234 /* SWPB insn, swaps only byte. */
11235 record_buf_mem
[0] = 1;
11237 record_buf_mem
[1] = u_regval
[0];
11238 arm_insn_r
->mem_rec_count
= 1;
11239 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11240 arm_insn_r
->reg_rec_count
= 1;
11242 else if (3 == arm_insn_r
->decode
&& 0x12 == opcode1
11243 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
11245 /* Handle BLX, branch and link/exchange. */
11246 if (9 == arm_insn_r
->opcode
)
11248 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
11249 and R14 stores the return address. */
11250 record_buf
[0] = ARM_PS_REGNUM
;
11251 record_buf
[1] = ARM_LR_REGNUM
;
11252 arm_insn_r
->reg_rec_count
= 2;
11255 else if (7 == arm_insn_r
->decode
&& 0x12 == opcode1
)
11257 /* Handle enhanced software breakpoint insn, BKPT. */
11258 /* CPSR is changed to be executed in ARM state, disabling normal
11259 interrupts, entering abort mode. */
11260 /* According to high vector configuration PC is set. */
11261 /* user hit breakpoint and type reverse, in
11262 that case, we need to go back with previous CPSR and
11263 Program Counter. */
11264 record_buf
[0] = ARM_PS_REGNUM
;
11265 record_buf
[1] = ARM_LR_REGNUM
;
11266 arm_insn_r
->reg_rec_count
= 2;
11268 /* Save SPSR also; how? */
11269 printf_unfiltered (_("Process record does not support instruction "
11270 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11271 paddress (arm_insn_r
->gdbarch
,
11272 arm_insn_r
->this_addr
));
11275 else if (11 == arm_insn_r
->decode
11276 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11278 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
11280 /* Handle str(x) insn */
11281 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11284 else if (1 == arm_insn_r
->decode
&& 0x12 == opcode1
11285 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
11287 /* Handle BX, branch and link/exchange. */
11288 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
11289 record_buf
[0] = ARM_PS_REGNUM
;
11290 arm_insn_r
->reg_rec_count
= 1;
11292 else if (1 == arm_insn_r
->decode
&& 0x16 == opcode1
11293 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 4, 1)
11294 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1))
11296 /* Count leading zeros: CLZ. */
11297 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11298 arm_insn_r
->reg_rec_count
= 1;
11300 else if (!bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
11301 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
11302 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1)
11303 && sbo_sbz (arm_insn_r
->arm_insn
, 1, 12, 0)
11306 /* Handle MRS insn. */
11307 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11308 arm_insn_r
->reg_rec_count
= 1;
11310 else if (arm_insn_r
->opcode
<= 15)
11312 /* Normal data processing insns. */
11313 /* Out of 11 shifter operands mode, all the insn modifies destination
11314 register, which is specified by 13-16 decode. */
11315 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11316 record_buf
[1] = ARM_PS_REGNUM
;
11317 arm_insn_r
->reg_rec_count
= 2;
11324 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11325 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11329 /* Handling opcode 001 insns. */
11332 arm_record_data_proc_imm (insn_decode_record
*arm_insn_r
)
11334 uint32_t record_buf
[8], record_buf_mem
[8];
11336 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11337 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11339 if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
11340 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21)
11341 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
11344 /* Handle MSR insn. */
11345 if (9 == arm_insn_r
->opcode
)
11347 /* CSPR is going to be changed. */
11348 record_buf
[0] = ARM_PS_REGNUM
;
11349 arm_insn_r
->reg_rec_count
= 1;
11353 /* SPSR is going to be changed. */
11356 else if (arm_insn_r
->opcode
<= 15)
11358 /* Normal data processing insns. */
11359 /* Out of 11 shifter operands mode, all the insn modifies destination
11360 register, which is specified by 13-16 decode. */
11361 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11362 record_buf
[1] = ARM_PS_REGNUM
;
11363 arm_insn_r
->reg_rec_count
= 2;
11370 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11371 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11375 /* Handling opcode 010 insns. */
11378 arm_record_ld_st_imm_offset (insn_decode_record
*arm_insn_r
)
11380 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11382 uint32_t reg_src1
= 0 , reg_dest
= 0;
11383 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
11384 uint32_t record_buf
[8], record_buf_mem
[8];
11386 ULONGEST u_regval
= 0;
11388 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11389 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11391 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11393 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11394 /* LDR insn has a capability to do branching, if
11395 MOV LR, PC is precedded by LDR insn having Rn as R15
11396 in that case, it emulates branch and link insn, and hence we
11397 need to save CSPR and PC as well. */
11398 if (ARM_PC_REGNUM
!= reg_dest
)
11400 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11401 arm_insn_r
->reg_rec_count
= 1;
11405 record_buf
[0] = reg_dest
;
11406 record_buf
[1] = ARM_PS_REGNUM
;
11407 arm_insn_r
->reg_rec_count
= 2;
11412 /* Store, immediate offset, immediate pre-indexed,
11413 immediate post-indexed. */
11414 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11415 offset_12
= bits (arm_insn_r
->arm_insn
, 0, 11);
11416 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11418 if (bit (arm_insn_r
->arm_insn
, 23))
11420 tgt_mem_addr
= u_regval
+ offset_12
;
11424 tgt_mem_addr
= u_regval
- offset_12
;
11427 switch (arm_insn_r
->opcode
)
11441 record_buf_mem
[0] = 4;
11456 record_buf_mem
[0] = 1;
11460 gdb_assert_not_reached ("no decoding pattern found");
11463 record_buf_mem
[1] = tgt_mem_addr
;
11464 arm_insn_r
->mem_rec_count
= 1;
11466 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
11467 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
11468 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
11469 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
11470 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
11471 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
11474 /* We are handling pre-indexed mode; post-indexed mode;
11475 where Rn is going to be changed. */
11476 record_buf
[0] = reg_src1
;
11477 arm_insn_r
->reg_rec_count
= 1;
11481 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11482 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11486 /* Handling opcode 011 insns. */
11489 arm_record_ld_st_reg_offset (insn_decode_record
*arm_insn_r
)
11491 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11493 uint32_t shift_imm
= 0;
11494 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
11495 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
11496 uint32_t record_buf
[8], record_buf_mem
[8];
11499 ULONGEST u_regval
[2];
11501 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11502 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11504 /* Handle enhanced store insns and LDRD DSP insn,
11505 order begins according to addressing modes for store insns
11509 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11511 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11512 /* LDR insn has a capability to do branching, if
11513 MOV LR, PC is precedded by LDR insn having Rn as R15
11514 in that case, it emulates branch and link insn, and hence we
11515 need to save CSPR and PC as well. */
11516 if (15 != reg_dest
)
11518 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11519 arm_insn_r
->reg_rec_count
= 1;
11523 record_buf
[0] = reg_dest
;
11524 record_buf
[1] = ARM_PS_REGNUM
;
11525 arm_insn_r
->reg_rec_count
= 2;
11530 if (! bits (arm_insn_r
->arm_insn
, 4, 11))
11532 /* Store insn, register offset and register pre-indexed,
11533 register post-indexed. */
11535 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
11537 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11538 regcache_raw_read_unsigned (reg_cache
, reg_src1
11540 regcache_raw_read_unsigned (reg_cache
, reg_src2
11542 if (15 == reg_src2
)
11544 /* If R15 was used as Rn, hence current PC+8. */
11545 /* Pre-indexed mode doesnt reach here ; illegal insn. */
11546 u_regval
[0] = u_regval
[0] + 8;
11548 /* Calculate target store address, Rn +/- Rm, register offset. */
11550 if (bit (arm_insn_r
->arm_insn
, 23))
11552 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
11556 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
11559 switch (arm_insn_r
->opcode
)
11573 record_buf_mem
[0] = 4;
11588 record_buf_mem
[0] = 1;
11592 gdb_assert_not_reached ("no decoding pattern found");
11595 record_buf_mem
[1] = tgt_mem_addr
;
11596 arm_insn_r
->mem_rec_count
= 1;
11598 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
11599 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
11600 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
11601 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
11602 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
11603 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
11606 /* Rn is going to be changed in pre-indexed mode and
11607 post-indexed mode as well. */
11608 record_buf
[0] = reg_src2
;
11609 arm_insn_r
->reg_rec_count
= 1;
11614 /* Store insn, scaled register offset; scaled pre-indexed. */
11615 offset_12
= bits (arm_insn_r
->arm_insn
, 5, 6);
11617 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
11619 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11620 /* Get shift_imm. */
11621 shift_imm
= bits (arm_insn_r
->arm_insn
, 7, 11);
11622 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11623 regcache_raw_read_signed (reg_cache
, reg_src1
, &s_word
);
11624 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11625 /* Offset_12 used as shift. */
11629 /* Offset_12 used as index. */
11630 offset_12
= u_regval
[0] << shift_imm
;
11634 offset_12
= (!shift_imm
)?0:u_regval
[0] >> shift_imm
;
11640 if (bit (u_regval
[0], 31))
11642 offset_12
= 0xFFFFFFFF;
11651 /* This is arithmetic shift. */
11652 offset_12
= s_word
>> shift_imm
;
11659 regcache_raw_read_unsigned (reg_cache
, ARM_PS_REGNUM
,
11661 /* Get C flag value and shift it by 31. */
11662 offset_12
= (((bit (u_regval
[1], 29)) << 31) \
11663 | (u_regval
[0]) >> 1);
11667 offset_12
= (u_regval
[0] >> shift_imm
) \
11669 (sizeof(uint32_t) - shift_imm
));
11674 gdb_assert_not_reached ("no decoding pattern found");
11678 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11680 if (bit (arm_insn_r
->arm_insn
, 23))
11682 tgt_mem_addr
= u_regval
[1] + offset_12
;
11686 tgt_mem_addr
= u_regval
[1] - offset_12
;
11689 switch (arm_insn_r
->opcode
)
11703 record_buf_mem
[0] = 4;
11718 record_buf_mem
[0] = 1;
11722 gdb_assert_not_reached ("no decoding pattern found");
11725 record_buf_mem
[1] = tgt_mem_addr
;
11726 arm_insn_r
->mem_rec_count
= 1;
11728 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
11729 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
11730 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
11731 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
11732 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
11733 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
11736 /* Rn is going to be changed in register scaled pre-indexed
11737 mode,and scaled post indexed mode. */
11738 record_buf
[0] = reg_src2
;
11739 arm_insn_r
->reg_rec_count
= 1;
11744 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11745 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11749 /* Handling opcode 100 insns. */
11752 arm_record_ld_st_multiple (insn_decode_record
*arm_insn_r
)
11754 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11756 uint32_t register_list
[16] = {0}, register_count
= 0, register_bits
= 0;
11757 uint32_t reg_src1
= 0, addr_mode
= 0, no_of_regs
= 0;
11758 uint32_t start_address
= 0, index
= 0;
11759 uint32_t record_buf
[24], record_buf_mem
[48];
11761 ULONGEST u_regval
[2] = {0};
11763 /* This mode is exclusively for load and store multiple. */
11764 /* Handle incremenrt after/before and decrment after.before mode;
11765 Rn is changing depending on W bit, but as of now we store Rn too
11766 without optimization. */
11768 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11770 /* LDM (1,2,3) where LDM (3) changes CPSR too. */
11772 if (bit (arm_insn_r
->arm_insn
, 20) && !bit (arm_insn_r
->arm_insn
, 22))
11774 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
11779 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 14);
11783 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11784 while (register_bits
)
11786 if (register_bits
& 0x00000001)
11787 register_list
[register_count
++] = 1;
11788 register_bits
= register_bits
>> 1;
11791 /* Extra space for Base Register and CPSR; wihtout optimization. */
11792 record_buf
[register_count
] = reg_src1
;
11793 record_buf
[register_count
+ 1] = ARM_PS_REGNUM
;
11794 arm_insn_r
->reg_rec_count
= register_count
+ 2;
11796 for (register_count
= 0; register_count
< no_of_regs
; register_count
++)
11798 if (register_list
[register_count
])
11800 /* Register_count gives total no of registers
11801 and dually working as reg number. */
11802 record_buf
[index
] = register_count
;
11810 /* It handles both STM(1) and STM(2). */
11811 addr_mode
= bits (arm_insn_r
->arm_insn
, 23, 24);
11813 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
11815 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11816 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11817 while (register_bits
)
11819 if (register_bits
& 0x00000001)
11821 register_bits
= register_bits
>> 1;
11826 /* Decrement after. */
11828 start_address
= (u_regval
[0]) - (register_count
* 4) + 4;
11829 arm_insn_r
->mem_rec_count
= register_count
;
11830 while (register_count
)
11832 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11833 record_buf_mem
[(register_count
* 2) - 2] = 4;
11834 start_address
= start_address
+ 4;
11839 /* Increment after. */
11841 start_address
= u_regval
[0];
11842 arm_insn_r
->mem_rec_count
= register_count
;
11843 while (register_count
)
11845 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11846 record_buf_mem
[(register_count
* 2) - 2] = 4;
11847 start_address
= start_address
+ 4;
11852 /* Decrement before. */
11855 start_address
= (u_regval
[0]) - (register_count
* 4);
11856 arm_insn_r
->mem_rec_count
= register_count
;
11857 while (register_count
)
11859 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11860 record_buf_mem
[(register_count
* 2) - 2] = 4;
11861 start_address
= start_address
+ 4;
11866 /* Increment before. */
11868 start_address
= u_regval
[0] + 4;
11869 arm_insn_r
->mem_rec_count
= register_count
;
11870 while (register_count
)
11872 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
11873 record_buf_mem
[(register_count
* 2) - 2] = 4;
11874 start_address
= start_address
+ 4;
11880 gdb_assert_not_reached ("no decoding pattern found");
11884 /* Base register also changes; based on condition and W bit. */
11885 /* We save it anyway without optimization. */
11886 record_buf
[0] = reg_src1
;
11887 arm_insn_r
->reg_rec_count
= 1;
11890 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11891 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11895 /* Handling opcode 101 insns. */
11898 arm_record_b_bl (insn_decode_record
*arm_insn_r
)
11900 uint32_t record_buf
[8];
11902 /* Handle B, BL, BLX(1) insns. */
11903 /* B simply branches so we do nothing here. */
11904 /* Note: BLX(1) doesnt fall here but instead it falls into
11905 extension space. */
11906 if (bit (arm_insn_r
->arm_insn
, 24))
11908 record_buf
[0] = ARM_LR_REGNUM
;
11909 arm_insn_r
->reg_rec_count
= 1;
11912 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11917 /* Handling opcode 110 insns. */
11920 arm_record_coproc (insn_decode_record
*arm_insn_r
)
11922 printf_unfiltered (_("Process record does not support instruction "
11923 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11924 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11929 /* Handling opcode 111 insns. */
11932 arm_record_coproc_data_proc (insn_decode_record
*arm_insn_r
)
11934 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arm_insn_r
->gdbarch
);
11935 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11936 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
11938 /* Handle SWI insn; system call would be handled over here. */
11940 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 24, 27);
11941 if (15 == arm_insn_r
->opcode
)
11943 /* Handle arm syscall insn. */
11944 if (tdep
->arm_swi_record
!= NULL
)
11946 ret
= tdep
->arm_swi_record(reg_cache
);
11950 printf_unfiltered (_("no syscall record support\n"));
11955 printf_unfiltered (_("Process record does not support instruction "
11956 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11957 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11961 /* Handling opcode 000 insns. */
11964 thumb_record_shift_add_sub (insn_decode_record
*thumb_insn_r
)
11966 uint32_t record_buf
[8];
11967 uint32_t reg_src1
= 0;
11969 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
11971 record_buf
[0] = ARM_PS_REGNUM
;
11972 record_buf
[1] = reg_src1
;
11973 thumb_insn_r
->reg_rec_count
= 2;
11975 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
11981 /* Handling opcode 001 insns. */
11984 thumb_record_add_sub_cmp_mov (insn_decode_record
*thumb_insn_r
)
11986 uint32_t record_buf
[8];
11987 uint32_t reg_src1
= 0;
11989 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
11991 record_buf
[0] = ARM_PS_REGNUM
;
11992 record_buf
[1] = reg_src1
;
11993 thumb_insn_r
->reg_rec_count
= 2;
11995 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12000 /* Handling opcode 010 insns. */
12003 thumb_record_ld_st_reg_offset (insn_decode_record
*thumb_insn_r
)
12005 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12006 uint32_t record_buf
[8], record_buf_mem
[8];
12008 uint32_t reg_src1
= 0, reg_src2
= 0;
12009 uint32_t opcode1
= 0, opcode2
= 0, opcode3
= 0;
12011 ULONGEST u_regval
[2] = {0};
12013 opcode1
= bits (thumb_insn_r
->arm_insn
, 10, 12);
12015 if (bit (thumb_insn_r
->arm_insn
, 12))
12017 /* Handle load/store register offset. */
12018 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 10);
12019 if (opcode2
>= 12 && opcode2
<= 15)
12021 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
12022 reg_src1
= bits (thumb_insn_r
->arm_insn
,0, 2);
12023 record_buf
[0] = reg_src1
;
12024 thumb_insn_r
->reg_rec_count
= 1;
12026 else if (opcode2
>= 8 && opcode2
<= 10)
12028 /* STR(2), STRB(2), STRH(2) . */
12029 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12030 reg_src2
= bits (thumb_insn_r
->arm_insn
, 6, 8);
12031 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
12032 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
12034 record_buf_mem
[0] = 4; /* STR (2). */
12035 else if (10 == opcode2
)
12036 record_buf_mem
[0] = 1; /* STRB (2). */
12037 else if (9 == opcode2
)
12038 record_buf_mem
[0] = 2; /* STRH (2). */
12039 record_buf_mem
[1] = u_regval
[0] + u_regval
[1];
12040 thumb_insn_r
->mem_rec_count
= 1;
12043 else if (bit (thumb_insn_r
->arm_insn
, 11))
12045 /* Handle load from literal pool. */
12047 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12048 record_buf
[0] = reg_src1
;
12049 thumb_insn_r
->reg_rec_count
= 1;
12053 opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 9);
12054 opcode3
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12055 if ((3 == opcode2
) && (!opcode3
))
12057 /* Branch with exchange. */
12058 record_buf
[0] = ARM_PS_REGNUM
;
12059 thumb_insn_r
->reg_rec_count
= 1;
12063 /* Format 8; special data processing insns. */
12064 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12065 record_buf
[0] = ARM_PS_REGNUM
;
12066 record_buf
[1] = reg_src1
;
12067 thumb_insn_r
->reg_rec_count
= 2;
12072 /* Format 5; data processing insns. */
12073 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12074 if (bit (thumb_insn_r
->arm_insn
, 7))
12076 reg_src1
= reg_src1
+ 8;
12078 record_buf
[0] = ARM_PS_REGNUM
;
12079 record_buf
[1] = reg_src1
;
12080 thumb_insn_r
->reg_rec_count
= 2;
12083 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12084 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12090 /* Handling opcode 001 insns. */
12093 thumb_record_ld_st_imm_offset (insn_decode_record
*thumb_insn_r
)
12095 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12096 uint32_t record_buf
[8], record_buf_mem
[8];
12098 uint32_t reg_src1
= 0;
12099 uint32_t opcode
= 0, immed_5
= 0;
12101 ULONGEST u_regval
= 0;
12103 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12108 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12109 record_buf
[0] = reg_src1
;
12110 thumb_insn_r
->reg_rec_count
= 1;
12115 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12116 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
12117 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12118 record_buf_mem
[0] = 4;
12119 record_buf_mem
[1] = u_regval
+ (immed_5
* 4);
12120 thumb_insn_r
->mem_rec_count
= 1;
12123 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12124 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12130 /* Handling opcode 100 insns. */
12133 thumb_record_ld_st_stack (insn_decode_record
*thumb_insn_r
)
12135 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12136 uint32_t record_buf
[8], record_buf_mem
[8];
12138 uint32_t reg_src1
= 0;
12139 uint32_t opcode
= 0, immed_8
= 0, immed_5
= 0;
12141 ULONGEST u_regval
= 0;
12143 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12148 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12149 record_buf
[0] = reg_src1
;
12150 thumb_insn_r
->reg_rec_count
= 1;
12152 else if (1 == opcode
)
12155 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12156 record_buf
[0] = reg_src1
;
12157 thumb_insn_r
->reg_rec_count
= 1;
12159 else if (2 == opcode
)
12162 immed_8
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12163 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
12164 record_buf_mem
[0] = 4;
12165 record_buf_mem
[1] = u_regval
+ (immed_8
* 4);
12166 thumb_insn_r
->mem_rec_count
= 1;
12168 else if (0 == opcode
)
12171 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
12172 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12173 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12174 record_buf_mem
[0] = 2;
12175 record_buf_mem
[1] = u_regval
+ (immed_5
* 2);
12176 thumb_insn_r
->mem_rec_count
= 1;
12179 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12180 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12186 /* Handling opcode 101 insns. */
12189 thumb_record_misc (insn_decode_record
*thumb_insn_r
)
12191 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12193 uint32_t opcode
= 0, opcode1
= 0, opcode2
= 0;
12194 uint32_t register_bits
= 0, register_count
= 0;
12195 uint32_t register_list
[8] = {0}, index
= 0, start_address
= 0;
12196 uint32_t record_buf
[24], record_buf_mem
[48];
12199 ULONGEST u_regval
= 0;
12201 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12202 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12203 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 12);
12208 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12209 while (register_bits
)
12211 if (register_bits
& 0x00000001)
12212 register_list
[register_count
++] = 1;
12213 register_bits
= register_bits
>> 1;
12215 record_buf
[register_count
] = ARM_PS_REGNUM
;
12216 record_buf
[register_count
+ 1] = ARM_SP_REGNUM
;
12217 thumb_insn_r
->reg_rec_count
= register_count
+ 2;
12218 for (register_count
= 0; register_count
< 8; register_count
++)
12220 if (register_list
[register_count
])
12222 record_buf
[index
] = register_count
;
12227 else if (10 == opcode2
)
12230 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12231 regcache_raw_read_unsigned (reg_cache
, ARM_PC_REGNUM
, &u_regval
);
12232 while (register_bits
)
12234 if (register_bits
& 0x00000001)
12236 register_bits
= register_bits
>> 1;
12238 start_address
= u_regval
- \
12239 (4 * (bit (thumb_insn_r
->arm_insn
, 8) + register_count
));
12240 thumb_insn_r
->mem_rec_count
= register_count
;
12241 while (register_count
)
12243 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12244 record_buf_mem
[(register_count
* 2) - 2] = 4;
12245 start_address
= start_address
+ 4;
12248 record_buf
[0] = ARM_SP_REGNUM
;
12249 thumb_insn_r
->reg_rec_count
= 1;
12251 else if (0x1E == opcode1
)
12254 /* Handle enhanced software breakpoint insn, BKPT. */
12255 /* CPSR is changed to be executed in ARM state, disabling normal
12256 interrupts, entering abort mode. */
12257 /* According to high vector configuration PC is set. */
12258 /* User hits breakpoint and type reverse, in that case, we need to go back with
12259 previous CPSR and Program Counter. */
12260 record_buf
[0] = ARM_PS_REGNUM
;
12261 record_buf
[1] = ARM_LR_REGNUM
;
12262 thumb_insn_r
->reg_rec_count
= 2;
12263 /* We need to save SPSR value, which is not yet done. */
12264 printf_unfiltered (_("Process record does not support instruction "
12265 "0x%0x at address %s.\n"),
12266 thumb_insn_r
->arm_insn
,
12267 paddress (thumb_insn_r
->gdbarch
,
12268 thumb_insn_r
->this_addr
));
12271 else if ((0 == opcode
) || (1 == opcode
))
12273 /* ADD(5), ADD(6). */
12274 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12275 record_buf
[0] = reg_src1
;
12276 thumb_insn_r
->reg_rec_count
= 1;
12278 else if (2 == opcode
)
12280 /* ADD(7), SUB(4). */
12281 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12282 record_buf
[0] = ARM_SP_REGNUM
;
12283 thumb_insn_r
->reg_rec_count
= 1;
12286 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12287 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12293 /* Handling opcode 110 insns. */
12296 thumb_record_ldm_stm_swi (insn_decode_record
*thumb_insn_r
)
12298 struct gdbarch_tdep
*tdep
= gdbarch_tdep (thumb_insn_r
->gdbarch
);
12299 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12301 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
12302 uint32_t reg_src1
= 0;
12303 uint32_t opcode1
= 0, opcode2
= 0, register_bits
= 0, register_count
= 0;
12304 uint32_t register_list
[8] = {0}, index
= 0, start_address
= 0;
12305 uint32_t record_buf
[24], record_buf_mem
[48];
12307 ULONGEST u_regval
= 0;
12309 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12310 opcode2
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12316 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12318 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12319 while (register_bits
)
12321 if (register_bits
& 0x00000001)
12322 register_list
[register_count
++] = 1;
12323 register_bits
= register_bits
>> 1;
12325 record_buf
[register_count
] = reg_src1
;
12326 thumb_insn_r
->reg_rec_count
= register_count
+ 1;
12327 for (register_count
= 0; register_count
< 8; register_count
++)
12329 if (register_list
[register_count
])
12331 record_buf
[index
] = register_count
;
12336 else if (0 == opcode2
)
12338 /* It handles both STMIA. */
12339 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12341 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12342 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12343 while (register_bits
)
12345 if (register_bits
& 0x00000001)
12347 register_bits
= register_bits
>> 1;
12349 start_address
= u_regval
;
12350 thumb_insn_r
->mem_rec_count
= register_count
;
12351 while (register_count
)
12353 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12354 record_buf_mem
[(register_count
* 2) - 2] = 4;
12355 start_address
= start_address
+ 4;
12359 else if (0x1F == opcode1
)
12361 /* Handle arm syscall insn. */
12362 if (tdep
->arm_swi_record
!= NULL
)
12364 ret
= tdep
->arm_swi_record(reg_cache
);
12368 printf_unfiltered (_("no syscall record support\n"));
12373 /* B (1), conditional branch is automatically taken care in process_record,
12374 as PC is saved there. */
12376 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12377 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12383 /* Handling opcode 111 insns. */
12386 thumb_record_branch (insn_decode_record
*thumb_insn_r
)
12388 uint32_t record_buf
[8];
12389 uint32_t bits_h
= 0;
12391 bits_h
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12393 if (2 == bits_h
|| 3 == bits_h
)
12396 record_buf
[0] = ARM_LR_REGNUM
;
12397 thumb_insn_r
->reg_rec_count
= 1;
12399 else if (1 == bits_h
)
12402 record_buf
[0] = ARM_PS_REGNUM
;
12403 record_buf
[1] = ARM_LR_REGNUM
;
12404 thumb_insn_r
->reg_rec_count
= 2;
12407 /* B(2) is automatically taken care in process_record, as PC is
12410 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12416 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
12417 and positive val on fauilure. */
12420 extract_arm_insn (insn_decode_record
*insn_record
, uint32_t insn_size
)
12422 gdb_byte buf
[insn_size
];
12424 memset (&buf
[0], 0, insn_size
);
12426 if (target_read_memory (insn_record
->this_addr
, &buf
[0], insn_size
))
12428 insn_record
->arm_insn
= (uint32_t) extract_unsigned_integer (&buf
[0],
12430 gdbarch_byte_order (insn_record
->gdbarch
));
12434 typedef int (*sti_arm_hdl_fp_t
) (insn_decode_record
*);
12436 /* Decode arm/thumb insn depending on condition cods and opcodes; and
12440 decode_insn (insn_decode_record
*arm_record
, record_type_t record_type
,
12441 uint32_t insn_size
)
12444 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */
12445 static const sti_arm_hdl_fp_t
const arm_handle_insn
[8] =
12447 arm_record_data_proc_misc_ld_str
, /* 000. */
12448 arm_record_data_proc_imm
, /* 001. */
12449 arm_record_ld_st_imm_offset
, /* 010. */
12450 arm_record_ld_st_reg_offset
, /* 011. */
12451 arm_record_ld_st_multiple
, /* 100. */
12452 arm_record_b_bl
, /* 101. */
12453 arm_record_coproc
, /* 110. */
12454 arm_record_coproc_data_proc
/* 111. */
12457 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */
12458 static const sti_arm_hdl_fp_t
const thumb_handle_insn
[8] =
12460 thumb_record_shift_add_sub
, /* 000. */
12461 thumb_record_add_sub_cmp_mov
, /* 001. */
12462 thumb_record_ld_st_reg_offset
, /* 010. */
12463 thumb_record_ld_st_imm_offset
, /* 011. */
12464 thumb_record_ld_st_stack
, /* 100. */
12465 thumb_record_misc
, /* 101. */
12466 thumb_record_ldm_stm_swi
, /* 110. */
12467 thumb_record_branch
/* 111. */
12470 uint32_t ret
= 0; /* return value: negative:failure 0:success. */
12471 uint32_t insn_id
= 0;
12473 if (extract_arm_insn (arm_record
, insn_size
))
12477 printf_unfiltered (_("Process record: error reading memory at "
12478 "addr %s len = %d.\n"),
12479 paddress (arm_record
->gdbarch
, arm_record
->this_addr
), insn_size
);
12483 else if (ARM_RECORD
== record_type
)
12485 arm_record
->cond
= bits (arm_record
->arm_insn
, 28, 31);
12486 insn_id
= bits (arm_record
->arm_insn
, 25, 27);
12487 ret
= arm_record_extension_space (arm_record
);
12488 /* If this insn has fallen into extension space
12489 then we need not decode it anymore. */
12490 if (ret
!= -1 && !INSN_RECORDED(arm_record
))
12492 ret
= arm_handle_insn
[insn_id
] (arm_record
);
12495 else if (THUMB_RECORD
== record_type
)
12497 /* As thumb does not have condition codes, we set negative. */
12498 arm_record
->cond
= -1;
12499 insn_id
= bits (arm_record
->arm_insn
, 13, 15);
12500 ret
= thumb_handle_insn
[insn_id
] (arm_record
);
12502 else if (THUMB2_RECORD
== record_type
)
12504 printf_unfiltered (_("Process record doesnt support thumb32 instruction "
12505 "0x%0x at address %s.\n"),arm_record
->arm_insn
,
12506 paddress (arm_record
->gdbarch
,
12507 arm_record
->this_addr
));
12512 /* Throw assertion. */
12513 gdb_assert_not_reached ("not a valid instruction, could not decode");
12520 /* Cleans up local record registers and memory allocations. */
12523 deallocate_reg_mem (insn_decode_record
*record
)
12525 xfree (record
->arm_regs
);
12526 xfree (record
->arm_mems
);
12530 /* Parse the current instruction and record the values of the registers and
12531 memory that will be changed in current instruction to record_arch_list".
12532 Return -1 if something is wrong. */
12535 arm_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
12536 CORE_ADDR insn_addr
)
12539 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
12540 uint32_t no_of_rec
= 0;
12541 uint32_t ret
= 0; /* return value: -1:record failure ; 0:success */
12542 ULONGEST t_bit
= 0, insn_id
= 0;
12544 ULONGEST u_regval
= 0;
12546 insn_decode_record arm_record
;
12548 memset (&arm_record
, 0, sizeof (insn_decode_record
));
12549 arm_record
.regcache
= regcache
;
12550 arm_record
.this_addr
= insn_addr
;
12551 arm_record
.gdbarch
= gdbarch
;
12554 if (record_debug
> 1)
12556 fprintf_unfiltered (gdb_stdlog
, "Process record: arm_process_record "
12558 paddress (gdbarch
, arm_record
.this_addr
));
12561 if (extract_arm_insn (&arm_record
, 2))
12565 printf_unfiltered (_("Process record: error reading memory at "
12566 "addr %s len = %d.\n"),
12567 paddress (arm_record
.gdbarch
,
12568 arm_record
.this_addr
), 2);
12573 /* Check the insn, whether it is thumb or arm one. */
12575 t_bit
= arm_psr_thumb_bit (arm_record
.gdbarch
);
12576 regcache_raw_read_unsigned (arm_record
.regcache
, ARM_PS_REGNUM
, &u_regval
);
12579 if (!(u_regval
& t_bit
))
12581 /* We are decoding arm insn. */
12582 ret
= decode_insn (&arm_record
, ARM_RECORD
, ARM_INSN_SIZE_BYTES
);
12586 insn_id
= bits (arm_record
.arm_insn
, 11, 15);
12587 /* is it thumb2 insn? */
12588 if ((0x1D == insn_id
) || (0x1E == insn_id
) || (0x1F == insn_id
))
12590 ret
= decode_insn (&arm_record
, THUMB2_RECORD
,
12591 THUMB2_INSN_SIZE_BYTES
);
12595 /* We are decoding thumb insn. */
12596 ret
= decode_insn (&arm_record
, THUMB_RECORD
, THUMB_INSN_SIZE_BYTES
);
12602 /* Record registers. */
12603 record_arch_list_add_reg (arm_record
.regcache
, ARM_PC_REGNUM
);
12604 if (arm_record
.arm_regs
)
12606 for (no_of_rec
= 0; no_of_rec
< arm_record
.reg_rec_count
; no_of_rec
++)
12608 if (record_arch_list_add_reg (arm_record
.regcache
,
12609 arm_record
.arm_regs
[no_of_rec
]))
12613 /* Record memories. */
12614 if (arm_record
.arm_mems
)
12616 for (no_of_rec
= 0; no_of_rec
< arm_record
.mem_rec_count
; no_of_rec
++)
12618 if (record_arch_list_add_mem
12619 ((CORE_ADDR
)arm_record
.arm_mems
[no_of_rec
].addr
,
12620 arm_record
.arm_mems
[no_of_rec
].len
))
12625 if (record_arch_list_add_end ())
12630 deallocate_reg_mem (&arm_record
);