1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999,
4 2000, 2001, 2002, 2003, 2004, 2005, 2006
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
24 #include <ctype.h> /* XXX for isupper () */
31 #include "gdb_string.h"
32 #include "dis-asm.h" /* For register styles. */
36 #include "arch-utils.h"
38 #include "frame-unwind.h"
39 #include "frame-base.h"
40 #include "trad-frame.h"
42 #include "dwarf2-frame.h"
46 #include "gdb/sim-arm.h"
49 #include "coff/internal.h"
52 #include "gdb_assert.h"
56 /* Macros for setting and testing a bit in a minimal symbol that marks
57 it as Thumb function. The MSB of the minimal symbol's "info" field
58 is used for this purpose.
60 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
61 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
63 #define MSYMBOL_SET_SPECIAL(msym) \
64 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
67 #define MSYMBOL_IS_SPECIAL(msym) \
68 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
70 /* The list of available "set arm ..." and "show arm ..." commands. */
71 static struct cmd_list_element
*setarmcmdlist
= NULL
;
72 static struct cmd_list_element
*showarmcmdlist
= NULL
;
74 /* The type of floating-point to use. Keep this in sync with enum
75 arm_float_model, and the help string in _initialize_arm_tdep. */
76 static const char *fp_model_strings
[] =
86 /* A variable that can be configured by the user. */
87 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
88 static const char *current_fp_model
= "auto";
90 /* The ABI to use. Keep this in sync with arm_abi_kind. */
91 static const char *arm_abi_strings
[] =
99 /* A variable that can be configured by the user. */
100 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
101 static const char *arm_abi_string
= "auto";
103 /* Number of different reg name sets (options). */
104 static int num_disassembly_options
;
106 /* We have more registers than the disassembler as gdb can print the value
107 of special registers as well.
108 The general register names are overwritten by whatever is being used by
109 the disassembler at the moment. We also adjust the case of cpsr and fps. */
111 /* Initial value: Register names used in ARM's ISA documentation. */
112 static char * arm_register_name_strings
[] =
113 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
114 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
115 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
116 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
117 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
118 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
119 "fps", "cpsr" }; /* 24 25 */
120 static char **arm_register_names
= arm_register_name_strings
;
122 /* Valid register name styles. */
123 static const char **valid_disassembly_styles
;
125 /* Disassembly style to use. Default to "std" register names. */
126 static const char *disassembly_style
;
127 /* Index to that option in the opcodes table. */
128 static int current_option
;
130 /* This is used to keep the bfd arch_info in sync with the disassembly
132 static void set_disassembly_style_sfunc(char *, int,
133 struct cmd_list_element
*);
134 static void set_disassembly_style (void);
136 static void convert_from_extended (const struct floatformat
*, const void *,
138 static void convert_to_extended (const struct floatformat
*, void *,
141 struct arm_prologue_cache
143 /* The stack pointer at the time this frame was created; i.e. the
144 caller's stack pointer when this function was called. It is used
145 to identify this frame. */
148 /* The frame base for this frame is just prev_sp + frame offset -
149 frame size. FRAMESIZE is the size of this stack frame, and
150 FRAMEOFFSET if the initial offset from the stack pointer (this
151 frame's stack pointer, not PREV_SP) to the frame base. */
156 /* The register used to hold the frame pointer for this frame. */
159 /* Saved register offsets. */
160 struct trad_frame_saved_reg
*saved_regs
;
163 /* Addresses for calling Thumb functions have the bit 0 set.
164 Here are some macros to test, set, or clear bit 0 of addresses. */
165 #define IS_THUMB_ADDR(addr) ((addr) & 1)
166 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
167 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
169 /* Set to true if the 32-bit mode is in use. */
173 /* Determine if the program counter specified in MEMADDR is in a Thumb
177 arm_pc_is_thumb (CORE_ADDR memaddr
)
179 struct minimal_symbol
*sym
;
181 /* If bit 0 of the address is set, assume this is a Thumb address. */
182 if (IS_THUMB_ADDR (memaddr
))
185 /* Thumb functions have a "special" bit set in minimal symbols. */
186 sym
= lookup_minimal_symbol_by_pc (memaddr
);
189 return (MSYMBOL_IS_SPECIAL (sym
));
197 /* Remove useless bits from addresses in a running program. */
199 arm_addr_bits_remove (CORE_ADDR val
)
202 return (val
& (arm_pc_is_thumb (val
) ? 0xfffffffe : 0xfffffffc));
204 return (val
& 0x03fffffc);
207 /* When reading symbols, we need to zap the low bit of the address,
208 which may be set to 1 for Thumb functions. */
210 arm_smash_text_address (CORE_ADDR val
)
215 /* Immediately after a function call, return the saved pc. Can't
216 always go through the frames for this because on some machines the
217 new frame is not set up until the new function executes some
221 arm_saved_pc_after_call (struct frame_info
*frame
)
223 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM
));
226 /* A typical Thumb prologue looks like this:
230 Sometimes the latter instruction may be replaced by:
238 or, on tpcs, like this:
245 There is always one instruction of three classes:
250 When we have found at least one of each class we are done with the prolog.
251 Note that the "sub sp, #NN" before the push does not count.
255 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
257 CORE_ADDR current_pc
;
259 bit 0 - push { rlist }
260 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
261 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
265 for (current_pc
= pc
;
266 current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40;
269 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
271 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
273 findmask
|= 1; /* push found */
275 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
278 if ((findmask
& 1) == 0) /* before push ? */
281 findmask
|= 4; /* add/sub sp found */
283 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
285 findmask
|= 2; /* setting of r7 found */
287 else if (insn
== 0x466f) /* mov r7, sp */
289 findmask
|= 2; /* setting of r7 found */
291 else if (findmask
== (4+2+1))
293 /* We have found one of each type of prologue instruction */
297 /* Something in the prolog that we don't care about or some
298 instruction from outside the prolog scheduled here for
306 /* Advance the PC across any function entry prologue instructions to
307 reach some "real" code.
309 The APCS (ARM Procedure Call Standard) defines the following
313 [stmfd sp!, {a1,a2,a3,a4}]
314 stmfd sp!, {...,fp,ip,lr,pc}
315 [stfe f7, [sp, #-12]!]
316 [stfe f6, [sp, #-12]!]
317 [stfe f5, [sp, #-12]!]
318 [stfe f4, [sp, #-12]!]
319 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
322 arm_skip_prologue (CORE_ADDR pc
)
326 CORE_ADDR func_addr
, func_end
= 0;
328 struct symtab_and_line sal
;
330 /* If we're in a dummy frame, don't even try to skip the prologue. */
331 if (deprecated_pc_in_call_dummy (pc
))
334 /* See what the symbol table says. */
336 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
340 /* Found a function. */
341 sym
= lookup_symbol (func_name
, NULL
, VAR_DOMAIN
, NULL
, NULL
);
342 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
344 /* Don't use this trick for assembly source files. */
345 sal
= find_pc_line (func_addr
, 0);
346 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
351 /* Check if this is Thumb code. */
352 if (arm_pc_is_thumb (pc
))
353 return thumb_skip_prologue (pc
, func_end
);
355 /* Can't find the prologue end in the symbol table, try it the hard way
356 by disassembling the instructions. */
358 /* Like arm_scan_prologue, stop no later than pc + 64. */
359 if (func_end
== 0 || func_end
> pc
+ 64)
362 for (skip_pc
= pc
; skip_pc
< func_end
; skip_pc
+= 4)
364 inst
= read_memory_unsigned_integer (skip_pc
, 4);
366 /* "mov ip, sp" is no longer a required part of the prologue. */
367 if (inst
== 0xe1a0c00d) /* mov ip, sp */
370 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
373 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
376 /* Some prologues begin with "str lr, [sp, #-4]!". */
377 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
380 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
383 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
386 /* Any insns after this point may float into the code, if it makes
387 for better instruction scheduling, so we skip them only if we
388 find them, but still consider the function to be frame-ful. */
390 /* We may have either one sfmfd instruction here, or several stfe
391 insns, depending on the version of floating point code we
393 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
396 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
399 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
402 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
405 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
406 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
407 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
410 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
411 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
412 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
415 /* Un-recognized instruction; stop scanning. */
419 return skip_pc
; /* End of prologue */
423 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
424 This function decodes a Thumb function prologue to determine:
425 1) the size of the stack frame
426 2) which registers are saved on it
427 3) the offsets of saved regs
428 4) the offset from the stack pointer to the frame pointer
430 A typical Thumb function prologue would create this stack frame
431 (offsets relative to FP)
432 old SP -> 24 stack parameters
435 R7 -> 0 local variables (16 bytes)
436 SP -> -12 additional stack space (12 bytes)
437 The frame size would thus be 36 bytes, and the frame offset would be
438 12 bytes. The frame register is R7.
440 The comments for thumb_skip_prolog() describe the algorithm we use
441 to detect the end of the prolog. */
445 thumb_scan_prologue (CORE_ADDR prev_pc
, struct arm_prologue_cache
*cache
)
447 CORE_ADDR prologue_start
;
448 CORE_ADDR prologue_end
;
449 CORE_ADDR current_pc
;
450 /* Which register has been copied to register n? */
453 bit 0 - push { rlist }
454 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
455 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
460 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
462 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
464 if (sal
.line
== 0) /* no line info, use current PC */
465 prologue_end
= prev_pc
;
466 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
467 prologue_end
= sal
.end
; /* (probably means no prologue) */
470 /* We're in the boondocks: we have no idea where the start of the
474 prologue_end
= min (prologue_end
, prev_pc
);
476 /* Initialize the saved register map. When register H is copied to
477 register L, we will put H in saved_reg[L]. */
478 for (i
= 0; i
< 16; i
++)
481 /* Search the prologue looking for instructions that set up the
482 frame pointer, adjust the stack pointer, and save registers.
483 Do this until all basic prolog instructions are found. */
485 cache
->framesize
= 0;
486 for (current_pc
= prologue_start
;
487 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
494 insn
= read_memory_unsigned_integer (current_pc
, 2);
496 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
499 findmask
|= 1; /* push found */
500 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
501 whether to save LR (R14). */
502 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
504 /* Calculate offsets of saved R0-R7 and LR. */
505 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
506 if (mask
& (1 << regno
))
508 cache
->framesize
+= 4;
509 cache
->saved_regs
[saved_reg
[regno
]].addr
= -cache
->framesize
;
510 /* Reset saved register map. */
511 saved_reg
[regno
] = regno
;
514 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
517 if ((findmask
& 1) == 0) /* before push? */
520 findmask
|= 4; /* add/sub sp found */
522 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
523 if (insn
& 0x80) /* is it signed? (==subtracting) */
525 cache
->frameoffset
+= offset
;
528 cache
->framesize
-= offset
;
530 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
532 findmask
|= 2; /* setting of r7 found */
533 cache
->framereg
= THUMB_FP_REGNUM
;
534 /* get scaled offset */
535 cache
->frameoffset
= (insn
& 0xff) << 2;
537 else if (insn
== 0x466f) /* mov r7, sp */
539 findmask
|= 2; /* setting of r7 found */
540 cache
->framereg
= THUMB_FP_REGNUM
;
541 cache
->frameoffset
= 0;
542 saved_reg
[THUMB_FP_REGNUM
] = ARM_SP_REGNUM
;
544 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
546 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
547 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
548 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
551 /* Something in the prolog that we don't care about or some
552 instruction from outside the prolog scheduled here for
558 /* This function decodes an ARM function prologue to determine:
559 1) the size of the stack frame
560 2) which registers are saved on it
561 3) the offsets of saved regs
562 4) the offset from the stack pointer to the frame pointer
563 This information is stored in the "extra" fields of the frame_info.
565 There are two basic forms for the ARM prologue. The fixed argument
566 function call will look like:
569 stmfd sp!, {fp, ip, lr, pc}
573 Which would create this stack frame (offsets relative to FP):
574 IP -> 4 (caller's stack)
575 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
576 -4 LR (return address in caller)
577 -8 IP (copy of caller's SP)
579 SP -> -28 Local variables
581 The frame size would thus be 32 bytes, and the frame offset would be
582 28 bytes. The stmfd call can also save any of the vN registers it
583 plans to use, which increases the frame size accordingly.
585 Note: The stored PC is 8 off of the STMFD instruction that stored it
586 because the ARM Store instructions always store PC + 8 when you read
589 A variable argument function call will look like:
592 stmfd sp!, {a1, a2, a3, a4}
593 stmfd sp!, {fp, ip, lr, pc}
596 Which would create this stack frame (offsets relative to FP):
597 IP -> 20 (caller's stack)
602 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
603 -4 LR (return address in caller)
604 -8 IP (copy of caller's SP)
606 SP -> -28 Local variables
608 The frame size would thus be 48 bytes, and the frame offset would be
611 There is another potential complication, which is that the optimizer
612 will try to separate the store of fp in the "stmfd" instruction from
613 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
614 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
616 Also, note, the original version of the ARM toolchain claimed that there
619 instruction at the end of the prologue. I have never seen GCC produce
620 this, and the ARM docs don't mention it. We still test for it below in
626 arm_scan_prologue (struct frame_info
*next_frame
, struct arm_prologue_cache
*cache
)
628 int regno
, sp_offset
, fp_offset
, ip_offset
;
629 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
630 CORE_ADDR prev_pc
= frame_pc_unwind (next_frame
);
632 /* Assume there is no frame until proven otherwise. */
633 cache
->framereg
= ARM_SP_REGNUM
;
634 cache
->framesize
= 0;
635 cache
->frameoffset
= 0;
637 /* Check for Thumb prologue. */
638 if (arm_pc_is_thumb (prev_pc
))
640 thumb_scan_prologue (prev_pc
, cache
);
644 /* Find the function prologue. If we can't find the function in
645 the symbol table, peek in the stack frame to find the PC. */
646 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
648 /* One way to find the end of the prologue (which works well
649 for unoptimized code) is to do the following:
651 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
654 prologue_end = prev_pc;
655 else if (sal.end < prologue_end)
656 prologue_end = sal.end;
658 This mechanism is very accurate so long as the optimizer
659 doesn't move any instructions from the function body into the
660 prologue. If this happens, sal.end will be the last
661 instruction in the first hunk of prologue code just before
662 the first instruction that the scheduler has moved from
663 the body to the prologue.
665 In order to make sure that we scan all of the prologue
666 instructions, we use a slightly less accurate mechanism which
667 may scan more than necessary. To help compensate for this
668 lack of accuracy, the prologue scanning loop below contains
669 several clauses which'll cause the loop to terminate early if
670 an implausible prologue instruction is encountered.
676 is a suitable endpoint since it accounts for the largest
677 possible prologue plus up to five instructions inserted by
680 if (prologue_end
> prologue_start
+ 64)
682 prologue_end
= prologue_start
+ 64; /* See above. */
687 /* We have no symbol information. Our only option is to assume this
688 function has a standard stack frame and the normal frame register.
689 Then, we can find the value of our frame pointer on entrance to
690 the callee (or at the present moment if this is the innermost frame).
691 The value stored there should be the address of the stmfd + 8. */
693 LONGEST return_value
;
695 frame_loc
= frame_unwind_register_unsigned (next_frame
, ARM_FP_REGNUM
);
696 if (!safe_read_memory_integer (frame_loc
, 4, &return_value
))
700 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
701 prologue_end
= prologue_start
+ 64; /* See above. */
705 if (prev_pc
< prologue_end
)
706 prologue_end
= prev_pc
;
708 /* Now search the prologue looking for instructions that set up the
709 frame pointer, adjust the stack pointer, and save registers.
711 Be careful, however, and if it doesn't look like a prologue,
712 don't try to scan it. If, for instance, a frameless function
713 begins with stmfd sp!, then we will tell ourselves there is
714 a frame, which will confuse stack traceback, as well as "finish"
715 and other operations that rely on a knowledge of the stack
718 In the APCS, the prologue should start with "mov ip, sp" so
719 if we don't see this as the first insn, we will stop.
721 [Note: This doesn't seem to be true any longer, so it's now an
722 optional part of the prologue. - Kevin Buettner, 2001-11-20]
724 [Note further: The "mov ip,sp" only seems to be missing in
725 frameless functions at optimization level "-O2" or above,
726 in which case it is often (but not always) replaced by
727 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
729 sp_offset
= fp_offset
= ip_offset
= 0;
731 for (current_pc
= prologue_start
;
732 current_pc
< prologue_end
;
735 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
737 if (insn
== 0xe1a0c00d) /* mov ip, sp */
742 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
744 unsigned imm
= insn
& 0xff; /* immediate value */
745 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
746 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
750 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
752 unsigned imm
= insn
& 0xff; /* immediate value */
753 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
754 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
758 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
761 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= sp_offset
;
764 else if ((insn
& 0xffff0000) == 0xe92d0000)
765 /* stmfd sp!, {..., fp, ip, lr, pc}
767 stmfd sp!, {a1, a2, a3, a4} */
769 int mask
= insn
& 0xffff;
771 /* Calculate offsets of saved registers. */
772 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
773 if (mask
& (1 << regno
))
776 cache
->saved_regs
[regno
].addr
= sp_offset
;
779 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
780 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
781 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
783 /* No need to add this to saved_regs -- it's just an arg reg. */
786 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
787 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
788 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
790 /* No need to add this to saved_regs -- it's just an arg reg. */
793 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
795 unsigned imm
= insn
& 0xff; /* immediate value */
796 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
797 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
798 fp_offset
= -imm
+ ip_offset
;
799 cache
->framereg
= ARM_FP_REGNUM
;
801 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
803 unsigned imm
= insn
& 0xff; /* immediate value */
804 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
805 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
808 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
811 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
812 cache
->saved_regs
[regno
].addr
= sp_offset
;
814 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
817 unsigned int fp_start_reg
, fp_bound_reg
;
819 if ((insn
& 0x800) == 0x800) /* N0 is set */
821 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
828 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
834 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
835 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
836 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
839 cache
->saved_regs
[fp_start_reg
++].addr
= sp_offset
;
842 else if ((insn
& 0xf0000000) != 0xe0000000)
843 break; /* Condition not true, exit early */
844 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
845 break; /* Don't scan past a block load */
847 /* The optimizer might shove anything into the prologue,
848 so we just skip what we don't recognize. */
852 /* The frame size is just the negative of the offset (from the
853 original SP) of the last thing thing we pushed on the stack.
854 The frame offset is [new FP] - [new SP]. */
855 cache
->framesize
= -sp_offset
;
856 if (cache
->framereg
== ARM_FP_REGNUM
)
857 cache
->frameoffset
= fp_offset
- sp_offset
;
859 cache
->frameoffset
= 0;
862 static struct arm_prologue_cache
*
863 arm_make_prologue_cache (struct frame_info
*next_frame
)
866 struct arm_prologue_cache
*cache
;
867 CORE_ADDR unwound_fp
;
869 cache
= frame_obstack_zalloc (sizeof (struct arm_prologue_cache
));
870 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
872 arm_scan_prologue (next_frame
, cache
);
874 unwound_fp
= frame_unwind_register_unsigned (next_frame
, cache
->framereg
);
878 cache
->prev_sp
= unwound_fp
+ cache
->framesize
- cache
->frameoffset
;
880 /* Calculate actual addresses of saved registers using offsets
881 determined by arm_scan_prologue. */
882 for (reg
= 0; reg
< NUM_REGS
; reg
++)
883 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
884 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
889 /* Our frame ID for a normal frame is the current function's starting PC
890 and the caller's SP when we were called. */
893 arm_prologue_this_id (struct frame_info
*next_frame
,
895 struct frame_id
*this_id
)
897 struct arm_prologue_cache
*cache
;
901 if (*this_cache
== NULL
)
902 *this_cache
= arm_make_prologue_cache (next_frame
);
905 func
= frame_func_unwind (next_frame
);
907 /* This is meant to halt the backtrace at "_start". Make sure we
908 don't halt it at a generic dummy frame. */
909 if (func
<= LOWEST_PC
)
912 /* If we've hit a wall, stop. */
913 if (cache
->prev_sp
== 0)
916 id
= frame_id_build (cache
->prev_sp
, func
);
921 arm_prologue_prev_register (struct frame_info
*next_frame
,
925 enum lval_type
*lvalp
,
930 struct arm_prologue_cache
*cache
;
932 if (*this_cache
== NULL
)
933 *this_cache
= arm_make_prologue_cache (next_frame
);
936 /* If we are asked to unwind the PC, then we need to return the LR
937 instead. The saved value of PC points into this frame's
938 prologue, not the next frame's resume location. */
939 if (prev_regnum
== ARM_PC_REGNUM
)
940 prev_regnum
= ARM_LR_REGNUM
;
942 /* SP is generally not saved to the stack, but this frame is
943 identified by NEXT_FRAME's stack pointer at the time of the call.
944 The value was already reconstructed into PREV_SP. */
945 if (prev_regnum
== ARM_SP_REGNUM
)
949 store_unsigned_integer (valuep
, 4, cache
->prev_sp
);
953 trad_frame_get_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
954 optimized
, lvalp
, addrp
, realnump
, valuep
);
957 struct frame_unwind arm_prologue_unwind
= {
959 arm_prologue_this_id
,
960 arm_prologue_prev_register
963 static const struct frame_unwind
*
964 arm_prologue_unwind_sniffer (struct frame_info
*next_frame
)
966 return &arm_prologue_unwind
;
969 static struct arm_prologue_cache
*
970 arm_make_stub_cache (struct frame_info
*next_frame
)
973 struct arm_prologue_cache
*cache
;
974 CORE_ADDR unwound_fp
;
976 cache
= frame_obstack_zalloc (sizeof (struct arm_prologue_cache
));
977 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
979 cache
->prev_sp
= frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
);
984 /* Our frame ID for a stub frame is the current SP and LR. */
987 arm_stub_this_id (struct frame_info
*next_frame
,
989 struct frame_id
*this_id
)
991 struct arm_prologue_cache
*cache
;
993 if (*this_cache
== NULL
)
994 *this_cache
= arm_make_stub_cache (next_frame
);
997 *this_id
= frame_id_build (cache
->prev_sp
,
998 frame_pc_unwind (next_frame
));
1001 struct frame_unwind arm_stub_unwind
= {
1004 arm_prologue_prev_register
1007 static const struct frame_unwind
*
1008 arm_stub_unwind_sniffer (struct frame_info
*next_frame
)
1012 if (in_plt_section (frame_unwind_address_in_block (next_frame
), NULL
)
1013 || target_read_memory (frame_pc_unwind (next_frame
), dummy
, 4) != 0)
1014 return &arm_stub_unwind
;
1020 arm_normal_frame_base (struct frame_info
*next_frame
, void **this_cache
)
1022 struct arm_prologue_cache
*cache
;
1024 if (*this_cache
== NULL
)
1025 *this_cache
= arm_make_prologue_cache (next_frame
);
1026 cache
= *this_cache
;
1028 return cache
->prev_sp
+ cache
->frameoffset
- cache
->framesize
;
1031 struct frame_base arm_normal_base
= {
1032 &arm_prologue_unwind
,
1033 arm_normal_frame_base
,
1034 arm_normal_frame_base
,
1035 arm_normal_frame_base
1038 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1039 dummy frame. The frame ID's base needs to match the TOS value
1040 saved by save_dummy_frame_tos() and returned from
1041 arm_push_dummy_call, and the PC needs to match the dummy frame's
1044 static struct frame_id
1045 arm_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1047 return frame_id_build (frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
),
1048 frame_pc_unwind (next_frame
));
1051 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1052 be used to construct the previous frame's ID, after looking up the
1053 containing function). */
1056 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1059 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1060 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1064 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1066 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1069 /* When arguments must be pushed onto the stack, they go on in reverse
1070 order. The code below implements a FILO (stack) to do this. */
1075 struct stack_item
*prev
;
1079 static struct stack_item
*
1080 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1082 struct stack_item
*si
;
1083 si
= xmalloc (sizeof (struct stack_item
));
1084 si
->data
= xmalloc (len
);
1087 memcpy (si
->data
, contents
, len
);
1091 static struct stack_item
*
1092 pop_stack_item (struct stack_item
*si
)
1094 struct stack_item
*dead
= si
;
1102 /* Return the alignment (in bytes) of the given type. */
1105 arm_type_align (struct type
*t
)
1111 t
= check_typedef (t
);
1112 switch (TYPE_CODE (t
))
1115 /* Should never happen. */
1116 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1120 case TYPE_CODE_ENUM
:
1124 case TYPE_CODE_RANGE
:
1125 case TYPE_CODE_BITSTRING
:
1127 case TYPE_CODE_CHAR
:
1128 case TYPE_CODE_BOOL
:
1129 return TYPE_LENGTH (t
);
1131 case TYPE_CODE_ARRAY
:
1132 case TYPE_CODE_COMPLEX
:
1133 /* TODO: What about vector types? */
1134 return arm_type_align (TYPE_TARGET_TYPE (t
));
1136 case TYPE_CODE_STRUCT
:
1137 case TYPE_CODE_UNION
:
1139 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1141 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
1149 /* We currently only support passing parameters in integer registers. This
1150 conforms with GCC's default model. Several other variants exist and
1151 we should probably support some of them based on the selected ABI. */
1154 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1155 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1156 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1157 CORE_ADDR struct_addr
)
1162 struct stack_item
*si
= NULL
;
1164 /* Set the return address. For the ARM, the return breakpoint is
1165 always at BP_ADDR. */
1166 /* XXX Fix for Thumb. */
1167 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1169 /* Walk through the list of args and determine how large a temporary
1170 stack is required. Need to take care here as structs may be
1171 passed on the stack, and we have to to push them. */
1174 argreg
= ARM_A1_REGNUM
;
1177 /* The struct_return pointer occupies the first parameter
1178 passing register. */
1182 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = 0x%s\n",
1183 REGISTER_NAME (argreg
), paddr (struct_addr
));
1184 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1188 for (argnum
= 0; argnum
< nargs
; argnum
++)
1191 struct type
*arg_type
;
1192 struct type
*target_type
;
1193 enum type_code typecode
;
1197 arg_type
= check_typedef (value_type (args
[argnum
]));
1198 len
= TYPE_LENGTH (arg_type
);
1199 target_type
= TYPE_TARGET_TYPE (arg_type
);
1200 typecode
= TYPE_CODE (arg_type
);
1201 val
= value_contents_writeable (args
[argnum
]);
1203 align
= arm_type_align (arg_type
);
1204 /* Round alignment up to a whole number of words. */
1205 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
1206 /* Different ABIs have different maximum alignments. */
1207 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
1209 /* The APCS ABI only requires word alignment. */
1210 align
= INT_REGISTER_SIZE
;
1214 /* The AAPCS requires at most doubleword alignment. */
1215 if (align
> INT_REGISTER_SIZE
* 2)
1216 align
= INT_REGISTER_SIZE
* 2;
1219 /* Push stack padding for dowubleword alignment. */
1220 if (nstack
& (align
- 1))
1222 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1223 nstack
+= INT_REGISTER_SIZE
;
1226 /* Doubleword aligned quantities must go in even register pairs. */
1227 if (argreg
<= ARM_LAST_ARG_REGNUM
1228 && align
> INT_REGISTER_SIZE
1232 /* If the argument is a pointer to a function, and it is a
1233 Thumb function, create a LOCAL copy of the value and set
1234 the THUMB bit in it. */
1235 if (TYPE_CODE_PTR
== typecode
1236 && target_type
!= NULL
1237 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1239 CORE_ADDR regval
= extract_unsigned_integer (val
, len
);
1240 if (arm_pc_is_thumb (regval
))
1243 store_unsigned_integer (val
, len
, MAKE_THUMB_ADDR (regval
));
1247 /* Copy the argument to general registers or the stack in
1248 register-sized pieces. Large arguments are split between
1249 registers and stack. */
1252 int partial_len
= len
< DEPRECATED_REGISTER_SIZE
? len
: DEPRECATED_REGISTER_SIZE
;
1254 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1256 /* The argument is being passed in a general purpose
1258 CORE_ADDR regval
= extract_unsigned_integer (val
, partial_len
);
1260 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1261 argnum
, REGISTER_NAME (argreg
),
1262 phex (regval
, DEPRECATED_REGISTER_SIZE
));
1263 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1268 /* Push the arguments onto the stack. */
1270 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1272 si
= push_stack_item (si
, val
, DEPRECATED_REGISTER_SIZE
);
1273 nstack
+= DEPRECATED_REGISTER_SIZE
;
1280 /* If we have an odd number of words to push, then decrement the stack
1281 by one word now, so first stack argument will be dword aligned. */
1288 write_memory (sp
, si
->data
, si
->len
);
1289 si
= pop_stack_item (si
);
1292 /* Finally, update teh SP register. */
1293 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1299 /* Always align the frame to an 8-byte boundary. This is required on
1300 some platforms and harmless on the rest. */
1303 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1305 /* Align the stack to eight bytes. */
1306 return sp
& ~ (CORE_ADDR
) 7;
1310 print_fpu_flags (int flags
)
1312 if (flags
& (1 << 0))
1313 fputs ("IVO ", stdout
);
1314 if (flags
& (1 << 1))
1315 fputs ("DVZ ", stdout
);
1316 if (flags
& (1 << 2))
1317 fputs ("OFL ", stdout
);
1318 if (flags
& (1 << 3))
1319 fputs ("UFL ", stdout
);
1320 if (flags
& (1 << 4))
1321 fputs ("INX ", stdout
);
1325 /* Print interesting information about the floating point processor
1326 (if present) or emulator. */
1328 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1329 struct frame_info
*frame
, const char *args
)
1331 unsigned long status
= read_register (ARM_FPS_REGNUM
);
1334 type
= (status
>> 24) & 127;
1335 if (status
& (1 << 31))
1336 printf (_("Hardware FPU type %d\n"), type
);
1338 printf (_("Software FPU type %d\n"), type
);
1339 /* i18n: [floating point unit] mask */
1340 fputs (_("mask: "), stdout
);
1341 print_fpu_flags (status
>> 16);
1342 /* i18n: [floating point unit] flags */
1343 fputs (_("flags: "), stdout
);
1344 print_fpu_flags (status
);
1347 /* Return the GDB type object for the "standard" data type of data in
1350 static struct type
*
1351 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
1353 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1355 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1356 return builtin_type_arm_ext_big
;
1358 return builtin_type_arm_ext_littlebyte_bigword
;
1360 else if (regnum
== ARM_SP_REGNUM
)
1361 return builtin_type_void_data_ptr
;
1362 else if (regnum
== ARM_PC_REGNUM
)
1363 return builtin_type_void_func_ptr
;
1365 return builtin_type_uint32
;
1368 /* Index within `registers' of the first byte of the space for
1372 arm_register_byte (int regnum
)
1374 if (regnum
< ARM_F0_REGNUM
)
1375 return regnum
* INT_REGISTER_SIZE
;
1376 else if (regnum
< ARM_PS_REGNUM
)
1377 return (NUM_GREGS
* INT_REGISTER_SIZE
1378 + (regnum
- ARM_F0_REGNUM
) * FP_REGISTER_SIZE
);
1380 return (NUM_GREGS
* INT_REGISTER_SIZE
1381 + NUM_FREGS
* FP_REGISTER_SIZE
1382 + (regnum
- ARM_FPS_REGNUM
) * STATUS_REGISTER_SIZE
);
1385 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1387 arm_register_sim_regno (int regnum
)
1390 gdb_assert (reg
>= 0 && reg
< NUM_REGS
);
1392 if (reg
< NUM_GREGS
)
1393 return SIM_ARM_R0_REGNUM
+ reg
;
1396 if (reg
< NUM_FREGS
)
1397 return SIM_ARM_FP0_REGNUM
+ reg
;
1400 if (reg
< NUM_SREGS
)
1401 return SIM_ARM_FPS_REGNUM
+ reg
;
1404 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
1407 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1408 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1409 It is thought that this is is the floating-point register format on
1410 little-endian systems. */
1413 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
1417 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1418 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1420 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1422 floatformat_from_doublest (fmt
, &d
, dbl
);
1426 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
)
1429 floatformat_to_doublest (fmt
, ptr
, &d
);
1430 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1431 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1433 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1438 condition_true (unsigned long cond
, unsigned long status_reg
)
1440 if (cond
== INST_AL
|| cond
== INST_NV
)
1446 return ((status_reg
& FLAG_Z
) != 0);
1448 return ((status_reg
& FLAG_Z
) == 0);
1450 return ((status_reg
& FLAG_C
) != 0);
1452 return ((status_reg
& FLAG_C
) == 0);
1454 return ((status_reg
& FLAG_N
) != 0);
1456 return ((status_reg
& FLAG_N
) == 0);
1458 return ((status_reg
& FLAG_V
) != 0);
1460 return ((status_reg
& FLAG_V
) == 0);
1462 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1464 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1466 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1468 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1470 return (((status_reg
& FLAG_Z
) == 0) &&
1471 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1473 return (((status_reg
& FLAG_Z
) != 0) ||
1474 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1479 /* Support routines for single stepping. Calculate the next PC value. */
1480 #define submask(x) ((1L << ((x) + 1)) - 1)
1481 #define bit(obj,st) (((obj) >> (st)) & 1)
1482 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1483 #define sbits(obj,st,fn) \
1484 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1485 #define BranchDest(addr,instr) \
1486 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1489 static unsigned long
1490 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1491 unsigned long status_reg
)
1493 unsigned long res
, shift
;
1494 int rm
= bits (inst
, 0, 3);
1495 unsigned long shifttype
= bits (inst
, 5, 6);
1499 int rs
= bits (inst
, 8, 11);
1500 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1503 shift
= bits (inst
, 7, 11);
1506 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1507 + (bit (inst
, 4) ? 12 : 8))
1508 : read_register (rm
));
1513 res
= shift
>= 32 ? 0 : res
<< shift
;
1517 res
= shift
>= 32 ? 0 : res
>> shift
;
1523 res
= ((res
& 0x80000000L
)
1524 ? ~((~res
) >> shift
) : res
>> shift
);
1527 case 3: /* ROR/RRX */
1530 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1532 res
= (res
>> shift
) | (res
<< (32 - shift
));
1536 return res
& 0xffffffff;
1539 /* Return number of 1-bits in VAL. */
1542 bitcount (unsigned long val
)
1545 for (nbits
= 0; val
!= 0; nbits
++)
1546 val
&= val
- 1; /* delete rightmost 1-bit in val */
1551 thumb_get_next_pc (CORE_ADDR pc
)
1553 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1554 unsigned short inst1
= read_memory_unsigned_integer (pc
, 2);
1555 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1556 unsigned long offset
;
1558 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1562 /* Fetch the saved PC from the stack. It's stored above
1563 all of the other registers. */
1564 offset
= bitcount (bits (inst1
, 0, 7)) * DEPRECATED_REGISTER_SIZE
;
1565 sp
= read_register (ARM_SP_REGNUM
);
1566 nextpc
= (CORE_ADDR
) read_memory_unsigned_integer (sp
+ offset
, 4);
1567 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1569 error (_("Infinite loop detected"));
1571 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1573 unsigned long status
= read_register (ARM_PS_REGNUM
);
1574 unsigned long cond
= bits (inst1
, 8, 11);
1575 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1576 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1578 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1580 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1582 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link, and blx */
1584 unsigned short inst2
= read_memory_unsigned_integer (pc
+ 2, 2);
1585 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1586 nextpc
= pc_val
+ offset
;
1587 /* For BLX make sure to clear the low bits. */
1588 if (bits (inst2
, 11, 12) == 1)
1589 nextpc
= nextpc
& 0xfffffffc;
1591 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
1593 if (bits (inst1
, 3, 6) == 0x0f)
1596 nextpc
= read_register (bits (inst1
, 3, 6));
1598 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1600 error (_("Infinite loop detected"));
1607 arm_get_next_pc (CORE_ADDR pc
)
1609 unsigned long pc_val
;
1610 unsigned long this_instr
;
1611 unsigned long status
;
1614 if (arm_pc_is_thumb (pc
))
1615 return thumb_get_next_pc (pc
);
1617 pc_val
= (unsigned long) pc
;
1618 this_instr
= read_memory_unsigned_integer (pc
, 4);
1619 status
= read_register (ARM_PS_REGNUM
);
1620 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1622 if (condition_true (bits (this_instr
, 28, 31), status
))
1624 switch (bits (this_instr
, 24, 27))
1627 case 0x1: /* data processing */
1631 unsigned long operand1
, operand2
, result
= 0;
1635 if (bits (this_instr
, 12, 15) != 15)
1638 if (bits (this_instr
, 22, 25) == 0
1639 && bits (this_instr
, 4, 7) == 9) /* multiply */
1640 error (_("Invalid update to pc in instruction"));
1642 /* BX <reg>, BLX <reg> */
1643 if (bits (this_instr
, 4, 28) == 0x12fff1
1644 || bits (this_instr
, 4, 28) == 0x12fff3)
1646 rn
= bits (this_instr
, 0, 3);
1647 result
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1648 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1651 error (_("Infinite loop detected"));
1656 /* Multiply into PC */
1657 c
= (status
& FLAG_C
) ? 1 : 0;
1658 rn
= bits (this_instr
, 16, 19);
1659 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1661 if (bit (this_instr
, 25))
1663 unsigned long immval
= bits (this_instr
, 0, 7);
1664 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1665 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1668 else /* operand 2 is a shifted register */
1669 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1671 switch (bits (this_instr
, 21, 24))
1674 result
= operand1
& operand2
;
1678 result
= operand1
^ operand2
;
1682 result
= operand1
- operand2
;
1686 result
= operand2
- operand1
;
1690 result
= operand1
+ operand2
;
1694 result
= operand1
+ operand2
+ c
;
1698 result
= operand1
- operand2
+ c
;
1702 result
= operand2
- operand1
+ c
;
1708 case 0xb: /* tst, teq, cmp, cmn */
1709 result
= (unsigned long) nextpc
;
1713 result
= operand1
| operand2
;
1717 /* Always step into a function. */
1722 result
= operand1
& ~operand2
;
1729 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1732 error (_("Infinite loop detected"));
1737 case 0x5: /* data transfer */
1740 if (bit (this_instr
, 20))
1743 if (bits (this_instr
, 12, 15) == 15)
1749 if (bit (this_instr
, 22))
1750 error (_("Invalid update to pc in instruction"));
1752 /* byte write to PC */
1753 rn
= bits (this_instr
, 16, 19);
1754 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1755 if (bit (this_instr
, 24))
1758 int c
= (status
& FLAG_C
) ? 1 : 0;
1759 unsigned long offset
=
1760 (bit (this_instr
, 25)
1761 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1762 : bits (this_instr
, 0, 11));
1764 if (bit (this_instr
, 23))
1769 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1772 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1775 error (_("Infinite loop detected"));
1781 case 0x9: /* block transfer */
1782 if (bit (this_instr
, 20))
1785 if (bit (this_instr
, 15))
1790 if (bit (this_instr
, 23))
1793 unsigned long reglist
= bits (this_instr
, 0, 14);
1794 offset
= bitcount (reglist
) * 4;
1795 if (bit (this_instr
, 24)) /* pre */
1798 else if (bit (this_instr
, 24))
1802 unsigned long rn_val
=
1803 read_register (bits (this_instr
, 16, 19));
1805 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1809 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1811 error (_("Infinite loop detected"));
1816 case 0xb: /* branch & link */
1817 case 0xa: /* branch */
1819 nextpc
= BranchDest (pc
, this_instr
);
1822 if (bits (this_instr
, 28, 31) == INST_NV
)
1823 nextpc
|= bit (this_instr
, 24) << 1;
1825 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1827 error (_("Infinite loop detected"));
1833 case 0xe: /* coproc ops */
1838 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
1846 /* single_step() is called just before we want to resume the inferior,
1847 if we want to single-step it but there is no hardware or kernel
1848 single-step support. We find the target of the coming instruction
1851 single_step() is also called just after the inferior stops. If we
1852 had set up a simulated single-step, we undo our damage. */
1855 arm_software_single_step (enum target_signal sig
, int insert_bpt
)
1857 /* NOTE: This may insert the wrong breakpoint instruction when
1858 single-stepping over a mode-changing instruction, if the
1859 CPSR heuristics are used. */
1863 CORE_ADDR next_pc
= arm_get_next_pc (read_register (ARM_PC_REGNUM
));
1865 insert_single_step_breakpoint (next_pc
);
1868 remove_single_step_breakpoints ();
1871 #include "bfd-in2.h"
1872 #include "libcoff.h"
1875 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
1877 if (arm_pc_is_thumb (memaddr
))
1879 static asymbol
*asym
;
1880 static combined_entry_type ce
;
1881 static struct coff_symbol_struct csym
;
1882 static struct bfd fake_bfd
;
1883 static bfd_target fake_target
;
1885 if (csym
.native
== NULL
)
1887 /* Create a fake symbol vector containing a Thumb symbol.
1888 This is solely so that the code in print_insn_little_arm()
1889 and print_insn_big_arm() in opcodes/arm-dis.c will detect
1890 the presence of a Thumb symbol and switch to decoding
1891 Thumb instructions. */
1893 fake_target
.flavour
= bfd_target_coff_flavour
;
1894 fake_bfd
.xvec
= &fake_target
;
1895 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
1897 csym
.symbol
.the_bfd
= &fake_bfd
;
1898 csym
.symbol
.name
= "fake";
1899 asym
= (asymbol
*) & csym
;
1902 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
1903 info
->symbols
= &asym
;
1906 info
->symbols
= NULL
;
1908 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1909 return print_insn_big_arm (memaddr
, info
);
1911 return print_insn_little_arm (memaddr
, info
);
1914 /* The following define instruction sequences that will cause ARM
1915 cpu's to take an undefined instruction trap. These are used to
1916 signal a breakpoint to GDB.
1918 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
1919 modes. A different instruction is required for each mode. The ARM
1920 cpu's can also be big or little endian. Thus four different
1921 instructions are needed to support all cases.
1923 Note: ARMv4 defines several new instructions that will take the
1924 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
1925 not in fact add the new instructions. The new undefined
1926 instructions in ARMv4 are all instructions that had no defined
1927 behaviour in earlier chips. There is no guarantee that they will
1928 raise an exception, but may be treated as NOP's. In practice, it
1929 may only safe to rely on instructions matching:
1931 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1932 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1933 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
1935 Even this may only true if the condition predicate is true. The
1936 following use a condition predicate of ALWAYS so it is always TRUE.
1938 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
1939 and NetBSD all use a software interrupt rather than an undefined
1940 instruction to force a trap. This can be handled by by the
1941 abi-specific code during establishment of the gdbarch vector. */
1944 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
1945 override these definitions. */
1946 #ifndef ARM_LE_BREAKPOINT
1947 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
1949 #ifndef ARM_BE_BREAKPOINT
1950 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
1952 #ifndef THUMB_LE_BREAKPOINT
1953 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
1955 #ifndef THUMB_BE_BREAKPOINT
1956 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
1959 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
1960 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
1961 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
1962 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
1964 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
1965 the program counter value to determine whether a 16-bit or 32-bit
1966 breakpoint should be used. It returns a pointer to a string of
1967 bytes that encode a breakpoint instruction, stores the length of
1968 the string to *lenptr, and adjusts the program counter (if
1969 necessary) to point to the actual memory location where the
1970 breakpoint should be inserted. */
1972 static const unsigned char *
1973 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1975 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1977 if (arm_pc_is_thumb (*pcptr
))
1979 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1980 *lenptr
= tdep
->thumb_breakpoint_size
;
1981 return tdep
->thumb_breakpoint
;
1985 *lenptr
= tdep
->arm_breakpoint_size
;
1986 return tdep
->arm_breakpoint
;
1990 /* Extract from an array REGBUF containing the (raw) register state a
1991 function return value of type TYPE, and copy that, in virtual
1992 format, into VALBUF. */
1995 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
1998 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2000 switch (gdbarch_tdep (current_gdbarch
)->fp_model
)
2004 /* The value is in register F0 in internal format. We need to
2005 extract the raw value and then convert it to the desired
2007 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
2009 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
2010 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
2015 case ARM_FLOAT_SOFT_FPA
:
2016 case ARM_FLOAT_SOFT_VFP
:
2017 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
2018 if (TYPE_LENGTH (type
) > 4)
2019 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
2020 valbuf
+ INT_REGISTER_SIZE
);
2025 (__FILE__
, __LINE__
,
2026 _("arm_extract_return_value: Floating point model not supported"));
2030 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2031 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2032 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2033 || TYPE_CODE (type
) == TYPE_CODE_PTR
2034 || TYPE_CODE (type
) == TYPE_CODE_REF
2035 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2037 /* If the the type is a plain integer, then the access is
2038 straight-forward. Otherwise we have to play around a bit more. */
2039 int len
= TYPE_LENGTH (type
);
2040 int regno
= ARM_A1_REGNUM
;
2045 /* By using store_unsigned_integer we avoid having to do
2046 anything special for small big-endian values. */
2047 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2048 store_unsigned_integer (valbuf
,
2049 (len
> INT_REGISTER_SIZE
2050 ? INT_REGISTER_SIZE
: len
),
2052 len
-= INT_REGISTER_SIZE
;
2053 valbuf
+= INT_REGISTER_SIZE
;
2058 /* For a structure or union the behaviour is as if the value had
2059 been stored to word-aligned memory and then loaded into
2060 registers with 32-bit load instruction(s). */
2061 int len
= TYPE_LENGTH (type
);
2062 int regno
= ARM_A1_REGNUM
;
2063 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2067 regcache_cooked_read (regs
, regno
++, tmpbuf
);
2068 memcpy (valbuf
, tmpbuf
,
2069 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2070 len
-= INT_REGISTER_SIZE
;
2071 valbuf
+= INT_REGISTER_SIZE
;
2077 /* Will a function return an aggregate type in memory or in a
2078 register? Return 0 if an aggregate type can be returned in a
2079 register, 1 if it must be returned in memory. */
2082 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2085 enum type_code code
;
2087 CHECK_TYPEDEF (type
);
2089 /* In the ARM ABI, "integer" like aggregate types are returned in
2090 registers. For an aggregate type to be integer like, its size
2091 must be less than or equal to DEPRECATED_REGISTER_SIZE and the
2092 offset of each addressable subfield must be zero. Note that bit
2093 fields are not addressable, and all addressable subfields of
2094 unions always start at offset zero.
2096 This function is based on the behaviour of GCC 2.95.1.
2097 See: gcc/arm.c: arm_return_in_memory() for details.
2099 Note: All versions of GCC before GCC 2.95.2 do not set up the
2100 parameters correctly for a function returning the following
2101 structure: struct { float f;}; This should be returned in memory,
2102 not a register. Richard Earnshaw sent me a patch, but I do not
2103 know of any way to detect if a function like the above has been
2104 compiled with the correct calling convention. */
2106 /* All aggregate types that won't fit in a register must be returned
2108 if (TYPE_LENGTH (type
) > DEPRECATED_REGISTER_SIZE
)
2113 /* The AAPCS says all aggregates not larger than a word are returned
2115 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
2118 /* The only aggregate types that can be returned in a register are
2119 structs and unions. Arrays must be returned in memory. */
2120 code
= TYPE_CODE (type
);
2121 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2126 /* Assume all other aggregate types can be returned in a register.
2127 Run a check for structures, unions and arrays. */
2130 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2133 /* Need to check if this struct/union is "integer" like. For
2134 this to be true, its size must be less than or equal to
2135 DEPRECATED_REGISTER_SIZE and the offset of each addressable
2136 subfield must be zero. Note that bit fields are not
2137 addressable, and unions always start at offset zero. If any
2138 of the subfields is a floating point type, the struct/union
2139 cannot be an integer type. */
2141 /* For each field in the object, check:
2142 1) Is it FP? --> yes, nRc = 1;
2143 2) Is it addressable (bitpos != 0) and
2144 not packed (bitsize == 0)?
2148 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2150 enum type_code field_type_code
;
2151 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, i
)));
2153 /* Is it a floating point type field? */
2154 if (field_type_code
== TYPE_CODE_FLT
)
2160 /* If bitpos != 0, then we have to care about it. */
2161 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2163 /* Bitfields are not addressable. If the field bitsize is
2164 zero, then the field is not packed. Hence it cannot be
2165 a bitfield or any other packed type. */
2166 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2178 /* Write into appropriate registers a function return value of type
2179 TYPE, given in virtual format. */
2182 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
2183 const gdb_byte
*valbuf
)
2185 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2187 char buf
[MAX_REGISTER_SIZE
];
2189 switch (gdbarch_tdep (current_gdbarch
)->fp_model
)
2193 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
);
2194 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
2197 case ARM_FLOAT_SOFT_FPA
:
2198 case ARM_FLOAT_SOFT_VFP
:
2199 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
2200 if (TYPE_LENGTH (type
) > 4)
2201 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
2202 valbuf
+ INT_REGISTER_SIZE
);
2207 (__FILE__
, __LINE__
,
2208 _("arm_store_return_value: Floating point model not supported"));
2212 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2213 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2214 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2215 || TYPE_CODE (type
) == TYPE_CODE_PTR
2216 || TYPE_CODE (type
) == TYPE_CODE_REF
2217 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2219 if (TYPE_LENGTH (type
) <= 4)
2221 /* Values of one word or less are zero/sign-extended and
2223 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2224 LONGEST val
= unpack_long (type
, valbuf
);
2226 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, val
);
2227 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
2231 /* Integral values greater than one word are stored in consecutive
2232 registers starting with r0. This will always be a multiple of
2233 the regiser size. */
2234 int len
= TYPE_LENGTH (type
);
2235 int regno
= ARM_A1_REGNUM
;
2239 regcache_cooked_write (regs
, regno
++, valbuf
);
2240 len
-= INT_REGISTER_SIZE
;
2241 valbuf
+= INT_REGISTER_SIZE
;
2247 /* For a structure or union the behaviour is as if the value had
2248 been stored to word-aligned memory and then loaded into
2249 registers with 32-bit load instruction(s). */
2250 int len
= TYPE_LENGTH (type
);
2251 int regno
= ARM_A1_REGNUM
;
2252 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2256 memcpy (tmpbuf
, valbuf
,
2257 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2258 regcache_cooked_write (regs
, regno
++, tmpbuf
);
2259 len
-= INT_REGISTER_SIZE
;
2260 valbuf
+= INT_REGISTER_SIZE
;
2266 /* Handle function return values. */
2268 static enum return_value_convention
2269 arm_return_value (struct gdbarch
*gdbarch
, struct type
*valtype
,
2270 struct regcache
*regcache
, gdb_byte
*readbuf
,
2271 const gdb_byte
*writebuf
)
2273 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2274 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2275 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2277 if (arm_return_in_memory (gdbarch
, valtype
))
2278 return RETURN_VALUE_STRUCT_CONVENTION
;
2282 arm_store_return_value (valtype
, regcache
, writebuf
);
2285 arm_extract_return_value (valtype
, regcache
, readbuf
);
2287 return RETURN_VALUE_REGISTER_CONVENTION
;
2292 arm_get_longjmp_target (CORE_ADDR
*pc
)
2295 char buf
[INT_REGISTER_SIZE
];
2296 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2298 jb_addr
= read_register (ARM_A1_REGNUM
);
2300 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2304 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
);
2308 /* Return non-zero if the PC is inside a thumb call thunk. */
2311 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2313 CORE_ADDR start_addr
;
2315 /* Find the starting address of the function containing the PC. If
2316 the caller didn't give us a name, look it up at the same time. */
2317 if (0 == find_pc_partial_function (pc
, name
? NULL
: &name
,
2321 return strncmp (name
, "_call_via_r", 11) == 0;
2324 /* If PC is in a Thumb call or return stub, return the address of the
2325 target PC, which is in a register. The thunk functions are called
2326 _called_via_xx, where x is the register name. The possible names
2327 are r0-r9, sl, fp, ip, sp, and lr. */
2330 arm_skip_stub (CORE_ADDR pc
)
2333 CORE_ADDR start_addr
;
2335 /* Find the starting address and name of the function containing the PC. */
2336 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2339 /* Call thunks always start with "_call_via_". */
2340 if (strncmp (name
, "_call_via_", 10) == 0)
2342 /* Use the name suffix to determine which register contains the
2344 static char *table
[15] =
2345 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2346 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2350 for (regno
= 0; regno
<= 14; regno
++)
2351 if (strcmp (&name
[10], table
[regno
]) == 0)
2352 return read_register (regno
);
2355 return 0; /* not a stub */
2359 set_arm_command (char *args
, int from_tty
)
2361 printf_unfiltered (_("\
2362 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2363 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
2367 show_arm_command (char *args
, int from_tty
)
2369 cmd_show_list (showarmcmdlist
, from_tty
, "");
2373 arm_update_current_architecture (void)
2375 struct gdbarch_info info
;
2377 /* If the current architecture is not ARM, we have nothing to do. */
2378 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_arm
)
2381 /* Update the architecture. */
2382 gdbarch_info_init (&info
);
2384 if (!gdbarch_update_p (info
))
2385 internal_error (__FILE__
, __LINE__
, "could not update architecture");
2389 set_fp_model_sfunc (char *args
, int from_tty
,
2390 struct cmd_list_element
*c
)
2392 enum arm_float_model fp_model
;
2394 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
2395 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
2397 arm_fp_model
= fp_model
;
2401 if (fp_model
== ARM_FLOAT_LAST
)
2402 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
2405 arm_update_current_architecture ();
2409 show_fp_model (struct ui_file
*file
, int from_tty
,
2410 struct cmd_list_element
*c
, const char *value
)
2412 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2414 if (arm_fp_model
== ARM_FLOAT_AUTO
2415 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2416 fprintf_filtered (file
, _("\
2417 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2418 fp_model_strings
[tdep
->fp_model
]);
2420 fprintf_filtered (file
, _("\
2421 The current ARM floating point model is \"%s\".\n"),
2422 fp_model_strings
[arm_fp_model
]);
2426 arm_set_abi (char *args
, int from_tty
,
2427 struct cmd_list_element
*c
)
2429 enum arm_abi_kind arm_abi
;
2431 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
2432 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
2434 arm_abi_global
= arm_abi
;
2438 if (arm_abi
== ARM_ABI_LAST
)
2439 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
2442 arm_update_current_architecture ();
2446 arm_show_abi (struct ui_file
*file
, int from_tty
,
2447 struct cmd_list_element
*c
, const char *value
)
2449 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2451 if (arm_abi_global
== ARM_ABI_AUTO
2452 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2453 fprintf_filtered (file
, _("\
2454 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2455 arm_abi_strings
[tdep
->arm_abi
]);
2457 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
2461 /* If the user changes the register disassembly style used for info
2462 register and other commands, we have to also switch the style used
2463 in opcodes for disassembly output. This function is run in the "set
2464 arm disassembly" command, and does that. */
2467 set_disassembly_style_sfunc (char *args
, int from_tty
,
2468 struct cmd_list_element
*c
)
2470 set_disassembly_style ();
2473 /* Return the ARM register name corresponding to register I. */
2475 arm_register_name (int i
)
2477 return arm_register_names
[i
];
2481 set_disassembly_style (void)
2483 const char *setname
, *setdesc
, *const *regnames
;
2486 /* Find the style that the user wants in the opcodes table. */
2488 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2489 while ((disassembly_style
!= setname
)
2490 && (current
< num_disassembly_options
))
2491 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2492 current_option
= current
;
2494 /* Fill our copy. */
2495 for (j
= 0; j
< numregs
; j
++)
2496 arm_register_names
[j
] = (char *) regnames
[j
];
2499 if (isupper (*regnames
[ARM_PC_REGNUM
]))
2501 arm_register_names
[ARM_FPS_REGNUM
] = "FPS";
2502 arm_register_names
[ARM_PS_REGNUM
] = "CPSR";
2506 arm_register_names
[ARM_FPS_REGNUM
] = "fps";
2507 arm_register_names
[ARM_PS_REGNUM
] = "cpsr";
2510 /* Synchronize the disassembler. */
2511 set_arm_regname_option (current
);
2514 /* Test whether the coff symbol specific value corresponds to a Thumb
2518 coff_sym_is_thumb (int val
)
2520 return (val
== C_THUMBEXT
||
2521 val
== C_THUMBSTAT
||
2522 val
== C_THUMBEXTFUNC
||
2523 val
== C_THUMBSTATFUNC
||
2524 val
== C_THUMBLABEL
);
2527 /* arm_coff_make_msymbol_special()
2528 arm_elf_make_msymbol_special()
2530 These functions test whether the COFF or ELF symbol corresponds to
2531 an address in thumb code, and set a "special" bit in a minimal
2532 symbol to indicate that it does. */
2535 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2537 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2539 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2541 MSYMBOL_SET_SPECIAL (msym
);
2545 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2547 if (coff_sym_is_thumb (val
))
2548 MSYMBOL_SET_SPECIAL (msym
);
2552 arm_write_pc (CORE_ADDR pc
, ptid_t ptid
)
2554 write_register_pid (ARM_PC_REGNUM
, pc
, ptid
);
2556 /* If necessary, set the T bit. */
2559 CORE_ADDR val
= read_register_pid (ARM_PS_REGNUM
, ptid
);
2560 if (arm_pc_is_thumb (pc
))
2561 write_register_pid (ARM_PS_REGNUM
, val
| 0x20, ptid
);
2563 write_register_pid (ARM_PS_REGNUM
, val
& ~(CORE_ADDR
) 0x20, ptid
);
2567 static enum gdb_osabi
2568 arm_elf_osabi_sniffer (bfd
*abfd
)
2570 unsigned int elfosabi
;
2571 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2573 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2575 if (elfosabi
== ELFOSABI_ARM
)
2576 /* GNU tools use this value. Check note sections in this case,
2578 bfd_map_over_sections (abfd
,
2579 generic_elf_osabi_sniff_abi_tag_sections
,
2582 /* Anything else will be handled by the generic ELF sniffer. */
2587 /* Initialize the current architecture based on INFO. If possible,
2588 re-use an architecture from ARCHES, which is a list of
2589 architectures already created during this debugging session.
2591 Called e.g. at program startup, when reading a core file, and when
2592 reading a binary file. */
2594 static struct gdbarch
*
2595 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2597 struct gdbarch_tdep
*tdep
;
2598 struct gdbarch
*gdbarch
;
2599 struct gdbarch_list
*best_arch
;
2600 enum arm_abi_kind arm_abi
= arm_abi_global
;
2601 enum arm_float_model fp_model
= arm_fp_model
;
2603 /* If we have an object to base this architecture on, try to determine
2606 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
2610 switch (bfd_get_flavour (info
.abfd
))
2612 case bfd_target_aout_flavour
:
2613 /* Assume it's an old APCS-style ABI. */
2614 arm_abi
= ARM_ABI_APCS
;
2617 case bfd_target_coff_flavour
:
2618 /* Assume it's an old APCS-style ABI. */
2620 arm_abi
= ARM_ABI_APCS
;
2623 case bfd_target_elf_flavour
:
2624 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
2625 if (ei_osabi
== ELFOSABI_ARM
)
2627 /* GNU tools used to use this value, but do not for EABI
2628 objects. There's nowhere to tag an EABI version anyway,
2630 arm_abi
= ARM_ABI_APCS
;
2632 else if (ei_osabi
== ELFOSABI_NONE
)
2634 int e_flags
, eabi_ver
;
2636 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2637 eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
2641 case EF_ARM_EABI_UNKNOWN
:
2642 /* Assume GNU tools. */
2643 arm_abi
= ARM_ABI_APCS
;
2646 case EF_ARM_EABI_VER4
:
2647 arm_abi
= ARM_ABI_AAPCS
;
2648 /* EABI binaries default to VFP float ordering. */
2649 if (fp_model
== ARM_FLOAT_AUTO
)
2650 fp_model
= ARM_FLOAT_SOFT_VFP
;
2654 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
2655 arm_abi
= ARM_ABI_APCS
;
2662 /* Leave it as "auto". */
2667 /* Now that we have inferred any architecture settings that we
2668 can, try to inherit from the last ARM ABI. */
2671 if (arm_abi
== ARM_ABI_AUTO
)
2672 arm_abi
= gdbarch_tdep (arches
->gdbarch
)->arm_abi
;
2674 if (fp_model
== ARM_FLOAT_AUTO
)
2675 fp_model
= gdbarch_tdep (arches
->gdbarch
)->fp_model
;
2679 /* There was no prior ARM architecture; fill in default values. */
2681 if (arm_abi
== ARM_ABI_AUTO
)
2682 arm_abi
= ARM_ABI_APCS
;
2684 /* We used to default to FPA for generic ARM, but almost nobody
2685 uses that now, and we now provide a way for the user to force
2686 the model. So default to the most useful variant. */
2687 if (fp_model
== ARM_FLOAT_AUTO
)
2688 fp_model
= ARM_FLOAT_SOFT_FPA
;
2691 /* If there is already a candidate, use it. */
2692 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
2694 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
2696 if (arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
2699 if (fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
2702 /* Found a match. */
2706 if (best_arch
!= NULL
)
2707 return best_arch
->gdbarch
;
2709 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
2710 gdbarch
= gdbarch_alloc (&info
, tdep
);
2712 /* Record additional information about the architecture we are defining.
2713 These are gdbarch discriminators, like the OSABI. */
2714 tdep
->arm_abi
= arm_abi
;
2715 tdep
->fp_model
= fp_model
;
2718 switch (info
.byte_order
)
2720 case BFD_ENDIAN_BIG
:
2721 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
2722 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
2723 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
2724 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
2728 case BFD_ENDIAN_LITTLE
:
2729 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
2730 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
2731 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
2732 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
2737 internal_error (__FILE__
, __LINE__
,
2738 _("arm_gdbarch_init: bad byte order for float format"));
2741 /* On ARM targets char defaults to unsigned. */
2742 set_gdbarch_char_signed (gdbarch
, 0);
2744 /* This should be low enough for everything. */
2745 tdep
->lowest_pc
= 0x20;
2746 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
2748 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
2749 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
2751 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
2753 /* Frame handling. */
2754 set_gdbarch_unwind_dummy_id (gdbarch
, arm_unwind_dummy_id
);
2755 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
2756 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
2758 frame_base_set_default (gdbarch
, &arm_normal_base
);
2760 /* Address manipulation. */
2761 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
2762 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
2764 /* Advance PC across function entry code. */
2765 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
2767 /* Get the PC when a frame might not be available. */
2768 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
, arm_saved_pc_after_call
);
2770 /* The stack grows downward. */
2771 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2773 /* Breakpoint manipulation. */
2774 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
2776 /* Information about registers, etc. */
2777 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
2778 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
2779 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
2780 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
2781 set_gdbarch_deprecated_register_byte (gdbarch
, arm_register_byte
);
2782 set_gdbarch_num_regs (gdbarch
, NUM_GREGS
+ NUM_FREGS
+ NUM_SREGS
);
2783 set_gdbarch_register_type (gdbarch
, arm_register_type
);
2785 /* Internal <-> external register number maps. */
2786 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
2788 /* Integer registers are 4 bytes. */
2789 set_gdbarch_deprecated_register_size (gdbarch
, 4);
2790 set_gdbarch_register_name (gdbarch
, arm_register_name
);
2792 /* Returning results. */
2793 set_gdbarch_return_value (gdbarch
, arm_return_value
);
2795 /* Single stepping. */
2796 /* XXX For an RDI target we should ask the target if it can single-step. */
2797 set_gdbarch_software_single_step (gdbarch
, arm_software_single_step
);
2800 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
2802 /* Minsymbol frobbing. */
2803 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
2804 set_gdbarch_coff_make_msymbol_special (gdbarch
,
2805 arm_coff_make_msymbol_special
);
2807 /* Hook in the ABI-specific overrides, if they have been registered. */
2808 gdbarch_init_osabi (info
, gdbarch
);
2810 /* Add some default predicates. */
2811 frame_unwind_append_sniffer (gdbarch
, arm_stub_unwind_sniffer
);
2812 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
2813 frame_unwind_append_sniffer (gdbarch
, arm_prologue_unwind_sniffer
);
2815 /* Now we have tuned the configuration, set a few final things,
2816 based on what the OS ABI has told us. */
2818 if (tdep
->jb_pc
>= 0)
2819 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
2821 /* Floating point sizes and format. */
2822 switch (info
.byte_order
)
2824 case BFD_ENDIAN_BIG
:
2825 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
2826 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_big
);
2827 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
2830 case BFD_ENDIAN_LITTLE
:
2831 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
2832 if (fp_model
== ARM_FLOAT_SOFT_FPA
|| fp_model
== ARM_FLOAT_FPA
)
2834 set_gdbarch_double_format
2835 (gdbarch
, &floatformat_ieee_double_littlebyte_bigword
);
2836 set_gdbarch_long_double_format
2837 (gdbarch
, &floatformat_ieee_double_littlebyte_bigword
);
2841 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_little
);
2842 set_gdbarch_long_double_format (gdbarch
,
2843 &floatformat_ieee_double_little
);
2848 internal_error (__FILE__
, __LINE__
,
2849 _("arm_gdbarch_init: bad byte order for float format"));
2856 arm_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
2858 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2863 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
2864 (unsigned long) tdep
->lowest_pc
);
2867 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
2870 _initialize_arm_tdep (void)
2872 struct ui_file
*stb
;
2874 struct cmd_list_element
*new_set
, *new_show
;
2875 const char *setname
;
2876 const char *setdesc
;
2877 const char *const *regnames
;
2879 static char *helptext
;
2880 char regdesc
[1024], *rdptr
= regdesc
;
2881 size_t rest
= sizeof (regdesc
);
2883 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
2885 /* Register an ELF OS ABI sniffer for ARM binaries. */
2886 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
2887 bfd_target_elf_flavour
,
2888 arm_elf_osabi_sniffer
);
2890 /* Get the number of possible sets of register names defined in opcodes. */
2891 num_disassembly_options
= get_arm_regname_num_options ();
2893 /* Add root prefix command for all "set arm"/"show arm" commands. */
2894 add_prefix_cmd ("arm", no_class
, set_arm_command
,
2895 _("Various ARM-specific commands."),
2896 &setarmcmdlist
, "set arm ", 0, &setlist
);
2898 add_prefix_cmd ("arm", no_class
, show_arm_command
,
2899 _("Various ARM-specific commands."),
2900 &showarmcmdlist
, "show arm ", 0, &showlist
);
2902 /* Sync the opcode insn printer with our register viewer. */
2903 parse_arm_disassembler_option ("reg-names-std");
2905 /* Initialize the array that will be passed to
2906 add_setshow_enum_cmd(). */
2907 valid_disassembly_styles
2908 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
2909 for (i
= 0; i
< num_disassembly_options
; i
++)
2911 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
2912 valid_disassembly_styles
[i
] = setname
;
2913 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
2916 /* Copy the default names (if found) and synchronize disassembler. */
2917 if (!strcmp (setname
, "std"))
2919 disassembly_style
= setname
;
2921 for (j
= 0; j
< numregs
; j
++)
2922 arm_register_names
[j
] = (char *) regnames
[j
];
2923 set_arm_regname_option (i
);
2926 /* Mark the end of valid options. */
2927 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
2929 /* Create the help text. */
2930 stb
= mem_fileopen ();
2931 fprintf_unfiltered (stb
, "%s%s%s",
2932 _("The valid values are:\n"),
2934 _("The default is \"std\"."));
2935 helptext
= ui_file_xstrdup (stb
, &length
);
2936 ui_file_delete (stb
);
2938 add_setshow_enum_cmd("disassembler", no_class
,
2939 valid_disassembly_styles
, &disassembly_style
,
2940 _("Set the disassembly style."),
2941 _("Show the disassembly style."),
2943 set_disassembly_style_sfunc
,
2944 NULL
, /* FIXME: i18n: The disassembly style is \"%s\". */
2945 &setarmcmdlist
, &showarmcmdlist
);
2947 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
2948 _("Set usage of ARM 32-bit mode."),
2949 _("Show usage of ARM 32-bit mode."),
2950 _("When off, a 26-bit PC will be used."),
2952 NULL
, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
2953 &setarmcmdlist
, &showarmcmdlist
);
2955 /* Add a command to allow the user to force the FPU model. */
2956 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
2957 _("Set the floating point type."),
2958 _("Show the floating point type."),
2959 _("auto - Determine the FP typefrom the OS-ABI.\n\
2960 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
2961 fpa - FPA co-processor (GCC compiled).\n\
2962 softvfp - Software FP with pure-endian doubles.\n\
2963 vfp - VFP co-processor."),
2964 set_fp_model_sfunc
, show_fp_model
,
2965 &setarmcmdlist
, &showarmcmdlist
);
2967 /* Add a command to allow the user to force the ABI. */
2968 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
2971 NULL
, arm_set_abi
, arm_show_abi
,
2972 &setarmcmdlist
, &showarmcmdlist
);
2974 /* Debugging flag. */
2975 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
2976 _("Set ARM debugging."),
2977 _("Show ARM debugging."),
2978 _("When on, arm-specific debugging is enabled."),
2980 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
2981 &setdebuglist
, &showdebuglist
);