1 /* Common target dependent code for GDB on ARM systems.
3 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999,
4 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 #include <ctype.h> /* XXX for isupper () */
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register styles. */
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
41 #include "dwarf2-frame.h"
44 #include "gdb/sim-arm.h"
47 #include "coff/internal.h"
50 #include "gdb_assert.h"
54 /* Each OS has a different mechanism for accessing the various
55 registers stored in the sigcontext structure.
57 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
58 function pointer) which may be used to determine the addresses
59 of the various saved registers in the sigcontext structure.
61 For the ARM target, there are three parameters to this function.
62 The first is the pc value of the frame under consideration, the
63 second the stack pointer of this frame, and the last is the
64 register number to fetch.
66 If the tm.h file does not define this macro, then it's assumed that
67 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
70 When it comes time to multi-arching this code, see the identically
71 named machinery in ia64-tdep.c for an example of how it could be
72 done. It should not be necessary to modify the code below where
73 this macro is used. */
75 #ifdef SIGCONTEXT_REGISTER_ADDRESS
76 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
77 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
80 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
81 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
84 /* Macros for setting and testing a bit in a minimal symbol that marks
85 it as Thumb function. The MSB of the minimal symbol's "info" field
86 is used for this purpose.
88 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
89 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
91 #define MSYMBOL_SET_SPECIAL(msym) \
92 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
95 #define MSYMBOL_IS_SPECIAL(msym) \
96 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
98 /* The list of available "set arm ..." and "show arm ..." commands. */
99 static struct cmd_list_element
*setarmcmdlist
= NULL
;
100 static struct cmd_list_element
*showarmcmdlist
= NULL
;
102 /* The type of floating-point to use. Keep this in sync with enum
103 arm_float_model, and the help string in _initialize_arm_tdep. */
104 static const char *fp_model_strings
[] =
113 /* A variable that can be configured by the user. */
114 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
115 static const char *current_fp_model
= "auto";
117 /* Number of different reg name sets (options). */
118 static int num_disassembly_options
;
120 /* We have more registers than the disassembler as gdb can print the value
121 of special registers as well.
122 The general register names are overwritten by whatever is being used by
123 the disassembler at the moment. We also adjust the case of cpsr and fps. */
125 /* Initial value: Register names used in ARM's ISA documentation. */
126 static char * arm_register_name_strings
[] =
127 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
128 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
129 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
130 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
131 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
132 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
133 "fps", "cpsr" }; /* 24 25 */
134 static char **arm_register_names
= arm_register_name_strings
;
136 /* Valid register name styles. */
137 static const char **valid_disassembly_styles
;
139 /* Disassembly style to use. Default to "std" register names. */
140 static const char *disassembly_style
;
141 /* Index to that option in the opcodes table. */
142 static int current_option
;
144 /* This is used to keep the bfd arch_info in sync with the disassembly
146 static void set_disassembly_style_sfunc(char *, int,
147 struct cmd_list_element
*);
148 static void set_disassembly_style (void);
150 static void convert_from_extended (const struct floatformat
*, const void *,
152 static void convert_to_extended (const struct floatformat
*, void *,
155 struct arm_prologue_cache
157 /* The stack pointer at the time this frame was created; i.e. the
158 caller's stack pointer when this function was called. It is used
159 to identify this frame. */
162 /* The frame base for this frame is just prev_sp + frame offset -
163 frame size. FRAMESIZE is the size of this stack frame, and
164 FRAMEOFFSET if the initial offset from the stack pointer (this
165 frame's stack pointer, not PREV_SP) to the frame base. */
170 /* The register used to hold the frame pointer for this frame. */
173 /* Saved register offsets. */
174 struct trad_frame_saved_reg
*saved_regs
;
177 /* Addresses for calling Thumb functions have the bit 0 set.
178 Here are some macros to test, set, or clear bit 0 of addresses. */
179 #define IS_THUMB_ADDR(addr) ((addr) & 1)
180 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
181 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
183 /* Set to true if the 32-bit mode is in use. */
187 /* Determine if the program counter specified in MEMADDR is in a Thumb
191 arm_pc_is_thumb (CORE_ADDR memaddr
)
193 struct minimal_symbol
*sym
;
195 /* If bit 0 of the address is set, assume this is a Thumb address. */
196 if (IS_THUMB_ADDR (memaddr
))
199 /* Thumb functions have a "special" bit set in minimal symbols. */
200 sym
= lookup_minimal_symbol_by_pc (memaddr
);
203 return (MSYMBOL_IS_SPECIAL (sym
));
211 /* Remove useless bits from addresses in a running program. */
213 arm_addr_bits_remove (CORE_ADDR val
)
216 return (val
& (arm_pc_is_thumb (val
) ? 0xfffffffe : 0xfffffffc));
218 return (val
& 0x03fffffc);
221 /* When reading symbols, we need to zap the low bit of the address,
222 which may be set to 1 for Thumb functions. */
224 arm_smash_text_address (CORE_ADDR val
)
229 /* Immediately after a function call, return the saved pc. Can't
230 always go through the frames for this because on some machines the
231 new frame is not set up until the new function executes some
235 arm_saved_pc_after_call (struct frame_info
*frame
)
237 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM
));
240 /* A typical Thumb prologue looks like this:
244 Sometimes the latter instruction may be replaced by:
252 or, on tpcs, like this:
259 There is always one instruction of three classes:
264 When we have found at least one of each class we are done with the prolog.
265 Note that the "sub sp, #NN" before the push does not count.
269 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
271 CORE_ADDR current_pc
;
273 bit 0 - push { rlist }
274 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
275 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
279 for (current_pc
= pc
;
280 current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40;
283 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
285 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
287 findmask
|= 1; /* push found */
289 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
292 if ((findmask
& 1) == 0) /* before push ? */
295 findmask
|= 4; /* add/sub sp found */
297 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
299 findmask
|= 2; /* setting of r7 found */
301 else if (insn
== 0x466f) /* mov r7, sp */
303 findmask
|= 2; /* setting of r7 found */
305 else if (findmask
== (4+2+1))
307 /* We have found one of each type of prologue instruction */
311 /* Something in the prolog that we don't care about or some
312 instruction from outside the prolog scheduled here for
320 /* Advance the PC across any function entry prologue instructions to
321 reach some "real" code.
323 The APCS (ARM Procedure Call Standard) defines the following
327 [stmfd sp!, {a1,a2,a3,a4}]
328 stmfd sp!, {...,fp,ip,lr,pc}
329 [stfe f7, [sp, #-12]!]
330 [stfe f6, [sp, #-12]!]
331 [stfe f5, [sp, #-12]!]
332 [stfe f4, [sp, #-12]!]
333 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
336 arm_skip_prologue (CORE_ADDR pc
)
340 CORE_ADDR func_addr
, func_end
= 0;
342 struct symtab_and_line sal
;
344 /* If we're in a dummy frame, don't even try to skip the prologue. */
345 if (deprecated_pc_in_call_dummy (pc
))
348 /* See what the symbol table says. */
350 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
354 /* Found a function. */
355 sym
= lookup_symbol (func_name
, NULL
, VAR_DOMAIN
, NULL
, NULL
);
356 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
358 /* Don't use this trick for assembly source files. */
359 sal
= find_pc_line (func_addr
, 0);
360 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
365 /* Check if this is Thumb code. */
366 if (arm_pc_is_thumb (pc
))
367 return thumb_skip_prologue (pc
, func_end
);
369 /* Can't find the prologue end in the symbol table, try it the hard way
370 by disassembling the instructions. */
372 /* Like arm_scan_prologue, stop no later than pc + 64. */
373 if (func_end
== 0 || func_end
> pc
+ 64)
376 for (skip_pc
= pc
; skip_pc
< func_end
; skip_pc
+= 4)
378 inst
= read_memory_integer (skip_pc
, 4);
380 /* "mov ip, sp" is no longer a required part of the prologue. */
381 if (inst
== 0xe1a0c00d) /* mov ip, sp */
384 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
387 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
390 /* Some prologues begin with "str lr, [sp, #-4]!". */
391 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
394 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
397 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
400 /* Any insns after this point may float into the code, if it makes
401 for better instruction scheduling, so we skip them only if we
402 find them, but still consider the function to be frame-ful. */
404 /* We may have either one sfmfd instruction here, or several stfe
405 insns, depending on the version of floating point code we
407 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
410 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
413 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
416 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
419 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
420 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
421 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
424 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
425 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
426 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
429 /* Un-recognized instruction; stop scanning. */
433 return skip_pc
; /* End of prologue */
437 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
438 This function decodes a Thumb function prologue to determine:
439 1) the size of the stack frame
440 2) which registers are saved on it
441 3) the offsets of saved regs
442 4) the offset from the stack pointer to the frame pointer
444 A typical Thumb function prologue would create this stack frame
445 (offsets relative to FP)
446 old SP -> 24 stack parameters
449 R7 -> 0 local variables (16 bytes)
450 SP -> -12 additional stack space (12 bytes)
451 The frame size would thus be 36 bytes, and the frame offset would be
452 12 bytes. The frame register is R7.
454 The comments for thumb_skip_prolog() describe the algorithm we use
455 to detect the end of the prolog. */
459 thumb_scan_prologue (CORE_ADDR prev_pc
, struct arm_prologue_cache
*cache
)
461 CORE_ADDR prologue_start
;
462 CORE_ADDR prologue_end
;
463 CORE_ADDR current_pc
;
464 /* Which register has been copied to register n? */
467 bit 0 - push { rlist }
468 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
469 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
474 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
476 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
478 if (sal
.line
== 0) /* no line info, use current PC */
479 prologue_end
= prev_pc
;
480 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
481 prologue_end
= sal
.end
; /* (probably means no prologue) */
484 /* We're in the boondocks: allow for
485 16 pushes, an add, and "mv fp,sp". */
486 prologue_end
= prologue_start
+ 40;
488 prologue_end
= min (prologue_end
, prev_pc
);
490 /* Initialize the saved register map. When register H is copied to
491 register L, we will put H in saved_reg[L]. */
492 for (i
= 0; i
< 16; i
++)
495 /* Search the prologue looking for instructions that set up the
496 frame pointer, adjust the stack pointer, and save registers.
497 Do this until all basic prolog instructions are found. */
499 cache
->framesize
= 0;
500 for (current_pc
= prologue_start
;
501 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
508 insn
= read_memory_unsigned_integer (current_pc
, 2);
510 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
513 findmask
|= 1; /* push found */
514 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
515 whether to save LR (R14). */
516 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
518 /* Calculate offsets of saved R0-R7 and LR. */
519 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
520 if (mask
& (1 << regno
))
522 cache
->framesize
+= 4;
523 cache
->saved_regs
[saved_reg
[regno
]].addr
= -cache
->framesize
;
524 /* Reset saved register map. */
525 saved_reg
[regno
] = regno
;
528 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
531 if ((findmask
& 1) == 0) /* before push? */
534 findmask
|= 4; /* add/sub sp found */
536 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
537 if (insn
& 0x80) /* is it signed? (==subtracting) */
539 cache
->frameoffset
+= offset
;
542 cache
->framesize
-= offset
;
544 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
546 findmask
|= 2; /* setting of r7 found */
547 cache
->framereg
= THUMB_FP_REGNUM
;
548 /* get scaled offset */
549 cache
->frameoffset
= (insn
& 0xff) << 2;
551 else if (insn
== 0x466f) /* mov r7, sp */
553 findmask
|= 2; /* setting of r7 found */
554 cache
->framereg
= THUMB_FP_REGNUM
;
555 cache
->frameoffset
= 0;
556 saved_reg
[THUMB_FP_REGNUM
] = ARM_SP_REGNUM
;
558 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
560 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
561 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
562 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
565 /* Something in the prolog that we don't care about or some
566 instruction from outside the prolog scheduled here for
572 /* This function decodes an ARM function prologue to determine:
573 1) the size of the stack frame
574 2) which registers are saved on it
575 3) the offsets of saved regs
576 4) the offset from the stack pointer to the frame pointer
577 This information is stored in the "extra" fields of the frame_info.
579 There are two basic forms for the ARM prologue. The fixed argument
580 function call will look like:
583 stmfd sp!, {fp, ip, lr, pc}
587 Which would create this stack frame (offsets relative to FP):
588 IP -> 4 (caller's stack)
589 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
590 -4 LR (return address in caller)
591 -8 IP (copy of caller's SP)
593 SP -> -28 Local variables
595 The frame size would thus be 32 bytes, and the frame offset would be
596 28 bytes. The stmfd call can also save any of the vN registers it
597 plans to use, which increases the frame size accordingly.
599 Note: The stored PC is 8 off of the STMFD instruction that stored it
600 because the ARM Store instructions always store PC + 8 when you read
603 A variable argument function call will look like:
606 stmfd sp!, {a1, a2, a3, a4}
607 stmfd sp!, {fp, ip, lr, pc}
610 Which would create this stack frame (offsets relative to FP):
611 IP -> 20 (caller's stack)
616 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
617 -4 LR (return address in caller)
618 -8 IP (copy of caller's SP)
620 SP -> -28 Local variables
622 The frame size would thus be 48 bytes, and the frame offset would be
625 There is another potential complication, which is that the optimizer
626 will try to separate the store of fp in the "stmfd" instruction from
627 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
628 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
630 Also, note, the original version of the ARM toolchain claimed that there
633 instruction at the end of the prologue. I have never seen GCC produce
634 this, and the ARM docs don't mention it. We still test for it below in
640 arm_scan_prologue (struct frame_info
*next_frame
, struct arm_prologue_cache
*cache
)
642 int regno
, sp_offset
, fp_offset
, ip_offset
;
643 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
644 CORE_ADDR prev_pc
= frame_pc_unwind (next_frame
);
646 /* Assume there is no frame until proven otherwise. */
647 cache
->framereg
= ARM_SP_REGNUM
;
648 cache
->framesize
= 0;
649 cache
->frameoffset
= 0;
651 /* Check for Thumb prologue. */
652 if (arm_pc_is_thumb (prev_pc
))
654 thumb_scan_prologue (prev_pc
, cache
);
658 /* Find the function prologue. If we can't find the function in
659 the symbol table, peek in the stack frame to find the PC. */
660 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
662 /* One way to find the end of the prologue (which works well
663 for unoptimized code) is to do the following:
665 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
668 prologue_end = prev_pc;
669 else if (sal.end < prologue_end)
670 prologue_end = sal.end;
672 This mechanism is very accurate so long as the optimizer
673 doesn't move any instructions from the function body into the
674 prologue. If this happens, sal.end will be the last
675 instruction in the first hunk of prologue code just before
676 the first instruction that the scheduler has moved from
677 the body to the prologue.
679 In order to make sure that we scan all of the prologue
680 instructions, we use a slightly less accurate mechanism which
681 may scan more than necessary. To help compensate for this
682 lack of accuracy, the prologue scanning loop below contains
683 several clauses which'll cause the loop to terminate early if
684 an implausible prologue instruction is encountered.
690 is a suitable endpoint since it accounts for the largest
691 possible prologue plus up to five instructions inserted by
694 if (prologue_end
> prologue_start
+ 64)
696 prologue_end
= prologue_start
+ 64; /* See above. */
701 /* We have no symbol information. Our only option is to assume this
702 function has a standard stack frame and the normal frame register.
703 Then, we can find the value of our frame pointer on entrance to
704 the callee (or at the present moment if this is the innermost frame).
705 The value stored there should be the address of the stmfd + 8. */
707 LONGEST return_value
;
709 frame_loc
= frame_unwind_register_unsigned (next_frame
, ARM_FP_REGNUM
);
710 if (!safe_read_memory_integer (frame_loc
, 4, &return_value
))
714 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
715 prologue_end
= prologue_start
+ 64; /* See above. */
719 if (prev_pc
< prologue_end
)
720 prologue_end
= prev_pc
;
722 /* Now search the prologue looking for instructions that set up the
723 frame pointer, adjust the stack pointer, and save registers.
725 Be careful, however, and if it doesn't look like a prologue,
726 don't try to scan it. If, for instance, a frameless function
727 begins with stmfd sp!, then we will tell ourselves there is
728 a frame, which will confuse stack traceback, as well as "finish"
729 and other operations that rely on a knowledge of the stack
732 In the APCS, the prologue should start with "mov ip, sp" so
733 if we don't see this as the first insn, we will stop.
735 [Note: This doesn't seem to be true any longer, so it's now an
736 optional part of the prologue. - Kevin Buettner, 2001-11-20]
738 [Note further: The "mov ip,sp" only seems to be missing in
739 frameless functions at optimization level "-O2" or above,
740 in which case it is often (but not always) replaced by
741 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
743 sp_offset
= fp_offset
= ip_offset
= 0;
745 for (current_pc
= prologue_start
;
746 current_pc
< prologue_end
;
749 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
751 if (insn
== 0xe1a0c00d) /* mov ip, sp */
756 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
758 unsigned imm
= insn
& 0xff; /* immediate value */
759 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
760 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
764 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
766 unsigned imm
= insn
& 0xff; /* immediate value */
767 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
768 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
772 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
775 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= sp_offset
;
778 else if ((insn
& 0xffff0000) == 0xe92d0000)
779 /* stmfd sp!, {..., fp, ip, lr, pc}
781 stmfd sp!, {a1, a2, a3, a4} */
783 int mask
= insn
& 0xffff;
785 /* Calculate offsets of saved registers. */
786 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
787 if (mask
& (1 << regno
))
790 cache
->saved_regs
[regno
].addr
= sp_offset
;
793 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
794 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
795 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
797 /* No need to add this to saved_regs -- it's just an arg reg. */
800 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
801 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
802 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
804 /* No need to add this to saved_regs -- it's just an arg reg. */
807 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
809 unsigned imm
= insn
& 0xff; /* immediate value */
810 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
811 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
812 fp_offset
= -imm
+ ip_offset
;
813 cache
->framereg
= ARM_FP_REGNUM
;
815 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
817 unsigned imm
= insn
& 0xff; /* immediate value */
818 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
819 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
822 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
825 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
826 cache
->saved_regs
[regno
].addr
= sp_offset
;
828 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
831 unsigned int fp_start_reg
, fp_bound_reg
;
833 if ((insn
& 0x800) == 0x800) /* N0 is set */
835 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
842 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
848 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
849 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
850 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
853 cache
->saved_regs
[fp_start_reg
++].addr
= sp_offset
;
856 else if ((insn
& 0xf0000000) != 0xe0000000)
857 break; /* Condition not true, exit early */
858 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
859 break; /* Don't scan past a block load */
861 /* The optimizer might shove anything into the prologue,
862 so we just skip what we don't recognize. */
866 /* The frame size is just the negative of the offset (from the
867 original SP) of the last thing thing we pushed on the stack.
868 The frame offset is [new FP] - [new SP]. */
869 cache
->framesize
= -sp_offset
;
870 if (cache
->framereg
== ARM_FP_REGNUM
)
871 cache
->frameoffset
= fp_offset
- sp_offset
;
873 cache
->frameoffset
= 0;
876 static struct arm_prologue_cache
*
877 arm_make_prologue_cache (struct frame_info
*next_frame
)
880 struct arm_prologue_cache
*cache
;
881 CORE_ADDR unwound_fp
;
883 cache
= frame_obstack_zalloc (sizeof (struct arm_prologue_cache
));
884 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
886 arm_scan_prologue (next_frame
, cache
);
888 unwound_fp
= frame_unwind_register_unsigned (next_frame
, cache
->framereg
);
892 cache
->prev_sp
= unwound_fp
+ cache
->framesize
- cache
->frameoffset
;
894 /* Calculate actual addresses of saved registers using offsets
895 determined by arm_scan_prologue. */
896 for (reg
= 0; reg
< NUM_REGS
; reg
++)
897 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
898 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
903 /* Our frame ID for a normal frame is the current function's starting PC
904 and the caller's SP when we were called. */
907 arm_prologue_this_id (struct frame_info
*next_frame
,
909 struct frame_id
*this_id
)
911 struct arm_prologue_cache
*cache
;
915 if (*this_cache
== NULL
)
916 *this_cache
= arm_make_prologue_cache (next_frame
);
919 func
= frame_func_unwind (next_frame
);
921 /* This is meant to halt the backtrace at "_start". Make sure we
922 don't halt it at a generic dummy frame. */
923 if (func
<= LOWEST_PC
)
926 /* If we've hit a wall, stop. */
927 if (cache
->prev_sp
== 0)
930 id
= frame_id_build (cache
->prev_sp
, func
);
935 arm_prologue_prev_register (struct frame_info
*next_frame
,
939 enum lval_type
*lvalp
,
944 struct arm_prologue_cache
*cache
;
946 if (*this_cache
== NULL
)
947 *this_cache
= arm_make_prologue_cache (next_frame
);
950 /* If we are asked to unwind the PC, then we need to return the LR
951 instead. The saved value of PC points into this frame's
952 prologue, not the next frame's resume location. */
953 if (prev_regnum
== ARM_PC_REGNUM
)
954 prev_regnum
= ARM_LR_REGNUM
;
956 /* SP is generally not saved to the stack, but this frame is
957 identified by NEXT_FRAME's stack pointer at the time of the call.
958 The value was already reconstructed into PREV_SP. */
959 if (prev_regnum
== ARM_SP_REGNUM
)
963 store_unsigned_integer (valuep
, 4, cache
->prev_sp
);
967 trad_frame_get_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
968 optimized
, lvalp
, addrp
, realnump
, valuep
);
971 struct frame_unwind arm_prologue_unwind
= {
973 arm_prologue_this_id
,
974 arm_prologue_prev_register
977 static const struct frame_unwind
*
978 arm_prologue_unwind_sniffer (struct frame_info
*next_frame
)
980 return &arm_prologue_unwind
;
983 static struct arm_prologue_cache
*
984 arm_make_stub_cache (struct frame_info
*next_frame
)
987 struct arm_prologue_cache
*cache
;
988 CORE_ADDR unwound_fp
;
990 cache
= frame_obstack_zalloc (sizeof (struct arm_prologue_cache
));
991 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
993 cache
->prev_sp
= frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
);
998 /* Our frame ID for a stub frame is the current SP and LR. */
1001 arm_stub_this_id (struct frame_info
*next_frame
,
1003 struct frame_id
*this_id
)
1005 struct arm_prologue_cache
*cache
;
1007 if (*this_cache
== NULL
)
1008 *this_cache
= arm_make_stub_cache (next_frame
);
1009 cache
= *this_cache
;
1011 *this_id
= frame_id_build (cache
->prev_sp
,
1012 frame_pc_unwind (next_frame
));
1015 struct frame_unwind arm_stub_unwind
= {
1018 arm_prologue_prev_register
1021 static const struct frame_unwind
*
1022 arm_stub_unwind_sniffer (struct frame_info
*next_frame
)
1026 if (in_plt_section (frame_unwind_address_in_block (next_frame
), NULL
)
1027 || target_read_memory (frame_pc_unwind (next_frame
), dummy
, 4) != 0)
1028 return &arm_stub_unwind
;
1034 arm_normal_frame_base (struct frame_info
*next_frame
, void **this_cache
)
1036 struct arm_prologue_cache
*cache
;
1038 if (*this_cache
== NULL
)
1039 *this_cache
= arm_make_prologue_cache (next_frame
);
1040 cache
= *this_cache
;
1042 return cache
->prev_sp
+ cache
->frameoffset
- cache
->framesize
;
1045 struct frame_base arm_normal_base
= {
1046 &arm_prologue_unwind
,
1047 arm_normal_frame_base
,
1048 arm_normal_frame_base
,
1049 arm_normal_frame_base
1052 static struct arm_prologue_cache
*
1053 arm_make_sigtramp_cache (struct frame_info
*next_frame
)
1055 struct arm_prologue_cache
*cache
;
1058 cache
= frame_obstack_zalloc (sizeof (struct arm_prologue_cache
));
1060 cache
->prev_sp
= frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
);
1062 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1064 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1065 cache
->saved_regs
[reg
].addr
1066 = SIGCONTEXT_REGISTER_ADDRESS (cache
->prev_sp
,
1067 frame_pc_unwind (next_frame
), reg
);
1069 /* FIXME: What about thumb mode? */
1070 cache
->framereg
= ARM_SP_REGNUM
;
1072 = read_memory_integer (cache
->saved_regs
[cache
->framereg
].addr
,
1073 register_size (current_gdbarch
, cache
->framereg
));
1079 arm_sigtramp_this_id (struct frame_info
*next_frame
,
1081 struct frame_id
*this_id
)
1083 struct arm_prologue_cache
*cache
;
1085 if (*this_cache
== NULL
)
1086 *this_cache
= arm_make_sigtramp_cache (next_frame
);
1087 cache
= *this_cache
;
1089 /* FIXME drow/2003-07-07: This isn't right if we single-step within
1090 the sigtramp frame; the PC should be the beginning of the trampoline. */
1091 *this_id
= frame_id_build (cache
->prev_sp
, frame_pc_unwind (next_frame
));
1095 arm_sigtramp_prev_register (struct frame_info
*next_frame
,
1099 enum lval_type
*lvalp
,
1104 struct arm_prologue_cache
*cache
;
1106 if (*this_cache
== NULL
)
1107 *this_cache
= arm_make_sigtramp_cache (next_frame
);
1108 cache
= *this_cache
;
1110 trad_frame_get_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
1111 optimized
, lvalp
, addrp
, realnump
, valuep
);
1114 struct frame_unwind arm_sigtramp_unwind
= {
1116 arm_sigtramp_this_id
,
1117 arm_sigtramp_prev_register
1120 static const struct frame_unwind
*
1121 arm_sigtramp_unwind_sniffer (struct frame_info
*next_frame
)
1123 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1124 && legacy_pc_in_sigtramp (frame_pc_unwind (next_frame
), (char *) 0))
1125 return &arm_sigtramp_unwind
;
1130 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1131 dummy frame. The frame ID's base needs to match the TOS value
1132 saved by save_dummy_frame_tos() and returned from
1133 arm_push_dummy_call, and the PC needs to match the dummy frame's
1136 static struct frame_id
1137 arm_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1139 return frame_id_build (frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
),
1140 frame_pc_unwind (next_frame
));
1143 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1144 be used to construct the previous frame's ID, after looking up the
1145 containing function). */
1148 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1151 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1152 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1156 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1158 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1161 /* When arguments must be pushed onto the stack, they go on in reverse
1162 order. The code below implements a FILO (stack) to do this. */
1167 struct stack_item
*prev
;
1171 static struct stack_item
*
1172 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1174 struct stack_item
*si
;
1175 si
= xmalloc (sizeof (struct stack_item
));
1176 si
->data
= xmalloc (len
);
1179 memcpy (si
->data
, contents
, len
);
1183 static struct stack_item
*
1184 pop_stack_item (struct stack_item
*si
)
1186 struct stack_item
*dead
= si
;
1193 /* We currently only support passing parameters in integer registers. This
1194 conforms with GCC's default model. Several other variants exist and
1195 we should probably support some of them based on the selected ABI. */
1198 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1199 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1200 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1201 CORE_ADDR struct_addr
)
1206 struct stack_item
*si
= NULL
;
1208 /* Set the return address. For the ARM, the return breakpoint is
1209 always at BP_ADDR. */
1210 /* XXX Fix for Thumb. */
1211 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1213 /* Walk through the list of args and determine how large a temporary
1214 stack is required. Need to take care here as structs may be
1215 passed on the stack, and we have to to push them. */
1218 argreg
= ARM_A1_REGNUM
;
1221 /* Some platforms require a double-word aligned stack. Make sure sp
1222 is correctly aligned before we start. We always do this even if
1223 it isn't really needed -- it can never hurt things. */
1224 sp
&= ~(CORE_ADDR
)(2 * DEPRECATED_REGISTER_SIZE
- 1);
1226 /* The struct_return pointer occupies the first parameter
1227 passing register. */
1231 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = 0x%s\n",
1232 REGISTER_NAME (argreg
), paddr (struct_addr
));
1233 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1237 for (argnum
= 0; argnum
< nargs
; argnum
++)
1240 struct type
*arg_type
;
1241 struct type
*target_type
;
1242 enum type_code typecode
;
1245 arg_type
= check_typedef (value_type (args
[argnum
]));
1246 len
= TYPE_LENGTH (arg_type
);
1247 target_type
= TYPE_TARGET_TYPE (arg_type
);
1248 typecode
= TYPE_CODE (arg_type
);
1249 val
= value_contents_writeable (args
[argnum
]);
1251 /* If the argument is a pointer to a function, and it is a
1252 Thumb function, create a LOCAL copy of the value and set
1253 the THUMB bit in it. */
1254 if (TYPE_CODE_PTR
== typecode
1255 && target_type
!= NULL
1256 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1258 CORE_ADDR regval
= extract_unsigned_integer (val
, len
);
1259 if (arm_pc_is_thumb (regval
))
1262 store_unsigned_integer (val
, len
, MAKE_THUMB_ADDR (regval
));
1266 /* Copy the argument to general registers or the stack in
1267 register-sized pieces. Large arguments are split between
1268 registers and stack. */
1271 int partial_len
= len
< DEPRECATED_REGISTER_SIZE
? len
: DEPRECATED_REGISTER_SIZE
;
1273 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1275 /* The argument is being passed in a general purpose
1277 CORE_ADDR regval
= extract_unsigned_integer (val
, partial_len
);
1279 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1280 argnum
, REGISTER_NAME (argreg
),
1281 phex (regval
, DEPRECATED_REGISTER_SIZE
));
1282 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1287 /* Push the arguments onto the stack. */
1289 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1291 si
= push_stack_item (si
, val
, DEPRECATED_REGISTER_SIZE
);
1292 nstack
+= DEPRECATED_REGISTER_SIZE
;
1299 /* If we have an odd number of words to push, then decrement the stack
1300 by one word now, so first stack argument will be dword aligned. */
1307 write_memory (sp
, si
->data
, si
->len
);
1308 si
= pop_stack_item (si
);
1311 /* Finally, update teh SP register. */
1312 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1318 print_fpu_flags (int flags
)
1320 if (flags
& (1 << 0))
1321 fputs ("IVO ", stdout
);
1322 if (flags
& (1 << 1))
1323 fputs ("DVZ ", stdout
);
1324 if (flags
& (1 << 2))
1325 fputs ("OFL ", stdout
);
1326 if (flags
& (1 << 3))
1327 fputs ("UFL ", stdout
);
1328 if (flags
& (1 << 4))
1329 fputs ("INX ", stdout
);
1333 /* Print interesting information about the floating point processor
1334 (if present) or emulator. */
1336 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1337 struct frame_info
*frame
, const char *args
)
1339 unsigned long status
= read_register (ARM_FPS_REGNUM
);
1342 type
= (status
>> 24) & 127;
1343 if (status
& (1 << 31))
1344 printf (_("Hardware FPU type %d\n"), type
);
1346 printf (_("Software FPU type %d\n"), type
);
1347 /* i18n: [floating point unit] mask */
1348 fputs (_("mask: "), stdout
);
1349 print_fpu_flags (status
>> 16);
1350 /* i18n: [floating point unit] flags */
1351 fputs (_("flags: "), stdout
);
1352 print_fpu_flags (status
);
1355 /* Return the GDB type object for the "standard" data type of data in
1358 static struct type
*
1359 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
1361 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1363 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1364 return builtin_type_arm_ext_big
;
1366 return builtin_type_arm_ext_littlebyte_bigword
;
1369 return builtin_type_int32
;
1372 /* Index within `registers' of the first byte of the space for
1376 arm_register_byte (int regnum
)
1378 if (regnum
< ARM_F0_REGNUM
)
1379 return regnum
* INT_REGISTER_SIZE
;
1380 else if (regnum
< ARM_PS_REGNUM
)
1381 return (NUM_GREGS
* INT_REGISTER_SIZE
1382 + (regnum
- ARM_F0_REGNUM
) * FP_REGISTER_SIZE
);
1384 return (NUM_GREGS
* INT_REGISTER_SIZE
1385 + NUM_FREGS
* FP_REGISTER_SIZE
1386 + (regnum
- ARM_FPS_REGNUM
) * STATUS_REGISTER_SIZE
);
1389 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1391 arm_register_sim_regno (int regnum
)
1394 gdb_assert (reg
>= 0 && reg
< NUM_REGS
);
1396 if (reg
< NUM_GREGS
)
1397 return SIM_ARM_R0_REGNUM
+ reg
;
1400 if (reg
< NUM_FREGS
)
1401 return SIM_ARM_FP0_REGNUM
+ reg
;
1404 if (reg
< NUM_SREGS
)
1405 return SIM_ARM_FPS_REGNUM
+ reg
;
1408 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
1411 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1412 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1413 It is thought that this is is the floating-point register format on
1414 little-endian systems. */
1417 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
1421 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1422 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1424 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1426 floatformat_from_doublest (fmt
, &d
, dbl
);
1430 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
)
1433 floatformat_to_doublest (fmt
, ptr
, &d
);
1434 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1435 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1437 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1442 condition_true (unsigned long cond
, unsigned long status_reg
)
1444 if (cond
== INST_AL
|| cond
== INST_NV
)
1450 return ((status_reg
& FLAG_Z
) != 0);
1452 return ((status_reg
& FLAG_Z
) == 0);
1454 return ((status_reg
& FLAG_C
) != 0);
1456 return ((status_reg
& FLAG_C
) == 0);
1458 return ((status_reg
& FLAG_N
) != 0);
1460 return ((status_reg
& FLAG_N
) == 0);
1462 return ((status_reg
& FLAG_V
) != 0);
1464 return ((status_reg
& FLAG_V
) == 0);
1466 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1468 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1470 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1472 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1474 return (((status_reg
& FLAG_Z
) == 0) &&
1475 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1477 return (((status_reg
& FLAG_Z
) != 0) ||
1478 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1483 /* Support routines for single stepping. Calculate the next PC value. */
1484 #define submask(x) ((1L << ((x) + 1)) - 1)
1485 #define bit(obj,st) (((obj) >> (st)) & 1)
1486 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1487 #define sbits(obj,st,fn) \
1488 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1489 #define BranchDest(addr,instr) \
1490 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1493 static unsigned long
1494 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1495 unsigned long status_reg
)
1497 unsigned long res
, shift
;
1498 int rm
= bits (inst
, 0, 3);
1499 unsigned long shifttype
= bits (inst
, 5, 6);
1503 int rs
= bits (inst
, 8, 11);
1504 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1507 shift
= bits (inst
, 7, 11);
1510 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1511 + (bit (inst
, 4) ? 12 : 8))
1512 : read_register (rm
));
1517 res
= shift
>= 32 ? 0 : res
<< shift
;
1521 res
= shift
>= 32 ? 0 : res
>> shift
;
1527 res
= ((res
& 0x80000000L
)
1528 ? ~((~res
) >> shift
) : res
>> shift
);
1531 case 3: /* ROR/RRX */
1534 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1536 res
= (res
>> shift
) | (res
<< (32 - shift
));
1540 return res
& 0xffffffff;
1543 /* Return number of 1-bits in VAL. */
1546 bitcount (unsigned long val
)
1549 for (nbits
= 0; val
!= 0; nbits
++)
1550 val
&= val
- 1; /* delete rightmost 1-bit in val */
1555 thumb_get_next_pc (CORE_ADDR pc
)
1557 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1558 unsigned short inst1
= read_memory_integer (pc
, 2);
1559 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1560 unsigned long offset
;
1562 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1566 /* Fetch the saved PC from the stack. It's stored above
1567 all of the other registers. */
1568 offset
= bitcount (bits (inst1
, 0, 7)) * DEPRECATED_REGISTER_SIZE
;
1569 sp
= read_register (ARM_SP_REGNUM
);
1570 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1571 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1573 error (_("Infinite loop detected"));
1575 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1577 unsigned long status
= read_register (ARM_PS_REGNUM
);
1578 unsigned long cond
= bits (inst1
, 8, 11);
1579 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1580 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1582 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1584 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1586 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link, and blx */
1588 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1589 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1590 nextpc
= pc_val
+ offset
;
1591 /* For BLX make sure to clear the low bits. */
1592 if (bits (inst2
, 11, 12) == 1)
1593 nextpc
= nextpc
& 0xfffffffc;
1595 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
1597 if (bits (inst1
, 3, 6) == 0x0f)
1600 nextpc
= read_register (bits (inst1
, 3, 6));
1602 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1604 error (_("Infinite loop detected"));
1611 arm_get_next_pc (CORE_ADDR pc
)
1613 unsigned long pc_val
;
1614 unsigned long this_instr
;
1615 unsigned long status
;
1618 if (arm_pc_is_thumb (pc
))
1619 return thumb_get_next_pc (pc
);
1621 pc_val
= (unsigned long) pc
;
1622 this_instr
= read_memory_integer (pc
, 4);
1623 status
= read_register (ARM_PS_REGNUM
);
1624 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1626 if (condition_true (bits (this_instr
, 28, 31), status
))
1628 switch (bits (this_instr
, 24, 27))
1631 case 0x1: /* data processing */
1635 unsigned long operand1
, operand2
, result
= 0;
1639 if (bits (this_instr
, 12, 15) != 15)
1642 if (bits (this_instr
, 22, 25) == 0
1643 && bits (this_instr
, 4, 7) == 9) /* multiply */
1644 error (_("Invalid update to pc in instruction"));
1646 /* BX <reg>, BLX <reg> */
1647 if (bits (this_instr
, 4, 28) == 0x12fff1
1648 || bits (this_instr
, 4, 28) == 0x12fff3)
1650 rn
= bits (this_instr
, 0, 3);
1651 result
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1652 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1655 error (_("Infinite loop detected"));
1660 /* Multiply into PC */
1661 c
= (status
& FLAG_C
) ? 1 : 0;
1662 rn
= bits (this_instr
, 16, 19);
1663 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1665 if (bit (this_instr
, 25))
1667 unsigned long immval
= bits (this_instr
, 0, 7);
1668 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1669 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1672 else /* operand 2 is a shifted register */
1673 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1675 switch (bits (this_instr
, 21, 24))
1678 result
= operand1
& operand2
;
1682 result
= operand1
^ operand2
;
1686 result
= operand1
- operand2
;
1690 result
= operand2
- operand1
;
1694 result
= operand1
+ operand2
;
1698 result
= operand1
+ operand2
+ c
;
1702 result
= operand1
- operand2
+ c
;
1706 result
= operand2
- operand1
+ c
;
1712 case 0xb: /* tst, teq, cmp, cmn */
1713 result
= (unsigned long) nextpc
;
1717 result
= operand1
| operand2
;
1721 /* Always step into a function. */
1726 result
= operand1
& ~operand2
;
1733 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1736 error (_("Infinite loop detected"));
1741 case 0x5: /* data transfer */
1744 if (bit (this_instr
, 20))
1747 if (bits (this_instr
, 12, 15) == 15)
1753 if (bit (this_instr
, 22))
1754 error (_("Invalid update to pc in instruction"));
1756 /* byte write to PC */
1757 rn
= bits (this_instr
, 16, 19);
1758 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1759 if (bit (this_instr
, 24))
1762 int c
= (status
& FLAG_C
) ? 1 : 0;
1763 unsigned long offset
=
1764 (bit (this_instr
, 25)
1765 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1766 : bits (this_instr
, 0, 11));
1768 if (bit (this_instr
, 23))
1773 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1776 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1779 error (_("Infinite loop detected"));
1785 case 0x9: /* block transfer */
1786 if (bit (this_instr
, 20))
1789 if (bit (this_instr
, 15))
1794 if (bit (this_instr
, 23))
1797 unsigned long reglist
= bits (this_instr
, 0, 14);
1798 offset
= bitcount (reglist
) * 4;
1799 if (bit (this_instr
, 24)) /* pre */
1802 else if (bit (this_instr
, 24))
1806 unsigned long rn_val
=
1807 read_register (bits (this_instr
, 16, 19));
1809 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1813 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1815 error (_("Infinite loop detected"));
1820 case 0xb: /* branch & link */
1821 case 0xa: /* branch */
1823 nextpc
= BranchDest (pc
, this_instr
);
1826 if (bits (this_instr
, 28, 31) == INST_NV
)
1827 nextpc
|= bit (this_instr
, 24) << 1;
1829 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1831 error (_("Infinite loop detected"));
1837 case 0xe: /* coproc ops */
1842 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
1850 /* single_step() is called just before we want to resume the inferior,
1851 if we want to single-step it but there is no hardware or kernel
1852 single-step support. We find the target of the coming instruction
1855 single_step() is also called just after the inferior stops. If we
1856 had set up a simulated single-step, we undo our damage. */
1859 arm_software_single_step (enum target_signal sig
, int insert_bpt
)
1861 static int next_pc
; /* State between setting and unsetting. */
1862 static char break_mem
[BREAKPOINT_MAX
]; /* Temporary storage for mem@bpt */
1866 next_pc
= arm_get_next_pc (read_register (ARM_PC_REGNUM
));
1867 target_insert_breakpoint (next_pc
, break_mem
);
1870 target_remove_breakpoint (next_pc
, break_mem
);
1873 #include "bfd-in2.h"
1874 #include "libcoff.h"
1877 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
1879 if (arm_pc_is_thumb (memaddr
))
1881 static asymbol
*asym
;
1882 static combined_entry_type ce
;
1883 static struct coff_symbol_struct csym
;
1884 static struct bfd fake_bfd
;
1885 static bfd_target fake_target
;
1887 if (csym
.native
== NULL
)
1889 /* Create a fake symbol vector containing a Thumb symbol.
1890 This is solely so that the code in print_insn_little_arm()
1891 and print_insn_big_arm() in opcodes/arm-dis.c will detect
1892 the presence of a Thumb symbol and switch to decoding
1893 Thumb instructions. */
1895 fake_target
.flavour
= bfd_target_coff_flavour
;
1896 fake_bfd
.xvec
= &fake_target
;
1897 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
1899 csym
.symbol
.the_bfd
= &fake_bfd
;
1900 csym
.symbol
.name
= "fake";
1901 asym
= (asymbol
*) & csym
;
1904 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
1905 info
->symbols
= &asym
;
1908 info
->symbols
= NULL
;
1910 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1911 return print_insn_big_arm (memaddr
, info
);
1913 return print_insn_little_arm (memaddr
, info
);
1916 /* The following define instruction sequences that will cause ARM
1917 cpu's to take an undefined instruction trap. These are used to
1918 signal a breakpoint to GDB.
1920 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
1921 modes. A different instruction is required for each mode. The ARM
1922 cpu's can also be big or little endian. Thus four different
1923 instructions are needed to support all cases.
1925 Note: ARMv4 defines several new instructions that will take the
1926 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
1927 not in fact add the new instructions. The new undefined
1928 instructions in ARMv4 are all instructions that had no defined
1929 behaviour in earlier chips. There is no guarantee that they will
1930 raise an exception, but may be treated as NOP's. In practice, it
1931 may only safe to rely on instructions matching:
1933 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1934 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1935 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
1937 Even this may only true if the condition predicate is true. The
1938 following use a condition predicate of ALWAYS so it is always TRUE.
1940 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
1941 and NetBSD all use a software interrupt rather than an undefined
1942 instruction to force a trap. This can be handled by by the
1943 abi-specific code during establishment of the gdbarch vector. */
1946 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
1947 override these definitions. */
1948 #ifndef ARM_LE_BREAKPOINT
1949 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
1951 #ifndef ARM_BE_BREAKPOINT
1952 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
1954 #ifndef THUMB_LE_BREAKPOINT
1955 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
1957 #ifndef THUMB_BE_BREAKPOINT
1958 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
1961 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
1962 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
1963 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
1964 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
1966 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
1967 the program counter value to determine whether a 16-bit or 32-bit
1968 breakpoint should be used. It returns a pointer to a string of
1969 bytes that encode a breakpoint instruction, stores the length of
1970 the string to *lenptr, and adjusts the program counter (if
1971 necessary) to point to the actual memory location where the
1972 breakpoint should be inserted. */
1974 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
1975 breakpoints and storing their handles instread of what was in
1976 memory. It is nice that this is the same size as a handle -
1977 otherwise remote-rdp will have to change. */
1979 static const unsigned char *
1980 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1982 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1984 if (arm_pc_is_thumb (*pcptr
))
1986 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1987 *lenptr
= tdep
->thumb_breakpoint_size
;
1988 return tdep
->thumb_breakpoint
;
1992 *lenptr
= tdep
->arm_breakpoint_size
;
1993 return tdep
->arm_breakpoint
;
1997 /* Extract from an array REGBUF containing the (raw) register state a
1998 function return value of type TYPE, and copy that, in virtual
1999 format, into VALBUF. */
2002 arm_extract_return_value (struct type
*type
,
2003 struct regcache
*regs
,
2006 bfd_byte
*valbuf
= dst
;
2008 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2010 switch (arm_get_fp_model (current_gdbarch
))
2014 /* The value is in register F0 in internal format. We need to
2015 extract the raw value and then convert it to the desired
2017 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
2019 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
2020 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
2025 case ARM_FLOAT_SOFT_FPA
:
2026 case ARM_FLOAT_SOFT_VFP
:
2027 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
2028 if (TYPE_LENGTH (type
) > 4)
2029 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
2030 valbuf
+ INT_REGISTER_SIZE
);
2035 (__FILE__
, __LINE__
,
2036 _("arm_extract_return_value: Floating point model not supported"));
2040 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2041 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2042 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2043 || TYPE_CODE (type
) == TYPE_CODE_PTR
2044 || TYPE_CODE (type
) == TYPE_CODE_REF
2045 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2047 /* If the the type is a plain integer, then the access is
2048 straight-forward. Otherwise we have to play around a bit more. */
2049 int len
= TYPE_LENGTH (type
);
2050 int regno
= ARM_A1_REGNUM
;
2055 /* By using store_unsigned_integer we avoid having to do
2056 anything special for small big-endian values. */
2057 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2058 store_unsigned_integer (valbuf
,
2059 (len
> INT_REGISTER_SIZE
2060 ? INT_REGISTER_SIZE
: len
),
2062 len
-= INT_REGISTER_SIZE
;
2063 valbuf
+= INT_REGISTER_SIZE
;
2068 /* For a structure or union the behaviour is as if the value had
2069 been stored to word-aligned memory and then loaded into
2070 registers with 32-bit load instruction(s). */
2071 int len
= TYPE_LENGTH (type
);
2072 int regno
= ARM_A1_REGNUM
;
2073 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2077 regcache_cooked_read (regs
, regno
++, tmpbuf
);
2078 memcpy (valbuf
, tmpbuf
,
2079 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2080 len
-= INT_REGISTER_SIZE
;
2081 valbuf
+= INT_REGISTER_SIZE
;
2086 /* Extract from an array REGBUF containing the (raw) register state
2087 the address in which a function should return its structure value. */
2090 arm_extract_struct_value_address (struct regcache
*regcache
)
2094 regcache_cooked_read_unsigned (regcache
, ARM_A1_REGNUM
, &ret
);
2098 /* Will a function return an aggregate type in memory or in a
2099 register? Return 0 if an aggregate type can be returned in a
2100 register, 1 if it must be returned in memory. */
2103 arm_use_struct_convention (int gcc_p
, struct type
*type
)
2106 enum type_code code
;
2108 CHECK_TYPEDEF (type
);
2110 /* In the ARM ABI, "integer" like aggregate types are returned in
2111 registers. For an aggregate type to be integer like, its size
2112 must be less than or equal to DEPRECATED_REGISTER_SIZE and the
2113 offset of each addressable subfield must be zero. Note that bit
2114 fields are not addressable, and all addressable subfields of
2115 unions always start at offset zero.
2117 This function is based on the behaviour of GCC 2.95.1.
2118 See: gcc/arm.c: arm_return_in_memory() for details.
2120 Note: All versions of GCC before GCC 2.95.2 do not set up the
2121 parameters correctly for a function returning the following
2122 structure: struct { float f;}; This should be returned in memory,
2123 not a register. Richard Earnshaw sent me a patch, but I do not
2124 know of any way to detect if a function like the above has been
2125 compiled with the correct calling convention. */
2127 /* All aggregate types that won't fit in a register must be returned
2129 if (TYPE_LENGTH (type
) > DEPRECATED_REGISTER_SIZE
)
2134 /* The only aggregate types that can be returned in a register are
2135 structs and unions. Arrays must be returned in memory. */
2136 code
= TYPE_CODE (type
);
2137 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2142 /* Assume all other aggregate types can be returned in a register.
2143 Run a check for structures, unions and arrays. */
2146 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2149 /* Need to check if this struct/union is "integer" like. For
2150 this to be true, its size must be less than or equal to
2151 DEPRECATED_REGISTER_SIZE and the offset of each addressable
2152 subfield must be zero. Note that bit fields are not
2153 addressable, and unions always start at offset zero. If any
2154 of the subfields is a floating point type, the struct/union
2155 cannot be an integer type. */
2157 /* For each field in the object, check:
2158 1) Is it FP? --> yes, nRc = 1;
2159 2) Is it addressable (bitpos != 0) and
2160 not packed (bitsize == 0)?
2164 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2166 enum type_code field_type_code
;
2167 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, i
)));
2169 /* Is it a floating point type field? */
2170 if (field_type_code
== TYPE_CODE_FLT
)
2176 /* If bitpos != 0, then we have to care about it. */
2177 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2179 /* Bitfields are not addressable. If the field bitsize is
2180 zero, then the field is not packed. Hence it cannot be
2181 a bitfield or any other packed type. */
2182 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2194 /* Write into appropriate registers a function return value of type
2195 TYPE, given in virtual format. */
2198 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
2201 const bfd_byte
*valbuf
= src
;
2203 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2205 char buf
[MAX_REGISTER_SIZE
];
2207 switch (arm_get_fp_model (current_gdbarch
))
2211 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
);
2212 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
2215 case ARM_FLOAT_SOFT_FPA
:
2216 case ARM_FLOAT_SOFT_VFP
:
2217 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
2218 if (TYPE_LENGTH (type
) > 4)
2219 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
2220 valbuf
+ INT_REGISTER_SIZE
);
2225 (__FILE__
, __LINE__
,
2226 _("arm_store_return_value: Floating point model not supported"));
2230 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2231 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2232 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2233 || TYPE_CODE (type
) == TYPE_CODE_PTR
2234 || TYPE_CODE (type
) == TYPE_CODE_REF
2235 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2237 if (TYPE_LENGTH (type
) <= 4)
2239 /* Values of one word or less are zero/sign-extended and
2241 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2242 LONGEST val
= unpack_long (type
, valbuf
);
2244 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, val
);
2245 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
2249 /* Integral values greater than one word are stored in consecutive
2250 registers starting with r0. This will always be a multiple of
2251 the regiser size. */
2252 int len
= TYPE_LENGTH (type
);
2253 int regno
= ARM_A1_REGNUM
;
2257 regcache_cooked_write (regs
, regno
++, valbuf
);
2258 len
-= INT_REGISTER_SIZE
;
2259 valbuf
+= INT_REGISTER_SIZE
;
2265 /* For a structure or union the behaviour is as if the value had
2266 been stored to word-aligned memory and then loaded into
2267 registers with 32-bit load instruction(s). */
2268 int len
= TYPE_LENGTH (type
);
2269 int regno
= ARM_A1_REGNUM
;
2270 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2274 memcpy (tmpbuf
, valbuf
,
2275 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2276 regcache_cooked_write (regs
, regno
++, tmpbuf
);
2277 len
-= INT_REGISTER_SIZE
;
2278 valbuf
+= INT_REGISTER_SIZE
;
2284 arm_get_longjmp_target (CORE_ADDR
*pc
)
2287 char buf
[INT_REGISTER_SIZE
];
2288 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2290 jb_addr
= read_register (ARM_A1_REGNUM
);
2292 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2296 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
);
2300 /* Return non-zero if the PC is inside a thumb call thunk. */
2303 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2305 CORE_ADDR start_addr
;
2307 /* Find the starting address of the function containing the PC. If
2308 the caller didn't give us a name, look it up at the same time. */
2309 if (0 == find_pc_partial_function (pc
, name
? NULL
: &name
,
2313 return strncmp (name
, "_call_via_r", 11) == 0;
2316 /* If PC is in a Thumb call or return stub, return the address of the
2317 target PC, which is in a register. The thunk functions are called
2318 _called_via_xx, where x is the register name. The possible names
2319 are r0-r9, sl, fp, ip, sp, and lr. */
2322 arm_skip_stub (CORE_ADDR pc
)
2325 CORE_ADDR start_addr
;
2327 /* Find the starting address and name of the function containing the PC. */
2328 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2331 /* Call thunks always start with "_call_via_". */
2332 if (strncmp (name
, "_call_via_", 10) == 0)
2334 /* Use the name suffix to determine which register contains the
2336 static char *table
[15] =
2337 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2338 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2342 for (regno
= 0; regno
<= 14; regno
++)
2343 if (strcmp (&name
[10], table
[regno
]) == 0)
2344 return read_register (regno
);
2347 return 0; /* not a stub */
2351 set_arm_command (char *args
, int from_tty
)
2353 printf_unfiltered (_("\
2354 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2355 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
2359 show_arm_command (char *args
, int from_tty
)
2361 cmd_show_list (showarmcmdlist
, from_tty
, "");
2364 enum arm_float_model
2365 arm_get_fp_model (struct gdbarch
*gdbarch
)
2367 if (arm_fp_model
== ARM_FLOAT_AUTO
)
2368 return gdbarch_tdep (gdbarch
)->fp_model
;
2370 return arm_fp_model
;
2374 arm_set_fp (struct gdbarch
*gdbarch
)
2376 enum arm_float_model fp_model
= arm_get_fp_model (gdbarch
);
2378 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
2379 && (fp_model
== ARM_FLOAT_SOFT_FPA
|| fp_model
== ARM_FLOAT_FPA
))
2381 set_gdbarch_double_format (gdbarch
,
2382 &floatformat_ieee_double_littlebyte_bigword
);
2383 set_gdbarch_long_double_format
2384 (gdbarch
, &floatformat_ieee_double_littlebyte_bigword
);
2388 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_little
);
2389 set_gdbarch_long_double_format (gdbarch
,
2390 &floatformat_ieee_double_little
);
2395 set_fp_model_sfunc (char *args
, int from_tty
,
2396 struct cmd_list_element
*c
)
2398 enum arm_float_model fp_model
;
2400 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
2401 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
2403 arm_fp_model
= fp_model
;
2407 if (fp_model
== ARM_FLOAT_LAST
)
2408 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
2411 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2412 arm_set_fp (current_gdbarch
);
2416 show_fp_model (struct ui_file
*file
, int from_tty
,
2417 struct cmd_list_element
*c
, const char *value
)
2419 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2421 deprecated_show_value_hack (file
, from_tty
, c
, value
);
2422 if (arm_fp_model
== ARM_FLOAT_AUTO
2423 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2424 /* i18n: "the default [floating point model] for the current ABI..." */
2425 printf_filtered (_(" - the default for the current ABI is \"%s\".\n"),
2426 fp_model_strings
[tdep
->fp_model
]);
2429 /* If the user changes the register disassembly style used for info
2430 register and other commands, we have to also switch the style used
2431 in opcodes for disassembly output. This function is run in the "set
2432 arm disassembly" command, and does that. */
2435 set_disassembly_style_sfunc (char *args
, int from_tty
,
2436 struct cmd_list_element
*c
)
2438 set_disassembly_style ();
2441 /* Return the ARM register name corresponding to register I. */
2443 arm_register_name (int i
)
2445 return arm_register_names
[i
];
2449 set_disassembly_style (void)
2451 const char *setname
, *setdesc
, **regnames
;
2454 /* Find the style that the user wants in the opcodes table. */
2456 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2457 while ((disassembly_style
!= setname
)
2458 && (current
< num_disassembly_options
))
2459 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2460 current_option
= current
;
2462 /* Fill our copy. */
2463 for (j
= 0; j
< numregs
; j
++)
2464 arm_register_names
[j
] = (char *) regnames
[j
];
2467 if (isupper (*regnames
[ARM_PC_REGNUM
]))
2469 arm_register_names
[ARM_FPS_REGNUM
] = "FPS";
2470 arm_register_names
[ARM_PS_REGNUM
] = "CPSR";
2474 arm_register_names
[ARM_FPS_REGNUM
] = "fps";
2475 arm_register_names
[ARM_PS_REGNUM
] = "cpsr";
2478 /* Synchronize the disassembler. */
2479 set_arm_regname_option (current
);
2482 /* Test whether the coff symbol specific value corresponds to a Thumb
2486 coff_sym_is_thumb (int val
)
2488 return (val
== C_THUMBEXT
||
2489 val
== C_THUMBSTAT
||
2490 val
== C_THUMBEXTFUNC
||
2491 val
== C_THUMBSTATFUNC
||
2492 val
== C_THUMBLABEL
);
2495 /* arm_coff_make_msymbol_special()
2496 arm_elf_make_msymbol_special()
2498 These functions test whether the COFF or ELF symbol corresponds to
2499 an address in thumb code, and set a "special" bit in a minimal
2500 symbol to indicate that it does. */
2503 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2505 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2507 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2509 MSYMBOL_SET_SPECIAL (msym
);
2513 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2515 if (coff_sym_is_thumb (val
))
2516 MSYMBOL_SET_SPECIAL (msym
);
2520 arm_write_pc (CORE_ADDR pc
, ptid_t ptid
)
2522 write_register_pid (ARM_PC_REGNUM
, pc
, ptid
);
2524 /* If necessary, set the T bit. */
2527 CORE_ADDR val
= read_register_pid (ARM_PS_REGNUM
, ptid
);
2528 if (arm_pc_is_thumb (pc
))
2529 write_register_pid (ARM_PS_REGNUM
, val
| 0x20, ptid
);
2531 write_register_pid (ARM_PS_REGNUM
, val
& ~(CORE_ADDR
) 0x20, ptid
);
2535 static enum gdb_osabi
2536 arm_elf_osabi_sniffer (bfd
*abfd
)
2538 unsigned int elfosabi
, eflags
;
2539 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2541 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2546 /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the
2547 file are conforming to the base specification for that machine
2548 (there are no OS-specific extensions). In order to determine the
2549 real OS in use we must look for OS notes that have been added. */
2550 bfd_map_over_sections (abfd
,
2551 generic_elf_osabi_sniff_abi_tag_sections
,
2553 if (osabi
== GDB_OSABI_UNKNOWN
)
2555 /* Existing ARM tools don't set this field, so look at the EI_FLAGS
2556 field for more information. */
2557 eflags
= EF_ARM_EABI_VERSION(elf_elfheader(abfd
)->e_flags
);
2560 case EF_ARM_EABI_VER1
:
2561 osabi
= GDB_OSABI_ARM_EABI_V1
;
2564 case EF_ARM_EABI_VER2
:
2565 osabi
= GDB_OSABI_ARM_EABI_V2
;
2568 case EF_ARM_EABI_UNKNOWN
:
2569 /* Assume GNU tools. */
2570 osabi
= GDB_OSABI_ARM_APCS
;
2574 internal_error (__FILE__
, __LINE__
,
2576 arm_elf_osabi_sniffer: Unknown ARM EABI version 0x%x"),
2583 /* GNU tools use this value. Check note sections in this case,
2585 bfd_map_over_sections (abfd
,
2586 generic_elf_osabi_sniff_abi_tag_sections
,
2588 if (osabi
== GDB_OSABI_UNKNOWN
)
2590 /* Assume APCS ABI. */
2591 osabi
= GDB_OSABI_ARM_APCS
;
2595 case ELFOSABI_FREEBSD
:
2596 osabi
= GDB_OSABI_FREEBSD_ELF
;
2599 case ELFOSABI_NETBSD
:
2600 osabi
= GDB_OSABI_NETBSD_ELF
;
2603 case ELFOSABI_LINUX
:
2604 osabi
= GDB_OSABI_LINUX
;
2612 /* Initialize the current architecture based on INFO. If possible,
2613 re-use an architecture from ARCHES, which is a list of
2614 architectures already created during this debugging session.
2616 Called e.g. at program startup, when reading a core file, and when
2617 reading a binary file. */
2619 static struct gdbarch
*
2620 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2622 struct gdbarch_tdep
*tdep
;
2623 struct gdbarch
*gdbarch
;
2625 /* Try to deterimine the ABI of the object we are loading. */
2627 if (info
.abfd
!= NULL
&& info
.osabi
== GDB_OSABI_UNKNOWN
)
2629 switch (bfd_get_flavour (info
.abfd
))
2631 case bfd_target_aout_flavour
:
2632 /* Assume it's an old APCS-style ABI. */
2633 info
.osabi
= GDB_OSABI_ARM_APCS
;
2636 case bfd_target_coff_flavour
:
2637 /* Assume it's an old APCS-style ABI. */
2639 info
.osabi
= GDB_OSABI_ARM_APCS
;
2643 /* Leave it as "unknown". */
2648 /* If there is already a candidate, use it. */
2649 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2651 return arches
->gdbarch
;
2653 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
2654 gdbarch
= gdbarch_alloc (&info
, tdep
);
2656 /* We used to default to FPA for generic ARM, but almost nobody uses that
2657 now, and we now provide a way for the user to force the model. So
2658 default to the most useful variant. */
2659 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
2662 switch (info
.byte_order
)
2664 case BFD_ENDIAN_BIG
:
2665 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
2666 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
2667 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
2668 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
2672 case BFD_ENDIAN_LITTLE
:
2673 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
2674 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
2675 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
2676 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
2681 internal_error (__FILE__
, __LINE__
,
2682 _("arm_gdbarch_init: bad byte order for float format"));
2685 /* On ARM targets char defaults to unsigned. */
2686 set_gdbarch_char_signed (gdbarch
, 0);
2688 /* This should be low enough for everything. */
2689 tdep
->lowest_pc
= 0x20;
2690 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
2692 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
2694 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
2696 /* Frame handling. */
2697 set_gdbarch_unwind_dummy_id (gdbarch
, arm_unwind_dummy_id
);
2698 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
2699 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
2701 frame_base_set_default (gdbarch
, &arm_normal_base
);
2703 /* Address manipulation. */
2704 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
2705 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
2707 /* Advance PC across function entry code. */
2708 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
2710 /* Get the PC when a frame might not be available. */
2711 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
, arm_saved_pc_after_call
);
2713 /* The stack grows downward. */
2714 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2716 /* Breakpoint manipulation. */
2717 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
2719 /* Information about registers, etc. */
2720 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
2721 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
2722 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
2723 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
2724 set_gdbarch_deprecated_register_byte (gdbarch
, arm_register_byte
);
2725 set_gdbarch_num_regs (gdbarch
, NUM_GREGS
+ NUM_FREGS
+ NUM_SREGS
);
2726 set_gdbarch_register_type (gdbarch
, arm_register_type
);
2728 /* Internal <-> external register number maps. */
2729 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
2731 /* Integer registers are 4 bytes. */
2732 set_gdbarch_deprecated_register_size (gdbarch
, 4);
2733 set_gdbarch_register_name (gdbarch
, arm_register_name
);
2735 /* Returning results. */
2736 set_gdbarch_extract_return_value (gdbarch
, arm_extract_return_value
);
2737 set_gdbarch_store_return_value (gdbarch
, arm_store_return_value
);
2738 set_gdbarch_deprecated_use_struct_convention (gdbarch
, arm_use_struct_convention
);
2739 set_gdbarch_deprecated_extract_struct_value_address (gdbarch
, arm_extract_struct_value_address
);
2741 /* Single stepping. */
2742 /* XXX For an RDI target we should ask the target if it can single-step. */
2743 set_gdbarch_software_single_step (gdbarch
, arm_software_single_step
);
2746 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
2748 /* Minsymbol frobbing. */
2749 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
2750 set_gdbarch_coff_make_msymbol_special (gdbarch
,
2751 arm_coff_make_msymbol_special
);
2753 /* Hook in the ABI-specific overrides, if they have been registered. */
2754 gdbarch_init_osabi (info
, gdbarch
);
2756 /* Add some default predicates. */
2757 frame_unwind_append_sniffer (gdbarch
, arm_stub_unwind_sniffer
);
2758 frame_unwind_append_sniffer (gdbarch
, arm_sigtramp_unwind_sniffer
);
2759 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
2760 frame_unwind_append_sniffer (gdbarch
, arm_prologue_unwind_sniffer
);
2762 /* Now we have tuned the configuration, set a few final things,
2763 based on what the OS ABI has told us. */
2765 if (tdep
->jb_pc
>= 0)
2766 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
2768 /* Floating point sizes and format. */
2769 switch (info
.byte_order
)
2771 case BFD_ENDIAN_BIG
:
2772 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
2773 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_big
);
2774 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
2778 case BFD_ENDIAN_LITTLE
:
2779 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
2780 arm_set_fp (gdbarch
);
2784 internal_error (__FILE__
, __LINE__
,
2785 _("arm_gdbarch_init: bad byte order for float format"));
2792 arm_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
2794 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2799 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
2800 (unsigned long) tdep
->lowest_pc
);
2804 arm_init_abi_eabi_v1 (struct gdbarch_info info
,
2805 struct gdbarch
*gdbarch
)
2811 arm_init_abi_eabi_v2 (struct gdbarch_info info
,
2812 struct gdbarch
*gdbarch
)
2818 arm_init_abi_apcs (struct gdbarch_info info
,
2819 struct gdbarch
*gdbarch
)
2824 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
2827 _initialize_arm_tdep (void)
2829 struct ui_file
*stb
;
2831 struct cmd_list_element
*new_set
, *new_show
;
2832 const char *setname
;
2833 const char *setdesc
;
2834 const char **regnames
;
2836 static char *helptext
;
2837 char regdesc
[1024], *rdptr
= regdesc
;
2838 size_t rest
= sizeof (regdesc
);
2840 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
2842 /* Register an ELF OS ABI sniffer for ARM binaries. */
2843 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
2844 bfd_target_elf_flavour
,
2845 arm_elf_osabi_sniffer
);
2847 /* Register some ABI variants for embedded systems. */
2848 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_EABI_V1
,
2849 arm_init_abi_eabi_v1
);
2850 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_EABI_V2
,
2851 arm_init_abi_eabi_v2
);
2852 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_APCS
,
2855 /* Get the number of possible sets of register names defined in opcodes. */
2856 num_disassembly_options
= get_arm_regname_num_options ();
2858 /* Add root prefix command for all "set arm"/"show arm" commands. */
2859 add_prefix_cmd ("arm", no_class
, set_arm_command
,
2860 _("Various ARM-specific commands."),
2861 &setarmcmdlist
, "set arm ", 0, &setlist
);
2863 add_prefix_cmd ("arm", no_class
, show_arm_command
,
2864 _("Various ARM-specific commands."),
2865 &showarmcmdlist
, "show arm ", 0, &showlist
);
2867 /* Sync the opcode insn printer with our register viewer. */
2868 parse_arm_disassembler_option ("reg-names-std");
2870 /* Initialize the array that will be passed to
2871 add_setshow_enum_cmd(). */
2872 valid_disassembly_styles
2873 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
2874 for (i
= 0; i
< num_disassembly_options
; i
++)
2876 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
2877 valid_disassembly_styles
[i
] = setname
;
2878 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
2881 /* Copy the default names (if found) and synchronize disassembler. */
2882 if (!strcmp (setname
, "std"))
2884 disassembly_style
= setname
;
2886 for (j
= 0; j
< numregs
; j
++)
2887 arm_register_names
[j
] = (char *) regnames
[j
];
2888 set_arm_regname_option (i
);
2891 /* Mark the end of valid options. */
2892 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
2894 /* Create the help text. */
2895 stb
= mem_fileopen ();
2896 fprintf_unfiltered (stb
, "%s%s%s",
2897 _("The valid values are:\n"),
2899 _("The default is \"std\"."));
2900 helptext
= ui_file_xstrdup (stb
, &length
);
2901 ui_file_delete (stb
);
2903 add_setshow_enum_cmd("disassembler", no_class
,
2904 valid_disassembly_styles
, &disassembly_style
,
2905 _("Set the disassembly style."),
2906 _("Show the disassembly style."),
2908 set_disassembly_style_sfunc
,
2909 NULL
, /* FIXME: i18n: The disassembly style is \"%s\". */
2910 &setarmcmdlist
, &showarmcmdlist
);
2912 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
2913 _("Set usage of ARM 32-bit mode."),
2914 _("Show usage of ARM 32-bit mode."),
2915 _("When off, a 26-bit PC will be used."),
2917 NULL
, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
2918 &setarmcmdlist
, &showarmcmdlist
);
2920 /* Add a command to allow the user to force the FPU model. */
2921 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
2922 _("Set the floating point type."),
2923 _("Show the floating point type."),
2924 _("auto - Determine the FP typefrom the OS-ABI.\n\
2925 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
2926 fpa - FPA co-processor (GCC compiled).\n\
2927 softvfp - Software FP with pure-endian doubles.\n\
2928 vfp - VFP co-processor."),
2929 set_fp_model_sfunc
, show_fp_model
,
2930 &setarmcmdlist
, &showarmcmdlist
);
2932 /* Debugging flag. */
2933 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
2934 _("Set ARM debugging."),
2935 _("Show ARM debugging."),
2936 _("When on, arm-specific debugging is enabled."),
2938 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
2939 &setdebuglist
, &showdebuglist
);