1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "coff/internal.h" /* Internal format of COFF symbols in BFD */
30 #include "dis-asm.h" /* For register flavors. */
31 #include <ctype.h> /* for isupper () */
35 #include "solib-svr4.h"
37 #include "coff/internal.h"
39 /* Each OS has a different mechanism for accessing the various
40 registers stored in the sigcontext structure.
42 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
43 function pointer) which may be used to determine the addresses
44 of the various saved registers in the sigcontext structure.
46 For the ARM target, there are three parameters to this function.
47 The first is the pc value of the frame under consideration, the
48 second the stack pointer of this frame, and the last is the
49 register number to fetch.
51 If the tm.h file does not define this macro, then it's assumed that
52 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
55 When it comes time to multi-arching this code, see the identically
56 named machinery in ia64-tdep.c for an example of how it could be
57 done. It should not be necessary to modify the code below where
58 this macro is used. */
60 #ifdef SIGCONTEXT_REGISTER_ADDRESS
61 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
62 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
65 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
66 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
69 /* Macros for setting and testing a bit in a minimal symbol that marks
70 it as Thumb function. The MSB of the minimal symbol's "info" field
71 is used for this purpose. This field is already being used to store
72 the symbol size, so the assumption is that the symbol size cannot
75 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
76 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol.
77 MSYMBOL_SIZE Returns the size of the minimal symbol,
78 i.e. the "info" field with the "special" bit
81 #define MSYMBOL_SET_SPECIAL(msym) \
82 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
85 #define MSYMBOL_IS_SPECIAL(msym) \
86 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
88 #define MSYMBOL_SIZE(msym) \
89 ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
91 /* Number of different reg name sets (options). */
92 static int num_flavor_options
;
94 /* We have more registers than the disassembler as gdb can print the value
95 of special registers as well.
96 The general register names are overwritten by whatever is being used by
97 the disassembler at the moment. We also adjust the case of cpsr and fps. */
99 /* Initial value: Register names used in ARM's ISA documentation. */
100 static char * arm_register_name_strings
[] =
101 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
102 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
103 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
104 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
105 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
106 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
107 "fps", "cpsr" }; /* 24 25 */
108 static char **arm_register_names
= arm_register_name_strings
;
110 /* Valid register name flavors. */
111 static const char **valid_flavors
;
113 /* Disassembly flavor to use. Default to "std" register names. */
114 static const char *disassembly_flavor
;
115 static int current_option
; /* Index to that option in the opcodes table. */
117 /* This is used to keep the bfd arch_info in sync with the disassembly
119 static void set_disassembly_flavor_sfunc(char *, int,
120 struct cmd_list_element
*);
121 static void set_disassembly_flavor (void);
123 static void convert_from_extended (void *ptr
, void *dbl
);
125 /* Define other aspects of the stack frame. We keep the offsets of
126 all saved registers, 'cause we need 'em a lot! We also keep the
127 current size of the stack frame, and the offset of the frame
128 pointer from the stack pointer (for frameless functions, and when
129 we're still in the prologue of a function with a frame) */
131 struct frame_extra_info
138 /* Addresses for calling Thumb functions have the bit 0 set.
139 Here are some macros to test, set, or clear bit 0 of addresses. */
140 #define IS_THUMB_ADDR(addr) ((addr) & 1)
141 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
142 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
144 /* Will a function return an aggregate type in memory or in a
145 register? Return 0 if an aggregate type can be returned in a
146 register, 1 if it must be returned in memory. */
149 arm_use_struct_convention (int gcc_p
, struct type
*type
)
152 register enum type_code code
;
154 /* In the ARM ABI, "integer" like aggregate types are returned in
155 registers. For an aggregate type to be integer like, its size
156 must be less than or equal to REGISTER_SIZE and the offset of
157 each addressable subfield must be zero. Note that bit fields are
158 not addressable, and all addressable subfields of unions always
159 start at offset zero.
161 This function is based on the behaviour of GCC 2.95.1.
162 See: gcc/arm.c: arm_return_in_memory() for details.
164 Note: All versions of GCC before GCC 2.95.2 do not set up the
165 parameters correctly for a function returning the following
166 structure: struct { float f;}; This should be returned in memory,
167 not a register. Richard Earnshaw sent me a patch, but I do not
168 know of any way to detect if a function like the above has been
169 compiled with the correct calling convention. */
171 /* All aggregate types that won't fit in a register must be returned
173 if (TYPE_LENGTH (type
) > REGISTER_SIZE
)
178 /* The only aggregate types that can be returned in a register are
179 structs and unions. Arrays must be returned in memory. */
180 code
= TYPE_CODE (type
);
181 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
186 /* Assume all other aggregate types can be returned in a register.
187 Run a check for structures, unions and arrays. */
190 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
193 /* Need to check if this struct/union is "integer" like. For
194 this to be true, its size must be less than or equal to
195 REGISTER_SIZE and the offset of each addressable subfield
196 must be zero. Note that bit fields are not addressable, and
197 unions always start at offset zero. If any of the subfields
198 is a floating point type, the struct/union cannot be an
201 /* For each field in the object, check:
202 1) Is it FP? --> yes, nRc = 1;
203 2) Is it addressable (bitpos != 0) and
204 not packed (bitsize == 0)?
208 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
210 enum type_code field_type_code
;
211 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
213 /* Is it a floating point type field? */
214 if (field_type_code
== TYPE_CODE_FLT
)
220 /* If bitpos != 0, then we have to care about it. */
221 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
223 /* Bitfields are not addressable. If the field bitsize is
224 zero, then the field is not packed. Hence it cannot be
225 a bitfield or any other packed type. */
226 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
239 arm_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*thisframe
)
241 return (chain
!= 0 && (FRAME_SAVED_PC (thisframe
) >= LOWEST_PC
));
244 /* Set to true if the 32-bit mode is in use. */
248 /* Flag set by arm_fix_call_dummy that tells whether the target
249 function is a Thumb function. This flag is checked by
250 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
251 its use in valops.c) to pass the function address as an additional
254 static int target_is_thumb
;
256 /* Flag set by arm_fix_call_dummy that tells whether the calling
257 function is a Thumb function. This flag is checked by
258 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
260 static int caller_is_thumb
;
262 /* Determine if the program counter specified in MEMADDR is in a Thumb
266 arm_pc_is_thumb (CORE_ADDR memaddr
)
268 struct minimal_symbol
*sym
;
270 /* If bit 0 of the address is set, assume this is a Thumb address. */
271 if (IS_THUMB_ADDR (memaddr
))
274 /* Thumb functions have a "special" bit set in minimal symbols. */
275 sym
= lookup_minimal_symbol_by_pc (memaddr
);
278 return (MSYMBOL_IS_SPECIAL (sym
));
286 /* Determine if the program counter specified in MEMADDR is in a call
287 dummy being called from a Thumb function. */
290 arm_pc_is_thumb_dummy (CORE_ADDR memaddr
)
292 CORE_ADDR sp
= read_sp ();
294 /* FIXME: Until we switch for the new call dummy macros, this heuristic
295 is the best we can do. We are trying to determine if the pc is on
296 the stack, which (hopefully) will only happen in a call dummy.
297 We hope the current stack pointer is not so far alway from the dummy
298 frame location (true if we have not pushed large data structures or
299 gone too many levels deep) and that our 1024 is not enough to consider
300 code regions as part of the stack (true for most practical purposes) */
301 if (PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 1024))
302 return caller_is_thumb
;
307 /* Remove useless bits from addresses in a running program. */
309 arm_addr_bits_remove (CORE_ADDR val
)
311 if (arm_pc_is_thumb (val
))
312 return (val
& (arm_apcs_32
? 0xfffffffe : 0x03fffffe));
314 return (val
& (arm_apcs_32
? 0xfffffffc : 0x03fffffc));
317 /* When reading symbols, we need to zap the low bit of the address,
318 which may be set to 1 for Thumb functions. */
320 arm_smash_text_address (CORE_ADDR val
)
326 arm_saved_pc_after_call (struct frame_info
*frame
)
328 return ADDR_BITS_REMOVE (read_register (LR_REGNUM
));
331 /* Determine whether the function invocation represented by FI has a
332 frame on the stack associated with it. If it does return zero,
333 otherwise return 1. */
336 arm_frameless_function_invocation (struct frame_info
*fi
)
338 CORE_ADDR func_start
, after_prologue
;
341 /* Sometimes we have functions that do a little setup (like saving the
342 vN registers with the stmdb instruction, but DO NOT set up a frame.
343 The symbol table will report this as a prologue. However, it is
344 important not to try to parse these partial frames as frames, or we
345 will get really confused.
347 So I will demand 3 instructions between the start & end of the
348 prologue before I call it a real prologue, i.e. at least
353 func_start
= (get_pc_function_start ((fi
)->pc
) + FUNCTION_START_OFFSET
);
354 after_prologue
= SKIP_PROLOGUE (func_start
);
356 /* There are some frameless functions whose first two instructions
357 follow the standard APCS form, in which case after_prologue will
358 be func_start + 8. */
360 frameless
= (after_prologue
< func_start
+ 12);
364 /* The address of the arguments in the frame. */
366 arm_frame_args_address (struct frame_info
*fi
)
371 /* The address of the local variables in the frame. */
373 arm_frame_locals_address (struct frame_info
*fi
)
378 /* The number of arguments being passed in the frame. */
380 arm_frame_num_args (struct frame_info
*fi
)
382 /* We have no way of knowing. */
386 /* A typical Thumb prologue looks like this:
390 Sometimes the latter instruction may be replaced by:
398 or, on tpcs, like this:
405 There is always one instruction of three classes:
410 When we have found at least one of each class we are done with the prolog.
411 Note that the "sub sp, #NN" before the push does not count.
415 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
417 CORE_ADDR current_pc
;
418 int findmask
= 0; /* findmask:
419 bit 0 - push { rlist }
420 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
421 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
424 for (current_pc
= pc
; current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40; current_pc
+= 2)
426 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
428 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
430 findmask
|= 1; /* push found */
432 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
434 if ((findmask
& 1) == 0) /* before push ? */
437 findmask
|= 4; /* add/sub sp found */
439 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
441 findmask
|= 2; /* setting of r7 found */
443 else if (insn
== 0x466f) /* mov r7, sp */
445 findmask
|= 2; /* setting of r7 found */
447 else if (findmask
== (4+2+1))
449 break; /* We have found one of each type of prologue instruction */
452 continue; /* something in the prolog that we don't care about or some
453 instruction from outside the prolog scheduled here for optimization */
459 /* The APCS (ARM Procedure Call Standard) defines the following
463 [stmfd sp!, {a1,a2,a3,a4}]
464 stmfd sp!, {...,fp,ip,lr,pc}
465 [stfe f7, [sp, #-12]!]
466 [stfe f6, [sp, #-12]!]
467 [stfe f5, [sp, #-12]!]
468 [stfe f4, [sp, #-12]!]
469 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
472 arm_skip_prologue (CORE_ADDR pc
)
476 CORE_ADDR func_addr
, func_end
;
478 struct symtab_and_line sal
;
480 /* See what the symbol table says. */
482 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
486 /* Found a function. */
487 sym
= lookup_symbol (func_name
, NULL
, VAR_NAMESPACE
, NULL
, NULL
);
488 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
490 /* Don't use this trick for assembly source files. */
491 sal
= find_pc_line (func_addr
, 0);
492 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
497 /* Check if this is Thumb code. */
498 if (arm_pc_is_thumb (pc
))
499 return thumb_skip_prologue (pc
, func_end
);
501 /* Can't find the prologue end in the symbol table, try it the hard way
502 by disassembling the instructions. */
504 inst
= read_memory_integer (skip_pc
, 4);
505 if (inst
!= 0xe1a0c00d) /* mov ip, sp */
509 inst
= read_memory_integer (skip_pc
, 4);
510 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
513 inst
= read_memory_integer (skip_pc
, 4);
516 if ((inst
& 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */
520 inst
= read_memory_integer (skip_pc
, 4);
522 /* Any insns after this point may float into the code, if it makes
523 for better instruction scheduling, so we skip them only if we
524 find them, but still consdier the function to be frame-ful. */
526 /* We may have either one sfmfd instruction here, or several stfe
527 insns, depending on the version of floating point code we
529 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
532 inst
= read_memory_integer (skip_pc
, 4);
536 while ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
539 inst
= read_memory_integer (skip_pc
, 4);
543 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
549 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
550 This function decodes a Thumb function prologue to determine:
551 1) the size of the stack frame
552 2) which registers are saved on it
553 3) the offsets of saved regs
554 4) the offset from the stack pointer to the frame pointer
555 This information is stored in the "extra" fields of the frame_info.
557 A typical Thumb function prologue would create this stack frame
558 (offsets relative to FP)
559 old SP -> 24 stack parameters
562 R7 -> 0 local variables (16 bytes)
563 SP -> -12 additional stack space (12 bytes)
564 The frame size would thus be 36 bytes, and the frame offset would be
565 12 bytes. The frame register is R7.
567 The comments for thumb_skip_prolog() describe the algorithm we use to detect
568 the end of the prolog */
572 thumb_scan_prologue (struct frame_info
*fi
)
574 CORE_ADDR prologue_start
;
575 CORE_ADDR prologue_end
;
576 CORE_ADDR current_pc
;
577 int saved_reg
[16]; /* which register has been copied to register n? */
578 int findmask
= 0; /* findmask:
579 bit 0 - push { rlist }
580 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
581 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
585 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
587 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
589 if (sal
.line
== 0) /* no line info, use current PC */
590 prologue_end
= fi
->pc
;
591 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
592 prologue_end
= sal
.end
; /* (probably means no prologue) */
595 prologue_end
= prologue_start
+ 40; /* We're in the boondocks: allow for */
596 /* 16 pushes, an add, and "mv fp,sp" */
598 prologue_end
= min (prologue_end
, fi
->pc
);
600 /* Initialize the saved register map. When register H is copied to
601 register L, we will put H in saved_reg[L]. */
602 for (i
= 0; i
< 16; i
++)
605 /* Search the prologue looking for instructions that set up the
606 frame pointer, adjust the stack pointer, and save registers.
607 Do this until all basic prolog instructions are found. */
609 fi
->extra_info
->framesize
= 0;
610 for (current_pc
= prologue_start
;
611 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
618 insn
= read_memory_unsigned_integer (current_pc
, 2);
620 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
623 findmask
|= 1; /* push found */
624 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
625 whether to save LR (R14). */
626 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
628 /* Calculate offsets of saved R0-R7 and LR. */
629 for (regno
= LR_REGNUM
; regno
>= 0; regno
--)
630 if (mask
& (1 << regno
))
632 fi
->extra_info
->framesize
+= 4;
633 fi
->saved_regs
[saved_reg
[regno
]] =
634 -(fi
->extra_info
->framesize
);
635 saved_reg
[regno
] = regno
; /* reset saved register map */
638 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
640 if ((findmask
& 1) == 0) /* before push ? */
643 findmask
|= 4; /* add/sub sp found */
645 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
646 if (insn
& 0x80) /* is it signed? (==subtracting) */
648 fi
->extra_info
->frameoffset
+= offset
;
651 fi
->extra_info
->framesize
-= offset
;
653 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
655 findmask
|= 2; /* setting of r7 found */
656 fi
->extra_info
->framereg
= THUMB_FP_REGNUM
;
657 /* get scaled offset */
658 fi
->extra_info
->frameoffset
= (insn
& 0xff) << 2;
660 else if (insn
== 0x466f) /* mov r7, sp */
662 findmask
|= 2; /* setting of r7 found */
663 fi
->extra_info
->framereg
= THUMB_FP_REGNUM
;
664 fi
->extra_info
->frameoffset
= 0;
665 saved_reg
[THUMB_FP_REGNUM
] = SP_REGNUM
;
667 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
669 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
670 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
671 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
674 continue; /* something in the prolog that we don't care about or some
675 instruction from outside the prolog scheduled here for optimization */
679 /* Check if prologue for this frame's PC has already been scanned. If
680 it has, copy the relevant information about that prologue and
681 return non-zero. Otherwise do not copy anything and return zero.
683 The information saved in the cache includes:
684 * the frame register number;
685 * the size of the stack frame;
686 * the offsets of saved regs (relative to the old SP); and
687 * the offset from the stack pointer to the frame pointer
689 The cache contains only one entry, since this is adequate for the
690 typical sequence of prologue scan requests we get. When performing
691 a backtrace, GDB will usually ask to scan the same function twice
692 in a row (once to get the frame chain, and once to fill in the
693 extra frame information). */
695 static struct frame_info prologue_cache
;
698 check_prologue_cache (struct frame_info
*fi
)
702 if (fi
->pc
== prologue_cache
.pc
)
704 fi
->extra_info
->framereg
= prologue_cache
.extra_info
->framereg
;
705 fi
->extra_info
->framesize
= prologue_cache
.extra_info
->framesize
;
706 fi
->extra_info
->frameoffset
= prologue_cache
.extra_info
->frameoffset
;
707 for (i
= 0; i
< NUM_REGS
+ NUM_PSEUDO_REGS
; i
++)
708 fi
->saved_regs
[i
] = prologue_cache
.saved_regs
[i
];
716 /* Copy the prologue information from fi to the prologue cache. */
719 save_prologue_cache (struct frame_info
*fi
)
723 prologue_cache
.pc
= fi
->pc
;
724 prologue_cache
.extra_info
->framereg
= fi
->extra_info
->framereg
;
725 prologue_cache
.extra_info
->framesize
= fi
->extra_info
->framesize
;
726 prologue_cache
.extra_info
->frameoffset
= fi
->extra_info
->frameoffset
;
728 for (i
= 0; i
< NUM_REGS
+ NUM_PSEUDO_REGS
; i
++)
729 prologue_cache
.saved_regs
[i
] = fi
->saved_regs
[i
];
733 /* This function decodes an ARM function prologue to determine:
734 1) the size of the stack frame
735 2) which registers are saved on it
736 3) the offsets of saved regs
737 4) the offset from the stack pointer to the frame pointer
738 This information is stored in the "extra" fields of the frame_info.
740 There are two basic forms for the ARM prologue. The fixed argument
741 function call will look like:
744 stmfd sp!, {fp, ip, lr, pc}
748 Which would create this stack frame (offsets relative to FP):
749 IP -> 4 (caller's stack)
750 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
751 -4 LR (return address in caller)
752 -8 IP (copy of caller's SP)
754 SP -> -28 Local variables
756 The frame size would thus be 32 bytes, and the frame offset would be
757 28 bytes. The stmfd call can also save any of the vN registers it
758 plans to use, which increases the frame size accordingly.
760 Note: The stored PC is 8 off of the STMFD instruction that stored it
761 because the ARM Store instructions always store PC + 8 when you read
764 A variable argument function call will look like:
767 stmfd sp!, {a1, a2, a3, a4}
768 stmfd sp!, {fp, ip, lr, pc}
771 Which would create this stack frame (offsets relative to FP):
772 IP -> 20 (caller's stack)
777 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
778 -4 LR (return address in caller)
779 -8 IP (copy of caller's SP)
781 SP -> -28 Local variables
783 The frame size would thus be 48 bytes, and the frame offset would be
786 There is another potential complication, which is that the optimizer
787 will try to separate the store of fp in the "stmfd" instruction from
788 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
789 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
791 Also, note, the original version of the ARM toolchain claimed that there
794 instruction at the end of the prologue. I have never seen GCC produce
795 this, and the ARM docs don't mention it. We still test for it below in
801 arm_scan_prologue (struct frame_info
*fi
)
803 int regno
, sp_offset
, fp_offset
;
804 LONGEST return_value
;
805 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
807 /* Check if this function is already in the cache of frame information. */
808 if (check_prologue_cache (fi
))
811 /* Assume there is no frame until proven otherwise. */
812 fi
->extra_info
->framereg
= SP_REGNUM
;
813 fi
->extra_info
->framesize
= 0;
814 fi
->extra_info
->frameoffset
= 0;
816 /* Check for Thumb prologue. */
817 if (arm_pc_is_thumb (fi
->pc
))
819 thumb_scan_prologue (fi
);
820 save_prologue_cache (fi
);
824 /* Find the function prologue. If we can't find the function in
825 the symbol table, peek in the stack frame to find the PC. */
826 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
828 /* One way to find the end of the prologue (which works well
829 for unoptimized code) is to do the following:
831 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
834 prologue_end = fi->pc;
835 else if (sal.end < prologue_end)
836 prologue_end = sal.end;
838 This mechanism is very accurate so long as the optimizer
839 doesn't move any instructions from the function body into the
840 prologue. If this happens, sal.end will be the last
841 instruction in the first hunk of prologue code just before
842 the first instruction that the scheduler has moved from
843 the body to the prologue.
845 In order to make sure that we scan all of the prologue
846 instructions, we use a slightly less accurate mechanism which
847 may scan more than necessary. To help compensate for this
848 lack of accuracy, the prologue scanning loop below contains
849 several clauses which'll cause the loop to terminate early if
850 an implausible prologue instruction is encountered.
856 is a suitable endpoint since it accounts for the largest
857 possible prologue plus up to five instructions inserted by
860 if (prologue_end
> prologue_start
+ 64)
862 prologue_end
= prologue_start
+ 64; /* See above. */
867 /* Get address of the stmfd in the prologue of the callee; the saved
868 PC is the address of the stmfd + 8. */
869 if (!safe_read_memory_integer (fi
->frame
, 4, &return_value
))
873 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
874 prologue_end
= prologue_start
+ 64; /* See above. */
878 /* Now search the prologue looking for instructions that set up the
879 frame pointer, adjust the stack pointer, and save registers.
881 Be careful, however, and if it doesn't look like a prologue,
882 don't try to scan it. If, for instance, a frameless function
883 begins with stmfd sp!, then we will tell ourselves there is
884 a frame, which will confuse stack traceback, as well ad"finish"
885 and other operations that rely on a knowledge of the stack
888 In the APCS, the prologue should start with "mov ip, sp" so
889 if we don't see this as the first insn, we will stop. [Note:
890 This doesn't seem to be true any longer, so it's now an optional
891 part of the prologue. - Kevin Buettner, 2001-11-20] */
893 sp_offset
= fp_offset
= 0;
895 if (read_memory_unsigned_integer (prologue_start
, 4)
896 == 0xe1a0c00d) /* mov ip, sp */
897 current_pc
= prologue_start
+ 4;
899 current_pc
= prologue_start
;
901 for (; current_pc
< prologue_end
; current_pc
+= 4)
903 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
905 if ((insn
& 0xffff0000) == 0xe92d0000)
906 /* stmfd sp!, {..., fp, ip, lr, pc}
908 stmfd sp!, {a1, a2, a3, a4} */
910 int mask
= insn
& 0xffff;
912 /* Calculate offsets of saved registers. */
913 for (regno
= PC_REGNUM
; regno
>= 0; regno
--)
914 if (mask
& (1 << regno
))
917 fi
->saved_regs
[regno
] = sp_offset
;
920 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
922 unsigned imm
= insn
& 0xff; /* immediate value */
923 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
924 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
926 fi
->extra_info
->framereg
= FP_REGNUM
;
928 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
930 unsigned imm
= insn
& 0xff; /* immediate value */
931 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
932 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
935 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
938 regno
= F0_REGNUM
+ ((insn
>> 12) & 0x07);
939 fi
->saved_regs
[regno
] = sp_offset
;
941 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
944 unsigned int fp_start_reg
, fp_bound_reg
;
946 if ((insn
& 0x800) == 0x800) /* N0 is set */
948 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
955 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
961 fp_start_reg
= F0_REGNUM
+ ((insn
>> 12) & 0x7);
962 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
963 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
966 fi
->saved_regs
[fp_start_reg
++] = sp_offset
;
969 else if ((insn
& 0xf0000000) != 0xe0000000)
970 break; /* Condition not true, exit early */
971 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
972 break; /* Don't scan past a block load */
974 /* The optimizer might shove anything into the prologue,
975 so we just skip what we don't recognize. */
979 /* The frame size is just the negative of the offset (from the original SP)
980 of the last thing thing we pushed on the stack. The frame offset is
981 [new FP] - [new SP]. */
982 fi
->extra_info
->framesize
= -sp_offset
;
983 if (fi
->extra_info
->framereg
== FP_REGNUM
)
984 fi
->extra_info
->frameoffset
= fp_offset
- sp_offset
;
986 fi
->extra_info
->frameoffset
= 0;
988 save_prologue_cache (fi
);
991 /* Find REGNUM on the stack. Otherwise, it's in an active register.
992 One thing we might want to do here is to check REGNUM against the
993 clobber mask, and somehow flag it as invalid if it isn't saved on
994 the stack somewhere. This would provide a graceful failure mode
995 when trying to get the value of caller-saves registers for an inner
999 arm_find_callers_reg (struct frame_info
*fi
, int regnum
)
1001 for (; fi
; fi
= fi
->next
)
1003 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1004 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1005 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
1008 if (fi
->saved_regs
[regnum
] != 0)
1009 return read_memory_integer (fi
->saved_regs
[regnum
],
1010 REGISTER_RAW_SIZE (regnum
));
1011 return read_register (regnum
);
1013 /* Function: frame_chain Given a GDB frame, determine the address of
1014 the calling function's frame. This will be used to create a new
1015 GDB frame struct, and then INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC
1016 will be called for the new frame. For ARM, we save the frame size
1017 when we initialize the frame_info. */
1020 arm_frame_chain (struct frame_info
*fi
)
1022 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1023 CORE_ADDR fn_start
, callers_pc
, fp
;
1025 /* is this a dummy frame? */
1026 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1027 return fi
->frame
; /* dummy frame same as caller's frame */
1029 /* is caller-of-this a dummy frame? */
1030 callers_pc
= FRAME_SAVED_PC (fi
); /* find out who called us: */
1031 fp
= arm_find_callers_reg (fi
, FP_REGNUM
);
1032 if (PC_IN_CALL_DUMMY (callers_pc
, fp
, fp
))
1033 return fp
; /* dummy frame's frame may bear no relation to ours */
1035 if (find_pc_partial_function (fi
->pc
, 0, &fn_start
, 0))
1036 if (fn_start
== entry_point_address ())
1037 return 0; /* in _start fn, don't chain further */
1039 CORE_ADDR caller_pc
, fn_start
;
1040 int framereg
= fi
->extra_info
->framereg
;
1042 if (fi
->pc
< LOWEST_PC
)
1045 /* If the caller is the startup code, we're at the end of the chain. */
1046 caller_pc
= FRAME_SAVED_PC (fi
);
1047 if (find_pc_partial_function (caller_pc
, 0, &fn_start
, 0))
1048 if (fn_start
== entry_point_address ())
1051 /* If the caller is Thumb and the caller is ARM, or vice versa,
1052 the frame register of the caller is different from ours.
1053 So we must scan the prologue of the caller to determine its
1054 frame register number. */
1055 /* XXX Fixme, we should try to do this without creating a temporary
1057 if (arm_pc_is_thumb (caller_pc
) != arm_pc_is_thumb (fi
->pc
))
1059 struct frame_info caller_fi
;
1060 struct cleanup
*old_chain
;
1062 /* Create a temporary frame suitable for scanning the caller's
1064 memset (&caller_fi
, 0, sizeof (caller_fi
));
1065 caller_fi
.extra_info
= (struct frame_extra_info
*)
1066 xcalloc (1, sizeof (struct frame_extra_info
));
1067 old_chain
= make_cleanup (xfree
, caller_fi
.extra_info
);
1068 caller_fi
.saved_regs
= (CORE_ADDR
*)
1069 xcalloc (1, SIZEOF_FRAME_SAVED_REGS
);
1070 make_cleanup (xfree
, caller_fi
.saved_regs
);
1072 /* Now, scan the prologue and obtain the frame register. */
1073 caller_fi
.pc
= caller_pc
;
1074 arm_scan_prologue (&caller_fi
);
1075 framereg
= caller_fi
.extra_info
->framereg
;
1077 /* Deallocate the storage associated with the temporary frame
1079 do_cleanups (old_chain
);
1082 /* If the caller used a frame register, return its value.
1083 Otherwise, return the caller's stack pointer. */
1084 if (framereg
== FP_REGNUM
|| framereg
== THUMB_FP_REGNUM
)
1085 return arm_find_callers_reg (fi
, framereg
);
1087 return fi
->frame
+ fi
->extra_info
->framesize
;
1090 /* This function actually figures out the frame address for a given pc
1091 and sp. This is tricky because we sometimes don't use an explicit
1092 frame pointer, and the previous stack pointer isn't necessarily
1093 recorded on the stack. The only reliable way to get this info is
1094 to examine the prologue. FROMLEAF is a little confusing, it means
1095 this is the next frame up the chain AFTER a frameless function. If
1096 this is true, then the frame value for this frame is still in the
1100 arm_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1105 if (fi
->saved_regs
== NULL
)
1106 frame_saved_regs_zalloc (fi
);
1108 fi
->extra_info
= (struct frame_extra_info
*)
1109 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1111 fi
->extra_info
->framesize
= 0;
1112 fi
->extra_info
->frameoffset
= 0;
1113 fi
->extra_info
->framereg
= 0;
1116 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1118 memset (fi
->saved_regs
, '\000', sizeof fi
->saved_regs
);
1120 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1121 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1123 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1124 by assuming it's always FP. */
1125 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
, SP_REGNUM
);
1126 fi
->extra_info
->framesize
= 0;
1127 fi
->extra_info
->frameoffset
= 0;
1133 /* Compute stack pointer for this frame. We use this value for both the
1134 sigtramp and call dummy cases. */
1138 sp
= (fi
->next
->frame
- fi
->next
->extra_info
->frameoffset
1139 + fi
->next
->extra_info
->framesize
);
1141 /* Determine whether or not we're in a sigtramp frame.
1142 Unfortunately, it isn't sufficient to test
1143 fi->signal_handler_caller because this value is sometimes set
1144 after invoking INIT_EXTRA_FRAME_INFO. So we test *both*
1145 fi->signal_handler_caller and IN_SIGTRAMP to determine if we need
1146 to use the sigcontext addresses for the saved registers.
1148 Note: If an ARM IN_SIGTRAMP method ever needs to compare against
1149 the name of the function, the code below will have to be changed
1150 to first fetch the name of the function and then pass this name
1153 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1154 && (fi
->signal_handler_caller
|| IN_SIGTRAMP (fi
->pc
, (char *)0)))
1156 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1157 fi
->saved_regs
[reg
] = SIGCONTEXT_REGISTER_ADDRESS (sp
, fi
->pc
, reg
);
1159 /* FIXME: What about thumb mode? */
1160 fi
->extra_info
->framereg
= SP_REGNUM
;
1162 read_memory_integer (fi
->saved_regs
[fi
->extra_info
->framereg
],
1163 REGISTER_RAW_SIZE (fi
->extra_info
->framereg
));
1164 fi
->extra_info
->framesize
= 0;
1165 fi
->extra_info
->frameoffset
= 0;
1168 else if (PC_IN_CALL_DUMMY (fi
->pc
, sp
, fi
->frame
))
1171 CORE_ADDR callers_sp
;
1173 /* Set rp point at the high end of the saved registers. */
1174 rp
= fi
->frame
- REGISTER_SIZE
;
1176 /* Fill in addresses of saved registers. */
1177 fi
->saved_regs
[PS_REGNUM
] = rp
;
1178 rp
-= REGISTER_RAW_SIZE (PS_REGNUM
);
1179 for (reg
= PC_REGNUM
; reg
>= 0; reg
--)
1181 fi
->saved_regs
[reg
] = rp
;
1182 rp
-= REGISTER_RAW_SIZE (reg
);
1185 callers_sp
= read_memory_integer (fi
->saved_regs
[SP_REGNUM
],
1186 REGISTER_RAW_SIZE (SP_REGNUM
));
1187 fi
->extra_info
->framereg
= FP_REGNUM
;
1188 fi
->extra_info
->framesize
= callers_sp
- sp
;
1189 fi
->extra_info
->frameoffset
= fi
->frame
- sp
;
1193 arm_scan_prologue (fi
);
1196 /* this is the innermost frame? */
1197 fi
->frame
= read_register (fi
->extra_info
->framereg
);
1198 else if (fi
->extra_info
->framereg
== FP_REGNUM
1199 || fi
->extra_info
->framereg
== THUMB_FP_REGNUM
)
1201 /* not the innermost frame */
1202 /* If we have an FP, the callee saved it. */
1203 if (fi
->next
->saved_regs
[fi
->extra_info
->framereg
] != 0)
1205 read_memory_integer (fi
->next
1206 ->saved_regs
[fi
->extra_info
->framereg
], 4);
1208 /* If we were called by a frameless fn. then our frame is
1209 still in the frame pointer register on the board... */
1210 fi
->frame
= read_fp ();
1213 /* Calculate actual addresses of saved registers using offsets
1214 determined by arm_scan_prologue. */
1215 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1216 if (fi
->saved_regs
[reg
] != 0)
1217 fi
->saved_regs
[reg
] += (fi
->frame
+ fi
->extra_info
->framesize
1218 - fi
->extra_info
->frameoffset
);
1223 /* Find the caller of this frame. We do this by seeing if LR_REGNUM
1224 is saved in the stack anywhere, otherwise we get it from the
1227 The old definition of this function was a macro:
1228 #define FRAME_SAVED_PC(FRAME) \
1229 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1232 arm_frame_saved_pc (struct frame_info
*fi
)
1234 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1235 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1236 return generic_read_register_dummy (fi
->pc
, fi
->frame
, PC_REGNUM
);
1239 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
- fi
->extra_info
->frameoffset
,
1242 return read_memory_integer (fi
->saved_regs
[PC_REGNUM
],
1243 REGISTER_RAW_SIZE (PC_REGNUM
));
1247 CORE_ADDR pc
= arm_find_callers_reg (fi
, LR_REGNUM
);
1248 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1252 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1253 Examine the Program Status Register to decide which state we're in. */
1258 if (read_register (PS_REGNUM
) & 0x20) /* Bit 5 is Thumb state bit */
1259 return read_register (THUMB_FP_REGNUM
); /* R7 if Thumb */
1261 return read_register (FP_REGNUM
); /* R11 if ARM */
1264 /* Store into a struct frame_saved_regs the addresses of the saved
1265 registers of frame described by FRAME_INFO. This includes special
1266 registers such as PC and FP saved in special ways in the stack
1267 frame. SP is even more special: the address we return for it IS
1268 the sp for the next frame. */
1271 arm_frame_init_saved_regs (struct frame_info
*fip
)
1274 if (fip
->saved_regs
)
1277 arm_init_extra_frame_info (0, fip
);
1280 /* Push an empty stack frame, to record the current PC, etc. */
1283 arm_push_dummy_frame (void)
1285 CORE_ADDR old_sp
= read_register (SP_REGNUM
);
1286 CORE_ADDR sp
= old_sp
;
1287 CORE_ADDR fp
, prologue_start
;
1290 /* Push the two dummy prologue instructions in reverse order,
1291 so that they'll be in the correct low-to-high order in memory. */
1292 /* sub fp, ip, #4 */
1293 sp
= push_word (sp
, 0xe24cb004);
1294 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1295 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
1297 /* Push a pointer to the dummy prologue + 12, because when stm
1298 instruction stores the PC, it stores the address of the stm
1299 instruction itself plus 12. */
1300 fp
= sp
= push_word (sp
, prologue_start
+ 12);
1302 /* Push the processor status. */
1303 sp
= push_word (sp
, read_register (PS_REGNUM
));
1305 /* Push all 16 registers starting with r15. */
1306 for (regnum
= PC_REGNUM
; regnum
>= 0; regnum
--)
1307 sp
= push_word (sp
, read_register (regnum
));
1309 /* Update fp (for both Thumb and ARM) and sp. */
1310 write_register (FP_REGNUM
, fp
);
1311 write_register (THUMB_FP_REGNUM
, fp
);
1312 write_register (SP_REGNUM
, sp
);
1315 /* CALL_DUMMY_WORDS:
1316 This sequence of words is the instructions
1322 Note this is 12 bytes. */
1324 LONGEST arm_call_dummy_words
[] =
1326 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
1329 /* Fix up the call dummy, based on whether the processor is currently
1330 in Thumb or ARM mode, and whether the target function is Thumb or
1331 ARM. There are three different situations requiring three
1334 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1335 been copied into the dummy parameter to this function.
1336 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1337 "mov pc,r4" instruction patched to be a "bx r4" instead.
1338 * Thumb calling anything: uses the Thumb dummy defined below, which
1339 works for calling both ARM and Thumb functions.
1341 All three call dummies expect to receive the target function
1342 address in R4, with the low bit set if it's a Thumb function. */
1345 arm_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
1346 struct value
**args
, struct type
*type
, int gcc_p
)
1348 static short thumb_dummy
[4] =
1350 0xf000, 0xf801, /* bl label */
1351 0xdf18, /* swi 24 */
1352 0x4720, /* label: bx r4 */
1354 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
1356 /* Set flag indicating whether the current PC is in a Thumb function. */
1357 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
1359 /* If the target function is Thumb, set the low bit of the function
1360 address. And if the CPU is currently in ARM mode, patch the
1361 second instruction of call dummy to use a BX instruction to
1362 switch to Thumb mode. */
1363 target_is_thumb
= arm_pc_is_thumb (fun
);
1364 if (target_is_thumb
)
1367 if (!caller_is_thumb
)
1368 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
1371 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1372 instead of the ARM one that's already been copied. This will
1373 work for both Thumb and ARM target functions. */
1374 if (caller_is_thumb
)
1378 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
1380 for (i
= 0; i
< len
; i
++)
1382 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1383 p
+= sizeof (thumb_dummy
[0]);
1387 /* Put the target address in r4; the call dummy will copy this to
1389 write_register (4, fun
);
1392 /* Return the offset in the call dummy of the instruction that needs
1393 to have a breakpoint placed on it. This is the offset of the 'swi
1394 24' instruction, which is no longer actually used, but simply acts
1395 as a place-holder now.
1397 This implements the CALL_DUMMY_BREAK_OFFSET macro. */
1400 arm_call_dummy_breakpoint_offset (void)
1402 if (caller_is_thumb
)
1410 This function does not support passing parameters using the FPA
1411 variant of the APCS. It passes any floating point arguments in the
1412 general registers and/or on the stack. */
1415 arm_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
1416 int struct_return
, CORE_ADDR struct_addr
)
1419 int argnum
, argreg
, nstack_size
;
1421 /* Walk through the list of args and determine how large a temporary
1422 stack is required. Need to take care here as structs may be
1423 passed on the stack, and we have to to push them. */
1424 nstack_size
= -4 * REGISTER_SIZE
; /* Some arguments go into A1-A4. */
1425 if (struct_return
) /* The struct address goes in A1. */
1426 nstack_size
+= REGISTER_SIZE
;
1428 /* Walk through the arguments and add their size to nstack_size. */
1429 for (argnum
= 0; argnum
< nargs
; argnum
++)
1432 struct type
*arg_type
;
1434 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1435 len
= TYPE_LENGTH (arg_type
);
1437 /* ANSI C code passes float arguments as integers, K&R code
1438 passes float arguments as doubles. Correct for this here. */
1439 if (TYPE_CODE_FLT
== TYPE_CODE (arg_type
) && REGISTER_SIZE
== len
)
1440 nstack_size
+= FP_REGISTER_VIRTUAL_SIZE
;
1445 /* Allocate room on the stack, and initialize our stack frame
1448 if (nstack_size
> 0)
1454 /* Initialize the integer argument register pointer. */
1457 /* The struct_return pointer occupies the first parameter passing
1460 write_register (argreg
++, struct_addr
);
1462 /* Process arguments from left to right. Store as many as allowed
1463 in the parameter passing registers (A1-A4), and save the rest on
1464 the temporary stack. */
1465 for (argnum
= 0; argnum
< nargs
; argnum
++)
1470 enum type_code typecode
;
1471 struct type
*arg_type
, *target_type
;
1473 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1474 target_type
= TYPE_TARGET_TYPE (arg_type
);
1475 len
= TYPE_LENGTH (arg_type
);
1476 typecode
= TYPE_CODE (arg_type
);
1477 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
1479 /* ANSI C code passes float arguments as integers, K&R code
1480 passes float arguments as doubles. The .stabs record for
1481 for ANSI prototype floating point arguments records the
1482 type as FP_INTEGER, while a K&R style (no prototype)
1483 .stabs records the type as FP_FLOAT. In this latter case
1484 the compiler converts the float arguments to double before
1485 calling the function. */
1486 if (TYPE_CODE_FLT
== typecode
&& REGISTER_SIZE
== len
)
1489 dblval
= extract_floating (val
, len
);
1490 len
= TARGET_DOUBLE_BIT
/ TARGET_CHAR_BIT
;
1492 store_floating (val
, len
, dblval
);
1495 /* I don't know why this code was disable. The only logical use
1496 for a function pointer is to call that function, so setting
1497 the mode bit is perfectly fine. FN */
1498 /* If the argument is a pointer to a function, and it is a Thumb
1499 function, set the low bit of the pointer. */
1500 if (TYPE_CODE_PTR
== typecode
1501 && NULL
!= target_type
1502 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1504 CORE_ADDR regval
= extract_address (val
, len
);
1505 if (arm_pc_is_thumb (regval
))
1506 store_address (val
, len
, MAKE_THUMB_ADDR (regval
));
1509 /* Copy the argument to general registers or the stack in
1510 register-sized pieces. Large arguments are split between
1511 registers and stack. */
1514 int partial_len
= len
< REGISTER_SIZE
? len
: REGISTER_SIZE
;
1516 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1518 /* It's an argument being passed in a general register. */
1519 regval
= extract_address (val
, partial_len
);
1520 write_register (argreg
++, regval
);
1524 /* Push the arguments onto the stack. */
1525 write_memory ((CORE_ADDR
) fp
, val
, REGISTER_SIZE
);
1526 fp
+= REGISTER_SIZE
;
1534 /* Return adjusted stack pointer. */
1538 /* Pop the current frame. So long as the frame info has been initialized
1539 properly (see arm_init_extra_frame_info), this code works for dummy frames
1540 as well as regular frames. I.e, there's no need to have a special case
1541 for dummy frames. */
1543 arm_pop_frame (void)
1546 struct frame_info
*frame
= get_current_frame ();
1547 CORE_ADDR old_SP
= (frame
->frame
- frame
->extra_info
->frameoffset
1548 + frame
->extra_info
->framesize
);
1550 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1551 if (frame
->saved_regs
[regnum
] != 0)
1552 write_register (regnum
,
1553 read_memory_integer (frame
->saved_regs
[regnum
],
1554 REGISTER_RAW_SIZE (regnum
)));
1556 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
1557 write_register (SP_REGNUM
, old_SP
);
1559 flush_cached_frames ();
1563 print_fpu_flags (int flags
)
1565 if (flags
& (1 << 0))
1566 fputs ("IVO ", stdout
);
1567 if (flags
& (1 << 1))
1568 fputs ("DVZ ", stdout
);
1569 if (flags
& (1 << 2))
1570 fputs ("OFL ", stdout
);
1571 if (flags
& (1 << 3))
1572 fputs ("UFL ", stdout
);
1573 if (flags
& (1 << 4))
1574 fputs ("INX ", stdout
);
1578 /* Print interesting information about the floating point processor
1579 (if present) or emulator. */
1581 arm_print_float_info (void)
1583 register unsigned long status
= read_register (FPS_REGNUM
);
1586 type
= (status
>> 24) & 127;
1587 printf ("%s FPU type %d\n",
1588 (status
& (1 << 31)) ? "Hardware" : "Software",
1590 fputs ("mask: ", stdout
);
1591 print_fpu_flags (status
>> 16);
1592 fputs ("flags: ", stdout
);
1593 print_fpu_flags (status
);
1597 arm_register_type (int regnum
)
1599 if (regnum
>= F0_REGNUM
&& regnum
< F0_REGNUM
+ NUM_FREGS
)
1601 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1602 return builtin_type_arm_ext_big
;
1604 return builtin_type_arm_ext_littlebyte_bigword
;
1607 return builtin_type_int32
;
1610 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1611 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1612 It is thought that this is is the floating-point register format on
1613 little-endian systems. */
1616 convert_from_extended (void *ptr
, void *dbl
)
1619 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1620 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1622 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1624 floatformat_from_doublest (TARGET_DOUBLE_FORMAT
, &d
, dbl
);
1628 convert_to_extended (void *dbl
, void *ptr
)
1631 floatformat_to_doublest (TARGET_DOUBLE_FORMAT
, ptr
, &d
);
1632 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1633 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1635 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1640 condition_true (unsigned long cond
, unsigned long status_reg
)
1642 if (cond
== INST_AL
|| cond
== INST_NV
)
1648 return ((status_reg
& FLAG_Z
) != 0);
1650 return ((status_reg
& FLAG_Z
) == 0);
1652 return ((status_reg
& FLAG_C
) != 0);
1654 return ((status_reg
& FLAG_C
) == 0);
1656 return ((status_reg
& FLAG_N
) != 0);
1658 return ((status_reg
& FLAG_N
) == 0);
1660 return ((status_reg
& FLAG_V
) != 0);
1662 return ((status_reg
& FLAG_V
) == 0);
1664 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1666 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1668 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1670 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1672 return (((status_reg
& FLAG_Z
) == 0) &&
1673 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1675 return (((status_reg
& FLAG_Z
) != 0) ||
1676 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1681 /* Support routines for single stepping. Calculate the next PC value. */
1682 #define submask(x) ((1L << ((x) + 1)) - 1)
1683 #define bit(obj,st) (((obj) >> (st)) & 1)
1684 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1685 #define sbits(obj,st,fn) \
1686 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1687 #define BranchDest(addr,instr) \
1688 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1691 static unsigned long
1692 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1693 unsigned long status_reg
)
1695 unsigned long res
, shift
;
1696 int rm
= bits (inst
, 0, 3);
1697 unsigned long shifttype
= bits (inst
, 5, 6);
1701 int rs
= bits (inst
, 8, 11);
1702 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1705 shift
= bits (inst
, 7, 11);
1708 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1709 + (bit (inst
, 4) ? 12 : 8))
1710 : read_register (rm
));
1715 res
= shift
>= 32 ? 0 : res
<< shift
;
1719 res
= shift
>= 32 ? 0 : res
>> shift
;
1725 res
= ((res
& 0x80000000L
)
1726 ? ~((~res
) >> shift
) : res
>> shift
);
1729 case 3: /* ROR/RRX */
1732 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1734 res
= (res
>> shift
) | (res
<< (32 - shift
));
1738 return res
& 0xffffffff;
1741 /* Return number of 1-bits in VAL. */
1744 bitcount (unsigned long val
)
1747 for (nbits
= 0; val
!= 0; nbits
++)
1748 val
&= val
- 1; /* delete rightmost 1-bit in val */
1753 thumb_get_next_pc (CORE_ADDR pc
)
1755 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1756 unsigned short inst1
= read_memory_integer (pc
, 2);
1757 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1758 unsigned long offset
;
1760 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1764 /* Fetch the saved PC from the stack. It's stored above
1765 all of the other registers. */
1766 offset
= bitcount (bits (inst1
, 0, 7)) * REGISTER_SIZE
;
1767 sp
= read_register (SP_REGNUM
);
1768 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1769 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1771 error ("Infinite loop detected");
1773 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1775 unsigned long status
= read_register (PS_REGNUM
);
1776 unsigned long cond
= bits (inst1
, 8, 11);
1777 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1778 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1780 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1782 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1784 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1786 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1787 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1788 nextpc
= pc_val
+ offset
;
1795 arm_get_next_pc (CORE_ADDR pc
)
1797 unsigned long pc_val
;
1798 unsigned long this_instr
;
1799 unsigned long status
;
1802 if (arm_pc_is_thumb (pc
))
1803 return thumb_get_next_pc (pc
);
1805 pc_val
= (unsigned long) pc
;
1806 this_instr
= read_memory_integer (pc
, 4);
1807 status
= read_register (PS_REGNUM
);
1808 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1810 if (condition_true (bits (this_instr
, 28, 31), status
))
1812 switch (bits (this_instr
, 24, 27))
1815 case 0x1: /* data processing */
1819 unsigned long operand1
, operand2
, result
= 0;
1823 if (bits (this_instr
, 12, 15) != 15)
1826 if (bits (this_instr
, 22, 25) == 0
1827 && bits (this_instr
, 4, 7) == 9) /* multiply */
1828 error ("Illegal update to pc in instruction");
1830 /* Multiply into PC */
1831 c
= (status
& FLAG_C
) ? 1 : 0;
1832 rn
= bits (this_instr
, 16, 19);
1833 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1835 if (bit (this_instr
, 25))
1837 unsigned long immval
= bits (this_instr
, 0, 7);
1838 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1839 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1842 else /* operand 2 is a shifted register */
1843 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1845 switch (bits (this_instr
, 21, 24))
1848 result
= operand1
& operand2
;
1852 result
= operand1
^ operand2
;
1856 result
= operand1
- operand2
;
1860 result
= operand2
- operand1
;
1864 result
= operand1
+ operand2
;
1868 result
= operand1
+ operand2
+ c
;
1872 result
= operand1
- operand2
+ c
;
1876 result
= operand2
- operand1
+ c
;
1882 case 0xb: /* tst, teq, cmp, cmn */
1883 result
= (unsigned long) nextpc
;
1887 result
= operand1
| operand2
;
1891 /* Always step into a function. */
1896 result
= operand1
& ~operand2
;
1903 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1906 error ("Infinite loop detected");
1911 case 0x5: /* data transfer */
1914 if (bit (this_instr
, 20))
1917 if (bits (this_instr
, 12, 15) == 15)
1923 if (bit (this_instr
, 22))
1924 error ("Illegal update to pc in instruction");
1926 /* byte write to PC */
1927 rn
= bits (this_instr
, 16, 19);
1928 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1929 if (bit (this_instr
, 24))
1932 int c
= (status
& FLAG_C
) ? 1 : 0;
1933 unsigned long offset
=
1934 (bit (this_instr
, 25)
1935 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1936 : bits (this_instr
, 0, 11));
1938 if (bit (this_instr
, 23))
1943 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1946 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1949 error ("Infinite loop detected");
1955 case 0x9: /* block transfer */
1956 if (bit (this_instr
, 20))
1959 if (bit (this_instr
, 15))
1964 if (bit (this_instr
, 23))
1967 unsigned long reglist
= bits (this_instr
, 0, 14);
1968 offset
= bitcount (reglist
) * 4;
1969 if (bit (this_instr
, 24)) /* pre */
1972 else if (bit (this_instr
, 24))
1976 unsigned long rn_val
=
1977 read_register (bits (this_instr
, 16, 19));
1979 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1983 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1985 error ("Infinite loop detected");
1990 case 0xb: /* branch & link */
1991 case 0xa: /* branch */
1993 nextpc
= BranchDest (pc
, this_instr
);
1995 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1997 error ("Infinite loop detected");
2003 case 0xe: /* coproc ops */
2008 fprintf (stderr
, "Bad bit-field extraction\n");
2016 /* single_step() is called just before we want to resume the inferior,
2017 if we want to single-step it but there is no hardware or kernel
2018 single-step support. We find the target of the coming instruction
2021 single_step is also called just after the inferior stops. If we had
2022 set up a simulated single-step, we undo our damage. */
2025 arm_software_single_step (int ignore
, int insert_bpt
)
2027 static int next_pc
; /* State between setting and unsetting. */
2028 static char break_mem
[BREAKPOINT_MAX
]; /* Temporary storage for mem@bpt */
2032 next_pc
= arm_get_next_pc (read_register (PC_REGNUM
));
2033 target_insert_breakpoint (next_pc
, break_mem
);
2036 target_remove_breakpoint (next_pc
, break_mem
);
2039 #include "bfd-in2.h"
2040 #include "libcoff.h"
2043 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
2045 if (arm_pc_is_thumb (memaddr
))
2047 static asymbol
*asym
;
2048 static combined_entry_type ce
;
2049 static struct coff_symbol_struct csym
;
2050 static struct _bfd fake_bfd
;
2051 static bfd_target fake_target
;
2053 if (csym
.native
== NULL
)
2055 /* Create a fake symbol vector containing a Thumb symbol. This is
2056 solely so that the code in print_insn_little_arm() and
2057 print_insn_big_arm() in opcodes/arm-dis.c will detect the presence
2058 of a Thumb symbol and switch to decoding Thumb instructions. */
2060 fake_target
.flavour
= bfd_target_coff_flavour
;
2061 fake_bfd
.xvec
= &fake_target
;
2062 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
2064 csym
.symbol
.the_bfd
= &fake_bfd
;
2065 csym
.symbol
.name
= "fake";
2066 asym
= (asymbol
*) & csym
;
2069 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
2070 info
->symbols
= &asym
;
2073 info
->symbols
= NULL
;
2075 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2076 return print_insn_big_arm (memaddr
, info
);
2078 return print_insn_little_arm (memaddr
, info
);
2081 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the
2082 program counter value to determine whether a 16-bit or 32-bit
2083 breakpoint should be used. It returns a pointer to a string of
2084 bytes that encode a breakpoint instruction, stores the length of
2085 the string to *lenptr, and adjusts the program counter (if
2086 necessary) to point to the actual memory location where the
2087 breakpoint should be inserted. */
2090 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
2092 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
2094 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2096 static char thumb_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2097 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2098 *lenptr
= sizeof (thumb_breakpoint
);
2099 return thumb_breakpoint
;
2103 static char thumb_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2104 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2105 *lenptr
= sizeof (thumb_breakpoint
);
2106 return thumb_breakpoint
;
2111 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2113 static char arm_breakpoint
[] = ARM_BE_BREAKPOINT
;
2114 *lenptr
= sizeof (arm_breakpoint
);
2115 return arm_breakpoint
;
2119 static char arm_breakpoint
[] = ARM_LE_BREAKPOINT
;
2120 *lenptr
= sizeof (arm_breakpoint
);
2121 return arm_breakpoint
;
2126 /* Extract from an array REGBUF containing the (raw) register state a
2127 function return value of type TYPE, and copy that, in virtual
2128 format, into VALBUF. */
2131 arm_extract_return_value (struct type
*type
,
2132 char regbuf
[REGISTER_BYTES
],
2135 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2136 convert_from_extended (®buf
[REGISTER_BYTE (F0_REGNUM
)], valbuf
);
2138 memcpy (valbuf
, ®buf
[REGISTER_BYTE (A1_REGNUM
)], TYPE_LENGTH (type
));
2141 /* Return non-zero if the PC is inside a thumb call thunk. */
2144 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2146 CORE_ADDR start_addr
;
2148 /* Find the starting address of the function containing the PC. If
2149 the caller didn't give us a name, look it up at the same time. */
2150 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
2153 return strncmp (name
, "_call_via_r", 11) == 0;
2156 /* If PC is in a Thumb call or return stub, return the address of the
2157 target PC, which is in a register. The thunk functions are called
2158 _called_via_xx, where x is the register name. The possible names
2159 are r0-r9, sl, fp, ip, sp, and lr. */
2162 arm_skip_stub (CORE_ADDR pc
)
2165 CORE_ADDR start_addr
;
2167 /* Find the starting address and name of the function containing the PC. */
2168 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2171 /* Call thunks always start with "_call_via_". */
2172 if (strncmp (name
, "_call_via_", 10) == 0)
2174 /* Use the name suffix to determine which register contains the
2176 static char *table
[15] =
2177 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2178 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2182 for (regno
= 0; regno
<= 14; regno
++)
2183 if (strcmp (&name
[10], table
[regno
]) == 0)
2184 return read_register (regno
);
2187 return 0; /* not a stub */
2190 /* If the user changes the register disassembly flavor used for info register
2191 and other commands, we have to also switch the flavor used in opcodes
2192 for disassembly output.
2193 This function is run in the set disassembly_flavor command, and does that. */
2196 set_disassembly_flavor_sfunc (char *args
, int from_tty
,
2197 struct cmd_list_element
*c
)
2199 set_disassembly_flavor ();
2202 /* Return the ARM register name corresponding to register I. */
2204 arm_register_name(int i
)
2206 return arm_register_names
[i
];
2210 set_disassembly_flavor (void)
2212 const char *setname
, *setdesc
, **regnames
;
2215 /* Find the flavor that the user wants in the opcodes table. */
2217 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2218 while ((disassembly_flavor
!= setname
)
2219 && (current
< num_flavor_options
))
2220 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2221 current_option
= current
;
2223 /* Fill our copy. */
2224 for (j
= 0; j
< numregs
; j
++)
2225 arm_register_names
[j
] = (char *) regnames
[j
];
2228 if (isupper (*regnames
[PC_REGNUM
]))
2230 arm_register_names
[FPS_REGNUM
] = "FPS";
2231 arm_register_names
[PS_REGNUM
] = "CPSR";
2235 arm_register_names
[FPS_REGNUM
] = "fps";
2236 arm_register_names
[PS_REGNUM
] = "cpsr";
2239 /* Synchronize the disassembler. */
2240 set_arm_regname_option (current
);
2243 /* arm_othernames implements the "othernames" command. This is kind
2244 of hacky, and I prefer the set-show disassembly-flavor which is
2245 also used for the x86 gdb. I will keep this around, however, in
2246 case anyone is actually using it. */
2249 arm_othernames (char *names
, int n
)
2251 /* Circle through the various flavors. */
2252 current_option
= (current_option
+ 1) % num_flavor_options
;
2254 disassembly_flavor
= valid_flavors
[current_option
];
2255 set_disassembly_flavor ();
2258 /* Fetch, and possibly build, an appropriate link_map_offsets structure
2259 for ARM linux targets using the struct offsets defined in <link.h>.
2260 Note, however, that link.h is not actually referred to in this file.
2261 Instead, the relevant structs offsets were obtained from examining
2262 link.h. (We can't refer to link.h from this file because the host
2263 system won't necessarily have it, or if it does, the structs which
2264 it defines will refer to the host system, not the target.) */
2266 struct link_map_offsets
*
2267 arm_linux_svr4_fetch_link_map_offsets (void)
2269 static struct link_map_offsets lmo
;
2270 static struct link_map_offsets
*lmp
= 0;
2276 lmo
.r_debug_size
= 8; /* Actual size is 20, but this is all we
2279 lmo
.r_map_offset
= 4;
2282 lmo
.link_map_size
= 20; /* Actual size is 552, but this is all we
2285 lmo
.l_addr_offset
= 0;
2286 lmo
.l_addr_size
= 4;
2288 lmo
.l_name_offset
= 4;
2289 lmo
.l_name_size
= 4;
2291 lmo
.l_next_offset
= 12;
2292 lmo
.l_next_size
= 4;
2294 lmo
.l_prev_offset
= 16;
2295 lmo
.l_prev_size
= 4;
2301 /* Test whether the coff symbol specific value corresponds to a Thumb
2305 coff_sym_is_thumb (int val
)
2307 return (val
== C_THUMBEXT
||
2308 val
== C_THUMBSTAT
||
2309 val
== C_THUMBEXTFUNC
||
2310 val
== C_THUMBSTATFUNC
||
2311 val
== C_THUMBLABEL
);
2314 /* arm_coff_make_msymbol_special()
2315 arm_elf_make_msymbol_special()
2317 These functions test whether the COFF or ELF symbol corresponds to
2318 an address in thumb code, and set a "special" bit in a minimal
2319 symbol to indicate that it does. */
2322 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2324 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2326 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2328 MSYMBOL_SET_SPECIAL (msym
);
2332 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2334 if (coff_sym_is_thumb (val
))
2335 MSYMBOL_SET_SPECIAL (msym
);
2338 static struct gdbarch
*
2339 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2341 struct gdbarch
*gdbarch
;
2344 return arches
->gdbarch
;
2346 /* XXX We'll probably need to set the tdep field soon. */
2347 gdbarch
= gdbarch_alloc (&info
, NULL
);
2349 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
2351 /* Call dummy code. */
2352 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
2353 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
2354 set_gdbarch_call_dummy_p (gdbarch
, 1);
2355 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
2357 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_on_stack
);
2359 set_gdbarch_get_saved_register (gdbarch
, generic_get_saved_register
);
2360 set_gdbarch_push_arguments (gdbarch
, arm_push_arguments
);
2362 /* Frame handling. */
2363 set_gdbarch_frame_chain_valid (gdbarch
, arm_frame_chain_valid
);
2364 set_gdbarch_init_extra_frame_info (gdbarch
, arm_init_extra_frame_info
);
2365 set_gdbarch_read_fp (gdbarch
, arm_read_fp
);
2366 set_gdbarch_frame_chain (gdbarch
, arm_frame_chain
);
2367 set_gdbarch_frameless_function_invocation
2368 (gdbarch
, arm_frameless_function_invocation
);
2369 set_gdbarch_frame_saved_pc (gdbarch
, arm_frame_saved_pc
);
2370 set_gdbarch_frame_args_address (gdbarch
, arm_frame_args_address
);
2371 set_gdbarch_frame_locals_address (gdbarch
, arm_frame_locals_address
);
2372 set_gdbarch_frame_num_args (gdbarch
, arm_frame_num_args
);
2373 set_gdbarch_frame_args_skip (gdbarch
, 0);
2374 set_gdbarch_frame_init_saved_regs (gdbarch
, arm_frame_init_saved_regs
);
2375 set_gdbarch_push_dummy_frame (gdbarch
, arm_push_dummy_frame
);
2376 set_gdbarch_pop_frame (gdbarch
, arm_pop_frame
);
2383 _initialize_arm_tdep (void)
2385 struct ui_file
*stb
;
2387 struct cmd_list_element
*new_cmd
;
2388 const char *setname
;
2389 const char *setdesc
;
2390 const char **regnames
;
2392 static char *helptext
;
2395 register_gdbarch_init (bfd_arch_arm
, arm_gdbarch_init
);
2397 tm_print_insn
= gdb_print_insn_arm
;
2399 /* Get the number of possible sets of register names defined in opcodes. */
2400 num_flavor_options
= get_arm_regname_num_options ();
2402 /* Sync the opcode insn printer with our register viewer: */
2403 parse_arm_disassembler_option ("reg-names-std");
2405 /* Begin creating the help text. */
2406 stb
= mem_fileopen ();
2407 fprintf_unfiltered (stb
, "Set the disassembly flavor.\n\
2408 The valid values are:\n");
2410 /* Initialize the array that will be passed to add_set_enum_cmd(). */
2411 valid_flavors
= xmalloc ((num_flavor_options
+ 1) * sizeof (char *));
2412 for (i
= 0; i
< num_flavor_options
; i
++)
2414 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
2415 valid_flavors
[i
] = setname
;
2416 fprintf_unfiltered (stb
, "%s - %s\n", setname
,
2418 /* Copy the default names (if found) and synchronize disassembler. */
2419 if (!strcmp (setname
, "std"))
2421 disassembly_flavor
= setname
;
2423 for (j
= 0; j
< numregs
; j
++)
2424 arm_register_names
[j
] = (char *) regnames
[j
];
2425 set_arm_regname_option (i
);
2428 /* Mark the end of valid options. */
2429 valid_flavors
[num_flavor_options
] = NULL
;
2431 /* Finish the creation of the help text. */
2432 fprintf_unfiltered (stb
, "The default is \"std\".");
2433 helptext
= ui_file_xstrdup (stb
, &length
);
2434 ui_file_delete (stb
);
2436 /* Add the disassembly-flavor command */
2437 new_cmd
= add_set_enum_cmd ("disassembly-flavor", no_class
,
2439 &disassembly_flavor
,
2442 set_cmd_sfunc (new_cmd
, set_disassembly_flavor_sfunc
);
2443 add_show_from_set (new_cmd
, &showlist
);
2445 /* ??? Maybe this should be a boolean. */
2446 add_show_from_set (add_set_cmd ("apcs32", no_class
,
2447 var_zinteger
, (char *) &arm_apcs_32
,
2448 "Set usage of ARM 32-bit mode.\n", &setlist
),
2451 /* Add the deprecated "othernames" command */
2453 add_com ("othernames", class_obscure
, arm_othernames
,
2454 "Switch to the next set of register names.");
2456 /* Fill in the prologue_cache fields. */
2457 prologue_cache
.extra_info
= (struct frame_extra_info
*)
2458 xcalloc (1, sizeof (struct frame_extra_info
));
2459 prologue_cache
.saved_regs
= (CORE_ADDR
*)
2460 xcalloc (1, SIZEOF_FRAME_SAVED_REGS
);