1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 #include <ctype.h> /* XXX for isupper () */
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register styles. */
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
42 #include "gdb/sim-arm.h"
45 #include "coff/internal.h"
48 #include "gdb_assert.h"
52 /* Each OS has a different mechanism for accessing the various
53 registers stored in the sigcontext structure.
55 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
56 function pointer) which may be used to determine the addresses
57 of the various saved registers in the sigcontext structure.
59 For the ARM target, there are three parameters to this function.
60 The first is the pc value of the frame under consideration, the
61 second the stack pointer of this frame, and the last is the
62 register number to fetch.
64 If the tm.h file does not define this macro, then it's assumed that
65 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
68 When it comes time to multi-arching this code, see the identically
69 named machinery in ia64-tdep.c for an example of how it could be
70 done. It should not be necessary to modify the code below where
71 this macro is used. */
73 #ifdef SIGCONTEXT_REGISTER_ADDRESS
74 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
75 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
78 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
79 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
82 /* Macros for setting and testing a bit in a minimal symbol that marks
83 it as Thumb function. The MSB of the minimal symbol's "info" field
84 is used for this purpose. This field is already being used to store
85 the symbol size, so the assumption is that the symbol size cannot
88 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
89 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol.
90 MSYMBOL_SIZE Returns the size of the minimal symbol,
91 i.e. the "info" field with the "special" bit
94 #define MSYMBOL_SET_SPECIAL(msym) \
95 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
98 #define MSYMBOL_IS_SPECIAL(msym) \
99 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
101 #define MSYMBOL_SIZE(msym) \
102 ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
104 /* The list of available "set arm ..." and "show arm ..." commands. */
105 static struct cmd_list_element
*setarmcmdlist
= NULL
;
106 static struct cmd_list_element
*showarmcmdlist
= NULL
;
108 /* The type of floating-point to use. Keep this in sync with enum
109 arm_float_model, and the help string in _initialize_arm_tdep. */
110 static const char *fp_model_strings
[] =
119 /* A variable that can be configured by the user. */
120 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
121 static const char *current_fp_model
= "auto";
123 /* Number of different reg name sets (options). */
124 static int num_disassembly_options
;
126 /* We have more registers than the disassembler as gdb can print the value
127 of special registers as well.
128 The general register names are overwritten by whatever is being used by
129 the disassembler at the moment. We also adjust the case of cpsr and fps. */
131 /* Initial value: Register names used in ARM's ISA documentation. */
132 static char * arm_register_name_strings
[] =
133 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
134 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
135 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
136 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
137 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
138 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
139 "fps", "cpsr" }; /* 24 25 */
140 static char **arm_register_names
= arm_register_name_strings
;
142 /* Valid register name styles. */
143 static const char **valid_disassembly_styles
;
145 /* Disassembly style to use. Default to "std" register names. */
146 static const char *disassembly_style
;
147 /* Index to that option in the opcodes table. */
148 static int current_option
;
150 /* This is used to keep the bfd arch_info in sync with the disassembly
152 static void set_disassembly_style_sfunc(char *, int,
153 struct cmd_list_element
*);
154 static void set_disassembly_style (void);
156 static void convert_from_extended (const struct floatformat
*, const void *,
158 static void convert_to_extended (const struct floatformat
*, void *,
161 struct arm_prologue_cache
163 /* The stack pointer at the time this frame was created; i.e. the
164 caller's stack pointer when this function was called. It is used
165 to identify this frame. */
168 /* The frame base for this frame is just prev_sp + frame offset -
169 frame size. FRAMESIZE is the size of this stack frame, and
170 FRAMEOFFSET if the initial offset from the stack pointer (this
171 frame's stack pointer, not PREV_SP) to the frame base. */
176 /* The register used to hold the frame pointer for this frame. */
179 /* Saved register offsets. */
180 struct trad_frame_saved_reg
*saved_regs
;
183 /* Addresses for calling Thumb functions have the bit 0 set.
184 Here are some macros to test, set, or clear bit 0 of addresses. */
185 #define IS_THUMB_ADDR(addr) ((addr) & 1)
186 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
187 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
189 /* Set to true if the 32-bit mode is in use. */
193 /* Flag set by arm_fix_call_dummy that tells whether the target
194 function is a Thumb function. This flag is checked by
195 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
196 its use in valops.c) to pass the function address as an additional
199 static int target_is_thumb
;
201 /* Flag set by arm_fix_call_dummy that tells whether the calling
202 function is a Thumb function. This flag is checked by
203 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
205 static int caller_is_thumb
;
207 /* Determine if the program counter specified in MEMADDR is in a Thumb
211 arm_pc_is_thumb (CORE_ADDR memaddr
)
213 struct minimal_symbol
*sym
;
215 /* If bit 0 of the address is set, assume this is a Thumb address. */
216 if (IS_THUMB_ADDR (memaddr
))
219 /* Thumb functions have a "special" bit set in minimal symbols. */
220 sym
= lookup_minimal_symbol_by_pc (memaddr
);
223 return (MSYMBOL_IS_SPECIAL (sym
));
231 /* Determine if the program counter specified in MEMADDR is in a call
232 dummy being called from a Thumb function. */
235 arm_pc_is_thumb_dummy (CORE_ADDR memaddr
)
237 CORE_ADDR sp
= read_sp ();
239 /* FIXME: Until we switch for the new call dummy macros, this heuristic
240 is the best we can do. We are trying to determine if the pc is on
241 the stack, which (hopefully) will only happen in a call dummy.
242 We hope the current stack pointer is not so far alway from the dummy
243 frame location (true if we have not pushed large data structures or
244 gone too many levels deep) and that our 1024 is not enough to consider
245 code regions as part of the stack (true for most practical purposes). */
246 if (DEPRECATED_PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 1024))
247 return caller_is_thumb
;
252 /* Remove useless bits from addresses in a running program. */
254 arm_addr_bits_remove (CORE_ADDR val
)
257 return (val
& (arm_pc_is_thumb (val
) ? 0xfffffffe : 0xfffffffc));
259 return (val
& 0x03fffffc);
262 /* When reading symbols, we need to zap the low bit of the address,
263 which may be set to 1 for Thumb functions. */
265 arm_smash_text_address (CORE_ADDR val
)
270 /* Immediately after a function call, return the saved pc. Can't
271 always go through the frames for this because on some machines the
272 new frame is not set up until the new function executes some
276 arm_saved_pc_after_call (struct frame_info
*frame
)
278 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM
));
281 /* Determine whether the function invocation represented by FI has a
282 frame on the stack associated with it. If it does return zero,
283 otherwise return 1. */
286 arm_frameless_function_invocation (struct frame_info
*fi
)
288 CORE_ADDR func_start
, after_prologue
;
291 /* Sometimes we have functions that do a little setup (like saving the
292 vN registers with the stmdb instruction, but DO NOT set up a frame.
293 The symbol table will report this as a prologue. However, it is
294 important not to try to parse these partial frames as frames, or we
295 will get really confused.
297 So I will demand 3 instructions between the start & end of the
298 prologue before I call it a real prologue, i.e. at least
303 func_start
= (get_frame_func (fi
) + FUNCTION_START_OFFSET
);
304 after_prologue
= SKIP_PROLOGUE (func_start
);
306 /* There are some frameless functions whose first two instructions
307 follow the standard APCS form, in which case after_prologue will
308 be func_start + 8. */
310 frameless
= (after_prologue
< func_start
+ 12);
314 /* A typical Thumb prologue looks like this:
318 Sometimes the latter instruction may be replaced by:
326 or, on tpcs, like this:
333 There is always one instruction of three classes:
338 When we have found at least one of each class we are done with the prolog.
339 Note that the "sub sp, #NN" before the push does not count.
343 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
345 CORE_ADDR current_pc
;
347 bit 0 - push { rlist }
348 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
349 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
353 for (current_pc
= pc
;
354 current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40;
357 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
359 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
361 findmask
|= 1; /* push found */
363 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
366 if ((findmask
& 1) == 0) /* before push ? */
369 findmask
|= 4; /* add/sub sp found */
371 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
373 findmask
|= 2; /* setting of r7 found */
375 else if (insn
== 0x466f) /* mov r7, sp */
377 findmask
|= 2; /* setting of r7 found */
379 else if (findmask
== (4+2+1))
381 /* We have found one of each type of prologue instruction */
385 /* Something in the prolog that we don't care about or some
386 instruction from outside the prolog scheduled here for
394 /* Advance the PC across any function entry prologue instructions to
395 reach some "real" code.
397 The APCS (ARM Procedure Call Standard) defines the following
401 [stmfd sp!, {a1,a2,a3,a4}]
402 stmfd sp!, {...,fp,ip,lr,pc}
403 [stfe f7, [sp, #-12]!]
404 [stfe f6, [sp, #-12]!]
405 [stfe f5, [sp, #-12]!]
406 [stfe f4, [sp, #-12]!]
407 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
410 arm_skip_prologue (CORE_ADDR pc
)
414 CORE_ADDR func_addr
, func_end
= 0;
416 struct symtab_and_line sal
;
418 /* If we're in a dummy frame, don't even try to skip the prologue. */
419 if (DEPRECATED_PC_IN_CALL_DUMMY (pc
, 0, 0))
422 /* See what the symbol table says. */
424 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
428 /* Found a function. */
429 sym
= lookup_symbol (func_name
, NULL
, VAR_DOMAIN
, NULL
, NULL
);
430 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
432 /* Don't use this trick for assembly source files. */
433 sal
= find_pc_line (func_addr
, 0);
434 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
439 /* Check if this is Thumb code. */
440 if (arm_pc_is_thumb (pc
))
441 return thumb_skip_prologue (pc
, func_end
);
443 /* Can't find the prologue end in the symbol table, try it the hard way
444 by disassembling the instructions. */
446 /* Like arm_scan_prologue, stop no later than pc + 64. */
447 if (func_end
== 0 || func_end
> pc
+ 64)
450 for (skip_pc
= pc
; skip_pc
< func_end
; skip_pc
+= 4)
452 inst
= read_memory_integer (skip_pc
, 4);
454 /* "mov ip, sp" is no longer a required part of the prologue. */
455 if (inst
== 0xe1a0c00d) /* mov ip, sp */
458 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
461 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
464 /* Some prologues begin with "str lr, [sp, #-4]!". */
465 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
468 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
471 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
474 /* Any insns after this point may float into the code, if it makes
475 for better instruction scheduling, so we skip them only if we
476 find them, but still consider the function to be frame-ful. */
478 /* We may have either one sfmfd instruction here, or several stfe
479 insns, depending on the version of floating point code we
481 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
484 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
487 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
490 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
493 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
494 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
495 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
498 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
499 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
500 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
503 /* Un-recognized instruction; stop scanning. */
507 return skip_pc
; /* End of prologue */
511 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
512 This function decodes a Thumb function prologue to determine:
513 1) the size of the stack frame
514 2) which registers are saved on it
515 3) the offsets of saved regs
516 4) the offset from the stack pointer to the frame pointer
518 A typical Thumb function prologue would create this stack frame
519 (offsets relative to FP)
520 old SP -> 24 stack parameters
523 R7 -> 0 local variables (16 bytes)
524 SP -> -12 additional stack space (12 bytes)
525 The frame size would thus be 36 bytes, and the frame offset would be
526 12 bytes. The frame register is R7.
528 The comments for thumb_skip_prolog() describe the algorithm we use
529 to detect the end of the prolog. */
533 thumb_scan_prologue (CORE_ADDR prev_pc
, struct arm_prologue_cache
*cache
)
535 CORE_ADDR prologue_start
;
536 CORE_ADDR prologue_end
;
537 CORE_ADDR current_pc
;
538 /* Which register has been copied to register n? */
541 bit 0 - push { rlist }
542 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
543 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
548 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
550 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
552 if (sal
.line
== 0) /* no line info, use current PC */
553 prologue_end
= prev_pc
;
554 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
555 prologue_end
= sal
.end
; /* (probably means no prologue) */
558 /* We're in the boondocks: allow for
559 16 pushes, an add, and "mv fp,sp". */
560 prologue_end
= prologue_start
+ 40;
562 prologue_end
= min (prologue_end
, prev_pc
);
564 /* Initialize the saved register map. When register H is copied to
565 register L, we will put H in saved_reg[L]. */
566 for (i
= 0; i
< 16; i
++)
569 /* Search the prologue looking for instructions that set up the
570 frame pointer, adjust the stack pointer, and save registers.
571 Do this until all basic prolog instructions are found. */
573 cache
->framesize
= 0;
574 for (current_pc
= prologue_start
;
575 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
582 insn
= read_memory_unsigned_integer (current_pc
, 2);
584 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
587 findmask
|= 1; /* push found */
588 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
589 whether to save LR (R14). */
590 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
592 /* Calculate offsets of saved R0-R7 and LR. */
593 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
594 if (mask
& (1 << regno
))
596 cache
->framesize
+= 4;
597 cache
->saved_regs
[saved_reg
[regno
]].addr
= -cache
->framesize
;
598 /* Reset saved register map. */
599 saved_reg
[regno
] = regno
;
602 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
605 if ((findmask
& 1) == 0) /* before push? */
608 findmask
|= 4; /* add/sub sp found */
610 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
611 if (insn
& 0x80) /* is it signed? (==subtracting) */
613 cache
->frameoffset
+= offset
;
616 cache
->framesize
-= offset
;
618 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
620 findmask
|= 2; /* setting of r7 found */
621 cache
->framereg
= THUMB_FP_REGNUM
;
622 /* get scaled offset */
623 cache
->frameoffset
= (insn
& 0xff) << 2;
625 else if (insn
== 0x466f) /* mov r7, sp */
627 findmask
|= 2; /* setting of r7 found */
628 cache
->framereg
= THUMB_FP_REGNUM
;
629 cache
->frameoffset
= 0;
630 saved_reg
[THUMB_FP_REGNUM
] = ARM_SP_REGNUM
;
632 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
634 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
635 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
636 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
639 /* Something in the prolog that we don't care about or some
640 instruction from outside the prolog scheduled here for
646 /* This function decodes an ARM function prologue to determine:
647 1) the size of the stack frame
648 2) which registers are saved on it
649 3) the offsets of saved regs
650 4) the offset from the stack pointer to the frame pointer
651 This information is stored in the "extra" fields of the frame_info.
653 There are two basic forms for the ARM prologue. The fixed argument
654 function call will look like:
657 stmfd sp!, {fp, ip, lr, pc}
661 Which would create this stack frame (offsets relative to FP):
662 IP -> 4 (caller's stack)
663 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
664 -4 LR (return address in caller)
665 -8 IP (copy of caller's SP)
667 SP -> -28 Local variables
669 The frame size would thus be 32 bytes, and the frame offset would be
670 28 bytes. The stmfd call can also save any of the vN registers it
671 plans to use, which increases the frame size accordingly.
673 Note: The stored PC is 8 off of the STMFD instruction that stored it
674 because the ARM Store instructions always store PC + 8 when you read
677 A variable argument function call will look like:
680 stmfd sp!, {a1, a2, a3, a4}
681 stmfd sp!, {fp, ip, lr, pc}
684 Which would create this stack frame (offsets relative to FP):
685 IP -> 20 (caller's stack)
690 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
691 -4 LR (return address in caller)
692 -8 IP (copy of caller's SP)
694 SP -> -28 Local variables
696 The frame size would thus be 48 bytes, and the frame offset would be
699 There is another potential complication, which is that the optimizer
700 will try to separate the store of fp in the "stmfd" instruction from
701 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
702 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
704 Also, note, the original version of the ARM toolchain claimed that there
707 instruction at the end of the prologue. I have never seen GCC produce
708 this, and the ARM docs don't mention it. We still test for it below in
714 arm_scan_prologue (struct frame_info
*next_frame
, struct arm_prologue_cache
*cache
)
716 int regno
, sp_offset
, fp_offset
, ip_offset
;
717 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
718 CORE_ADDR prev_pc
= frame_pc_unwind (next_frame
);
720 /* Assume there is no frame until proven otherwise. */
721 cache
->framereg
= ARM_SP_REGNUM
;
722 cache
->framesize
= 0;
723 cache
->frameoffset
= 0;
725 /* Check for Thumb prologue. */
726 if (arm_pc_is_thumb (prev_pc
))
728 thumb_scan_prologue (prev_pc
, cache
);
732 /* Find the function prologue. If we can't find the function in
733 the symbol table, peek in the stack frame to find the PC. */
734 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
736 /* One way to find the end of the prologue (which works well
737 for unoptimized code) is to do the following:
739 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
742 prologue_end = prev_pc;
743 else if (sal.end < prologue_end)
744 prologue_end = sal.end;
746 This mechanism is very accurate so long as the optimizer
747 doesn't move any instructions from the function body into the
748 prologue. If this happens, sal.end will be the last
749 instruction in the first hunk of prologue code just before
750 the first instruction that the scheduler has moved from
751 the body to the prologue.
753 In order to make sure that we scan all of the prologue
754 instructions, we use a slightly less accurate mechanism which
755 may scan more than necessary. To help compensate for this
756 lack of accuracy, the prologue scanning loop below contains
757 several clauses which'll cause the loop to terminate early if
758 an implausible prologue instruction is encountered.
764 is a suitable endpoint since it accounts for the largest
765 possible prologue plus up to five instructions inserted by
768 if (prologue_end
> prologue_start
+ 64)
770 prologue_end
= prologue_start
+ 64; /* See above. */
775 /* We have no symbol information. Our only option is to assume this
776 function has a standard stack frame and the normal frame register.
777 Then, we can find the value of our frame pointer on entrance to
778 the callee (or at the present moment if this is the innermost frame).
779 The value stored there should be the address of the stmfd + 8. */
781 LONGEST return_value
;
783 frame_loc
= frame_unwind_register_unsigned (next_frame
, ARM_FP_REGNUM
);
784 if (!safe_read_memory_integer (frame_loc
, 4, &return_value
))
788 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
789 prologue_end
= prologue_start
+ 64; /* See above. */
793 if (prev_pc
< prologue_end
)
794 prologue_end
= prev_pc
;
796 /* Now search the prologue looking for instructions that set up the
797 frame pointer, adjust the stack pointer, and save registers.
799 Be careful, however, and if it doesn't look like a prologue,
800 don't try to scan it. If, for instance, a frameless function
801 begins with stmfd sp!, then we will tell ourselves there is
802 a frame, which will confuse stack traceback, as well as "finish"
803 and other operations that rely on a knowledge of the stack
806 In the APCS, the prologue should start with "mov ip, sp" so
807 if we don't see this as the first insn, we will stop.
809 [Note: This doesn't seem to be true any longer, so it's now an
810 optional part of the prologue. - Kevin Buettner, 2001-11-20]
812 [Note further: The "mov ip,sp" only seems to be missing in
813 frameless functions at optimization level "-O2" or above,
814 in which case it is often (but not always) replaced by
815 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
817 sp_offset
= fp_offset
= ip_offset
= 0;
819 for (current_pc
= prologue_start
;
820 current_pc
< prologue_end
;
823 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
825 if (insn
== 0xe1a0c00d) /* mov ip, sp */
830 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
832 unsigned imm
= insn
& 0xff; /* immediate value */
833 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
834 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
838 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
840 unsigned imm
= insn
& 0xff; /* immediate value */
841 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
842 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
846 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
848 /* Function is frameless: extra_info defaults OK? */
851 else if ((insn
& 0xffff0000) == 0xe92d0000)
852 /* stmfd sp!, {..., fp, ip, lr, pc}
854 stmfd sp!, {a1, a2, a3, a4} */
856 int mask
= insn
& 0xffff;
858 /* Calculate offsets of saved registers. */
859 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
860 if (mask
& (1 << regno
))
863 cache
->saved_regs
[regno
].addr
= sp_offset
;
866 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
867 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
868 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
870 /* No need to add this to saved_regs -- it's just an arg reg. */
873 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
874 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
875 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
877 /* No need to add this to saved_regs -- it's just an arg reg. */
880 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
882 unsigned imm
= insn
& 0xff; /* immediate value */
883 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
884 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
885 fp_offset
= -imm
+ ip_offset
;
886 cache
->framereg
= ARM_FP_REGNUM
;
888 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
890 unsigned imm
= insn
& 0xff; /* immediate value */
891 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
892 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
895 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
898 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
899 cache
->saved_regs
[regno
].addr
= sp_offset
;
901 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
904 unsigned int fp_start_reg
, fp_bound_reg
;
906 if ((insn
& 0x800) == 0x800) /* N0 is set */
908 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
915 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
921 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
922 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
923 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
926 cache
->saved_regs
[fp_start_reg
++].addr
= sp_offset
;
929 else if ((insn
& 0xf0000000) != 0xe0000000)
930 break; /* Condition not true, exit early */
931 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
932 break; /* Don't scan past a block load */
934 /* The optimizer might shove anything into the prologue,
935 so we just skip what we don't recognize. */
939 /* The frame size is just the negative of the offset (from the
940 original SP) of the last thing thing we pushed on the stack.
941 The frame offset is [new FP] - [new SP]. */
942 cache
->framesize
= -sp_offset
;
943 if (cache
->framereg
== ARM_FP_REGNUM
)
944 cache
->frameoffset
= fp_offset
- sp_offset
;
946 cache
->frameoffset
= 0;
949 static struct arm_prologue_cache
*
950 arm_make_prologue_cache (struct frame_info
*next_frame
)
953 struct arm_prologue_cache
*cache
;
954 CORE_ADDR unwound_fp
;
956 cache
= frame_obstack_zalloc (sizeof (struct arm_prologue_cache
));
957 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
959 arm_scan_prologue (next_frame
, cache
);
961 unwound_fp
= frame_unwind_register_unsigned (next_frame
, cache
->framereg
);
965 cache
->prev_sp
= unwound_fp
+ cache
->framesize
- cache
->frameoffset
;
967 /* Calculate actual addresses of saved registers using offsets
968 determined by arm_scan_prologue. */
969 for (reg
= 0; reg
< NUM_REGS
; reg
++)
970 if (cache
->saved_regs
[reg
].addr
!= 0)
971 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
976 /* Our frame ID for a normal frame is the current function's starting PC
977 and the caller's SP when we were called. */
980 arm_prologue_this_id (struct frame_info
*next_frame
,
982 struct frame_id
*this_id
)
984 struct arm_prologue_cache
*cache
;
988 if (*this_cache
== NULL
)
989 *this_cache
= arm_make_prologue_cache (next_frame
);
992 func
= frame_func_unwind (next_frame
);
994 /* This is meant to halt the backtrace at "_start". Make sure we
995 don't halt it at a generic dummy frame. */
996 if (func
<= LOWEST_PC
|| deprecated_inside_entry_file (func
))
999 /* If we've hit a wall, stop. */
1000 if (cache
->prev_sp
== 0)
1003 id
= frame_id_build (cache
->prev_sp
, func
);
1005 /* Check that we're not going round in circles with the same frame
1006 ID (but avoid applying the test to sentinel frames which do go
1007 round in circles). */
1008 if (frame_relative_level (next_frame
) >= 0
1009 && get_frame_type (next_frame
) == NORMAL_FRAME
1010 && frame_id_eq (get_frame_id (next_frame
), id
))
1017 arm_prologue_prev_register (struct frame_info
*next_frame
,
1021 enum lval_type
*lvalp
,
1026 struct arm_prologue_cache
*cache
;
1028 if (*this_cache
== NULL
)
1029 *this_cache
= arm_make_prologue_cache (next_frame
);
1030 cache
= *this_cache
;
1032 /* If we are asked to unwind the PC, then we need to return the LR
1033 instead. The saved value of PC points into this frame's
1034 prologue, not the next frame's resume location. */
1035 if (prev_regnum
== ARM_PC_REGNUM
)
1036 prev_regnum
= ARM_LR_REGNUM
;
1038 /* SP is generally not saved to the stack, but this frame is
1039 identified by NEXT_FRAME's stack pointer at the time of the call.
1040 The value was already reconstructed into PREV_SP. */
1041 if (prev_regnum
== ARM_SP_REGNUM
)
1045 store_unsigned_integer (valuep
, 4, cache
->prev_sp
);
1049 trad_frame_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
1050 optimized
, lvalp
, addrp
, realnump
, valuep
);
1053 struct frame_unwind arm_prologue_unwind
= {
1055 arm_prologue_this_id
,
1056 arm_prologue_prev_register
1059 static const struct frame_unwind
*
1060 arm_prologue_unwind_sniffer (struct frame_info
*next_frame
)
1062 return &arm_prologue_unwind
;
1066 arm_normal_frame_base (struct frame_info
*next_frame
, void **this_cache
)
1068 struct arm_prologue_cache
*cache
;
1070 if (*this_cache
== NULL
)
1071 *this_cache
= arm_make_prologue_cache (next_frame
);
1072 cache
= *this_cache
;
1074 return cache
->prev_sp
+ cache
->frameoffset
- cache
->framesize
;
1077 struct frame_base arm_normal_base
= {
1078 &arm_prologue_unwind
,
1079 arm_normal_frame_base
,
1080 arm_normal_frame_base
,
1081 arm_normal_frame_base
1084 static struct arm_prologue_cache
*
1085 arm_make_sigtramp_cache (struct frame_info
*next_frame
)
1087 struct arm_prologue_cache
*cache
;
1090 cache
= frame_obstack_zalloc (sizeof (struct arm_prologue_cache
));
1092 cache
->prev_sp
= frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
);
1094 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1096 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1097 cache
->saved_regs
[reg
].addr
1098 = SIGCONTEXT_REGISTER_ADDRESS (cache
->prev_sp
,
1099 frame_pc_unwind (next_frame
), reg
);
1101 /* FIXME: What about thumb mode? */
1102 cache
->framereg
= ARM_SP_REGNUM
;
1104 = read_memory_integer (cache
->saved_regs
[cache
->framereg
].addr
,
1105 REGISTER_RAW_SIZE (cache
->framereg
));
1111 arm_sigtramp_this_id (struct frame_info
*next_frame
,
1113 struct frame_id
*this_id
)
1115 struct arm_prologue_cache
*cache
;
1117 if (*this_cache
== NULL
)
1118 *this_cache
= arm_make_sigtramp_cache (next_frame
);
1119 cache
= *this_cache
;
1121 /* FIXME drow/2003-07-07: This isn't right if we single-step within
1122 the sigtramp frame; the PC should be the beginning of the trampoline. */
1123 *this_id
= frame_id_build (cache
->prev_sp
, frame_pc_unwind (next_frame
));
1127 arm_sigtramp_prev_register (struct frame_info
*next_frame
,
1131 enum lval_type
*lvalp
,
1136 struct arm_prologue_cache
*cache
;
1138 if (*this_cache
== NULL
)
1139 *this_cache
= arm_make_sigtramp_cache (next_frame
);
1140 cache
= *this_cache
;
1142 trad_frame_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
1143 optimized
, lvalp
, addrp
, realnump
, valuep
);
1146 struct frame_unwind arm_sigtramp_unwind
= {
1148 arm_sigtramp_this_id
,
1149 arm_sigtramp_prev_register
1152 static const struct frame_unwind
*
1153 arm_sigtramp_unwind_sniffer (struct frame_info
*next_frame
)
1155 /* Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare
1156 against the name of the function, the code below will have to be
1157 changed to first fetch the name of the function and then pass
1158 this name to PC_IN_SIGTRAMP. */
1160 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1161 && PC_IN_SIGTRAMP (frame_pc_unwind (next_frame
), (char *) 0))
1162 return &arm_sigtramp_unwind
;
1167 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1168 dummy frame. The frame ID's base needs to match the TOS value
1169 saved by save_dummy_frame_tos() and returned from
1170 arm_push_dummy_call, and the PC needs to match the dummy frame's
1173 static struct frame_id
1174 arm_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1176 return frame_id_build (frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
),
1177 frame_pc_unwind (next_frame
));
1180 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1181 be used to construct the previous frame's ID, after looking up the
1182 containing function). */
1185 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1188 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1189 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1193 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1195 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1198 /* Set the return address for a generic dummy frame. ARM uses the
1202 arm_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
1204 write_register (ARM_LR_REGNUM
, entry_point_address ());
1208 /* Push an empty stack frame, to record the current PC, etc. */
1211 arm_push_dummy_frame (void)
1213 CORE_ADDR old_sp
= read_register (ARM_SP_REGNUM
);
1214 CORE_ADDR sp
= old_sp
;
1215 CORE_ADDR fp
, prologue_start
;
1218 /* Push the two dummy prologue instructions in reverse order,
1219 so that they'll be in the correct low-to-high order in memory. */
1220 /* sub fp, ip, #4 */
1221 sp
= push_word (sp
, 0xe24cb004);
1222 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1223 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
1225 /* Push a pointer to the dummy prologue + 12, because when stm
1226 instruction stores the PC, it stores the address of the stm
1227 instruction itself plus 12. */
1228 fp
= sp
= push_word (sp
, prologue_start
+ 12);
1230 /* Push the processor status. */
1231 sp
= push_word (sp
, read_register (ARM_PS_REGNUM
));
1233 /* Push all 16 registers starting with r15. */
1234 for (regnum
= ARM_PC_REGNUM
; regnum
>= 0; regnum
--)
1235 sp
= push_word (sp
, read_register (regnum
));
1237 /* Update fp (for both Thumb and ARM) and sp. */
1238 write_register (ARM_FP_REGNUM
, fp
);
1239 write_register (THUMB_FP_REGNUM
, fp
);
1240 write_register (ARM_SP_REGNUM
, sp
);
1243 /* DEPRECATED_CALL_DUMMY_WORDS:
1244 This sequence of words is the instructions
1250 Note this is 12 bytes. */
1252 static LONGEST arm_call_dummy_words
[] =
1254 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
1257 /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy
1258 breakpoint to the proper address in the call dummy, so that
1259 `finish' after a stop in a call dummy works.
1261 FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an
1262 optimal solution, but the call to arm_fix_call_dummy is immediately
1263 followed by a call to call_function_by_hand, which is the only
1264 function where call_dummy_breakpoint_offset is actually used. */
1268 arm_set_call_dummy_breakpoint_offset (void)
1270 if (caller_is_thumb
)
1271 set_gdbarch_deprecated_call_dummy_breakpoint_offset (current_gdbarch
, 4);
1273 set_gdbarch_deprecated_call_dummy_breakpoint_offset (current_gdbarch
, 8);
1276 /* Fix up the call dummy, based on whether the processor is currently
1277 in Thumb or ARM mode, and whether the target function is Thumb or
1278 ARM. There are three different situations requiring three
1281 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1282 been copied into the dummy parameter to this function.
1283 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1284 "mov pc,r4" instruction patched to be a "bx r4" instead.
1285 * Thumb calling anything: uses the Thumb dummy defined below, which
1286 works for calling both ARM and Thumb functions.
1288 All three call dummies expect to receive the target function
1289 address in R4, with the low bit set if it's a Thumb function. */
1292 arm_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
1293 struct value
**args
, struct type
*type
, int gcc_p
)
1295 static short thumb_dummy
[4] =
1297 0xf000, 0xf801, /* bl label */
1298 0xdf18, /* swi 24 */
1299 0x4720, /* label: bx r4 */
1301 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
1303 /* Set flag indicating whether the current PC is in a Thumb function. */
1304 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
1305 arm_set_call_dummy_breakpoint_offset ();
1307 /* If the target function is Thumb, set the low bit of the function
1308 address. And if the CPU is currently in ARM mode, patch the
1309 second instruction of call dummy to use a BX instruction to
1310 switch to Thumb mode. */
1311 target_is_thumb
= arm_pc_is_thumb (fun
);
1312 if (target_is_thumb
)
1315 if (!caller_is_thumb
)
1316 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
1319 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1320 instead of the ARM one that's already been copied. This will
1321 work for both Thumb and ARM target functions. */
1322 if (caller_is_thumb
)
1326 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
1328 for (i
= 0; i
< len
; i
++)
1330 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1331 p
+= sizeof (thumb_dummy
[0]);
1335 /* Put the target address in r4; the call dummy will copy this to
1337 write_register (4, fun
);
1340 /* When arguments must be pushed onto the stack, they go on in reverse
1341 order. The code below implements a FILO (stack) to do this. */
1346 struct stack_item
*prev
;
1350 static struct stack_item
*
1351 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1353 struct stack_item
*si
;
1354 si
= xmalloc (sizeof (struct stack_item
));
1355 si
->data
= xmalloc (len
);
1358 memcpy (si
->data
, contents
, len
);
1362 static struct stack_item
*
1363 pop_stack_item (struct stack_item
*si
)
1365 struct stack_item
*dead
= si
;
1372 /* We currently only support passing parameters in integer registers. This
1373 conforms with GCC's default model. Several other variants exist and
1374 we should probably support some of them based on the selected ABI. */
1377 arm_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
1378 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1379 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1380 CORE_ADDR struct_addr
)
1385 struct stack_item
*si
= NULL
;
1387 /* Set the return address. For the ARM, the return breakpoint is
1388 always at BP_ADDR. */
1389 /* XXX Fix for Thumb. */
1390 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1392 /* Walk through the list of args and determine how large a temporary
1393 stack is required. Need to take care here as structs may be
1394 passed on the stack, and we have to to push them. */
1397 argreg
= ARM_A1_REGNUM
;
1400 /* Some platforms require a double-word aligned stack. Make sure sp
1401 is correctly aligned before we start. We always do this even if
1402 it isn't really needed -- it can never hurt things. */
1403 sp
&= ~(CORE_ADDR
)(2 * DEPRECATED_REGISTER_SIZE
- 1);
1405 /* The struct_return pointer occupies the first parameter
1406 passing register. */
1410 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = 0x%s\n",
1411 REGISTER_NAME (argreg
), paddr (struct_addr
));
1412 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1416 for (argnum
= 0; argnum
< nargs
; argnum
++)
1419 struct type
*arg_type
;
1420 struct type
*target_type
;
1421 enum type_code typecode
;
1424 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1425 len
= TYPE_LENGTH (arg_type
);
1426 target_type
= TYPE_TARGET_TYPE (arg_type
);
1427 typecode
= TYPE_CODE (arg_type
);
1428 val
= VALUE_CONTENTS (args
[argnum
]);
1430 /* If the argument is a pointer to a function, and it is a
1431 Thumb function, create a LOCAL copy of the value and set
1432 the THUMB bit in it. */
1433 if (TYPE_CODE_PTR
== typecode
1434 && target_type
!= NULL
1435 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1437 CORE_ADDR regval
= extract_unsigned_integer (val
, len
);
1438 if (arm_pc_is_thumb (regval
))
1441 store_unsigned_integer (val
, len
, MAKE_THUMB_ADDR (regval
));
1445 /* Copy the argument to general registers or the stack in
1446 register-sized pieces. Large arguments are split between
1447 registers and stack. */
1450 int partial_len
= len
< DEPRECATED_REGISTER_SIZE
? len
: DEPRECATED_REGISTER_SIZE
;
1452 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1454 /* The argument is being passed in a general purpose
1456 CORE_ADDR regval
= extract_unsigned_integer (val
, partial_len
);
1458 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1459 argnum
, REGISTER_NAME (argreg
),
1460 phex (regval
, DEPRECATED_REGISTER_SIZE
));
1461 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1466 /* Push the arguments onto the stack. */
1468 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1470 si
= push_stack_item (si
, val
, DEPRECATED_REGISTER_SIZE
);
1471 nstack
+= DEPRECATED_REGISTER_SIZE
;
1478 /* If we have an odd number of words to push, then decrement the stack
1479 by one word now, so first stack argument will be dword aligned. */
1486 write_memory (sp
, si
->data
, si
->len
);
1487 si
= pop_stack_item (si
);
1490 /* Finally, update teh SP register. */
1491 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1497 print_fpu_flags (int flags
)
1499 if (flags
& (1 << 0))
1500 fputs ("IVO ", stdout
);
1501 if (flags
& (1 << 1))
1502 fputs ("DVZ ", stdout
);
1503 if (flags
& (1 << 2))
1504 fputs ("OFL ", stdout
);
1505 if (flags
& (1 << 3))
1506 fputs ("UFL ", stdout
);
1507 if (flags
& (1 << 4))
1508 fputs ("INX ", stdout
);
1512 /* Print interesting information about the floating point processor
1513 (if present) or emulator. */
1515 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1516 struct frame_info
*frame
, const char *args
)
1518 unsigned long status
= read_register (ARM_FPS_REGNUM
);
1521 type
= (status
>> 24) & 127;
1522 printf ("%s FPU type %d\n",
1523 (status
& (1 << 31)) ? "Hardware" : "Software",
1525 fputs ("mask: ", stdout
);
1526 print_fpu_flags (status
>> 16);
1527 fputs ("flags: ", stdout
);
1528 print_fpu_flags (status
);
1531 /* Return the GDB type object for the "standard" data type of data in
1534 static struct type
*
1535 arm_register_type (int regnum
)
1537 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1539 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1540 return builtin_type_arm_ext_big
;
1542 return builtin_type_arm_ext_littlebyte_bigword
;
1545 return builtin_type_int32
;
1548 /* Index within `registers' of the first byte of the space for
1552 arm_register_byte (int regnum
)
1554 if (regnum
< ARM_F0_REGNUM
)
1555 return regnum
* INT_REGISTER_RAW_SIZE
;
1556 else if (regnum
< ARM_PS_REGNUM
)
1557 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1558 + (regnum
- ARM_F0_REGNUM
) * FP_REGISTER_RAW_SIZE
);
1560 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1561 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
1562 + (regnum
- ARM_FPS_REGNUM
) * STATUS_REGISTER_SIZE
);
1565 /* Number of bytes of storage in the actual machine representation for
1566 register N. All registers are 4 bytes, except fp0 - fp7, which are
1567 12 bytes in length. */
1570 arm_register_raw_size (int regnum
)
1572 if (regnum
< ARM_F0_REGNUM
)
1573 return INT_REGISTER_RAW_SIZE
;
1574 else if (regnum
< ARM_FPS_REGNUM
)
1575 return FP_REGISTER_RAW_SIZE
;
1577 return STATUS_REGISTER_SIZE
;
1580 /* Number of bytes of storage in a program's representation
1583 arm_register_virtual_size (int regnum
)
1585 if (regnum
< ARM_F0_REGNUM
)
1586 return INT_REGISTER_VIRTUAL_SIZE
;
1587 else if (regnum
< ARM_FPS_REGNUM
)
1588 return FP_REGISTER_VIRTUAL_SIZE
;
1590 return STATUS_REGISTER_SIZE
;
1593 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1595 arm_register_sim_regno (int regnum
)
1598 gdb_assert (reg
>= 0 && reg
< NUM_REGS
);
1600 if (reg
< NUM_GREGS
)
1601 return SIM_ARM_R0_REGNUM
+ reg
;
1604 if (reg
< NUM_FREGS
)
1605 return SIM_ARM_FP0_REGNUM
+ reg
;
1608 if (reg
< NUM_SREGS
)
1609 return SIM_ARM_FPS_REGNUM
+ reg
;
1612 internal_error (__FILE__
, __LINE__
, "Bad REGNUM %d", regnum
);
1615 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1616 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1617 It is thought that this is is the floating-point register format on
1618 little-endian systems. */
1621 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
1625 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1626 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1628 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1630 floatformat_from_doublest (fmt
, &d
, dbl
);
1634 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
)
1637 floatformat_to_doublest (fmt
, ptr
, &d
);
1638 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1639 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1641 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1646 condition_true (unsigned long cond
, unsigned long status_reg
)
1648 if (cond
== INST_AL
|| cond
== INST_NV
)
1654 return ((status_reg
& FLAG_Z
) != 0);
1656 return ((status_reg
& FLAG_Z
) == 0);
1658 return ((status_reg
& FLAG_C
) != 0);
1660 return ((status_reg
& FLAG_C
) == 0);
1662 return ((status_reg
& FLAG_N
) != 0);
1664 return ((status_reg
& FLAG_N
) == 0);
1666 return ((status_reg
& FLAG_V
) != 0);
1668 return ((status_reg
& FLAG_V
) == 0);
1670 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1672 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1674 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1676 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1678 return (((status_reg
& FLAG_Z
) == 0) &&
1679 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1681 return (((status_reg
& FLAG_Z
) != 0) ||
1682 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1687 /* Support routines for single stepping. Calculate the next PC value. */
1688 #define submask(x) ((1L << ((x) + 1)) - 1)
1689 #define bit(obj,st) (((obj) >> (st)) & 1)
1690 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1691 #define sbits(obj,st,fn) \
1692 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1693 #define BranchDest(addr,instr) \
1694 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1697 static unsigned long
1698 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1699 unsigned long status_reg
)
1701 unsigned long res
, shift
;
1702 int rm
= bits (inst
, 0, 3);
1703 unsigned long shifttype
= bits (inst
, 5, 6);
1707 int rs
= bits (inst
, 8, 11);
1708 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1711 shift
= bits (inst
, 7, 11);
1714 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1715 + (bit (inst
, 4) ? 12 : 8))
1716 : read_register (rm
));
1721 res
= shift
>= 32 ? 0 : res
<< shift
;
1725 res
= shift
>= 32 ? 0 : res
>> shift
;
1731 res
= ((res
& 0x80000000L
)
1732 ? ~((~res
) >> shift
) : res
>> shift
);
1735 case 3: /* ROR/RRX */
1738 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1740 res
= (res
>> shift
) | (res
<< (32 - shift
));
1744 return res
& 0xffffffff;
1747 /* Return number of 1-bits in VAL. */
1750 bitcount (unsigned long val
)
1753 for (nbits
= 0; val
!= 0; nbits
++)
1754 val
&= val
- 1; /* delete rightmost 1-bit in val */
1759 thumb_get_next_pc (CORE_ADDR pc
)
1761 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1762 unsigned short inst1
= read_memory_integer (pc
, 2);
1763 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1764 unsigned long offset
;
1766 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1770 /* Fetch the saved PC from the stack. It's stored above
1771 all of the other registers. */
1772 offset
= bitcount (bits (inst1
, 0, 7)) * DEPRECATED_REGISTER_SIZE
;
1773 sp
= read_register (ARM_SP_REGNUM
);
1774 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1775 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1777 error ("Infinite loop detected");
1779 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1781 unsigned long status
= read_register (ARM_PS_REGNUM
);
1782 unsigned long cond
= bits (inst1
, 8, 11);
1783 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1784 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1786 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1788 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1790 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1792 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1793 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1794 nextpc
= pc_val
+ offset
;
1801 arm_get_next_pc (CORE_ADDR pc
)
1803 unsigned long pc_val
;
1804 unsigned long this_instr
;
1805 unsigned long status
;
1808 if (arm_pc_is_thumb (pc
))
1809 return thumb_get_next_pc (pc
);
1811 pc_val
= (unsigned long) pc
;
1812 this_instr
= read_memory_integer (pc
, 4);
1813 status
= read_register (ARM_PS_REGNUM
);
1814 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1816 if (condition_true (bits (this_instr
, 28, 31), status
))
1818 switch (bits (this_instr
, 24, 27))
1821 case 0x1: /* data processing */
1825 unsigned long operand1
, operand2
, result
= 0;
1829 if (bits (this_instr
, 12, 15) != 15)
1832 if (bits (this_instr
, 22, 25) == 0
1833 && bits (this_instr
, 4, 7) == 9) /* multiply */
1834 error ("Illegal update to pc in instruction");
1836 /* Multiply into PC */
1837 c
= (status
& FLAG_C
) ? 1 : 0;
1838 rn
= bits (this_instr
, 16, 19);
1839 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1841 if (bit (this_instr
, 25))
1843 unsigned long immval
= bits (this_instr
, 0, 7);
1844 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1845 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1848 else /* operand 2 is a shifted register */
1849 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1851 switch (bits (this_instr
, 21, 24))
1854 result
= operand1
& operand2
;
1858 result
= operand1
^ operand2
;
1862 result
= operand1
- operand2
;
1866 result
= operand2
- operand1
;
1870 result
= operand1
+ operand2
;
1874 result
= operand1
+ operand2
+ c
;
1878 result
= operand1
- operand2
+ c
;
1882 result
= operand2
- operand1
+ c
;
1888 case 0xb: /* tst, teq, cmp, cmn */
1889 result
= (unsigned long) nextpc
;
1893 result
= operand1
| operand2
;
1897 /* Always step into a function. */
1902 result
= operand1
& ~operand2
;
1909 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1912 error ("Infinite loop detected");
1917 case 0x5: /* data transfer */
1920 if (bit (this_instr
, 20))
1923 if (bits (this_instr
, 12, 15) == 15)
1929 if (bit (this_instr
, 22))
1930 error ("Illegal update to pc in instruction");
1932 /* byte write to PC */
1933 rn
= bits (this_instr
, 16, 19);
1934 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1935 if (bit (this_instr
, 24))
1938 int c
= (status
& FLAG_C
) ? 1 : 0;
1939 unsigned long offset
=
1940 (bit (this_instr
, 25)
1941 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1942 : bits (this_instr
, 0, 11));
1944 if (bit (this_instr
, 23))
1949 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1952 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1955 error ("Infinite loop detected");
1961 case 0x9: /* block transfer */
1962 if (bit (this_instr
, 20))
1965 if (bit (this_instr
, 15))
1970 if (bit (this_instr
, 23))
1973 unsigned long reglist
= bits (this_instr
, 0, 14);
1974 offset
= bitcount (reglist
) * 4;
1975 if (bit (this_instr
, 24)) /* pre */
1978 else if (bit (this_instr
, 24))
1982 unsigned long rn_val
=
1983 read_register (bits (this_instr
, 16, 19));
1985 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1989 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1991 error ("Infinite loop detected");
1996 case 0xb: /* branch & link */
1997 case 0xa: /* branch */
1999 nextpc
= BranchDest (pc
, this_instr
);
2001 nextpc
= ADDR_BITS_REMOVE (nextpc
);
2003 error ("Infinite loop detected");
2009 case 0xe: /* coproc ops */
2014 fprintf_filtered (gdb_stderr
, "Bad bit-field extraction\n");
2022 /* single_step() is called just before we want to resume the inferior,
2023 if we want to single-step it but there is no hardware or kernel
2024 single-step support. We find the target of the coming instruction
2027 single_step() is also called just after the inferior stops. If we
2028 had set up a simulated single-step, we undo our damage. */
2031 arm_software_single_step (enum target_signal sig
, int insert_bpt
)
2033 static int next_pc
; /* State between setting and unsetting. */
2034 static char break_mem
[BREAKPOINT_MAX
]; /* Temporary storage for mem@bpt */
2038 next_pc
= arm_get_next_pc (read_register (ARM_PC_REGNUM
));
2039 target_insert_breakpoint (next_pc
, break_mem
);
2042 target_remove_breakpoint (next_pc
, break_mem
);
2045 #include "bfd-in2.h"
2046 #include "libcoff.h"
2049 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
2051 if (arm_pc_is_thumb (memaddr
))
2053 static asymbol
*asym
;
2054 static combined_entry_type ce
;
2055 static struct coff_symbol_struct csym
;
2056 static struct bfd fake_bfd
;
2057 static bfd_target fake_target
;
2059 if (csym
.native
== NULL
)
2061 /* Create a fake symbol vector containing a Thumb symbol.
2062 This is solely so that the code in print_insn_little_arm()
2063 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2064 the presence of a Thumb symbol and switch to decoding
2065 Thumb instructions. */
2067 fake_target
.flavour
= bfd_target_coff_flavour
;
2068 fake_bfd
.xvec
= &fake_target
;
2069 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
2071 csym
.symbol
.the_bfd
= &fake_bfd
;
2072 csym
.symbol
.name
= "fake";
2073 asym
= (asymbol
*) & csym
;
2076 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
2077 info
->symbols
= &asym
;
2080 info
->symbols
= NULL
;
2082 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2083 return print_insn_big_arm (memaddr
, info
);
2085 return print_insn_little_arm (memaddr
, info
);
2088 /* The following define instruction sequences that will cause ARM
2089 cpu's to take an undefined instruction trap. These are used to
2090 signal a breakpoint to GDB.
2092 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2093 modes. A different instruction is required for each mode. The ARM
2094 cpu's can also be big or little endian. Thus four different
2095 instructions are needed to support all cases.
2097 Note: ARMv4 defines several new instructions that will take the
2098 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2099 not in fact add the new instructions. The new undefined
2100 instructions in ARMv4 are all instructions that had no defined
2101 behaviour in earlier chips. There is no guarantee that they will
2102 raise an exception, but may be treated as NOP's. In practice, it
2103 may only safe to rely on instructions matching:
2105 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2106 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2107 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2109 Even this may only true if the condition predicate is true. The
2110 following use a condition predicate of ALWAYS so it is always TRUE.
2112 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2113 and NetBSD all use a software interrupt rather than an undefined
2114 instruction to force a trap. This can be handled by by the
2115 abi-specific code during establishment of the gdbarch vector. */
2118 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
2119 override these definitions. */
2120 #ifndef ARM_LE_BREAKPOINT
2121 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2123 #ifndef ARM_BE_BREAKPOINT
2124 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2126 #ifndef THUMB_LE_BREAKPOINT
2127 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
2129 #ifndef THUMB_BE_BREAKPOINT
2130 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
2133 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
2134 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
2135 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2136 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2138 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2139 the program counter value to determine whether a 16-bit or 32-bit
2140 breakpoint should be used. It returns a pointer to a string of
2141 bytes that encode a breakpoint instruction, stores the length of
2142 the string to *lenptr, and adjusts the program counter (if
2143 necessary) to point to the actual memory location where the
2144 breakpoint should be inserted. */
2146 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
2147 breakpoints and storing their handles instread of what was in
2148 memory. It is nice that this is the same size as a handle -
2149 otherwise remote-rdp will have to change. */
2151 static const unsigned char *
2152 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
2154 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2156 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
2158 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2159 *lenptr
= tdep
->thumb_breakpoint_size
;
2160 return tdep
->thumb_breakpoint
;
2164 *lenptr
= tdep
->arm_breakpoint_size
;
2165 return tdep
->arm_breakpoint
;
2169 /* Extract from an array REGBUF containing the (raw) register state a
2170 function return value of type TYPE, and copy that, in virtual
2171 format, into VALBUF. */
2174 arm_extract_return_value (struct type
*type
,
2175 struct regcache
*regs
,
2178 bfd_byte
*valbuf
= dst
;
2180 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2182 switch (arm_get_fp_model (current_gdbarch
))
2186 /* The value is in register F0 in internal format. We need to
2187 extract the raw value and then convert it to the desired
2189 bfd_byte tmpbuf
[FP_REGISTER_RAW_SIZE
];
2191 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
2192 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
2197 case ARM_FLOAT_SOFT_FPA
:
2198 case ARM_FLOAT_SOFT_VFP
:
2199 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
2200 if (TYPE_LENGTH (type
) > 4)
2201 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
2202 valbuf
+ INT_REGISTER_RAW_SIZE
);
2207 (__FILE__
, __LINE__
,
2208 "arm_extract_return_value: Floating point model not supported");
2212 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2213 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2214 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2215 || TYPE_CODE (type
) == TYPE_CODE_PTR
2216 || TYPE_CODE (type
) == TYPE_CODE_REF
2217 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2219 /* If the the type is a plain integer, then the access is
2220 straight-forward. Otherwise we have to play around a bit more. */
2221 int len
= TYPE_LENGTH (type
);
2222 int regno
= ARM_A1_REGNUM
;
2227 /* By using store_unsigned_integer we avoid having to do
2228 anything special for small big-endian values. */
2229 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2230 store_unsigned_integer (valbuf
,
2231 (len
> INT_REGISTER_RAW_SIZE
2232 ? INT_REGISTER_RAW_SIZE
: len
),
2234 len
-= INT_REGISTER_RAW_SIZE
;
2235 valbuf
+= INT_REGISTER_RAW_SIZE
;
2240 /* For a structure or union the behaviour is as if the value had
2241 been stored to word-aligned memory and then loaded into
2242 registers with 32-bit load instruction(s). */
2243 int len
= TYPE_LENGTH (type
);
2244 int regno
= ARM_A1_REGNUM
;
2245 bfd_byte tmpbuf
[INT_REGISTER_RAW_SIZE
];
2249 regcache_cooked_read (regs
, regno
++, tmpbuf
);
2250 memcpy (valbuf
, tmpbuf
,
2251 len
> INT_REGISTER_RAW_SIZE
? INT_REGISTER_RAW_SIZE
: len
);
2252 len
-= INT_REGISTER_RAW_SIZE
;
2253 valbuf
+= INT_REGISTER_RAW_SIZE
;
2258 /* Extract from an array REGBUF containing the (raw) register state
2259 the address in which a function should return its structure value. */
2262 arm_extract_struct_value_address (struct regcache
*regcache
)
2266 regcache_cooked_read_unsigned (regcache
, ARM_A1_REGNUM
, &ret
);
2270 /* Will a function return an aggregate type in memory or in a
2271 register? Return 0 if an aggregate type can be returned in a
2272 register, 1 if it must be returned in memory. */
2275 arm_use_struct_convention (int gcc_p
, struct type
*type
)
2278 enum type_code code
;
2280 /* In the ARM ABI, "integer" like aggregate types are returned in
2281 registers. For an aggregate type to be integer like, its size
2282 must be less than or equal to DEPRECATED_REGISTER_SIZE and the
2283 offset of each addressable subfield must be zero. Note that bit
2284 fields are not addressable, and all addressable subfields of
2285 unions always start at offset zero.
2287 This function is based on the behaviour of GCC 2.95.1.
2288 See: gcc/arm.c: arm_return_in_memory() for details.
2290 Note: All versions of GCC before GCC 2.95.2 do not set up the
2291 parameters correctly for a function returning the following
2292 structure: struct { float f;}; This should be returned in memory,
2293 not a register. Richard Earnshaw sent me a patch, but I do not
2294 know of any way to detect if a function like the above has been
2295 compiled with the correct calling convention. */
2297 /* All aggregate types that won't fit in a register must be returned
2299 if (TYPE_LENGTH (type
) > DEPRECATED_REGISTER_SIZE
)
2304 /* The only aggregate types that can be returned in a register are
2305 structs and unions. Arrays must be returned in memory. */
2306 code
= TYPE_CODE (type
);
2307 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2312 /* Assume all other aggregate types can be returned in a register.
2313 Run a check for structures, unions and arrays. */
2316 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2319 /* Need to check if this struct/union is "integer" like. For
2320 this to be true, its size must be less than or equal to
2321 DEPRECATED_REGISTER_SIZE and the offset of each addressable
2322 subfield must be zero. Note that bit fields are not
2323 addressable, and unions always start at offset zero. If any
2324 of the subfields is a floating point type, the struct/union
2325 cannot be an integer type. */
2327 /* For each field in the object, check:
2328 1) Is it FP? --> yes, nRc = 1;
2329 2) Is it addressable (bitpos != 0) and
2330 not packed (bitsize == 0)?
2334 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2336 enum type_code field_type_code
;
2337 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
2339 /* Is it a floating point type field? */
2340 if (field_type_code
== TYPE_CODE_FLT
)
2346 /* If bitpos != 0, then we have to care about it. */
2347 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2349 /* Bitfields are not addressable. If the field bitsize is
2350 zero, then the field is not packed. Hence it cannot be
2351 a bitfield or any other packed type. */
2352 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2364 /* Write into appropriate registers a function return value of type
2365 TYPE, given in virtual format. */
2368 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
2371 const bfd_byte
*valbuf
= src
;
2373 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2375 char buf
[ARM_MAX_REGISTER_RAW_SIZE
];
2377 switch (arm_get_fp_model (current_gdbarch
))
2381 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
);
2382 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
2385 case ARM_FLOAT_SOFT_FPA
:
2386 case ARM_FLOAT_SOFT_VFP
:
2387 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
2388 if (TYPE_LENGTH (type
) > 4)
2389 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
2390 valbuf
+ INT_REGISTER_RAW_SIZE
);
2395 (__FILE__
, __LINE__
,
2396 "arm_store_return_value: Floating point model not supported");
2400 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2401 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2402 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2403 || TYPE_CODE (type
) == TYPE_CODE_PTR
2404 || TYPE_CODE (type
) == TYPE_CODE_REF
2405 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2407 if (TYPE_LENGTH (type
) <= 4)
2409 /* Values of one word or less are zero/sign-extended and
2411 bfd_byte tmpbuf
[INT_REGISTER_RAW_SIZE
];
2412 LONGEST val
= unpack_long (type
, valbuf
);
2414 store_signed_integer (tmpbuf
, INT_REGISTER_RAW_SIZE
, val
);
2415 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
2419 /* Integral values greater than one word are stored in consecutive
2420 registers starting with r0. This will always be a multiple of
2421 the regiser size. */
2422 int len
= TYPE_LENGTH (type
);
2423 int regno
= ARM_A1_REGNUM
;
2427 regcache_cooked_write (regs
, regno
++, valbuf
);
2428 len
-= INT_REGISTER_RAW_SIZE
;
2429 valbuf
+= INT_REGISTER_RAW_SIZE
;
2435 /* For a structure or union the behaviour is as if the value had
2436 been stored to word-aligned memory and then loaded into
2437 registers with 32-bit load instruction(s). */
2438 int len
= TYPE_LENGTH (type
);
2439 int regno
= ARM_A1_REGNUM
;
2440 bfd_byte tmpbuf
[INT_REGISTER_RAW_SIZE
];
2444 memcpy (tmpbuf
, valbuf
,
2445 len
> INT_REGISTER_RAW_SIZE
? INT_REGISTER_RAW_SIZE
: len
);
2446 regcache_cooked_write (regs
, regno
++, tmpbuf
);
2447 len
-= INT_REGISTER_RAW_SIZE
;
2448 valbuf
+= INT_REGISTER_RAW_SIZE
;
2454 arm_get_longjmp_target (CORE_ADDR
*pc
)
2457 char buf
[INT_REGISTER_RAW_SIZE
];
2458 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2460 jb_addr
= read_register (ARM_A1_REGNUM
);
2462 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2463 INT_REGISTER_RAW_SIZE
))
2466 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_RAW_SIZE
);
2470 /* Return non-zero if the PC is inside a thumb call thunk. */
2473 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2475 CORE_ADDR start_addr
;
2477 /* Find the starting address of the function containing the PC. If
2478 the caller didn't give us a name, look it up at the same time. */
2479 if (0 == find_pc_partial_function (pc
, name
? NULL
: &name
,
2483 return strncmp (name
, "_call_via_r", 11) == 0;
2486 /* If PC is in a Thumb call or return stub, return the address of the
2487 target PC, which is in a register. The thunk functions are called
2488 _called_via_xx, where x is the register name. The possible names
2489 are r0-r9, sl, fp, ip, sp, and lr. */
2492 arm_skip_stub (CORE_ADDR pc
)
2495 CORE_ADDR start_addr
;
2497 /* Find the starting address and name of the function containing the PC. */
2498 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2501 /* Call thunks always start with "_call_via_". */
2502 if (strncmp (name
, "_call_via_", 10) == 0)
2504 /* Use the name suffix to determine which register contains the
2506 static char *table
[15] =
2507 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2508 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2512 for (regno
= 0; regno
<= 14; regno
++)
2513 if (strcmp (&name
[10], table
[regno
]) == 0)
2514 return read_register (regno
);
2517 return 0; /* not a stub */
2521 set_arm_command (char *args
, int from_tty
)
2523 printf_unfiltered ("\"set arm\" must be followed by an apporpriate subcommand.\n");
2524 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
2528 show_arm_command (char *args
, int from_tty
)
2530 cmd_show_list (showarmcmdlist
, from_tty
, "");
2533 enum arm_float_model
2534 arm_get_fp_model (struct gdbarch
*gdbarch
)
2536 if (arm_fp_model
== ARM_FLOAT_AUTO
)
2537 return gdbarch_tdep (gdbarch
)->fp_model
;
2539 return arm_fp_model
;
2543 arm_set_fp (struct gdbarch
*gdbarch
)
2545 enum arm_float_model fp_model
= arm_get_fp_model (gdbarch
);
2547 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
2548 && (fp_model
== ARM_FLOAT_SOFT_FPA
|| fp_model
== ARM_FLOAT_FPA
))
2550 set_gdbarch_double_format (gdbarch
,
2551 &floatformat_ieee_double_littlebyte_bigword
);
2552 set_gdbarch_long_double_format
2553 (gdbarch
, &floatformat_ieee_double_littlebyte_bigword
);
2557 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_little
);
2558 set_gdbarch_long_double_format (gdbarch
,
2559 &floatformat_ieee_double_little
);
2564 set_fp_model_sfunc (char *args
, int from_tty
,
2565 struct cmd_list_element
*c
)
2567 enum arm_float_model fp_model
;
2569 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
2570 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
2572 arm_fp_model
= fp_model
;
2576 if (fp_model
== ARM_FLOAT_LAST
)
2577 internal_error (__FILE__
, __LINE__
, "Invalid fp model accepted: %s.",
2580 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2581 arm_set_fp (current_gdbarch
);
2585 show_fp_model (char *args
, int from_tty
,
2586 struct cmd_list_element
*c
)
2588 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2590 if (arm_fp_model
== ARM_FLOAT_AUTO
2591 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2592 printf_filtered (" - the default for the current ABI is \"%s\".\n",
2593 fp_model_strings
[tdep
->fp_model
]);
2596 /* If the user changes the register disassembly style used for info
2597 register and other commands, we have to also switch the style used
2598 in opcodes for disassembly output. This function is run in the "set
2599 arm disassembly" command, and does that. */
2602 set_disassembly_style_sfunc (char *args
, int from_tty
,
2603 struct cmd_list_element
*c
)
2605 set_disassembly_style ();
2608 /* Return the ARM register name corresponding to register I. */
2610 arm_register_name (int i
)
2612 return arm_register_names
[i
];
2616 set_disassembly_style (void)
2618 const char *setname
, *setdesc
, **regnames
;
2621 /* Find the style that the user wants in the opcodes table. */
2623 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2624 while ((disassembly_style
!= setname
)
2625 && (current
< num_disassembly_options
))
2626 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2627 current_option
= current
;
2629 /* Fill our copy. */
2630 for (j
= 0; j
< numregs
; j
++)
2631 arm_register_names
[j
] = (char *) regnames
[j
];
2634 if (isupper (*regnames
[ARM_PC_REGNUM
]))
2636 arm_register_names
[ARM_FPS_REGNUM
] = "FPS";
2637 arm_register_names
[ARM_PS_REGNUM
] = "CPSR";
2641 arm_register_names
[ARM_FPS_REGNUM
] = "fps";
2642 arm_register_names
[ARM_PS_REGNUM
] = "cpsr";
2645 /* Synchronize the disassembler. */
2646 set_arm_regname_option (current
);
2649 /* arm_othernames implements the "othernames" command. This is deprecated
2650 by the "set arm disassembly" command. */
2653 arm_othernames (char *names
, int n
)
2655 /* Circle through the various flavors. */
2656 current_option
= (current_option
+ 1) % num_disassembly_options
;
2658 disassembly_style
= valid_disassembly_styles
[current_option
];
2659 set_disassembly_style ();
2662 /* Test whether the coff symbol specific value corresponds to a Thumb
2666 coff_sym_is_thumb (int val
)
2668 return (val
== C_THUMBEXT
||
2669 val
== C_THUMBSTAT
||
2670 val
== C_THUMBEXTFUNC
||
2671 val
== C_THUMBSTATFUNC
||
2672 val
== C_THUMBLABEL
);
2675 /* arm_coff_make_msymbol_special()
2676 arm_elf_make_msymbol_special()
2678 These functions test whether the COFF or ELF symbol corresponds to
2679 an address in thumb code, and set a "special" bit in a minimal
2680 symbol to indicate that it does. */
2683 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2685 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2687 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2689 MSYMBOL_SET_SPECIAL (msym
);
2693 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2695 if (coff_sym_is_thumb (val
))
2696 MSYMBOL_SET_SPECIAL (msym
);
2700 static enum gdb_osabi
2701 arm_elf_osabi_sniffer (bfd
*abfd
)
2703 unsigned int elfosabi
, eflags
;
2704 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2706 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2711 /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the
2712 file are conforming to the base specification for that machine
2713 (there are no OS-specific extensions). In order to determine the
2714 real OS in use we must look for OS notes that have been added. */
2715 bfd_map_over_sections (abfd
,
2716 generic_elf_osabi_sniff_abi_tag_sections
,
2718 if (osabi
== GDB_OSABI_UNKNOWN
)
2720 /* Existing ARM tools don't set this field, so look at the EI_FLAGS
2721 field for more information. */
2722 eflags
= EF_ARM_EABI_VERSION(elf_elfheader(abfd
)->e_flags
);
2725 case EF_ARM_EABI_VER1
:
2726 osabi
= GDB_OSABI_ARM_EABI_V1
;
2729 case EF_ARM_EABI_VER2
:
2730 osabi
= GDB_OSABI_ARM_EABI_V2
;
2733 case EF_ARM_EABI_UNKNOWN
:
2734 /* Assume GNU tools. */
2735 osabi
= GDB_OSABI_ARM_APCS
;
2739 internal_error (__FILE__
, __LINE__
,
2740 "arm_elf_osabi_sniffer: Unknown ARM EABI "
2741 "version 0x%x", eflags
);
2747 /* GNU tools use this value. Check note sections in this case,
2749 bfd_map_over_sections (abfd
,
2750 generic_elf_osabi_sniff_abi_tag_sections
,
2752 if (osabi
== GDB_OSABI_UNKNOWN
)
2754 /* Assume APCS ABI. */
2755 osabi
= GDB_OSABI_ARM_APCS
;
2759 case ELFOSABI_FREEBSD
:
2760 osabi
= GDB_OSABI_FREEBSD_ELF
;
2763 case ELFOSABI_NETBSD
:
2764 osabi
= GDB_OSABI_NETBSD_ELF
;
2767 case ELFOSABI_LINUX
:
2768 osabi
= GDB_OSABI_LINUX
;
2776 /* Initialize the current architecture based on INFO. If possible,
2777 re-use an architecture from ARCHES, which is a list of
2778 architectures already created during this debugging session.
2780 Called e.g. at program startup, when reading a core file, and when
2781 reading a binary file. */
2783 static struct gdbarch
*
2784 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2786 struct gdbarch_tdep
*tdep
;
2787 struct gdbarch
*gdbarch
;
2789 /* Try to deterimine the ABI of the object we are loading. */
2791 if (info
.abfd
!= NULL
&& info
.osabi
== GDB_OSABI_UNKNOWN
)
2793 switch (bfd_get_flavour (info
.abfd
))
2795 case bfd_target_aout_flavour
:
2796 /* Assume it's an old APCS-style ABI. */
2797 info
.osabi
= GDB_OSABI_ARM_APCS
;
2800 case bfd_target_coff_flavour
:
2801 /* Assume it's an old APCS-style ABI. */
2803 info
.osabi
= GDB_OSABI_ARM_APCS
;
2807 /* Leave it as "unknown". */
2812 /* If there is already a candidate, use it. */
2813 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2815 return arches
->gdbarch
;
2817 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
2818 gdbarch
= gdbarch_alloc (&info
, tdep
);
2820 /* We used to default to FPA for generic ARM, but almost nobody uses that
2821 now, and we now provide a way for the user to force the model. So
2822 default to the most useful variant. */
2823 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
2826 switch (info
.byte_order
)
2828 case BFD_ENDIAN_BIG
:
2829 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
2830 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
2831 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
2832 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
2836 case BFD_ENDIAN_LITTLE
:
2837 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
2838 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
2839 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
2840 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
2845 internal_error (__FILE__
, __LINE__
,
2846 "arm_gdbarch_init: bad byte order for float format");
2849 /* On ARM targets char defaults to unsigned. */
2850 set_gdbarch_char_signed (gdbarch
, 0);
2852 /* This should be low enough for everything. */
2853 tdep
->lowest_pc
= 0x20;
2854 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
2856 set_gdbarch_deprecated_call_dummy_words (gdbarch
, arm_call_dummy_words
);
2857 set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch
, 0);
2859 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
2861 /* Frame handling. */
2862 set_gdbarch_unwind_dummy_id (gdbarch
, arm_unwind_dummy_id
);
2863 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
2864 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
2866 set_gdbarch_frameless_function_invocation
2867 (gdbarch
, arm_frameless_function_invocation
);
2868 set_gdbarch_frame_args_skip (gdbarch
, 0);
2870 frame_base_set_default (gdbarch
, &arm_normal_base
);
2872 /* Address manipulation. */
2873 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
2874 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
2876 /* Offset from address of function to start of its code. */
2877 set_gdbarch_function_start_offset (gdbarch
, 0);
2879 /* Advance PC across function entry code. */
2880 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
2882 /* Get the PC when a frame might not be available. */
2883 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
, arm_saved_pc_after_call
);
2885 /* The stack grows downward. */
2886 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2888 /* Breakpoint manipulation. */
2889 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
2890 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2892 /* Information about registers, etc. */
2893 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
2894 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
2895 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
2896 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
2897 set_gdbarch_deprecated_register_byte (gdbarch
, arm_register_byte
);
2898 set_gdbarch_deprecated_register_bytes (gdbarch
,
2899 (NUM_GREGS
* INT_REGISTER_RAW_SIZE
2900 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
2901 + NUM_SREGS
* STATUS_REGISTER_SIZE
));
2902 set_gdbarch_num_regs (gdbarch
, NUM_GREGS
+ NUM_FREGS
+ NUM_SREGS
);
2903 set_gdbarch_deprecated_register_raw_size (gdbarch
, arm_register_raw_size
);
2904 set_gdbarch_deprecated_register_virtual_size (gdbarch
, arm_register_virtual_size
);
2905 set_gdbarch_deprecated_max_register_raw_size (gdbarch
, FP_REGISTER_RAW_SIZE
);
2906 set_gdbarch_deprecated_max_register_virtual_size (gdbarch
, FP_REGISTER_VIRTUAL_SIZE
);
2907 set_gdbarch_deprecated_register_virtual_type (gdbarch
, arm_register_type
);
2909 /* Internal <-> external register number maps. */
2910 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
2912 /* Integer registers are 4 bytes. */
2913 set_gdbarch_deprecated_register_size (gdbarch
, 4);
2914 set_gdbarch_register_name (gdbarch
, arm_register_name
);
2916 /* Returning results. */
2917 set_gdbarch_extract_return_value (gdbarch
, arm_extract_return_value
);
2918 set_gdbarch_store_return_value (gdbarch
, arm_store_return_value
);
2919 set_gdbarch_use_struct_convention (gdbarch
, arm_use_struct_convention
);
2920 set_gdbarch_extract_struct_value_address (gdbarch
,
2921 arm_extract_struct_value_address
);
2923 /* Single stepping. */
2924 /* XXX For an RDI target we should ask the target if it can single-step. */
2925 set_gdbarch_software_single_step (gdbarch
, arm_software_single_step
);
2928 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
2930 /* Minsymbol frobbing. */
2931 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
2932 set_gdbarch_coff_make_msymbol_special (gdbarch
,
2933 arm_coff_make_msymbol_special
);
2935 /* Hook in the ABI-specific overrides, if they have been registered. */
2936 gdbarch_init_osabi (info
, gdbarch
);
2938 /* Add some default predicates. */
2939 frame_unwind_append_sniffer (gdbarch
, arm_sigtramp_unwind_sniffer
);
2940 frame_unwind_append_sniffer (gdbarch
, arm_prologue_unwind_sniffer
);
2942 /* Now we have tuned the configuration, set a few final things,
2943 based on what the OS ABI has told us. */
2945 if (tdep
->jb_pc
>= 0)
2946 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
2948 /* Floating point sizes and format. */
2949 switch (info
.byte_order
)
2951 case BFD_ENDIAN_BIG
:
2952 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
2953 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_big
);
2954 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
2958 case BFD_ENDIAN_LITTLE
:
2959 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
2960 arm_set_fp (gdbarch
);
2964 internal_error (__FILE__
, __LINE__
,
2965 "arm_gdbarch_init: bad byte order for float format");
2972 arm_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
2974 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2979 fprintf_unfiltered (file
, "arm_dump_tdep: Lowest pc = 0x%lx",
2980 (unsigned long) tdep
->lowest_pc
);
2984 arm_init_abi_eabi_v1 (struct gdbarch_info info
,
2985 struct gdbarch
*gdbarch
)
2991 arm_init_abi_eabi_v2 (struct gdbarch_info info
,
2992 struct gdbarch
*gdbarch
)
2998 arm_init_abi_apcs (struct gdbarch_info info
,
2999 struct gdbarch
*gdbarch
)
3004 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
3007 _initialize_arm_tdep (void)
3009 struct ui_file
*stb
;
3011 struct cmd_list_element
*new_set
, *new_show
;
3012 const char *setname
;
3013 const char *setdesc
;
3014 const char **regnames
;
3016 static char *helptext
;
3018 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
3020 /* Register an ELF OS ABI sniffer for ARM binaries. */
3021 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
3022 bfd_target_elf_flavour
,
3023 arm_elf_osabi_sniffer
);
3025 /* Register some ABI variants for embedded systems. */
3026 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_EABI_V1
,
3027 arm_init_abi_eabi_v1
);
3028 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_EABI_V2
,
3029 arm_init_abi_eabi_v2
);
3030 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_APCS
,
3033 /* Get the number of possible sets of register names defined in opcodes. */
3034 num_disassembly_options
= get_arm_regname_num_options ();
3036 /* Add root prefix command for all "set arm"/"show arm" commands. */
3037 add_prefix_cmd ("arm", no_class
, set_arm_command
,
3038 "Various ARM-specific commands.",
3039 &setarmcmdlist
, "set arm ", 0, &setlist
);
3041 add_prefix_cmd ("arm", no_class
, show_arm_command
,
3042 "Various ARM-specific commands.",
3043 &showarmcmdlist
, "show arm ", 0, &showlist
);
3045 /* Sync the opcode insn printer with our register viewer. */
3046 parse_arm_disassembler_option ("reg-names-std");
3048 /* Begin creating the help text. */
3049 stb
= mem_fileopen ();
3050 fprintf_unfiltered (stb
, "Set the disassembly style.\n"
3051 "The valid values are:\n");
3053 /* Initialize the array that will be passed to add_set_enum_cmd(). */
3054 valid_disassembly_styles
3055 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
3056 for (i
= 0; i
< num_disassembly_options
; i
++)
3058 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
3059 valid_disassembly_styles
[i
] = setname
;
3060 fprintf_unfiltered (stb
, "%s - %s\n", setname
,
3062 /* Copy the default names (if found) and synchronize disassembler. */
3063 if (!strcmp (setname
, "std"))
3065 disassembly_style
= setname
;
3067 for (j
= 0; j
< numregs
; j
++)
3068 arm_register_names
[j
] = (char *) regnames
[j
];
3069 set_arm_regname_option (i
);
3072 /* Mark the end of valid options. */
3073 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
3075 /* Finish the creation of the help text. */
3076 fprintf_unfiltered (stb
, "The default is \"std\".");
3077 helptext
= ui_file_xstrdup (stb
, &length
);
3078 ui_file_delete (stb
);
3080 /* Add the deprecated disassembly-flavor command. */
3081 new_set
= add_set_enum_cmd ("disassembly-flavor", no_class
,
3082 valid_disassembly_styles
,
3086 set_cmd_sfunc (new_set
, set_disassembly_style_sfunc
);
3087 deprecate_cmd (new_set
, "set arm disassembly");
3088 deprecate_cmd (add_show_from_set (new_set
, &showlist
),
3089 "show arm disassembly");
3091 /* And now add the new interface. */
3092 new_set
= add_set_enum_cmd ("disassembler", no_class
,
3093 valid_disassembly_styles
, &disassembly_style
,
3094 helptext
, &setarmcmdlist
);
3096 set_cmd_sfunc (new_set
, set_disassembly_style_sfunc
);
3097 add_show_from_set (new_set
, &showarmcmdlist
);
3099 add_setshow_cmd_full ("apcs32", no_class
,
3100 var_boolean
, (char *) &arm_apcs_32
,
3101 "Set usage of ARM 32-bit mode.",
3102 "Show usage of ARM 32-bit mode.",
3104 &setlist
, &showlist
, &new_set
, &new_show
);
3105 deprecate_cmd (new_set
, "set arm apcs32");
3106 deprecate_cmd (new_show
, "show arm apcs32");
3108 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
3109 "Set usage of ARM 32-bit mode. "
3110 "When off, a 26-bit PC will be used.",
3111 "Show usage of ARM 32-bit mode. "
3112 "When off, a 26-bit PC will be used.",
3114 &setarmcmdlist
, &showarmcmdlist
);
3116 /* Add a command to allow the user to force the FPU model. */
3117 new_set
= add_set_enum_cmd
3118 ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
3119 "Set the floating point type.\n"
3120 "auto - Determine the FP typefrom the OS-ABI.\n"
3121 "softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n"
3122 "fpa - FPA co-processor (GCC compiled).\n"
3123 "softvfp - Software FP with pure-endian doubles.\n"
3124 "vfp - VFP co-processor.",
3126 set_cmd_sfunc (new_set
, set_fp_model_sfunc
);
3127 set_cmd_sfunc (add_show_from_set (new_set
, &showarmcmdlist
), show_fp_model
);
3129 /* Add the deprecated "othernames" command. */
3130 deprecate_cmd (add_com ("othernames", class_obscure
, arm_othernames
,
3131 "Switch to the next set of register names."),
3132 "set arm disassembly");
3134 /* Debugging flag. */
3135 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
3136 "Set ARM debugging. "
3137 "When on, arm-specific debugging is enabled.",
3138 "Show ARM debugging. "
3139 "When on, arm-specific debugging is enabled.",
3141 &setdebuglist
, &showdebuglist
);