1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper () */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
43 #include "target-descriptions.h"
44 #include "user-regs.h"
47 #include "gdb/sim-arm.h"
50 #include "coff/internal.h"
53 #include "gdb_assert.h"
57 /* Macros for setting and testing a bit in a minimal symbol that marks
58 it as Thumb function. The MSB of the minimal symbol's "info" field
59 is used for this purpose.
61 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
62 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
64 #define MSYMBOL_SET_SPECIAL(msym) \
65 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
68 #define MSYMBOL_IS_SPECIAL(msym) \
69 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
71 /* The list of available "set arm ..." and "show arm ..." commands. */
72 static struct cmd_list_element
*setarmcmdlist
= NULL
;
73 static struct cmd_list_element
*showarmcmdlist
= NULL
;
75 /* The type of floating-point to use. Keep this in sync with enum
76 arm_float_model, and the help string in _initialize_arm_tdep. */
77 static const char *fp_model_strings
[] =
87 /* A variable that can be configured by the user. */
88 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
89 static const char *current_fp_model
= "auto";
91 /* The ABI to use. Keep this in sync with arm_abi_kind. */
92 static const char *arm_abi_strings
[] =
100 /* A variable that can be configured by the user. */
101 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
102 static const char *arm_abi_string
= "auto";
104 /* Number of different reg name sets (options). */
105 static int num_disassembly_options
;
107 /* The standard register names, and all the valid aliases for them. */
112 } arm_register_aliases
[] = {
113 /* Basic register numbers. */
130 /* Synonyms (argument and variable registers). */
143 /* Other platform-specific names for r9. */
151 /* Names used by GCC (not listed in the ARM EABI). */
154 /* A special name from the older ATPCS. */
158 static const char *const arm_register_names
[] =
159 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
160 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
161 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
162 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
163 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
164 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
165 "fps", "cpsr" }; /* 24 25 */
167 /* Valid register name styles. */
168 static const char **valid_disassembly_styles
;
170 /* Disassembly style to use. Default to "std" register names. */
171 static const char *disassembly_style
;
173 /* This is used to keep the bfd arch_info in sync with the disassembly
175 static void set_disassembly_style_sfunc(char *, int,
176 struct cmd_list_element
*);
177 static void set_disassembly_style (void);
179 static void convert_from_extended (const struct floatformat
*, const void *,
181 static void convert_to_extended (const struct floatformat
*, void *,
184 struct arm_prologue_cache
186 /* The stack pointer at the time this frame was created; i.e. the
187 caller's stack pointer when this function was called. It is used
188 to identify this frame. */
191 /* The frame base for this frame is just prev_sp - frame size.
192 FRAMESIZE is the distance from the frame pointer to the
193 initial stack pointer. */
197 /* The register used to hold the frame pointer for this frame. */
200 /* Saved register offsets. */
201 struct trad_frame_saved_reg
*saved_regs
;
204 /* Addresses for calling Thumb functions have the bit 0 set.
205 Here are some macros to test, set, or clear bit 0 of addresses. */
206 #define IS_THUMB_ADDR(addr) ((addr) & 1)
207 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
208 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
210 /* Set to true if the 32-bit mode is in use. */
214 /* Determine if the program counter specified in MEMADDR is in a Thumb
218 arm_pc_is_thumb (CORE_ADDR memaddr
)
220 struct minimal_symbol
*sym
;
222 /* If bit 0 of the address is set, assume this is a Thumb address. */
223 if (IS_THUMB_ADDR (memaddr
))
226 /* Thumb functions have a "special" bit set in minimal symbols. */
227 sym
= lookup_minimal_symbol_by_pc (memaddr
);
230 return (MSYMBOL_IS_SPECIAL (sym
));
238 /* Remove useless bits from addresses in a running program. */
240 arm_addr_bits_remove (CORE_ADDR val
)
243 return (val
& (arm_pc_is_thumb (val
) ? 0xfffffffe : 0xfffffffc));
245 return (val
& 0x03fffffc);
248 /* When reading symbols, we need to zap the low bit of the address,
249 which may be set to 1 for Thumb functions. */
251 arm_smash_text_address (CORE_ADDR val
)
256 /* Analyze a Thumb prologue, looking for a recognizable stack frame
257 and frame pointer. Scan until we encounter a store that could
258 clobber the stack frame unexpectedly, or an unknown instruction. */
261 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
262 CORE_ADDR start
, CORE_ADDR limit
,
263 struct arm_prologue_cache
*cache
)
267 struct pv_area
*stack
;
268 struct cleanup
*back_to
;
271 for (i
= 0; i
< 16; i
++)
272 regs
[i
] = pv_register (i
, 0);
273 stack
= make_pv_area (ARM_SP_REGNUM
);
274 back_to
= make_cleanup_free_pv_area (stack
);
276 /* The call instruction saved PC in LR, and the current PC is not
277 interesting. Due to this file's conventions, we want the value
278 of LR at this function's entry, not at the call site, so we do
279 not record the save of the PC - when the ARM prologue analyzer
280 has also been converted to the pv mechanism, we could record the
281 save here and remove the hack in prev_register. */
282 regs
[ARM_PC_REGNUM
] = pv_unknown ();
284 while (start
< limit
)
288 insn
= read_memory_unsigned_integer (start
, 2);
290 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
295 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
298 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
299 whether to save LR (R14). */
300 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
302 /* Calculate offsets of saved R0-R7 and LR. */
303 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
304 if (mask
& (1 << regno
))
306 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
308 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
311 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
314 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
315 if (insn
& 0x80) /* Check for SUB. */
316 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
319 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
322 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
323 regs
[THUMB_FP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
325 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
327 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
328 int src_reg
= (insn
& 0x78) >> 3;
329 regs
[dst_reg
] = regs
[src_reg
];
331 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
333 /* Handle stores to the stack. Normally pushes are used,
334 but with GCC -mtpcs-frame, there may be other stores
335 in the prologue to create the frame. */
336 int regno
= (insn
>> 8) & 0x7;
339 offset
= (insn
& 0xff) << 2;
340 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
342 if (pv_area_store_would_trash (stack
, addr
))
345 pv_area_store (stack
, addr
, 4, regs
[regno
]);
349 /* We don't know what this instruction is. We're finished
350 scanning. NOTE: Recognizing more safe-to-ignore
351 instructions here will improve support for optimized
361 do_cleanups (back_to
);
365 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
367 /* Frame pointer is fp. Frame size is constant. */
368 cache
->framereg
= ARM_FP_REGNUM
;
369 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
371 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
373 /* Frame pointer is r7. Frame size is constant. */
374 cache
->framereg
= THUMB_FP_REGNUM
;
375 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
377 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
379 /* Try the stack pointer... this is a bit desperate. */
380 cache
->framereg
= ARM_SP_REGNUM
;
381 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
385 /* We're just out of luck. We don't know where the frame is. */
386 cache
->framereg
= -1;
387 cache
->framesize
= 0;
390 for (i
= 0; i
< 16; i
++)
391 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
392 cache
->saved_regs
[i
].addr
= offset
;
394 do_cleanups (back_to
);
398 /* Advance the PC across any function entry prologue instructions to
399 reach some "real" code.
401 The APCS (ARM Procedure Call Standard) defines the following
405 [stmfd sp!, {a1,a2,a3,a4}]
406 stmfd sp!, {...,fp,ip,lr,pc}
407 [stfe f7, [sp, #-12]!]
408 [stfe f6, [sp, #-12]!]
409 [stfe f5, [sp, #-12]!]
410 [stfe f4, [sp, #-12]!]
411 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
414 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
418 CORE_ADDR func_addr
, func_end
= 0;
420 struct symtab_and_line sal
;
422 /* If we're in a dummy frame, don't even try to skip the prologue. */
423 if (deprecated_pc_in_call_dummy (pc
))
426 /* See what the symbol table says. */
428 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
432 /* Found a function. */
433 sym
= lookup_symbol (func_name
, NULL
, VAR_DOMAIN
, NULL
, NULL
);
434 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
436 /* Don't use this trick for assembly source files. */
437 sal
= find_pc_line (func_addr
, 0);
438 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
443 /* Can't find the prologue end in the symbol table, try it the hard way
444 by disassembling the instructions. */
446 /* Like arm_scan_prologue, stop no later than pc + 64. */
447 if (func_end
== 0 || func_end
> pc
+ 64)
450 /* Check if this is Thumb code. */
451 if (arm_pc_is_thumb (pc
))
452 return thumb_analyze_prologue (gdbarch
, pc
, func_end
, NULL
);
454 for (skip_pc
= pc
; skip_pc
< func_end
; skip_pc
+= 4)
456 inst
= read_memory_unsigned_integer (skip_pc
, 4);
458 /* "mov ip, sp" is no longer a required part of the prologue. */
459 if (inst
== 0xe1a0c00d) /* mov ip, sp */
462 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
465 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
468 /* Some prologues begin with "str lr, [sp, #-4]!". */
469 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
472 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
475 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
478 /* Any insns after this point may float into the code, if it makes
479 for better instruction scheduling, so we skip them only if we
480 find them, but still consider the function to be frame-ful. */
482 /* We may have either one sfmfd instruction here, or several stfe
483 insns, depending on the version of floating point code we
485 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
488 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
491 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
494 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
497 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
498 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
499 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
502 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
503 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
504 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
507 /* Un-recognized instruction; stop scanning. */
511 return skip_pc
; /* End of prologue */
515 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
516 This function decodes a Thumb function prologue to determine:
517 1) the size of the stack frame
518 2) which registers are saved on it
519 3) the offsets of saved regs
520 4) the offset from the stack pointer to the frame pointer
522 A typical Thumb function prologue would create this stack frame
523 (offsets relative to FP)
524 old SP -> 24 stack parameters
527 R7 -> 0 local variables (16 bytes)
528 SP -> -12 additional stack space (12 bytes)
529 The frame size would thus be 36 bytes, and the frame offset would be
530 12 bytes. The frame register is R7.
532 The comments for thumb_skip_prolog() describe the algorithm we use
533 to detect the end of the prolog. */
537 thumb_scan_prologue (CORE_ADDR prev_pc
, struct arm_prologue_cache
*cache
)
539 CORE_ADDR prologue_start
;
540 CORE_ADDR prologue_end
;
541 CORE_ADDR current_pc
;
542 /* Which register has been copied to register n? */
545 bit 0 - push { rlist }
546 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
547 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
552 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
554 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
556 if (sal
.line
== 0) /* no line info, use current PC */
557 prologue_end
= prev_pc
;
558 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
559 prologue_end
= sal
.end
; /* (probably means no prologue) */
562 /* We're in the boondocks: we have no idea where the start of the
566 prologue_end
= min (prologue_end
, prev_pc
);
568 thumb_analyze_prologue (current_gdbarch
, prologue_start
, prologue_end
,
572 /* This function decodes an ARM function prologue to determine:
573 1) the size of the stack frame
574 2) which registers are saved on it
575 3) the offsets of saved regs
576 4) the offset from the stack pointer to the frame pointer
577 This information is stored in the "extra" fields of the frame_info.
579 There are two basic forms for the ARM prologue. The fixed argument
580 function call will look like:
583 stmfd sp!, {fp, ip, lr, pc}
587 Which would create this stack frame (offsets relative to FP):
588 IP -> 4 (caller's stack)
589 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
590 -4 LR (return address in caller)
591 -8 IP (copy of caller's SP)
593 SP -> -28 Local variables
595 The frame size would thus be 32 bytes, and the frame offset would be
596 28 bytes. The stmfd call can also save any of the vN registers it
597 plans to use, which increases the frame size accordingly.
599 Note: The stored PC is 8 off of the STMFD instruction that stored it
600 because the ARM Store instructions always store PC + 8 when you read
603 A variable argument function call will look like:
606 stmfd sp!, {a1, a2, a3, a4}
607 stmfd sp!, {fp, ip, lr, pc}
610 Which would create this stack frame (offsets relative to FP):
611 IP -> 20 (caller's stack)
616 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
617 -4 LR (return address in caller)
618 -8 IP (copy of caller's SP)
620 SP -> -28 Local variables
622 The frame size would thus be 48 bytes, and the frame offset would be
625 There is another potential complication, which is that the optimizer
626 will try to separate the store of fp in the "stmfd" instruction from
627 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
628 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
630 Also, note, the original version of the ARM toolchain claimed that there
633 instruction at the end of the prologue. I have never seen GCC produce
634 this, and the ARM docs don't mention it. We still test for it below in
640 arm_scan_prologue (struct frame_info
*next_frame
,
641 struct arm_prologue_cache
*cache
)
643 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
645 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
646 CORE_ADDR prev_pc
= frame_pc_unwind (next_frame
);
647 pv_t regs
[ARM_FPS_REGNUM
];
648 struct pv_area
*stack
;
649 struct cleanup
*back_to
;
652 /* Assume there is no frame until proven otherwise. */
653 cache
->framereg
= ARM_SP_REGNUM
;
654 cache
->framesize
= 0;
656 /* Check for Thumb prologue. */
657 if (arm_pc_is_thumb (prev_pc
))
659 thumb_scan_prologue (prev_pc
, cache
);
663 /* Find the function prologue. If we can't find the function in
664 the symbol table, peek in the stack frame to find the PC. */
665 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
667 /* One way to find the end of the prologue (which works well
668 for unoptimized code) is to do the following:
670 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
673 prologue_end = prev_pc;
674 else if (sal.end < prologue_end)
675 prologue_end = sal.end;
677 This mechanism is very accurate so long as the optimizer
678 doesn't move any instructions from the function body into the
679 prologue. If this happens, sal.end will be the last
680 instruction in the first hunk of prologue code just before
681 the first instruction that the scheduler has moved from
682 the body to the prologue.
684 In order to make sure that we scan all of the prologue
685 instructions, we use a slightly less accurate mechanism which
686 may scan more than necessary. To help compensate for this
687 lack of accuracy, the prologue scanning loop below contains
688 several clauses which'll cause the loop to terminate early if
689 an implausible prologue instruction is encountered.
695 is a suitable endpoint since it accounts for the largest
696 possible prologue plus up to five instructions inserted by
699 if (prologue_end
> prologue_start
+ 64)
701 prologue_end
= prologue_start
+ 64; /* See above. */
706 /* We have no symbol information. Our only option is to assume this
707 function has a standard stack frame and the normal frame register.
708 Then, we can find the value of our frame pointer on entrance to
709 the callee (or at the present moment if this is the innermost frame).
710 The value stored there should be the address of the stmfd + 8. */
712 LONGEST return_value
;
714 frame_loc
= frame_unwind_register_unsigned (next_frame
, ARM_FP_REGNUM
);
715 if (!safe_read_memory_integer (frame_loc
, 4, &return_value
))
719 prologue_start
= gdbarch_addr_bits_remove
720 (gdbarch
, return_value
) - 8;
721 prologue_end
= prologue_start
+ 64; /* See above. */
725 if (prev_pc
< prologue_end
)
726 prologue_end
= prev_pc
;
728 /* Now search the prologue looking for instructions that set up the
729 frame pointer, adjust the stack pointer, and save registers.
731 Be careful, however, and if it doesn't look like a prologue,
732 don't try to scan it. If, for instance, a frameless function
733 begins with stmfd sp!, then we will tell ourselves there is
734 a frame, which will confuse stack traceback, as well as "finish"
735 and other operations that rely on a knowledge of the stack
738 In the APCS, the prologue should start with "mov ip, sp" so
739 if we don't see this as the first insn, we will stop.
741 [Note: This doesn't seem to be true any longer, so it's now an
742 optional part of the prologue. - Kevin Buettner, 2001-11-20]
744 [Note further: The "mov ip,sp" only seems to be missing in
745 frameless functions at optimization level "-O2" or above,
746 in which case it is often (but not always) replaced by
747 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
749 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
750 regs
[regno
] = pv_register (regno
, 0);
751 stack
= make_pv_area (ARM_SP_REGNUM
);
752 back_to
= make_cleanup_free_pv_area (stack
);
754 regs
[ARM_PC_REGNUM
] = pv_unknown ();
756 for (current_pc
= prologue_start
;
757 current_pc
< prologue_end
;
760 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
762 if (insn
== 0xe1a0c00d) /* mov ip, sp */
764 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
767 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
769 unsigned imm
= insn
& 0xff; /* immediate value */
770 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
771 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
772 regs
[ARM_IP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], imm
);
775 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
777 unsigned imm
= insn
& 0xff; /* immediate value */
778 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
779 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
780 regs
[ARM_IP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
783 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
785 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
787 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
788 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[ARM_LR_REGNUM
]);
791 else if ((insn
& 0xffff0000) == 0xe92d0000)
792 /* stmfd sp!, {..., fp, ip, lr, pc}
794 stmfd sp!, {a1, a2, a3, a4} */
796 int mask
= insn
& 0xffff;
798 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
801 /* Calculate offsets of saved registers. */
802 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
803 if (mask
& (1 << regno
))
805 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
806 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
809 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
810 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
811 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
813 /* No need to add this to saved_regs -- it's just an arg reg. */
816 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
817 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
818 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
820 /* No need to add this to saved_regs -- it's just an arg reg. */
823 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
825 unsigned imm
= insn
& 0xff; /* immediate value */
826 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
827 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
828 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
830 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
832 unsigned imm
= insn
& 0xff; /* immediate value */
833 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
834 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
835 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
837 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
838 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
840 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
843 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
844 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
845 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
847 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
848 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
851 unsigned int fp_start_reg
, fp_bound_reg
;
853 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
856 if ((insn
& 0x800) == 0x800) /* N0 is set */
858 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
865 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
871 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
872 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
873 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
875 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
876 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
877 regs
[fp_start_reg
++]);
880 else if ((insn
& 0xf0000000) != 0xe0000000)
881 break; /* Condition not true, exit early */
882 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
883 break; /* Don't scan past a block load */
885 /* The optimizer might shove anything into the prologue,
886 so we just skip what we don't recognize. */
890 /* The frame size is just the distance from the frame register
891 to the original stack pointer. */
892 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
894 /* Frame pointer is fp. */
895 cache
->framereg
= ARM_FP_REGNUM
;
896 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
898 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
900 /* Try the stack pointer... this is a bit desperate. */
901 cache
->framereg
= ARM_SP_REGNUM
;
902 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
906 /* We're just out of luck. We don't know where the frame is. */
907 cache
->framereg
= -1;
908 cache
->framesize
= 0;
911 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
912 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
913 cache
->saved_regs
[regno
].addr
= offset
;
915 do_cleanups (back_to
);
918 static struct arm_prologue_cache
*
919 arm_make_prologue_cache (struct frame_info
*next_frame
)
922 struct arm_prologue_cache
*cache
;
923 CORE_ADDR unwound_fp
;
925 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
926 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
928 arm_scan_prologue (next_frame
, cache
);
930 unwound_fp
= frame_unwind_register_unsigned (next_frame
, cache
->framereg
);
934 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
936 /* Calculate actual addresses of saved registers using offsets
937 determined by arm_scan_prologue. */
938 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (next_frame
)); reg
++)
939 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
940 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
945 /* Our frame ID for a normal frame is the current function's starting PC
946 and the caller's SP when we were called. */
949 arm_prologue_this_id (struct frame_info
*next_frame
,
951 struct frame_id
*this_id
)
953 struct arm_prologue_cache
*cache
;
957 if (*this_cache
== NULL
)
958 *this_cache
= arm_make_prologue_cache (next_frame
);
961 func
= frame_func_unwind (next_frame
, NORMAL_FRAME
);
963 /* This is meant to halt the backtrace at "_start". Make sure we
964 don't halt it at a generic dummy frame. */
965 if (func
<= gdbarch_tdep (get_frame_arch (next_frame
))->lowest_pc
)
968 /* If we've hit a wall, stop. */
969 if (cache
->prev_sp
== 0)
972 id
= frame_id_build (cache
->prev_sp
, func
);
977 arm_prologue_prev_register (struct frame_info
*next_frame
,
981 enum lval_type
*lvalp
,
986 struct arm_prologue_cache
*cache
;
988 if (*this_cache
== NULL
)
989 *this_cache
= arm_make_prologue_cache (next_frame
);
992 /* If we are asked to unwind the PC, then we need to return the LR
993 instead. The saved value of PC points into this frame's
994 prologue, not the next frame's resume location. */
995 if (prev_regnum
== ARM_PC_REGNUM
)
996 prev_regnum
= ARM_LR_REGNUM
;
998 /* SP is generally not saved to the stack, but this frame is
999 identified by NEXT_FRAME's stack pointer at the time of the call.
1000 The value was already reconstructed into PREV_SP. */
1001 if (prev_regnum
== ARM_SP_REGNUM
)
1005 store_unsigned_integer (valuep
, 4, cache
->prev_sp
);
1009 trad_frame_get_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
1010 optimized
, lvalp
, addrp
, realnump
, valuep
);
1013 struct frame_unwind arm_prologue_unwind
= {
1015 arm_prologue_this_id
,
1016 arm_prologue_prev_register
1019 static const struct frame_unwind
*
1020 arm_prologue_unwind_sniffer (struct frame_info
*next_frame
)
1022 return &arm_prologue_unwind
;
1025 static struct arm_prologue_cache
*
1026 arm_make_stub_cache (struct frame_info
*next_frame
)
1029 struct arm_prologue_cache
*cache
;
1030 CORE_ADDR unwound_fp
;
1032 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1033 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1035 cache
->prev_sp
= frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
);
1040 /* Our frame ID for a stub frame is the current SP and LR. */
1043 arm_stub_this_id (struct frame_info
*next_frame
,
1045 struct frame_id
*this_id
)
1047 struct arm_prologue_cache
*cache
;
1049 if (*this_cache
== NULL
)
1050 *this_cache
= arm_make_stub_cache (next_frame
);
1051 cache
= *this_cache
;
1053 *this_id
= frame_id_build (cache
->prev_sp
,
1054 frame_pc_unwind (next_frame
));
1057 struct frame_unwind arm_stub_unwind
= {
1060 arm_prologue_prev_register
1063 static const struct frame_unwind
*
1064 arm_stub_unwind_sniffer (struct frame_info
*next_frame
)
1066 CORE_ADDR addr_in_block
;
1069 addr_in_block
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1070 if (in_plt_section (addr_in_block
, NULL
)
1071 || target_read_memory (frame_pc_unwind (next_frame
), dummy
, 4) != 0)
1072 return &arm_stub_unwind
;
1078 arm_normal_frame_base (struct frame_info
*next_frame
, void **this_cache
)
1080 struct arm_prologue_cache
*cache
;
1082 if (*this_cache
== NULL
)
1083 *this_cache
= arm_make_prologue_cache (next_frame
);
1084 cache
= *this_cache
;
1086 return cache
->prev_sp
- cache
->framesize
;
1089 struct frame_base arm_normal_base
= {
1090 &arm_prologue_unwind
,
1091 arm_normal_frame_base
,
1092 arm_normal_frame_base
,
1093 arm_normal_frame_base
1096 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1097 dummy frame. The frame ID's base needs to match the TOS value
1098 saved by save_dummy_frame_tos() and returned from
1099 arm_push_dummy_call, and the PC needs to match the dummy frame's
1102 static struct frame_id
1103 arm_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1105 return frame_id_build (frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
),
1106 frame_pc_unwind (next_frame
));
1109 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1110 be used to construct the previous frame's ID, after looking up the
1111 containing function). */
1114 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1117 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1118 return arm_addr_bits_remove (pc
);
1122 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1124 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1127 /* When arguments must be pushed onto the stack, they go on in reverse
1128 order. The code below implements a FILO (stack) to do this. */
1133 struct stack_item
*prev
;
1137 static struct stack_item
*
1138 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1140 struct stack_item
*si
;
1141 si
= xmalloc (sizeof (struct stack_item
));
1142 si
->data
= xmalloc (len
);
1145 memcpy (si
->data
, contents
, len
);
1149 static struct stack_item
*
1150 pop_stack_item (struct stack_item
*si
)
1152 struct stack_item
*dead
= si
;
1160 /* Return the alignment (in bytes) of the given type. */
1163 arm_type_align (struct type
*t
)
1169 t
= check_typedef (t
);
1170 switch (TYPE_CODE (t
))
1173 /* Should never happen. */
1174 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1178 case TYPE_CODE_ENUM
:
1182 case TYPE_CODE_RANGE
:
1183 case TYPE_CODE_BITSTRING
:
1185 case TYPE_CODE_CHAR
:
1186 case TYPE_CODE_BOOL
:
1187 return TYPE_LENGTH (t
);
1189 case TYPE_CODE_ARRAY
:
1190 case TYPE_CODE_COMPLEX
:
1191 /* TODO: What about vector types? */
1192 return arm_type_align (TYPE_TARGET_TYPE (t
));
1194 case TYPE_CODE_STRUCT
:
1195 case TYPE_CODE_UNION
:
1197 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1199 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
1207 /* We currently only support passing parameters in integer registers. This
1208 conforms with GCC's default model. Several other variants exist and
1209 we should probably support some of them based on the selected ABI. */
1212 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1213 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1214 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1215 CORE_ADDR struct_addr
)
1220 struct stack_item
*si
= NULL
;
1222 /* Set the return address. For the ARM, the return breakpoint is
1223 always at BP_ADDR. */
1224 /* XXX Fix for Thumb. */
1225 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1227 /* Walk through the list of args and determine how large a temporary
1228 stack is required. Need to take care here as structs may be
1229 passed on the stack, and we have to to push them. */
1232 argreg
= ARM_A1_REGNUM
;
1235 /* The struct_return pointer occupies the first parameter
1236 passing register. */
1240 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = 0x%s\n",
1241 gdbarch_register_name (gdbarch
, argreg
),
1242 paddr (struct_addr
));
1243 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1247 for (argnum
= 0; argnum
< nargs
; argnum
++)
1250 struct type
*arg_type
;
1251 struct type
*target_type
;
1252 enum type_code typecode
;
1256 arg_type
= check_typedef (value_type (args
[argnum
]));
1257 len
= TYPE_LENGTH (arg_type
);
1258 target_type
= TYPE_TARGET_TYPE (arg_type
);
1259 typecode
= TYPE_CODE (arg_type
);
1260 val
= value_contents_writeable (args
[argnum
]);
1262 align
= arm_type_align (arg_type
);
1263 /* Round alignment up to a whole number of words. */
1264 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
1265 /* Different ABIs have different maximum alignments. */
1266 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
1268 /* The APCS ABI only requires word alignment. */
1269 align
= INT_REGISTER_SIZE
;
1273 /* The AAPCS requires at most doubleword alignment. */
1274 if (align
> INT_REGISTER_SIZE
* 2)
1275 align
= INT_REGISTER_SIZE
* 2;
1278 /* Push stack padding for dowubleword alignment. */
1279 if (nstack
& (align
- 1))
1281 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1282 nstack
+= INT_REGISTER_SIZE
;
1285 /* Doubleword aligned quantities must go in even register pairs. */
1286 if (argreg
<= ARM_LAST_ARG_REGNUM
1287 && align
> INT_REGISTER_SIZE
1291 /* If the argument is a pointer to a function, and it is a
1292 Thumb function, create a LOCAL copy of the value and set
1293 the THUMB bit in it. */
1294 if (TYPE_CODE_PTR
== typecode
1295 && target_type
!= NULL
1296 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1298 CORE_ADDR regval
= extract_unsigned_integer (val
, len
);
1299 if (arm_pc_is_thumb (regval
))
1302 store_unsigned_integer (val
, len
, MAKE_THUMB_ADDR (regval
));
1306 /* Copy the argument to general registers or the stack in
1307 register-sized pieces. Large arguments are split between
1308 registers and stack. */
1311 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
1313 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1315 /* The argument is being passed in a general purpose
1317 CORE_ADDR regval
= extract_unsigned_integer (val
, partial_len
);
1318 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1319 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
1321 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1323 gdbarch_register_name
1325 phex (regval
, INT_REGISTER_SIZE
));
1326 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1331 /* Push the arguments onto the stack. */
1333 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1335 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1336 nstack
+= INT_REGISTER_SIZE
;
1343 /* If we have an odd number of words to push, then decrement the stack
1344 by one word now, so first stack argument will be dword aligned. */
1351 write_memory (sp
, si
->data
, si
->len
);
1352 si
= pop_stack_item (si
);
1355 /* Finally, update teh SP register. */
1356 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1362 /* Always align the frame to an 8-byte boundary. This is required on
1363 some platforms and harmless on the rest. */
1366 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1368 /* Align the stack to eight bytes. */
1369 return sp
& ~ (CORE_ADDR
) 7;
1373 print_fpu_flags (int flags
)
1375 if (flags
& (1 << 0))
1376 fputs ("IVO ", stdout
);
1377 if (flags
& (1 << 1))
1378 fputs ("DVZ ", stdout
);
1379 if (flags
& (1 << 2))
1380 fputs ("OFL ", stdout
);
1381 if (flags
& (1 << 3))
1382 fputs ("UFL ", stdout
);
1383 if (flags
& (1 << 4))
1384 fputs ("INX ", stdout
);
1388 /* Print interesting information about the floating point processor
1389 (if present) or emulator. */
1391 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1392 struct frame_info
*frame
, const char *args
)
1394 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
1397 type
= (status
>> 24) & 127;
1398 if (status
& (1 << 31))
1399 printf (_("Hardware FPU type %d\n"), type
);
1401 printf (_("Software FPU type %d\n"), type
);
1402 /* i18n: [floating point unit] mask */
1403 fputs (_("mask: "), stdout
);
1404 print_fpu_flags (status
>> 16);
1405 /* i18n: [floating point unit] flags */
1406 fputs (_("flags: "), stdout
);
1407 print_fpu_flags (status
);
1410 /* Return the GDB type object for the "standard" data type of data in
1413 static struct type
*
1414 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
1416 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1417 return builtin_type_arm_ext
;
1418 else if (regnum
== ARM_SP_REGNUM
)
1419 return builtin_type_void_data_ptr
;
1420 else if (regnum
== ARM_PC_REGNUM
)
1421 return builtin_type_void_func_ptr
;
1422 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
1423 /* These registers are only supported on targets which supply
1424 an XML description. */
1425 return builtin_type_int0
;
1427 return builtin_type_uint32
;
1430 /* Map a DWARF register REGNUM onto the appropriate GDB register
1434 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
1436 /* Core integer regs. */
1437 if (reg
>= 0 && reg
<= 15)
1440 /* Legacy FPA encoding. These were once used in a way which
1441 overlapped with VFP register numbering, so their use is
1442 discouraged, but GDB doesn't support the ARM toolchain
1443 which used them for VFP. */
1444 if (reg
>= 16 && reg
<= 23)
1445 return ARM_F0_REGNUM
+ reg
- 16;
1447 /* New assignments for the FPA registers. */
1448 if (reg
>= 96 && reg
<= 103)
1449 return ARM_F0_REGNUM
+ reg
- 96;
1451 /* WMMX register assignments. */
1452 if (reg
>= 104 && reg
<= 111)
1453 return ARM_WCGR0_REGNUM
+ reg
- 104;
1455 if (reg
>= 112 && reg
<= 127)
1456 return ARM_WR0_REGNUM
+ reg
- 112;
1458 if (reg
>= 192 && reg
<= 199)
1459 return ARM_WC0_REGNUM
+ reg
- 192;
1464 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1466 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
1469 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
1471 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
1472 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
1474 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
1475 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
1477 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
1478 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
1480 if (reg
< NUM_GREGS
)
1481 return SIM_ARM_R0_REGNUM
+ reg
;
1484 if (reg
< NUM_FREGS
)
1485 return SIM_ARM_FP0_REGNUM
+ reg
;
1488 if (reg
< NUM_SREGS
)
1489 return SIM_ARM_FPS_REGNUM
+ reg
;
1492 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
1495 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1496 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1497 It is thought that this is is the floating-point register format on
1498 little-endian systems. */
1501 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
1505 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1506 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1508 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1510 floatformat_from_doublest (fmt
, &d
, dbl
);
1514 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
)
1517 floatformat_to_doublest (fmt
, ptr
, &d
);
1518 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1519 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1521 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1526 condition_true (unsigned long cond
, unsigned long status_reg
)
1528 if (cond
== INST_AL
|| cond
== INST_NV
)
1534 return ((status_reg
& FLAG_Z
) != 0);
1536 return ((status_reg
& FLAG_Z
) == 0);
1538 return ((status_reg
& FLAG_C
) != 0);
1540 return ((status_reg
& FLAG_C
) == 0);
1542 return ((status_reg
& FLAG_N
) != 0);
1544 return ((status_reg
& FLAG_N
) == 0);
1546 return ((status_reg
& FLAG_V
) != 0);
1548 return ((status_reg
& FLAG_V
) == 0);
1550 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1552 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1554 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1556 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1558 return (((status_reg
& FLAG_Z
) == 0) &&
1559 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1561 return (((status_reg
& FLAG_Z
) != 0) ||
1562 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1567 /* Support routines for single stepping. Calculate the next PC value. */
1568 #define submask(x) ((1L << ((x) + 1)) - 1)
1569 #define bit(obj,st) (((obj) >> (st)) & 1)
1570 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1571 #define sbits(obj,st,fn) \
1572 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1573 #define BranchDest(addr,instr) \
1574 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1577 static unsigned long
1578 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
1579 unsigned long pc_val
, unsigned long status_reg
)
1581 unsigned long res
, shift
;
1582 int rm
= bits (inst
, 0, 3);
1583 unsigned long shifttype
= bits (inst
, 5, 6);
1587 int rs
= bits (inst
, 8, 11);
1588 shift
= (rs
== 15 ? pc_val
+ 8
1589 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
1592 shift
= bits (inst
, 7, 11);
1595 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1596 + (bit (inst
, 4) ? 12 : 8))
1597 : get_frame_register_unsigned (frame
, rm
));
1602 res
= shift
>= 32 ? 0 : res
<< shift
;
1606 res
= shift
>= 32 ? 0 : res
>> shift
;
1612 res
= ((res
& 0x80000000L
)
1613 ? ~((~res
) >> shift
) : res
>> shift
);
1616 case 3: /* ROR/RRX */
1619 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1621 res
= (res
>> shift
) | (res
<< (32 - shift
));
1625 return res
& 0xffffffff;
1628 /* Return number of 1-bits in VAL. */
1631 bitcount (unsigned long val
)
1634 for (nbits
= 0; val
!= 0; nbits
++)
1635 val
&= val
- 1; /* delete rightmost 1-bit in val */
1640 thumb_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1642 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1643 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1644 unsigned short inst1
= read_memory_unsigned_integer (pc
, 2);
1645 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1646 unsigned long offset
;
1648 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1652 /* Fetch the saved PC from the stack. It's stored above
1653 all of the other registers. */
1654 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
1655 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
1656 nextpc
= (CORE_ADDR
) read_memory_unsigned_integer (sp
+ offset
, 4);
1657 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1659 error (_("Infinite loop detected"));
1661 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1663 unsigned long status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
1664 unsigned long cond
= bits (inst1
, 8, 11);
1665 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1666 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1668 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1670 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1672 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link, and blx */
1674 unsigned short inst2
= read_memory_unsigned_integer (pc
+ 2, 2);
1675 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1676 nextpc
= pc_val
+ offset
;
1677 /* For BLX make sure to clear the low bits. */
1678 if (bits (inst2
, 11, 12) == 1)
1679 nextpc
= nextpc
& 0xfffffffc;
1681 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
1683 if (bits (inst1
, 3, 6) == 0x0f)
1686 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
1688 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1690 error (_("Infinite loop detected"));
1697 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1699 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1700 unsigned long pc_val
;
1701 unsigned long this_instr
;
1702 unsigned long status
;
1705 if (arm_pc_is_thumb (pc
))
1706 return thumb_get_next_pc (frame
, pc
);
1708 pc_val
= (unsigned long) pc
;
1709 this_instr
= read_memory_unsigned_integer (pc
, 4);
1710 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
1711 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1713 if (bits (this_instr
, 28, 31) == INST_NV
)
1714 switch (bits (this_instr
, 24, 27))
1719 /* Branch with Link and change to Thumb. */
1720 nextpc
= BranchDest (pc
, this_instr
);
1721 nextpc
|= bit (this_instr
, 24) << 1;
1723 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1725 error (_("Infinite loop detected"));
1731 /* Coprocessor register transfer. */
1732 if (bits (this_instr
, 12, 15) == 15)
1733 error (_("Invalid update to pc in instruction"));
1736 else if (condition_true (bits (this_instr
, 28, 31), status
))
1738 switch (bits (this_instr
, 24, 27))
1741 case 0x1: /* data processing */
1745 unsigned long operand1
, operand2
, result
= 0;
1749 if (bits (this_instr
, 12, 15) != 15)
1752 if (bits (this_instr
, 22, 25) == 0
1753 && bits (this_instr
, 4, 7) == 9) /* multiply */
1754 error (_("Invalid update to pc in instruction"));
1756 /* BX <reg>, BLX <reg> */
1757 if (bits (this_instr
, 4, 27) == 0x12fff1
1758 || bits (this_instr
, 4, 27) == 0x12fff3)
1760 rn
= bits (this_instr
, 0, 3);
1761 result
= (rn
== 15) ? pc_val
+ 8
1762 : get_frame_register_unsigned (frame
, rn
);
1763 nextpc
= (CORE_ADDR
) gdbarch_addr_bits_remove
1767 error (_("Infinite loop detected"));
1772 /* Multiply into PC */
1773 c
= (status
& FLAG_C
) ? 1 : 0;
1774 rn
= bits (this_instr
, 16, 19);
1775 operand1
= (rn
== 15) ? pc_val
+ 8
1776 : get_frame_register_unsigned (frame
, rn
);
1778 if (bit (this_instr
, 25))
1780 unsigned long immval
= bits (this_instr
, 0, 7);
1781 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1782 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1785 else /* operand 2 is a shifted register */
1786 operand2
= shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
);
1788 switch (bits (this_instr
, 21, 24))
1791 result
= operand1
& operand2
;
1795 result
= operand1
^ operand2
;
1799 result
= operand1
- operand2
;
1803 result
= operand2
- operand1
;
1807 result
= operand1
+ operand2
;
1811 result
= operand1
+ operand2
+ c
;
1815 result
= operand1
- operand2
+ c
;
1819 result
= operand2
- operand1
+ c
;
1825 case 0xb: /* tst, teq, cmp, cmn */
1826 result
= (unsigned long) nextpc
;
1830 result
= operand1
| operand2
;
1834 /* Always step into a function. */
1839 result
= operand1
& ~operand2
;
1846 nextpc
= (CORE_ADDR
) gdbarch_addr_bits_remove
1850 error (_("Infinite loop detected"));
1855 case 0x5: /* data transfer */
1858 if (bit (this_instr
, 20))
1861 if (bits (this_instr
, 12, 15) == 15)
1867 if (bit (this_instr
, 22))
1868 error (_("Invalid update to pc in instruction"));
1870 /* byte write to PC */
1871 rn
= bits (this_instr
, 16, 19);
1872 base
= (rn
== 15) ? pc_val
+ 8
1873 : get_frame_register_unsigned (frame
, rn
);
1874 if (bit (this_instr
, 24))
1877 int c
= (status
& FLAG_C
) ? 1 : 0;
1878 unsigned long offset
=
1879 (bit (this_instr
, 25)
1880 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
1881 : bits (this_instr
, 0, 11));
1883 if (bit (this_instr
, 23))
1888 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1891 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1894 error (_("Infinite loop detected"));
1900 case 0x9: /* block transfer */
1901 if (bit (this_instr
, 20))
1904 if (bit (this_instr
, 15))
1909 if (bit (this_instr
, 23))
1912 unsigned long reglist
= bits (this_instr
, 0, 14);
1913 offset
= bitcount (reglist
) * 4;
1914 if (bit (this_instr
, 24)) /* pre */
1917 else if (bit (this_instr
, 24))
1921 unsigned long rn_val
=
1922 get_frame_register_unsigned (frame
,
1923 bits (this_instr
, 16, 19));
1925 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1929 nextpc
= gdbarch_addr_bits_remove
1932 error (_("Infinite loop detected"));
1937 case 0xb: /* branch & link */
1938 case 0xa: /* branch */
1940 nextpc
= BranchDest (pc
, this_instr
);
1942 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1944 error (_("Infinite loop detected"));
1950 case 0xe: /* coproc ops */
1955 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
1963 /* single_step() is called just before we want to resume the inferior,
1964 if we want to single-step it but there is no hardware or kernel
1965 single-step support. We find the target of the coming instruction
1966 and breakpoint it. */
1969 arm_software_single_step (struct frame_info
*frame
)
1971 /* NOTE: This may insert the wrong breakpoint instruction when
1972 single-stepping over a mode-changing instruction, if the
1973 CPSR heuristics are used. */
1975 CORE_ADDR next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
1976 insert_single_step_breakpoint (next_pc
);
1981 #include "bfd-in2.h"
1982 #include "libcoff.h"
1985 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
1987 if (arm_pc_is_thumb (memaddr
))
1989 static asymbol
*asym
;
1990 static combined_entry_type ce
;
1991 static struct coff_symbol_struct csym
;
1992 static struct bfd fake_bfd
;
1993 static bfd_target fake_target
;
1995 if (csym
.native
== NULL
)
1997 /* Create a fake symbol vector containing a Thumb symbol.
1998 This is solely so that the code in print_insn_little_arm()
1999 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2000 the presence of a Thumb symbol and switch to decoding
2001 Thumb instructions. */
2003 fake_target
.flavour
= bfd_target_coff_flavour
;
2004 fake_bfd
.xvec
= &fake_target
;
2005 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
2007 csym
.symbol
.the_bfd
= &fake_bfd
;
2008 csym
.symbol
.name
= "fake";
2009 asym
= (asymbol
*) & csym
;
2012 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
2013 info
->symbols
= &asym
;
2016 info
->symbols
= NULL
;
2018 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
2019 return print_insn_big_arm (memaddr
, info
);
2021 return print_insn_little_arm (memaddr
, info
);
2024 /* The following define instruction sequences that will cause ARM
2025 cpu's to take an undefined instruction trap. These are used to
2026 signal a breakpoint to GDB.
2028 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2029 modes. A different instruction is required for each mode. The ARM
2030 cpu's can also be big or little endian. Thus four different
2031 instructions are needed to support all cases.
2033 Note: ARMv4 defines several new instructions that will take the
2034 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2035 not in fact add the new instructions. The new undefined
2036 instructions in ARMv4 are all instructions that had no defined
2037 behaviour in earlier chips. There is no guarantee that they will
2038 raise an exception, but may be treated as NOP's. In practice, it
2039 may only safe to rely on instructions matching:
2041 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2042 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2043 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2045 Even this may only true if the condition predicate is true. The
2046 following use a condition predicate of ALWAYS so it is always TRUE.
2048 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2049 and NetBSD all use a software interrupt rather than an undefined
2050 instruction to force a trap. This can be handled by by the
2051 abi-specific code during establishment of the gdbarch vector. */
2053 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2054 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2055 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
2056 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
2058 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
2059 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
2060 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2061 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2063 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2064 the program counter value to determine whether a 16-bit or 32-bit
2065 breakpoint should be used. It returns a pointer to a string of
2066 bytes that encode a breakpoint instruction, stores the length of
2067 the string to *lenptr, and adjusts the program counter (if
2068 necessary) to point to the actual memory location where the
2069 breakpoint should be inserted. */
2071 static const unsigned char *
2072 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
2074 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2076 if (arm_pc_is_thumb (*pcptr
))
2078 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2079 *lenptr
= tdep
->thumb_breakpoint_size
;
2080 return tdep
->thumb_breakpoint
;
2084 *lenptr
= tdep
->arm_breakpoint_size
;
2085 return tdep
->arm_breakpoint
;
2089 /* Extract from an array REGBUF containing the (raw) register state a
2090 function return value of type TYPE, and copy that, in virtual
2091 format, into VALBUF. */
2094 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
2097 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2099 switch (gdbarch_tdep (get_regcache_arch (regs
))->fp_model
)
2103 /* The value is in register F0 in internal format. We need to
2104 extract the raw value and then convert it to the desired
2106 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
2108 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
2109 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
2114 case ARM_FLOAT_SOFT_FPA
:
2115 case ARM_FLOAT_SOFT_VFP
:
2116 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
2117 if (TYPE_LENGTH (type
) > 4)
2118 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
2119 valbuf
+ INT_REGISTER_SIZE
);
2124 (__FILE__
, __LINE__
,
2125 _("arm_extract_return_value: Floating point model not supported"));
2129 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2130 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2131 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2132 || TYPE_CODE (type
) == TYPE_CODE_PTR
2133 || TYPE_CODE (type
) == TYPE_CODE_REF
2134 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2136 /* If the the type is a plain integer, then the access is
2137 straight-forward. Otherwise we have to play around a bit more. */
2138 int len
= TYPE_LENGTH (type
);
2139 int regno
= ARM_A1_REGNUM
;
2144 /* By using store_unsigned_integer we avoid having to do
2145 anything special for small big-endian values. */
2146 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2147 store_unsigned_integer (valbuf
,
2148 (len
> INT_REGISTER_SIZE
2149 ? INT_REGISTER_SIZE
: len
),
2151 len
-= INT_REGISTER_SIZE
;
2152 valbuf
+= INT_REGISTER_SIZE
;
2157 /* For a structure or union the behaviour is as if the value had
2158 been stored to word-aligned memory and then loaded into
2159 registers with 32-bit load instruction(s). */
2160 int len
= TYPE_LENGTH (type
);
2161 int regno
= ARM_A1_REGNUM
;
2162 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2166 regcache_cooked_read (regs
, regno
++, tmpbuf
);
2167 memcpy (valbuf
, tmpbuf
,
2168 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2169 len
-= INT_REGISTER_SIZE
;
2170 valbuf
+= INT_REGISTER_SIZE
;
2176 /* Will a function return an aggregate type in memory or in a
2177 register? Return 0 if an aggregate type can be returned in a
2178 register, 1 if it must be returned in memory. */
2181 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2184 enum type_code code
;
2186 CHECK_TYPEDEF (type
);
2188 /* In the ARM ABI, "integer" like aggregate types are returned in
2189 registers. For an aggregate type to be integer like, its size
2190 must be less than or equal to INT_REGISTER_SIZE and the
2191 offset of each addressable subfield must be zero. Note that bit
2192 fields are not addressable, and all addressable subfields of
2193 unions always start at offset zero.
2195 This function is based on the behaviour of GCC 2.95.1.
2196 See: gcc/arm.c: arm_return_in_memory() for details.
2198 Note: All versions of GCC before GCC 2.95.2 do not set up the
2199 parameters correctly for a function returning the following
2200 structure: struct { float f;}; This should be returned in memory,
2201 not a register. Richard Earnshaw sent me a patch, but I do not
2202 know of any way to detect if a function like the above has been
2203 compiled with the correct calling convention. */
2205 /* All aggregate types that won't fit in a register must be returned
2207 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
2212 /* The AAPCS says all aggregates not larger than a word are returned
2214 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
2217 /* The only aggregate types that can be returned in a register are
2218 structs and unions. Arrays must be returned in memory. */
2219 code
= TYPE_CODE (type
);
2220 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2225 /* Assume all other aggregate types can be returned in a register.
2226 Run a check for structures, unions and arrays. */
2229 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2232 /* Need to check if this struct/union is "integer" like. For
2233 this to be true, its size must be less than or equal to
2234 INT_REGISTER_SIZE and the offset of each addressable
2235 subfield must be zero. Note that bit fields are not
2236 addressable, and unions always start at offset zero. If any
2237 of the subfields is a floating point type, the struct/union
2238 cannot be an integer type. */
2240 /* For each field in the object, check:
2241 1) Is it FP? --> yes, nRc = 1;
2242 2) Is it addressable (bitpos != 0) and
2243 not packed (bitsize == 0)?
2247 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2249 enum type_code field_type_code
;
2250 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, i
)));
2252 /* Is it a floating point type field? */
2253 if (field_type_code
== TYPE_CODE_FLT
)
2259 /* If bitpos != 0, then we have to care about it. */
2260 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2262 /* Bitfields are not addressable. If the field bitsize is
2263 zero, then the field is not packed. Hence it cannot be
2264 a bitfield or any other packed type. */
2265 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2277 /* Write into appropriate registers a function return value of type
2278 TYPE, given in virtual format. */
2281 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
2282 const gdb_byte
*valbuf
)
2284 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2286 char buf
[MAX_REGISTER_SIZE
];
2288 switch (gdbarch_tdep (get_regcache_arch (regs
))->fp_model
)
2292 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
);
2293 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
2296 case ARM_FLOAT_SOFT_FPA
:
2297 case ARM_FLOAT_SOFT_VFP
:
2298 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
2299 if (TYPE_LENGTH (type
) > 4)
2300 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
2301 valbuf
+ INT_REGISTER_SIZE
);
2306 (__FILE__
, __LINE__
,
2307 _("arm_store_return_value: Floating point model not supported"));
2311 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2312 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2313 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2314 || TYPE_CODE (type
) == TYPE_CODE_PTR
2315 || TYPE_CODE (type
) == TYPE_CODE_REF
2316 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2318 if (TYPE_LENGTH (type
) <= 4)
2320 /* Values of one word or less are zero/sign-extended and
2322 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2323 LONGEST val
= unpack_long (type
, valbuf
);
2325 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, val
);
2326 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
2330 /* Integral values greater than one word are stored in consecutive
2331 registers starting with r0. This will always be a multiple of
2332 the regiser size. */
2333 int len
= TYPE_LENGTH (type
);
2334 int regno
= ARM_A1_REGNUM
;
2338 regcache_cooked_write (regs
, regno
++, valbuf
);
2339 len
-= INT_REGISTER_SIZE
;
2340 valbuf
+= INT_REGISTER_SIZE
;
2346 /* For a structure or union the behaviour is as if the value had
2347 been stored to word-aligned memory and then loaded into
2348 registers with 32-bit load instruction(s). */
2349 int len
= TYPE_LENGTH (type
);
2350 int regno
= ARM_A1_REGNUM
;
2351 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2355 memcpy (tmpbuf
, valbuf
,
2356 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2357 regcache_cooked_write (regs
, regno
++, tmpbuf
);
2358 len
-= INT_REGISTER_SIZE
;
2359 valbuf
+= INT_REGISTER_SIZE
;
2365 /* Handle function return values. */
2367 static enum return_value_convention
2368 arm_return_value (struct gdbarch
*gdbarch
, struct type
*valtype
,
2369 struct regcache
*regcache
, gdb_byte
*readbuf
,
2370 const gdb_byte
*writebuf
)
2372 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2374 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2375 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2376 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2378 if (tdep
->struct_return
== pcc_struct_return
2379 || arm_return_in_memory (gdbarch
, valtype
))
2380 return RETURN_VALUE_STRUCT_CONVENTION
;
2384 arm_store_return_value (valtype
, regcache
, writebuf
);
2387 arm_extract_return_value (valtype
, regcache
, readbuf
);
2389 return RETURN_VALUE_REGISTER_CONVENTION
;
2394 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2397 char buf
[INT_REGISTER_SIZE
];
2398 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (frame
));
2400 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
2402 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2406 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
);
2410 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
2411 return the target PC. Otherwise return 0. */
2414 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
2418 CORE_ADDR start_addr
;
2420 /* Find the starting address and name of the function containing the PC. */
2421 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2424 /* If PC is in a Thumb call or return stub, return the address of the
2425 target PC, which is in a register. The thunk functions are called
2426 _call_via_xx, where x is the register name. The possible names
2427 are r0-r9, sl, fp, ip, sp, and lr. */
2428 if (strncmp (name
, "_call_via_", 10) == 0)
2430 /* Use the name suffix to determine which register contains the
2432 static char *table
[15] =
2433 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2434 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2437 int offset
= strlen (name
) - 2;
2439 for (regno
= 0; regno
<= 14; regno
++)
2440 if (strcmp (&name
[offset
], table
[regno
]) == 0)
2441 return get_frame_register_unsigned (frame
, regno
);
2444 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
2445 non-interworking calls to foo. We could decode the stubs
2446 to find the target but it's easier to use the symbol table. */
2447 namelen
= strlen (name
);
2448 if (name
[0] == '_' && name
[1] == '_'
2449 && ((namelen
> 2 + strlen ("_from_thumb")
2450 && strncmp (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb",
2451 strlen ("_from_thumb")) == 0)
2452 || (namelen
> 2 + strlen ("_from_arm")
2453 && strncmp (name
+ namelen
- strlen ("_from_arm"), "_from_arm",
2454 strlen ("_from_arm")) == 0)))
2457 int target_len
= namelen
- 2;
2458 struct minimal_symbol
*minsym
;
2459 struct objfile
*objfile
;
2460 struct obj_section
*sec
;
2462 if (name
[namelen
- 1] == 'b')
2463 target_len
-= strlen ("_from_thumb");
2465 target_len
-= strlen ("_from_arm");
2467 target_name
= alloca (target_len
+ 1);
2468 memcpy (target_name
, name
+ 2, target_len
);
2469 target_name
[target_len
] = '\0';
2471 sec
= find_pc_section (pc
);
2472 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
2473 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
2475 return SYMBOL_VALUE_ADDRESS (minsym
);
2480 return 0; /* not a stub */
2484 set_arm_command (char *args
, int from_tty
)
2486 printf_unfiltered (_("\
2487 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2488 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
2492 show_arm_command (char *args
, int from_tty
)
2494 cmd_show_list (showarmcmdlist
, from_tty
, "");
2498 arm_update_current_architecture (void)
2500 struct gdbarch_info info
;
2502 /* If the current architecture is not ARM, we have nothing to do. */
2503 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_arm
)
2506 /* Update the architecture. */
2507 gdbarch_info_init (&info
);
2509 if (!gdbarch_update_p (info
))
2510 internal_error (__FILE__
, __LINE__
, "could not update architecture");
2514 set_fp_model_sfunc (char *args
, int from_tty
,
2515 struct cmd_list_element
*c
)
2517 enum arm_float_model fp_model
;
2519 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
2520 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
2522 arm_fp_model
= fp_model
;
2526 if (fp_model
== ARM_FLOAT_LAST
)
2527 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
2530 arm_update_current_architecture ();
2534 show_fp_model (struct ui_file
*file
, int from_tty
,
2535 struct cmd_list_element
*c
, const char *value
)
2537 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2539 if (arm_fp_model
== ARM_FLOAT_AUTO
2540 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2541 fprintf_filtered (file
, _("\
2542 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2543 fp_model_strings
[tdep
->fp_model
]);
2545 fprintf_filtered (file
, _("\
2546 The current ARM floating point model is \"%s\".\n"),
2547 fp_model_strings
[arm_fp_model
]);
2551 arm_set_abi (char *args
, int from_tty
,
2552 struct cmd_list_element
*c
)
2554 enum arm_abi_kind arm_abi
;
2556 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
2557 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
2559 arm_abi_global
= arm_abi
;
2563 if (arm_abi
== ARM_ABI_LAST
)
2564 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
2567 arm_update_current_architecture ();
2571 arm_show_abi (struct ui_file
*file
, int from_tty
,
2572 struct cmd_list_element
*c
, const char *value
)
2574 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2576 if (arm_abi_global
== ARM_ABI_AUTO
2577 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2578 fprintf_filtered (file
, _("\
2579 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2580 arm_abi_strings
[tdep
->arm_abi
]);
2582 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
2586 /* If the user changes the register disassembly style used for info
2587 register and other commands, we have to also switch the style used
2588 in opcodes for disassembly output. This function is run in the "set
2589 arm disassembly" command, and does that. */
2592 set_disassembly_style_sfunc (char *args
, int from_tty
,
2593 struct cmd_list_element
*c
)
2595 set_disassembly_style ();
2598 /* Return the ARM register name corresponding to register I. */
2600 arm_register_name (struct gdbarch
*gdbarch
, int i
)
2602 if (i
>= ARRAY_SIZE (arm_register_names
))
2603 /* These registers are only supported on targets which supply
2604 an XML description. */
2607 return arm_register_names
[i
];
2611 set_disassembly_style (void)
2615 /* Find the style that the user wants. */
2616 for (current
= 0; current
< num_disassembly_options
; current
++)
2617 if (disassembly_style
== valid_disassembly_styles
[current
])
2619 gdb_assert (current
< num_disassembly_options
);
2621 /* Synchronize the disassembler. */
2622 set_arm_regname_option (current
);
2625 /* Test whether the coff symbol specific value corresponds to a Thumb
2629 coff_sym_is_thumb (int val
)
2631 return (val
== C_THUMBEXT
||
2632 val
== C_THUMBSTAT
||
2633 val
== C_THUMBEXTFUNC
||
2634 val
== C_THUMBSTATFUNC
||
2635 val
== C_THUMBLABEL
);
2638 /* arm_coff_make_msymbol_special()
2639 arm_elf_make_msymbol_special()
2641 These functions test whether the COFF or ELF symbol corresponds to
2642 an address in thumb code, and set a "special" bit in a minimal
2643 symbol to indicate that it does. */
2646 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2648 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2650 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2652 MSYMBOL_SET_SPECIAL (msym
);
2656 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2658 if (coff_sym_is_thumb (val
))
2659 MSYMBOL_SET_SPECIAL (msym
);
2663 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2665 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
2667 /* If necessary, set the T bit. */
2671 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
2672 if (arm_pc_is_thumb (pc
))
2673 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
, val
| 0x20);
2675 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
2676 val
& ~(ULONGEST
) 0x20);
2680 static struct value
*
2681 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
2683 const int *reg_p
= baton
;
2684 return value_of_register (*reg_p
, frame
);
2687 static enum gdb_osabi
2688 arm_elf_osabi_sniffer (bfd
*abfd
)
2690 unsigned int elfosabi
;
2691 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2693 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2695 if (elfosabi
== ELFOSABI_ARM
)
2696 /* GNU tools use this value. Check note sections in this case,
2698 bfd_map_over_sections (abfd
,
2699 generic_elf_osabi_sniff_abi_tag_sections
,
2702 /* Anything else will be handled by the generic ELF sniffer. */
2707 /* Initialize the current architecture based on INFO. If possible,
2708 re-use an architecture from ARCHES, which is a list of
2709 architectures already created during this debugging session.
2711 Called e.g. at program startup, when reading a core file, and when
2712 reading a binary file. */
2714 static struct gdbarch
*
2715 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2717 struct gdbarch_tdep
*tdep
;
2718 struct gdbarch
*gdbarch
;
2719 struct gdbarch_list
*best_arch
;
2720 enum arm_abi_kind arm_abi
= arm_abi_global
;
2721 enum arm_float_model fp_model
= arm_fp_model
;
2722 struct tdesc_arch_data
*tdesc_data
= NULL
;
2724 int have_fpa_registers
= 1;
2726 /* Check any target description for validity. */
2727 if (tdesc_has_registers (info
.target_desc
))
2729 /* For most registers we require GDB's default names; but also allow
2730 the numeric names for sp / lr / pc, as a convenience. */
2731 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
2732 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
2733 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
2735 const struct tdesc_feature
*feature
;
2738 feature
= tdesc_find_feature (info
.target_desc
,
2739 "org.gnu.gdb.arm.core");
2740 if (feature
== NULL
)
2743 tdesc_data
= tdesc_data_alloc ();
2746 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
2747 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
2748 arm_register_names
[i
]);
2749 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2752 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2755 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2758 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2759 ARM_PS_REGNUM
, "cpsr");
2763 tdesc_data_cleanup (tdesc_data
);
2767 feature
= tdesc_find_feature (info
.target_desc
,
2768 "org.gnu.gdb.arm.fpa");
2769 if (feature
!= NULL
)
2772 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
2773 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
2774 arm_register_names
[i
]);
2777 tdesc_data_cleanup (tdesc_data
);
2782 have_fpa_registers
= 0;
2784 feature
= tdesc_find_feature (info
.target_desc
,
2785 "org.gnu.gdb.xscale.iwmmxt");
2786 if (feature
!= NULL
)
2788 static const char *const iwmmxt_names
[] = {
2789 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
2790 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
2791 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
2792 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
2796 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
2798 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
2799 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
2801 /* Check for the control registers, but do not fail if they
2803 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
2804 tdesc_numbered_register (feature
, tdesc_data
, i
,
2805 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
2807 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
2809 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
2810 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
2814 tdesc_data_cleanup (tdesc_data
);
2820 /* If we have an object to base this architecture on, try to determine
2823 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
2825 int ei_osabi
, e_flags
;
2827 switch (bfd_get_flavour (info
.abfd
))
2829 case bfd_target_aout_flavour
:
2830 /* Assume it's an old APCS-style ABI. */
2831 arm_abi
= ARM_ABI_APCS
;
2834 case bfd_target_coff_flavour
:
2835 /* Assume it's an old APCS-style ABI. */
2837 arm_abi
= ARM_ABI_APCS
;
2840 case bfd_target_elf_flavour
:
2841 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
2842 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2844 if (ei_osabi
== ELFOSABI_ARM
)
2846 /* GNU tools used to use this value, but do not for EABI
2847 objects. There's nowhere to tag an EABI version
2848 anyway, so assume APCS. */
2849 arm_abi
= ARM_ABI_APCS
;
2851 else if (ei_osabi
== ELFOSABI_NONE
)
2853 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
2857 case EF_ARM_EABI_UNKNOWN
:
2858 /* Assume GNU tools. */
2859 arm_abi
= ARM_ABI_APCS
;
2862 case EF_ARM_EABI_VER4
:
2863 case EF_ARM_EABI_VER5
:
2864 arm_abi
= ARM_ABI_AAPCS
;
2865 /* EABI binaries default to VFP float ordering. */
2866 if (fp_model
== ARM_FLOAT_AUTO
)
2867 fp_model
= ARM_FLOAT_SOFT_VFP
;
2871 /* Leave it as "auto". */
2872 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
2877 if (fp_model
== ARM_FLOAT_AUTO
)
2879 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2881 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
2884 /* Leave it as "auto". Strictly speaking this case
2885 means FPA, but almost nobody uses that now, and
2886 many toolchains fail to set the appropriate bits
2887 for the floating-point model they use. */
2889 case EF_ARM_SOFT_FLOAT
:
2890 fp_model
= ARM_FLOAT_SOFT_FPA
;
2892 case EF_ARM_VFP_FLOAT
:
2893 fp_model
= ARM_FLOAT_VFP
;
2895 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
2896 fp_model
= ARM_FLOAT_SOFT_VFP
;
2903 /* Leave it as "auto". */
2908 /* If there is already a candidate, use it. */
2909 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
2911 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
2913 if (arm_abi
!= ARM_ABI_AUTO
2914 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
2917 if (fp_model
!= ARM_FLOAT_AUTO
2918 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
2921 /* Found a match. */
2925 if (best_arch
!= NULL
)
2927 if (tdesc_data
!= NULL
)
2928 tdesc_data_cleanup (tdesc_data
);
2929 return best_arch
->gdbarch
;
2932 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
2933 gdbarch
= gdbarch_alloc (&info
, tdep
);
2935 /* Record additional information about the architecture we are defining.
2936 These are gdbarch discriminators, like the OSABI. */
2937 tdep
->arm_abi
= arm_abi
;
2938 tdep
->fp_model
= fp_model
;
2939 tdep
->have_fpa_registers
= have_fpa_registers
;
2942 switch (info
.byte_order
)
2944 case BFD_ENDIAN_BIG
:
2945 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
2946 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
2947 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
2948 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
2952 case BFD_ENDIAN_LITTLE
:
2953 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
2954 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
2955 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
2956 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
2961 internal_error (__FILE__
, __LINE__
,
2962 _("arm_gdbarch_init: bad byte order for float format"));
2965 /* On ARM targets char defaults to unsigned. */
2966 set_gdbarch_char_signed (gdbarch
, 0);
2968 /* This should be low enough for everything. */
2969 tdep
->lowest_pc
= 0x20;
2970 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
2972 /* The default, for both APCS and AAPCS, is to return small
2973 structures in registers. */
2974 tdep
->struct_return
= reg_struct_return
;
2976 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
2977 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
2979 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
2981 /* Frame handling. */
2982 set_gdbarch_unwind_dummy_id (gdbarch
, arm_unwind_dummy_id
);
2983 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
2984 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
2986 frame_base_set_default (gdbarch
, &arm_normal_base
);
2988 /* Address manipulation. */
2989 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
2990 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
2992 /* Advance PC across function entry code. */
2993 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
2995 /* Skip trampolines. */
2996 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
2998 /* The stack grows downward. */
2999 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3001 /* Breakpoint manipulation. */
3002 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
3004 /* Information about registers, etc. */
3005 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
3006 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
3007 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
3008 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
3009 set_gdbarch_register_type (gdbarch
, arm_register_type
);
3011 /* This "info float" is FPA-specific. Use the generic version if we
3013 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
3014 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
3016 /* Internal <-> external register number maps. */
3017 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
3018 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
3019 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
3021 set_gdbarch_register_name (gdbarch
, arm_register_name
);
3023 /* Returning results. */
3024 set_gdbarch_return_value (gdbarch
, arm_return_value
);
3027 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
3029 /* Minsymbol frobbing. */
3030 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
3031 set_gdbarch_coff_make_msymbol_special (gdbarch
,
3032 arm_coff_make_msymbol_special
);
3034 /* Virtual tables. */
3035 set_gdbarch_vbit_in_delta (gdbarch
, 1);
3037 /* Hook in the ABI-specific overrides, if they have been registered. */
3038 gdbarch_init_osabi (info
, gdbarch
);
3040 /* Add some default predicates. */
3041 frame_unwind_append_sniffer (gdbarch
, arm_stub_unwind_sniffer
);
3042 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
3043 frame_unwind_append_sniffer (gdbarch
, arm_prologue_unwind_sniffer
);
3045 /* Now we have tuned the configuration, set a few final things,
3046 based on what the OS ABI has told us. */
3048 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
3049 binaries are always marked. */
3050 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
3051 tdep
->arm_abi
= ARM_ABI_APCS
;
3053 /* We used to default to FPA for generic ARM, but almost nobody
3054 uses that now, and we now provide a way for the user to force
3055 the model. So default to the most useful variant. */
3056 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
3057 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
3059 if (tdep
->jb_pc
>= 0)
3060 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
3062 /* Floating point sizes and format. */
3063 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
3064 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
3066 set_gdbarch_double_format
3067 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
3068 set_gdbarch_long_double_format
3069 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
3073 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
3074 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
3078 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
3080 /* Add standard register aliases. We add aliases even for those
3081 nanes which are used by the current architecture - it's simpler,
3082 and does no harm, since nothing ever lists user registers. */
3083 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
3084 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
3085 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
3091 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3093 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3098 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
3099 (unsigned long) tdep
->lowest_pc
);
3102 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
3105 _initialize_arm_tdep (void)
3107 struct ui_file
*stb
;
3109 struct cmd_list_element
*new_set
, *new_show
;
3110 const char *setname
;
3111 const char *setdesc
;
3112 const char *const *regnames
;
3114 static char *helptext
;
3115 char regdesc
[1024], *rdptr
= regdesc
;
3116 size_t rest
= sizeof (regdesc
);
3118 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
3120 /* Register an ELF OS ABI sniffer for ARM binaries. */
3121 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
3122 bfd_target_elf_flavour
,
3123 arm_elf_osabi_sniffer
);
3125 /* Get the number of possible sets of register names defined in opcodes. */
3126 num_disassembly_options
= get_arm_regname_num_options ();
3128 /* Add root prefix command for all "set arm"/"show arm" commands. */
3129 add_prefix_cmd ("arm", no_class
, set_arm_command
,
3130 _("Various ARM-specific commands."),
3131 &setarmcmdlist
, "set arm ", 0, &setlist
);
3133 add_prefix_cmd ("arm", no_class
, show_arm_command
,
3134 _("Various ARM-specific commands."),
3135 &showarmcmdlist
, "show arm ", 0, &showlist
);
3137 /* Sync the opcode insn printer with our register viewer. */
3138 parse_arm_disassembler_option ("reg-names-std");
3140 /* Initialize the array that will be passed to
3141 add_setshow_enum_cmd(). */
3142 valid_disassembly_styles
3143 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
3144 for (i
= 0; i
< num_disassembly_options
; i
++)
3146 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
3147 valid_disassembly_styles
[i
] = setname
;
3148 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
3151 /* When we find the default names, tell the disassembler to use
3153 if (!strcmp (setname
, "std"))
3155 disassembly_style
= setname
;
3156 set_arm_regname_option (i
);
3159 /* Mark the end of valid options. */
3160 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
3162 /* Create the help text. */
3163 stb
= mem_fileopen ();
3164 fprintf_unfiltered (stb
, "%s%s%s",
3165 _("The valid values are:\n"),
3167 _("The default is \"std\"."));
3168 helptext
= ui_file_xstrdup (stb
, &length
);
3169 ui_file_delete (stb
);
3171 add_setshow_enum_cmd("disassembler", no_class
,
3172 valid_disassembly_styles
, &disassembly_style
,
3173 _("Set the disassembly style."),
3174 _("Show the disassembly style."),
3176 set_disassembly_style_sfunc
,
3177 NULL
, /* FIXME: i18n: The disassembly style is \"%s\". */
3178 &setarmcmdlist
, &showarmcmdlist
);
3180 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
3181 _("Set usage of ARM 32-bit mode."),
3182 _("Show usage of ARM 32-bit mode."),
3183 _("When off, a 26-bit PC will be used."),
3185 NULL
, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
3186 &setarmcmdlist
, &showarmcmdlist
);
3188 /* Add a command to allow the user to force the FPU model. */
3189 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
3190 _("Set the floating point type."),
3191 _("Show the floating point type."),
3192 _("auto - Determine the FP typefrom the OS-ABI.\n\
3193 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
3194 fpa - FPA co-processor (GCC compiled).\n\
3195 softvfp - Software FP with pure-endian doubles.\n\
3196 vfp - VFP co-processor."),
3197 set_fp_model_sfunc
, show_fp_model
,
3198 &setarmcmdlist
, &showarmcmdlist
);
3200 /* Add a command to allow the user to force the ABI. */
3201 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
3204 NULL
, arm_set_abi
, arm_show_abi
,
3205 &setarmcmdlist
, &showarmcmdlist
);
3207 /* Debugging flag. */
3208 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
3209 _("Set ARM debugging."),
3210 _("Show ARM debugging."),
3211 _("When on, arm-specific debugging is enabled."),
3213 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
3214 &setdebuglist
, &showdebuglist
);