1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 #include <ctype.h> /* XXX for isupper () */
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register styles. */
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
42 #include "gdb/sim-arm.h"
45 #include "coff/internal.h"
48 #include "gdb_assert.h"
52 /* Each OS has a different mechanism for accessing the various
53 registers stored in the sigcontext structure.
55 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
56 function pointer) which may be used to determine the addresses
57 of the various saved registers in the sigcontext structure.
59 For the ARM target, there are three parameters to this function.
60 The first is the pc value of the frame under consideration, the
61 second the stack pointer of this frame, and the last is the
62 register number to fetch.
64 If the tm.h file does not define this macro, then it's assumed that
65 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
68 When it comes time to multi-arching this code, see the identically
69 named machinery in ia64-tdep.c for an example of how it could be
70 done. It should not be necessary to modify the code below where
71 this macro is used. */
73 #ifdef SIGCONTEXT_REGISTER_ADDRESS
74 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
75 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
78 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
79 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
82 /* Macros for setting and testing a bit in a minimal symbol that marks
83 it as Thumb function. The MSB of the minimal symbol's "info" field
84 is used for this purpose.
86 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
87 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
89 #define MSYMBOL_SET_SPECIAL(msym) \
90 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
93 #define MSYMBOL_IS_SPECIAL(msym) \
94 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
96 /* The list of available "set arm ..." and "show arm ..." commands. */
97 static struct cmd_list_element
*setarmcmdlist
= NULL
;
98 static struct cmd_list_element
*showarmcmdlist
= NULL
;
100 /* The type of floating-point to use. Keep this in sync with enum
101 arm_float_model, and the help string in _initialize_arm_tdep. */
102 static const char *fp_model_strings
[] =
111 /* A variable that can be configured by the user. */
112 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
113 static const char *current_fp_model
= "auto";
115 /* Number of different reg name sets (options). */
116 static int num_disassembly_options
;
118 /* We have more registers than the disassembler as gdb can print the value
119 of special registers as well.
120 The general register names are overwritten by whatever is being used by
121 the disassembler at the moment. We also adjust the case of cpsr and fps. */
123 /* Initial value: Register names used in ARM's ISA documentation. */
124 static char * arm_register_name_strings
[] =
125 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
126 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
127 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
128 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
129 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
130 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
131 "fps", "cpsr" }; /* 24 25 */
132 static char **arm_register_names
= arm_register_name_strings
;
134 /* Valid register name styles. */
135 static const char **valid_disassembly_styles
;
137 /* Disassembly style to use. Default to "std" register names. */
138 static const char *disassembly_style
;
139 /* Index to that option in the opcodes table. */
140 static int current_option
;
142 /* This is used to keep the bfd arch_info in sync with the disassembly
144 static void set_disassembly_style_sfunc(char *, int,
145 struct cmd_list_element
*);
146 static void set_disassembly_style (void);
148 static void convert_from_extended (const struct floatformat
*, const void *,
150 static void convert_to_extended (const struct floatformat
*, void *,
153 struct arm_prologue_cache
155 /* The stack pointer at the time this frame was created; i.e. the
156 caller's stack pointer when this function was called. It is used
157 to identify this frame. */
160 /* The frame base for this frame is just prev_sp + frame offset -
161 frame size. FRAMESIZE is the size of this stack frame, and
162 FRAMEOFFSET if the initial offset from the stack pointer (this
163 frame's stack pointer, not PREV_SP) to the frame base. */
168 /* The register used to hold the frame pointer for this frame. */
171 /* Saved register offsets. */
172 struct trad_frame_saved_reg
*saved_regs
;
175 /* Addresses for calling Thumb functions have the bit 0 set.
176 Here are some macros to test, set, or clear bit 0 of addresses. */
177 #define IS_THUMB_ADDR(addr) ((addr) & 1)
178 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
179 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
181 /* Set to true if the 32-bit mode is in use. */
185 /* Flag set by arm_fix_call_dummy that tells whether the target
186 function is a Thumb function. This flag is checked by
187 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
188 its use in valops.c) to pass the function address as an additional
191 static int target_is_thumb
;
193 /* Flag set by arm_fix_call_dummy that tells whether the calling
194 function is a Thumb function. This flag is checked by
195 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
197 static int caller_is_thumb
;
199 /* Determine if the program counter specified in MEMADDR is in a Thumb
203 arm_pc_is_thumb (CORE_ADDR memaddr
)
205 struct minimal_symbol
*sym
;
207 /* If bit 0 of the address is set, assume this is a Thumb address. */
208 if (IS_THUMB_ADDR (memaddr
))
211 /* Thumb functions have a "special" bit set in minimal symbols. */
212 sym
= lookup_minimal_symbol_by_pc (memaddr
);
215 return (MSYMBOL_IS_SPECIAL (sym
));
223 /* Determine if the program counter specified in MEMADDR is in a call
224 dummy being called from a Thumb function. */
227 arm_pc_is_thumb_dummy (CORE_ADDR memaddr
)
229 CORE_ADDR sp
= read_sp ();
231 /* FIXME: Until we switch for the new call dummy macros, this heuristic
232 is the best we can do. We are trying to determine if the pc is on
233 the stack, which (hopefully) will only happen in a call dummy.
234 We hope the current stack pointer is not so far alway from the dummy
235 frame location (true if we have not pushed large data structures or
236 gone too many levels deep) and that our 1024 is not enough to consider
237 code regions as part of the stack (true for most practical purposes). */
238 if (DEPRECATED_PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 1024))
239 return caller_is_thumb
;
244 /* Remove useless bits from addresses in a running program. */
246 arm_addr_bits_remove (CORE_ADDR val
)
249 return (val
& (arm_pc_is_thumb (val
) ? 0xfffffffe : 0xfffffffc));
251 return (val
& 0x03fffffc);
254 /* When reading symbols, we need to zap the low bit of the address,
255 which may be set to 1 for Thumb functions. */
257 arm_smash_text_address (CORE_ADDR val
)
262 /* Immediately after a function call, return the saved pc. Can't
263 always go through the frames for this because on some machines the
264 new frame is not set up until the new function executes some
268 arm_saved_pc_after_call (struct frame_info
*frame
)
270 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM
));
273 /* Determine whether the function invocation represented by FI has a
274 frame on the stack associated with it. If it does return zero,
275 otherwise return 1. */
278 arm_frameless_function_invocation (struct frame_info
*fi
)
280 CORE_ADDR func_start
, after_prologue
;
283 /* Sometimes we have functions that do a little setup (like saving the
284 vN registers with the stmdb instruction, but DO NOT set up a frame.
285 The symbol table will report this as a prologue. However, it is
286 important not to try to parse these partial frames as frames, or we
287 will get really confused.
289 So I will demand 3 instructions between the start & end of the
290 prologue before I call it a real prologue, i.e. at least
295 func_start
= (get_frame_func (fi
) + FUNCTION_START_OFFSET
);
296 after_prologue
= SKIP_PROLOGUE (func_start
);
298 /* There are some frameless functions whose first two instructions
299 follow the standard APCS form, in which case after_prologue will
300 be func_start + 8. */
302 frameless
= (after_prologue
< func_start
+ 12);
306 /* A typical Thumb prologue looks like this:
310 Sometimes the latter instruction may be replaced by:
318 or, on tpcs, like this:
325 There is always one instruction of three classes:
330 When we have found at least one of each class we are done with the prolog.
331 Note that the "sub sp, #NN" before the push does not count.
335 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
337 CORE_ADDR current_pc
;
339 bit 0 - push { rlist }
340 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
341 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
345 for (current_pc
= pc
;
346 current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40;
349 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
351 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
353 findmask
|= 1; /* push found */
355 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
358 if ((findmask
& 1) == 0) /* before push ? */
361 findmask
|= 4; /* add/sub sp found */
363 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
365 findmask
|= 2; /* setting of r7 found */
367 else if (insn
== 0x466f) /* mov r7, sp */
369 findmask
|= 2; /* setting of r7 found */
371 else if (findmask
== (4+2+1))
373 /* We have found one of each type of prologue instruction */
377 /* Something in the prolog that we don't care about or some
378 instruction from outside the prolog scheduled here for
386 /* Advance the PC across any function entry prologue instructions to
387 reach some "real" code.
389 The APCS (ARM Procedure Call Standard) defines the following
393 [stmfd sp!, {a1,a2,a3,a4}]
394 stmfd sp!, {...,fp,ip,lr,pc}
395 [stfe f7, [sp, #-12]!]
396 [stfe f6, [sp, #-12]!]
397 [stfe f5, [sp, #-12]!]
398 [stfe f4, [sp, #-12]!]
399 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
402 arm_skip_prologue (CORE_ADDR pc
)
406 CORE_ADDR func_addr
, func_end
= 0;
408 struct symtab_and_line sal
;
410 /* If we're in a dummy frame, don't even try to skip the prologue. */
411 if (DEPRECATED_PC_IN_CALL_DUMMY (pc
, 0, 0))
414 /* See what the symbol table says. */
416 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
420 /* Found a function. */
421 sym
= lookup_symbol (func_name
, NULL
, VAR_DOMAIN
, NULL
, NULL
);
422 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
424 /* Don't use this trick for assembly source files. */
425 sal
= find_pc_line (func_addr
, 0);
426 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
431 /* Check if this is Thumb code. */
432 if (arm_pc_is_thumb (pc
))
433 return thumb_skip_prologue (pc
, func_end
);
435 /* Can't find the prologue end in the symbol table, try it the hard way
436 by disassembling the instructions. */
438 /* Like arm_scan_prologue, stop no later than pc + 64. */
439 if (func_end
== 0 || func_end
> pc
+ 64)
442 for (skip_pc
= pc
; skip_pc
< func_end
; skip_pc
+= 4)
444 inst
= read_memory_integer (skip_pc
, 4);
446 /* "mov ip, sp" is no longer a required part of the prologue. */
447 if (inst
== 0xe1a0c00d) /* mov ip, sp */
450 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
453 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
456 /* Some prologues begin with "str lr, [sp, #-4]!". */
457 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
460 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
463 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
466 /* Any insns after this point may float into the code, if it makes
467 for better instruction scheduling, so we skip them only if we
468 find them, but still consider the function to be frame-ful. */
470 /* We may have either one sfmfd instruction here, or several stfe
471 insns, depending on the version of floating point code we
473 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
476 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
479 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
482 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
485 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
486 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
487 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
490 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
491 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
492 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
495 /* Un-recognized instruction; stop scanning. */
499 return skip_pc
; /* End of prologue */
503 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
504 This function decodes a Thumb function prologue to determine:
505 1) the size of the stack frame
506 2) which registers are saved on it
507 3) the offsets of saved regs
508 4) the offset from the stack pointer to the frame pointer
510 A typical Thumb function prologue would create this stack frame
511 (offsets relative to FP)
512 old SP -> 24 stack parameters
515 R7 -> 0 local variables (16 bytes)
516 SP -> -12 additional stack space (12 bytes)
517 The frame size would thus be 36 bytes, and the frame offset would be
518 12 bytes. The frame register is R7.
520 The comments for thumb_skip_prolog() describe the algorithm we use
521 to detect the end of the prolog. */
525 thumb_scan_prologue (CORE_ADDR prev_pc
, struct arm_prologue_cache
*cache
)
527 CORE_ADDR prologue_start
;
528 CORE_ADDR prologue_end
;
529 CORE_ADDR current_pc
;
530 /* Which register has been copied to register n? */
533 bit 0 - push { rlist }
534 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
535 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
540 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
542 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
544 if (sal
.line
== 0) /* no line info, use current PC */
545 prologue_end
= prev_pc
;
546 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
547 prologue_end
= sal
.end
; /* (probably means no prologue) */
550 /* We're in the boondocks: allow for
551 16 pushes, an add, and "mv fp,sp". */
552 prologue_end
= prologue_start
+ 40;
554 prologue_end
= min (prologue_end
, prev_pc
);
556 /* Initialize the saved register map. When register H is copied to
557 register L, we will put H in saved_reg[L]. */
558 for (i
= 0; i
< 16; i
++)
561 /* Search the prologue looking for instructions that set up the
562 frame pointer, adjust the stack pointer, and save registers.
563 Do this until all basic prolog instructions are found. */
565 cache
->framesize
= 0;
566 for (current_pc
= prologue_start
;
567 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
574 insn
= read_memory_unsigned_integer (current_pc
, 2);
576 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
579 findmask
|= 1; /* push found */
580 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
581 whether to save LR (R14). */
582 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
584 /* Calculate offsets of saved R0-R7 and LR. */
585 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
586 if (mask
& (1 << regno
))
588 cache
->framesize
+= 4;
589 cache
->saved_regs
[saved_reg
[regno
]].addr
= -cache
->framesize
;
590 /* Reset saved register map. */
591 saved_reg
[regno
] = regno
;
594 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
597 if ((findmask
& 1) == 0) /* before push? */
600 findmask
|= 4; /* add/sub sp found */
602 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
603 if (insn
& 0x80) /* is it signed? (==subtracting) */
605 cache
->frameoffset
+= offset
;
608 cache
->framesize
-= offset
;
610 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
612 findmask
|= 2; /* setting of r7 found */
613 cache
->framereg
= THUMB_FP_REGNUM
;
614 /* get scaled offset */
615 cache
->frameoffset
= (insn
& 0xff) << 2;
617 else if (insn
== 0x466f) /* mov r7, sp */
619 findmask
|= 2; /* setting of r7 found */
620 cache
->framereg
= THUMB_FP_REGNUM
;
621 cache
->frameoffset
= 0;
622 saved_reg
[THUMB_FP_REGNUM
] = ARM_SP_REGNUM
;
624 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
626 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
627 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
628 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
631 /* Something in the prolog that we don't care about or some
632 instruction from outside the prolog scheduled here for
638 /* This function decodes an ARM function prologue to determine:
639 1) the size of the stack frame
640 2) which registers are saved on it
641 3) the offsets of saved regs
642 4) the offset from the stack pointer to the frame pointer
643 This information is stored in the "extra" fields of the frame_info.
645 There are two basic forms for the ARM prologue. The fixed argument
646 function call will look like:
649 stmfd sp!, {fp, ip, lr, pc}
653 Which would create this stack frame (offsets relative to FP):
654 IP -> 4 (caller's stack)
655 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
656 -4 LR (return address in caller)
657 -8 IP (copy of caller's SP)
659 SP -> -28 Local variables
661 The frame size would thus be 32 bytes, and the frame offset would be
662 28 bytes. The stmfd call can also save any of the vN registers it
663 plans to use, which increases the frame size accordingly.
665 Note: The stored PC is 8 off of the STMFD instruction that stored it
666 because the ARM Store instructions always store PC + 8 when you read
669 A variable argument function call will look like:
672 stmfd sp!, {a1, a2, a3, a4}
673 stmfd sp!, {fp, ip, lr, pc}
676 Which would create this stack frame (offsets relative to FP):
677 IP -> 20 (caller's stack)
682 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
683 -4 LR (return address in caller)
684 -8 IP (copy of caller's SP)
686 SP -> -28 Local variables
688 The frame size would thus be 48 bytes, and the frame offset would be
691 There is another potential complication, which is that the optimizer
692 will try to separate the store of fp in the "stmfd" instruction from
693 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
694 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
696 Also, note, the original version of the ARM toolchain claimed that there
699 instruction at the end of the prologue. I have never seen GCC produce
700 this, and the ARM docs don't mention it. We still test for it below in
706 arm_scan_prologue (struct frame_info
*next_frame
, struct arm_prologue_cache
*cache
)
708 int regno
, sp_offset
, fp_offset
, ip_offset
;
709 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
710 CORE_ADDR prev_pc
= frame_pc_unwind (next_frame
);
712 /* Assume there is no frame until proven otherwise. */
713 cache
->framereg
= ARM_SP_REGNUM
;
714 cache
->framesize
= 0;
715 cache
->frameoffset
= 0;
717 /* Check for Thumb prologue. */
718 if (arm_pc_is_thumb (prev_pc
))
720 thumb_scan_prologue (prev_pc
, cache
);
724 /* Find the function prologue. If we can't find the function in
725 the symbol table, peek in the stack frame to find the PC. */
726 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
728 /* One way to find the end of the prologue (which works well
729 for unoptimized code) is to do the following:
731 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
734 prologue_end = prev_pc;
735 else if (sal.end < prologue_end)
736 prologue_end = sal.end;
738 This mechanism is very accurate so long as the optimizer
739 doesn't move any instructions from the function body into the
740 prologue. If this happens, sal.end will be the last
741 instruction in the first hunk of prologue code just before
742 the first instruction that the scheduler has moved from
743 the body to the prologue.
745 In order to make sure that we scan all of the prologue
746 instructions, we use a slightly less accurate mechanism which
747 may scan more than necessary. To help compensate for this
748 lack of accuracy, the prologue scanning loop below contains
749 several clauses which'll cause the loop to terminate early if
750 an implausible prologue instruction is encountered.
756 is a suitable endpoint since it accounts for the largest
757 possible prologue plus up to five instructions inserted by
760 if (prologue_end
> prologue_start
+ 64)
762 prologue_end
= prologue_start
+ 64; /* See above. */
767 /* We have no symbol information. Our only option is to assume this
768 function has a standard stack frame and the normal frame register.
769 Then, we can find the value of our frame pointer on entrance to
770 the callee (or at the present moment if this is the innermost frame).
771 The value stored there should be the address of the stmfd + 8. */
773 LONGEST return_value
;
775 frame_loc
= frame_unwind_register_unsigned (next_frame
, ARM_FP_REGNUM
);
776 if (!safe_read_memory_integer (frame_loc
, 4, &return_value
))
780 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
781 prologue_end
= prologue_start
+ 64; /* See above. */
785 if (prev_pc
< prologue_end
)
786 prologue_end
= prev_pc
;
788 /* Now search the prologue looking for instructions that set up the
789 frame pointer, adjust the stack pointer, and save registers.
791 Be careful, however, and if it doesn't look like a prologue,
792 don't try to scan it. If, for instance, a frameless function
793 begins with stmfd sp!, then we will tell ourselves there is
794 a frame, which will confuse stack traceback, as well as "finish"
795 and other operations that rely on a knowledge of the stack
798 In the APCS, the prologue should start with "mov ip, sp" so
799 if we don't see this as the first insn, we will stop.
801 [Note: This doesn't seem to be true any longer, so it's now an
802 optional part of the prologue. - Kevin Buettner, 2001-11-20]
804 [Note further: The "mov ip,sp" only seems to be missing in
805 frameless functions at optimization level "-O2" or above,
806 in which case it is often (but not always) replaced by
807 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
809 sp_offset
= fp_offset
= ip_offset
= 0;
811 for (current_pc
= prologue_start
;
812 current_pc
< prologue_end
;
815 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
817 if (insn
== 0xe1a0c00d) /* mov ip, sp */
822 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
824 unsigned imm
= insn
& 0xff; /* immediate value */
825 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
826 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
830 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
832 unsigned imm
= insn
& 0xff; /* immediate value */
833 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
834 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
838 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
841 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= sp_offset
;
844 else if ((insn
& 0xffff0000) == 0xe92d0000)
845 /* stmfd sp!, {..., fp, ip, lr, pc}
847 stmfd sp!, {a1, a2, a3, a4} */
849 int mask
= insn
& 0xffff;
851 /* Calculate offsets of saved registers. */
852 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
853 if (mask
& (1 << regno
))
856 cache
->saved_regs
[regno
].addr
= sp_offset
;
859 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
860 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
861 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
863 /* No need to add this to saved_regs -- it's just an arg reg. */
866 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
867 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
868 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
870 /* No need to add this to saved_regs -- it's just an arg reg. */
873 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
875 unsigned imm
= insn
& 0xff; /* immediate value */
876 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
877 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
878 fp_offset
= -imm
+ ip_offset
;
879 cache
->framereg
= ARM_FP_REGNUM
;
881 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
883 unsigned imm
= insn
& 0xff; /* immediate value */
884 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
885 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
888 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
891 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
892 cache
->saved_regs
[regno
].addr
= sp_offset
;
894 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
897 unsigned int fp_start_reg
, fp_bound_reg
;
899 if ((insn
& 0x800) == 0x800) /* N0 is set */
901 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
908 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
914 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
915 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
916 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
919 cache
->saved_regs
[fp_start_reg
++].addr
= sp_offset
;
922 else if ((insn
& 0xf0000000) != 0xe0000000)
923 break; /* Condition not true, exit early */
924 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
925 break; /* Don't scan past a block load */
927 /* The optimizer might shove anything into the prologue,
928 so we just skip what we don't recognize. */
932 /* The frame size is just the negative of the offset (from the
933 original SP) of the last thing thing we pushed on the stack.
934 The frame offset is [new FP] - [new SP]. */
935 cache
->framesize
= -sp_offset
;
936 if (cache
->framereg
== ARM_FP_REGNUM
)
937 cache
->frameoffset
= fp_offset
- sp_offset
;
939 cache
->frameoffset
= 0;
942 static struct arm_prologue_cache
*
943 arm_make_prologue_cache (struct frame_info
*next_frame
)
946 struct arm_prologue_cache
*cache
;
947 CORE_ADDR unwound_fp
;
949 cache
= frame_obstack_zalloc (sizeof (struct arm_prologue_cache
));
950 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
952 arm_scan_prologue (next_frame
, cache
);
954 unwound_fp
= frame_unwind_register_unsigned (next_frame
, cache
->framereg
);
958 cache
->prev_sp
= unwound_fp
+ cache
->framesize
- cache
->frameoffset
;
960 /* Calculate actual addresses of saved registers using offsets
961 determined by arm_scan_prologue. */
962 for (reg
= 0; reg
< NUM_REGS
; reg
++)
963 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
964 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
969 /* Our frame ID for a normal frame is the current function's starting PC
970 and the caller's SP when we were called. */
973 arm_prologue_this_id (struct frame_info
*next_frame
,
975 struct frame_id
*this_id
)
977 struct arm_prologue_cache
*cache
;
981 if (*this_cache
== NULL
)
982 *this_cache
= arm_make_prologue_cache (next_frame
);
985 func
= frame_func_unwind (next_frame
);
987 /* This is meant to halt the backtrace at "_start". Make sure we
988 don't halt it at a generic dummy frame. */
989 if (func
<= LOWEST_PC
)
992 /* If we've hit a wall, stop. */
993 if (cache
->prev_sp
== 0)
996 id
= frame_id_build (cache
->prev_sp
, func
);
998 /* Check that we're not going round in circles with the same frame
999 ID (but avoid applying the test to sentinel frames which do go
1000 round in circles). */
1001 if (frame_relative_level (next_frame
) >= 0
1002 && get_frame_type (next_frame
) == NORMAL_FRAME
1003 && frame_id_eq (get_frame_id (next_frame
), id
))
1010 arm_prologue_prev_register (struct frame_info
*next_frame
,
1014 enum lval_type
*lvalp
,
1019 struct arm_prologue_cache
*cache
;
1021 if (*this_cache
== NULL
)
1022 *this_cache
= arm_make_prologue_cache (next_frame
);
1023 cache
= *this_cache
;
1025 /* If we are asked to unwind the PC, then we need to return the LR
1026 instead. The saved value of PC points into this frame's
1027 prologue, not the next frame's resume location. */
1028 if (prev_regnum
== ARM_PC_REGNUM
)
1029 prev_regnum
= ARM_LR_REGNUM
;
1031 /* SP is generally not saved to the stack, but this frame is
1032 identified by NEXT_FRAME's stack pointer at the time of the call.
1033 The value was already reconstructed into PREV_SP. */
1034 if (prev_regnum
== ARM_SP_REGNUM
)
1038 store_unsigned_integer (valuep
, 4, cache
->prev_sp
);
1042 trad_frame_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
1043 optimized
, lvalp
, addrp
, realnump
, valuep
);
1046 struct frame_unwind arm_prologue_unwind
= {
1048 arm_prologue_this_id
,
1049 arm_prologue_prev_register
1052 static const struct frame_unwind
*
1053 arm_prologue_unwind_sniffer (struct frame_info
*next_frame
)
1055 return &arm_prologue_unwind
;
1059 arm_normal_frame_base (struct frame_info
*next_frame
, void **this_cache
)
1061 struct arm_prologue_cache
*cache
;
1063 if (*this_cache
== NULL
)
1064 *this_cache
= arm_make_prologue_cache (next_frame
);
1065 cache
= *this_cache
;
1067 return cache
->prev_sp
+ cache
->frameoffset
- cache
->framesize
;
1070 struct frame_base arm_normal_base
= {
1071 &arm_prologue_unwind
,
1072 arm_normal_frame_base
,
1073 arm_normal_frame_base
,
1074 arm_normal_frame_base
1077 static struct arm_prologue_cache
*
1078 arm_make_sigtramp_cache (struct frame_info
*next_frame
)
1080 struct arm_prologue_cache
*cache
;
1083 cache
= frame_obstack_zalloc (sizeof (struct arm_prologue_cache
));
1085 cache
->prev_sp
= frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
);
1087 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1089 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1090 cache
->saved_regs
[reg
].addr
1091 = SIGCONTEXT_REGISTER_ADDRESS (cache
->prev_sp
,
1092 frame_pc_unwind (next_frame
), reg
);
1094 /* FIXME: What about thumb mode? */
1095 cache
->framereg
= ARM_SP_REGNUM
;
1097 = read_memory_integer (cache
->saved_regs
[cache
->framereg
].addr
,
1098 DEPRECATED_REGISTER_RAW_SIZE (cache
->framereg
));
1104 arm_sigtramp_this_id (struct frame_info
*next_frame
,
1106 struct frame_id
*this_id
)
1108 struct arm_prologue_cache
*cache
;
1110 if (*this_cache
== NULL
)
1111 *this_cache
= arm_make_sigtramp_cache (next_frame
);
1112 cache
= *this_cache
;
1114 /* FIXME drow/2003-07-07: This isn't right if we single-step within
1115 the sigtramp frame; the PC should be the beginning of the trampoline. */
1116 *this_id
= frame_id_build (cache
->prev_sp
, frame_pc_unwind (next_frame
));
1120 arm_sigtramp_prev_register (struct frame_info
*next_frame
,
1124 enum lval_type
*lvalp
,
1129 struct arm_prologue_cache
*cache
;
1131 if (*this_cache
== NULL
)
1132 *this_cache
= arm_make_sigtramp_cache (next_frame
);
1133 cache
= *this_cache
;
1135 trad_frame_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
1136 optimized
, lvalp
, addrp
, realnump
, valuep
);
1139 struct frame_unwind arm_sigtramp_unwind
= {
1141 arm_sigtramp_this_id
,
1142 arm_sigtramp_prev_register
1145 static const struct frame_unwind
*
1146 arm_sigtramp_unwind_sniffer (struct frame_info
*next_frame
)
1148 /* Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare
1149 against the name of the function, the code below will have to be
1150 changed to first fetch the name of the function and then pass
1151 this name to PC_IN_SIGTRAMP. */
1153 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1154 && PC_IN_SIGTRAMP (frame_pc_unwind (next_frame
), (char *) 0))
1155 return &arm_sigtramp_unwind
;
1160 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1161 dummy frame. The frame ID's base needs to match the TOS value
1162 saved by save_dummy_frame_tos() and returned from
1163 arm_push_dummy_call, and the PC needs to match the dummy frame's
1166 static struct frame_id
1167 arm_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1169 return frame_id_build (frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
),
1170 frame_pc_unwind (next_frame
));
1173 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1174 be used to construct the previous frame's ID, after looking up the
1175 containing function). */
1178 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1181 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1182 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1186 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1188 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1191 /* DEPRECATED_CALL_DUMMY_WORDS:
1192 This sequence of words is the instructions
1198 Note this is 12 bytes. */
1200 static LONGEST arm_call_dummy_words
[] =
1202 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
1205 /* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy
1206 breakpoint to the proper address in the call dummy, so that
1207 `finish' after a stop in a call dummy works.
1209 FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an
1210 optimal solution, but the call to arm_fix_call_dummy is immediately
1211 followed by a call to call_function_by_hand, which is the only
1212 function where call_dummy_breakpoint_offset is actually used. */
1216 arm_set_call_dummy_breakpoint_offset (void)
1218 if (caller_is_thumb
)
1219 set_gdbarch_deprecated_call_dummy_breakpoint_offset (current_gdbarch
, 4);
1221 set_gdbarch_deprecated_call_dummy_breakpoint_offset (current_gdbarch
, 8);
1224 /* When arguments must be pushed onto the stack, they go on in reverse
1225 order. The code below implements a FILO (stack) to do this. */
1230 struct stack_item
*prev
;
1234 static struct stack_item
*
1235 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1237 struct stack_item
*si
;
1238 si
= xmalloc (sizeof (struct stack_item
));
1239 si
->data
= xmalloc (len
);
1242 memcpy (si
->data
, contents
, len
);
1246 static struct stack_item
*
1247 pop_stack_item (struct stack_item
*si
)
1249 struct stack_item
*dead
= si
;
1256 /* We currently only support passing parameters in integer registers. This
1257 conforms with GCC's default model. Several other variants exist and
1258 we should probably support some of them based on the selected ABI. */
1261 arm_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
1262 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1263 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1264 CORE_ADDR struct_addr
)
1269 struct stack_item
*si
= NULL
;
1271 /* Set the return address. For the ARM, the return breakpoint is
1272 always at BP_ADDR. */
1273 /* XXX Fix for Thumb. */
1274 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1276 /* Walk through the list of args and determine how large a temporary
1277 stack is required. Need to take care here as structs may be
1278 passed on the stack, and we have to to push them. */
1281 argreg
= ARM_A1_REGNUM
;
1284 /* Some platforms require a double-word aligned stack. Make sure sp
1285 is correctly aligned before we start. We always do this even if
1286 it isn't really needed -- it can never hurt things. */
1287 sp
&= ~(CORE_ADDR
)(2 * DEPRECATED_REGISTER_SIZE
- 1);
1289 /* The struct_return pointer occupies the first parameter
1290 passing register. */
1294 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = 0x%s\n",
1295 REGISTER_NAME (argreg
), paddr (struct_addr
));
1296 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1300 for (argnum
= 0; argnum
< nargs
; argnum
++)
1303 struct type
*arg_type
;
1304 struct type
*target_type
;
1305 enum type_code typecode
;
1308 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1309 len
= TYPE_LENGTH (arg_type
);
1310 target_type
= TYPE_TARGET_TYPE (arg_type
);
1311 typecode
= TYPE_CODE (arg_type
);
1312 val
= VALUE_CONTENTS (args
[argnum
]);
1314 /* If the argument is a pointer to a function, and it is a
1315 Thumb function, create a LOCAL copy of the value and set
1316 the THUMB bit in it. */
1317 if (TYPE_CODE_PTR
== typecode
1318 && target_type
!= NULL
1319 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1321 CORE_ADDR regval
= extract_unsigned_integer (val
, len
);
1322 if (arm_pc_is_thumb (regval
))
1325 store_unsigned_integer (val
, len
, MAKE_THUMB_ADDR (regval
));
1329 /* Copy the argument to general registers or the stack in
1330 register-sized pieces. Large arguments are split between
1331 registers and stack. */
1334 int partial_len
= len
< DEPRECATED_REGISTER_SIZE
? len
: DEPRECATED_REGISTER_SIZE
;
1336 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1338 /* The argument is being passed in a general purpose
1340 CORE_ADDR regval
= extract_unsigned_integer (val
, partial_len
);
1342 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1343 argnum
, REGISTER_NAME (argreg
),
1344 phex (regval
, DEPRECATED_REGISTER_SIZE
));
1345 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1350 /* Push the arguments onto the stack. */
1352 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1354 si
= push_stack_item (si
, val
, DEPRECATED_REGISTER_SIZE
);
1355 nstack
+= DEPRECATED_REGISTER_SIZE
;
1362 /* If we have an odd number of words to push, then decrement the stack
1363 by one word now, so first stack argument will be dword aligned. */
1370 write_memory (sp
, si
->data
, si
->len
);
1371 si
= pop_stack_item (si
);
1374 /* Finally, update teh SP register. */
1375 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1381 print_fpu_flags (int flags
)
1383 if (flags
& (1 << 0))
1384 fputs ("IVO ", stdout
);
1385 if (flags
& (1 << 1))
1386 fputs ("DVZ ", stdout
);
1387 if (flags
& (1 << 2))
1388 fputs ("OFL ", stdout
);
1389 if (flags
& (1 << 3))
1390 fputs ("UFL ", stdout
);
1391 if (flags
& (1 << 4))
1392 fputs ("INX ", stdout
);
1396 /* Print interesting information about the floating point processor
1397 (if present) or emulator. */
1399 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1400 struct frame_info
*frame
, const char *args
)
1402 unsigned long status
= read_register (ARM_FPS_REGNUM
);
1405 type
= (status
>> 24) & 127;
1406 printf ("%s FPU type %d\n",
1407 (status
& (1 << 31)) ? "Hardware" : "Software",
1409 fputs ("mask: ", stdout
);
1410 print_fpu_flags (status
>> 16);
1411 fputs ("flags: ", stdout
);
1412 print_fpu_flags (status
);
1415 /* Return the GDB type object for the "standard" data type of data in
1418 static struct type
*
1419 arm_register_type (int regnum
)
1421 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1423 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1424 return builtin_type_arm_ext_big
;
1426 return builtin_type_arm_ext_littlebyte_bigword
;
1429 return builtin_type_int32
;
1432 /* Index within `registers' of the first byte of the space for
1436 arm_register_byte (int regnum
)
1438 if (regnum
< ARM_F0_REGNUM
)
1439 return regnum
* INT_REGISTER_RAW_SIZE
;
1440 else if (regnum
< ARM_PS_REGNUM
)
1441 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1442 + (regnum
- ARM_F0_REGNUM
) * FP_REGISTER_RAW_SIZE
);
1444 return (NUM_GREGS
* INT_REGISTER_RAW_SIZE
1445 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
1446 + (regnum
- ARM_FPS_REGNUM
) * STATUS_REGISTER_SIZE
);
1449 /* Number of bytes of storage in the actual machine representation for
1450 register N. All registers are 4 bytes, except fp0 - fp7, which are
1451 12 bytes in length. */
1454 arm_register_raw_size (int regnum
)
1456 if (regnum
< ARM_F0_REGNUM
)
1457 return INT_REGISTER_RAW_SIZE
;
1458 else if (regnum
< ARM_FPS_REGNUM
)
1459 return FP_REGISTER_RAW_SIZE
;
1461 return STATUS_REGISTER_SIZE
;
1464 /* Number of bytes of storage in a program's representation
1467 arm_register_virtual_size (int regnum
)
1469 if (regnum
< ARM_F0_REGNUM
)
1470 return INT_REGISTER_VIRTUAL_SIZE
;
1471 else if (regnum
< ARM_FPS_REGNUM
)
1472 return FP_REGISTER_VIRTUAL_SIZE
;
1474 return STATUS_REGISTER_SIZE
;
1477 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1479 arm_register_sim_regno (int regnum
)
1482 gdb_assert (reg
>= 0 && reg
< NUM_REGS
);
1484 if (reg
< NUM_GREGS
)
1485 return SIM_ARM_R0_REGNUM
+ reg
;
1488 if (reg
< NUM_FREGS
)
1489 return SIM_ARM_FP0_REGNUM
+ reg
;
1492 if (reg
< NUM_SREGS
)
1493 return SIM_ARM_FPS_REGNUM
+ reg
;
1496 internal_error (__FILE__
, __LINE__
, "Bad REGNUM %d", regnum
);
1499 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1500 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1501 It is thought that this is is the floating-point register format on
1502 little-endian systems. */
1505 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
1509 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1510 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1512 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1514 floatformat_from_doublest (fmt
, &d
, dbl
);
1518 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
)
1521 floatformat_to_doublest (fmt
, ptr
, &d
);
1522 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1523 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1525 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1530 condition_true (unsigned long cond
, unsigned long status_reg
)
1532 if (cond
== INST_AL
|| cond
== INST_NV
)
1538 return ((status_reg
& FLAG_Z
) != 0);
1540 return ((status_reg
& FLAG_Z
) == 0);
1542 return ((status_reg
& FLAG_C
) != 0);
1544 return ((status_reg
& FLAG_C
) == 0);
1546 return ((status_reg
& FLAG_N
) != 0);
1548 return ((status_reg
& FLAG_N
) == 0);
1550 return ((status_reg
& FLAG_V
) != 0);
1552 return ((status_reg
& FLAG_V
) == 0);
1554 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1556 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1558 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1560 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1562 return (((status_reg
& FLAG_Z
) == 0) &&
1563 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1565 return (((status_reg
& FLAG_Z
) != 0) ||
1566 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1571 /* Support routines for single stepping. Calculate the next PC value. */
1572 #define submask(x) ((1L << ((x) + 1)) - 1)
1573 #define bit(obj,st) (((obj) >> (st)) & 1)
1574 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1575 #define sbits(obj,st,fn) \
1576 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1577 #define BranchDest(addr,instr) \
1578 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1581 static unsigned long
1582 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1583 unsigned long status_reg
)
1585 unsigned long res
, shift
;
1586 int rm
= bits (inst
, 0, 3);
1587 unsigned long shifttype
= bits (inst
, 5, 6);
1591 int rs
= bits (inst
, 8, 11);
1592 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1595 shift
= bits (inst
, 7, 11);
1598 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1599 + (bit (inst
, 4) ? 12 : 8))
1600 : read_register (rm
));
1605 res
= shift
>= 32 ? 0 : res
<< shift
;
1609 res
= shift
>= 32 ? 0 : res
>> shift
;
1615 res
= ((res
& 0x80000000L
)
1616 ? ~((~res
) >> shift
) : res
>> shift
);
1619 case 3: /* ROR/RRX */
1622 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1624 res
= (res
>> shift
) | (res
<< (32 - shift
));
1628 return res
& 0xffffffff;
1631 /* Return number of 1-bits in VAL. */
1634 bitcount (unsigned long val
)
1637 for (nbits
= 0; val
!= 0; nbits
++)
1638 val
&= val
- 1; /* delete rightmost 1-bit in val */
1643 thumb_get_next_pc (CORE_ADDR pc
)
1645 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1646 unsigned short inst1
= read_memory_integer (pc
, 2);
1647 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1648 unsigned long offset
;
1650 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1654 /* Fetch the saved PC from the stack. It's stored above
1655 all of the other registers. */
1656 offset
= bitcount (bits (inst1
, 0, 7)) * DEPRECATED_REGISTER_SIZE
;
1657 sp
= read_register (ARM_SP_REGNUM
);
1658 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1659 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1661 error ("Infinite loop detected");
1663 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1665 unsigned long status
= read_register (ARM_PS_REGNUM
);
1666 unsigned long cond
= bits (inst1
, 8, 11);
1667 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1668 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1670 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1672 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1674 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1676 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1677 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1678 nextpc
= pc_val
+ offset
;
1685 arm_get_next_pc (CORE_ADDR pc
)
1687 unsigned long pc_val
;
1688 unsigned long this_instr
;
1689 unsigned long status
;
1692 if (arm_pc_is_thumb (pc
))
1693 return thumb_get_next_pc (pc
);
1695 pc_val
= (unsigned long) pc
;
1696 this_instr
= read_memory_integer (pc
, 4);
1697 status
= read_register (ARM_PS_REGNUM
);
1698 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1700 if (condition_true (bits (this_instr
, 28, 31), status
))
1702 switch (bits (this_instr
, 24, 27))
1705 case 0x1: /* data processing */
1709 unsigned long operand1
, operand2
, result
= 0;
1713 if (bits (this_instr
, 12, 15) != 15)
1716 if (bits (this_instr
, 22, 25) == 0
1717 && bits (this_instr
, 4, 7) == 9) /* multiply */
1718 error ("Illegal update to pc in instruction");
1720 /* Multiply into PC */
1721 c
= (status
& FLAG_C
) ? 1 : 0;
1722 rn
= bits (this_instr
, 16, 19);
1723 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1725 if (bit (this_instr
, 25))
1727 unsigned long immval
= bits (this_instr
, 0, 7);
1728 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1729 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1732 else /* operand 2 is a shifted register */
1733 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1735 switch (bits (this_instr
, 21, 24))
1738 result
= operand1
& operand2
;
1742 result
= operand1
^ operand2
;
1746 result
= operand1
- operand2
;
1750 result
= operand2
- operand1
;
1754 result
= operand1
+ operand2
;
1758 result
= operand1
+ operand2
+ c
;
1762 result
= operand1
- operand2
+ c
;
1766 result
= operand2
- operand1
+ c
;
1772 case 0xb: /* tst, teq, cmp, cmn */
1773 result
= (unsigned long) nextpc
;
1777 result
= operand1
| operand2
;
1781 /* Always step into a function. */
1786 result
= operand1
& ~operand2
;
1793 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1796 error ("Infinite loop detected");
1801 case 0x5: /* data transfer */
1804 if (bit (this_instr
, 20))
1807 if (bits (this_instr
, 12, 15) == 15)
1813 if (bit (this_instr
, 22))
1814 error ("Illegal update to pc in instruction");
1816 /* byte write to PC */
1817 rn
= bits (this_instr
, 16, 19);
1818 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1819 if (bit (this_instr
, 24))
1822 int c
= (status
& FLAG_C
) ? 1 : 0;
1823 unsigned long offset
=
1824 (bit (this_instr
, 25)
1825 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1826 : bits (this_instr
, 0, 11));
1828 if (bit (this_instr
, 23))
1833 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1836 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1839 error ("Infinite loop detected");
1845 case 0x9: /* block transfer */
1846 if (bit (this_instr
, 20))
1849 if (bit (this_instr
, 15))
1854 if (bit (this_instr
, 23))
1857 unsigned long reglist
= bits (this_instr
, 0, 14);
1858 offset
= bitcount (reglist
) * 4;
1859 if (bit (this_instr
, 24)) /* pre */
1862 else if (bit (this_instr
, 24))
1866 unsigned long rn_val
=
1867 read_register (bits (this_instr
, 16, 19));
1869 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1873 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1875 error ("Infinite loop detected");
1880 case 0xb: /* branch & link */
1881 case 0xa: /* branch */
1883 nextpc
= BranchDest (pc
, this_instr
);
1885 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1887 error ("Infinite loop detected");
1893 case 0xe: /* coproc ops */
1898 fprintf_filtered (gdb_stderr
, "Bad bit-field extraction\n");
1906 /* single_step() is called just before we want to resume the inferior,
1907 if we want to single-step it but there is no hardware or kernel
1908 single-step support. We find the target of the coming instruction
1911 single_step() is also called just after the inferior stops. If we
1912 had set up a simulated single-step, we undo our damage. */
1915 arm_software_single_step (enum target_signal sig
, int insert_bpt
)
1917 static int next_pc
; /* State between setting and unsetting. */
1918 static char break_mem
[BREAKPOINT_MAX
]; /* Temporary storage for mem@bpt */
1922 next_pc
= arm_get_next_pc (read_register (ARM_PC_REGNUM
));
1923 target_insert_breakpoint (next_pc
, break_mem
);
1926 target_remove_breakpoint (next_pc
, break_mem
);
1929 #include "bfd-in2.h"
1930 #include "libcoff.h"
1933 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
1935 if (arm_pc_is_thumb (memaddr
))
1937 static asymbol
*asym
;
1938 static combined_entry_type ce
;
1939 static struct coff_symbol_struct csym
;
1940 static struct bfd fake_bfd
;
1941 static bfd_target fake_target
;
1943 if (csym
.native
== NULL
)
1945 /* Create a fake symbol vector containing a Thumb symbol.
1946 This is solely so that the code in print_insn_little_arm()
1947 and print_insn_big_arm() in opcodes/arm-dis.c will detect
1948 the presence of a Thumb symbol and switch to decoding
1949 Thumb instructions. */
1951 fake_target
.flavour
= bfd_target_coff_flavour
;
1952 fake_bfd
.xvec
= &fake_target
;
1953 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
1955 csym
.symbol
.the_bfd
= &fake_bfd
;
1956 csym
.symbol
.name
= "fake";
1957 asym
= (asymbol
*) & csym
;
1960 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
1961 info
->symbols
= &asym
;
1964 info
->symbols
= NULL
;
1966 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1967 return print_insn_big_arm (memaddr
, info
);
1969 return print_insn_little_arm (memaddr
, info
);
1972 /* The following define instruction sequences that will cause ARM
1973 cpu's to take an undefined instruction trap. These are used to
1974 signal a breakpoint to GDB.
1976 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
1977 modes. A different instruction is required for each mode. The ARM
1978 cpu's can also be big or little endian. Thus four different
1979 instructions are needed to support all cases.
1981 Note: ARMv4 defines several new instructions that will take the
1982 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
1983 not in fact add the new instructions. The new undefined
1984 instructions in ARMv4 are all instructions that had no defined
1985 behaviour in earlier chips. There is no guarantee that they will
1986 raise an exception, but may be treated as NOP's. In practice, it
1987 may only safe to rely on instructions matching:
1989 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1990 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1991 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
1993 Even this may only true if the condition predicate is true. The
1994 following use a condition predicate of ALWAYS so it is always TRUE.
1996 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
1997 and NetBSD all use a software interrupt rather than an undefined
1998 instruction to force a trap. This can be handled by by the
1999 abi-specific code during establishment of the gdbarch vector. */
2002 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
2003 override these definitions. */
2004 #ifndef ARM_LE_BREAKPOINT
2005 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2007 #ifndef ARM_BE_BREAKPOINT
2008 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2010 #ifndef THUMB_LE_BREAKPOINT
2011 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
2013 #ifndef THUMB_BE_BREAKPOINT
2014 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
2017 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
2018 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
2019 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2020 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2022 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2023 the program counter value to determine whether a 16-bit or 32-bit
2024 breakpoint should be used. It returns a pointer to a string of
2025 bytes that encode a breakpoint instruction, stores the length of
2026 the string to *lenptr, and adjusts the program counter (if
2027 necessary) to point to the actual memory location where the
2028 breakpoint should be inserted. */
2030 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
2031 breakpoints and storing their handles instread of what was in
2032 memory. It is nice that this is the same size as a handle -
2033 otherwise remote-rdp will have to change. */
2035 static const unsigned char *
2036 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
2038 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2040 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
2042 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2043 *lenptr
= tdep
->thumb_breakpoint_size
;
2044 return tdep
->thumb_breakpoint
;
2048 *lenptr
= tdep
->arm_breakpoint_size
;
2049 return tdep
->arm_breakpoint
;
2053 /* Extract from an array REGBUF containing the (raw) register state a
2054 function return value of type TYPE, and copy that, in virtual
2055 format, into VALBUF. */
2058 arm_extract_return_value (struct type
*type
,
2059 struct regcache
*regs
,
2062 bfd_byte
*valbuf
= dst
;
2064 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2066 switch (arm_get_fp_model (current_gdbarch
))
2070 /* The value is in register F0 in internal format. We need to
2071 extract the raw value and then convert it to the desired
2073 bfd_byte tmpbuf
[FP_REGISTER_RAW_SIZE
];
2075 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
2076 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
2081 case ARM_FLOAT_SOFT_FPA
:
2082 case ARM_FLOAT_SOFT_VFP
:
2083 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
2084 if (TYPE_LENGTH (type
) > 4)
2085 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
2086 valbuf
+ INT_REGISTER_RAW_SIZE
);
2091 (__FILE__
, __LINE__
,
2092 "arm_extract_return_value: Floating point model not supported");
2096 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2097 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2098 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2099 || TYPE_CODE (type
) == TYPE_CODE_PTR
2100 || TYPE_CODE (type
) == TYPE_CODE_REF
2101 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2103 /* If the the type is a plain integer, then the access is
2104 straight-forward. Otherwise we have to play around a bit more. */
2105 int len
= TYPE_LENGTH (type
);
2106 int regno
= ARM_A1_REGNUM
;
2111 /* By using store_unsigned_integer we avoid having to do
2112 anything special for small big-endian values. */
2113 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2114 store_unsigned_integer (valbuf
,
2115 (len
> INT_REGISTER_RAW_SIZE
2116 ? INT_REGISTER_RAW_SIZE
: len
),
2118 len
-= INT_REGISTER_RAW_SIZE
;
2119 valbuf
+= INT_REGISTER_RAW_SIZE
;
2124 /* For a structure or union the behaviour is as if the value had
2125 been stored to word-aligned memory and then loaded into
2126 registers with 32-bit load instruction(s). */
2127 int len
= TYPE_LENGTH (type
);
2128 int regno
= ARM_A1_REGNUM
;
2129 bfd_byte tmpbuf
[INT_REGISTER_RAW_SIZE
];
2133 regcache_cooked_read (regs
, regno
++, tmpbuf
);
2134 memcpy (valbuf
, tmpbuf
,
2135 len
> INT_REGISTER_RAW_SIZE
? INT_REGISTER_RAW_SIZE
: len
);
2136 len
-= INT_REGISTER_RAW_SIZE
;
2137 valbuf
+= INT_REGISTER_RAW_SIZE
;
2142 /* Extract from an array REGBUF containing the (raw) register state
2143 the address in which a function should return its structure value. */
2146 arm_extract_struct_value_address (struct regcache
*regcache
)
2150 regcache_cooked_read_unsigned (regcache
, ARM_A1_REGNUM
, &ret
);
2154 /* Will a function return an aggregate type in memory or in a
2155 register? Return 0 if an aggregate type can be returned in a
2156 register, 1 if it must be returned in memory. */
2159 arm_use_struct_convention (int gcc_p
, struct type
*type
)
2162 enum type_code code
;
2164 /* In the ARM ABI, "integer" like aggregate types are returned in
2165 registers. For an aggregate type to be integer like, its size
2166 must be less than or equal to DEPRECATED_REGISTER_SIZE and the
2167 offset of each addressable subfield must be zero. Note that bit
2168 fields are not addressable, and all addressable subfields of
2169 unions always start at offset zero.
2171 This function is based on the behaviour of GCC 2.95.1.
2172 See: gcc/arm.c: arm_return_in_memory() for details.
2174 Note: All versions of GCC before GCC 2.95.2 do not set up the
2175 parameters correctly for a function returning the following
2176 structure: struct { float f;}; This should be returned in memory,
2177 not a register. Richard Earnshaw sent me a patch, but I do not
2178 know of any way to detect if a function like the above has been
2179 compiled with the correct calling convention. */
2181 /* All aggregate types that won't fit in a register must be returned
2183 if (TYPE_LENGTH (type
) > DEPRECATED_REGISTER_SIZE
)
2188 /* The only aggregate types that can be returned in a register are
2189 structs and unions. Arrays must be returned in memory. */
2190 code
= TYPE_CODE (type
);
2191 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2196 /* Assume all other aggregate types can be returned in a register.
2197 Run a check for structures, unions and arrays. */
2200 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2203 /* Need to check if this struct/union is "integer" like. For
2204 this to be true, its size must be less than or equal to
2205 DEPRECATED_REGISTER_SIZE and the offset of each addressable
2206 subfield must be zero. Note that bit fields are not
2207 addressable, and unions always start at offset zero. If any
2208 of the subfields is a floating point type, the struct/union
2209 cannot be an integer type. */
2211 /* For each field in the object, check:
2212 1) Is it FP? --> yes, nRc = 1;
2213 2) Is it addressable (bitpos != 0) and
2214 not packed (bitsize == 0)?
2218 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2220 enum type_code field_type_code
;
2221 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
2223 /* Is it a floating point type field? */
2224 if (field_type_code
== TYPE_CODE_FLT
)
2230 /* If bitpos != 0, then we have to care about it. */
2231 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2233 /* Bitfields are not addressable. If the field bitsize is
2234 zero, then the field is not packed. Hence it cannot be
2235 a bitfield or any other packed type. */
2236 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2248 /* Write into appropriate registers a function return value of type
2249 TYPE, given in virtual format. */
2252 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
2255 const bfd_byte
*valbuf
= src
;
2257 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2259 char buf
[ARM_MAX_REGISTER_RAW_SIZE
];
2261 switch (arm_get_fp_model (current_gdbarch
))
2265 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
);
2266 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
2269 case ARM_FLOAT_SOFT_FPA
:
2270 case ARM_FLOAT_SOFT_VFP
:
2271 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
2272 if (TYPE_LENGTH (type
) > 4)
2273 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
2274 valbuf
+ INT_REGISTER_RAW_SIZE
);
2279 (__FILE__
, __LINE__
,
2280 "arm_store_return_value: Floating point model not supported");
2284 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2285 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2286 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2287 || TYPE_CODE (type
) == TYPE_CODE_PTR
2288 || TYPE_CODE (type
) == TYPE_CODE_REF
2289 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2291 if (TYPE_LENGTH (type
) <= 4)
2293 /* Values of one word or less are zero/sign-extended and
2295 bfd_byte tmpbuf
[INT_REGISTER_RAW_SIZE
];
2296 LONGEST val
= unpack_long (type
, valbuf
);
2298 store_signed_integer (tmpbuf
, INT_REGISTER_RAW_SIZE
, val
);
2299 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
2303 /* Integral values greater than one word are stored in consecutive
2304 registers starting with r0. This will always be a multiple of
2305 the regiser size. */
2306 int len
= TYPE_LENGTH (type
);
2307 int regno
= ARM_A1_REGNUM
;
2311 regcache_cooked_write (regs
, regno
++, valbuf
);
2312 len
-= INT_REGISTER_RAW_SIZE
;
2313 valbuf
+= INT_REGISTER_RAW_SIZE
;
2319 /* For a structure or union the behaviour is as if the value had
2320 been stored to word-aligned memory and then loaded into
2321 registers with 32-bit load instruction(s). */
2322 int len
= TYPE_LENGTH (type
);
2323 int regno
= ARM_A1_REGNUM
;
2324 bfd_byte tmpbuf
[INT_REGISTER_RAW_SIZE
];
2328 memcpy (tmpbuf
, valbuf
,
2329 len
> INT_REGISTER_RAW_SIZE
? INT_REGISTER_RAW_SIZE
: len
);
2330 regcache_cooked_write (regs
, regno
++, tmpbuf
);
2331 len
-= INT_REGISTER_RAW_SIZE
;
2332 valbuf
+= INT_REGISTER_RAW_SIZE
;
2338 arm_get_longjmp_target (CORE_ADDR
*pc
)
2341 char buf
[INT_REGISTER_RAW_SIZE
];
2342 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2344 jb_addr
= read_register (ARM_A1_REGNUM
);
2346 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2347 INT_REGISTER_RAW_SIZE
))
2350 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_RAW_SIZE
);
2354 /* Return non-zero if the PC is inside a thumb call thunk. */
2357 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2359 CORE_ADDR start_addr
;
2361 /* Find the starting address of the function containing the PC. If
2362 the caller didn't give us a name, look it up at the same time. */
2363 if (0 == find_pc_partial_function (pc
, name
? NULL
: &name
,
2367 return strncmp (name
, "_call_via_r", 11) == 0;
2370 /* If PC is in a Thumb call or return stub, return the address of the
2371 target PC, which is in a register. The thunk functions are called
2372 _called_via_xx, where x is the register name. The possible names
2373 are r0-r9, sl, fp, ip, sp, and lr. */
2376 arm_skip_stub (CORE_ADDR pc
)
2379 CORE_ADDR start_addr
;
2381 /* Find the starting address and name of the function containing the PC. */
2382 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2385 /* Call thunks always start with "_call_via_". */
2386 if (strncmp (name
, "_call_via_", 10) == 0)
2388 /* Use the name suffix to determine which register contains the
2390 static char *table
[15] =
2391 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2392 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2396 for (regno
= 0; regno
<= 14; regno
++)
2397 if (strcmp (&name
[10], table
[regno
]) == 0)
2398 return read_register (regno
);
2401 return 0; /* not a stub */
2405 set_arm_command (char *args
, int from_tty
)
2407 printf_unfiltered ("\"set arm\" must be followed by an apporpriate subcommand.\n");
2408 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
2412 show_arm_command (char *args
, int from_tty
)
2414 cmd_show_list (showarmcmdlist
, from_tty
, "");
2417 enum arm_float_model
2418 arm_get_fp_model (struct gdbarch
*gdbarch
)
2420 if (arm_fp_model
== ARM_FLOAT_AUTO
)
2421 return gdbarch_tdep (gdbarch
)->fp_model
;
2423 return arm_fp_model
;
2427 arm_set_fp (struct gdbarch
*gdbarch
)
2429 enum arm_float_model fp_model
= arm_get_fp_model (gdbarch
);
2431 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
2432 && (fp_model
== ARM_FLOAT_SOFT_FPA
|| fp_model
== ARM_FLOAT_FPA
))
2434 set_gdbarch_double_format (gdbarch
,
2435 &floatformat_ieee_double_littlebyte_bigword
);
2436 set_gdbarch_long_double_format
2437 (gdbarch
, &floatformat_ieee_double_littlebyte_bigword
);
2441 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_little
);
2442 set_gdbarch_long_double_format (gdbarch
,
2443 &floatformat_ieee_double_little
);
2448 set_fp_model_sfunc (char *args
, int from_tty
,
2449 struct cmd_list_element
*c
)
2451 enum arm_float_model fp_model
;
2453 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
2454 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
2456 arm_fp_model
= fp_model
;
2460 if (fp_model
== ARM_FLOAT_LAST
)
2461 internal_error (__FILE__
, __LINE__
, "Invalid fp model accepted: %s.",
2464 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2465 arm_set_fp (current_gdbarch
);
2469 show_fp_model (char *args
, int from_tty
,
2470 struct cmd_list_element
*c
)
2472 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2474 if (arm_fp_model
== ARM_FLOAT_AUTO
2475 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2476 printf_filtered (" - the default for the current ABI is \"%s\".\n",
2477 fp_model_strings
[tdep
->fp_model
]);
2480 /* If the user changes the register disassembly style used for info
2481 register and other commands, we have to also switch the style used
2482 in opcodes for disassembly output. This function is run in the "set
2483 arm disassembly" command, and does that. */
2486 set_disassembly_style_sfunc (char *args
, int from_tty
,
2487 struct cmd_list_element
*c
)
2489 set_disassembly_style ();
2492 /* Return the ARM register name corresponding to register I. */
2494 arm_register_name (int i
)
2496 return arm_register_names
[i
];
2500 set_disassembly_style (void)
2502 const char *setname
, *setdesc
, **regnames
;
2505 /* Find the style that the user wants in the opcodes table. */
2507 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2508 while ((disassembly_style
!= setname
)
2509 && (current
< num_disassembly_options
))
2510 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2511 current_option
= current
;
2513 /* Fill our copy. */
2514 for (j
= 0; j
< numregs
; j
++)
2515 arm_register_names
[j
] = (char *) regnames
[j
];
2518 if (isupper (*regnames
[ARM_PC_REGNUM
]))
2520 arm_register_names
[ARM_FPS_REGNUM
] = "FPS";
2521 arm_register_names
[ARM_PS_REGNUM
] = "CPSR";
2525 arm_register_names
[ARM_FPS_REGNUM
] = "fps";
2526 arm_register_names
[ARM_PS_REGNUM
] = "cpsr";
2529 /* Synchronize the disassembler. */
2530 set_arm_regname_option (current
);
2533 /* arm_othernames implements the "othernames" command. This is deprecated
2534 by the "set arm disassembly" command. */
2537 arm_othernames (char *names
, int n
)
2539 /* Circle through the various flavors. */
2540 current_option
= (current_option
+ 1) % num_disassembly_options
;
2542 disassembly_style
= valid_disassembly_styles
[current_option
];
2543 set_disassembly_style ();
2546 /* Test whether the coff symbol specific value corresponds to a Thumb
2550 coff_sym_is_thumb (int val
)
2552 return (val
== C_THUMBEXT
||
2553 val
== C_THUMBSTAT
||
2554 val
== C_THUMBEXTFUNC
||
2555 val
== C_THUMBSTATFUNC
||
2556 val
== C_THUMBLABEL
);
2559 /* arm_coff_make_msymbol_special()
2560 arm_elf_make_msymbol_special()
2562 These functions test whether the COFF or ELF symbol corresponds to
2563 an address in thumb code, and set a "special" bit in a minimal
2564 symbol to indicate that it does. */
2567 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2569 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2571 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2573 MSYMBOL_SET_SPECIAL (msym
);
2577 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2579 if (coff_sym_is_thumb (val
))
2580 MSYMBOL_SET_SPECIAL (msym
);
2584 arm_write_pc (CORE_ADDR pc
, ptid_t ptid
)
2586 write_register_pid (ARM_PC_REGNUM
, pc
, ptid
);
2588 /* If necessary, set the T bit. */
2591 CORE_ADDR val
= read_register_pid (ARM_PS_REGNUM
, ptid
);
2592 if (arm_pc_is_thumb (pc
))
2593 write_register_pid (ARM_PS_REGNUM
, val
| 0x20, ptid
);
2595 write_register_pid (ARM_PS_REGNUM
, val
& ~(CORE_ADDR
) 0x20, ptid
);
2599 static enum gdb_osabi
2600 arm_elf_osabi_sniffer (bfd
*abfd
)
2602 unsigned int elfosabi
, eflags
;
2603 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2605 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2610 /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the
2611 file are conforming to the base specification for that machine
2612 (there are no OS-specific extensions). In order to determine the
2613 real OS in use we must look for OS notes that have been added. */
2614 bfd_map_over_sections (abfd
,
2615 generic_elf_osabi_sniff_abi_tag_sections
,
2617 if (osabi
== GDB_OSABI_UNKNOWN
)
2619 /* Existing ARM tools don't set this field, so look at the EI_FLAGS
2620 field for more information. */
2621 eflags
= EF_ARM_EABI_VERSION(elf_elfheader(abfd
)->e_flags
);
2624 case EF_ARM_EABI_VER1
:
2625 osabi
= GDB_OSABI_ARM_EABI_V1
;
2628 case EF_ARM_EABI_VER2
:
2629 osabi
= GDB_OSABI_ARM_EABI_V2
;
2632 case EF_ARM_EABI_UNKNOWN
:
2633 /* Assume GNU tools. */
2634 osabi
= GDB_OSABI_ARM_APCS
;
2638 internal_error (__FILE__
, __LINE__
,
2639 "arm_elf_osabi_sniffer: Unknown ARM EABI "
2640 "version 0x%x", eflags
);
2646 /* GNU tools use this value. Check note sections in this case,
2648 bfd_map_over_sections (abfd
,
2649 generic_elf_osabi_sniff_abi_tag_sections
,
2651 if (osabi
== GDB_OSABI_UNKNOWN
)
2653 /* Assume APCS ABI. */
2654 osabi
= GDB_OSABI_ARM_APCS
;
2658 case ELFOSABI_FREEBSD
:
2659 osabi
= GDB_OSABI_FREEBSD_ELF
;
2662 case ELFOSABI_NETBSD
:
2663 osabi
= GDB_OSABI_NETBSD_ELF
;
2666 case ELFOSABI_LINUX
:
2667 osabi
= GDB_OSABI_LINUX
;
2675 /* Initialize the current architecture based on INFO. If possible,
2676 re-use an architecture from ARCHES, which is a list of
2677 architectures already created during this debugging session.
2679 Called e.g. at program startup, when reading a core file, and when
2680 reading a binary file. */
2682 static struct gdbarch
*
2683 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2685 struct gdbarch_tdep
*tdep
;
2686 struct gdbarch
*gdbarch
;
2688 /* Try to deterimine the ABI of the object we are loading. */
2690 if (info
.abfd
!= NULL
&& info
.osabi
== GDB_OSABI_UNKNOWN
)
2692 switch (bfd_get_flavour (info
.abfd
))
2694 case bfd_target_aout_flavour
:
2695 /* Assume it's an old APCS-style ABI. */
2696 info
.osabi
= GDB_OSABI_ARM_APCS
;
2699 case bfd_target_coff_flavour
:
2700 /* Assume it's an old APCS-style ABI. */
2702 info
.osabi
= GDB_OSABI_ARM_APCS
;
2706 /* Leave it as "unknown". */
2711 /* If there is already a candidate, use it. */
2712 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2714 return arches
->gdbarch
;
2716 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
2717 gdbarch
= gdbarch_alloc (&info
, tdep
);
2719 /* We used to default to FPA for generic ARM, but almost nobody uses that
2720 now, and we now provide a way for the user to force the model. So
2721 default to the most useful variant. */
2722 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
2725 switch (info
.byte_order
)
2727 case BFD_ENDIAN_BIG
:
2728 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
2729 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
2730 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
2731 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
2735 case BFD_ENDIAN_LITTLE
:
2736 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
2737 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
2738 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
2739 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
2744 internal_error (__FILE__
, __LINE__
,
2745 "arm_gdbarch_init: bad byte order for float format");
2748 /* On ARM targets char defaults to unsigned. */
2749 set_gdbarch_char_signed (gdbarch
, 0);
2751 /* This should be low enough for everything. */
2752 tdep
->lowest_pc
= 0x20;
2753 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
2755 set_gdbarch_deprecated_call_dummy_words (gdbarch
, arm_call_dummy_words
);
2756 set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch
, 0);
2758 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
2760 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
2762 /* Frame handling. */
2763 set_gdbarch_unwind_dummy_id (gdbarch
, arm_unwind_dummy_id
);
2764 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
2765 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
2767 set_gdbarch_frameless_function_invocation
2768 (gdbarch
, arm_frameless_function_invocation
);
2770 frame_base_set_default (gdbarch
, &arm_normal_base
);
2772 /* Address manipulation. */
2773 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
2774 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
2776 /* Advance PC across function entry code. */
2777 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
2779 /* Get the PC when a frame might not be available. */
2780 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
, arm_saved_pc_after_call
);
2782 /* The stack grows downward. */
2783 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2785 /* Breakpoint manipulation. */
2786 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
2788 /* Information about registers, etc. */
2789 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
2790 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
2791 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
2792 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
2793 set_gdbarch_deprecated_register_byte (gdbarch
, arm_register_byte
);
2794 set_gdbarch_deprecated_register_bytes (gdbarch
,
2795 (NUM_GREGS
* INT_REGISTER_RAW_SIZE
2796 + NUM_FREGS
* FP_REGISTER_RAW_SIZE
2797 + NUM_SREGS
* STATUS_REGISTER_SIZE
));
2798 set_gdbarch_num_regs (gdbarch
, NUM_GREGS
+ NUM_FREGS
+ NUM_SREGS
);
2799 set_gdbarch_deprecated_register_raw_size (gdbarch
, arm_register_raw_size
);
2800 set_gdbarch_deprecated_register_virtual_size (gdbarch
, arm_register_virtual_size
);
2801 set_gdbarch_deprecated_max_register_raw_size (gdbarch
, FP_REGISTER_RAW_SIZE
);
2802 set_gdbarch_deprecated_max_register_virtual_size (gdbarch
, FP_REGISTER_VIRTUAL_SIZE
);
2803 set_gdbarch_deprecated_register_virtual_type (gdbarch
, arm_register_type
);
2805 /* Internal <-> external register number maps. */
2806 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
2808 /* Integer registers are 4 bytes. */
2809 set_gdbarch_deprecated_register_size (gdbarch
, 4);
2810 set_gdbarch_register_name (gdbarch
, arm_register_name
);
2812 /* Returning results. */
2813 set_gdbarch_extract_return_value (gdbarch
, arm_extract_return_value
);
2814 set_gdbarch_store_return_value (gdbarch
, arm_store_return_value
);
2815 set_gdbarch_use_struct_convention (gdbarch
, arm_use_struct_convention
);
2816 set_gdbarch_deprecated_extract_struct_value_address (gdbarch
, arm_extract_struct_value_address
);
2818 /* Single stepping. */
2819 /* XXX For an RDI target we should ask the target if it can single-step. */
2820 set_gdbarch_software_single_step (gdbarch
, arm_software_single_step
);
2823 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
2825 /* Minsymbol frobbing. */
2826 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
2827 set_gdbarch_coff_make_msymbol_special (gdbarch
,
2828 arm_coff_make_msymbol_special
);
2830 /* Hook in the ABI-specific overrides, if they have been registered. */
2831 gdbarch_init_osabi (info
, gdbarch
);
2833 /* Add some default predicates. */
2834 frame_unwind_append_sniffer (gdbarch
, arm_sigtramp_unwind_sniffer
);
2835 frame_unwind_append_sniffer (gdbarch
, arm_prologue_unwind_sniffer
);
2837 /* Now we have tuned the configuration, set a few final things,
2838 based on what the OS ABI has told us. */
2840 if (tdep
->jb_pc
>= 0)
2841 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
2843 /* Floating point sizes and format. */
2844 switch (info
.byte_order
)
2846 case BFD_ENDIAN_BIG
:
2847 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
2848 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_big
);
2849 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
2853 case BFD_ENDIAN_LITTLE
:
2854 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
2855 arm_set_fp (gdbarch
);
2859 internal_error (__FILE__
, __LINE__
,
2860 "arm_gdbarch_init: bad byte order for float format");
2867 arm_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
2869 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2874 fprintf_unfiltered (file
, "arm_dump_tdep: Lowest pc = 0x%lx",
2875 (unsigned long) tdep
->lowest_pc
);
2879 arm_init_abi_eabi_v1 (struct gdbarch_info info
,
2880 struct gdbarch
*gdbarch
)
2886 arm_init_abi_eabi_v2 (struct gdbarch_info info
,
2887 struct gdbarch
*gdbarch
)
2893 arm_init_abi_apcs (struct gdbarch_info info
,
2894 struct gdbarch
*gdbarch
)
2899 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
2902 _initialize_arm_tdep (void)
2904 struct ui_file
*stb
;
2906 struct cmd_list_element
*new_set
, *new_show
;
2907 const char *setname
;
2908 const char *setdesc
;
2909 const char **regnames
;
2911 static char *helptext
;
2913 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
2915 /* Register an ELF OS ABI sniffer for ARM binaries. */
2916 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
2917 bfd_target_elf_flavour
,
2918 arm_elf_osabi_sniffer
);
2920 /* Register some ABI variants for embedded systems. */
2921 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_EABI_V1
,
2922 arm_init_abi_eabi_v1
);
2923 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_EABI_V2
,
2924 arm_init_abi_eabi_v2
);
2925 gdbarch_register_osabi (bfd_arch_arm
, 0, GDB_OSABI_ARM_APCS
,
2928 /* Get the number of possible sets of register names defined in opcodes. */
2929 num_disassembly_options
= get_arm_regname_num_options ();
2931 /* Add root prefix command for all "set arm"/"show arm" commands. */
2932 add_prefix_cmd ("arm", no_class
, set_arm_command
,
2933 "Various ARM-specific commands.",
2934 &setarmcmdlist
, "set arm ", 0, &setlist
);
2936 add_prefix_cmd ("arm", no_class
, show_arm_command
,
2937 "Various ARM-specific commands.",
2938 &showarmcmdlist
, "show arm ", 0, &showlist
);
2940 /* Sync the opcode insn printer with our register viewer. */
2941 parse_arm_disassembler_option ("reg-names-std");
2943 /* Begin creating the help text. */
2944 stb
= mem_fileopen ();
2945 fprintf_unfiltered (stb
, "Set the disassembly style.\n"
2946 "The valid values are:\n");
2948 /* Initialize the array that will be passed to add_set_enum_cmd(). */
2949 valid_disassembly_styles
2950 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
2951 for (i
= 0; i
< num_disassembly_options
; i
++)
2953 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
2954 valid_disassembly_styles
[i
] = setname
;
2955 fprintf_unfiltered (stb
, "%s - %s\n", setname
,
2957 /* Copy the default names (if found) and synchronize disassembler. */
2958 if (!strcmp (setname
, "std"))
2960 disassembly_style
= setname
;
2962 for (j
= 0; j
< numregs
; j
++)
2963 arm_register_names
[j
] = (char *) regnames
[j
];
2964 set_arm_regname_option (i
);
2967 /* Mark the end of valid options. */
2968 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
2970 /* Finish the creation of the help text. */
2971 fprintf_unfiltered (stb
, "The default is \"std\".");
2972 helptext
= ui_file_xstrdup (stb
, &length
);
2973 ui_file_delete (stb
);
2975 /* Add the deprecated disassembly-flavor command. */
2976 new_set
= add_set_enum_cmd ("disassembly-flavor", no_class
,
2977 valid_disassembly_styles
,
2981 set_cmd_sfunc (new_set
, set_disassembly_style_sfunc
);
2982 deprecate_cmd (new_set
, "set arm disassembly");
2983 deprecate_cmd (add_show_from_set (new_set
, &showlist
),
2984 "show arm disassembly");
2986 /* And now add the new interface. */
2987 new_set
= add_set_enum_cmd ("disassembler", no_class
,
2988 valid_disassembly_styles
, &disassembly_style
,
2989 helptext
, &setarmcmdlist
);
2991 set_cmd_sfunc (new_set
, set_disassembly_style_sfunc
);
2992 add_show_from_set (new_set
, &showarmcmdlist
);
2994 add_setshow_cmd_full ("apcs32", no_class
,
2995 var_boolean
, (char *) &arm_apcs_32
,
2996 "Set usage of ARM 32-bit mode.",
2997 "Show usage of ARM 32-bit mode.",
2999 &setlist
, &showlist
, &new_set
, &new_show
);
3000 deprecate_cmd (new_set
, "set arm apcs32");
3001 deprecate_cmd (new_show
, "show arm apcs32");
3003 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
3004 "Set usage of ARM 32-bit mode. "
3005 "When off, a 26-bit PC will be used.",
3006 "Show usage of ARM 32-bit mode. "
3007 "When off, a 26-bit PC will be used.",
3009 &setarmcmdlist
, &showarmcmdlist
);
3011 /* Add a command to allow the user to force the FPU model. */
3012 new_set
= add_set_enum_cmd
3013 ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
3014 "Set the floating point type.\n"
3015 "auto - Determine the FP typefrom the OS-ABI.\n"
3016 "softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n"
3017 "fpa - FPA co-processor (GCC compiled).\n"
3018 "softvfp - Software FP with pure-endian doubles.\n"
3019 "vfp - VFP co-processor.",
3021 set_cmd_sfunc (new_set
, set_fp_model_sfunc
);
3022 set_cmd_sfunc (add_show_from_set (new_set
, &showarmcmdlist
), show_fp_model
);
3024 /* Add the deprecated "othernames" command. */
3025 deprecate_cmd (add_com ("othernames", class_obscure
, arm_othernames
,
3026 "Switch to the next set of register names."),
3027 "set arm disassembly");
3029 /* Debugging flag. */
3030 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
3031 "Set ARM debugging. "
3032 "When on, arm-specific debugging is enabled.",
3033 "Show ARM debugging. "
3034 "When on, arm-specific debugging is enabled.",
3036 &setdebuglist
, &showdebuglist
);