1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "coff/internal.h" /* Internal format of COFF symbols in BFD */
30 #include "dis-asm.h" /* For register flavors. */
31 #include <ctype.h> /* for isupper () */
35 #include "solib-svr4.h"
37 /* Each OS has a different mechanism for accessing the various
38 registers stored in the sigcontext structure.
40 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
41 function pointer) which may be used to determine the addresses
42 of the various saved registers in the sigcontext structure.
44 For the ARM target, there are three parameters to this function.
45 The first is the pc value of the frame under consideration, the
46 second the stack pointer of this frame, and the last is the
47 register number to fetch.
49 If the tm.h file does not define this macro, then it's assumed that
50 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
53 When it comes time to multi-arching this code, see the identically
54 named machinery in ia64-tdep.c for an example of how it could be
55 done. It should not be necessary to modify the code below where
56 this macro is used. */
58 #ifdef SIGCONTEXT_REGISTER_ADDRESS
59 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
60 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
63 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
64 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
67 extern void _initialize_arm_tdep (void);
69 /* Number of different reg name sets (options). */
70 static int num_flavor_options
;
72 /* We have more registers than the disassembler as gdb can print the value
73 of special registers as well.
74 The general register names are overwritten by whatever is being used by
75 the disassembler at the moment. We also adjust the case of cpsr and fps. */
77 /* Initial value: Register names used in ARM's ISA documentation. */
78 static char * arm_register_name_strings
[] =
79 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
80 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
81 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
82 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
83 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
84 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
85 "fps", "cpsr" }; /* 24 25 */
86 char **arm_register_names
= arm_register_name_strings
;
88 /* Valid register name flavors. */
89 static const char **valid_flavors
;
91 /* Disassembly flavor to use. Default to "std" register names. */
92 static const char *disassembly_flavor
;
93 static int current_option
; /* Index to that option in the opcodes table. */
95 /* This is used to keep the bfd arch_info in sync with the disassembly
97 static void set_disassembly_flavor_sfunc(char *, int,
98 struct cmd_list_element
*);
99 static void set_disassembly_flavor (void);
101 static void convert_from_extended (void *ptr
, void *dbl
);
103 /* Define other aspects of the stack frame. We keep the offsets of
104 all saved registers, 'cause we need 'em a lot! We also keep the
105 current size of the stack frame, and the offset of the frame
106 pointer from the stack pointer (for frameless functions, and when
107 we're still in the prologue of a function with a frame) */
109 struct frame_extra_info
111 struct frame_saved_regs fsr
;
117 /* Addresses for calling Thumb functions have the bit 0 set.
118 Here are some macros to test, set, or clear bit 0 of addresses. */
119 #define IS_THUMB_ADDR(addr) ((addr) & 1)
120 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
121 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
123 /* Will a function return an aggregate type in memory or in a
124 register? Return 0 if an aggregate type can be returned in a
125 register, 1 if it must be returned in memory. */
128 arm_use_struct_convention (int gcc_p
, struct type
*type
)
131 register enum type_code code
;
133 /* In the ARM ABI, "integer" like aggregate types are returned in
134 registers. For an aggregate type to be integer like, its size
135 must be less than or equal to REGISTER_SIZE and the offset of
136 each addressable subfield must be zero. Note that bit fields are
137 not addressable, and all addressable subfields of unions always
138 start at offset zero.
140 This function is based on the behaviour of GCC 2.95.1.
141 See: gcc/arm.c: arm_return_in_memory() for details.
143 Note: All versions of GCC before GCC 2.95.2 do not set up the
144 parameters correctly for a function returning the following
145 structure: struct { float f;}; This should be returned in memory,
146 not a register. Richard Earnshaw sent me a patch, but I do not
147 know of any way to detect if a function like the above has been
148 compiled with the correct calling convention. */
150 /* All aggregate types that won't fit in a register must be returned
152 if (TYPE_LENGTH (type
) > REGISTER_SIZE
)
157 /* The only aggregate types that can be returned in a register are
158 structs and unions. Arrays must be returned in memory. */
159 code
= TYPE_CODE (type
);
160 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
165 /* Assume all other aggregate types can be returned in a register.
166 Run a check for structures, unions and arrays. */
169 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
172 /* Need to check if this struct/union is "integer" like. For
173 this to be true, its size must be less than or equal to
174 REGISTER_SIZE and the offset of each addressable subfield
175 must be zero. Note that bit fields are not addressable, and
176 unions always start at offset zero. If any of the subfields
177 is a floating point type, the struct/union cannot be an
180 /* For each field in the object, check:
181 1) Is it FP? --> yes, nRc = 1;
182 2) Is it addressable (bitpos != 0) and
183 not packed (bitsize == 0)?
187 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
189 enum type_code field_type_code
;
190 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
192 /* Is it a floating point type field? */
193 if (field_type_code
== TYPE_CODE_FLT
)
199 /* If bitpos != 0, then we have to care about it. */
200 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
202 /* Bitfields are not addressable. If the field bitsize is
203 zero, then the field is not packed. Hence it cannot be
204 a bitfield or any other packed type. */
205 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
218 arm_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*thisframe
)
220 return (chain
!= 0 && (FRAME_SAVED_PC (thisframe
) >= LOWEST_PC
));
223 /* Set to true if the 32-bit mode is in use. */
227 /* Flag set by arm_fix_call_dummy that tells whether the target
228 function is a Thumb function. This flag is checked by
229 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
230 its use in valops.c) to pass the function address as an additional
233 static int target_is_thumb
;
235 /* Flag set by arm_fix_call_dummy that tells whether the calling
236 function is a Thumb function. This flag is checked by
237 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
239 static int caller_is_thumb
;
241 /* Determine if the program counter specified in MEMADDR is in a Thumb
245 arm_pc_is_thumb (CORE_ADDR memaddr
)
247 struct minimal_symbol
*sym
;
249 /* If bit 0 of the address is set, assume this is a Thumb address. */
250 if (IS_THUMB_ADDR (memaddr
))
253 /* Thumb functions have a "special" bit set in minimal symbols. */
254 sym
= lookup_minimal_symbol_by_pc (memaddr
);
257 return (MSYMBOL_IS_SPECIAL (sym
));
265 /* Determine if the program counter specified in MEMADDR is in a call
266 dummy being called from a Thumb function. */
269 arm_pc_is_thumb_dummy (CORE_ADDR memaddr
)
271 CORE_ADDR sp
= read_sp ();
273 /* FIXME: Until we switch for the new call dummy macros, this heuristic
274 is the best we can do. We are trying to determine if the pc is on
275 the stack, which (hopefully) will only happen in a call dummy.
276 We hope the current stack pointer is not so far alway from the dummy
277 frame location (true if we have not pushed large data structures or
278 gone too many levels deep) and that our 1024 is not enough to consider
279 code regions as part of the stack (true for most practical purposes) */
280 if (PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 1024))
281 return caller_is_thumb
;
287 arm_addr_bits_remove (CORE_ADDR val
)
289 if (arm_pc_is_thumb (val
))
290 return (val
& (arm_apcs_32
? 0xfffffffe : 0x03fffffe));
292 return (val
& (arm_apcs_32
? 0xfffffffc : 0x03fffffc));
296 arm_saved_pc_after_call (struct frame_info
*frame
)
298 return ADDR_BITS_REMOVE (read_register (LR_REGNUM
));
302 arm_frameless_function_invocation (struct frame_info
*fi
)
304 CORE_ADDR func_start
, after_prologue
;
307 func_start
= (get_pc_function_start ((fi
)->pc
) + FUNCTION_START_OFFSET
);
308 after_prologue
= SKIP_PROLOGUE (func_start
);
310 /* There are some frameless functions whose first two instructions
311 follow the standard APCS form, in which case after_prologue will
312 be func_start + 8. */
314 frameless
= (after_prologue
< func_start
+ 12);
318 /* A typical Thumb prologue looks like this:
322 Sometimes the latter instruction may be replaced by:
330 or, on tpcs, like this:
337 There is always one instruction of three classes:
342 When we have found at least one of each class we are done with the prolog.
343 Note that the "sub sp, #NN" before the push does not count.
347 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
349 CORE_ADDR current_pc
;
350 int findmask
= 0; /* findmask:
351 bit 0 - push { rlist }
352 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
353 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
356 for (current_pc
= pc
; current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40; current_pc
+= 2)
358 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
360 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
362 findmask
|= 1; /* push found */
364 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
366 if ((findmask
& 1) == 0) /* before push ? */
369 findmask
|= 4; /* add/sub sp found */
371 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
373 findmask
|= 2; /* setting of r7 found */
375 else if (insn
== 0x466f) /* mov r7, sp */
377 findmask
|= 2; /* setting of r7 found */
380 continue; /* something in the prolog that we don't care about or some
381 instruction from outside the prolog scheduled here for optimization */
387 /* The APCS (ARM Procedure Call Standard) defines the following
391 [stmfd sp!, {a1,a2,a3,a4}]
392 stmfd sp!, {...,fp,ip,lr,pc}
393 [stfe f7, [sp, #-12]!]
394 [stfe f6, [sp, #-12]!]
395 [stfe f5, [sp, #-12]!]
396 [stfe f4, [sp, #-12]!]
397 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
400 arm_skip_prologue (CORE_ADDR pc
)
404 CORE_ADDR func_addr
, func_end
;
405 struct symtab_and_line sal
;
407 /* See what the symbol table says. */
409 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
411 sal
= find_pc_line (func_addr
, 0);
412 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
416 /* Check if this is Thumb code. */
417 if (arm_pc_is_thumb (pc
))
418 return thumb_skip_prologue (pc
, func_end
);
420 /* Can't find the prologue end in the symbol table, try it the hard way
421 by disassembling the instructions. */
423 inst
= read_memory_integer (skip_pc
, 4);
424 if (inst
!= 0xe1a0c00d) /* mov ip, sp */
428 inst
= read_memory_integer (skip_pc
, 4);
429 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
432 inst
= read_memory_integer (skip_pc
, 4);
435 if ((inst
& 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */
439 inst
= read_memory_integer (skip_pc
, 4);
441 /* Any insns after this point may float into the code, if it makes
442 for better instruction scheduling, so we skip them only if we
443 find them, but still consdier the function to be frame-ful. */
445 /* We may have either one sfmfd instruction here, or several stfe
446 insns, depending on the version of floating point code we
448 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
451 inst
= read_memory_integer (skip_pc
, 4);
455 while ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
458 inst
= read_memory_integer (skip_pc
, 4);
462 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
468 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
469 This function decodes a Thumb function prologue to determine:
470 1) the size of the stack frame
471 2) which registers are saved on it
472 3) the offsets of saved regs
473 4) the offset from the stack pointer to the frame pointer
474 This information is stored in the "extra" fields of the frame_info.
476 A typical Thumb function prologue would create this stack frame
477 (offsets relative to FP)
478 old SP -> 24 stack parameters
481 R7 -> 0 local variables (16 bytes)
482 SP -> -12 additional stack space (12 bytes)
483 The frame size would thus be 36 bytes, and the frame offset would be
484 12 bytes. The frame register is R7.
486 The comments for thumb_skip_prolog() describe the algorithm we use to detect
487 the end of the prolog */
491 thumb_scan_prologue (struct frame_info
*fi
)
493 CORE_ADDR prologue_start
;
494 CORE_ADDR prologue_end
;
495 CORE_ADDR current_pc
;
496 int saved_reg
[16]; /* which register has been copied to register n? */
497 int findmask
= 0; /* findmask:
498 bit 0 - push { rlist }
499 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
500 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
504 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
506 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
508 if (sal
.line
== 0) /* no line info, use current PC */
509 prologue_end
= fi
->pc
;
510 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
511 prologue_end
= sal
.end
; /* (probably means no prologue) */
514 prologue_end
= prologue_start
+ 40; /* We're in the boondocks: allow for */
515 /* 16 pushes, an add, and "mv fp,sp" */
517 prologue_end
= min (prologue_end
, fi
->pc
);
519 /* Initialize the saved register map. When register H is copied to
520 register L, we will put H in saved_reg[L]. */
521 for (i
= 0; i
< 16; i
++)
524 /* Search the prologue looking for instructions that set up the
525 frame pointer, adjust the stack pointer, and save registers.
526 Do this until all basic prolog instructions are found. */
529 for (current_pc
= prologue_start
;
530 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
537 insn
= read_memory_unsigned_integer (current_pc
, 2);
539 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
542 findmask
|= 1; /* push found */
543 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
544 whether to save LR (R14). */
545 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
547 /* Calculate offsets of saved R0-R7 and LR. */
548 for (regno
= LR_REGNUM
; regno
>= 0; regno
--)
549 if (mask
& (1 << regno
))
552 fi
->fsr
.regs
[saved_reg
[regno
]] = -(fi
->framesize
);
553 saved_reg
[regno
] = regno
; /* reset saved register map */
556 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
558 if ((findmask
& 1) == 0) /* before push ? */
561 findmask
|= 4; /* add/sub sp found */
563 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
564 if (insn
& 0x80) /* is it signed? (==subtracting) */
566 fi
->frameoffset
+= offset
;
569 fi
->framesize
-= offset
;
571 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
573 findmask
|= 2; /* setting of r7 found */
574 fi
->framereg
= THUMB_FP_REGNUM
;
575 fi
->frameoffset
= (insn
& 0xff) << 2; /* get scaled offset */
577 else if (insn
== 0x466f) /* mov r7, sp */
579 findmask
|= 2; /* setting of r7 found */
580 fi
->framereg
= THUMB_FP_REGNUM
;
582 saved_reg
[THUMB_FP_REGNUM
] = SP_REGNUM
;
584 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
586 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
587 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
588 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
591 continue; /* something in the prolog that we don't care about or some
592 instruction from outside the prolog scheduled here for optimization */
596 /* Check if prologue for this frame's PC has already been scanned. If
597 it has, copy the relevant information about that prologue and
598 return non-zero. Otherwise do not copy anything and return zero.
600 The information saved in the cache includes:
601 * the frame register number;
602 * the size of the stack frame;
603 * the offsets of saved regs (relative to the old SP); and
604 * the offset from the stack pointer to the frame pointer
606 The cache contains only one entry, since this is adequate for the
607 typical sequence of prologue scan requests we get. When performing
608 a backtrace, GDB will usually ask to scan the same function twice
609 in a row (once to get the frame chain, and once to fill in the
610 extra frame information). */
612 static struct frame_info prologue_cache
;
615 check_prologue_cache (struct frame_info
*fi
)
619 if (fi
->pc
== prologue_cache
.pc
)
621 fi
->framereg
= prologue_cache
.framereg
;
622 fi
->framesize
= prologue_cache
.framesize
;
623 fi
->frameoffset
= prologue_cache
.frameoffset
;
624 for (i
= 0; i
< NUM_REGS
; i
++)
625 fi
->fsr
.regs
[i
] = prologue_cache
.fsr
.regs
[i
];
633 /* Copy the prologue information from fi to the prologue cache. */
636 save_prologue_cache (struct frame_info
*fi
)
640 prologue_cache
.pc
= fi
->pc
;
641 prologue_cache
.framereg
= fi
->framereg
;
642 prologue_cache
.framesize
= fi
->framesize
;
643 prologue_cache
.frameoffset
= fi
->frameoffset
;
645 for (i
= 0; i
< NUM_REGS
; i
++)
646 prologue_cache
.fsr
.regs
[i
] = fi
->fsr
.regs
[i
];
650 /* This function decodes an ARM function prologue to determine:
651 1) the size of the stack frame
652 2) which registers are saved on it
653 3) the offsets of saved regs
654 4) the offset from the stack pointer to the frame pointer
655 This information is stored in the "extra" fields of the frame_info.
657 There are two basic forms for the ARM prologue. The fixed argument
658 function call will look like:
661 stmfd sp!, {fp, ip, lr, pc}
665 Which would create this stack frame (offsets relative to FP):
666 IP -> 4 (caller's stack)
667 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
668 -4 LR (return address in caller)
669 -8 IP (copy of caller's SP)
671 SP -> -28 Local variables
673 The frame size would thus be 32 bytes, and the frame offset would be
674 28 bytes. The stmfd call can also save any of the vN registers it
675 plans to use, which increases the frame size accordingly.
677 Note: The stored PC is 8 off of the STMFD instruction that stored it
678 because the ARM Store instructions always store PC + 8 when you read
681 A variable argument function call will look like:
684 stmfd sp!, {a1, a2, a3, a4}
685 stmfd sp!, {fp, ip, lr, pc}
688 Which would create this stack frame (offsets relative to FP):
689 IP -> 20 (caller's stack)
694 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
695 -4 LR (return address in caller)
696 -8 IP (copy of caller's SP)
698 SP -> -28 Local variables
700 The frame size would thus be 48 bytes, and the frame offset would be
703 There is another potential complication, which is that the optimizer
704 will try to separate the store of fp in the "stmfd" instruction from
705 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
706 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
708 Also, note, the original version of the ARM toolchain claimed that there
711 instruction at the end of the prologue. I have never seen GCC produce
712 this, and the ARM docs don't mention it. We still test for it below in
718 arm_scan_prologue (struct frame_info
*fi
)
720 int regno
, sp_offset
, fp_offset
;
721 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
723 /* Check if this function is already in the cache of frame information. */
724 if (check_prologue_cache (fi
))
727 /* Assume there is no frame until proven otherwise. */
728 fi
->framereg
= SP_REGNUM
;
732 /* Check for Thumb prologue. */
733 if (arm_pc_is_thumb (fi
->pc
))
735 thumb_scan_prologue (fi
);
736 save_prologue_cache (fi
);
740 /* Find the function prologue. If we can't find the function in
741 the symbol table, peek in the stack frame to find the PC. */
742 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
744 /* One way to find the end of the prologue (which works well
745 for unoptimized code) is to do the following:
747 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
750 prologue_end = fi->pc;
751 else if (sal.end < prologue_end)
752 prologue_end = sal.end;
754 This mechanism is very accurate so long as the optimizer
755 doesn't move any instructions from the function body into the
756 prologue. If this happens, sal.end will be the last
757 instruction in the first hunk of prologue code just before
758 the first instruction that the scheduler has moved from
759 the body to the prologue.
761 In order to make sure that we scan all of the prologue
762 instructions, we use a slightly less accurate mechanism which
763 may scan more than necessary. To help compensate for this
764 lack of accuracy, the prologue scanning loop below contains
765 several clauses which'll cause the loop to terminate early if
766 an implausible prologue instruction is encountered.
772 is a suitable endpoint since it accounts for the largest
773 possible prologue plus up to five instructions inserted by
776 if (prologue_end
> prologue_start
+ 64)
778 prologue_end
= prologue_start
+ 64; /* See above. */
783 /* Get address of the stmfd in the prologue of the callee; the saved
784 PC is the address of the stmfd + 8. */
785 prologue_start
= ADDR_BITS_REMOVE (read_memory_integer (fi
->frame
, 4))
787 prologue_end
= prologue_start
+ 64; /* See above. */
790 /* Now search the prologue looking for instructions that set up the
791 frame pointer, adjust the stack pointer, and save registers.
793 Be careful, however, and if it doesn't look like a prologue,
794 don't try to scan it. If, for instance, a frameless function
795 begins with stmfd sp!, then we will tell ourselves there is
796 a frame, which will confuse stack traceback, as well ad"finish"
797 and other operations that rely on a knowledge of the stack
800 In the APCS, the prologue should start with "mov ip, sp" so
801 if we don't see this as the first insn, we will stop. */
803 sp_offset
= fp_offset
= 0;
805 if (read_memory_unsigned_integer (prologue_start
, 4)
806 == 0xe1a0c00d) /* mov ip, sp */
808 for (current_pc
= prologue_start
+ 4; current_pc
< prologue_end
;
811 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
813 if ((insn
& 0xffff0000) == 0xe92d0000)
814 /* stmfd sp!, {..., fp, ip, lr, pc}
816 stmfd sp!, {a1, a2, a3, a4} */
818 int mask
= insn
& 0xffff;
820 /* Calculate offsets of saved registers. */
821 for (regno
= PC_REGNUM
; regno
>= 0; regno
--)
822 if (mask
& (1 << regno
))
825 fi
->fsr
.regs
[regno
] = sp_offset
;
828 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
830 unsigned imm
= insn
& 0xff; /* immediate value */
831 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
832 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
834 fi
->framereg
= FP_REGNUM
;
836 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
838 unsigned imm
= insn
& 0xff; /* immediate value */
839 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
840 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
843 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
846 regno
= F0_REGNUM
+ ((insn
>> 12) & 0x07);
847 fi
->fsr
.regs
[regno
] = sp_offset
;
849 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
852 unsigned int fp_start_reg
, fp_bound_reg
;
854 if ((insn
& 0x800) == 0x800) /* N0 is set */
856 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
863 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
869 fp_start_reg
= F0_REGNUM
+ ((insn
>> 12) & 0x7);
870 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
871 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
874 fi
->fsr
.regs
[fp_start_reg
++] = sp_offset
;
877 else if ((insn
& 0xf0000000) != 0xe0000000)
878 break; /* Condition not true, exit early */
879 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
880 break; /* Don't scan past a block load */
882 /* The optimizer might shove anything into the prologue,
883 so we just skip what we don't recognize. */
888 /* The frame size is just the negative of the offset (from the original SP)
889 of the last thing thing we pushed on the stack. The frame offset is
890 [new FP] - [new SP]. */
891 fi
->framesize
= -sp_offset
;
892 fi
->frameoffset
= fp_offset
- sp_offset
;
894 save_prologue_cache (fi
);
897 /* Find REGNUM on the stack. Otherwise, it's in an active register.
898 One thing we might want to do here is to check REGNUM against the
899 clobber mask, and somehow flag it as invalid if it isn't saved on
900 the stack somewhere. This would provide a graceful failure mode
901 when trying to get the value of caller-saves registers for an inner
905 arm_find_callers_reg (struct frame_info
*fi
, int regnum
)
907 for (; fi
; fi
= fi
->next
)
909 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
910 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
911 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
914 if (fi
->fsr
.regs
[regnum
] != 0)
915 return read_memory_integer (fi
->fsr
.regs
[regnum
],
916 REGISTER_RAW_SIZE (regnum
));
917 return read_register (regnum
);
920 /* Function: frame_chain
921 Given a GDB frame, determine the address of the calling function's frame.
922 This will be used to create a new GDB frame struct, and then
923 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
924 For ARM, we save the frame size when we initialize the frame_info.
926 The original definition of this function was a macro in tm-arm.h:
927 { In the case of the ARM, the frame's nominal address is the FP value,
928 and 12 bytes before comes the saved previous FP value as a 4-byte word. }
930 #define FRAME_CHAIN(thisframe) \
931 ((thisframe)->pc >= LOWEST_PC ? \
932 read_memory_integer ((thisframe)->frame - 12, 4) :\
938 arm_frame_chain (struct frame_info
*fi
)
940 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
941 CORE_ADDR fn_start
, callers_pc
, fp
;
943 /* is this a dummy frame? */
944 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
945 return fi
->frame
; /* dummy frame same as caller's frame */
947 /* is caller-of-this a dummy frame? */
948 callers_pc
= FRAME_SAVED_PC (fi
); /* find out who called us: */
949 fp
= arm_find_callers_reg (fi
, FP_REGNUM
);
950 if (PC_IN_CALL_DUMMY (callers_pc
, fp
, fp
))
951 return fp
; /* dummy frame's frame may bear no relation to ours */
953 if (find_pc_partial_function (fi
->pc
, 0, &fn_start
, 0))
954 if (fn_start
== entry_point_address ())
955 return 0; /* in _start fn, don't chain further */
957 CORE_ADDR caller_pc
, fn_start
;
958 struct frame_info caller_fi
;
959 int framereg
= fi
->framereg
;
961 if (fi
->pc
< LOWEST_PC
)
964 /* If the caller is the startup code, we're at the end of the chain. */
965 caller_pc
= FRAME_SAVED_PC (fi
);
966 if (find_pc_partial_function (caller_pc
, 0, &fn_start
, 0))
967 if (fn_start
== entry_point_address ())
970 /* If the caller is Thumb and the caller is ARM, or vice versa,
971 the frame register of the caller is different from ours.
972 So we must scan the prologue of the caller to determine its
973 frame register number. */
974 if (arm_pc_is_thumb (caller_pc
) != arm_pc_is_thumb (fi
->pc
))
976 memset (&caller_fi
, 0, sizeof (caller_fi
));
977 caller_fi
.pc
= caller_pc
;
978 arm_scan_prologue (&caller_fi
);
979 framereg
= caller_fi
.framereg
;
982 /* If the caller used a frame register, return its value.
983 Otherwise, return the caller's stack pointer. */
984 if (framereg
== FP_REGNUM
|| framereg
== THUMB_FP_REGNUM
)
985 return arm_find_callers_reg (fi
, framereg
);
987 return fi
->frame
+ fi
->framesize
;
990 /* This function actually figures out the frame address for a given pc
991 and sp. This is tricky because we sometimes don't use an explicit
992 frame pointer, and the previous stack pointer isn't necessarily
993 recorded on the stack. The only reliable way to get this info is
994 to examine the prologue. FROMLEAF is a little confusing, it means
995 this is the next frame up the chain AFTER a frameless function. If
996 this is true, then the frame value for this frame is still in the
1000 arm_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1005 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1007 memset (fi
->fsr
.regs
, '\000', sizeof fi
->fsr
.regs
);
1009 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1010 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1012 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1013 by assuming it's always FP. */
1014 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
, SP_REGNUM
);
1016 fi
->frameoffset
= 0;
1022 /* Determine whether or not we're in a sigtramp frame.
1023 Unfortunately, it isn't sufficient to test
1024 fi->signal_handler_caller because this value is sometimes set
1025 after invoking INIT_EXTRA_FRAME_INFO. So we test *both*
1026 fi->signal_handler_caller and IN_SIGTRAMP to determine if we need
1027 to use the sigcontext addresses for the saved registers.
1029 Note: If an ARM IN_SIGTRAMP method ever needs to compare against
1030 the name of the function, the code below will have to be changed
1031 to first fetch the name of the function and then pass this name
1034 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1035 && (fi
->signal_handler_caller
|| IN_SIGTRAMP (fi
->pc
, 0)))
1042 sp
= fi
->next
->frame
- fi
->next
->frameoffset
+ fi
->next
->framesize
;
1044 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1045 fi
->fsr
.regs
[reg
] = SIGCONTEXT_REGISTER_ADDRESS (sp
, fi
->pc
, reg
);
1047 /* FIXME: What about thumb mode? */
1048 fi
->framereg
= SP_REGNUM
;
1049 fi
->frame
= read_memory_integer (fi
->fsr
.regs
[fi
->framereg
], 4);
1051 fi
->frameoffset
= 0;
1056 arm_scan_prologue (fi
);
1059 /* this is the innermost frame? */
1060 fi
->frame
= read_register (fi
->framereg
);
1061 else if (fi
->framereg
== FP_REGNUM
|| fi
->framereg
== THUMB_FP_REGNUM
)
1063 /* not the innermost frame */
1064 /* If we have an FP, the callee saved it. */
1065 if (fi
->next
->fsr
.regs
[fi
->framereg
] != 0)
1067 read_memory_integer (fi
->next
->fsr
.regs
[fi
->framereg
], 4);
1069 /* If we were called by a frameless fn. then our frame is
1070 still in the frame pointer register on the board... */
1071 fi
->frame
= read_fp ();
1074 /* Calculate actual addresses of saved registers using offsets
1075 determined by arm_scan_prologue. */
1076 for (reg
= 0; reg
< NUM_REGS
; reg
++)
1077 if (fi
->fsr
.regs
[reg
] != 0)
1078 fi
->fsr
.regs
[reg
] += fi
->frame
+ fi
->framesize
- fi
->frameoffset
;
1083 /* Find the caller of this frame. We do this by seeing if LR_REGNUM
1084 is saved in the stack anywhere, otherwise we get it from the
1087 The old definition of this function was a macro:
1088 #define FRAME_SAVED_PC(FRAME) \
1089 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1092 arm_frame_saved_pc (struct frame_info
*fi
)
1094 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1095 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1096 return generic_read_register_dummy (fi
->pc
, fi
->frame
, PC_REGNUM
);
1100 CORE_ADDR pc
= arm_find_callers_reg (fi
, LR_REGNUM
);
1101 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1105 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1106 Examine the Program Status Register to decide which state we're in. */
1109 arm_target_read_fp (void)
1111 if (read_register (PS_REGNUM
) & 0x20) /* Bit 5 is Thumb state bit */
1112 return read_register (THUMB_FP_REGNUM
); /* R7 if Thumb */
1114 return read_register (FP_REGNUM
); /* R11 if ARM */
1117 /* Calculate the frame offsets of the saved registers (ARM version). */
1120 arm_frame_find_saved_regs (struct frame_info
*fi
,
1121 struct frame_saved_regs
*regaddr
)
1123 memcpy (regaddr
, &fi
->fsr
, sizeof (struct frame_saved_regs
));
1127 arm_push_dummy_frame (void)
1129 CORE_ADDR old_sp
= read_register (SP_REGNUM
);
1130 CORE_ADDR sp
= old_sp
;
1131 CORE_ADDR fp
, prologue_start
;
1134 /* Push the two dummy prologue instructions in reverse order,
1135 so that they'll be in the correct low-to-high order in memory. */
1136 /* sub fp, ip, #4 */
1137 sp
= push_word (sp
, 0xe24cb004);
1138 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1139 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
1141 /* Push a pointer to the dummy prologue + 12, because when stm
1142 instruction stores the PC, it stores the address of the stm
1143 instruction itself plus 12. */
1144 fp
= sp
= push_word (sp
, prologue_start
+ 12);
1145 sp
= push_word (sp
, read_register (PC_REGNUM
)); /* FIXME: was PS_REGNUM */
1146 sp
= push_word (sp
, old_sp
);
1147 sp
= push_word (sp
, read_register (FP_REGNUM
));
1149 for (regnum
= 10; regnum
>= 0; regnum
--)
1150 sp
= push_word (sp
, read_register (regnum
));
1152 write_register (FP_REGNUM
, fp
);
1153 write_register (THUMB_FP_REGNUM
, fp
);
1154 write_register (SP_REGNUM
, sp
);
1157 /* Fix up the call dummy, based on whether the processor is currently
1158 in Thumb or ARM mode, and whether the target function is Thumb or
1159 ARM. There are three different situations requiring three
1162 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1163 been copied into the dummy parameter to this function.
1164 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1165 "mov pc,r4" instruction patched to be a "bx r4" instead.
1166 * Thumb calling anything: uses the Thumb dummy defined below, which
1167 works for calling both ARM and Thumb functions.
1169 All three call dummies expect to receive the target function
1170 address in R4, with the low bit set if it's a Thumb function. */
1173 arm_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
1174 struct value
**args
, struct type
*type
, int gcc_p
)
1176 static short thumb_dummy
[4] =
1178 0xf000, 0xf801, /* bl label */
1179 0xdf18, /* swi 24 */
1180 0x4720, /* label: bx r4 */
1182 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
1184 /* Set flag indicating whether the current PC is in a Thumb function. */
1185 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
1187 /* If the target function is Thumb, set the low bit of the function
1188 address. And if the CPU is currently in ARM mode, patch the
1189 second instruction of call dummy to use a BX instruction to
1190 switch to Thumb mode. */
1191 target_is_thumb
= arm_pc_is_thumb (fun
);
1192 if (target_is_thumb
)
1195 if (!caller_is_thumb
)
1196 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
1199 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1200 instead of the ARM one that's already been copied. This will
1201 work for both Thumb and ARM target functions. */
1202 if (caller_is_thumb
)
1206 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
1208 for (i
= 0; i
< len
; i
++)
1210 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1211 p
+= sizeof (thumb_dummy
[0]);
1215 /* Put the target address in r4; the call dummy will copy this to
1217 write_register (4, fun
);
1220 /* Return the offset in the call dummy of the instruction that needs
1221 to have a breakpoint placed on it. This is the offset of the 'swi
1222 24' instruction, which is no longer actually used, but simply acts
1223 as a place-holder now.
1225 This implements the CALL_DUMMY_BREAK_OFFSET macro. */
1228 arm_call_dummy_breakpoint_offset (void)
1230 if (caller_is_thumb
)
1238 This function does not support passing parameters using the FPA
1239 variant of the APCS. It passes any floating point arguments in the
1240 general registers and/or on the stack. */
1243 arm_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
1244 int struct_return
, CORE_ADDR struct_addr
)
1247 int argnum
, argreg
, nstack_size
;
1249 /* Walk through the list of args and determine how large a temporary
1250 stack is required. Need to take care here as structs may be
1251 passed on the stack, and we have to to push them. */
1252 nstack_size
= -4 * REGISTER_SIZE
; /* Some arguments go into A1-A4. */
1253 if (struct_return
) /* The struct address goes in A1. */
1254 nstack_size
+= REGISTER_SIZE
;
1256 /* Walk through the arguments and add their size to nstack_size. */
1257 for (argnum
= 0; argnum
< nargs
; argnum
++)
1260 struct type
*arg_type
;
1262 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1263 len
= TYPE_LENGTH (arg_type
);
1265 /* ANSI C code passes float arguments as integers, K&R code
1266 passes float arguments as doubles. Correct for this here. */
1267 if (TYPE_CODE_FLT
== TYPE_CODE (arg_type
) && REGISTER_SIZE
== len
)
1268 nstack_size
+= FP_REGISTER_VIRTUAL_SIZE
;
1273 /* Allocate room on the stack, and initialize our stack frame
1276 if (nstack_size
> 0)
1282 /* Initialize the integer argument register pointer. */
1285 /* The struct_return pointer occupies the first parameter passing
1288 write_register (argreg
++, struct_addr
);
1290 /* Process arguments from left to right. Store as many as allowed
1291 in the parameter passing registers (A1-A4), and save the rest on
1292 the temporary stack. */
1293 for (argnum
= 0; argnum
< nargs
; argnum
++)
1298 enum type_code typecode
;
1299 struct type
*arg_type
, *target_type
;
1301 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1302 target_type
= TYPE_TARGET_TYPE (arg_type
);
1303 len
= TYPE_LENGTH (arg_type
);
1304 typecode
= TYPE_CODE (arg_type
);
1305 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
1307 /* ANSI C code passes float arguments as integers, K&R code
1308 passes float arguments as doubles. The .stabs record for
1309 for ANSI prototype floating point arguments records the
1310 type as FP_INTEGER, while a K&R style (no prototype)
1311 .stabs records the type as FP_FLOAT. In this latter case
1312 the compiler converts the float arguments to double before
1313 calling the function. */
1314 if (TYPE_CODE_FLT
== typecode
&& REGISTER_SIZE
== len
)
1317 dblval
= extract_floating (val
, len
);
1318 len
= TARGET_DOUBLE_BIT
/ TARGET_CHAR_BIT
;
1320 store_floating (val
, len
, dblval
);
1323 /* I don't know why this code was disable. The only logical use
1324 for a function pointer is to call that function, so setting
1325 the mode bit is perfectly fine. FN */
1326 /* If the argument is a pointer to a function, and it is a Thumb
1327 function, set the low bit of the pointer. */
1328 if (TYPE_CODE_PTR
== typecode
1329 && NULL
!= target_type
1330 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1332 CORE_ADDR regval
= extract_address (val
, len
);
1333 if (arm_pc_is_thumb (regval
))
1334 store_address (val
, len
, MAKE_THUMB_ADDR (regval
));
1337 /* Copy the argument to general registers or the stack in
1338 register-sized pieces. Large arguments are split between
1339 registers and stack. */
1342 int partial_len
= len
< REGISTER_SIZE
? len
: REGISTER_SIZE
;
1344 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1346 /* It's an argument being passed in a general register. */
1347 regval
= extract_address (val
, partial_len
);
1348 write_register (argreg
++, regval
);
1352 /* Push the arguments onto the stack. */
1353 write_memory ((CORE_ADDR
) fp
, val
, REGISTER_SIZE
);
1354 fp
+= REGISTER_SIZE
;
1362 /* Return adjusted stack pointer. */
1367 arm_pop_frame (void)
1370 struct frame_info
*frame
= get_current_frame ();
1372 if (!PC_IN_CALL_DUMMY(frame
->pc
, frame
->frame
, read_fp()))
1376 old_SP
= read_register (frame
->framereg
);
1377 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1378 if (frame
->fsr
.regs
[regnum
] != 0)
1379 write_register (regnum
,
1380 read_memory_integer (frame
->fsr
.regs
[regnum
], 4));
1382 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
1383 write_register (SP_REGNUM
, old_SP
);
1389 sp
= read_register (FP_REGNUM
);
1390 sp
-= sizeof(CORE_ADDR
); /* we don't care about this first word */
1392 write_register (PC_REGNUM
, read_memory_integer (sp
, 4));
1393 sp
-= sizeof(CORE_ADDR
);
1394 write_register (SP_REGNUM
, read_memory_integer (sp
, 4));
1395 sp
-= sizeof(CORE_ADDR
);
1396 write_register (FP_REGNUM
, read_memory_integer (sp
, 4));
1397 sp
-= sizeof(CORE_ADDR
);
1399 for (regnum
= 10; regnum
>= 0; regnum
--)
1401 write_register (regnum
, read_memory_integer (sp
, 4));
1402 sp
-= sizeof(CORE_ADDR
);
1406 flush_cached_frames ();
1410 print_fpu_flags (int flags
)
1412 if (flags
& (1 << 0))
1413 fputs ("IVO ", stdout
);
1414 if (flags
& (1 << 1))
1415 fputs ("DVZ ", stdout
);
1416 if (flags
& (1 << 2))
1417 fputs ("OFL ", stdout
);
1418 if (flags
& (1 << 3))
1419 fputs ("UFL ", stdout
);
1420 if (flags
& (1 << 4))
1421 fputs ("INX ", stdout
);
1426 arm_float_info (void)
1428 register unsigned long status
= read_register (FPS_REGNUM
);
1431 type
= (status
>> 24) & 127;
1432 printf ("%s FPU type %d\n",
1433 (status
& (1 << 31)) ? "Hardware" : "Software",
1435 fputs ("mask: ", stdout
);
1436 print_fpu_flags (status
>> 16);
1437 fputs ("flags: ", stdout
);
1438 print_fpu_flags (status
);
1442 arm_register_type (int regnum
)
1444 if (regnum
>= F0_REGNUM
&& regnum
< F0_REGNUM
+ NUM_FREGS
)
1446 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1447 return builtin_type_arm_ext_big
;
1449 return builtin_type_arm_ext_littlebyte_bigword
;
1452 return builtin_type_int32
;
1455 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1456 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1457 It is thought that this is is the floating-point register format on
1458 little-endian systems. */
1461 convert_from_extended (void *ptr
, void *dbl
)
1464 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1465 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1467 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1469 floatformat_from_doublest (TARGET_DOUBLE_FORMAT
, &d
, dbl
);
1473 convert_to_extended (void *dbl
, void *ptr
)
1476 floatformat_to_doublest (TARGET_DOUBLE_FORMAT
, ptr
, &d
);
1477 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1478 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1480 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1485 condition_true (unsigned long cond
, unsigned long status_reg
)
1487 if (cond
== INST_AL
|| cond
== INST_NV
)
1493 return ((status_reg
& FLAG_Z
) != 0);
1495 return ((status_reg
& FLAG_Z
) == 0);
1497 return ((status_reg
& FLAG_C
) != 0);
1499 return ((status_reg
& FLAG_C
) == 0);
1501 return ((status_reg
& FLAG_N
) != 0);
1503 return ((status_reg
& FLAG_N
) == 0);
1505 return ((status_reg
& FLAG_V
) != 0);
1507 return ((status_reg
& FLAG_V
) == 0);
1509 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1511 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1513 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1515 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1517 return (((status_reg
& FLAG_Z
) == 0) &&
1518 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1520 return (((status_reg
& FLAG_Z
) != 0) ||
1521 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1526 #define submask(x) ((1L << ((x) + 1)) - 1)
1527 #define bit(obj,st) (((obj) >> (st)) & 1)
1528 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1529 #define sbits(obj,st,fn) \
1530 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1531 #define BranchDest(addr,instr) \
1532 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1535 static unsigned long
1536 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1537 unsigned long status_reg
)
1539 unsigned long res
, shift
;
1540 int rm
= bits (inst
, 0, 3);
1541 unsigned long shifttype
= bits (inst
, 5, 6);
1545 int rs
= bits (inst
, 8, 11);
1546 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1549 shift
= bits (inst
, 7, 11);
1552 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1553 + (bit (inst
, 4) ? 12 : 8))
1554 : read_register (rm
));
1559 res
= shift
>= 32 ? 0 : res
<< shift
;
1563 res
= shift
>= 32 ? 0 : res
>> shift
;
1569 res
= ((res
& 0x80000000L
)
1570 ? ~((~res
) >> shift
) : res
>> shift
);
1573 case 3: /* ROR/RRX */
1576 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1578 res
= (res
>> shift
) | (res
<< (32 - shift
));
1582 return res
& 0xffffffff;
1585 /* Return number of 1-bits in VAL. */
1588 bitcount (unsigned long val
)
1591 for (nbits
= 0; val
!= 0; nbits
++)
1592 val
&= val
- 1; /* delete rightmost 1-bit in val */
1597 thumb_get_next_pc (CORE_ADDR pc
)
1599 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1600 unsigned short inst1
= read_memory_integer (pc
, 2);
1601 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1602 unsigned long offset
;
1604 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1608 /* Fetch the saved PC from the stack. It's stored above
1609 all of the other registers. */
1610 offset
= bitcount (bits (inst1
, 0, 7)) * REGISTER_SIZE
;
1611 sp
= read_register (SP_REGNUM
);
1612 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1613 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1615 error ("Infinite loop detected");
1617 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1619 unsigned long status
= read_register (PS_REGNUM
);
1620 unsigned long cond
= bits (inst1
, 8, 11);
1621 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1622 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1624 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1626 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1628 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1630 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1631 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1632 nextpc
= pc_val
+ offset
;
1639 arm_get_next_pc (CORE_ADDR pc
)
1641 unsigned long pc_val
;
1642 unsigned long this_instr
;
1643 unsigned long status
;
1646 if (arm_pc_is_thumb (pc
))
1647 return thumb_get_next_pc (pc
);
1649 pc_val
= (unsigned long) pc
;
1650 this_instr
= read_memory_integer (pc
, 4);
1651 status
= read_register (PS_REGNUM
);
1652 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1654 if (condition_true (bits (this_instr
, 28, 31), status
))
1656 switch (bits (this_instr
, 24, 27))
1659 case 0x1: /* data processing */
1663 unsigned long operand1
, operand2
, result
= 0;
1667 if (bits (this_instr
, 12, 15) != 15)
1670 if (bits (this_instr
, 22, 25) == 0
1671 && bits (this_instr
, 4, 7) == 9) /* multiply */
1672 error ("Illegal update to pc in instruction");
1674 /* Multiply into PC */
1675 c
= (status
& FLAG_C
) ? 1 : 0;
1676 rn
= bits (this_instr
, 16, 19);
1677 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1679 if (bit (this_instr
, 25))
1681 unsigned long immval
= bits (this_instr
, 0, 7);
1682 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1683 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1686 else /* operand 2 is a shifted register */
1687 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1689 switch (bits (this_instr
, 21, 24))
1692 result
= operand1
& operand2
;
1696 result
= operand1
^ operand2
;
1700 result
= operand1
- operand2
;
1704 result
= operand2
- operand1
;
1708 result
= operand1
+ operand2
;
1712 result
= operand1
+ operand2
+ c
;
1716 result
= operand1
- operand2
+ c
;
1720 result
= operand2
- operand1
+ c
;
1726 case 0xb: /* tst, teq, cmp, cmn */
1727 result
= (unsigned long) nextpc
;
1731 result
= operand1
| operand2
;
1735 /* Always step into a function. */
1740 result
= operand1
& ~operand2
;
1747 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1750 error ("Infinite loop detected");
1755 case 0x5: /* data transfer */
1758 if (bit (this_instr
, 20))
1761 if (bits (this_instr
, 12, 15) == 15)
1767 if (bit (this_instr
, 22))
1768 error ("Illegal update to pc in instruction");
1770 /* byte write to PC */
1771 rn
= bits (this_instr
, 16, 19);
1772 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1773 if (bit (this_instr
, 24))
1776 int c
= (status
& FLAG_C
) ? 1 : 0;
1777 unsigned long offset
=
1778 (bit (this_instr
, 25)
1779 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1780 : bits (this_instr
, 0, 11));
1782 if (bit (this_instr
, 23))
1787 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1790 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1793 error ("Infinite loop detected");
1799 case 0x9: /* block transfer */
1800 if (bit (this_instr
, 20))
1803 if (bit (this_instr
, 15))
1808 if (bit (this_instr
, 23))
1811 unsigned long reglist
= bits (this_instr
, 0, 14);
1812 offset
= bitcount (reglist
) * 4;
1813 if (bit (this_instr
, 24)) /* pre */
1816 else if (bit (this_instr
, 24))
1820 unsigned long rn_val
=
1821 read_register (bits (this_instr
, 16, 19));
1823 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1827 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1829 error ("Infinite loop detected");
1834 case 0xb: /* branch & link */
1835 case 0xa: /* branch */
1837 nextpc
= BranchDest (pc
, this_instr
);
1839 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1841 error ("Infinite loop detected");
1847 case 0xe: /* coproc ops */
1852 fprintf (stderr
, "Bad bit-field extraction\n");
1860 #include "bfd-in2.h"
1861 #include "libcoff.h"
1864 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
1866 if (arm_pc_is_thumb (memaddr
))
1868 static asymbol
*asym
;
1869 static combined_entry_type ce
;
1870 static struct coff_symbol_struct csym
;
1871 static struct _bfd fake_bfd
;
1872 static bfd_target fake_target
;
1874 if (csym
.native
== NULL
)
1876 /* Create a fake symbol vector containing a Thumb symbol. This is
1877 solely so that the code in print_insn_little_arm() and
1878 print_insn_big_arm() in opcodes/arm-dis.c will detect the presence
1879 of a Thumb symbol and switch to decoding Thumb instructions. */
1881 fake_target
.flavour
= bfd_target_coff_flavour
;
1882 fake_bfd
.xvec
= &fake_target
;
1883 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
1885 csym
.symbol
.the_bfd
= &fake_bfd
;
1886 csym
.symbol
.name
= "fake";
1887 asym
= (asymbol
*) & csym
;
1890 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
1891 info
->symbols
= &asym
;
1894 info
->symbols
= NULL
;
1896 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1897 return print_insn_big_arm (memaddr
, info
);
1899 return print_insn_little_arm (memaddr
, info
);
1902 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the
1903 program counter value to determine whether a 16-bit or 32-bit
1904 breakpoint should be used. It returns a pointer to a string of
1905 bytes that encode a breakpoint instruction, stores the length of
1906 the string to *lenptr, and adjusts the program counter (if
1907 necessary) to point to the actual memory location where the
1908 breakpoint should be inserted. */
1911 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1913 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
1915 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1917 static char thumb_breakpoint
[] = THUMB_BE_BREAKPOINT
;
1918 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1919 *lenptr
= sizeof (thumb_breakpoint
);
1920 return thumb_breakpoint
;
1924 static char thumb_breakpoint
[] = THUMB_LE_BREAKPOINT
;
1925 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1926 *lenptr
= sizeof (thumb_breakpoint
);
1927 return thumb_breakpoint
;
1932 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1934 static char arm_breakpoint
[] = ARM_BE_BREAKPOINT
;
1935 *lenptr
= sizeof (arm_breakpoint
);
1936 return arm_breakpoint
;
1940 static char arm_breakpoint
[] = ARM_LE_BREAKPOINT
;
1941 *lenptr
= sizeof (arm_breakpoint
);
1942 return arm_breakpoint
;
1947 /* Extract from an array REGBUF containing the (raw) register state a
1948 function return value of type TYPE, and copy that, in virtual
1949 format, into VALBUF. */
1952 arm_extract_return_value (struct type
*type
,
1953 char regbuf
[REGISTER_BYTES
],
1956 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
1957 convert_from_extended (®buf
[REGISTER_BYTE (F0_REGNUM
)], valbuf
);
1959 memcpy (valbuf
, ®buf
[REGISTER_BYTE (A1_REGNUM
)], TYPE_LENGTH (type
));
1962 /* Return non-zero if the PC is inside a thumb call thunk. */
1965 arm_in_call_stub (CORE_ADDR pc
, char *name
)
1967 CORE_ADDR start_addr
;
1969 /* Find the starting address of the function containing the PC. If
1970 the caller didn't give us a name, look it up at the same time. */
1971 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
1974 return strncmp (name
, "_call_via_r", 11) == 0;
1977 /* If PC is in a Thumb call or return stub, return the address of the
1978 target PC, which is in a register. The thunk functions are called
1979 _called_via_xx, where x is the register name. The possible names
1980 are r0-r9, sl, fp, ip, sp, and lr. */
1983 arm_skip_stub (CORE_ADDR pc
)
1986 CORE_ADDR start_addr
;
1988 /* Find the starting address and name of the function containing the PC. */
1989 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1992 /* Call thunks always start with "_call_via_". */
1993 if (strncmp (name
, "_call_via_", 10) == 0)
1995 /* Use the name suffix to determine which register contains the
1997 static char *table
[15] =
1998 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1999 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2003 for (regno
= 0; regno
<= 14; regno
++)
2004 if (strcmp (&name
[10], table
[regno
]) == 0)
2005 return read_register (regno
);
2008 return 0; /* not a stub */
2011 /* If the user changes the register disassembly flavor used for info register
2012 and other commands, we have to also switch the flavor used in opcodes
2013 for disassembly output.
2014 This function is run in the set disassembly_flavor command, and does that. */
2017 set_disassembly_flavor_sfunc (char *args
, int from_tty
,
2018 struct cmd_list_element
*c
)
2020 set_disassembly_flavor ();
2024 set_disassembly_flavor (void)
2026 const char *setname
, *setdesc
, **regnames
;
2029 /* Find the flavor that the user wants in the opcodes table. */
2031 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2032 while ((disassembly_flavor
!= setname
)
2033 && (current
< num_flavor_options
))
2034 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2035 current_option
= current
;
2037 /* Fill our copy. */
2038 for (j
= 0; j
< numregs
; j
++)
2039 arm_register_names
[j
] = (char *) regnames
[j
];
2042 if (isupper (*regnames
[PC_REGNUM
]))
2044 arm_register_names
[FPS_REGNUM
] = "FPS";
2045 arm_register_names
[PS_REGNUM
] = "CPSR";
2049 arm_register_names
[FPS_REGNUM
] = "fps";
2050 arm_register_names
[PS_REGNUM
] = "cpsr";
2053 /* Synchronize the disassembler. */
2054 set_arm_regname_option (current
);
2057 /* arm_othernames implements the "othernames" command. This is kind
2058 of hacky, and I prefer the set-show disassembly-flavor which is
2059 also used for the x86 gdb. I will keep this around, however, in
2060 case anyone is actually using it. */
2063 arm_othernames (char *names
, int n
)
2065 /* Circle through the various flavors. */
2066 current_option
= (current_option
+ 1) % num_flavor_options
;
2068 disassembly_flavor
= valid_flavors
[current_option
];
2069 set_disassembly_flavor ();
2072 /* Fetch, and possibly build, an appropriate link_map_offsets structure
2073 for ARM linux targets using the struct offsets defined in <link.h>.
2074 Note, however, that link.h is not actually referred to in this file.
2075 Instead, the relevant structs offsets were obtained from examining
2076 link.h. (We can't refer to link.h from this file because the host
2077 system won't necessarily have it, or if it does, the structs which
2078 it defines will refer to the host system, not the target.) */
2080 struct link_map_offsets
*
2081 arm_linux_svr4_fetch_link_map_offsets (void)
2083 static struct link_map_offsets lmo
;
2084 static struct link_map_offsets
*lmp
= 0;
2090 lmo
.r_debug_size
= 8; /* Actual size is 20, but this is all we
2093 lmo
.r_map_offset
= 4;
2096 lmo
.link_map_size
= 20; /* Actual size is 552, but this is all we
2099 lmo
.l_addr_offset
= 0;
2100 lmo
.l_addr_size
= 4;
2102 lmo
.l_name_offset
= 4;
2103 lmo
.l_name_size
= 4;
2105 lmo
.l_next_offset
= 12;
2106 lmo
.l_next_size
= 4;
2108 lmo
.l_prev_offset
= 16;
2109 lmo
.l_prev_size
= 4;
2116 _initialize_arm_tdep (void)
2118 struct ui_file
*stb
;
2120 struct cmd_list_element
*new_cmd
;
2121 const char *setname
;
2122 const char *setdesc
;
2123 const char **regnames
;
2125 static char *helptext
;
2127 tm_print_insn
= gdb_print_insn_arm
;
2129 /* Get the number of possible sets of register names defined in opcodes. */
2130 num_flavor_options
= get_arm_regname_num_options ();
2132 /* Sync the opcode insn printer with our register viewer: */
2133 parse_arm_disassembler_option ("reg-names-std");
2135 /* Begin creating the help text. */
2136 stb
= mem_fileopen ();
2137 fprintf_unfiltered (stb
, "Set the disassembly flavor.\n\
2138 The valid values are:\n");
2140 /* Initialize the array that will be passed to add_set_enum_cmd(). */
2141 valid_flavors
= xmalloc ((num_flavor_options
+ 1) * sizeof (char *));
2142 for (i
= 0; i
< num_flavor_options
; i
++)
2144 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
2145 valid_flavors
[i
] = setname
;
2146 fprintf_unfiltered (stb
, "%s - %s\n", setname
,
2148 /* Copy the default names (if found) and synchronize disassembler. */
2149 if (!strcmp (setname
, "std"))
2151 disassembly_flavor
= setname
;
2153 for (j
= 0; j
< numregs
; j
++)
2154 arm_register_names
[j
] = (char *) regnames
[j
];
2155 set_arm_regname_option (i
);
2158 /* Mark the end of valid options. */
2159 valid_flavors
[num_flavor_options
] = NULL
;
2161 /* Finish the creation of the help text. */
2162 fprintf_unfiltered (stb
, "The default is \"std\".");
2163 helptext
= ui_file_xstrdup (stb
, &length
);
2164 ui_file_delete (stb
);
2166 /* Add the disassembly-flavor command */
2167 new_cmd
= add_set_enum_cmd ("disassembly-flavor", no_class
,
2169 &disassembly_flavor
,
2172 new_cmd
->function
.sfunc
= set_disassembly_flavor_sfunc
;
2173 add_show_from_set (new_cmd
, &showlist
);
2175 /* ??? Maybe this should be a boolean. */
2176 add_show_from_set (add_set_cmd ("apcs32", no_class
,
2177 var_zinteger
, (char *) &arm_apcs_32
,
2178 "Set usage of ARM 32-bit mode.\n", &setlist
),
2181 /* Add the deprecated "othernames" command */
2183 add_com ("othernames", class_obscure
, arm_othernames
,
2184 "Switch to the next set of register names.");
2187 /* Test whether the coff symbol specific value corresponds to a Thumb
2191 coff_sym_is_thumb (int val
)
2193 return (val
== C_THUMBEXT
||
2194 val
== C_THUMBSTAT
||
2195 val
== C_THUMBEXTFUNC
||
2196 val
== C_THUMBSTATFUNC
||
2197 val
== C_THUMBLABEL
);