1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper () */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
43 #include "target-descriptions.h"
44 #include "user-regs.h"
47 #include "gdb/sim-arm.h"
50 #include "coff/internal.h"
53 #include "gdb_assert.h"
58 /* Macros for setting and testing a bit in a minimal symbol that marks
59 it as Thumb function. The MSB of the minimal symbol's "info" field
60 is used for this purpose.
62 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
63 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
65 #define MSYMBOL_SET_SPECIAL(msym) \
66 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
69 #define MSYMBOL_IS_SPECIAL(msym) \
70 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
72 /* Macros for swapping shorts and ints. In the unlikely case that anybody else needs these,
73 move to a general header. (A better solution might be to define memory read routines that
74 know whether they are reading code or data.) */
76 #define SWAP_SHORT(x) \
77 ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8));
80 ( ((x & 0xff000000) >> 24) \
81 | ((x & 0x00ff0000) >> 8) \
82 | ((x & 0x0000ff00) << 8) \
83 | ((x & 0x000000ff) << 24))
85 /* Per-objfile data used for mapping symbols. */
86 static const struct objfile_data
*arm_objfile_data_key
;
88 struct arm_mapping_symbol
93 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
94 DEF_VEC_O(arm_mapping_symbol_s
);
96 struct arm_per_objfile
98 VEC(arm_mapping_symbol_s
) **section_maps
;
101 /* The list of available "set arm ..." and "show arm ..." commands. */
102 static struct cmd_list_element
*setarmcmdlist
= NULL
;
103 static struct cmd_list_element
*showarmcmdlist
= NULL
;
105 /* The type of floating-point to use. Keep this in sync with enum
106 arm_float_model, and the help string in _initialize_arm_tdep. */
107 static const char *fp_model_strings
[] =
117 /* A variable that can be configured by the user. */
118 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
119 static const char *current_fp_model
= "auto";
121 /* The ABI to use. Keep this in sync with arm_abi_kind. */
122 static const char *arm_abi_strings
[] =
130 /* A variable that can be configured by the user. */
131 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
132 static const char *arm_abi_string
= "auto";
134 /* The execution mode to assume. */
135 static const char *arm_mode_strings
[] =
142 static const char *arm_fallback_mode_string
= "auto";
143 static const char *arm_force_mode_string
= "auto";
145 /* Number of different reg name sets (options). */
146 static int num_disassembly_options
;
148 /* The standard register names, and all the valid aliases for them. */
153 } arm_register_aliases
[] = {
154 /* Basic register numbers. */
171 /* Synonyms (argument and variable registers). */
184 /* Other platform-specific names for r9. */
192 /* Names used by GCC (not listed in the ARM EABI). */
195 /* A special name from the older ATPCS. */
199 static const char *const arm_register_names
[] =
200 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
201 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
202 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
203 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
204 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
205 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
206 "fps", "cpsr" }; /* 24 25 */
208 /* Valid register name styles. */
209 static const char **valid_disassembly_styles
;
211 /* Disassembly style to use. Default to "std" register names. */
212 static const char *disassembly_style
;
214 /* This is used to keep the bfd arch_info in sync with the disassembly
216 static void set_disassembly_style_sfunc(char *, int,
217 struct cmd_list_element
*);
218 static void set_disassembly_style (void);
220 static void convert_from_extended (const struct floatformat
*, const void *,
222 static void convert_to_extended (const struct floatformat
*, void *,
225 struct arm_prologue_cache
227 /* The stack pointer at the time this frame was created; i.e. the
228 caller's stack pointer when this function was called. It is used
229 to identify this frame. */
232 /* The frame base for this frame is just prev_sp - frame size.
233 FRAMESIZE is the distance from the frame pointer to the
234 initial stack pointer. */
238 /* The register used to hold the frame pointer for this frame. */
241 /* Saved register offsets. */
242 struct trad_frame_saved_reg
*saved_regs
;
245 /* Addresses for calling Thumb functions have the bit 0 set.
246 Here are some macros to test, set, or clear bit 0 of addresses. */
247 #define IS_THUMB_ADDR(addr) ((addr) & 1)
248 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
249 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
251 /* Set to true if the 32-bit mode is in use. */
255 /* Determine if FRAME is executing in Thumb mode. */
258 arm_frame_is_thumb (struct frame_info
*frame
)
262 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
263 directly (from a signal frame or dummy frame) or by interpreting
264 the saved LR (from a prologue or DWARF frame). So consult it and
265 trust the unwinders. */
266 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
268 return (cpsr
& CPSR_T
) != 0;
271 /* Callback for VEC_lower_bound. */
274 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
275 const struct arm_mapping_symbol
*rhs
)
277 return lhs
->value
< rhs
->value
;
280 /* Determine if the program counter specified in MEMADDR is in a Thumb
281 function. This function should be called for addresses unrelated to
282 any executing frame; otherwise, prefer arm_frame_is_thumb. */
285 arm_pc_is_thumb (CORE_ADDR memaddr
)
287 struct obj_section
*sec
;
288 struct minimal_symbol
*sym
;
290 /* If bit 0 of the address is set, assume this is a Thumb address. */
291 if (IS_THUMB_ADDR (memaddr
))
294 /* If the user wants to override the symbol table, let him. */
295 if (strcmp (arm_force_mode_string
, "arm") == 0)
297 if (strcmp (arm_force_mode_string
, "thumb") == 0)
300 /* If there are mapping symbols, consult them. */
301 sec
= find_pc_section (memaddr
);
304 struct arm_per_objfile
*data
;
305 VEC(arm_mapping_symbol_s
) *map
;
306 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
310 data
= objfile_data (sec
->objfile
, arm_objfile_data_key
);
313 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
314 if (!VEC_empty (arm_mapping_symbol_s
, map
))
316 struct arm_mapping_symbol
*map_sym
;
318 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
319 arm_compare_mapping_symbols
);
321 /* VEC_lower_bound finds the earliest ordered insertion
322 point. If the following symbol starts at this exact
323 address, we use that; otherwise, the preceding
324 mapping symbol covers this address. */
325 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
327 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
328 if (map_sym
->value
== map_key
.value
)
329 return map_sym
->type
== 't';
334 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
335 return map_sym
->type
== 't';
341 /* Thumb functions have a "special" bit set in minimal symbols. */
342 sym
= lookup_minimal_symbol_by_pc (memaddr
);
344 return (MSYMBOL_IS_SPECIAL (sym
));
346 /* If the user wants to override the fallback mode, let them. */
347 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
349 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
352 /* If we couldn't find any symbol, but we're talking to a running
353 target, then trust the current value of $cpsr. This lets
354 "display/i $pc" always show the correct mode (though if there is
355 a symbol table we will not reach here, so it still may not be
356 displayed in the mode it will be executed). */
357 if (target_has_registers
)
358 return arm_frame_is_thumb (get_current_frame ());
360 /* Otherwise we're out of luck; we assume ARM. */
364 /* Remove useless bits from addresses in a running program. */
366 arm_addr_bits_remove (CORE_ADDR val
)
369 return UNMAKE_THUMB_ADDR (val
);
371 return (val
& 0x03fffffc);
374 /* When reading symbols, we need to zap the low bit of the address,
375 which may be set to 1 for Thumb functions. */
377 arm_smash_text_address (CORE_ADDR val
)
382 /* Analyze a Thumb prologue, looking for a recognizable stack frame
383 and frame pointer. Scan until we encounter a store that could
384 clobber the stack frame unexpectedly, or an unknown instruction. */
387 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
388 CORE_ADDR start
, CORE_ADDR limit
,
389 struct arm_prologue_cache
*cache
)
393 struct pv_area
*stack
;
394 struct cleanup
*back_to
;
397 for (i
= 0; i
< 16; i
++)
398 regs
[i
] = pv_register (i
, 0);
399 stack
= make_pv_area (ARM_SP_REGNUM
);
400 back_to
= make_cleanup_free_pv_area (stack
);
402 while (start
< limit
)
406 insn
= read_memory_unsigned_integer (start
, 2);
408 if (gdbarch_byte_order_for_code (gdbarch
) != gdbarch_byte_order (gdbarch
))
409 insn
= SWAP_SHORT (insn
);
411 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
416 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
419 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
420 whether to save LR (R14). */
421 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
423 /* Calculate offsets of saved R0-R7 and LR. */
424 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
425 if (mask
& (1 << regno
))
427 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
429 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
432 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
435 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
436 if (insn
& 0x80) /* Check for SUB. */
437 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
440 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
443 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
444 regs
[THUMB_FP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
446 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
448 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
449 int src_reg
= (insn
& 0x78) >> 3;
450 regs
[dst_reg
] = regs
[src_reg
];
452 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
454 /* Handle stores to the stack. Normally pushes are used,
455 but with GCC -mtpcs-frame, there may be other stores
456 in the prologue to create the frame. */
457 int regno
= (insn
>> 8) & 0x7;
460 offset
= (insn
& 0xff) << 2;
461 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
463 if (pv_area_store_would_trash (stack
, addr
))
466 pv_area_store (stack
, addr
, 4, regs
[regno
]);
470 /* We don't know what this instruction is. We're finished
471 scanning. NOTE: Recognizing more safe-to-ignore
472 instructions here will improve support for optimized
482 do_cleanups (back_to
);
486 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
488 /* Frame pointer is fp. Frame size is constant. */
489 cache
->framereg
= ARM_FP_REGNUM
;
490 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
492 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
494 /* Frame pointer is r7. Frame size is constant. */
495 cache
->framereg
= THUMB_FP_REGNUM
;
496 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
498 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
500 /* Try the stack pointer... this is a bit desperate. */
501 cache
->framereg
= ARM_SP_REGNUM
;
502 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
506 /* We're just out of luck. We don't know where the frame is. */
507 cache
->framereg
= -1;
508 cache
->framesize
= 0;
511 for (i
= 0; i
< 16; i
++)
512 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
513 cache
->saved_regs
[i
].addr
= offset
;
515 do_cleanups (back_to
);
519 /* Advance the PC across any function entry prologue instructions to
520 reach some "real" code.
522 The APCS (ARM Procedure Call Standard) defines the following
526 [stmfd sp!, {a1,a2,a3,a4}]
527 stmfd sp!, {...,fp,ip,lr,pc}
528 [stfe f7, [sp, #-12]!]
529 [stfe f6, [sp, #-12]!]
530 [stfe f5, [sp, #-12]!]
531 [stfe f4, [sp, #-12]!]
532 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
535 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
539 CORE_ADDR func_addr
, func_end
= 0;
541 struct symtab_and_line sal
;
543 /* If we're in a dummy frame, don't even try to skip the prologue. */
544 if (deprecated_pc_in_call_dummy (pc
))
547 /* See what the symbol table says. */
549 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
553 /* Found a function. */
554 sym
= lookup_symbol (func_name
, NULL
, VAR_DOMAIN
, NULL
);
555 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
557 /* Don't use this trick for assembly source files. */
558 sal
= find_pc_line (func_addr
, 0);
559 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
564 /* Can't find the prologue end in the symbol table, try it the hard way
565 by disassembling the instructions. */
567 /* Like arm_scan_prologue, stop no later than pc + 64. */
568 if (func_end
== 0 || func_end
> pc
+ 64)
571 /* Check if this is Thumb code. */
572 if (arm_pc_is_thumb (pc
))
573 return thumb_analyze_prologue (gdbarch
, pc
, func_end
, NULL
);
575 for (skip_pc
= pc
; skip_pc
< func_end
; skip_pc
+= 4)
577 inst
= read_memory_unsigned_integer (skip_pc
, 4);
579 if (gdbarch_byte_order_for_code (gdbarch
) != gdbarch_byte_order (gdbarch
))
580 inst
= SWAP_INT (inst
);
582 /* "mov ip, sp" is no longer a required part of the prologue. */
583 if (inst
== 0xe1a0c00d) /* mov ip, sp */
586 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
589 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
592 /* Some prologues begin with "str lr, [sp, #-4]!". */
593 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
596 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
599 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
602 /* Any insns after this point may float into the code, if it makes
603 for better instruction scheduling, so we skip them only if we
604 find them, but still consider the function to be frame-ful. */
606 /* We may have either one sfmfd instruction here, or several stfe
607 insns, depending on the version of floating point code we
609 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
612 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
615 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
618 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
621 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
622 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
623 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
626 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
627 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
628 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
631 /* Un-recognized instruction; stop scanning. */
635 return skip_pc
; /* End of prologue */
639 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
640 This function decodes a Thumb function prologue to determine:
641 1) the size of the stack frame
642 2) which registers are saved on it
643 3) the offsets of saved regs
644 4) the offset from the stack pointer to the frame pointer
646 A typical Thumb function prologue would create this stack frame
647 (offsets relative to FP)
648 old SP -> 24 stack parameters
651 R7 -> 0 local variables (16 bytes)
652 SP -> -12 additional stack space (12 bytes)
653 The frame size would thus be 36 bytes, and the frame offset would be
654 12 bytes. The frame register is R7.
656 The comments for thumb_skip_prolog() describe the algorithm we use
657 to detect the end of the prolog. */
661 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
662 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
664 CORE_ADDR prologue_start
;
665 CORE_ADDR prologue_end
;
666 CORE_ADDR current_pc
;
668 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
671 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
673 if (sal
.line
== 0) /* no line info, use current PC */
674 prologue_end
= prev_pc
;
675 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
676 prologue_end
= sal
.end
; /* (probably means no prologue) */
679 /* We're in the boondocks: we have no idea where the start of the
683 prologue_end
= min (prologue_end
, prev_pc
);
685 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
688 /* This function decodes an ARM function prologue to determine:
689 1) the size of the stack frame
690 2) which registers are saved on it
691 3) the offsets of saved regs
692 4) the offset from the stack pointer to the frame pointer
693 This information is stored in the "extra" fields of the frame_info.
695 There are two basic forms for the ARM prologue. The fixed argument
696 function call will look like:
699 stmfd sp!, {fp, ip, lr, pc}
703 Which would create this stack frame (offsets relative to FP):
704 IP -> 4 (caller's stack)
705 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
706 -4 LR (return address in caller)
707 -8 IP (copy of caller's SP)
709 SP -> -28 Local variables
711 The frame size would thus be 32 bytes, and the frame offset would be
712 28 bytes. The stmfd call can also save any of the vN registers it
713 plans to use, which increases the frame size accordingly.
715 Note: The stored PC is 8 off of the STMFD instruction that stored it
716 because the ARM Store instructions always store PC + 8 when you read
719 A variable argument function call will look like:
722 stmfd sp!, {a1, a2, a3, a4}
723 stmfd sp!, {fp, ip, lr, pc}
726 Which would create this stack frame (offsets relative to FP):
727 IP -> 20 (caller's stack)
732 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
733 -4 LR (return address in caller)
734 -8 IP (copy of caller's SP)
736 SP -> -28 Local variables
738 The frame size would thus be 48 bytes, and the frame offset would be
741 There is another potential complication, which is that the optimizer
742 will try to separate the store of fp in the "stmfd" instruction from
743 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
744 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
746 Also, note, the original version of the ARM toolchain claimed that there
749 instruction at the end of the prologue. I have never seen GCC produce
750 this, and the ARM docs don't mention it. We still test for it below in
756 arm_scan_prologue (struct frame_info
*this_frame
,
757 struct arm_prologue_cache
*cache
)
759 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
761 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
762 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
763 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
764 pv_t regs
[ARM_FPS_REGNUM
];
765 struct pv_area
*stack
;
766 struct cleanup
*back_to
;
769 /* Assume there is no frame until proven otherwise. */
770 cache
->framereg
= ARM_SP_REGNUM
;
771 cache
->framesize
= 0;
773 /* Check for Thumb prologue. */
774 if (arm_frame_is_thumb (this_frame
))
776 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
780 /* Find the function prologue. If we can't find the function in
781 the symbol table, peek in the stack frame to find the PC. */
782 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
785 /* One way to find the end of the prologue (which works well
786 for unoptimized code) is to do the following:
788 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
791 prologue_end = prev_pc;
792 else if (sal.end < prologue_end)
793 prologue_end = sal.end;
795 This mechanism is very accurate so long as the optimizer
796 doesn't move any instructions from the function body into the
797 prologue. If this happens, sal.end will be the last
798 instruction in the first hunk of prologue code just before
799 the first instruction that the scheduler has moved from
800 the body to the prologue.
802 In order to make sure that we scan all of the prologue
803 instructions, we use a slightly less accurate mechanism which
804 may scan more than necessary. To help compensate for this
805 lack of accuracy, the prologue scanning loop below contains
806 several clauses which'll cause the loop to terminate early if
807 an implausible prologue instruction is encountered.
813 is a suitable endpoint since it accounts for the largest
814 possible prologue plus up to five instructions inserted by
817 if (prologue_end
> prologue_start
+ 64)
819 prologue_end
= prologue_start
+ 64; /* See above. */
824 /* We have no symbol information. Our only option is to assume this
825 function has a standard stack frame and the normal frame register.
826 Then, we can find the value of our frame pointer on entrance to
827 the callee (or at the present moment if this is the innermost frame).
828 The value stored there should be the address of the stmfd + 8. */
830 LONGEST return_value
;
832 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
833 if (!safe_read_memory_integer (frame_loc
, 4, &return_value
))
837 prologue_start
= gdbarch_addr_bits_remove
838 (gdbarch
, return_value
) - 8;
839 prologue_end
= prologue_start
+ 64; /* See above. */
843 if (prev_pc
< prologue_end
)
844 prologue_end
= prev_pc
;
846 /* Now search the prologue looking for instructions that set up the
847 frame pointer, adjust the stack pointer, and save registers.
849 Be careful, however, and if it doesn't look like a prologue,
850 don't try to scan it. If, for instance, a frameless function
851 begins with stmfd sp!, then we will tell ourselves there is
852 a frame, which will confuse stack traceback, as well as "finish"
853 and other operations that rely on a knowledge of the stack
856 In the APCS, the prologue should start with "mov ip, sp" so
857 if we don't see this as the first insn, we will stop.
859 [Note: This doesn't seem to be true any longer, so it's now an
860 optional part of the prologue. - Kevin Buettner, 2001-11-20]
862 [Note further: The "mov ip,sp" only seems to be missing in
863 frameless functions at optimization level "-O2" or above,
864 in which case it is often (but not always) replaced by
865 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
867 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
868 regs
[regno
] = pv_register (regno
, 0);
869 stack
= make_pv_area (ARM_SP_REGNUM
);
870 back_to
= make_cleanup_free_pv_area (stack
);
872 for (current_pc
= prologue_start
;
873 current_pc
< prologue_end
;
876 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
878 if (gdbarch_byte_order_for_code (gdbarch
) != gdbarch_byte_order (gdbarch
))
879 insn
= SWAP_INT (insn
);
881 if (insn
== 0xe1a0c00d) /* mov ip, sp */
883 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
886 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
888 unsigned imm
= insn
& 0xff; /* immediate value */
889 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
890 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
891 regs
[ARM_IP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], imm
);
894 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
896 unsigned imm
= insn
& 0xff; /* immediate value */
897 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
898 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
899 regs
[ARM_IP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
902 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
904 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
906 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
907 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[ARM_LR_REGNUM
]);
910 else if ((insn
& 0xffff0000) == 0xe92d0000)
911 /* stmfd sp!, {..., fp, ip, lr, pc}
913 stmfd sp!, {a1, a2, a3, a4} */
915 int mask
= insn
& 0xffff;
917 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
920 /* Calculate offsets of saved registers. */
921 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
922 if (mask
& (1 << regno
))
924 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
925 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
928 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
929 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
930 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
932 /* No need to add this to saved_regs -- it's just an arg reg. */
935 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
936 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
937 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
939 /* No need to add this to saved_regs -- it's just an arg reg. */
942 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
944 unsigned imm
= insn
& 0xff; /* immediate value */
945 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
946 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
947 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
949 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
951 unsigned imm
= insn
& 0xff; /* immediate value */
952 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
953 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
954 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
956 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
957 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
959 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
962 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
963 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
964 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
966 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
967 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
970 unsigned int fp_start_reg
, fp_bound_reg
;
972 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
975 if ((insn
& 0x800) == 0x800) /* N0 is set */
977 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
984 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
990 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
991 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
992 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
994 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
995 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
996 regs
[fp_start_reg
++]);
999 else if ((insn
& 0xf0000000) != 0xe0000000)
1000 break; /* Condition not true, exit early */
1001 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
1002 break; /* Don't scan past a block load */
1004 /* The optimizer might shove anything into the prologue,
1005 so we just skip what we don't recognize. */
1009 /* The frame size is just the distance from the frame register
1010 to the original stack pointer. */
1011 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1013 /* Frame pointer is fp. */
1014 cache
->framereg
= ARM_FP_REGNUM
;
1015 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1017 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
1019 /* Try the stack pointer... this is a bit desperate. */
1020 cache
->framereg
= ARM_SP_REGNUM
;
1021 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1025 /* We're just out of luck. We don't know where the frame is. */
1026 cache
->framereg
= -1;
1027 cache
->framesize
= 0;
1030 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1031 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1032 cache
->saved_regs
[regno
].addr
= offset
;
1034 do_cleanups (back_to
);
1037 static struct arm_prologue_cache
*
1038 arm_make_prologue_cache (struct frame_info
*this_frame
)
1041 struct arm_prologue_cache
*cache
;
1042 CORE_ADDR unwound_fp
;
1044 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1045 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1047 arm_scan_prologue (this_frame
, cache
);
1049 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
1050 if (unwound_fp
== 0)
1053 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
1055 /* Calculate actual addresses of saved registers using offsets
1056 determined by arm_scan_prologue. */
1057 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
1058 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
1059 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
1064 /* Our frame ID for a normal frame is the current function's starting PC
1065 and the caller's SP when we were called. */
1068 arm_prologue_this_id (struct frame_info
*this_frame
,
1070 struct frame_id
*this_id
)
1072 struct arm_prologue_cache
*cache
;
1076 if (*this_cache
== NULL
)
1077 *this_cache
= arm_make_prologue_cache (this_frame
);
1078 cache
= *this_cache
;
1080 /* This is meant to halt the backtrace at "_start". */
1081 pc
= get_frame_pc (this_frame
);
1082 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1085 /* If we've hit a wall, stop. */
1086 if (cache
->prev_sp
== 0)
1089 func
= get_frame_func (this_frame
);
1090 id
= frame_id_build (cache
->prev_sp
, func
);
1094 static struct value
*
1095 arm_prologue_prev_register (struct frame_info
*this_frame
,
1099 struct arm_prologue_cache
*cache
;
1101 if (*this_cache
== NULL
)
1102 *this_cache
= arm_make_prologue_cache (this_frame
);
1103 cache
= *this_cache
;
1105 /* If we are asked to unwind the PC, then we need to return the LR
1106 instead. The prologue may save PC, but it will point into this
1107 frame's prologue, not the next frame's resume location. Also
1108 strip the saved T bit. A valid LR may have the low bit set, but
1109 a valid PC never does. */
1110 if (prev_regnum
== ARM_PC_REGNUM
)
1114 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1115 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1116 arm_addr_bits_remove (lr
));
1119 /* SP is generally not saved to the stack, but this frame is
1120 identified by the next frame's stack pointer at the time of the call.
1121 The value was already reconstructed into PREV_SP. */
1122 if (prev_regnum
== ARM_SP_REGNUM
)
1123 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1125 /* The CPSR may have been changed by the call instruction and by the
1126 called function. The only bit we can reconstruct is the T bit,
1127 by checking the low bit of LR as of the call. This is a reliable
1128 indicator of Thumb-ness except for some ARM v4T pre-interworking
1129 Thumb code, which could get away with a clear low bit as long as
1130 the called function did not use bx. Guess that all other
1131 bits are unchanged; the condition flags are presumably lost,
1132 but the processor status is likely valid. */
1133 if (prev_regnum
== ARM_PS_REGNUM
)
1137 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1138 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1139 if (IS_THUMB_ADDR (lr
))
1143 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1146 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1150 struct frame_unwind arm_prologue_unwind
= {
1152 arm_prologue_this_id
,
1153 arm_prologue_prev_register
,
1155 default_frame_sniffer
1158 static struct arm_prologue_cache
*
1159 arm_make_stub_cache (struct frame_info
*this_frame
)
1162 struct arm_prologue_cache
*cache
;
1163 CORE_ADDR unwound_fp
;
1165 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1166 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1168 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1173 /* Our frame ID for a stub frame is the current SP and LR. */
1176 arm_stub_this_id (struct frame_info
*this_frame
,
1178 struct frame_id
*this_id
)
1180 struct arm_prologue_cache
*cache
;
1182 if (*this_cache
== NULL
)
1183 *this_cache
= arm_make_stub_cache (this_frame
);
1184 cache
= *this_cache
;
1186 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
1190 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
1191 struct frame_info
*this_frame
,
1192 void **this_prologue_cache
)
1194 CORE_ADDR addr_in_block
;
1197 addr_in_block
= get_frame_address_in_block (this_frame
);
1198 if (in_plt_section (addr_in_block
, NULL
)
1199 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
1205 struct frame_unwind arm_stub_unwind
= {
1208 arm_prologue_prev_register
,
1210 arm_stub_unwind_sniffer
1214 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
1216 struct arm_prologue_cache
*cache
;
1218 if (*this_cache
== NULL
)
1219 *this_cache
= arm_make_prologue_cache (this_frame
);
1220 cache
= *this_cache
;
1222 return cache
->prev_sp
- cache
->framesize
;
1225 struct frame_base arm_normal_base
= {
1226 &arm_prologue_unwind
,
1227 arm_normal_frame_base
,
1228 arm_normal_frame_base
,
1229 arm_normal_frame_base
1232 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1233 dummy frame. The frame ID's base needs to match the TOS value
1234 saved by save_dummy_frame_tos() and returned from
1235 arm_push_dummy_call, and the PC needs to match the dummy frame's
1238 static struct frame_id
1239 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1241 return frame_id_build (get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
),
1242 get_frame_pc (this_frame
));
1245 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1246 be used to construct the previous frame's ID, after looking up the
1247 containing function). */
1250 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1253 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1254 return arm_addr_bits_remove (pc
);
1258 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1260 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1263 static struct value
*
1264 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1272 /* The PC is normally copied from the return column, which
1273 describes saves of LR. However, that version may have an
1274 extra bit set to indicate Thumb state. The bit is not
1276 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1277 return frame_unwind_got_constant (this_frame
, regnum
,
1278 arm_addr_bits_remove (lr
));
1281 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
1282 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
1283 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1284 if (IS_THUMB_ADDR (lr
))
1288 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
1291 internal_error (__FILE__
, __LINE__
,
1292 _("Unexpected register %d"), regnum
);
1297 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1298 struct dwarf2_frame_state_reg
*reg
,
1299 struct frame_info
*this_frame
)
1305 reg
->how
= DWARF2_FRAME_REG_FN
;
1306 reg
->loc
.fn
= arm_dwarf2_prev_register
;
1309 reg
->how
= DWARF2_FRAME_REG_CFA
;
1314 /* When arguments must be pushed onto the stack, they go on in reverse
1315 order. The code below implements a FILO (stack) to do this. */
1320 struct stack_item
*prev
;
1324 static struct stack_item
*
1325 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1327 struct stack_item
*si
;
1328 si
= xmalloc (sizeof (struct stack_item
));
1329 si
->data
= xmalloc (len
);
1332 memcpy (si
->data
, contents
, len
);
1336 static struct stack_item
*
1337 pop_stack_item (struct stack_item
*si
)
1339 struct stack_item
*dead
= si
;
1347 /* Return the alignment (in bytes) of the given type. */
1350 arm_type_align (struct type
*t
)
1356 t
= check_typedef (t
);
1357 switch (TYPE_CODE (t
))
1360 /* Should never happen. */
1361 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1365 case TYPE_CODE_ENUM
:
1369 case TYPE_CODE_RANGE
:
1370 case TYPE_CODE_BITSTRING
:
1372 case TYPE_CODE_CHAR
:
1373 case TYPE_CODE_BOOL
:
1374 return TYPE_LENGTH (t
);
1376 case TYPE_CODE_ARRAY
:
1377 case TYPE_CODE_COMPLEX
:
1378 /* TODO: What about vector types? */
1379 return arm_type_align (TYPE_TARGET_TYPE (t
));
1381 case TYPE_CODE_STRUCT
:
1382 case TYPE_CODE_UNION
:
1384 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1386 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
1394 /* We currently only support passing parameters in integer registers. This
1395 conforms with GCC's default model. Several other variants exist and
1396 we should probably support some of them based on the selected ABI. */
1399 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1400 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1401 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1402 CORE_ADDR struct_addr
)
1407 struct stack_item
*si
= NULL
;
1409 /* Set the return address. For the ARM, the return breakpoint is
1410 always at BP_ADDR. */
1411 /* XXX Fix for Thumb. */
1412 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1414 /* Walk through the list of args and determine how large a temporary
1415 stack is required. Need to take care here as structs may be
1416 passed on the stack, and we have to to push them. */
1419 argreg
= ARM_A1_REGNUM
;
1422 /* The struct_return pointer occupies the first parameter
1423 passing register. */
1427 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = 0x%s\n",
1428 gdbarch_register_name (gdbarch
, argreg
),
1429 paddr (struct_addr
));
1430 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1434 for (argnum
= 0; argnum
< nargs
; argnum
++)
1437 struct type
*arg_type
;
1438 struct type
*target_type
;
1439 enum type_code typecode
;
1443 arg_type
= check_typedef (value_type (args
[argnum
]));
1444 len
= TYPE_LENGTH (arg_type
);
1445 target_type
= TYPE_TARGET_TYPE (arg_type
);
1446 typecode
= TYPE_CODE (arg_type
);
1447 val
= value_contents_writeable (args
[argnum
]);
1449 align
= arm_type_align (arg_type
);
1450 /* Round alignment up to a whole number of words. */
1451 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
1452 /* Different ABIs have different maximum alignments. */
1453 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
1455 /* The APCS ABI only requires word alignment. */
1456 align
= INT_REGISTER_SIZE
;
1460 /* The AAPCS requires at most doubleword alignment. */
1461 if (align
> INT_REGISTER_SIZE
* 2)
1462 align
= INT_REGISTER_SIZE
* 2;
1465 /* Push stack padding for dowubleword alignment. */
1466 if (nstack
& (align
- 1))
1468 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1469 nstack
+= INT_REGISTER_SIZE
;
1472 /* Doubleword aligned quantities must go in even register pairs. */
1473 if (argreg
<= ARM_LAST_ARG_REGNUM
1474 && align
> INT_REGISTER_SIZE
1478 /* If the argument is a pointer to a function, and it is a
1479 Thumb function, create a LOCAL copy of the value and set
1480 the THUMB bit in it. */
1481 if (TYPE_CODE_PTR
== typecode
1482 && target_type
!= NULL
1483 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1485 CORE_ADDR regval
= extract_unsigned_integer (val
, len
);
1486 if (arm_pc_is_thumb (regval
))
1489 store_unsigned_integer (val
, len
, MAKE_THUMB_ADDR (regval
));
1493 /* Copy the argument to general registers or the stack in
1494 register-sized pieces. Large arguments are split between
1495 registers and stack. */
1498 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
1500 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1502 /* The argument is being passed in a general purpose
1504 CORE_ADDR regval
= extract_unsigned_integer (val
, partial_len
);
1505 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1506 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
1508 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1510 gdbarch_register_name
1512 phex (regval
, INT_REGISTER_SIZE
));
1513 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1518 /* Push the arguments onto the stack. */
1520 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1522 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1523 nstack
+= INT_REGISTER_SIZE
;
1530 /* If we have an odd number of words to push, then decrement the stack
1531 by one word now, so first stack argument will be dword aligned. */
1538 write_memory (sp
, si
->data
, si
->len
);
1539 si
= pop_stack_item (si
);
1542 /* Finally, update teh SP register. */
1543 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1549 /* Always align the frame to an 8-byte boundary. This is required on
1550 some platforms and harmless on the rest. */
1553 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1555 /* Align the stack to eight bytes. */
1556 return sp
& ~ (CORE_ADDR
) 7;
1560 print_fpu_flags (int flags
)
1562 if (flags
& (1 << 0))
1563 fputs ("IVO ", stdout
);
1564 if (flags
& (1 << 1))
1565 fputs ("DVZ ", stdout
);
1566 if (flags
& (1 << 2))
1567 fputs ("OFL ", stdout
);
1568 if (flags
& (1 << 3))
1569 fputs ("UFL ", stdout
);
1570 if (flags
& (1 << 4))
1571 fputs ("INX ", stdout
);
1575 /* Print interesting information about the floating point processor
1576 (if present) or emulator. */
1578 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1579 struct frame_info
*frame
, const char *args
)
1581 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
1584 type
= (status
>> 24) & 127;
1585 if (status
& (1 << 31))
1586 printf (_("Hardware FPU type %d\n"), type
);
1588 printf (_("Software FPU type %d\n"), type
);
1589 /* i18n: [floating point unit] mask */
1590 fputs (_("mask: "), stdout
);
1591 print_fpu_flags (status
>> 16);
1592 /* i18n: [floating point unit] flags */
1593 fputs (_("flags: "), stdout
);
1594 print_fpu_flags (status
);
1597 /* Return the GDB type object for the "standard" data type of data in
1600 static struct type
*
1601 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
1603 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1604 return builtin_type_arm_ext
;
1605 else if (regnum
== ARM_SP_REGNUM
)
1606 return builtin_type_void_data_ptr
;
1607 else if (regnum
== ARM_PC_REGNUM
)
1608 return builtin_type_void_func_ptr
;
1609 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
1610 /* These registers are only supported on targets which supply
1611 an XML description. */
1612 return builtin_type_int0
;
1614 return builtin_type_uint32
;
1617 /* Map a DWARF register REGNUM onto the appropriate GDB register
1621 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
1623 /* Core integer regs. */
1624 if (reg
>= 0 && reg
<= 15)
1627 /* Legacy FPA encoding. These were once used in a way which
1628 overlapped with VFP register numbering, so their use is
1629 discouraged, but GDB doesn't support the ARM toolchain
1630 which used them for VFP. */
1631 if (reg
>= 16 && reg
<= 23)
1632 return ARM_F0_REGNUM
+ reg
- 16;
1634 /* New assignments for the FPA registers. */
1635 if (reg
>= 96 && reg
<= 103)
1636 return ARM_F0_REGNUM
+ reg
- 96;
1638 /* WMMX register assignments. */
1639 if (reg
>= 104 && reg
<= 111)
1640 return ARM_WCGR0_REGNUM
+ reg
- 104;
1642 if (reg
>= 112 && reg
<= 127)
1643 return ARM_WR0_REGNUM
+ reg
- 112;
1645 if (reg
>= 192 && reg
<= 199)
1646 return ARM_WC0_REGNUM
+ reg
- 192;
1651 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1653 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
1656 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
1658 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
1659 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
1661 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
1662 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
1664 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
1665 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
1667 if (reg
< NUM_GREGS
)
1668 return SIM_ARM_R0_REGNUM
+ reg
;
1671 if (reg
< NUM_FREGS
)
1672 return SIM_ARM_FP0_REGNUM
+ reg
;
1675 if (reg
< NUM_SREGS
)
1676 return SIM_ARM_FPS_REGNUM
+ reg
;
1679 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
1682 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1683 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1684 It is thought that this is is the floating-point register format on
1685 little-endian systems. */
1688 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
1689 void *dbl
, int endianess
)
1693 if (endianess
== BFD_ENDIAN_BIG
)
1694 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1696 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1698 floatformat_from_doublest (fmt
, &d
, dbl
);
1702 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
1707 floatformat_to_doublest (fmt
, ptr
, &d
);
1708 if (endianess
== BFD_ENDIAN_BIG
)
1709 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1711 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1716 condition_true (unsigned long cond
, unsigned long status_reg
)
1718 if (cond
== INST_AL
|| cond
== INST_NV
)
1724 return ((status_reg
& FLAG_Z
) != 0);
1726 return ((status_reg
& FLAG_Z
) == 0);
1728 return ((status_reg
& FLAG_C
) != 0);
1730 return ((status_reg
& FLAG_C
) == 0);
1732 return ((status_reg
& FLAG_N
) != 0);
1734 return ((status_reg
& FLAG_N
) == 0);
1736 return ((status_reg
& FLAG_V
) != 0);
1738 return ((status_reg
& FLAG_V
) == 0);
1740 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1742 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1744 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1746 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1748 return (((status_reg
& FLAG_Z
) == 0) &&
1749 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1751 return (((status_reg
& FLAG_Z
) != 0) ||
1752 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1757 /* Support routines for single stepping. Calculate the next PC value. */
1758 #define submask(x) ((1L << ((x) + 1)) - 1)
1759 #define bit(obj,st) (((obj) >> (st)) & 1)
1760 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1761 #define sbits(obj,st,fn) \
1762 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1763 #define BranchDest(addr,instr) \
1764 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1767 static unsigned long
1768 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
1769 unsigned long pc_val
, unsigned long status_reg
)
1771 unsigned long res
, shift
;
1772 int rm
= bits (inst
, 0, 3);
1773 unsigned long shifttype
= bits (inst
, 5, 6);
1777 int rs
= bits (inst
, 8, 11);
1778 shift
= (rs
== 15 ? pc_val
+ 8
1779 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
1782 shift
= bits (inst
, 7, 11);
1785 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1786 + (bit (inst
, 4) ? 12 : 8))
1787 : get_frame_register_unsigned (frame
, rm
));
1792 res
= shift
>= 32 ? 0 : res
<< shift
;
1796 res
= shift
>= 32 ? 0 : res
>> shift
;
1802 res
= ((res
& 0x80000000L
)
1803 ? ~((~res
) >> shift
) : res
>> shift
);
1806 case 3: /* ROR/RRX */
1809 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1811 res
= (res
>> shift
) | (res
<< (32 - shift
));
1815 return res
& 0xffffffff;
1818 /* Return number of 1-bits in VAL. */
1821 bitcount (unsigned long val
)
1824 for (nbits
= 0; val
!= 0; nbits
++)
1825 val
&= val
- 1; /* delete rightmost 1-bit in val */
1830 thumb_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1832 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1833 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1834 unsigned short inst1
= read_memory_unsigned_integer (pc
, 2);
1835 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1836 unsigned long offset
;
1838 if (gdbarch_byte_order_for_code (gdbarch
) != gdbarch_byte_order (gdbarch
))
1839 inst1
= SWAP_SHORT (inst1
);
1841 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1845 /* Fetch the saved PC from the stack. It's stored above
1846 all of the other registers. */
1847 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
1848 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
1849 nextpc
= (CORE_ADDR
) read_memory_unsigned_integer (sp
+ offset
, 4);
1850 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1852 error (_("Infinite loop detected"));
1854 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1856 unsigned long status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
1857 unsigned long cond
= bits (inst1
, 8, 11);
1858 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1859 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1861 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1863 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1865 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link, and blx */
1867 unsigned short inst2
= read_memory_unsigned_integer (pc
+ 2, 2);
1868 if (gdbarch_byte_order_for_code (gdbarch
) != gdbarch_byte_order (gdbarch
))
1869 inst2
= SWAP_SHORT (inst2
);
1870 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1871 nextpc
= pc_val
+ offset
;
1872 /* For BLX make sure to clear the low bits. */
1873 if (bits (inst2
, 11, 12) == 1)
1874 nextpc
= nextpc
& 0xfffffffc;
1876 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
1878 if (bits (inst1
, 3, 6) == 0x0f)
1881 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
1883 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1885 error (_("Infinite loop detected"));
1892 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1894 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1895 unsigned long pc_val
;
1896 unsigned long this_instr
;
1897 unsigned long status
;
1900 if (arm_frame_is_thumb (frame
))
1901 return thumb_get_next_pc (frame
, pc
);
1903 pc_val
= (unsigned long) pc
;
1904 this_instr
= read_memory_unsigned_integer (pc
, 4);
1906 if (gdbarch_byte_order_for_code (gdbarch
) != gdbarch_byte_order (gdbarch
))
1907 this_instr
= SWAP_INT (this_instr
);
1909 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
1910 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1912 if (bits (this_instr
, 28, 31) == INST_NV
)
1913 switch (bits (this_instr
, 24, 27))
1918 /* Branch with Link and change to Thumb. */
1919 nextpc
= BranchDest (pc
, this_instr
);
1920 nextpc
|= bit (this_instr
, 24) << 1;
1922 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1924 error (_("Infinite loop detected"));
1930 /* Coprocessor register transfer. */
1931 if (bits (this_instr
, 12, 15) == 15)
1932 error (_("Invalid update to pc in instruction"));
1935 else if (condition_true (bits (this_instr
, 28, 31), status
))
1937 switch (bits (this_instr
, 24, 27))
1940 case 0x1: /* data processing */
1944 unsigned long operand1
, operand2
, result
= 0;
1948 if (bits (this_instr
, 12, 15) != 15)
1951 if (bits (this_instr
, 22, 25) == 0
1952 && bits (this_instr
, 4, 7) == 9) /* multiply */
1953 error (_("Invalid update to pc in instruction"));
1955 /* BX <reg>, BLX <reg> */
1956 if (bits (this_instr
, 4, 27) == 0x12fff1
1957 || bits (this_instr
, 4, 27) == 0x12fff3)
1959 rn
= bits (this_instr
, 0, 3);
1960 result
= (rn
== 15) ? pc_val
+ 8
1961 : get_frame_register_unsigned (frame
, rn
);
1962 nextpc
= (CORE_ADDR
) gdbarch_addr_bits_remove
1966 error (_("Infinite loop detected"));
1971 /* Multiply into PC */
1972 c
= (status
& FLAG_C
) ? 1 : 0;
1973 rn
= bits (this_instr
, 16, 19);
1974 operand1
= (rn
== 15) ? pc_val
+ 8
1975 : get_frame_register_unsigned (frame
, rn
);
1977 if (bit (this_instr
, 25))
1979 unsigned long immval
= bits (this_instr
, 0, 7);
1980 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1981 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1984 else /* operand 2 is a shifted register */
1985 operand2
= shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
);
1987 switch (bits (this_instr
, 21, 24))
1990 result
= operand1
& operand2
;
1994 result
= operand1
^ operand2
;
1998 result
= operand1
- operand2
;
2002 result
= operand2
- operand1
;
2006 result
= operand1
+ operand2
;
2010 result
= operand1
+ operand2
+ c
;
2014 result
= operand1
- operand2
+ c
;
2018 result
= operand2
- operand1
+ c
;
2024 case 0xb: /* tst, teq, cmp, cmn */
2025 result
= (unsigned long) nextpc
;
2029 result
= operand1
| operand2
;
2033 /* Always step into a function. */
2038 result
= operand1
& ~operand2
;
2045 nextpc
= (CORE_ADDR
) gdbarch_addr_bits_remove
2049 error (_("Infinite loop detected"));
2054 case 0x5: /* data transfer */
2057 if (bit (this_instr
, 20))
2060 if (bits (this_instr
, 12, 15) == 15)
2066 if (bit (this_instr
, 22))
2067 error (_("Invalid update to pc in instruction"));
2069 /* byte write to PC */
2070 rn
= bits (this_instr
, 16, 19);
2071 base
= (rn
== 15) ? pc_val
+ 8
2072 : get_frame_register_unsigned (frame
, rn
);
2073 if (bit (this_instr
, 24))
2076 int c
= (status
& FLAG_C
) ? 1 : 0;
2077 unsigned long offset
=
2078 (bit (this_instr
, 25)
2079 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
2080 : bits (this_instr
, 0, 11));
2082 if (bit (this_instr
, 23))
2087 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
2090 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
2093 error (_("Infinite loop detected"));
2099 case 0x9: /* block transfer */
2100 if (bit (this_instr
, 20))
2103 if (bit (this_instr
, 15))
2108 if (bit (this_instr
, 23))
2111 unsigned long reglist
= bits (this_instr
, 0, 14);
2112 offset
= bitcount (reglist
) * 4;
2113 if (bit (this_instr
, 24)) /* pre */
2116 else if (bit (this_instr
, 24))
2120 unsigned long rn_val
=
2121 get_frame_register_unsigned (frame
,
2122 bits (this_instr
, 16, 19));
2124 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
2128 nextpc
= gdbarch_addr_bits_remove
2131 error (_("Infinite loop detected"));
2136 case 0xb: /* branch & link */
2137 case 0xa: /* branch */
2139 nextpc
= BranchDest (pc
, this_instr
);
2141 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
2143 error (_("Infinite loop detected"));
2149 case 0xe: /* coproc ops */
2154 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
2162 /* single_step() is called just before we want to resume the inferior,
2163 if we want to single-step it but there is no hardware or kernel
2164 single-step support. We find the target of the coming instruction
2165 and breakpoint it. */
2168 arm_software_single_step (struct frame_info
*frame
)
2170 /* NOTE: This may insert the wrong breakpoint instruction when
2171 single-stepping over a mode-changing instruction, if the
2172 CPSR heuristics are used. */
2174 CORE_ADDR next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
2175 insert_single_step_breakpoint (next_pc
);
2180 #include "bfd-in2.h"
2181 #include "libcoff.h"
2184 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
2186 if (arm_pc_is_thumb (memaddr
))
2188 static asymbol
*asym
;
2189 static combined_entry_type ce
;
2190 static struct coff_symbol_struct csym
;
2191 static struct bfd fake_bfd
;
2192 static bfd_target fake_target
;
2194 if (csym
.native
== NULL
)
2196 /* Create a fake symbol vector containing a Thumb symbol.
2197 This is solely so that the code in print_insn_little_arm()
2198 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2199 the presence of a Thumb symbol and switch to decoding
2200 Thumb instructions. */
2202 fake_target
.flavour
= bfd_target_coff_flavour
;
2203 fake_bfd
.xvec
= &fake_target
;
2204 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
2206 csym
.symbol
.the_bfd
= &fake_bfd
;
2207 csym
.symbol
.name
= "fake";
2208 asym
= (asymbol
*) & csym
;
2211 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
2212 info
->symbols
= &asym
;
2215 info
->symbols
= NULL
;
2217 if (info
->endian
== BFD_ENDIAN_BIG
)
2218 return print_insn_big_arm (memaddr
, info
);
2220 return print_insn_little_arm (memaddr
, info
);
2223 /* The following define instruction sequences that will cause ARM
2224 cpu's to take an undefined instruction trap. These are used to
2225 signal a breakpoint to GDB.
2227 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2228 modes. A different instruction is required for each mode. The ARM
2229 cpu's can also be big or little endian. Thus four different
2230 instructions are needed to support all cases.
2232 Note: ARMv4 defines several new instructions that will take the
2233 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2234 not in fact add the new instructions. The new undefined
2235 instructions in ARMv4 are all instructions that had no defined
2236 behaviour in earlier chips. There is no guarantee that they will
2237 raise an exception, but may be treated as NOP's. In practice, it
2238 may only safe to rely on instructions matching:
2240 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2241 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2242 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2244 Even this may only true if the condition predicate is true. The
2245 following use a condition predicate of ALWAYS so it is always TRUE.
2247 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2248 and NetBSD all use a software interrupt rather than an undefined
2249 instruction to force a trap. This can be handled by by the
2250 abi-specific code during establishment of the gdbarch vector. */
2252 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2253 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2254 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
2255 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
2257 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
2258 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
2259 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2260 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2262 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2263 the program counter value to determine whether a 16-bit or 32-bit
2264 breakpoint should be used. It returns a pointer to a string of
2265 bytes that encode a breakpoint instruction, stores the length of
2266 the string to *lenptr, and adjusts the program counter (if
2267 necessary) to point to the actual memory location where the
2268 breakpoint should be inserted. */
2270 static const unsigned char *
2271 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
2273 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2275 if (arm_pc_is_thumb (*pcptr
))
2277 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2278 *lenptr
= tdep
->thumb_breakpoint_size
;
2279 return tdep
->thumb_breakpoint
;
2283 *lenptr
= tdep
->arm_breakpoint_size
;
2284 return tdep
->arm_breakpoint
;
2288 /* Extract from an array REGBUF containing the (raw) register state a
2289 function return value of type TYPE, and copy that, in virtual
2290 format, into VALBUF. */
2293 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
2296 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
2298 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2300 switch (gdbarch_tdep (gdbarch
)->fp_model
)
2304 /* The value is in register F0 in internal format. We need to
2305 extract the raw value and then convert it to the desired
2307 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
2309 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
2310 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
2311 valbuf
, gdbarch_byte_order (gdbarch
));
2315 case ARM_FLOAT_SOFT_FPA
:
2316 case ARM_FLOAT_SOFT_VFP
:
2317 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
2318 if (TYPE_LENGTH (type
) > 4)
2319 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
2320 valbuf
+ INT_REGISTER_SIZE
);
2325 (__FILE__
, __LINE__
,
2326 _("arm_extract_return_value: Floating point model not supported"));
2330 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2331 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2332 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2333 || TYPE_CODE (type
) == TYPE_CODE_PTR
2334 || TYPE_CODE (type
) == TYPE_CODE_REF
2335 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2337 /* If the the type is a plain integer, then the access is
2338 straight-forward. Otherwise we have to play around a bit more. */
2339 int len
= TYPE_LENGTH (type
);
2340 int regno
= ARM_A1_REGNUM
;
2345 /* By using store_unsigned_integer we avoid having to do
2346 anything special for small big-endian values. */
2347 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2348 store_unsigned_integer (valbuf
,
2349 (len
> INT_REGISTER_SIZE
2350 ? INT_REGISTER_SIZE
: len
),
2352 len
-= INT_REGISTER_SIZE
;
2353 valbuf
+= INT_REGISTER_SIZE
;
2358 /* For a structure or union the behaviour is as if the value had
2359 been stored to word-aligned memory and then loaded into
2360 registers with 32-bit load instruction(s). */
2361 int len
= TYPE_LENGTH (type
);
2362 int regno
= ARM_A1_REGNUM
;
2363 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2367 regcache_cooked_read (regs
, regno
++, tmpbuf
);
2368 memcpy (valbuf
, tmpbuf
,
2369 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2370 len
-= INT_REGISTER_SIZE
;
2371 valbuf
+= INT_REGISTER_SIZE
;
2377 /* Will a function return an aggregate type in memory or in a
2378 register? Return 0 if an aggregate type can be returned in a
2379 register, 1 if it must be returned in memory. */
2382 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2385 enum type_code code
;
2387 CHECK_TYPEDEF (type
);
2389 /* In the ARM ABI, "integer" like aggregate types are returned in
2390 registers. For an aggregate type to be integer like, its size
2391 must be less than or equal to INT_REGISTER_SIZE and the
2392 offset of each addressable subfield must be zero. Note that bit
2393 fields are not addressable, and all addressable subfields of
2394 unions always start at offset zero.
2396 This function is based on the behaviour of GCC 2.95.1.
2397 See: gcc/arm.c: arm_return_in_memory() for details.
2399 Note: All versions of GCC before GCC 2.95.2 do not set up the
2400 parameters correctly for a function returning the following
2401 structure: struct { float f;}; This should be returned in memory,
2402 not a register. Richard Earnshaw sent me a patch, but I do not
2403 know of any way to detect if a function like the above has been
2404 compiled with the correct calling convention. */
2406 /* All aggregate types that won't fit in a register must be returned
2408 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
2413 /* The AAPCS says all aggregates not larger than a word are returned
2415 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
2418 /* The only aggregate types that can be returned in a register are
2419 structs and unions. Arrays must be returned in memory. */
2420 code
= TYPE_CODE (type
);
2421 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2426 /* Assume all other aggregate types can be returned in a register.
2427 Run a check for structures, unions and arrays. */
2430 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2433 /* Need to check if this struct/union is "integer" like. For
2434 this to be true, its size must be less than or equal to
2435 INT_REGISTER_SIZE and the offset of each addressable
2436 subfield must be zero. Note that bit fields are not
2437 addressable, and unions always start at offset zero. If any
2438 of the subfields is a floating point type, the struct/union
2439 cannot be an integer type. */
2441 /* For each field in the object, check:
2442 1) Is it FP? --> yes, nRc = 1;
2443 2) Is it addressable (bitpos != 0) and
2444 not packed (bitsize == 0)?
2448 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2450 enum type_code field_type_code
;
2451 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, i
)));
2453 /* Is it a floating point type field? */
2454 if (field_type_code
== TYPE_CODE_FLT
)
2460 /* If bitpos != 0, then we have to care about it. */
2461 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2463 /* Bitfields are not addressable. If the field bitsize is
2464 zero, then the field is not packed. Hence it cannot be
2465 a bitfield or any other packed type. */
2466 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2478 /* Write into appropriate registers a function return value of type
2479 TYPE, given in virtual format. */
2482 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
2483 const gdb_byte
*valbuf
)
2485 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
2487 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2489 char buf
[MAX_REGISTER_SIZE
];
2491 switch (gdbarch_tdep (gdbarch
)->fp_model
)
2495 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
2496 gdbarch_byte_order (gdbarch
));
2497 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
2500 case ARM_FLOAT_SOFT_FPA
:
2501 case ARM_FLOAT_SOFT_VFP
:
2502 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
2503 if (TYPE_LENGTH (type
) > 4)
2504 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
2505 valbuf
+ INT_REGISTER_SIZE
);
2510 (__FILE__
, __LINE__
,
2511 _("arm_store_return_value: Floating point model not supported"));
2515 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2516 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2517 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2518 || TYPE_CODE (type
) == TYPE_CODE_PTR
2519 || TYPE_CODE (type
) == TYPE_CODE_REF
2520 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2522 if (TYPE_LENGTH (type
) <= 4)
2524 /* Values of one word or less are zero/sign-extended and
2526 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2527 LONGEST val
= unpack_long (type
, valbuf
);
2529 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, val
);
2530 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
2534 /* Integral values greater than one word are stored in consecutive
2535 registers starting with r0. This will always be a multiple of
2536 the regiser size. */
2537 int len
= TYPE_LENGTH (type
);
2538 int regno
= ARM_A1_REGNUM
;
2542 regcache_cooked_write (regs
, regno
++, valbuf
);
2543 len
-= INT_REGISTER_SIZE
;
2544 valbuf
+= INT_REGISTER_SIZE
;
2550 /* For a structure or union the behaviour is as if the value had
2551 been stored to word-aligned memory and then loaded into
2552 registers with 32-bit load instruction(s). */
2553 int len
= TYPE_LENGTH (type
);
2554 int regno
= ARM_A1_REGNUM
;
2555 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2559 memcpy (tmpbuf
, valbuf
,
2560 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2561 regcache_cooked_write (regs
, regno
++, tmpbuf
);
2562 len
-= INT_REGISTER_SIZE
;
2563 valbuf
+= INT_REGISTER_SIZE
;
2569 /* Handle function return values. */
2571 static enum return_value_convention
2572 arm_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2573 struct type
*valtype
, struct regcache
*regcache
,
2574 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2576 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2578 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2579 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2580 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2582 if (tdep
->struct_return
== pcc_struct_return
2583 || arm_return_in_memory (gdbarch
, valtype
))
2584 return RETURN_VALUE_STRUCT_CONVENTION
;
2588 arm_store_return_value (valtype
, regcache
, writebuf
);
2591 arm_extract_return_value (valtype
, regcache
, readbuf
);
2593 return RETURN_VALUE_REGISTER_CONVENTION
;
2598 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2601 char buf
[INT_REGISTER_SIZE
];
2602 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (frame
));
2604 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
2606 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2610 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
);
2614 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
2615 return the target PC. Otherwise return 0. */
2618 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
2622 CORE_ADDR start_addr
;
2624 /* Find the starting address and name of the function containing the PC. */
2625 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2628 /* If PC is in a Thumb call or return stub, return the address of the
2629 target PC, which is in a register. The thunk functions are called
2630 _call_via_xx, where x is the register name. The possible names
2631 are r0-r9, sl, fp, ip, sp, and lr. */
2632 if (strncmp (name
, "_call_via_", 10) == 0)
2634 /* Use the name suffix to determine which register contains the
2636 static char *table
[15] =
2637 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2638 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2641 int offset
= strlen (name
) - 2;
2643 for (regno
= 0; regno
<= 14; regno
++)
2644 if (strcmp (&name
[offset
], table
[regno
]) == 0)
2645 return get_frame_register_unsigned (frame
, regno
);
2648 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
2649 non-interworking calls to foo. We could decode the stubs
2650 to find the target but it's easier to use the symbol table. */
2651 namelen
= strlen (name
);
2652 if (name
[0] == '_' && name
[1] == '_'
2653 && ((namelen
> 2 + strlen ("_from_thumb")
2654 && strncmp (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb",
2655 strlen ("_from_thumb")) == 0)
2656 || (namelen
> 2 + strlen ("_from_arm")
2657 && strncmp (name
+ namelen
- strlen ("_from_arm"), "_from_arm",
2658 strlen ("_from_arm")) == 0)))
2661 int target_len
= namelen
- 2;
2662 struct minimal_symbol
*minsym
;
2663 struct objfile
*objfile
;
2664 struct obj_section
*sec
;
2666 if (name
[namelen
- 1] == 'b')
2667 target_len
-= strlen ("_from_thumb");
2669 target_len
-= strlen ("_from_arm");
2671 target_name
= alloca (target_len
+ 1);
2672 memcpy (target_name
, name
+ 2, target_len
);
2673 target_name
[target_len
] = '\0';
2675 sec
= find_pc_section (pc
);
2676 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
2677 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
2679 return SYMBOL_VALUE_ADDRESS (minsym
);
2684 return 0; /* not a stub */
2688 set_arm_command (char *args
, int from_tty
)
2690 printf_unfiltered (_("\
2691 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2692 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
2696 show_arm_command (char *args
, int from_tty
)
2698 cmd_show_list (showarmcmdlist
, from_tty
, "");
2702 arm_update_current_architecture (void)
2704 struct gdbarch_info info
;
2706 /* If the current architecture is not ARM, we have nothing to do. */
2707 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_arm
)
2710 /* Update the architecture. */
2711 gdbarch_info_init (&info
);
2713 if (!gdbarch_update_p (info
))
2714 internal_error (__FILE__
, __LINE__
, "could not update architecture");
2718 set_fp_model_sfunc (char *args
, int from_tty
,
2719 struct cmd_list_element
*c
)
2721 enum arm_float_model fp_model
;
2723 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
2724 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
2726 arm_fp_model
= fp_model
;
2730 if (fp_model
== ARM_FLOAT_LAST
)
2731 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
2734 arm_update_current_architecture ();
2738 show_fp_model (struct ui_file
*file
, int from_tty
,
2739 struct cmd_list_element
*c
, const char *value
)
2741 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2743 if (arm_fp_model
== ARM_FLOAT_AUTO
2744 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2745 fprintf_filtered (file
, _("\
2746 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2747 fp_model_strings
[tdep
->fp_model
]);
2749 fprintf_filtered (file
, _("\
2750 The current ARM floating point model is \"%s\".\n"),
2751 fp_model_strings
[arm_fp_model
]);
2755 arm_set_abi (char *args
, int from_tty
,
2756 struct cmd_list_element
*c
)
2758 enum arm_abi_kind arm_abi
;
2760 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
2761 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
2763 arm_abi_global
= arm_abi
;
2767 if (arm_abi
== ARM_ABI_LAST
)
2768 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
2771 arm_update_current_architecture ();
2775 arm_show_abi (struct ui_file
*file
, int from_tty
,
2776 struct cmd_list_element
*c
, const char *value
)
2778 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2780 if (arm_abi_global
== ARM_ABI_AUTO
2781 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2782 fprintf_filtered (file
, _("\
2783 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2784 arm_abi_strings
[tdep
->arm_abi
]);
2786 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
2791 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
2792 struct cmd_list_element
*c
, const char *value
)
2794 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2796 fprintf_filtered (file
, _("\
2797 The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"),
2798 arm_fallback_mode_string
);
2802 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
2803 struct cmd_list_element
*c
, const char *value
)
2805 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2807 fprintf_filtered (file
, _("\
2808 The current execution mode assumed (even when symbols are available) is \"%s\".\n"),
2809 arm_force_mode_string
);
2812 /* If the user changes the register disassembly style used for info
2813 register and other commands, we have to also switch the style used
2814 in opcodes for disassembly output. This function is run in the "set
2815 arm disassembly" command, and does that. */
2818 set_disassembly_style_sfunc (char *args
, int from_tty
,
2819 struct cmd_list_element
*c
)
2821 set_disassembly_style ();
2824 /* Return the ARM register name corresponding to register I. */
2826 arm_register_name (struct gdbarch
*gdbarch
, int i
)
2828 if (i
>= ARRAY_SIZE (arm_register_names
))
2829 /* These registers are only supported on targets which supply
2830 an XML description. */
2833 return arm_register_names
[i
];
2837 set_disassembly_style (void)
2841 /* Find the style that the user wants. */
2842 for (current
= 0; current
< num_disassembly_options
; current
++)
2843 if (disassembly_style
== valid_disassembly_styles
[current
])
2845 gdb_assert (current
< num_disassembly_options
);
2847 /* Synchronize the disassembler. */
2848 set_arm_regname_option (current
);
2851 /* Test whether the coff symbol specific value corresponds to a Thumb
2855 coff_sym_is_thumb (int val
)
2857 return (val
== C_THUMBEXT
||
2858 val
== C_THUMBSTAT
||
2859 val
== C_THUMBEXTFUNC
||
2860 val
== C_THUMBSTATFUNC
||
2861 val
== C_THUMBLABEL
);
2864 /* arm_coff_make_msymbol_special()
2865 arm_elf_make_msymbol_special()
2867 These functions test whether the COFF or ELF symbol corresponds to
2868 an address in thumb code, and set a "special" bit in a minimal
2869 symbol to indicate that it does. */
2872 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2874 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2876 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2878 MSYMBOL_SET_SPECIAL (msym
);
2882 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2884 if (coff_sym_is_thumb (val
))
2885 MSYMBOL_SET_SPECIAL (msym
);
2889 arm_objfile_data_cleanup (struct objfile
*objfile
, void *arg
)
2891 struct arm_per_objfile
*data
= arg
;
2894 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
2895 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
2899 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
2902 const char *name
= bfd_asymbol_name (sym
);
2903 struct arm_per_objfile
*data
;
2904 VEC(arm_mapping_symbol_s
) **map_p
;
2905 struct arm_mapping_symbol new_map_sym
;
2907 gdb_assert (name
[0] == '$');
2908 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
2911 data
= objfile_data (objfile
, arm_objfile_data_key
);
2914 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
2915 struct arm_per_objfile
);
2916 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
2917 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2918 objfile
->obfd
->section_count
,
2919 VEC(arm_mapping_symbol_s
) *);
2921 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
2923 new_map_sym
.value
= sym
->value
;
2924 new_map_sym
.type
= name
[1];
2926 /* Assume that most mapping symbols appear in order of increasing
2927 value. If they were randomly distributed, it would be faster to
2928 always push here and then sort at first use. */
2929 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
2931 struct arm_mapping_symbol
*prev_map_sym
;
2933 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
2934 if (prev_map_sym
->value
>= sym
->value
)
2937 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
2938 arm_compare_mapping_symbols
);
2939 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
2944 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
2948 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2950 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
2952 /* If necessary, set the T bit. */
2956 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
2957 if (arm_pc_is_thumb (pc
))
2958 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
, val
| CPSR_T
);
2960 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
2961 val
& ~(ULONGEST
) CPSR_T
);
2965 static struct value
*
2966 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
2968 const int *reg_p
= baton
;
2969 return value_of_register (*reg_p
, frame
);
2972 static enum gdb_osabi
2973 arm_elf_osabi_sniffer (bfd
*abfd
)
2975 unsigned int elfosabi
;
2976 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2978 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2980 if (elfosabi
== ELFOSABI_ARM
)
2981 /* GNU tools use this value. Check note sections in this case,
2983 bfd_map_over_sections (abfd
,
2984 generic_elf_osabi_sniff_abi_tag_sections
,
2987 /* Anything else will be handled by the generic ELF sniffer. */
2992 /* Initialize the current architecture based on INFO. If possible,
2993 re-use an architecture from ARCHES, which is a list of
2994 architectures already created during this debugging session.
2996 Called e.g. at program startup, when reading a core file, and when
2997 reading a binary file. */
2999 static struct gdbarch
*
3000 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3002 struct gdbarch_tdep
*tdep
;
3003 struct gdbarch
*gdbarch
;
3004 struct gdbarch_list
*best_arch
;
3005 enum arm_abi_kind arm_abi
= arm_abi_global
;
3006 enum arm_float_model fp_model
= arm_fp_model
;
3007 struct tdesc_arch_data
*tdesc_data
= NULL
;
3009 int have_fpa_registers
= 1;
3011 /* Check any target description for validity. */
3012 if (tdesc_has_registers (info
.target_desc
))
3014 /* For most registers we require GDB's default names; but also allow
3015 the numeric names for sp / lr / pc, as a convenience. */
3016 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
3017 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
3018 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
3020 const struct tdesc_feature
*feature
;
3023 feature
= tdesc_find_feature (info
.target_desc
,
3024 "org.gnu.gdb.arm.core");
3025 if (feature
== NULL
)
3028 tdesc_data
= tdesc_data_alloc ();
3031 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
3032 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
3033 arm_register_names
[i
]);
3034 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
3037 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
3040 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
3043 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3044 ARM_PS_REGNUM
, "cpsr");
3048 tdesc_data_cleanup (tdesc_data
);
3052 feature
= tdesc_find_feature (info
.target_desc
,
3053 "org.gnu.gdb.arm.fpa");
3054 if (feature
!= NULL
)
3057 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
3058 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
3059 arm_register_names
[i
]);
3062 tdesc_data_cleanup (tdesc_data
);
3067 have_fpa_registers
= 0;
3069 feature
= tdesc_find_feature (info
.target_desc
,
3070 "org.gnu.gdb.xscale.iwmmxt");
3071 if (feature
!= NULL
)
3073 static const char *const iwmmxt_names
[] = {
3074 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
3075 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
3076 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
3077 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
3081 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
3083 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
3084 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
3086 /* Check for the control registers, but do not fail if they
3088 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
3089 tdesc_numbered_register (feature
, tdesc_data
, i
,
3090 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
3092 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
3094 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
3095 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
3099 tdesc_data_cleanup (tdesc_data
);
3105 /* If we have an object to base this architecture on, try to determine
3108 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
3110 int ei_osabi
, e_flags
;
3112 switch (bfd_get_flavour (info
.abfd
))
3114 case bfd_target_aout_flavour
:
3115 /* Assume it's an old APCS-style ABI. */
3116 arm_abi
= ARM_ABI_APCS
;
3119 case bfd_target_coff_flavour
:
3120 /* Assume it's an old APCS-style ABI. */
3122 arm_abi
= ARM_ABI_APCS
;
3125 case bfd_target_elf_flavour
:
3126 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
3127 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
3129 if (ei_osabi
== ELFOSABI_ARM
)
3131 /* GNU tools used to use this value, but do not for EABI
3132 objects. There's nowhere to tag an EABI version
3133 anyway, so assume APCS. */
3134 arm_abi
= ARM_ABI_APCS
;
3136 else if (ei_osabi
== ELFOSABI_NONE
)
3138 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
3142 case EF_ARM_EABI_UNKNOWN
:
3143 /* Assume GNU tools. */
3144 arm_abi
= ARM_ABI_APCS
;
3147 case EF_ARM_EABI_VER4
:
3148 case EF_ARM_EABI_VER5
:
3149 arm_abi
= ARM_ABI_AAPCS
;
3150 /* EABI binaries default to VFP float ordering. */
3151 if (fp_model
== ARM_FLOAT_AUTO
)
3152 fp_model
= ARM_FLOAT_SOFT_VFP
;
3156 /* Leave it as "auto". */
3157 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
3162 if (fp_model
== ARM_FLOAT_AUTO
)
3164 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
3166 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
3169 /* Leave it as "auto". Strictly speaking this case
3170 means FPA, but almost nobody uses that now, and
3171 many toolchains fail to set the appropriate bits
3172 for the floating-point model they use. */
3174 case EF_ARM_SOFT_FLOAT
:
3175 fp_model
= ARM_FLOAT_SOFT_FPA
;
3177 case EF_ARM_VFP_FLOAT
:
3178 fp_model
= ARM_FLOAT_VFP
;
3180 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
3181 fp_model
= ARM_FLOAT_SOFT_VFP
;
3186 if (e_flags
& EF_ARM_BE8
)
3187 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
3192 /* Leave it as "auto". */
3197 /* If there is already a candidate, use it. */
3198 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
3200 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
3202 if (arm_abi
!= ARM_ABI_AUTO
3203 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
3206 if (fp_model
!= ARM_FLOAT_AUTO
3207 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
3210 /* Found a match. */
3214 if (best_arch
!= NULL
)
3216 if (tdesc_data
!= NULL
)
3217 tdesc_data_cleanup (tdesc_data
);
3218 return best_arch
->gdbarch
;
3221 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
3222 gdbarch
= gdbarch_alloc (&info
, tdep
);
3224 /* Record additional information about the architecture we are defining.
3225 These are gdbarch discriminators, like the OSABI. */
3226 tdep
->arm_abi
= arm_abi
;
3227 tdep
->fp_model
= fp_model
;
3228 tdep
->have_fpa_registers
= have_fpa_registers
;
3231 switch (info
.byte_order_for_code
)
3233 case BFD_ENDIAN_BIG
:
3234 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
3235 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
3236 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
3237 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
3241 case BFD_ENDIAN_LITTLE
:
3242 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
3243 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
3244 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
3245 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
3250 internal_error (__FILE__
, __LINE__
,
3251 _("arm_gdbarch_init: bad byte order for float format"));
3254 /* On ARM targets char defaults to unsigned. */
3255 set_gdbarch_char_signed (gdbarch
, 0);
3257 /* This should be low enough for everything. */
3258 tdep
->lowest_pc
= 0x20;
3259 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
3261 /* The default, for both APCS and AAPCS, is to return small
3262 structures in registers. */
3263 tdep
->struct_return
= reg_struct_return
;
3265 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
3266 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
3268 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
3270 /* Frame handling. */
3271 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
3272 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
3273 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
3275 frame_base_set_default (gdbarch
, &arm_normal_base
);
3277 /* Address manipulation. */
3278 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
3279 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
3281 /* Advance PC across function entry code. */
3282 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
3284 /* Skip trampolines. */
3285 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
3287 /* The stack grows downward. */
3288 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3290 /* Breakpoint manipulation. */
3291 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
3293 /* Information about registers, etc. */
3294 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
3295 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
3296 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
3297 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
3298 set_gdbarch_register_type (gdbarch
, arm_register_type
);
3300 /* This "info float" is FPA-specific. Use the generic version if we
3302 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
3303 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
3305 /* Internal <-> external register number maps. */
3306 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
3307 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
3309 set_gdbarch_register_name (gdbarch
, arm_register_name
);
3311 /* Returning results. */
3312 set_gdbarch_return_value (gdbarch
, arm_return_value
);
3315 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
3317 /* Minsymbol frobbing. */
3318 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
3319 set_gdbarch_coff_make_msymbol_special (gdbarch
,
3320 arm_coff_make_msymbol_special
);
3321 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
3323 /* Virtual tables. */
3324 set_gdbarch_vbit_in_delta (gdbarch
, 1);
3326 /* Hook in the ABI-specific overrides, if they have been registered. */
3327 gdbarch_init_osabi (info
, gdbarch
);
3329 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
3331 /* Add some default predicates. */
3332 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
3333 dwarf2_append_unwinders (gdbarch
);
3334 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
3336 /* Now we have tuned the configuration, set a few final things,
3337 based on what the OS ABI has told us. */
3339 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
3340 binaries are always marked. */
3341 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
3342 tdep
->arm_abi
= ARM_ABI_APCS
;
3344 /* We used to default to FPA for generic ARM, but almost nobody
3345 uses that now, and we now provide a way for the user to force
3346 the model. So default to the most useful variant. */
3347 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
3348 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
3350 if (tdep
->jb_pc
>= 0)
3351 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
3353 /* Floating point sizes and format. */
3354 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
3355 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
3357 set_gdbarch_double_format
3358 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
3359 set_gdbarch_long_double_format
3360 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
3364 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
3365 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
3369 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
3371 /* Add standard register aliases. We add aliases even for those
3372 nanes which are used by the current architecture - it's simpler,
3373 and does no harm, since nothing ever lists user registers. */
3374 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
3375 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
3376 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
3382 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3384 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3389 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
3390 (unsigned long) tdep
->lowest_pc
);
3393 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
3396 _initialize_arm_tdep (void)
3398 struct ui_file
*stb
;
3400 struct cmd_list_element
*new_set
, *new_show
;
3401 const char *setname
;
3402 const char *setdesc
;
3403 const char *const *regnames
;
3405 static char *helptext
;
3406 char regdesc
[1024], *rdptr
= regdesc
;
3407 size_t rest
= sizeof (regdesc
);
3409 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
3411 arm_objfile_data_key
3412 = register_objfile_data_with_cleanup (arm_objfile_data_cleanup
);
3414 /* Register an ELF OS ABI sniffer for ARM binaries. */
3415 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
3416 bfd_target_elf_flavour
,
3417 arm_elf_osabi_sniffer
);
3419 /* Get the number of possible sets of register names defined in opcodes. */
3420 num_disassembly_options
= get_arm_regname_num_options ();
3422 /* Add root prefix command for all "set arm"/"show arm" commands. */
3423 add_prefix_cmd ("arm", no_class
, set_arm_command
,
3424 _("Various ARM-specific commands."),
3425 &setarmcmdlist
, "set arm ", 0, &setlist
);
3427 add_prefix_cmd ("arm", no_class
, show_arm_command
,
3428 _("Various ARM-specific commands."),
3429 &showarmcmdlist
, "show arm ", 0, &showlist
);
3431 /* Sync the opcode insn printer with our register viewer. */
3432 parse_arm_disassembler_option ("reg-names-std");
3434 /* Initialize the array that will be passed to
3435 add_setshow_enum_cmd(). */
3436 valid_disassembly_styles
3437 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
3438 for (i
= 0; i
< num_disassembly_options
; i
++)
3440 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
3441 valid_disassembly_styles
[i
] = setname
;
3442 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
3445 /* When we find the default names, tell the disassembler to use
3447 if (!strcmp (setname
, "std"))
3449 disassembly_style
= setname
;
3450 set_arm_regname_option (i
);
3453 /* Mark the end of valid options. */
3454 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
3456 /* Create the help text. */
3457 stb
= mem_fileopen ();
3458 fprintf_unfiltered (stb
, "%s%s%s",
3459 _("The valid values are:\n"),
3461 _("The default is \"std\"."));
3462 helptext
= ui_file_xstrdup (stb
, &length
);
3463 ui_file_delete (stb
);
3465 add_setshow_enum_cmd("disassembler", no_class
,
3466 valid_disassembly_styles
, &disassembly_style
,
3467 _("Set the disassembly style."),
3468 _("Show the disassembly style."),
3470 set_disassembly_style_sfunc
,
3471 NULL
, /* FIXME: i18n: The disassembly style is \"%s\". */
3472 &setarmcmdlist
, &showarmcmdlist
);
3474 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
3475 _("Set usage of ARM 32-bit mode."),
3476 _("Show usage of ARM 32-bit mode."),
3477 _("When off, a 26-bit PC will be used."),
3479 NULL
, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
3480 &setarmcmdlist
, &showarmcmdlist
);
3482 /* Add a command to allow the user to force the FPU model. */
3483 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
3484 _("Set the floating point type."),
3485 _("Show the floating point type."),
3486 _("auto - Determine the FP typefrom the OS-ABI.\n\
3487 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
3488 fpa - FPA co-processor (GCC compiled).\n\
3489 softvfp - Software FP with pure-endian doubles.\n\
3490 vfp - VFP co-processor."),
3491 set_fp_model_sfunc
, show_fp_model
,
3492 &setarmcmdlist
, &showarmcmdlist
);
3494 /* Add a command to allow the user to force the ABI. */
3495 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
3498 NULL
, arm_set_abi
, arm_show_abi
,
3499 &setarmcmdlist
, &showarmcmdlist
);
3501 /* Add two commands to allow the user to force the assumed
3503 add_setshow_enum_cmd ("fallback-mode", class_support
,
3504 arm_mode_strings
, &arm_fallback_mode_string
,
3505 _("Set the mode assumed when symbols are unavailable."),
3506 _("Show the mode assumed when symbols are unavailable."),
3507 NULL
, NULL
, arm_show_fallback_mode
,
3508 &setarmcmdlist
, &showarmcmdlist
);
3509 add_setshow_enum_cmd ("force-mode", class_support
,
3510 arm_mode_strings
, &arm_force_mode_string
,
3511 _("Set the mode assumed even when symbols are available."),
3512 _("Show the mode assumed even when symbols are available."),
3513 NULL
, NULL
, arm_show_force_mode
,
3514 &setarmcmdlist
, &showarmcmdlist
);
3516 /* Debugging flag. */
3517 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
3518 _("Set ARM debugging."),
3519 _("Show ARM debugging."),
3520 _("When on, arm-specific debugging is enabled."),
3522 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
3523 &setdebuglist
, &showdebuglist
);