1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
4 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper () */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
43 #include "target-descriptions.h"
44 #include "user-regs.h"
47 #include "gdb/sim-arm.h"
50 #include "coff/internal.h"
53 #include "gdb_assert.h"
57 /* Macros for setting and testing a bit in a minimal symbol that marks
58 it as Thumb function. The MSB of the minimal symbol's "info" field
59 is used for this purpose.
61 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
62 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
64 #define MSYMBOL_SET_SPECIAL(msym) \
65 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
68 #define MSYMBOL_IS_SPECIAL(msym) \
69 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
71 /* The list of available "set arm ..." and "show arm ..." commands. */
72 static struct cmd_list_element
*setarmcmdlist
= NULL
;
73 static struct cmd_list_element
*showarmcmdlist
= NULL
;
75 /* The type of floating-point to use. Keep this in sync with enum
76 arm_float_model, and the help string in _initialize_arm_tdep. */
77 static const char *fp_model_strings
[] =
87 /* A variable that can be configured by the user. */
88 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
89 static const char *current_fp_model
= "auto";
91 /* The ABI to use. Keep this in sync with arm_abi_kind. */
92 static const char *arm_abi_strings
[] =
100 /* A variable that can be configured by the user. */
101 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
102 static const char *arm_abi_string
= "auto";
104 /* Number of different reg name sets (options). */
105 static int num_disassembly_options
;
107 /* The standard register names, and all the valid aliases for them. */
112 } arm_register_aliases
[] = {
113 /* Basic register numbers. */
130 /* Synonyms (argument and variable registers). */
143 /* Other platform-specific names for r9. */
151 /* Names used by GCC (not listed in the ARM EABI). */
154 /* A special name from the older ATPCS. */
158 static const char *const arm_register_names
[] =
159 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
160 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
161 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
162 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
163 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
164 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
165 "fps", "cpsr" }; /* 24 25 */
167 /* Valid register name styles. */
168 static const char **valid_disassembly_styles
;
170 /* Disassembly style to use. Default to "std" register names. */
171 static const char *disassembly_style
;
173 /* This is used to keep the bfd arch_info in sync with the disassembly
175 static void set_disassembly_style_sfunc(char *, int,
176 struct cmd_list_element
*);
177 static void set_disassembly_style (void);
179 static void convert_from_extended (const struct floatformat
*, const void *,
181 static void convert_to_extended (const struct floatformat
*, void *,
184 struct arm_prologue_cache
186 /* The stack pointer at the time this frame was created; i.e. the
187 caller's stack pointer when this function was called. It is used
188 to identify this frame. */
191 /* The frame base for this frame is just prev_sp - frame size.
192 FRAMESIZE is the distance from the frame pointer to the
193 initial stack pointer. */
197 /* The register used to hold the frame pointer for this frame. */
200 /* Saved register offsets. */
201 struct trad_frame_saved_reg
*saved_regs
;
204 /* Addresses for calling Thumb functions have the bit 0 set.
205 Here are some macros to test, set, or clear bit 0 of addresses. */
206 #define IS_THUMB_ADDR(addr) ((addr) & 1)
207 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
208 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
210 /* Set to true if the 32-bit mode is in use. */
214 /* Determine if FRAME is executing in Thumb mode. */
217 arm_frame_is_thumb (struct frame_info
*frame
)
221 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
222 directly (from a signal frame or dummy frame) or by interpreting
223 the saved LR (from a prologue or DWARF frame). So consult it and
224 trust the unwinders. */
225 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
227 return (cpsr
& CPSR_T
) != 0;
230 /* Determine if the program counter specified in MEMADDR is in a Thumb
231 function. This function should be called for addresses unrelated to
232 any executing frame; otherwise, prefer arm_frame_is_thumb. */
235 arm_pc_is_thumb (CORE_ADDR memaddr
)
237 struct minimal_symbol
*sym
;
239 /* If bit 0 of the address is set, assume this is a Thumb address. */
240 if (IS_THUMB_ADDR (memaddr
))
243 /* Thumb functions have a "special" bit set in minimal symbols. */
244 sym
= lookup_minimal_symbol_by_pc (memaddr
);
247 return (MSYMBOL_IS_SPECIAL (sym
));
255 /* Remove useless bits from addresses in a running program. */
257 arm_addr_bits_remove (CORE_ADDR val
)
260 return UNMAKE_THUMB_ADDR (val
);
262 return (val
& 0x03fffffc);
265 /* When reading symbols, we need to zap the low bit of the address,
266 which may be set to 1 for Thumb functions. */
268 arm_smash_text_address (CORE_ADDR val
)
273 /* Analyze a Thumb prologue, looking for a recognizable stack frame
274 and frame pointer. Scan until we encounter a store that could
275 clobber the stack frame unexpectedly, or an unknown instruction. */
278 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
279 CORE_ADDR start
, CORE_ADDR limit
,
280 struct arm_prologue_cache
*cache
)
284 struct pv_area
*stack
;
285 struct cleanup
*back_to
;
288 for (i
= 0; i
< 16; i
++)
289 regs
[i
] = pv_register (i
, 0);
290 stack
= make_pv_area (ARM_SP_REGNUM
);
291 back_to
= make_cleanup_free_pv_area (stack
);
293 while (start
< limit
)
297 insn
= read_memory_unsigned_integer (start
, 2);
299 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
304 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
307 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
308 whether to save LR (R14). */
309 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
311 /* Calculate offsets of saved R0-R7 and LR. */
312 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
313 if (mask
& (1 << regno
))
315 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
317 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
320 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
323 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
324 if (insn
& 0x80) /* Check for SUB. */
325 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
328 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
331 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
332 regs
[THUMB_FP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
334 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
336 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
337 int src_reg
= (insn
& 0x78) >> 3;
338 regs
[dst_reg
] = regs
[src_reg
];
340 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
342 /* Handle stores to the stack. Normally pushes are used,
343 but with GCC -mtpcs-frame, there may be other stores
344 in the prologue to create the frame. */
345 int regno
= (insn
>> 8) & 0x7;
348 offset
= (insn
& 0xff) << 2;
349 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
351 if (pv_area_store_would_trash (stack
, addr
))
354 pv_area_store (stack
, addr
, 4, regs
[regno
]);
358 /* We don't know what this instruction is. We're finished
359 scanning. NOTE: Recognizing more safe-to-ignore
360 instructions here will improve support for optimized
370 do_cleanups (back_to
);
374 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
376 /* Frame pointer is fp. Frame size is constant. */
377 cache
->framereg
= ARM_FP_REGNUM
;
378 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
380 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
382 /* Frame pointer is r7. Frame size is constant. */
383 cache
->framereg
= THUMB_FP_REGNUM
;
384 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
386 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
388 /* Try the stack pointer... this is a bit desperate. */
389 cache
->framereg
= ARM_SP_REGNUM
;
390 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
394 /* We're just out of luck. We don't know where the frame is. */
395 cache
->framereg
= -1;
396 cache
->framesize
= 0;
399 for (i
= 0; i
< 16; i
++)
400 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
401 cache
->saved_regs
[i
].addr
= offset
;
403 do_cleanups (back_to
);
407 /* Advance the PC across any function entry prologue instructions to
408 reach some "real" code.
410 The APCS (ARM Procedure Call Standard) defines the following
414 [stmfd sp!, {a1,a2,a3,a4}]
415 stmfd sp!, {...,fp,ip,lr,pc}
416 [stfe f7, [sp, #-12]!]
417 [stfe f6, [sp, #-12]!]
418 [stfe f5, [sp, #-12]!]
419 [stfe f4, [sp, #-12]!]
420 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
423 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
427 CORE_ADDR func_addr
, func_end
= 0;
429 struct symtab_and_line sal
;
431 /* If we're in a dummy frame, don't even try to skip the prologue. */
432 if (deprecated_pc_in_call_dummy (pc
))
435 /* See what the symbol table says. */
437 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
441 /* Found a function. */
442 sym
= lookup_symbol (func_name
, NULL
, VAR_DOMAIN
, NULL
, NULL
);
443 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
445 /* Don't use this trick for assembly source files. */
446 sal
= find_pc_line (func_addr
, 0);
447 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
452 /* Can't find the prologue end in the symbol table, try it the hard way
453 by disassembling the instructions. */
455 /* Like arm_scan_prologue, stop no later than pc + 64. */
456 if (func_end
== 0 || func_end
> pc
+ 64)
459 /* Check if this is Thumb code. */
460 if (arm_pc_is_thumb (pc
))
461 return thumb_analyze_prologue (gdbarch
, pc
, func_end
, NULL
);
463 for (skip_pc
= pc
; skip_pc
< func_end
; skip_pc
+= 4)
465 inst
= read_memory_unsigned_integer (skip_pc
, 4);
467 /* "mov ip, sp" is no longer a required part of the prologue. */
468 if (inst
== 0xe1a0c00d) /* mov ip, sp */
471 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
474 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
477 /* Some prologues begin with "str lr, [sp, #-4]!". */
478 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
481 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
484 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
487 /* Any insns after this point may float into the code, if it makes
488 for better instruction scheduling, so we skip them only if we
489 find them, but still consider the function to be frame-ful. */
491 /* We may have either one sfmfd instruction here, or several stfe
492 insns, depending on the version of floating point code we
494 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
497 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
500 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
503 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
506 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
507 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
508 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
511 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
512 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
513 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
516 /* Un-recognized instruction; stop scanning. */
520 return skip_pc
; /* End of prologue */
524 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
525 This function decodes a Thumb function prologue to determine:
526 1) the size of the stack frame
527 2) which registers are saved on it
528 3) the offsets of saved regs
529 4) the offset from the stack pointer to the frame pointer
531 A typical Thumb function prologue would create this stack frame
532 (offsets relative to FP)
533 old SP -> 24 stack parameters
536 R7 -> 0 local variables (16 bytes)
537 SP -> -12 additional stack space (12 bytes)
538 The frame size would thus be 36 bytes, and the frame offset would be
539 12 bytes. The frame register is R7.
541 The comments for thumb_skip_prolog() describe the algorithm we use
542 to detect the end of the prolog. */
546 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
547 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
549 CORE_ADDR prologue_start
;
550 CORE_ADDR prologue_end
;
551 CORE_ADDR current_pc
;
553 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
556 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
558 if (sal
.line
== 0) /* no line info, use current PC */
559 prologue_end
= prev_pc
;
560 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
561 prologue_end
= sal
.end
; /* (probably means no prologue) */
564 /* We're in the boondocks: we have no idea where the start of the
568 prologue_end
= min (prologue_end
, prev_pc
);
570 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
573 /* This function decodes an ARM function prologue to determine:
574 1) the size of the stack frame
575 2) which registers are saved on it
576 3) the offsets of saved regs
577 4) the offset from the stack pointer to the frame pointer
578 This information is stored in the "extra" fields of the frame_info.
580 There are two basic forms for the ARM prologue. The fixed argument
581 function call will look like:
584 stmfd sp!, {fp, ip, lr, pc}
588 Which would create this stack frame (offsets relative to FP):
589 IP -> 4 (caller's stack)
590 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
591 -4 LR (return address in caller)
592 -8 IP (copy of caller's SP)
594 SP -> -28 Local variables
596 The frame size would thus be 32 bytes, and the frame offset would be
597 28 bytes. The stmfd call can also save any of the vN registers it
598 plans to use, which increases the frame size accordingly.
600 Note: The stored PC is 8 off of the STMFD instruction that stored it
601 because the ARM Store instructions always store PC + 8 when you read
604 A variable argument function call will look like:
607 stmfd sp!, {a1, a2, a3, a4}
608 stmfd sp!, {fp, ip, lr, pc}
611 Which would create this stack frame (offsets relative to FP):
612 IP -> 20 (caller's stack)
617 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
618 -4 LR (return address in caller)
619 -8 IP (copy of caller's SP)
621 SP -> -28 Local variables
623 The frame size would thus be 48 bytes, and the frame offset would be
626 There is another potential complication, which is that the optimizer
627 will try to separate the store of fp in the "stmfd" instruction from
628 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
629 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
631 Also, note, the original version of the ARM toolchain claimed that there
634 instruction at the end of the prologue. I have never seen GCC produce
635 this, and the ARM docs don't mention it. We still test for it below in
641 arm_scan_prologue (struct frame_info
*this_frame
,
642 struct arm_prologue_cache
*cache
)
644 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
646 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
647 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
648 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
649 pv_t regs
[ARM_FPS_REGNUM
];
650 struct pv_area
*stack
;
651 struct cleanup
*back_to
;
654 /* Assume there is no frame until proven otherwise. */
655 cache
->framereg
= ARM_SP_REGNUM
;
656 cache
->framesize
= 0;
658 /* Check for Thumb prologue. */
659 if (arm_frame_is_thumb (this_frame
))
661 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
665 /* Find the function prologue. If we can't find the function in
666 the symbol table, peek in the stack frame to find the PC. */
667 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
670 /* One way to find the end of the prologue (which works well
671 for unoptimized code) is to do the following:
673 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
676 prologue_end = prev_pc;
677 else if (sal.end < prologue_end)
678 prologue_end = sal.end;
680 This mechanism is very accurate so long as the optimizer
681 doesn't move any instructions from the function body into the
682 prologue. If this happens, sal.end will be the last
683 instruction in the first hunk of prologue code just before
684 the first instruction that the scheduler has moved from
685 the body to the prologue.
687 In order to make sure that we scan all of the prologue
688 instructions, we use a slightly less accurate mechanism which
689 may scan more than necessary. To help compensate for this
690 lack of accuracy, the prologue scanning loop below contains
691 several clauses which'll cause the loop to terminate early if
692 an implausible prologue instruction is encountered.
698 is a suitable endpoint since it accounts for the largest
699 possible prologue plus up to five instructions inserted by
702 if (prologue_end
> prologue_start
+ 64)
704 prologue_end
= prologue_start
+ 64; /* See above. */
709 /* We have no symbol information. Our only option is to assume this
710 function has a standard stack frame and the normal frame register.
711 Then, we can find the value of our frame pointer on entrance to
712 the callee (or at the present moment if this is the innermost frame).
713 The value stored there should be the address of the stmfd + 8. */
715 LONGEST return_value
;
717 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
718 if (!safe_read_memory_integer (frame_loc
, 4, &return_value
))
722 prologue_start
= gdbarch_addr_bits_remove
723 (gdbarch
, return_value
) - 8;
724 prologue_end
= prologue_start
+ 64; /* See above. */
728 if (prev_pc
< prologue_end
)
729 prologue_end
= prev_pc
;
731 /* Now search the prologue looking for instructions that set up the
732 frame pointer, adjust the stack pointer, and save registers.
734 Be careful, however, and if it doesn't look like a prologue,
735 don't try to scan it. If, for instance, a frameless function
736 begins with stmfd sp!, then we will tell ourselves there is
737 a frame, which will confuse stack traceback, as well as "finish"
738 and other operations that rely on a knowledge of the stack
741 In the APCS, the prologue should start with "mov ip, sp" so
742 if we don't see this as the first insn, we will stop.
744 [Note: This doesn't seem to be true any longer, so it's now an
745 optional part of the prologue. - Kevin Buettner, 2001-11-20]
747 [Note further: The "mov ip,sp" only seems to be missing in
748 frameless functions at optimization level "-O2" or above,
749 in which case it is often (but not always) replaced by
750 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
752 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
753 regs
[regno
] = pv_register (regno
, 0);
754 stack
= make_pv_area (ARM_SP_REGNUM
);
755 back_to
= make_cleanup_free_pv_area (stack
);
757 for (current_pc
= prologue_start
;
758 current_pc
< prologue_end
;
761 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
763 if (insn
== 0xe1a0c00d) /* mov ip, sp */
765 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
768 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
770 unsigned imm
= insn
& 0xff; /* immediate value */
771 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
772 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
773 regs
[ARM_IP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], imm
);
776 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
778 unsigned imm
= insn
& 0xff; /* immediate value */
779 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
780 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
781 regs
[ARM_IP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
784 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
786 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
788 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
789 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[ARM_LR_REGNUM
]);
792 else if ((insn
& 0xffff0000) == 0xe92d0000)
793 /* stmfd sp!, {..., fp, ip, lr, pc}
795 stmfd sp!, {a1, a2, a3, a4} */
797 int mask
= insn
& 0xffff;
799 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
802 /* Calculate offsets of saved registers. */
803 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
804 if (mask
& (1 << regno
))
806 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
807 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
810 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
811 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
812 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
814 /* No need to add this to saved_regs -- it's just an arg reg. */
817 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
818 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
819 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
821 /* No need to add this to saved_regs -- it's just an arg reg. */
824 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
826 unsigned imm
= insn
& 0xff; /* immediate value */
827 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
828 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
829 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
831 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
833 unsigned imm
= insn
& 0xff; /* immediate value */
834 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
835 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
836 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
838 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
839 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
841 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
844 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
845 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
846 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
848 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
849 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
852 unsigned int fp_start_reg
, fp_bound_reg
;
854 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
857 if ((insn
& 0x800) == 0x800) /* N0 is set */
859 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
866 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
872 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
873 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
874 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
876 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
877 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
878 regs
[fp_start_reg
++]);
881 else if ((insn
& 0xf0000000) != 0xe0000000)
882 break; /* Condition not true, exit early */
883 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
884 break; /* Don't scan past a block load */
886 /* The optimizer might shove anything into the prologue,
887 so we just skip what we don't recognize. */
891 /* The frame size is just the distance from the frame register
892 to the original stack pointer. */
893 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
895 /* Frame pointer is fp. */
896 cache
->framereg
= ARM_FP_REGNUM
;
897 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
899 else if (pv_is_register (regs
[ARM_SP_REGNUM
], ARM_SP_REGNUM
))
901 /* Try the stack pointer... this is a bit desperate. */
902 cache
->framereg
= ARM_SP_REGNUM
;
903 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
907 /* We're just out of luck. We don't know where the frame is. */
908 cache
->framereg
= -1;
909 cache
->framesize
= 0;
912 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
913 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
914 cache
->saved_regs
[regno
].addr
= offset
;
916 do_cleanups (back_to
);
919 static struct arm_prologue_cache
*
920 arm_make_prologue_cache (struct frame_info
*this_frame
)
923 struct arm_prologue_cache
*cache
;
924 CORE_ADDR unwound_fp
;
926 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
927 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
929 arm_scan_prologue (this_frame
, cache
);
931 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
935 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
937 /* Calculate actual addresses of saved registers using offsets
938 determined by arm_scan_prologue. */
939 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
940 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
941 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
946 /* Our frame ID for a normal frame is the current function's starting PC
947 and the caller's SP when we were called. */
950 arm_prologue_this_id (struct frame_info
*this_frame
,
952 struct frame_id
*this_id
)
954 struct arm_prologue_cache
*cache
;
958 if (*this_cache
== NULL
)
959 *this_cache
= arm_make_prologue_cache (this_frame
);
962 func
= get_frame_func (this_frame
);
964 /* This is meant to halt the backtrace at "_start". Make sure we
965 don't halt it at a generic dummy frame. */
966 if (func
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
969 /* If we've hit a wall, stop. */
970 if (cache
->prev_sp
== 0)
973 id
= frame_id_build (cache
->prev_sp
, func
);
977 static struct value
*
978 arm_prologue_prev_register (struct frame_info
*this_frame
,
982 struct arm_prologue_cache
*cache
;
984 if (*this_cache
== NULL
)
985 *this_cache
= arm_make_prologue_cache (this_frame
);
988 /* If we are asked to unwind the PC, then we need to return the LR
989 instead. The prologue may save PC, but it will point into this
990 frame's prologue, not the next frame's resume location. Also
991 strip the saved T bit. A valid LR may have the low bit set, but
992 a valid PC never does. */
993 if (prev_regnum
== ARM_PC_REGNUM
)
997 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
998 return frame_unwind_got_constant (this_frame
, prev_regnum
,
999 arm_addr_bits_remove (lr
));
1002 /* SP is generally not saved to the stack, but this frame is
1003 identified by the next frame's stack pointer at the time of the call.
1004 The value was already reconstructed into PREV_SP. */
1005 if (prev_regnum
== ARM_SP_REGNUM
)
1006 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
1008 /* The CPSR may have been changed by the call instruction and by the
1009 called function. The only bit we can reconstruct is the T bit,
1010 by checking the low bit of LR as of the call. This is a reliable
1011 indicator of Thumb-ness except for some ARM v4T pre-interworking
1012 Thumb code, which could get away with a clear low bit as long as
1013 the called function did not use bx. Guess that all other
1014 bits are unchanged; the condition flags are presumably lost,
1015 but the processor status is likely valid. */
1016 if (prev_regnum
== ARM_PS_REGNUM
)
1020 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
1021 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1022 if (IS_THUMB_ADDR (lr
))
1026 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
1029 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1033 struct frame_unwind arm_prologue_unwind
= {
1035 arm_prologue_this_id
,
1036 arm_prologue_prev_register
,
1038 default_frame_sniffer
1041 static struct arm_prologue_cache
*
1042 arm_make_stub_cache (struct frame_info
*this_frame
)
1045 struct arm_prologue_cache
*cache
;
1046 CORE_ADDR unwound_fp
;
1048 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1049 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1051 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1056 /* Our frame ID for a stub frame is the current SP and LR. */
1059 arm_stub_this_id (struct frame_info
*this_frame
,
1061 struct frame_id
*this_id
)
1063 struct arm_prologue_cache
*cache
;
1065 if (*this_cache
== NULL
)
1066 *this_cache
= arm_make_stub_cache (this_frame
);
1067 cache
= *this_cache
;
1069 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
1073 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
1074 struct frame_info
*this_frame
,
1075 void **this_prologue_cache
)
1077 CORE_ADDR addr_in_block
;
1080 addr_in_block
= get_frame_address_in_block (this_frame
);
1081 if (in_plt_section (addr_in_block
, NULL
)
1082 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
1088 struct frame_unwind arm_stub_unwind
= {
1091 arm_prologue_prev_register
,
1093 arm_stub_unwind_sniffer
1097 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
1099 struct arm_prologue_cache
*cache
;
1101 if (*this_cache
== NULL
)
1102 *this_cache
= arm_make_prologue_cache (this_frame
);
1103 cache
= *this_cache
;
1105 return cache
->prev_sp
- cache
->framesize
;
1108 struct frame_base arm_normal_base
= {
1109 &arm_prologue_unwind
,
1110 arm_normal_frame_base
,
1111 arm_normal_frame_base
,
1112 arm_normal_frame_base
1115 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1116 dummy frame. The frame ID's base needs to match the TOS value
1117 saved by save_dummy_frame_tos() and returned from
1118 arm_push_dummy_call, and the PC needs to match the dummy frame's
1121 static struct frame_id
1122 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1124 return frame_id_build (get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
),
1125 get_frame_pc (this_frame
));
1128 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1129 be used to construct the previous frame's ID, after looking up the
1130 containing function). */
1133 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1136 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1137 return arm_addr_bits_remove (pc
);
1141 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1143 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1146 static struct value
*
1147 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1155 /* The PC is normally copied from the return column, which
1156 describes saves of LR. However, that version may have an
1157 extra bit set to indicate Thumb state. The bit is not
1159 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1160 return frame_unwind_got_constant (this_frame
, regnum
,
1161 arm_addr_bits_remove (lr
));
1164 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
1165 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
1166 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
1167 if (IS_THUMB_ADDR (lr
))
1171 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
1174 internal_error (__FILE__
, __LINE__
,
1175 _("Unexpected register %d"), regnum
);
1180 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1181 struct dwarf2_frame_state_reg
*reg
,
1182 struct frame_info
*this_frame
)
1188 reg
->how
= DWARF2_FRAME_REG_FN
;
1189 reg
->loc
.fn
= arm_dwarf2_prev_register
;
1192 reg
->how
= DWARF2_FRAME_REG_CFA
;
1197 /* When arguments must be pushed onto the stack, they go on in reverse
1198 order. The code below implements a FILO (stack) to do this. */
1203 struct stack_item
*prev
;
1207 static struct stack_item
*
1208 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1210 struct stack_item
*si
;
1211 si
= xmalloc (sizeof (struct stack_item
));
1212 si
->data
= xmalloc (len
);
1215 memcpy (si
->data
, contents
, len
);
1219 static struct stack_item
*
1220 pop_stack_item (struct stack_item
*si
)
1222 struct stack_item
*dead
= si
;
1230 /* Return the alignment (in bytes) of the given type. */
1233 arm_type_align (struct type
*t
)
1239 t
= check_typedef (t
);
1240 switch (TYPE_CODE (t
))
1243 /* Should never happen. */
1244 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1248 case TYPE_CODE_ENUM
:
1252 case TYPE_CODE_RANGE
:
1253 case TYPE_CODE_BITSTRING
:
1255 case TYPE_CODE_CHAR
:
1256 case TYPE_CODE_BOOL
:
1257 return TYPE_LENGTH (t
);
1259 case TYPE_CODE_ARRAY
:
1260 case TYPE_CODE_COMPLEX
:
1261 /* TODO: What about vector types? */
1262 return arm_type_align (TYPE_TARGET_TYPE (t
));
1264 case TYPE_CODE_STRUCT
:
1265 case TYPE_CODE_UNION
:
1267 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1269 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
1277 /* We currently only support passing parameters in integer registers. This
1278 conforms with GCC's default model. Several other variants exist and
1279 we should probably support some of them based on the selected ABI. */
1282 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1283 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1284 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1285 CORE_ADDR struct_addr
)
1290 struct stack_item
*si
= NULL
;
1292 /* Set the return address. For the ARM, the return breakpoint is
1293 always at BP_ADDR. */
1294 /* XXX Fix for Thumb. */
1295 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1297 /* Walk through the list of args and determine how large a temporary
1298 stack is required. Need to take care here as structs may be
1299 passed on the stack, and we have to to push them. */
1302 argreg
= ARM_A1_REGNUM
;
1305 /* The struct_return pointer occupies the first parameter
1306 passing register. */
1310 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = 0x%s\n",
1311 gdbarch_register_name (gdbarch
, argreg
),
1312 paddr (struct_addr
));
1313 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1317 for (argnum
= 0; argnum
< nargs
; argnum
++)
1320 struct type
*arg_type
;
1321 struct type
*target_type
;
1322 enum type_code typecode
;
1326 arg_type
= check_typedef (value_type (args
[argnum
]));
1327 len
= TYPE_LENGTH (arg_type
);
1328 target_type
= TYPE_TARGET_TYPE (arg_type
);
1329 typecode
= TYPE_CODE (arg_type
);
1330 val
= value_contents_writeable (args
[argnum
]);
1332 align
= arm_type_align (arg_type
);
1333 /* Round alignment up to a whole number of words. */
1334 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
1335 /* Different ABIs have different maximum alignments. */
1336 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
1338 /* The APCS ABI only requires word alignment. */
1339 align
= INT_REGISTER_SIZE
;
1343 /* The AAPCS requires at most doubleword alignment. */
1344 if (align
> INT_REGISTER_SIZE
* 2)
1345 align
= INT_REGISTER_SIZE
* 2;
1348 /* Push stack padding for dowubleword alignment. */
1349 if (nstack
& (align
- 1))
1351 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1352 nstack
+= INT_REGISTER_SIZE
;
1355 /* Doubleword aligned quantities must go in even register pairs. */
1356 if (argreg
<= ARM_LAST_ARG_REGNUM
1357 && align
> INT_REGISTER_SIZE
1361 /* If the argument is a pointer to a function, and it is a
1362 Thumb function, create a LOCAL copy of the value and set
1363 the THUMB bit in it. */
1364 if (TYPE_CODE_PTR
== typecode
1365 && target_type
!= NULL
1366 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1368 CORE_ADDR regval
= extract_unsigned_integer (val
, len
);
1369 if (arm_pc_is_thumb (regval
))
1372 store_unsigned_integer (val
, len
, MAKE_THUMB_ADDR (regval
));
1376 /* Copy the argument to general registers or the stack in
1377 register-sized pieces. Large arguments are split between
1378 registers and stack. */
1381 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
1383 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1385 /* The argument is being passed in a general purpose
1387 CORE_ADDR regval
= extract_unsigned_integer (val
, partial_len
);
1388 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1389 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
1391 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1393 gdbarch_register_name
1395 phex (regval
, INT_REGISTER_SIZE
));
1396 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1401 /* Push the arguments onto the stack. */
1403 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1405 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1406 nstack
+= INT_REGISTER_SIZE
;
1413 /* If we have an odd number of words to push, then decrement the stack
1414 by one word now, so first stack argument will be dword aligned. */
1421 write_memory (sp
, si
->data
, si
->len
);
1422 si
= pop_stack_item (si
);
1425 /* Finally, update teh SP register. */
1426 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1432 /* Always align the frame to an 8-byte boundary. This is required on
1433 some platforms and harmless on the rest. */
1436 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1438 /* Align the stack to eight bytes. */
1439 return sp
& ~ (CORE_ADDR
) 7;
1443 print_fpu_flags (int flags
)
1445 if (flags
& (1 << 0))
1446 fputs ("IVO ", stdout
);
1447 if (flags
& (1 << 1))
1448 fputs ("DVZ ", stdout
);
1449 if (flags
& (1 << 2))
1450 fputs ("OFL ", stdout
);
1451 if (flags
& (1 << 3))
1452 fputs ("UFL ", stdout
);
1453 if (flags
& (1 << 4))
1454 fputs ("INX ", stdout
);
1458 /* Print interesting information about the floating point processor
1459 (if present) or emulator. */
1461 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1462 struct frame_info
*frame
, const char *args
)
1464 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
1467 type
= (status
>> 24) & 127;
1468 if (status
& (1 << 31))
1469 printf (_("Hardware FPU type %d\n"), type
);
1471 printf (_("Software FPU type %d\n"), type
);
1472 /* i18n: [floating point unit] mask */
1473 fputs (_("mask: "), stdout
);
1474 print_fpu_flags (status
>> 16);
1475 /* i18n: [floating point unit] flags */
1476 fputs (_("flags: "), stdout
);
1477 print_fpu_flags (status
);
1480 /* Return the GDB type object for the "standard" data type of data in
1483 static struct type
*
1484 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
1486 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1487 return builtin_type_arm_ext
;
1488 else if (regnum
== ARM_SP_REGNUM
)
1489 return builtin_type_void_data_ptr
;
1490 else if (regnum
== ARM_PC_REGNUM
)
1491 return builtin_type_void_func_ptr
;
1492 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
1493 /* These registers are only supported on targets which supply
1494 an XML description. */
1495 return builtin_type_int0
;
1497 return builtin_type_uint32
;
1500 /* Map a DWARF register REGNUM onto the appropriate GDB register
1504 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
1506 /* Core integer regs. */
1507 if (reg
>= 0 && reg
<= 15)
1510 /* Legacy FPA encoding. These were once used in a way which
1511 overlapped with VFP register numbering, so their use is
1512 discouraged, but GDB doesn't support the ARM toolchain
1513 which used them for VFP. */
1514 if (reg
>= 16 && reg
<= 23)
1515 return ARM_F0_REGNUM
+ reg
- 16;
1517 /* New assignments for the FPA registers. */
1518 if (reg
>= 96 && reg
<= 103)
1519 return ARM_F0_REGNUM
+ reg
- 96;
1521 /* WMMX register assignments. */
1522 if (reg
>= 104 && reg
<= 111)
1523 return ARM_WCGR0_REGNUM
+ reg
- 104;
1525 if (reg
>= 112 && reg
<= 127)
1526 return ARM_WR0_REGNUM
+ reg
- 112;
1528 if (reg
>= 192 && reg
<= 199)
1529 return ARM_WC0_REGNUM
+ reg
- 192;
1534 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1536 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
1539 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
1541 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
1542 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
1544 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
1545 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
1547 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
1548 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
1550 if (reg
< NUM_GREGS
)
1551 return SIM_ARM_R0_REGNUM
+ reg
;
1554 if (reg
< NUM_FREGS
)
1555 return SIM_ARM_FP0_REGNUM
+ reg
;
1558 if (reg
< NUM_SREGS
)
1559 return SIM_ARM_FPS_REGNUM
+ reg
;
1562 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
1565 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1566 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1567 It is thought that this is is the floating-point register format on
1568 little-endian systems. */
1571 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
1572 void *dbl
, int endianess
)
1576 if (endianess
== BFD_ENDIAN_BIG
)
1577 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1579 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1581 floatformat_from_doublest (fmt
, &d
, dbl
);
1585 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
1590 floatformat_to_doublest (fmt
, ptr
, &d
);
1591 if (endianess
== BFD_ENDIAN_BIG
)
1592 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1594 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1599 condition_true (unsigned long cond
, unsigned long status_reg
)
1601 if (cond
== INST_AL
|| cond
== INST_NV
)
1607 return ((status_reg
& FLAG_Z
) != 0);
1609 return ((status_reg
& FLAG_Z
) == 0);
1611 return ((status_reg
& FLAG_C
) != 0);
1613 return ((status_reg
& FLAG_C
) == 0);
1615 return ((status_reg
& FLAG_N
) != 0);
1617 return ((status_reg
& FLAG_N
) == 0);
1619 return ((status_reg
& FLAG_V
) != 0);
1621 return ((status_reg
& FLAG_V
) == 0);
1623 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1625 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1627 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1629 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1631 return (((status_reg
& FLAG_Z
) == 0) &&
1632 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1634 return (((status_reg
& FLAG_Z
) != 0) ||
1635 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1640 /* Support routines for single stepping. Calculate the next PC value. */
1641 #define submask(x) ((1L << ((x) + 1)) - 1)
1642 #define bit(obj,st) (((obj) >> (st)) & 1)
1643 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1644 #define sbits(obj,st,fn) \
1645 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1646 #define BranchDest(addr,instr) \
1647 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1650 static unsigned long
1651 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
1652 unsigned long pc_val
, unsigned long status_reg
)
1654 unsigned long res
, shift
;
1655 int rm
= bits (inst
, 0, 3);
1656 unsigned long shifttype
= bits (inst
, 5, 6);
1660 int rs
= bits (inst
, 8, 11);
1661 shift
= (rs
== 15 ? pc_val
+ 8
1662 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
1665 shift
= bits (inst
, 7, 11);
1668 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1669 + (bit (inst
, 4) ? 12 : 8))
1670 : get_frame_register_unsigned (frame
, rm
));
1675 res
= shift
>= 32 ? 0 : res
<< shift
;
1679 res
= shift
>= 32 ? 0 : res
>> shift
;
1685 res
= ((res
& 0x80000000L
)
1686 ? ~((~res
) >> shift
) : res
>> shift
);
1689 case 3: /* ROR/RRX */
1692 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1694 res
= (res
>> shift
) | (res
<< (32 - shift
));
1698 return res
& 0xffffffff;
1701 /* Return number of 1-bits in VAL. */
1704 bitcount (unsigned long val
)
1707 for (nbits
= 0; val
!= 0; nbits
++)
1708 val
&= val
- 1; /* delete rightmost 1-bit in val */
1713 thumb_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1715 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1716 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1717 unsigned short inst1
= read_memory_unsigned_integer (pc
, 2);
1718 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1719 unsigned long offset
;
1721 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1725 /* Fetch the saved PC from the stack. It's stored above
1726 all of the other registers. */
1727 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
1728 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
1729 nextpc
= (CORE_ADDR
) read_memory_unsigned_integer (sp
+ offset
, 4);
1730 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1732 error (_("Infinite loop detected"));
1734 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1736 unsigned long status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
1737 unsigned long cond
= bits (inst1
, 8, 11);
1738 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1739 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1741 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1743 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1745 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link, and blx */
1747 unsigned short inst2
= read_memory_unsigned_integer (pc
+ 2, 2);
1748 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1749 nextpc
= pc_val
+ offset
;
1750 /* For BLX make sure to clear the low bits. */
1751 if (bits (inst2
, 11, 12) == 1)
1752 nextpc
= nextpc
& 0xfffffffc;
1754 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
1756 if (bits (inst1
, 3, 6) == 0x0f)
1759 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
1761 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1763 error (_("Infinite loop detected"));
1770 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1772 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1773 unsigned long pc_val
;
1774 unsigned long this_instr
;
1775 unsigned long status
;
1778 if (arm_frame_is_thumb (frame
))
1779 return thumb_get_next_pc (frame
, pc
);
1781 pc_val
= (unsigned long) pc
;
1782 this_instr
= read_memory_unsigned_integer (pc
, 4);
1783 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
1784 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1786 if (bits (this_instr
, 28, 31) == INST_NV
)
1787 switch (bits (this_instr
, 24, 27))
1792 /* Branch with Link and change to Thumb. */
1793 nextpc
= BranchDest (pc
, this_instr
);
1794 nextpc
|= bit (this_instr
, 24) << 1;
1796 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1798 error (_("Infinite loop detected"));
1804 /* Coprocessor register transfer. */
1805 if (bits (this_instr
, 12, 15) == 15)
1806 error (_("Invalid update to pc in instruction"));
1809 else if (condition_true (bits (this_instr
, 28, 31), status
))
1811 switch (bits (this_instr
, 24, 27))
1814 case 0x1: /* data processing */
1818 unsigned long operand1
, operand2
, result
= 0;
1822 if (bits (this_instr
, 12, 15) != 15)
1825 if (bits (this_instr
, 22, 25) == 0
1826 && bits (this_instr
, 4, 7) == 9) /* multiply */
1827 error (_("Invalid update to pc in instruction"));
1829 /* BX <reg>, BLX <reg> */
1830 if (bits (this_instr
, 4, 27) == 0x12fff1
1831 || bits (this_instr
, 4, 27) == 0x12fff3)
1833 rn
= bits (this_instr
, 0, 3);
1834 result
= (rn
== 15) ? pc_val
+ 8
1835 : get_frame_register_unsigned (frame
, rn
);
1836 nextpc
= (CORE_ADDR
) gdbarch_addr_bits_remove
1840 error (_("Infinite loop detected"));
1845 /* Multiply into PC */
1846 c
= (status
& FLAG_C
) ? 1 : 0;
1847 rn
= bits (this_instr
, 16, 19);
1848 operand1
= (rn
== 15) ? pc_val
+ 8
1849 : get_frame_register_unsigned (frame
, rn
);
1851 if (bit (this_instr
, 25))
1853 unsigned long immval
= bits (this_instr
, 0, 7);
1854 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1855 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1858 else /* operand 2 is a shifted register */
1859 operand2
= shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
);
1861 switch (bits (this_instr
, 21, 24))
1864 result
= operand1
& operand2
;
1868 result
= operand1
^ operand2
;
1872 result
= operand1
- operand2
;
1876 result
= operand2
- operand1
;
1880 result
= operand1
+ operand2
;
1884 result
= operand1
+ operand2
+ c
;
1888 result
= operand1
- operand2
+ c
;
1892 result
= operand2
- operand1
+ c
;
1898 case 0xb: /* tst, teq, cmp, cmn */
1899 result
= (unsigned long) nextpc
;
1903 result
= operand1
| operand2
;
1907 /* Always step into a function. */
1912 result
= operand1
& ~operand2
;
1919 nextpc
= (CORE_ADDR
) gdbarch_addr_bits_remove
1923 error (_("Infinite loop detected"));
1928 case 0x5: /* data transfer */
1931 if (bit (this_instr
, 20))
1934 if (bits (this_instr
, 12, 15) == 15)
1940 if (bit (this_instr
, 22))
1941 error (_("Invalid update to pc in instruction"));
1943 /* byte write to PC */
1944 rn
= bits (this_instr
, 16, 19);
1945 base
= (rn
== 15) ? pc_val
+ 8
1946 : get_frame_register_unsigned (frame
, rn
);
1947 if (bit (this_instr
, 24))
1950 int c
= (status
& FLAG_C
) ? 1 : 0;
1951 unsigned long offset
=
1952 (bit (this_instr
, 25)
1953 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
1954 : bits (this_instr
, 0, 11));
1956 if (bit (this_instr
, 23))
1961 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1964 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
1967 error (_("Infinite loop detected"));
1973 case 0x9: /* block transfer */
1974 if (bit (this_instr
, 20))
1977 if (bit (this_instr
, 15))
1982 if (bit (this_instr
, 23))
1985 unsigned long reglist
= bits (this_instr
, 0, 14);
1986 offset
= bitcount (reglist
) * 4;
1987 if (bit (this_instr
, 24)) /* pre */
1990 else if (bit (this_instr
, 24))
1994 unsigned long rn_val
=
1995 get_frame_register_unsigned (frame
,
1996 bits (this_instr
, 16, 19));
1998 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
2002 nextpc
= gdbarch_addr_bits_remove
2005 error (_("Infinite loop detected"));
2010 case 0xb: /* branch & link */
2011 case 0xa: /* branch */
2013 nextpc
= BranchDest (pc
, this_instr
);
2015 nextpc
= gdbarch_addr_bits_remove (gdbarch
, nextpc
);
2017 error (_("Infinite loop detected"));
2023 case 0xe: /* coproc ops */
2028 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
2036 /* single_step() is called just before we want to resume the inferior,
2037 if we want to single-step it but there is no hardware or kernel
2038 single-step support. We find the target of the coming instruction
2039 and breakpoint it. */
2042 arm_software_single_step (struct frame_info
*frame
)
2044 /* NOTE: This may insert the wrong breakpoint instruction when
2045 single-stepping over a mode-changing instruction, if the
2046 CPSR heuristics are used. */
2048 CORE_ADDR next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
2049 insert_single_step_breakpoint (next_pc
);
2054 #include "bfd-in2.h"
2055 #include "libcoff.h"
2058 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
2060 if (arm_pc_is_thumb (memaddr
))
2062 static asymbol
*asym
;
2063 static combined_entry_type ce
;
2064 static struct coff_symbol_struct csym
;
2065 static struct bfd fake_bfd
;
2066 static bfd_target fake_target
;
2068 if (csym
.native
== NULL
)
2070 /* Create a fake symbol vector containing a Thumb symbol.
2071 This is solely so that the code in print_insn_little_arm()
2072 and print_insn_big_arm() in opcodes/arm-dis.c will detect
2073 the presence of a Thumb symbol and switch to decoding
2074 Thumb instructions. */
2076 fake_target
.flavour
= bfd_target_coff_flavour
;
2077 fake_bfd
.xvec
= &fake_target
;
2078 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
2080 csym
.symbol
.the_bfd
= &fake_bfd
;
2081 csym
.symbol
.name
= "fake";
2082 asym
= (asymbol
*) & csym
;
2085 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
2086 info
->symbols
= &asym
;
2089 info
->symbols
= NULL
;
2091 if (info
->endian
== BFD_ENDIAN_BIG
)
2092 return print_insn_big_arm (memaddr
, info
);
2094 return print_insn_little_arm (memaddr
, info
);
2097 /* The following define instruction sequences that will cause ARM
2098 cpu's to take an undefined instruction trap. These are used to
2099 signal a breakpoint to GDB.
2101 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
2102 modes. A different instruction is required for each mode. The ARM
2103 cpu's can also be big or little endian. Thus four different
2104 instructions are needed to support all cases.
2106 Note: ARMv4 defines several new instructions that will take the
2107 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
2108 not in fact add the new instructions. The new undefined
2109 instructions in ARMv4 are all instructions that had no defined
2110 behaviour in earlier chips. There is no guarantee that they will
2111 raise an exception, but may be treated as NOP's. In practice, it
2112 may only safe to rely on instructions matching:
2114 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
2115 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
2116 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
2118 Even this may only true if the condition predicate is true. The
2119 following use a condition predicate of ALWAYS so it is always TRUE.
2121 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
2122 and NetBSD all use a software interrupt rather than an undefined
2123 instruction to force a trap. This can be handled by by the
2124 abi-specific code during establishment of the gdbarch vector. */
2126 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
2127 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
2128 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
2129 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
2131 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
2132 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
2133 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
2134 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
2136 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
2137 the program counter value to determine whether a 16-bit or 32-bit
2138 breakpoint should be used. It returns a pointer to a string of
2139 bytes that encode a breakpoint instruction, stores the length of
2140 the string to *lenptr, and adjusts the program counter (if
2141 necessary) to point to the actual memory location where the
2142 breakpoint should be inserted. */
2144 static const unsigned char *
2145 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
2147 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2149 if (arm_pc_is_thumb (*pcptr
))
2151 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
2152 *lenptr
= tdep
->thumb_breakpoint_size
;
2153 return tdep
->thumb_breakpoint
;
2157 *lenptr
= tdep
->arm_breakpoint_size
;
2158 return tdep
->arm_breakpoint
;
2162 /* Extract from an array REGBUF containing the (raw) register state a
2163 function return value of type TYPE, and copy that, in virtual
2164 format, into VALBUF. */
2167 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
2170 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
2172 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
2174 switch (gdbarch_tdep (gdbarch
)->fp_model
)
2178 /* The value is in register F0 in internal format. We need to
2179 extract the raw value and then convert it to the desired
2181 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
2183 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
2184 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
2185 valbuf
, gdbarch_byte_order (gdbarch
));
2189 case ARM_FLOAT_SOFT_FPA
:
2190 case ARM_FLOAT_SOFT_VFP
:
2191 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
2192 if (TYPE_LENGTH (type
) > 4)
2193 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
2194 valbuf
+ INT_REGISTER_SIZE
);
2199 (__FILE__
, __LINE__
,
2200 _("arm_extract_return_value: Floating point model not supported"));
2204 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2205 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2206 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2207 || TYPE_CODE (type
) == TYPE_CODE_PTR
2208 || TYPE_CODE (type
) == TYPE_CODE_REF
2209 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2211 /* If the the type is a plain integer, then the access is
2212 straight-forward. Otherwise we have to play around a bit more. */
2213 int len
= TYPE_LENGTH (type
);
2214 int regno
= ARM_A1_REGNUM
;
2219 /* By using store_unsigned_integer we avoid having to do
2220 anything special for small big-endian values. */
2221 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2222 store_unsigned_integer (valbuf
,
2223 (len
> INT_REGISTER_SIZE
2224 ? INT_REGISTER_SIZE
: len
),
2226 len
-= INT_REGISTER_SIZE
;
2227 valbuf
+= INT_REGISTER_SIZE
;
2232 /* For a structure or union the behaviour is as if the value had
2233 been stored to word-aligned memory and then loaded into
2234 registers with 32-bit load instruction(s). */
2235 int len
= TYPE_LENGTH (type
);
2236 int regno
= ARM_A1_REGNUM
;
2237 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2241 regcache_cooked_read (regs
, regno
++, tmpbuf
);
2242 memcpy (valbuf
, tmpbuf
,
2243 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2244 len
-= INT_REGISTER_SIZE
;
2245 valbuf
+= INT_REGISTER_SIZE
;
2251 /* Will a function return an aggregate type in memory or in a
2252 register? Return 0 if an aggregate type can be returned in a
2253 register, 1 if it must be returned in memory. */
2256 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2259 enum type_code code
;
2261 CHECK_TYPEDEF (type
);
2263 /* In the ARM ABI, "integer" like aggregate types are returned in
2264 registers. For an aggregate type to be integer like, its size
2265 must be less than or equal to INT_REGISTER_SIZE and the
2266 offset of each addressable subfield must be zero. Note that bit
2267 fields are not addressable, and all addressable subfields of
2268 unions always start at offset zero.
2270 This function is based on the behaviour of GCC 2.95.1.
2271 See: gcc/arm.c: arm_return_in_memory() for details.
2273 Note: All versions of GCC before GCC 2.95.2 do not set up the
2274 parameters correctly for a function returning the following
2275 structure: struct { float f;}; This should be returned in memory,
2276 not a register. Richard Earnshaw sent me a patch, but I do not
2277 know of any way to detect if a function like the above has been
2278 compiled with the correct calling convention. */
2280 /* All aggregate types that won't fit in a register must be returned
2282 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
2287 /* The AAPCS says all aggregates not larger than a word are returned
2289 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
2292 /* The only aggregate types that can be returned in a register are
2293 structs and unions. Arrays must be returned in memory. */
2294 code
= TYPE_CODE (type
);
2295 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2300 /* Assume all other aggregate types can be returned in a register.
2301 Run a check for structures, unions and arrays. */
2304 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2307 /* Need to check if this struct/union is "integer" like. For
2308 this to be true, its size must be less than or equal to
2309 INT_REGISTER_SIZE and the offset of each addressable
2310 subfield must be zero. Note that bit fields are not
2311 addressable, and unions always start at offset zero. If any
2312 of the subfields is a floating point type, the struct/union
2313 cannot be an integer type. */
2315 /* For each field in the object, check:
2316 1) Is it FP? --> yes, nRc = 1;
2317 2) Is it addressable (bitpos != 0) and
2318 not packed (bitsize == 0)?
2322 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2324 enum type_code field_type_code
;
2325 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, i
)));
2327 /* Is it a floating point type field? */
2328 if (field_type_code
== TYPE_CODE_FLT
)
2334 /* If bitpos != 0, then we have to care about it. */
2335 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2337 /* Bitfields are not addressable. If the field bitsize is
2338 zero, then the field is not packed. Hence it cannot be
2339 a bitfield or any other packed type. */
2340 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2352 /* Write into appropriate registers a function return value of type
2353 TYPE, given in virtual format. */
2356 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
2357 const gdb_byte
*valbuf
)
2359 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
2361 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2363 char buf
[MAX_REGISTER_SIZE
];
2365 switch (gdbarch_tdep (gdbarch
)->fp_model
)
2369 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
2370 gdbarch_byte_order (gdbarch
));
2371 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
2374 case ARM_FLOAT_SOFT_FPA
:
2375 case ARM_FLOAT_SOFT_VFP
:
2376 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
2377 if (TYPE_LENGTH (type
) > 4)
2378 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
2379 valbuf
+ INT_REGISTER_SIZE
);
2384 (__FILE__
, __LINE__
,
2385 _("arm_store_return_value: Floating point model not supported"));
2389 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2390 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2391 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2392 || TYPE_CODE (type
) == TYPE_CODE_PTR
2393 || TYPE_CODE (type
) == TYPE_CODE_REF
2394 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2396 if (TYPE_LENGTH (type
) <= 4)
2398 /* Values of one word or less are zero/sign-extended and
2400 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2401 LONGEST val
= unpack_long (type
, valbuf
);
2403 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, val
);
2404 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
2408 /* Integral values greater than one word are stored in consecutive
2409 registers starting with r0. This will always be a multiple of
2410 the regiser size. */
2411 int len
= TYPE_LENGTH (type
);
2412 int regno
= ARM_A1_REGNUM
;
2416 regcache_cooked_write (regs
, regno
++, valbuf
);
2417 len
-= INT_REGISTER_SIZE
;
2418 valbuf
+= INT_REGISTER_SIZE
;
2424 /* For a structure or union the behaviour is as if the value had
2425 been stored to word-aligned memory and then loaded into
2426 registers with 32-bit load instruction(s). */
2427 int len
= TYPE_LENGTH (type
);
2428 int regno
= ARM_A1_REGNUM
;
2429 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2433 memcpy (tmpbuf
, valbuf
,
2434 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2435 regcache_cooked_write (regs
, regno
++, tmpbuf
);
2436 len
-= INT_REGISTER_SIZE
;
2437 valbuf
+= INT_REGISTER_SIZE
;
2443 /* Handle function return values. */
2445 static enum return_value_convention
2446 arm_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2447 struct type
*valtype
, struct regcache
*regcache
,
2448 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2450 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2452 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2453 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2454 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2456 if (tdep
->struct_return
== pcc_struct_return
2457 || arm_return_in_memory (gdbarch
, valtype
))
2458 return RETURN_VALUE_STRUCT_CONVENTION
;
2462 arm_store_return_value (valtype
, regcache
, writebuf
);
2465 arm_extract_return_value (valtype
, regcache
, readbuf
);
2467 return RETURN_VALUE_REGISTER_CONVENTION
;
2472 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2475 char buf
[INT_REGISTER_SIZE
];
2476 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (frame
));
2478 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
2480 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2484 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
);
2488 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
2489 return the target PC. Otherwise return 0. */
2492 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
2496 CORE_ADDR start_addr
;
2498 /* Find the starting address and name of the function containing the PC. */
2499 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2502 /* If PC is in a Thumb call or return stub, return the address of the
2503 target PC, which is in a register. The thunk functions are called
2504 _call_via_xx, where x is the register name. The possible names
2505 are r0-r9, sl, fp, ip, sp, and lr. */
2506 if (strncmp (name
, "_call_via_", 10) == 0)
2508 /* Use the name suffix to determine which register contains the
2510 static char *table
[15] =
2511 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2512 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2515 int offset
= strlen (name
) - 2;
2517 for (regno
= 0; regno
<= 14; regno
++)
2518 if (strcmp (&name
[offset
], table
[regno
]) == 0)
2519 return get_frame_register_unsigned (frame
, regno
);
2522 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
2523 non-interworking calls to foo. We could decode the stubs
2524 to find the target but it's easier to use the symbol table. */
2525 namelen
= strlen (name
);
2526 if (name
[0] == '_' && name
[1] == '_'
2527 && ((namelen
> 2 + strlen ("_from_thumb")
2528 && strncmp (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb",
2529 strlen ("_from_thumb")) == 0)
2530 || (namelen
> 2 + strlen ("_from_arm")
2531 && strncmp (name
+ namelen
- strlen ("_from_arm"), "_from_arm",
2532 strlen ("_from_arm")) == 0)))
2535 int target_len
= namelen
- 2;
2536 struct minimal_symbol
*minsym
;
2537 struct objfile
*objfile
;
2538 struct obj_section
*sec
;
2540 if (name
[namelen
- 1] == 'b')
2541 target_len
-= strlen ("_from_thumb");
2543 target_len
-= strlen ("_from_arm");
2545 target_name
= alloca (target_len
+ 1);
2546 memcpy (target_name
, name
+ 2, target_len
);
2547 target_name
[target_len
] = '\0';
2549 sec
= find_pc_section (pc
);
2550 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
2551 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
2553 return SYMBOL_VALUE_ADDRESS (minsym
);
2558 return 0; /* not a stub */
2562 set_arm_command (char *args
, int from_tty
)
2564 printf_unfiltered (_("\
2565 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2566 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
2570 show_arm_command (char *args
, int from_tty
)
2572 cmd_show_list (showarmcmdlist
, from_tty
, "");
2576 arm_update_current_architecture (void)
2578 struct gdbarch_info info
;
2580 /* If the current architecture is not ARM, we have nothing to do. */
2581 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_arm
)
2584 /* Update the architecture. */
2585 gdbarch_info_init (&info
);
2587 if (!gdbarch_update_p (info
))
2588 internal_error (__FILE__
, __LINE__
, "could not update architecture");
2592 set_fp_model_sfunc (char *args
, int from_tty
,
2593 struct cmd_list_element
*c
)
2595 enum arm_float_model fp_model
;
2597 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
2598 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
2600 arm_fp_model
= fp_model
;
2604 if (fp_model
== ARM_FLOAT_LAST
)
2605 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
2608 arm_update_current_architecture ();
2612 show_fp_model (struct ui_file
*file
, int from_tty
,
2613 struct cmd_list_element
*c
, const char *value
)
2615 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2617 if (arm_fp_model
== ARM_FLOAT_AUTO
2618 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2619 fprintf_filtered (file
, _("\
2620 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2621 fp_model_strings
[tdep
->fp_model
]);
2623 fprintf_filtered (file
, _("\
2624 The current ARM floating point model is \"%s\".\n"),
2625 fp_model_strings
[arm_fp_model
]);
2629 arm_set_abi (char *args
, int from_tty
,
2630 struct cmd_list_element
*c
)
2632 enum arm_abi_kind arm_abi
;
2634 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
2635 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
2637 arm_abi_global
= arm_abi
;
2641 if (arm_abi
== ARM_ABI_LAST
)
2642 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
2645 arm_update_current_architecture ();
2649 arm_show_abi (struct ui_file
*file
, int from_tty
,
2650 struct cmd_list_element
*c
, const char *value
)
2652 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2654 if (arm_abi_global
== ARM_ABI_AUTO
2655 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2656 fprintf_filtered (file
, _("\
2657 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2658 arm_abi_strings
[tdep
->arm_abi
]);
2660 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
2664 /* If the user changes the register disassembly style used for info
2665 register and other commands, we have to also switch the style used
2666 in opcodes for disassembly output. This function is run in the "set
2667 arm disassembly" command, and does that. */
2670 set_disassembly_style_sfunc (char *args
, int from_tty
,
2671 struct cmd_list_element
*c
)
2673 set_disassembly_style ();
2676 /* Return the ARM register name corresponding to register I. */
2678 arm_register_name (struct gdbarch
*gdbarch
, int i
)
2680 if (i
>= ARRAY_SIZE (arm_register_names
))
2681 /* These registers are only supported on targets which supply
2682 an XML description. */
2685 return arm_register_names
[i
];
2689 set_disassembly_style (void)
2693 /* Find the style that the user wants. */
2694 for (current
= 0; current
< num_disassembly_options
; current
++)
2695 if (disassembly_style
== valid_disassembly_styles
[current
])
2697 gdb_assert (current
< num_disassembly_options
);
2699 /* Synchronize the disassembler. */
2700 set_arm_regname_option (current
);
2703 /* Test whether the coff symbol specific value corresponds to a Thumb
2707 coff_sym_is_thumb (int val
)
2709 return (val
== C_THUMBEXT
||
2710 val
== C_THUMBSTAT
||
2711 val
== C_THUMBEXTFUNC
||
2712 val
== C_THUMBSTATFUNC
||
2713 val
== C_THUMBLABEL
);
2716 /* arm_coff_make_msymbol_special()
2717 arm_elf_make_msymbol_special()
2719 These functions test whether the COFF or ELF symbol corresponds to
2720 an address in thumb code, and set a "special" bit in a minimal
2721 symbol to indicate that it does. */
2724 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2726 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2728 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2730 MSYMBOL_SET_SPECIAL (msym
);
2734 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2736 if (coff_sym_is_thumb (val
))
2737 MSYMBOL_SET_SPECIAL (msym
);
2741 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2743 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
2745 /* If necessary, set the T bit. */
2749 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
2750 if (arm_pc_is_thumb (pc
))
2751 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
, val
| CPSR_T
);
2753 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
2754 val
& ~(ULONGEST
) CPSR_T
);
2758 static struct value
*
2759 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
2761 const int *reg_p
= baton
;
2762 return value_of_register (*reg_p
, frame
);
2765 static enum gdb_osabi
2766 arm_elf_osabi_sniffer (bfd
*abfd
)
2768 unsigned int elfosabi
;
2769 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2771 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2773 if (elfosabi
== ELFOSABI_ARM
)
2774 /* GNU tools use this value. Check note sections in this case,
2776 bfd_map_over_sections (abfd
,
2777 generic_elf_osabi_sniff_abi_tag_sections
,
2780 /* Anything else will be handled by the generic ELF sniffer. */
2785 /* Initialize the current architecture based on INFO. If possible,
2786 re-use an architecture from ARCHES, which is a list of
2787 architectures already created during this debugging session.
2789 Called e.g. at program startup, when reading a core file, and when
2790 reading a binary file. */
2792 static struct gdbarch
*
2793 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2795 struct gdbarch_tdep
*tdep
;
2796 struct gdbarch
*gdbarch
;
2797 struct gdbarch_list
*best_arch
;
2798 enum arm_abi_kind arm_abi
= arm_abi_global
;
2799 enum arm_float_model fp_model
= arm_fp_model
;
2800 struct tdesc_arch_data
*tdesc_data
= NULL
;
2802 int have_fpa_registers
= 1;
2804 /* Check any target description for validity. */
2805 if (tdesc_has_registers (info
.target_desc
))
2807 /* For most registers we require GDB's default names; but also allow
2808 the numeric names for sp / lr / pc, as a convenience. */
2809 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
2810 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
2811 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
2813 const struct tdesc_feature
*feature
;
2816 feature
= tdesc_find_feature (info
.target_desc
,
2817 "org.gnu.gdb.arm.core");
2818 if (feature
== NULL
)
2821 tdesc_data
= tdesc_data_alloc ();
2824 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
2825 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
2826 arm_register_names
[i
]);
2827 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2830 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2833 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2836 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2837 ARM_PS_REGNUM
, "cpsr");
2841 tdesc_data_cleanup (tdesc_data
);
2845 feature
= tdesc_find_feature (info
.target_desc
,
2846 "org.gnu.gdb.arm.fpa");
2847 if (feature
!= NULL
)
2850 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
2851 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
2852 arm_register_names
[i
]);
2855 tdesc_data_cleanup (tdesc_data
);
2860 have_fpa_registers
= 0;
2862 feature
= tdesc_find_feature (info
.target_desc
,
2863 "org.gnu.gdb.xscale.iwmmxt");
2864 if (feature
!= NULL
)
2866 static const char *const iwmmxt_names
[] = {
2867 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
2868 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
2869 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
2870 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
2874 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
2876 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
2877 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
2879 /* Check for the control registers, but do not fail if they
2881 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
2882 tdesc_numbered_register (feature
, tdesc_data
, i
,
2883 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
2885 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
2887 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
2888 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
2892 tdesc_data_cleanup (tdesc_data
);
2898 /* If we have an object to base this architecture on, try to determine
2901 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
2903 int ei_osabi
, e_flags
;
2905 switch (bfd_get_flavour (info
.abfd
))
2907 case bfd_target_aout_flavour
:
2908 /* Assume it's an old APCS-style ABI. */
2909 arm_abi
= ARM_ABI_APCS
;
2912 case bfd_target_coff_flavour
:
2913 /* Assume it's an old APCS-style ABI. */
2915 arm_abi
= ARM_ABI_APCS
;
2918 case bfd_target_elf_flavour
:
2919 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
2920 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2922 if (ei_osabi
== ELFOSABI_ARM
)
2924 /* GNU tools used to use this value, but do not for EABI
2925 objects. There's nowhere to tag an EABI version
2926 anyway, so assume APCS. */
2927 arm_abi
= ARM_ABI_APCS
;
2929 else if (ei_osabi
== ELFOSABI_NONE
)
2931 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
2935 case EF_ARM_EABI_UNKNOWN
:
2936 /* Assume GNU tools. */
2937 arm_abi
= ARM_ABI_APCS
;
2940 case EF_ARM_EABI_VER4
:
2941 case EF_ARM_EABI_VER5
:
2942 arm_abi
= ARM_ABI_AAPCS
;
2943 /* EABI binaries default to VFP float ordering. */
2944 if (fp_model
== ARM_FLOAT_AUTO
)
2945 fp_model
= ARM_FLOAT_SOFT_VFP
;
2949 /* Leave it as "auto". */
2950 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
2955 if (fp_model
== ARM_FLOAT_AUTO
)
2957 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2959 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
2962 /* Leave it as "auto". Strictly speaking this case
2963 means FPA, but almost nobody uses that now, and
2964 many toolchains fail to set the appropriate bits
2965 for the floating-point model they use. */
2967 case EF_ARM_SOFT_FLOAT
:
2968 fp_model
= ARM_FLOAT_SOFT_FPA
;
2970 case EF_ARM_VFP_FLOAT
:
2971 fp_model
= ARM_FLOAT_VFP
;
2973 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
2974 fp_model
= ARM_FLOAT_SOFT_VFP
;
2981 /* Leave it as "auto". */
2986 /* If there is already a candidate, use it. */
2987 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
2989 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
2991 if (arm_abi
!= ARM_ABI_AUTO
2992 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
2995 if (fp_model
!= ARM_FLOAT_AUTO
2996 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
2999 /* Found a match. */
3003 if (best_arch
!= NULL
)
3005 if (tdesc_data
!= NULL
)
3006 tdesc_data_cleanup (tdesc_data
);
3007 return best_arch
->gdbarch
;
3010 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
3011 gdbarch
= gdbarch_alloc (&info
, tdep
);
3013 /* Record additional information about the architecture we are defining.
3014 These are gdbarch discriminators, like the OSABI. */
3015 tdep
->arm_abi
= arm_abi
;
3016 tdep
->fp_model
= fp_model
;
3017 tdep
->have_fpa_registers
= have_fpa_registers
;
3020 switch (info
.byte_order
)
3022 case BFD_ENDIAN_BIG
:
3023 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
3024 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
3025 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
3026 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
3030 case BFD_ENDIAN_LITTLE
:
3031 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
3032 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
3033 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
3034 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
3039 internal_error (__FILE__
, __LINE__
,
3040 _("arm_gdbarch_init: bad byte order for float format"));
3043 /* On ARM targets char defaults to unsigned. */
3044 set_gdbarch_char_signed (gdbarch
, 0);
3046 /* This should be low enough for everything. */
3047 tdep
->lowest_pc
= 0x20;
3048 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
3050 /* The default, for both APCS and AAPCS, is to return small
3051 structures in registers. */
3052 tdep
->struct_return
= reg_struct_return
;
3054 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
3055 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
3057 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
3059 /* Frame handling. */
3060 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
3061 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
3062 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
3064 frame_base_set_default (gdbarch
, &arm_normal_base
);
3066 /* Address manipulation. */
3067 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
3068 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
3070 /* Advance PC across function entry code. */
3071 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
3073 /* Skip trampolines. */
3074 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
3076 /* The stack grows downward. */
3077 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3079 /* Breakpoint manipulation. */
3080 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
3082 /* Information about registers, etc. */
3083 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
3084 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
3085 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
3086 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
3087 set_gdbarch_register_type (gdbarch
, arm_register_type
);
3089 /* This "info float" is FPA-specific. Use the generic version if we
3091 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
3092 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
3094 /* Internal <-> external register number maps. */
3095 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
3096 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
3097 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
3099 set_gdbarch_register_name (gdbarch
, arm_register_name
);
3101 /* Returning results. */
3102 set_gdbarch_return_value (gdbarch
, arm_return_value
);
3105 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
3107 /* Minsymbol frobbing. */
3108 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
3109 set_gdbarch_coff_make_msymbol_special (gdbarch
,
3110 arm_coff_make_msymbol_special
);
3112 /* Virtual tables. */
3113 set_gdbarch_vbit_in_delta (gdbarch
, 1);
3115 /* Hook in the ABI-specific overrides, if they have been registered. */
3116 gdbarch_init_osabi (info
, gdbarch
);
3118 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
3120 /* Add some default predicates. */
3121 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
3122 dwarf2_append_unwinders (gdbarch
);
3123 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
3125 /* Now we have tuned the configuration, set a few final things,
3126 based on what the OS ABI has told us. */
3128 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
3129 binaries are always marked. */
3130 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
3131 tdep
->arm_abi
= ARM_ABI_APCS
;
3133 /* We used to default to FPA for generic ARM, but almost nobody
3134 uses that now, and we now provide a way for the user to force
3135 the model. So default to the most useful variant. */
3136 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
3137 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
3139 if (tdep
->jb_pc
>= 0)
3140 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
3142 /* Floating point sizes and format. */
3143 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
3144 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
3146 set_gdbarch_double_format
3147 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
3148 set_gdbarch_long_double_format
3149 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
3153 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
3154 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
3158 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
3160 /* Add standard register aliases. We add aliases even for those
3161 nanes which are used by the current architecture - it's simpler,
3162 and does no harm, since nothing ever lists user registers. */
3163 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
3164 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
3165 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
3171 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3173 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3178 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
3179 (unsigned long) tdep
->lowest_pc
);
3182 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
3185 _initialize_arm_tdep (void)
3187 struct ui_file
*stb
;
3189 struct cmd_list_element
*new_set
, *new_show
;
3190 const char *setname
;
3191 const char *setdesc
;
3192 const char *const *regnames
;
3194 static char *helptext
;
3195 char regdesc
[1024], *rdptr
= regdesc
;
3196 size_t rest
= sizeof (regdesc
);
3198 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
3200 /* Register an ELF OS ABI sniffer for ARM binaries. */
3201 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
3202 bfd_target_elf_flavour
,
3203 arm_elf_osabi_sniffer
);
3205 /* Get the number of possible sets of register names defined in opcodes. */
3206 num_disassembly_options
= get_arm_regname_num_options ();
3208 /* Add root prefix command for all "set arm"/"show arm" commands. */
3209 add_prefix_cmd ("arm", no_class
, set_arm_command
,
3210 _("Various ARM-specific commands."),
3211 &setarmcmdlist
, "set arm ", 0, &setlist
);
3213 add_prefix_cmd ("arm", no_class
, show_arm_command
,
3214 _("Various ARM-specific commands."),
3215 &showarmcmdlist
, "show arm ", 0, &showlist
);
3217 /* Sync the opcode insn printer with our register viewer. */
3218 parse_arm_disassembler_option ("reg-names-std");
3220 /* Initialize the array that will be passed to
3221 add_setshow_enum_cmd(). */
3222 valid_disassembly_styles
3223 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
3224 for (i
= 0; i
< num_disassembly_options
; i
++)
3226 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
3227 valid_disassembly_styles
[i
] = setname
;
3228 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
3231 /* When we find the default names, tell the disassembler to use
3233 if (!strcmp (setname
, "std"))
3235 disassembly_style
= setname
;
3236 set_arm_regname_option (i
);
3239 /* Mark the end of valid options. */
3240 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
3242 /* Create the help text. */
3243 stb
= mem_fileopen ();
3244 fprintf_unfiltered (stb
, "%s%s%s",
3245 _("The valid values are:\n"),
3247 _("The default is \"std\"."));
3248 helptext
= ui_file_xstrdup (stb
, &length
);
3249 ui_file_delete (stb
);
3251 add_setshow_enum_cmd("disassembler", no_class
,
3252 valid_disassembly_styles
, &disassembly_style
,
3253 _("Set the disassembly style."),
3254 _("Show the disassembly style."),
3256 set_disassembly_style_sfunc
,
3257 NULL
, /* FIXME: i18n: The disassembly style is \"%s\". */
3258 &setarmcmdlist
, &showarmcmdlist
);
3260 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
3261 _("Set usage of ARM 32-bit mode."),
3262 _("Show usage of ARM 32-bit mode."),
3263 _("When off, a 26-bit PC will be used."),
3265 NULL
, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
3266 &setarmcmdlist
, &showarmcmdlist
);
3268 /* Add a command to allow the user to force the FPU model. */
3269 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
3270 _("Set the floating point type."),
3271 _("Show the floating point type."),
3272 _("auto - Determine the FP typefrom the OS-ABI.\n\
3273 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
3274 fpa - FPA co-processor (GCC compiled).\n\
3275 softvfp - Software FP with pure-endian doubles.\n\
3276 vfp - VFP co-processor."),
3277 set_fp_model_sfunc
, show_fp_model
,
3278 &setarmcmdlist
, &showarmcmdlist
);
3280 /* Add a command to allow the user to force the ABI. */
3281 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
3284 NULL
, arm_set_abi
, arm_show_abi
,
3285 &setarmcmdlist
, &showarmcmdlist
);
3287 /* Debugging flag. */
3288 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
3289 _("Set ARM debugging."),
3290 _("Show ARM debugging."),
3291 _("When on, arm-specific debugging is enabled."),
3293 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
3294 &setdebuglist
, &showdebuglist
);