1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2015 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include <ctype.h> /* XXX for isupper (). */
29 #include "dis-asm.h" /* For register styles. */
31 #include "reggroups.h"
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
40 #include "dwarf2-frame.h"
42 #include "prologue-value.h"
44 #include "target-descriptions.h"
45 #include "user-regs.h"
50 #include "gdb/sim-arm.h"
53 #include "coff/internal.h"
59 #include "record-full.h"
61 #include "features/arm-with-m.c"
62 #include "features/arm-with-m-fpa-layout.c"
63 #include "features/arm-with-m-vfp-d16.c"
64 #include "features/arm-with-iwmmxt.c"
65 #include "features/arm-with-vfpv2.c"
66 #include "features/arm-with-vfpv3.c"
67 #include "features/arm-with-neon.c"
71 /* Macros for setting and testing a bit in a minimal symbol that marks
72 it as Thumb function. The MSB of the minimal symbol's "info" field
73 is used for this purpose.
75 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
76 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
78 #define MSYMBOL_SET_SPECIAL(msym) \
79 MSYMBOL_TARGET_FLAG_1 (msym) = 1
81 #define MSYMBOL_IS_SPECIAL(msym) \
82 MSYMBOL_TARGET_FLAG_1 (msym)
84 /* Per-objfile data used for mapping symbols. */
85 static const struct objfile_data
*arm_objfile_data_key
;
87 struct arm_mapping_symbol
92 typedef struct arm_mapping_symbol arm_mapping_symbol_s
;
93 DEF_VEC_O(arm_mapping_symbol_s
);
95 struct arm_per_objfile
97 VEC(arm_mapping_symbol_s
) **section_maps
;
100 /* The list of available "set arm ..." and "show arm ..." commands. */
101 static struct cmd_list_element
*setarmcmdlist
= NULL
;
102 static struct cmd_list_element
*showarmcmdlist
= NULL
;
104 /* The type of floating-point to use. Keep this in sync with enum
105 arm_float_model, and the help string in _initialize_arm_tdep. */
106 static const char *const fp_model_strings
[] =
116 /* A variable that can be configured by the user. */
117 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
118 static const char *current_fp_model
= "auto";
120 /* The ABI to use. Keep this in sync with arm_abi_kind. */
121 static const char *const arm_abi_strings
[] =
129 /* A variable that can be configured by the user. */
130 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
131 static const char *arm_abi_string
= "auto";
133 /* The execution mode to assume. */
134 static const char *const arm_mode_strings
[] =
142 static const char *arm_fallback_mode_string
= "auto";
143 static const char *arm_force_mode_string
= "auto";
145 /* Internal override of the execution mode. -1 means no override,
146 0 means override to ARM mode, 1 means override to Thumb mode.
147 The effect is the same as if arm_force_mode has been set by the
148 user (except the internal override has precedence over a user's
149 arm_force_mode override). */
150 static int arm_override_mode
= -1;
152 /* Number of different reg name sets (options). */
153 static int num_disassembly_options
;
155 /* The standard register names, and all the valid aliases for them. Note
156 that `fp', `sp' and `pc' are not added in this alias list, because they
157 have been added as builtin user registers in
158 std-regs.c:_initialize_frame_reg. */
163 } arm_register_aliases
[] = {
164 /* Basic register numbers. */
181 /* Synonyms (argument and variable registers). */
194 /* Other platform-specific names for r9. */
200 /* Names used by GCC (not listed in the ARM EABI). */
202 /* A special name from the older ATPCS. */
206 static const char *const arm_register_names
[] =
207 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
208 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
209 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
210 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
211 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
212 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
213 "fps", "cpsr" }; /* 24 25 */
215 /* Valid register name styles. */
216 static const char **valid_disassembly_styles
;
218 /* Disassembly style to use. Default to "std" register names. */
219 static const char *disassembly_style
;
221 /* This is used to keep the bfd arch_info in sync with the disassembly
223 static void set_disassembly_style_sfunc(char *, int,
224 struct cmd_list_element
*);
225 static void set_disassembly_style (void);
227 static void convert_from_extended (const struct floatformat
*, const void *,
229 static void convert_to_extended (const struct floatformat
*, void *,
232 static enum register_status
arm_neon_quad_read (struct gdbarch
*gdbarch
,
233 struct regcache
*regcache
,
234 int regnum
, gdb_byte
*buf
);
235 static void arm_neon_quad_write (struct gdbarch
*gdbarch
,
236 struct regcache
*regcache
,
237 int regnum
, const gdb_byte
*buf
);
239 struct arm_prologue_cache
241 /* The stack pointer at the time this frame was created; i.e. the
242 caller's stack pointer when this function was called. It is used
243 to identify this frame. */
246 /* The frame base for this frame is just prev_sp - frame size.
247 FRAMESIZE is the distance from the frame pointer to the
248 initial stack pointer. */
252 /* The register used to hold the frame pointer for this frame. */
255 /* Saved register offsets. */
256 struct trad_frame_saved_reg
*saved_regs
;
259 static CORE_ADDR
arm_analyze_prologue (struct gdbarch
*gdbarch
,
260 CORE_ADDR prologue_start
,
261 CORE_ADDR prologue_end
,
262 struct arm_prologue_cache
*cache
);
264 /* Architecture version for displaced stepping. This effects the behaviour of
265 certain instructions, and really should not be hard-wired. */
267 #define DISPLACED_STEPPING_ARCH_VERSION 5
269 /* Set to true if the 32-bit mode is in use. */
273 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
276 arm_psr_thumb_bit (struct gdbarch
*gdbarch
)
278 if (gdbarch_tdep (gdbarch
)->is_m
)
284 /* Determine if FRAME is executing in Thumb mode. */
287 arm_frame_is_thumb (struct frame_info
*frame
)
290 ULONGEST t_bit
= arm_psr_thumb_bit (get_frame_arch (frame
));
292 /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
293 directly (from a signal frame or dummy frame) or by interpreting
294 the saved LR (from a prologue or DWARF frame). So consult it and
295 trust the unwinders. */
296 cpsr
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
298 return (cpsr
& t_bit
) != 0;
301 /* Callback for VEC_lower_bound. */
304 arm_compare_mapping_symbols (const struct arm_mapping_symbol
*lhs
,
305 const struct arm_mapping_symbol
*rhs
)
307 return lhs
->value
< rhs
->value
;
310 /* Search for the mapping symbol covering MEMADDR. If one is found,
311 return its type. Otherwise, return 0. If START is non-NULL,
312 set *START to the location of the mapping symbol. */
315 arm_find_mapping_symbol (CORE_ADDR memaddr
, CORE_ADDR
*start
)
317 struct obj_section
*sec
;
319 /* If there are mapping symbols, consult them. */
320 sec
= find_pc_section (memaddr
);
323 struct arm_per_objfile
*data
;
324 VEC(arm_mapping_symbol_s
) *map
;
325 struct arm_mapping_symbol map_key
= { memaddr
- obj_section_addr (sec
),
329 data
= (struct arm_per_objfile
*) objfile_data (sec
->objfile
,
330 arm_objfile_data_key
);
333 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
334 if (!VEC_empty (arm_mapping_symbol_s
, map
))
336 struct arm_mapping_symbol
*map_sym
;
338 idx
= VEC_lower_bound (arm_mapping_symbol_s
, map
, &map_key
,
339 arm_compare_mapping_symbols
);
341 /* VEC_lower_bound finds the earliest ordered insertion
342 point. If the following symbol starts at this exact
343 address, we use that; otherwise, the preceding
344 mapping symbol covers this address. */
345 if (idx
< VEC_length (arm_mapping_symbol_s
, map
))
347 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
);
348 if (map_sym
->value
== map_key
.value
)
351 *start
= map_sym
->value
+ obj_section_addr (sec
);
352 return map_sym
->type
;
358 map_sym
= VEC_index (arm_mapping_symbol_s
, map
, idx
- 1);
360 *start
= map_sym
->value
+ obj_section_addr (sec
);
361 return map_sym
->type
;
370 /* Determine if the program counter specified in MEMADDR is in a Thumb
371 function. This function should be called for addresses unrelated to
372 any executing frame; otherwise, prefer arm_frame_is_thumb. */
375 arm_pc_is_thumb (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
377 struct bound_minimal_symbol sym
;
379 struct displaced_step_closure
* dsc
380 = get_displaced_step_closure_by_addr(memaddr
);
382 /* If checking the mode of displaced instruction in copy area, the mode
383 should be determined by instruction on the original address. */
387 fprintf_unfiltered (gdb_stdlog
,
388 "displaced: check mode of %.8lx instead of %.8lx\n",
389 (unsigned long) dsc
->insn_addr
,
390 (unsigned long) memaddr
);
391 memaddr
= dsc
->insn_addr
;
394 /* If bit 0 of the address is set, assume this is a Thumb address. */
395 if (IS_THUMB_ADDR (memaddr
))
398 /* Respect internal mode override if active. */
399 if (arm_override_mode
!= -1)
400 return arm_override_mode
;
402 /* If the user wants to override the symbol table, let him. */
403 if (strcmp (arm_force_mode_string
, "arm") == 0)
405 if (strcmp (arm_force_mode_string
, "thumb") == 0)
408 /* ARM v6-M and v7-M are always in Thumb mode. */
409 if (gdbarch_tdep (gdbarch
)->is_m
)
412 /* If there are mapping symbols, consult them. */
413 type
= arm_find_mapping_symbol (memaddr
, NULL
);
417 /* Thumb functions have a "special" bit set in minimal symbols. */
418 sym
= lookup_minimal_symbol_by_pc (memaddr
);
420 return (MSYMBOL_IS_SPECIAL (sym
.minsym
));
422 /* If the user wants to override the fallback mode, let them. */
423 if (strcmp (arm_fallback_mode_string
, "arm") == 0)
425 if (strcmp (arm_fallback_mode_string
, "thumb") == 0)
428 /* If we couldn't find any symbol, but we're talking to a running
429 target, then trust the current value of $cpsr. This lets
430 "display/i $pc" always show the correct mode (though if there is
431 a symbol table we will not reach here, so it still may not be
432 displayed in the mode it will be executed). */
433 if (target_has_registers
)
434 return arm_frame_is_thumb (get_current_frame ());
436 /* Otherwise we're out of luck; we assume ARM. */
440 /* Remove useless bits from addresses in a running program. */
442 arm_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR val
)
444 /* On M-profile devices, do not strip the low bit from EXC_RETURN
445 (the magic exception return address). */
446 if (gdbarch_tdep (gdbarch
)->is_m
447 && (val
& 0xfffffff0) == 0xfffffff0)
451 return UNMAKE_THUMB_ADDR (val
);
453 return (val
& 0x03fffffc);
456 /* Return 1 if PC is the start of a compiler helper function which
457 can be safely ignored during prologue skipping. IS_THUMB is true
458 if the function is known to be a Thumb function due to the way it
461 skip_prologue_function (struct gdbarch
*gdbarch
, CORE_ADDR pc
, int is_thumb
)
463 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
464 struct bound_minimal_symbol msym
;
466 msym
= lookup_minimal_symbol_by_pc (pc
);
467 if (msym
.minsym
!= NULL
468 && BMSYMBOL_VALUE_ADDRESS (msym
) == pc
469 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
)
471 const char *name
= MSYMBOL_LINKAGE_NAME (msym
.minsym
);
473 /* The GNU linker's Thumb call stub to foo is named
475 if (strstr (name
, "_from_thumb") != NULL
)
478 /* On soft-float targets, __truncdfsf2 is called to convert promoted
479 arguments to their argument types in non-prototyped
481 if (startswith (name
, "__truncdfsf2"))
483 if (startswith (name
, "__aeabi_d2f"))
486 /* Internal functions related to thread-local storage. */
487 if (startswith (name
, "__tls_get_addr"))
489 if (startswith (name
, "__aeabi_read_tp"))
494 /* If we run against a stripped glibc, we may be unable to identify
495 special functions by name. Check for one important case,
496 __aeabi_read_tp, by comparing the *code* against the default
497 implementation (this is hand-written ARM assembler in glibc). */
500 && read_memory_unsigned_integer (pc
, 4, byte_order_for_code
)
501 == 0xe3e00a0f /* mov r0, #0xffff0fff */
502 && read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
)
503 == 0xe240f01f) /* sub pc, r0, #31 */
510 /* Support routines for instruction parsing. */
511 #define submask(x) ((1L << ((x) + 1)) - 1)
512 #define bit(obj,st) (((obj) >> (st)) & 1)
513 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
514 #define sbits(obj,st,fn) \
515 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
516 #define BranchDest(addr,instr) \
517 ((CORE_ADDR) (((unsigned long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
519 /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
520 the first 16-bit of instruction, and INSN2 is the second 16-bit of
522 #define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
523 ((bits ((insn1), 0, 3) << 12) \
524 | (bits ((insn1), 10, 10) << 11) \
525 | (bits ((insn2), 12, 14) << 8) \
526 | bits ((insn2), 0, 7))
528 /* Extract the immediate from instruction movw/movt of encoding A. INSN is
529 the 32-bit instruction. */
530 #define EXTRACT_MOVW_MOVT_IMM_A(insn) \
531 ((bits ((insn), 16, 19) << 12) \
532 | bits ((insn), 0, 11))
534 /* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
537 thumb_expand_immediate (unsigned int imm
)
539 unsigned int count
= imm
>> 7;
547 return (imm
& 0xff) | ((imm
& 0xff) << 16);
549 return ((imm
& 0xff) << 8) | ((imm
& 0xff) << 24);
551 return (imm
& 0xff) | ((imm
& 0xff) << 8)
552 | ((imm
& 0xff) << 16) | ((imm
& 0xff) << 24);
555 return (0x80 | (imm
& 0x7f)) << (32 - count
);
558 /* Return 1 if the 16-bit Thumb instruction INST might change
559 control flow, 0 otherwise. */
562 thumb_instruction_changes_pc (unsigned short inst
)
564 if ((inst
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
567 if ((inst
& 0xf000) == 0xd000) /* conditional branch */
570 if ((inst
& 0xf800) == 0xe000) /* unconditional branch */
573 if ((inst
& 0xff00) == 0x4700) /* bx REG, blx REG */
576 if ((inst
& 0xff87) == 0x4687) /* mov pc, REG */
579 if ((inst
& 0xf500) == 0xb100) /* CBNZ or CBZ. */
585 /* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
586 might change control flow, 0 otherwise. */
589 thumb2_instruction_changes_pc (unsigned short inst1
, unsigned short inst2
)
591 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
593 /* Branches and miscellaneous control instructions. */
595 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
600 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
602 /* SUBS PC, LR, #imm8. */
605 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
607 /* Conditional branch. */
614 if ((inst1
& 0xfe50) == 0xe810)
616 /* Load multiple or RFE. */
618 if (bit (inst1
, 7) && !bit (inst1
, 8))
624 else if (!bit (inst1
, 7) && bit (inst1
, 8))
630 else if (bit (inst1
, 7) && bit (inst1
, 8))
635 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
644 if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
646 /* MOV PC or MOVS PC. */
650 if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
653 if (bits (inst1
, 0, 3) == 15)
659 if ((inst2
& 0x0fc0) == 0x0000)
665 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
671 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
680 /* Return 1 if the 16-bit Thumb instruction INSN restores SP in
681 epilogue, 0 otherwise. */
684 thumb_instruction_restores_sp (unsigned short insn
)
686 return (insn
== 0x46bd /* mov sp, r7 */
687 || (insn
& 0xff80) == 0xb000 /* add sp, imm */
688 || (insn
& 0xfe00) == 0xbc00); /* pop <registers> */
691 /* Analyze a Thumb prologue, looking for a recognizable stack frame
692 and frame pointer. Scan until we encounter a store that could
693 clobber the stack frame unexpectedly, or an unknown instruction.
694 Return the last address which is definitely safe to skip for an
695 initial breakpoint. */
698 thumb_analyze_prologue (struct gdbarch
*gdbarch
,
699 CORE_ADDR start
, CORE_ADDR limit
,
700 struct arm_prologue_cache
*cache
)
702 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
703 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
706 struct pv_area
*stack
;
707 struct cleanup
*back_to
;
709 CORE_ADDR unrecognized_pc
= 0;
711 for (i
= 0; i
< 16; i
++)
712 regs
[i
] = pv_register (i
, 0);
713 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
714 back_to
= make_cleanup_free_pv_area (stack
);
716 while (start
< limit
)
720 insn
= read_memory_unsigned_integer (start
, 2, byte_order_for_code
);
722 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
727 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
730 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
731 whether to save LR (R14). */
732 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
734 /* Calculate offsets of saved R0-R7 and LR. */
735 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
736 if (mask
& (1 << regno
))
738 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
740 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
743 else if ((insn
& 0xff80) == 0xb080) /* sub sp, #imm */
745 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
746 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
],
749 else if (thumb_instruction_restores_sp (insn
))
751 /* Don't scan past the epilogue. */
754 else if ((insn
& 0xf800) == 0xa800) /* add Rd, sp, #imm */
755 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[ARM_SP_REGNUM
],
757 else if ((insn
& 0xfe00) == 0x1c00 /* add Rd, Rn, #imm */
758 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
759 regs
[bits (insn
, 0, 2)] = pv_add_constant (regs
[bits (insn
, 3, 5)],
761 else if ((insn
& 0xf800) == 0x3000 /* add Rd, #imm */
762 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
763 regs
[bits (insn
, 8, 10)] = pv_add_constant (regs
[bits (insn
, 8, 10)],
765 else if ((insn
& 0xfe00) == 0x1800 /* add Rd, Rn, Rm */
766 && pv_is_register (regs
[bits (insn
, 6, 8)], ARM_SP_REGNUM
)
767 && pv_is_constant (regs
[bits (insn
, 3, 5)]))
768 regs
[bits (insn
, 0, 2)] = pv_add (regs
[bits (insn
, 3, 5)],
769 regs
[bits (insn
, 6, 8)]);
770 else if ((insn
& 0xff00) == 0x4400 /* add Rd, Rm */
771 && pv_is_constant (regs
[bits (insn
, 3, 6)]))
773 int rd
= (bit (insn
, 7) << 3) + bits (insn
, 0, 2);
774 int rm
= bits (insn
, 3, 6);
775 regs
[rd
] = pv_add (regs
[rd
], regs
[rm
]);
777 else if ((insn
& 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
779 int dst_reg
= (insn
& 0x7) + ((insn
& 0x80) >> 4);
780 int src_reg
= (insn
& 0x78) >> 3;
781 regs
[dst_reg
] = regs
[src_reg
];
783 else if ((insn
& 0xf800) == 0x9000) /* str rd, [sp, #off] */
785 /* Handle stores to the stack. Normally pushes are used,
786 but with GCC -mtpcs-frame, there may be other stores
787 in the prologue to create the frame. */
788 int regno
= (insn
>> 8) & 0x7;
791 offset
= (insn
& 0xff) << 2;
792 addr
= pv_add_constant (regs
[ARM_SP_REGNUM
], offset
);
794 if (pv_area_store_would_trash (stack
, addr
))
797 pv_area_store (stack
, addr
, 4, regs
[regno
]);
799 else if ((insn
& 0xf800) == 0x6000) /* str rd, [rn, #off] */
801 int rd
= bits (insn
, 0, 2);
802 int rn
= bits (insn
, 3, 5);
805 offset
= bits (insn
, 6, 10) << 2;
806 addr
= pv_add_constant (regs
[rn
], offset
);
808 if (pv_area_store_would_trash (stack
, addr
))
811 pv_area_store (stack
, addr
, 4, regs
[rd
]);
813 else if (((insn
& 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
814 || (insn
& 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
815 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
))
816 /* Ignore stores of argument registers to the stack. */
818 else if ((insn
& 0xf800) == 0xc800 /* ldmia Rn!, { registers } */
819 && pv_is_register (regs
[bits (insn
, 8, 10)], ARM_SP_REGNUM
))
820 /* Ignore block loads from the stack, potentially copying
821 parameters from memory. */
823 else if ((insn
& 0xf800) == 0x9800 /* ldr Rd, [Rn, #immed] */
824 || ((insn
& 0xf800) == 0x6800 /* ldr Rd, [sp, #immed] */
825 && pv_is_register (regs
[bits (insn
, 3, 5)], ARM_SP_REGNUM
)))
826 /* Similarly ignore single loads from the stack. */
828 else if ((insn
& 0xffc0) == 0x0000 /* lsls Rd, Rm, #0 */
829 || (insn
& 0xffc0) == 0x1c00) /* add Rd, Rn, #0 */
830 /* Skip register copies, i.e. saves to another register
831 instead of the stack. */
833 else if ((insn
& 0xf800) == 0x2000) /* movs Rd, #imm */
834 /* Recognize constant loads; even with small stacks these are necessary
836 regs
[bits (insn
, 8, 10)] = pv_constant (bits (insn
, 0, 7));
837 else if ((insn
& 0xf800) == 0x4800) /* ldr Rd, [pc, #imm] */
839 /* Constant pool loads, for the same reason. */
840 unsigned int constant
;
843 loc
= start
+ 4 + bits (insn
, 0, 7) * 4;
844 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
845 regs
[bits (insn
, 8, 10)] = pv_constant (constant
);
847 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instructions. */
849 unsigned short inst2
;
851 inst2
= read_memory_unsigned_integer (start
+ 2, 2,
852 byte_order_for_code
);
854 if ((insn
& 0xf800) == 0xf000 && (inst2
& 0xe800) == 0xe800)
856 /* BL, BLX. Allow some special function calls when
857 skipping the prologue; GCC generates these before
858 storing arguments to the stack. */
860 int j1
, j2
, imm1
, imm2
;
862 imm1
= sbits (insn
, 0, 10);
863 imm2
= bits (inst2
, 0, 10);
864 j1
= bit (inst2
, 13);
865 j2
= bit (inst2
, 11);
867 offset
= ((imm1
<< 12) + (imm2
<< 1));
868 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
870 nextpc
= start
+ 4 + offset
;
871 /* For BLX make sure to clear the low bits. */
872 if (bit (inst2
, 12) == 0)
873 nextpc
= nextpc
& 0xfffffffc;
875 if (!skip_prologue_function (gdbarch
, nextpc
,
876 bit (inst2
, 12) != 0))
880 else if ((insn
& 0xffd0) == 0xe900 /* stmdb Rn{!},
882 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
884 pv_t addr
= regs
[bits (insn
, 0, 3)];
887 if (pv_area_store_would_trash (stack
, addr
))
890 /* Calculate offsets of saved registers. */
891 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
892 if (inst2
& (1 << regno
))
894 addr
= pv_add_constant (addr
, -4);
895 pv_area_store (stack
, addr
, 4, regs
[regno
]);
899 regs
[bits (insn
, 0, 3)] = addr
;
902 else if ((insn
& 0xff50) == 0xe940 /* strd Rt, Rt2,
904 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
906 int regno1
= bits (inst2
, 12, 15);
907 int regno2
= bits (inst2
, 8, 11);
908 pv_t addr
= regs
[bits (insn
, 0, 3)];
910 offset
= inst2
& 0xff;
912 addr
= pv_add_constant (addr
, offset
);
914 addr
= pv_add_constant (addr
, -offset
);
916 if (pv_area_store_would_trash (stack
, addr
))
919 pv_area_store (stack
, addr
, 4, regs
[regno1
]);
920 pv_area_store (stack
, pv_add_constant (addr
, 4),
924 regs
[bits (insn
, 0, 3)] = addr
;
927 else if ((insn
& 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
928 && (inst2
& 0x0c00) == 0x0c00
929 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
931 int regno
= bits (inst2
, 12, 15);
932 pv_t addr
= regs
[bits (insn
, 0, 3)];
934 offset
= inst2
& 0xff;
936 addr
= pv_add_constant (addr
, offset
);
938 addr
= pv_add_constant (addr
, -offset
);
940 if (pv_area_store_would_trash (stack
, addr
))
943 pv_area_store (stack
, addr
, 4, regs
[regno
]);
946 regs
[bits (insn
, 0, 3)] = addr
;
949 else if ((insn
& 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
950 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
952 int regno
= bits (inst2
, 12, 15);
955 offset
= inst2
& 0xfff;
956 addr
= pv_add_constant (regs
[bits (insn
, 0, 3)], offset
);
958 if (pv_area_store_would_trash (stack
, addr
))
961 pv_area_store (stack
, addr
, 4, regs
[regno
]);
964 else if ((insn
& 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
965 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
966 /* Ignore stores of argument registers to the stack. */
969 else if ((insn
& 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
970 && (inst2
& 0x0d00) == 0x0c00
971 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
972 /* Ignore stores of argument registers to the stack. */
975 else if ((insn
& 0xffd0) == 0xe890 /* ldmia Rn[!],
977 && (inst2
& 0x8000) == 0x0000
978 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
979 /* Ignore block loads from the stack, potentially copying
980 parameters from memory. */
983 else if ((insn
& 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
985 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
986 /* Similarly ignore dual loads from the stack. */
989 else if ((insn
& 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
990 && (inst2
& 0x0d00) == 0x0c00
991 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
992 /* Similarly ignore single loads from the stack. */
995 else if ((insn
& 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
996 && pv_is_register (regs
[bits (insn
, 0, 3)], ARM_SP_REGNUM
))
997 /* Similarly ignore single loads from the stack. */
1000 else if ((insn
& 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
1001 && (inst2
& 0x8000) == 0x0000)
1003 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1004 | (bits (inst2
, 12, 14) << 8)
1005 | bits (inst2
, 0, 7));
1007 regs
[bits (inst2
, 8, 11)]
1008 = pv_add_constant (regs
[bits (insn
, 0, 3)],
1009 thumb_expand_immediate (imm
));
1012 else if ((insn
& 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
1013 && (inst2
& 0x8000) == 0x0000)
1015 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1016 | (bits (inst2
, 12, 14) << 8)
1017 | bits (inst2
, 0, 7));
1019 regs
[bits (inst2
, 8, 11)]
1020 = pv_add_constant (regs
[bits (insn
, 0, 3)], imm
);
1023 else if ((insn
& 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
1024 && (inst2
& 0x8000) == 0x0000)
1026 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1027 | (bits (inst2
, 12, 14) << 8)
1028 | bits (inst2
, 0, 7));
1030 regs
[bits (inst2
, 8, 11)]
1031 = pv_add_constant (regs
[bits (insn
, 0, 3)],
1032 - (CORE_ADDR
) thumb_expand_immediate (imm
));
1035 else if ((insn
& 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
1036 && (inst2
& 0x8000) == 0x0000)
1038 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1039 | (bits (inst2
, 12, 14) << 8)
1040 | bits (inst2
, 0, 7));
1042 regs
[bits (inst2
, 8, 11)]
1043 = pv_add_constant (regs
[bits (insn
, 0, 3)], - (CORE_ADDR
) imm
);
1046 else if ((insn
& 0xfbff) == 0xf04f) /* mov.w Rd, #const */
1048 unsigned int imm
= ((bits (insn
, 10, 10) << 11)
1049 | (bits (inst2
, 12, 14) << 8)
1050 | bits (inst2
, 0, 7));
1052 regs
[bits (inst2
, 8, 11)]
1053 = pv_constant (thumb_expand_immediate (imm
));
1056 else if ((insn
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1059 = EXTRACT_MOVW_MOVT_IMM_T (insn
, inst2
);
1061 regs
[bits (inst2
, 8, 11)] = pv_constant (imm
);
1064 else if (insn
== 0xea5f /* mov.w Rd,Rm */
1065 && (inst2
& 0xf0f0) == 0)
1067 int dst_reg
= (inst2
& 0x0f00) >> 8;
1068 int src_reg
= inst2
& 0xf;
1069 regs
[dst_reg
] = regs
[src_reg
];
1072 else if ((insn
& 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
1074 /* Constant pool loads. */
1075 unsigned int constant
;
1078 offset
= bits (inst2
, 0, 11);
1080 loc
= start
+ 4 + offset
;
1082 loc
= start
+ 4 - offset
;
1084 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1085 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1088 else if ((insn
& 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
1090 /* Constant pool loads. */
1091 unsigned int constant
;
1094 offset
= bits (inst2
, 0, 7) << 2;
1096 loc
= start
+ 4 + offset
;
1098 loc
= start
+ 4 - offset
;
1100 constant
= read_memory_unsigned_integer (loc
, 4, byte_order
);
1101 regs
[bits (inst2
, 12, 15)] = pv_constant (constant
);
1103 constant
= read_memory_unsigned_integer (loc
+ 4, 4, byte_order
);
1104 regs
[bits (inst2
, 8, 11)] = pv_constant (constant
);
1107 else if (thumb2_instruction_changes_pc (insn
, inst2
))
1109 /* Don't scan past anything that might change control flow. */
1114 /* The optimizer might shove anything into the prologue,
1115 so we just skip what we don't recognize. */
1116 unrecognized_pc
= start
;
1121 else if (thumb_instruction_changes_pc (insn
))
1123 /* Don't scan past anything that might change control flow. */
1128 /* The optimizer might shove anything into the prologue,
1129 so we just skip what we don't recognize. */
1130 unrecognized_pc
= start
;
1137 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1138 paddress (gdbarch
, start
));
1140 if (unrecognized_pc
== 0)
1141 unrecognized_pc
= start
;
1145 do_cleanups (back_to
);
1146 return unrecognized_pc
;
1149 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1151 /* Frame pointer is fp. Frame size is constant. */
1152 cache
->framereg
= ARM_FP_REGNUM
;
1153 cache
->framesize
= -regs
[ARM_FP_REGNUM
].k
;
1155 else if (pv_is_register (regs
[THUMB_FP_REGNUM
], ARM_SP_REGNUM
))
1157 /* Frame pointer is r7. Frame size is constant. */
1158 cache
->framereg
= THUMB_FP_REGNUM
;
1159 cache
->framesize
= -regs
[THUMB_FP_REGNUM
].k
;
1163 /* Try the stack pointer... this is a bit desperate. */
1164 cache
->framereg
= ARM_SP_REGNUM
;
1165 cache
->framesize
= -regs
[ARM_SP_REGNUM
].k
;
1168 for (i
= 0; i
< 16; i
++)
1169 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
1170 cache
->saved_regs
[i
].addr
= offset
;
1172 do_cleanups (back_to
);
1173 return unrecognized_pc
;
1177 /* Try to analyze the instructions starting from PC, which load symbol
1178 __stack_chk_guard. Return the address of instruction after loading this
1179 symbol, set the dest register number to *BASEREG, and set the size of
1180 instructions for loading symbol in OFFSET. Return 0 if instructions are
1184 arm_analyze_load_stack_chk_guard(CORE_ADDR pc
, struct gdbarch
*gdbarch
,
1185 unsigned int *destreg
, int *offset
)
1187 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1188 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1189 unsigned int low
, high
, address
;
1194 unsigned short insn1
1195 = read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
1197 if ((insn1
& 0xf800) == 0x4800) /* ldr Rd, #immed */
1199 *destreg
= bits (insn1
, 8, 10);
1201 address
= (pc
& 0xfffffffc) + 4 + (bits (insn1
, 0, 7) << 2);
1202 address
= read_memory_unsigned_integer (address
, 4,
1203 byte_order_for_code
);
1205 else if ((insn1
& 0xfbf0) == 0xf240) /* movw Rd, #const */
1207 unsigned short insn2
1208 = read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
1210 low
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1213 = read_memory_unsigned_integer (pc
+ 4, 2, byte_order_for_code
);
1215 = read_memory_unsigned_integer (pc
+ 6, 2, byte_order_for_code
);
1217 /* movt Rd, #const */
1218 if ((insn1
& 0xfbc0) == 0xf2c0)
1220 high
= EXTRACT_MOVW_MOVT_IMM_T (insn1
, insn2
);
1221 *destreg
= bits (insn2
, 8, 11);
1223 address
= (high
<< 16 | low
);
1230 = read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
1232 if ((insn
& 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
1234 address
= bits (insn
, 0, 11) + pc
+ 8;
1235 address
= read_memory_unsigned_integer (address
, 4,
1236 byte_order_for_code
);
1238 *destreg
= bits (insn
, 12, 15);
1241 else if ((insn
& 0x0ff00000) == 0x03000000) /* movw Rd, #const */
1243 low
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1246 = read_memory_unsigned_integer (pc
+ 4, 4, byte_order_for_code
);
1248 if ((insn
& 0x0ff00000) == 0x03400000) /* movt Rd, #const */
1250 high
= EXTRACT_MOVW_MOVT_IMM_A (insn
);
1251 *destreg
= bits (insn
, 12, 15);
1253 address
= (high
<< 16 | low
);
1261 /* Try to skip a sequence of instructions used for stack protector. If PC
1262 points to the first instruction of this sequence, return the address of
1263 first instruction after this sequence, otherwise, return original PC.
1265 On arm, this sequence of instructions is composed of mainly three steps,
1266 Step 1: load symbol __stack_chk_guard,
1267 Step 2: load from address of __stack_chk_guard,
1268 Step 3: store it to somewhere else.
1270 Usually, instructions on step 2 and step 3 are the same on various ARM
1271 architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
1272 on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
1273 instructions in step 1 vary from different ARM architectures. On ARMv7,
1276 movw Rn, #:lower16:__stack_chk_guard
1277 movt Rn, #:upper16:__stack_chk_guard
1284 .word __stack_chk_guard
1286 Since ldr/str is a very popular instruction, we can't use them as
1287 'fingerprint' or 'signature' of stack protector sequence. Here we choose
1288 sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
1289 stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
1292 arm_skip_stack_protector(CORE_ADDR pc
, struct gdbarch
*gdbarch
)
1294 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1295 unsigned int basereg
;
1296 struct bound_minimal_symbol stack_chk_guard
;
1298 int is_thumb
= arm_pc_is_thumb (gdbarch
, pc
);
1301 /* Try to parse the instructions in Step 1. */
1302 addr
= arm_analyze_load_stack_chk_guard (pc
, gdbarch
,
1307 stack_chk_guard
= lookup_minimal_symbol_by_pc (addr
);
1308 /* ADDR must correspond to a symbol whose name is __stack_chk_guard.
1309 Otherwise, this sequence cannot be for stack protector. */
1310 if (stack_chk_guard
.minsym
== NULL
1311 || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard
.minsym
), "__stack_chk_guard"))
1316 unsigned int destreg
;
1318 = read_memory_unsigned_integer (pc
+ offset
, 2, byte_order_for_code
);
1320 /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
1321 if ((insn
& 0xf800) != 0x6800)
1323 if (bits (insn
, 3, 5) != basereg
)
1325 destreg
= bits (insn
, 0, 2);
1327 insn
= read_memory_unsigned_integer (pc
+ offset
+ 2, 2,
1328 byte_order_for_code
);
1329 /* Step 3: str Rd, [Rn, #immed], encoding T1. */
1330 if ((insn
& 0xf800) != 0x6000)
1332 if (destreg
!= bits (insn
, 0, 2))
1337 unsigned int destreg
;
1339 = read_memory_unsigned_integer (pc
+ offset
, 4, byte_order_for_code
);
1341 /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
1342 if ((insn
& 0x0e500000) != 0x04100000)
1344 if (bits (insn
, 16, 19) != basereg
)
1346 destreg
= bits (insn
, 12, 15);
1347 /* Step 3: str Rd, [Rn, #immed], encoding A1. */
1348 insn
= read_memory_unsigned_integer (pc
+ offset
+ 4,
1349 4, byte_order_for_code
);
1350 if ((insn
& 0x0e500000) != 0x04000000)
1352 if (bits (insn
, 12, 15) != destreg
)
1355 /* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
1358 return pc
+ offset
+ 4;
1360 return pc
+ offset
+ 8;
1363 /* Advance the PC across any function entry prologue instructions to
1364 reach some "real" code.
1366 The APCS (ARM Procedure Call Standard) defines the following
1370 [stmfd sp!, {a1,a2,a3,a4}]
1371 stmfd sp!, {...,fp,ip,lr,pc}
1372 [stfe f7, [sp, #-12]!]
1373 [stfe f6, [sp, #-12]!]
1374 [stfe f5, [sp, #-12]!]
1375 [stfe f4, [sp, #-12]!]
1376 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn. */
1379 arm_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1381 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1383 CORE_ADDR func_addr
, limit_pc
;
1385 /* See if we can determine the end of the prologue via the symbol table.
1386 If so, then return either PC, or the PC after the prologue, whichever
1388 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1390 CORE_ADDR post_prologue_pc
1391 = skip_prologue_using_sal (gdbarch
, func_addr
);
1392 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1394 if (post_prologue_pc
)
1396 = arm_skip_stack_protector (post_prologue_pc
, gdbarch
);
1399 /* GCC always emits a line note before the prologue and another
1400 one after, even if the two are at the same address or on the
1401 same line. Take advantage of this so that we do not need to
1402 know every instruction that might appear in the prologue. We
1403 will have producer information for most binaries; if it is
1404 missing (e.g. for -gstabs), assuming the GNU tools. */
1405 if (post_prologue_pc
1407 || COMPUNIT_PRODUCER (cust
) == NULL
1408 || startswith (COMPUNIT_PRODUCER (cust
), "GNU ")
1409 || startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
1410 return post_prologue_pc
;
1412 if (post_prologue_pc
!= 0)
1414 CORE_ADDR analyzed_limit
;
1416 /* For non-GCC compilers, make sure the entire line is an
1417 acceptable prologue; GDB will round this function's
1418 return value up to the end of the following line so we
1419 can not skip just part of a line (and we do not want to).
1421 RealView does not treat the prologue specially, but does
1422 associate prologue code with the opening brace; so this
1423 lets us skip the first line if we think it is the opening
1425 if (arm_pc_is_thumb (gdbarch
, func_addr
))
1426 analyzed_limit
= thumb_analyze_prologue (gdbarch
, func_addr
,
1427 post_prologue_pc
, NULL
);
1429 analyzed_limit
= arm_analyze_prologue (gdbarch
, func_addr
,
1430 post_prologue_pc
, NULL
);
1432 if (analyzed_limit
!= post_prologue_pc
)
1435 return post_prologue_pc
;
1439 /* Can't determine prologue from the symbol table, need to examine
1442 /* Find an upper limit on the function prologue using the debug
1443 information. If the debug information could not be used to provide
1444 that bound, then use an arbitrary large number as the upper bound. */
1445 /* Like arm_scan_prologue, stop no later than pc + 64. */
1446 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1448 limit_pc
= pc
+ 64; /* Magic. */
1451 /* Check if this is Thumb code. */
1452 if (arm_pc_is_thumb (gdbarch
, pc
))
1453 return thumb_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1455 return arm_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
1459 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
1460 This function decodes a Thumb function prologue to determine:
1461 1) the size of the stack frame
1462 2) which registers are saved on it
1463 3) the offsets of saved regs
1464 4) the offset from the stack pointer to the frame pointer
1466 A typical Thumb function prologue would create this stack frame
1467 (offsets relative to FP)
1468 old SP -> 24 stack parameters
1471 R7 -> 0 local variables (16 bytes)
1472 SP -> -12 additional stack space (12 bytes)
1473 The frame size would thus be 36 bytes, and the frame offset would be
1474 12 bytes. The frame register is R7.
1476 The comments for thumb_skip_prolog() describe the algorithm we use
1477 to detect the end of the prolog. */
1481 thumb_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR prev_pc
,
1482 CORE_ADDR block_addr
, struct arm_prologue_cache
*cache
)
1484 CORE_ADDR prologue_start
;
1485 CORE_ADDR prologue_end
;
1487 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1490 /* See comment in arm_scan_prologue for an explanation of
1492 if (prologue_end
> prologue_start
+ 64)
1494 prologue_end
= prologue_start
+ 64;
1498 /* We're in the boondocks: we have no idea where the start of the
1502 prologue_end
= min (prologue_end
, prev_pc
);
1504 thumb_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1507 /* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */
1510 arm_instruction_changes_pc (uint32_t this_instr
)
1512 if (bits (this_instr
, 28, 31) == INST_NV
)
1513 /* Unconditional instructions. */
1514 switch (bits (this_instr
, 24, 27))
1518 /* Branch with Link and change to Thumb. */
1523 /* Coprocessor register transfer. */
1524 if (bits (this_instr
, 12, 15) == 15)
1525 error (_("Invalid update to pc in instruction"));
1531 switch (bits (this_instr
, 25, 27))
1534 if (bits (this_instr
, 23, 24) == 2 && bit (this_instr
, 20) == 0)
1536 /* Multiplies and extra load/stores. */
1537 if (bit (this_instr
, 4) == 1 && bit (this_instr
, 7) == 1)
1538 /* Neither multiplies nor extension load/stores are allowed
1542 /* Otherwise, miscellaneous instructions. */
1544 /* BX <reg>, BXJ <reg>, BLX <reg> */
1545 if (bits (this_instr
, 4, 27) == 0x12fff1
1546 || bits (this_instr
, 4, 27) == 0x12fff2
1547 || bits (this_instr
, 4, 27) == 0x12fff3)
1550 /* Other miscellaneous instructions are unpredictable if they
1554 /* Data processing instruction. Fall through. */
1557 if (bits (this_instr
, 12, 15) == 15)
1564 /* Media instructions and architecturally undefined instructions. */
1565 if (bits (this_instr
, 25, 27) == 3 && bit (this_instr
, 4) == 1)
1569 if (bit (this_instr
, 20) == 0)
1573 if (bits (this_instr
, 12, 15) == ARM_PC_REGNUM
)
1579 /* Load/store multiple. */
1580 if (bit (this_instr
, 20) == 1 && bit (this_instr
, 15) == 1)
1586 /* Branch and branch with link. */
1591 /* Coprocessor transfers or SWIs can not affect PC. */
1595 internal_error (__FILE__
, __LINE__
, _("bad value in switch"));
1599 /* Return 1 if the ARM instruction INSN restores SP in epilogue, 0
1603 arm_instruction_restores_sp (unsigned int insn
)
1605 if (bits (insn
, 28, 31) != INST_NV
)
1607 if ((insn
& 0x0df0f000) == 0x0080d000
1608 /* ADD SP (register or immediate). */
1609 || (insn
& 0x0df0f000) == 0x0040d000
1610 /* SUB SP (register or immediate). */
1611 || (insn
& 0x0ffffff0) == 0x01a0d000
1613 || (insn
& 0x0fff0000) == 0x08bd0000
1615 || (insn
& 0x0fff0000) == 0x049d0000)
1616 /* POP of a single register. */
1623 /* Analyze an ARM mode prologue starting at PROLOGUE_START and
1624 continuing no further than PROLOGUE_END. If CACHE is non-NULL,
1625 fill it in. Return the first address not recognized as a prologue
1628 We recognize all the instructions typically found in ARM prologues,
1629 plus harmless instructions which can be skipped (either for analysis
1630 purposes, or a more restrictive set that can be skipped when finding
1631 the end of the prologue). */
1634 arm_analyze_prologue (struct gdbarch
*gdbarch
,
1635 CORE_ADDR prologue_start
, CORE_ADDR prologue_end
,
1636 struct arm_prologue_cache
*cache
)
1638 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1639 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1641 CORE_ADDR offset
, current_pc
;
1642 pv_t regs
[ARM_FPS_REGNUM
];
1643 struct pv_area
*stack
;
1644 struct cleanup
*back_to
;
1645 CORE_ADDR unrecognized_pc
= 0;
1647 /* Search the prologue looking for instructions that set up the
1648 frame pointer, adjust the stack pointer, and save registers.
1650 Be careful, however, and if it doesn't look like a prologue,
1651 don't try to scan it. If, for instance, a frameless function
1652 begins with stmfd sp!, then we will tell ourselves there is
1653 a frame, which will confuse stack traceback, as well as "finish"
1654 and other operations that rely on a knowledge of the stack
1657 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1658 regs
[regno
] = pv_register (regno
, 0);
1659 stack
= make_pv_area (ARM_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1660 back_to
= make_cleanup_free_pv_area (stack
);
1662 for (current_pc
= prologue_start
;
1663 current_pc
< prologue_end
;
1667 = read_memory_unsigned_integer (current_pc
, 4, byte_order_for_code
);
1669 if (insn
== 0xe1a0c00d) /* mov ip, sp */
1671 regs
[ARM_IP_REGNUM
] = regs
[ARM_SP_REGNUM
];
1674 else if ((insn
& 0xfff00000) == 0xe2800000 /* add Rd, Rn, #n */
1675 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1677 unsigned imm
= insn
& 0xff; /* immediate value */
1678 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1679 int rd
= bits (insn
, 12, 15);
1680 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1681 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], imm
);
1684 else if ((insn
& 0xfff00000) == 0xe2400000 /* sub Rd, Rn, #n */
1685 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1687 unsigned imm
= insn
& 0xff; /* immediate value */
1688 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1689 int rd
= bits (insn
, 12, 15);
1690 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1691 regs
[rd
] = pv_add_constant (regs
[bits (insn
, 16, 19)], -imm
);
1694 else if ((insn
& 0xffff0fff) == 0xe52d0004) /* str Rd,
1697 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1699 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1700 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4,
1701 regs
[bits (insn
, 12, 15)]);
1704 else if ((insn
& 0xffff0000) == 0xe92d0000)
1705 /* stmfd sp!, {..., fp, ip, lr, pc}
1707 stmfd sp!, {a1, a2, a3, a4} */
1709 int mask
= insn
& 0xffff;
1711 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1714 /* Calculate offsets of saved registers. */
1715 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
1716 if (mask
& (1 << regno
))
1719 = pv_add_constant (regs
[ARM_SP_REGNUM
], -4);
1720 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 4, regs
[regno
]);
1723 else if ((insn
& 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
1724 || (insn
& 0xffff00f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */
1725 || (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
1727 /* No need to add this to saved_regs -- it's just an arg reg. */
1730 else if ((insn
& 0xffff0000) == 0xe5cd0000 /* strb rx,[sp,#n] */
1731 || (insn
& 0xffff00f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */
1732 || (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
1734 /* No need to add this to saved_regs -- it's just an arg reg. */
1737 else if ((insn
& 0xfff00000) == 0xe8800000 /* stm Rn,
1739 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1741 /* No need to add this to saved_regs -- it's just arg regs. */
1744 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
1746 unsigned imm
= insn
& 0xff; /* immediate value */
1747 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1748 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1749 regs
[ARM_FP_REGNUM
] = pv_add_constant (regs
[ARM_IP_REGNUM
], -imm
);
1751 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
1753 unsigned imm
= insn
& 0xff; /* immediate value */
1754 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
1755 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
1756 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -imm
);
1758 else if ((insn
& 0xffff7fff) == 0xed6d0103 /* stfe f?,
1760 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1762 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1765 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1766 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
1767 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12, regs
[regno
]);
1769 else if ((insn
& 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
1771 && gdbarch_tdep (gdbarch
)->have_fpa_registers
)
1773 int n_saved_fp_regs
;
1774 unsigned int fp_start_reg
, fp_bound_reg
;
1776 if (pv_area_store_would_trash (stack
, regs
[ARM_SP_REGNUM
]))
1779 if ((insn
& 0x800) == 0x800) /* N0 is set */
1781 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1782 n_saved_fp_regs
= 3;
1784 n_saved_fp_regs
= 1;
1788 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
1789 n_saved_fp_regs
= 2;
1791 n_saved_fp_regs
= 4;
1794 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
1795 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
1796 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
1798 regs
[ARM_SP_REGNUM
] = pv_add_constant (regs
[ARM_SP_REGNUM
], -12);
1799 pv_area_store (stack
, regs
[ARM_SP_REGNUM
], 12,
1800 regs
[fp_start_reg
++]);
1803 else if ((insn
& 0xff000000) == 0xeb000000 && cache
== NULL
) /* bl */
1805 /* Allow some special function calls when skipping the
1806 prologue; GCC generates these before storing arguments to
1808 CORE_ADDR dest
= BranchDest (current_pc
, insn
);
1810 if (skip_prologue_function (gdbarch
, dest
, 0))
1815 else if ((insn
& 0xf0000000) != 0xe0000000)
1816 break; /* Condition not true, exit early. */
1817 else if (arm_instruction_changes_pc (insn
))
1818 /* Don't scan past anything that might change control flow. */
1820 else if (arm_instruction_restores_sp (insn
))
1822 /* Don't scan past the epilogue. */
1825 else if ((insn
& 0xfe500000) == 0xe8100000 /* ldm */
1826 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1827 /* Ignore block loads from the stack, potentially copying
1828 parameters from memory. */
1830 else if ((insn
& 0xfc500000) == 0xe4100000
1831 && pv_is_register (regs
[bits (insn
, 16, 19)], ARM_SP_REGNUM
))
1832 /* Similarly ignore single loads from the stack. */
1834 else if ((insn
& 0xffff0ff0) == 0xe1a00000)
1835 /* MOV Rd, Rm. Skip register copies, i.e. saves to another
1836 register instead of the stack. */
1840 /* The optimizer might shove anything into the prologue, if
1841 we build up cache (cache != NULL) from scanning prologue,
1842 we just skip what we don't recognize and scan further to
1843 make cache as complete as possible. However, if we skip
1844 prologue, we'll stop immediately on unrecognized
1846 unrecognized_pc
= current_pc
;
1854 if (unrecognized_pc
== 0)
1855 unrecognized_pc
= current_pc
;
1859 int framereg
, framesize
;
1861 /* The frame size is just the distance from the frame register
1862 to the original stack pointer. */
1863 if (pv_is_register (regs
[ARM_FP_REGNUM
], ARM_SP_REGNUM
))
1865 /* Frame pointer is fp. */
1866 framereg
= ARM_FP_REGNUM
;
1867 framesize
= -regs
[ARM_FP_REGNUM
].k
;
1871 /* Try the stack pointer... this is a bit desperate. */
1872 framereg
= ARM_SP_REGNUM
;
1873 framesize
= -regs
[ARM_SP_REGNUM
].k
;
1876 cache
->framereg
= framereg
;
1877 cache
->framesize
= framesize
;
1879 for (regno
= 0; regno
< ARM_FPS_REGNUM
; regno
++)
1880 if (pv_area_find_reg (stack
, gdbarch
, regno
, &offset
))
1881 cache
->saved_regs
[regno
].addr
= offset
;
1885 fprintf_unfiltered (gdb_stdlog
, "Prologue scan stopped at %s\n",
1886 paddress (gdbarch
, unrecognized_pc
));
1888 do_cleanups (back_to
);
1889 return unrecognized_pc
;
1893 arm_scan_prologue (struct frame_info
*this_frame
,
1894 struct arm_prologue_cache
*cache
)
1896 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1897 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1899 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
1900 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
1901 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
1902 pv_t regs
[ARM_FPS_REGNUM
];
1903 struct pv_area
*stack
;
1904 struct cleanup
*back_to
;
1907 /* Assume there is no frame until proven otherwise. */
1908 cache
->framereg
= ARM_SP_REGNUM
;
1909 cache
->framesize
= 0;
1911 /* Check for Thumb prologue. */
1912 if (arm_frame_is_thumb (this_frame
))
1914 thumb_scan_prologue (gdbarch
, prev_pc
, block_addr
, cache
);
1918 /* Find the function prologue. If we can't find the function in
1919 the symbol table, peek in the stack frame to find the PC. */
1920 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
1923 /* One way to find the end of the prologue (which works well
1924 for unoptimized code) is to do the following:
1926 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
1929 prologue_end = prev_pc;
1930 else if (sal.end < prologue_end)
1931 prologue_end = sal.end;
1933 This mechanism is very accurate so long as the optimizer
1934 doesn't move any instructions from the function body into the
1935 prologue. If this happens, sal.end will be the last
1936 instruction in the first hunk of prologue code just before
1937 the first instruction that the scheduler has moved from
1938 the body to the prologue.
1940 In order to make sure that we scan all of the prologue
1941 instructions, we use a slightly less accurate mechanism which
1942 may scan more than necessary. To help compensate for this
1943 lack of accuracy, the prologue scanning loop below contains
1944 several clauses which'll cause the loop to terminate early if
1945 an implausible prologue instruction is encountered.
1951 is a suitable endpoint since it accounts for the largest
1952 possible prologue plus up to five instructions inserted by
1955 if (prologue_end
> prologue_start
+ 64)
1957 prologue_end
= prologue_start
+ 64; /* See above. */
1962 /* We have no symbol information. Our only option is to assume this
1963 function has a standard stack frame and the normal frame register.
1964 Then, we can find the value of our frame pointer on entrance to
1965 the callee (or at the present moment if this is the innermost frame).
1966 The value stored there should be the address of the stmfd + 8. */
1967 CORE_ADDR frame_loc
;
1968 LONGEST return_value
;
1970 frame_loc
= get_frame_register_unsigned (this_frame
, ARM_FP_REGNUM
);
1971 if (!safe_read_memory_integer (frame_loc
, 4, byte_order
, &return_value
))
1975 prologue_start
= gdbarch_addr_bits_remove
1976 (gdbarch
, return_value
) - 8;
1977 prologue_end
= prologue_start
+ 64; /* See above. */
1981 if (prev_pc
< prologue_end
)
1982 prologue_end
= prev_pc
;
1984 arm_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
1987 static struct arm_prologue_cache
*
1988 arm_make_prologue_cache (struct frame_info
*this_frame
)
1991 struct arm_prologue_cache
*cache
;
1992 CORE_ADDR unwound_fp
;
1994 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
1995 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1997 arm_scan_prologue (this_frame
, cache
);
1999 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
2000 if (unwound_fp
== 0)
2003 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
2005 /* Calculate actual addresses of saved registers using offsets
2006 determined by arm_scan_prologue. */
2007 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
2008 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
2009 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
2014 /* Implementation of the stop_reason hook for arm_prologue frames. */
2016 static enum unwind_stop_reason
2017 arm_prologue_unwind_stop_reason (struct frame_info
*this_frame
,
2020 struct arm_prologue_cache
*cache
;
2023 if (*this_cache
== NULL
)
2024 *this_cache
= arm_make_prologue_cache (this_frame
);
2025 cache
= (struct arm_prologue_cache
*) *this_cache
;
2027 /* This is meant to halt the backtrace at "_start". */
2028 pc
= get_frame_pc (this_frame
);
2029 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
2030 return UNWIND_OUTERMOST
;
2032 /* If we've hit a wall, stop. */
2033 if (cache
->prev_sp
== 0)
2034 return UNWIND_OUTERMOST
;
2036 return UNWIND_NO_REASON
;
2039 /* Our frame ID for a normal frame is the current function's starting PC
2040 and the caller's SP when we were called. */
2043 arm_prologue_this_id (struct frame_info
*this_frame
,
2045 struct frame_id
*this_id
)
2047 struct arm_prologue_cache
*cache
;
2051 if (*this_cache
== NULL
)
2052 *this_cache
= arm_make_prologue_cache (this_frame
);
2053 cache
= (struct arm_prologue_cache
*) *this_cache
;
2055 /* Use function start address as part of the frame ID. If we cannot
2056 identify the start address (due to missing symbol information),
2057 fall back to just using the current PC. */
2058 pc
= get_frame_pc (this_frame
);
2059 func
= get_frame_func (this_frame
);
2063 id
= frame_id_build (cache
->prev_sp
, func
);
2067 static struct value
*
2068 arm_prologue_prev_register (struct frame_info
*this_frame
,
2072 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2073 struct arm_prologue_cache
*cache
;
2075 if (*this_cache
== NULL
)
2076 *this_cache
= arm_make_prologue_cache (this_frame
);
2077 cache
= (struct arm_prologue_cache
*) *this_cache
;
2079 /* If we are asked to unwind the PC, then we need to return the LR
2080 instead. The prologue may save PC, but it will point into this
2081 frame's prologue, not the next frame's resume location. Also
2082 strip the saved T bit. A valid LR may have the low bit set, but
2083 a valid PC never does. */
2084 if (prev_regnum
== ARM_PC_REGNUM
)
2088 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2089 return frame_unwind_got_constant (this_frame
, prev_regnum
,
2090 arm_addr_bits_remove (gdbarch
, lr
));
2093 /* SP is generally not saved to the stack, but this frame is
2094 identified by the next frame's stack pointer at the time of the call.
2095 The value was already reconstructed into PREV_SP. */
2096 if (prev_regnum
== ARM_SP_REGNUM
)
2097 return frame_unwind_got_constant (this_frame
, prev_regnum
, cache
->prev_sp
);
2099 /* The CPSR may have been changed by the call instruction and by the
2100 called function. The only bit we can reconstruct is the T bit,
2101 by checking the low bit of LR as of the call. This is a reliable
2102 indicator of Thumb-ness except for some ARM v4T pre-interworking
2103 Thumb code, which could get away with a clear low bit as long as
2104 the called function did not use bx. Guess that all other
2105 bits are unchanged; the condition flags are presumably lost,
2106 but the processor status is likely valid. */
2107 if (prev_regnum
== ARM_PS_REGNUM
)
2110 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
2112 cpsr
= get_frame_register_unsigned (this_frame
, prev_regnum
);
2113 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
2114 if (IS_THUMB_ADDR (lr
))
2118 return frame_unwind_got_constant (this_frame
, prev_regnum
, cpsr
);
2121 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
2125 struct frame_unwind arm_prologue_unwind
= {
2127 arm_prologue_unwind_stop_reason
,
2128 arm_prologue_this_id
,
2129 arm_prologue_prev_register
,
2131 default_frame_sniffer
2134 /* Maintain a list of ARM exception table entries per objfile, similar to the
2135 list of mapping symbols. We only cache entries for standard ARM-defined
2136 personality routines; the cache will contain only the frame unwinding
2137 instructions associated with the entry (not the descriptors). */
2139 static const struct objfile_data
*arm_exidx_data_key
;
2141 struct arm_exidx_entry
2146 typedef struct arm_exidx_entry arm_exidx_entry_s
;
2147 DEF_VEC_O(arm_exidx_entry_s
);
2149 struct arm_exidx_data
2151 VEC(arm_exidx_entry_s
) **section_maps
;
2155 arm_exidx_data_free (struct objfile
*objfile
, void *arg
)
2157 struct arm_exidx_data
*data
= (struct arm_exidx_data
*) arg
;
2160 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
2161 VEC_free (arm_exidx_entry_s
, data
->section_maps
[i
]);
2165 arm_compare_exidx_entries (const struct arm_exidx_entry
*lhs
,
2166 const struct arm_exidx_entry
*rhs
)
2168 return lhs
->addr
< rhs
->addr
;
2171 static struct obj_section
*
2172 arm_obj_section_from_vma (struct objfile
*objfile
, bfd_vma vma
)
2174 struct obj_section
*osect
;
2176 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
2177 if (bfd_get_section_flags (objfile
->obfd
,
2178 osect
->the_bfd_section
) & SEC_ALLOC
)
2180 bfd_vma start
, size
;
2181 start
= bfd_get_section_vma (objfile
->obfd
, osect
->the_bfd_section
);
2182 size
= bfd_get_section_size (osect
->the_bfd_section
);
2184 if (start
<= vma
&& vma
< start
+ size
)
2191 /* Parse contents of exception table and exception index sections
2192 of OBJFILE, and fill in the exception table entry cache.
2194 For each entry that refers to a standard ARM-defined personality
2195 routine, extract the frame unwinding instructions (from either
2196 the index or the table section). The unwinding instructions
2198 - extracting them from the rest of the table data
2199 - converting to host endianness
2200 - appending the implicit 0xb0 ("Finish") code
2202 The extracted and normalized instructions are stored for later
2203 retrieval by the arm_find_exidx_entry routine. */
2206 arm_exidx_new_objfile (struct objfile
*objfile
)
2208 struct cleanup
*cleanups
;
2209 struct arm_exidx_data
*data
;
2210 asection
*exidx
, *extab
;
2211 bfd_vma exidx_vma
= 0, extab_vma
= 0;
2212 bfd_size_type exidx_size
= 0, extab_size
= 0;
2213 gdb_byte
*exidx_data
= NULL
, *extab_data
= NULL
;
2216 /* If we've already touched this file, do nothing. */
2217 if (!objfile
|| objfile_data (objfile
, arm_exidx_data_key
) != NULL
)
2219 cleanups
= make_cleanup (null_cleanup
, NULL
);
2221 /* Read contents of exception table and index. */
2222 exidx
= bfd_get_section_by_name (objfile
->obfd
, ELF_STRING_ARM_unwind
);
2225 exidx_vma
= bfd_section_vma (objfile
->obfd
, exidx
);
2226 exidx_size
= bfd_get_section_size (exidx
);
2227 exidx_data
= (gdb_byte
*) xmalloc (exidx_size
);
2228 make_cleanup (xfree
, exidx_data
);
2230 if (!bfd_get_section_contents (objfile
->obfd
, exidx
,
2231 exidx_data
, 0, exidx_size
))
2233 do_cleanups (cleanups
);
2238 extab
= bfd_get_section_by_name (objfile
->obfd
, ".ARM.extab");
2241 extab_vma
= bfd_section_vma (objfile
->obfd
, extab
);
2242 extab_size
= bfd_get_section_size (extab
);
2243 extab_data
= (gdb_byte
*) xmalloc (extab_size
);
2244 make_cleanup (xfree
, extab_data
);
2246 if (!bfd_get_section_contents (objfile
->obfd
, extab
,
2247 extab_data
, 0, extab_size
))
2249 do_cleanups (cleanups
);
2254 /* Allocate exception table data structure. */
2255 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
, struct arm_exidx_data
);
2256 set_objfile_data (objfile
, arm_exidx_data_key
, data
);
2257 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
2258 objfile
->obfd
->section_count
,
2259 VEC(arm_exidx_entry_s
) *);
2261 /* Fill in exception table. */
2262 for (i
= 0; i
< exidx_size
/ 8; i
++)
2264 struct arm_exidx_entry new_exidx_entry
;
2265 bfd_vma idx
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8);
2266 bfd_vma val
= bfd_h_get_32 (objfile
->obfd
, exidx_data
+ i
* 8 + 4);
2267 bfd_vma addr
= 0, word
= 0;
2268 int n_bytes
= 0, n_words
= 0;
2269 struct obj_section
*sec
;
2270 gdb_byte
*entry
= NULL
;
2272 /* Extract address of start of function. */
2273 idx
= ((idx
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2274 idx
+= exidx_vma
+ i
* 8;
2276 /* Find section containing function and compute section offset. */
2277 sec
= arm_obj_section_from_vma (objfile
, idx
);
2280 idx
-= bfd_get_section_vma (objfile
->obfd
, sec
->the_bfd_section
);
2282 /* Determine address of exception table entry. */
2285 /* EXIDX_CANTUNWIND -- no exception table entry present. */
2287 else if ((val
& 0xff000000) == 0x80000000)
2289 /* Exception table entry embedded in .ARM.exidx
2290 -- must be short form. */
2294 else if (!(val
& 0x80000000))
2296 /* Exception table entry in .ARM.extab. */
2297 addr
= ((val
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2298 addr
+= exidx_vma
+ i
* 8 + 4;
2300 if (addr
>= extab_vma
&& addr
+ 4 <= extab_vma
+ extab_size
)
2302 word
= bfd_h_get_32 (objfile
->obfd
,
2303 extab_data
+ addr
- extab_vma
);
2306 if ((word
& 0xff000000) == 0x80000000)
2311 else if ((word
& 0xff000000) == 0x81000000
2312 || (word
& 0xff000000) == 0x82000000)
2316 n_words
= ((word
>> 16) & 0xff);
2318 else if (!(word
& 0x80000000))
2321 struct obj_section
*pers_sec
;
2322 int gnu_personality
= 0;
2324 /* Custom personality routine. */
2325 pers
= ((word
& 0x7fffffff) ^ 0x40000000) - 0x40000000;
2326 pers
= UNMAKE_THUMB_ADDR (pers
+ addr
- 4);
2328 /* Check whether we've got one of the variants of the
2329 GNU personality routines. */
2330 pers_sec
= arm_obj_section_from_vma (objfile
, pers
);
2333 static const char *personality
[] =
2335 "__gcc_personality_v0",
2336 "__gxx_personality_v0",
2337 "__gcj_personality_v0",
2338 "__gnu_objc_personality_v0",
2342 CORE_ADDR pc
= pers
+ obj_section_offset (pers_sec
);
2345 for (k
= 0; personality
[k
]; k
++)
2346 if (lookup_minimal_symbol_by_pc_name
2347 (pc
, personality
[k
], objfile
))
2349 gnu_personality
= 1;
2354 /* If so, the next word contains a word count in the high
2355 byte, followed by the same unwind instructions as the
2356 pre-defined forms. */
2358 && addr
+ 4 <= extab_vma
+ extab_size
)
2360 word
= bfd_h_get_32 (objfile
->obfd
,
2361 extab_data
+ addr
- extab_vma
);
2364 n_words
= ((word
>> 24) & 0xff);
2370 /* Sanity check address. */
2372 if (addr
< extab_vma
|| addr
+ 4 * n_words
> extab_vma
+ extab_size
)
2373 n_words
= n_bytes
= 0;
2375 /* The unwind instructions reside in WORD (only the N_BYTES least
2376 significant bytes are valid), followed by N_WORDS words in the
2377 extab section starting at ADDR. */
2378 if (n_bytes
|| n_words
)
2381 = (gdb_byte
*) obstack_alloc (&objfile
->objfile_obstack
,
2382 n_bytes
+ n_words
* 4 + 1);
2385 *p
++ = (gdb_byte
) ((word
>> (8 * n_bytes
)) & 0xff);
2389 word
= bfd_h_get_32 (objfile
->obfd
,
2390 extab_data
+ addr
- extab_vma
);
2393 *p
++ = (gdb_byte
) ((word
>> 24) & 0xff);
2394 *p
++ = (gdb_byte
) ((word
>> 16) & 0xff);
2395 *p
++ = (gdb_byte
) ((word
>> 8) & 0xff);
2396 *p
++ = (gdb_byte
) (word
& 0xff);
2399 /* Implied "Finish" to terminate the list. */
2403 /* Push entry onto vector. They are guaranteed to always
2404 appear in order of increasing addresses. */
2405 new_exidx_entry
.addr
= idx
;
2406 new_exidx_entry
.entry
= entry
;
2407 VEC_safe_push (arm_exidx_entry_s
,
2408 data
->section_maps
[sec
->the_bfd_section
->index
],
2412 do_cleanups (cleanups
);
2415 /* Search for the exception table entry covering MEMADDR. If one is found,
2416 return a pointer to its data. Otherwise, return 0. If START is non-NULL,
2417 set *START to the start of the region covered by this entry. */
2420 arm_find_exidx_entry (CORE_ADDR memaddr
, CORE_ADDR
*start
)
2422 struct obj_section
*sec
;
2424 sec
= find_pc_section (memaddr
);
2427 struct arm_exidx_data
*data
;
2428 VEC(arm_exidx_entry_s
) *map
;
2429 struct arm_exidx_entry map_key
= { memaddr
- obj_section_addr (sec
), 0 };
2432 data
= ((struct arm_exidx_data
*)
2433 objfile_data (sec
->objfile
, arm_exidx_data_key
));
2436 map
= data
->section_maps
[sec
->the_bfd_section
->index
];
2437 if (!VEC_empty (arm_exidx_entry_s
, map
))
2439 struct arm_exidx_entry
*map_sym
;
2441 idx
= VEC_lower_bound (arm_exidx_entry_s
, map
, &map_key
,
2442 arm_compare_exidx_entries
);
2444 /* VEC_lower_bound finds the earliest ordered insertion
2445 point. If the following symbol starts at this exact
2446 address, we use that; otherwise, the preceding
2447 exception table entry covers this address. */
2448 if (idx
< VEC_length (arm_exidx_entry_s
, map
))
2450 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
);
2451 if (map_sym
->addr
== map_key
.addr
)
2454 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2455 return map_sym
->entry
;
2461 map_sym
= VEC_index (arm_exidx_entry_s
, map
, idx
- 1);
2463 *start
= map_sym
->addr
+ obj_section_addr (sec
);
2464 return map_sym
->entry
;
2473 /* Given the current frame THIS_FRAME, and its associated frame unwinding
2474 instruction list from the ARM exception table entry ENTRY, allocate and
2475 return a prologue cache structure describing how to unwind this frame.
2477 Return NULL if the unwinding instruction list contains a "spare",
2478 "reserved" or "refuse to unwind" instruction as defined in section
2479 "9.3 Frame unwinding instructions" of the "Exception Handling ABI
2480 for the ARM Architecture" document. */
2482 static struct arm_prologue_cache
*
2483 arm_exidx_fill_cache (struct frame_info
*this_frame
, gdb_byte
*entry
)
2488 struct arm_prologue_cache
*cache
;
2489 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2490 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2496 /* Whenever we reload SP, we actually have to retrieve its
2497 actual value in the current frame. */
2500 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2502 int reg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2503 vsp
= get_frame_register_unsigned (this_frame
, reg
);
2507 CORE_ADDR addr
= cache
->saved_regs
[ARM_SP_REGNUM
].addr
;
2508 vsp
= get_frame_memory_unsigned (this_frame
, addr
, 4);
2514 /* Decode next unwind instruction. */
2517 if ((insn
& 0xc0) == 0)
2519 int offset
= insn
& 0x3f;
2520 vsp
+= (offset
<< 2) + 4;
2522 else if ((insn
& 0xc0) == 0x40)
2524 int offset
= insn
& 0x3f;
2525 vsp
-= (offset
<< 2) + 4;
2527 else if ((insn
& 0xf0) == 0x80)
2529 int mask
= ((insn
& 0xf) << 8) | *entry
++;
2532 /* The special case of an all-zero mask identifies
2533 "Refuse to unwind". We return NULL to fall back
2534 to the prologue analyzer. */
2538 /* Pop registers r4..r15 under mask. */
2539 for (i
= 0; i
< 12; i
++)
2540 if (mask
& (1 << i
))
2542 cache
->saved_regs
[4 + i
].addr
= vsp
;
2546 /* Special-case popping SP -- we need to reload vsp. */
2547 if (mask
& (1 << (ARM_SP_REGNUM
- 4)))
2550 else if ((insn
& 0xf0) == 0x90)
2552 int reg
= insn
& 0xf;
2554 /* Reserved cases. */
2555 if (reg
== ARM_SP_REGNUM
|| reg
== ARM_PC_REGNUM
)
2558 /* Set SP from another register and mark VSP for reload. */
2559 cache
->saved_regs
[ARM_SP_REGNUM
] = cache
->saved_regs
[reg
];
2562 else if ((insn
& 0xf0) == 0xa0)
2564 int count
= insn
& 0x7;
2565 int pop_lr
= (insn
& 0x8) != 0;
2568 /* Pop r4..r[4+count]. */
2569 for (i
= 0; i
<= count
; i
++)
2571 cache
->saved_regs
[4 + i
].addr
= vsp
;
2575 /* If indicated by flag, pop LR as well. */
2578 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= vsp
;
2582 else if (insn
== 0xb0)
2584 /* We could only have updated PC by popping into it; if so, it
2585 will show up as address. Otherwise, copy LR into PC. */
2586 if (!trad_frame_addr_p (cache
->saved_regs
, ARM_PC_REGNUM
))
2587 cache
->saved_regs
[ARM_PC_REGNUM
]
2588 = cache
->saved_regs
[ARM_LR_REGNUM
];
2593 else if (insn
== 0xb1)
2595 int mask
= *entry
++;
2598 /* All-zero mask and mask >= 16 is "spare". */
2599 if (mask
== 0 || mask
>= 16)
2602 /* Pop r0..r3 under mask. */
2603 for (i
= 0; i
< 4; i
++)
2604 if (mask
& (1 << i
))
2606 cache
->saved_regs
[i
].addr
= vsp
;
2610 else if (insn
== 0xb2)
2612 ULONGEST offset
= 0;
2617 offset
|= (*entry
& 0x7f) << shift
;
2620 while (*entry
++ & 0x80);
2622 vsp
+= 0x204 + (offset
<< 2);
2624 else if (insn
== 0xb3)
2626 int start
= *entry
>> 4;
2627 int count
= (*entry
++) & 0xf;
2630 /* Only registers D0..D15 are valid here. */
2631 if (start
+ count
>= 16)
2634 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2635 for (i
= 0; i
<= count
; i
++)
2637 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2641 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2644 else if ((insn
& 0xf8) == 0xb8)
2646 int count
= insn
& 0x7;
2649 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2650 for (i
= 0; i
<= count
; i
++)
2652 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2656 /* Add an extra 4 bytes for FSTMFDX-style stack. */
2659 else if (insn
== 0xc6)
2661 int start
= *entry
>> 4;
2662 int count
= (*entry
++) & 0xf;
2665 /* Only registers WR0..WR15 are valid. */
2666 if (start
+ count
>= 16)
2669 /* Pop iwmmx registers WR[start]..WR[start+count]. */
2670 for (i
= 0; i
<= count
; i
++)
2672 cache
->saved_regs
[ARM_WR0_REGNUM
+ start
+ i
].addr
= vsp
;
2676 else if (insn
== 0xc7)
2678 int mask
= *entry
++;
2681 /* All-zero mask and mask >= 16 is "spare". */
2682 if (mask
== 0 || mask
>= 16)
2685 /* Pop iwmmx general-purpose registers WCGR0..WCGR3 under mask. */
2686 for (i
= 0; i
< 4; i
++)
2687 if (mask
& (1 << i
))
2689 cache
->saved_regs
[ARM_WCGR0_REGNUM
+ i
].addr
= vsp
;
2693 else if ((insn
& 0xf8) == 0xc0)
2695 int count
= insn
& 0x7;
2698 /* Pop iwmmx registers WR[10]..WR[10+count]. */
2699 for (i
= 0; i
<= count
; i
++)
2701 cache
->saved_regs
[ARM_WR0_REGNUM
+ 10 + i
].addr
= vsp
;
2705 else if (insn
== 0xc8)
2707 int start
= *entry
>> 4;
2708 int count
= (*entry
++) & 0xf;
2711 /* Only registers D0..D31 are valid. */
2712 if (start
+ count
>= 16)
2715 /* Pop VFP double-precision registers
2716 D[16+start]..D[16+start+count]. */
2717 for (i
= 0; i
<= count
; i
++)
2719 cache
->saved_regs
[ARM_D0_REGNUM
+ 16 + start
+ i
].addr
= vsp
;
2723 else if (insn
== 0xc9)
2725 int start
= *entry
>> 4;
2726 int count
= (*entry
++) & 0xf;
2729 /* Pop VFP double-precision registers D[start]..D[start+count]. */
2730 for (i
= 0; i
<= count
; i
++)
2732 cache
->saved_regs
[ARM_D0_REGNUM
+ start
+ i
].addr
= vsp
;
2736 else if ((insn
& 0xf8) == 0xd0)
2738 int count
= insn
& 0x7;
2741 /* Pop VFP double-precision registers D[8]..D[8+count]. */
2742 for (i
= 0; i
<= count
; i
++)
2744 cache
->saved_regs
[ARM_D0_REGNUM
+ 8 + i
].addr
= vsp
;
2750 /* Everything else is "spare". */
2755 /* If we restore SP from a register, assume this was the frame register.
2756 Otherwise just fall back to SP as frame register. */
2757 if (trad_frame_realreg_p (cache
->saved_regs
, ARM_SP_REGNUM
))
2758 cache
->framereg
= cache
->saved_regs
[ARM_SP_REGNUM
].realreg
;
2760 cache
->framereg
= ARM_SP_REGNUM
;
2762 /* Determine offset to previous frame. */
2764 = vsp
- get_frame_register_unsigned (this_frame
, cache
->framereg
);
2766 /* We already got the previous SP. */
2767 cache
->prev_sp
= vsp
;
2772 /* Unwinding via ARM exception table entries. Note that the sniffer
2773 already computes a filled-in prologue cache, which is then used
2774 with the same arm_prologue_this_id and arm_prologue_prev_register
2775 routines also used for prologue-parsing based unwinding. */
2778 arm_exidx_unwind_sniffer (const struct frame_unwind
*self
,
2779 struct frame_info
*this_frame
,
2780 void **this_prologue_cache
)
2782 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2783 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2784 CORE_ADDR addr_in_block
, exidx_region
, func_start
;
2785 struct arm_prologue_cache
*cache
;
2788 /* See if we have an ARM exception table entry covering this address. */
2789 addr_in_block
= get_frame_address_in_block (this_frame
);
2790 entry
= arm_find_exidx_entry (addr_in_block
, &exidx_region
);
2794 /* The ARM exception table does not describe unwind information
2795 for arbitrary PC values, but is guaranteed to be correct only
2796 at call sites. We have to decide here whether we want to use
2797 ARM exception table information for this frame, or fall back
2798 to using prologue parsing. (Note that if we have DWARF CFI,
2799 this sniffer isn't even called -- CFI is always preferred.)
2801 Before we make this decision, however, we check whether we
2802 actually have *symbol* information for the current frame.
2803 If not, prologue parsing would not work anyway, so we might
2804 as well use the exception table and hope for the best. */
2805 if (find_pc_partial_function (addr_in_block
, NULL
, &func_start
, NULL
))
2809 /* If the next frame is "normal", we are at a call site in this
2810 frame, so exception information is guaranteed to be valid. */
2811 if (get_next_frame (this_frame
)
2812 && get_frame_type (get_next_frame (this_frame
)) == NORMAL_FRAME
)
2815 /* We also assume exception information is valid if we're currently
2816 blocked in a system call. The system library is supposed to
2817 ensure this, so that e.g. pthread cancellation works.
2819 But before verifying the instruction at the point of call, make
2820 sure this_frame is actually making a call (or, said differently,
2821 that it is not the innermost frame). For that, we compare
2822 this_frame's PC vs this_frame's addr_in_block. If equal, it means
2823 there is no call (otherwise, the PC would be the return address,
2824 which is the instruction after the call). */
2826 if (get_frame_pc (this_frame
) != addr_in_block
)
2828 if (arm_frame_is_thumb (this_frame
))
2832 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 2, 2,
2833 byte_order_for_code
, &insn
)
2834 && (insn
& 0xff00) == 0xdf00 /* svc */)
2841 if (safe_read_memory_integer (get_frame_pc (this_frame
) - 4, 4,
2842 byte_order_for_code
, &insn
)
2843 && (insn
& 0x0f000000) == 0x0f000000 /* svc */)
2848 /* Bail out if we don't know that exception information is valid. */
2852 /* The ARM exception index does not mark the *end* of the region
2853 covered by the entry, and some functions will not have any entry.
2854 To correctly recognize the end of the covered region, the linker
2855 should have inserted dummy records with a CANTUNWIND marker.
2857 Unfortunately, current versions of GNU ld do not reliably do
2858 this, and thus we may have found an incorrect entry above.
2859 As a (temporary) sanity check, we only use the entry if it
2860 lies *within* the bounds of the function. Note that this check
2861 might reject perfectly valid entries that just happen to cover
2862 multiple functions; therefore this check ought to be removed
2863 once the linker is fixed. */
2864 if (func_start
> exidx_region
)
2868 /* Decode the list of unwinding instructions into a prologue cache.
2869 Note that this may fail due to e.g. a "refuse to unwind" code. */
2870 cache
= arm_exidx_fill_cache (this_frame
, entry
);
2874 *this_prologue_cache
= cache
;
2878 struct frame_unwind arm_exidx_unwind
= {
2880 default_frame_unwind_stop_reason
,
2881 arm_prologue_this_id
,
2882 arm_prologue_prev_register
,
2884 arm_exidx_unwind_sniffer
2887 /* Recognize GCC's trampoline for thumb call-indirect. If we are in a
2888 trampoline, return the target PC. Otherwise return 0.
2890 void call0a (char c, short s, int i, long l) {}
2894 (*pointer_to_call0a) (c, s, i, l);
2897 Instead of calling a stub library function _call_via_xx (xx is
2898 the register name), GCC may inline the trampoline in the object
2899 file as below (register r2 has the address of call0a).
2902 .type main, %function
2911 The trampoline 'bx r2' doesn't belong to main. */
2914 arm_skip_bx_reg (struct frame_info
*frame
, CORE_ADDR pc
)
2916 /* The heuristics of recognizing such trampoline is that FRAME is
2917 executing in Thumb mode and the instruction on PC is 'bx Rm'. */
2918 if (arm_frame_is_thumb (frame
))
2922 if (target_read_memory (pc
, buf
, 2) == 0)
2924 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2925 enum bfd_endian byte_order_for_code
2926 = gdbarch_byte_order_for_code (gdbarch
);
2928 = extract_unsigned_integer (buf
, 2, byte_order_for_code
);
2930 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
2933 = get_frame_register_unsigned (frame
, bits (insn
, 3, 6));
2935 /* Clear the LSB so that gdb core sets step-resume
2936 breakpoint at the right address. */
2937 return UNMAKE_THUMB_ADDR (dest
);
2945 static struct arm_prologue_cache
*
2946 arm_make_stub_cache (struct frame_info
*this_frame
)
2948 struct arm_prologue_cache
*cache
;
2950 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
2951 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2953 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, ARM_SP_REGNUM
);
2958 /* Our frame ID for a stub frame is the current SP and LR. */
2961 arm_stub_this_id (struct frame_info
*this_frame
,
2963 struct frame_id
*this_id
)
2965 struct arm_prologue_cache
*cache
;
2967 if (*this_cache
== NULL
)
2968 *this_cache
= arm_make_stub_cache (this_frame
);
2969 cache
= (struct arm_prologue_cache
*) *this_cache
;
2971 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
2975 arm_stub_unwind_sniffer (const struct frame_unwind
*self
,
2976 struct frame_info
*this_frame
,
2977 void **this_prologue_cache
)
2979 CORE_ADDR addr_in_block
;
2981 CORE_ADDR pc
, start_addr
;
2984 addr_in_block
= get_frame_address_in_block (this_frame
);
2985 pc
= get_frame_pc (this_frame
);
2986 if (in_plt_section (addr_in_block
)
2987 /* We also use the stub winder if the target memory is unreadable
2988 to avoid having the prologue unwinder trying to read it. */
2989 || target_read_memory (pc
, dummy
, 4) != 0)
2992 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0
2993 && arm_skip_bx_reg (this_frame
, pc
) != 0)
2999 struct frame_unwind arm_stub_unwind
= {
3001 default_frame_unwind_stop_reason
,
3003 arm_prologue_prev_register
,
3005 arm_stub_unwind_sniffer
3008 /* Put here the code to store, into CACHE->saved_regs, the addresses
3009 of the saved registers of frame described by THIS_FRAME. CACHE is
3012 static struct arm_prologue_cache
*
3013 arm_m_exception_cache (struct frame_info
*this_frame
)
3015 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3016 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3017 struct arm_prologue_cache
*cache
;
3018 CORE_ADDR unwound_sp
;
3021 cache
= FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache
);
3022 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3024 unwound_sp
= get_frame_register_unsigned (this_frame
,
3027 /* The hardware saves eight 32-bit words, comprising xPSR,
3028 ReturnAddress, LR (R14), R12, R3, R2, R1, R0. See details in
3029 "B1.5.6 Exception entry behavior" in
3030 "ARMv7-M Architecture Reference Manual". */
3031 cache
->saved_regs
[0].addr
= unwound_sp
;
3032 cache
->saved_regs
[1].addr
= unwound_sp
+ 4;
3033 cache
->saved_regs
[2].addr
= unwound_sp
+ 8;
3034 cache
->saved_regs
[3].addr
= unwound_sp
+ 12;
3035 cache
->saved_regs
[12].addr
= unwound_sp
+ 16;
3036 cache
->saved_regs
[14].addr
= unwound_sp
+ 20;
3037 cache
->saved_regs
[15].addr
= unwound_sp
+ 24;
3038 cache
->saved_regs
[ARM_PS_REGNUM
].addr
= unwound_sp
+ 28;
3040 /* If bit 9 of the saved xPSR is set, then there is a four-byte
3041 aligner between the top of the 32-byte stack frame and the
3042 previous context's stack pointer. */
3043 cache
->prev_sp
= unwound_sp
+ 32;
3044 if (safe_read_memory_integer (unwound_sp
+ 28, 4, byte_order
, &xpsr
)
3045 && (xpsr
& (1 << 9)) != 0)
3046 cache
->prev_sp
+= 4;
3051 /* Implementation of function hook 'this_id' in
3052 'struct frame_uwnind'. */
3055 arm_m_exception_this_id (struct frame_info
*this_frame
,
3057 struct frame_id
*this_id
)
3059 struct arm_prologue_cache
*cache
;
3061 if (*this_cache
== NULL
)
3062 *this_cache
= arm_m_exception_cache (this_frame
);
3063 cache
= (struct arm_prologue_cache
*) *this_cache
;
3065 /* Our frame ID for a stub frame is the current SP and LR. */
3066 *this_id
= frame_id_build (cache
->prev_sp
,
3067 get_frame_pc (this_frame
));
3070 /* Implementation of function hook 'prev_register' in
3071 'struct frame_uwnind'. */
3073 static struct value
*
3074 arm_m_exception_prev_register (struct frame_info
*this_frame
,
3078 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3079 struct arm_prologue_cache
*cache
;
3081 if (*this_cache
== NULL
)
3082 *this_cache
= arm_m_exception_cache (this_frame
);
3083 cache
= (struct arm_prologue_cache
*) *this_cache
;
3085 /* The value was already reconstructed into PREV_SP. */
3086 if (prev_regnum
== ARM_SP_REGNUM
)
3087 return frame_unwind_got_constant (this_frame
, prev_regnum
,
3090 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
3094 /* Implementation of function hook 'sniffer' in
3095 'struct frame_uwnind'. */
3098 arm_m_exception_unwind_sniffer (const struct frame_unwind
*self
,
3099 struct frame_info
*this_frame
,
3100 void **this_prologue_cache
)
3102 CORE_ADDR this_pc
= get_frame_pc (this_frame
);
3104 /* No need to check is_m; this sniffer is only registered for
3105 M-profile architectures. */
3107 /* Exception frames return to one of these magic PCs. Other values
3108 are not defined as of v7-M. See details in "B1.5.8 Exception
3109 return behavior" in "ARMv7-M Architecture Reference Manual". */
3110 if (this_pc
== 0xfffffff1 || this_pc
== 0xfffffff9
3111 || this_pc
== 0xfffffffd)
3117 /* Frame unwinder for M-profile exceptions. */
3119 struct frame_unwind arm_m_exception_unwind
=
3122 default_frame_unwind_stop_reason
,
3123 arm_m_exception_this_id
,
3124 arm_m_exception_prev_register
,
3126 arm_m_exception_unwind_sniffer
3130 arm_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
3132 struct arm_prologue_cache
*cache
;
3134 if (*this_cache
== NULL
)
3135 *this_cache
= arm_make_prologue_cache (this_frame
);
3136 cache
= (struct arm_prologue_cache
*) *this_cache
;
3138 return cache
->prev_sp
- cache
->framesize
;
3141 struct frame_base arm_normal_base
= {
3142 &arm_prologue_unwind
,
3143 arm_normal_frame_base
,
3144 arm_normal_frame_base
,
3145 arm_normal_frame_base
3148 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
3149 dummy frame. The frame ID's base needs to match the TOS value
3150 saved by save_dummy_frame_tos() and returned from
3151 arm_push_dummy_call, and the PC needs to match the dummy frame's
3154 static struct frame_id
3155 arm_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3157 return frame_id_build (get_frame_register_unsigned (this_frame
,
3159 get_frame_pc (this_frame
));
3162 /* Given THIS_FRAME, find the previous frame's resume PC (which will
3163 be used to construct the previous frame's ID, after looking up the
3164 containing function). */
3167 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3170 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
3171 return arm_addr_bits_remove (gdbarch
, pc
);
3175 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3177 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
3180 static struct value
*
3181 arm_dwarf2_prev_register (struct frame_info
*this_frame
, void **this_cache
,
3184 struct gdbarch
* gdbarch
= get_frame_arch (this_frame
);
3186 ULONGEST t_bit
= arm_psr_thumb_bit (gdbarch
);
3191 /* The PC is normally copied from the return column, which
3192 describes saves of LR. However, that version may have an
3193 extra bit set to indicate Thumb state. The bit is not
3195 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3196 return frame_unwind_got_constant (this_frame
, regnum
,
3197 arm_addr_bits_remove (gdbarch
, lr
));
3200 /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
3201 cpsr
= get_frame_register_unsigned (this_frame
, regnum
);
3202 lr
= frame_unwind_register_unsigned (this_frame
, ARM_LR_REGNUM
);
3203 if (IS_THUMB_ADDR (lr
))
3207 return frame_unwind_got_constant (this_frame
, regnum
, cpsr
);
3210 internal_error (__FILE__
, __LINE__
,
3211 _("Unexpected register %d"), regnum
);
3216 arm_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3217 struct dwarf2_frame_state_reg
*reg
,
3218 struct frame_info
*this_frame
)
3224 reg
->how
= DWARF2_FRAME_REG_FN
;
3225 reg
->loc
.fn
= arm_dwarf2_prev_register
;
3228 reg
->how
= DWARF2_FRAME_REG_CFA
;
3233 /* Implement the stack_frame_destroyed_p gdbarch method. */
3236 thumb_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3238 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3239 unsigned int insn
, insn2
;
3240 int found_return
= 0, found_stack_adjust
= 0;
3241 CORE_ADDR func_start
, func_end
;
3245 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3248 /* The epilogue is a sequence of instructions along the following lines:
3250 - add stack frame size to SP or FP
3251 - [if frame pointer used] restore SP from FP
3252 - restore registers from SP [may include PC]
3253 - a return-type instruction [if PC wasn't already restored]
3255 In a first pass, we scan forward from the current PC and verify the
3256 instructions we find as compatible with this sequence, ending in a
3259 However, this is not sufficient to distinguish indirect function calls
3260 within a function from indirect tail calls in the epilogue in some cases.
3261 Therefore, if we didn't already find any SP-changing instruction during
3262 forward scan, we add a backward scanning heuristic to ensure we actually
3263 are in the epilogue. */
3266 while (scan_pc
< func_end
&& !found_return
)
3268 if (target_read_memory (scan_pc
, buf
, 2))
3272 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3274 if ((insn
& 0xff80) == 0x4700) /* bx <Rm> */
3276 else if (insn
== 0x46f7) /* mov pc, lr */
3278 else if (thumb_instruction_restores_sp (insn
))
3280 if ((insn
& 0xff00) == 0xbd00) /* pop <registers, PC> */
3283 else if (thumb_insn_size (insn
) == 4) /* 32-bit Thumb-2 instruction */
3285 if (target_read_memory (scan_pc
, buf
, 2))
3289 insn2
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3291 if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3293 if (insn2
& 0x8000) /* <registers> include PC. */
3296 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3297 && (insn2
& 0x0fff) == 0x0b04)
3299 if ((insn2
& 0xf000) == 0xf000) /* <Rt> is PC. */
3302 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3303 && (insn2
& 0x0e00) == 0x0a00)
3315 /* Since any instruction in the epilogue sequence, with the possible
3316 exception of return itself, updates the stack pointer, we need to
3317 scan backwards for at most one instruction. Try either a 16-bit or
3318 a 32-bit instruction. This is just a heuristic, so we do not worry
3319 too much about false positives. */
3321 if (pc
- 4 < func_start
)
3323 if (target_read_memory (pc
- 4, buf
, 4))
3326 insn
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
3327 insn2
= extract_unsigned_integer (buf
+ 2, 2, byte_order_for_code
);
3329 if (thumb_instruction_restores_sp (insn2
))
3330 found_stack_adjust
= 1;
3331 else if (insn
== 0xe8bd) /* ldm.w sp!, <registers> */
3332 found_stack_adjust
= 1;
3333 else if (insn
== 0xf85d /* ldr.w <Rt>, [sp], #4 */
3334 && (insn2
& 0x0fff) == 0x0b04)
3335 found_stack_adjust
= 1;
3336 else if ((insn
& 0xffbf) == 0xecbd /* vldm sp!, <list> */
3337 && (insn2
& 0x0e00) == 0x0a00)
3338 found_stack_adjust
= 1;
3340 return found_stack_adjust
;
3343 /* Implement the stack_frame_destroyed_p gdbarch method. */
3346 arm_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3348 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3351 CORE_ADDR func_start
, func_end
;
3353 if (arm_pc_is_thumb (gdbarch
, pc
))
3354 return thumb_stack_frame_destroyed_p (gdbarch
, pc
);
3356 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
3359 /* We are in the epilogue if the previous instruction was a stack
3360 adjustment and the next instruction is a possible return (bx, mov
3361 pc, or pop). We could have to scan backwards to find the stack
3362 adjustment, or forwards to find the return, but this is a decent
3363 approximation. First scan forwards. */
3366 insn
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
3367 if (bits (insn
, 28, 31) != INST_NV
)
3369 if ((insn
& 0x0ffffff0) == 0x012fff10)
3372 else if ((insn
& 0x0ffffff0) == 0x01a0f000)
3375 else if ((insn
& 0x0fff0000) == 0x08bd0000
3376 && (insn
& 0x0000c000) != 0)
3377 /* POP (LDMIA), including PC or LR. */
3384 /* Scan backwards. This is just a heuristic, so do not worry about
3385 false positives from mode changes. */
3387 if (pc
< func_start
+ 4)
3390 insn
= read_memory_unsigned_integer (pc
- 4, 4, byte_order_for_code
);
3391 if (arm_instruction_restores_sp (insn
))
3398 /* When arguments must be pushed onto the stack, they go on in reverse
3399 order. The code below implements a FILO (stack) to do this. */
3404 struct stack_item
*prev
;
3408 static struct stack_item
*
3409 push_stack_item (struct stack_item
*prev
, const gdb_byte
*contents
, int len
)
3411 struct stack_item
*si
;
3412 si
= XNEW (struct stack_item
);
3413 si
->data
= (gdb_byte
*) xmalloc (len
);
3416 memcpy (si
->data
, contents
, len
);
3420 static struct stack_item
*
3421 pop_stack_item (struct stack_item
*si
)
3423 struct stack_item
*dead
= si
;
3431 /* Return the alignment (in bytes) of the given type. */
3434 arm_type_align (struct type
*t
)
3440 t
= check_typedef (t
);
3441 switch (TYPE_CODE (t
))
3444 /* Should never happen. */
3445 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
3449 case TYPE_CODE_ENUM
:
3453 case TYPE_CODE_RANGE
:
3455 case TYPE_CODE_CHAR
:
3456 case TYPE_CODE_BOOL
:
3457 return TYPE_LENGTH (t
);
3459 case TYPE_CODE_ARRAY
:
3460 if (TYPE_VECTOR (t
))
3462 /* Use the natural alignment for vector types (the same for
3463 scalar type), but the maximum alignment is 64-bit. */
3464 if (TYPE_LENGTH (t
) > 8)
3467 return TYPE_LENGTH (t
);
3470 return arm_type_align (TYPE_TARGET_TYPE (t
));
3471 case TYPE_CODE_COMPLEX
:
3472 return arm_type_align (TYPE_TARGET_TYPE (t
));
3474 case TYPE_CODE_STRUCT
:
3475 case TYPE_CODE_UNION
:
3477 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
3479 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
3487 /* Possible base types for a candidate for passing and returning in
3490 enum arm_vfp_cprc_base_type
3499 /* The length of one element of base type B. */
3502 arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b
)
3506 case VFP_CPRC_SINGLE
:
3508 case VFP_CPRC_DOUBLE
:
3510 case VFP_CPRC_VEC64
:
3512 case VFP_CPRC_VEC128
:
3515 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3520 /* The character ('s', 'd' or 'q') for the type of VFP register used
3521 for passing base type B. */
3524 arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b
)
3528 case VFP_CPRC_SINGLE
:
3530 case VFP_CPRC_DOUBLE
:
3532 case VFP_CPRC_VEC64
:
3534 case VFP_CPRC_VEC128
:
3537 internal_error (__FILE__
, __LINE__
, _("Invalid VFP CPRC type: %d."),
3542 /* Determine whether T may be part of a candidate for passing and
3543 returning in VFP registers, ignoring the limit on the total number
3544 of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the
3545 classification of the first valid component found; if it is not
3546 VFP_CPRC_UNKNOWN, all components must have the same classification
3547 as *BASE_TYPE. If it is found that T contains a type not permitted
3548 for passing and returning in VFP registers, a type differently
3549 classified from *BASE_TYPE, or two types differently classified
3550 from each other, return -1, otherwise return the total number of
3551 base-type elements found (possibly 0 in an empty structure or
3552 array). Vector types are not currently supported, matching the
3553 generic AAPCS support. */
3556 arm_vfp_cprc_sub_candidate (struct type
*t
,
3557 enum arm_vfp_cprc_base_type
*base_type
)
3559 t
= check_typedef (t
);
3560 switch (TYPE_CODE (t
))
3563 switch (TYPE_LENGTH (t
))
3566 if (*base_type
== VFP_CPRC_UNKNOWN
)
3567 *base_type
= VFP_CPRC_SINGLE
;
3568 else if (*base_type
!= VFP_CPRC_SINGLE
)
3573 if (*base_type
== VFP_CPRC_UNKNOWN
)
3574 *base_type
= VFP_CPRC_DOUBLE
;
3575 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3584 case TYPE_CODE_COMPLEX
:
3585 /* Arguments of complex T where T is one of the types float or
3586 double get treated as if they are implemented as:
3595 switch (TYPE_LENGTH (t
))
3598 if (*base_type
== VFP_CPRC_UNKNOWN
)
3599 *base_type
= VFP_CPRC_SINGLE
;
3600 else if (*base_type
!= VFP_CPRC_SINGLE
)
3605 if (*base_type
== VFP_CPRC_UNKNOWN
)
3606 *base_type
= VFP_CPRC_DOUBLE
;
3607 else if (*base_type
!= VFP_CPRC_DOUBLE
)
3616 case TYPE_CODE_ARRAY
:
3618 if (TYPE_VECTOR (t
))
3620 /* A 64-bit or 128-bit containerized vector type are VFP
3622 switch (TYPE_LENGTH (t
))
3625 if (*base_type
== VFP_CPRC_UNKNOWN
)
3626 *base_type
= VFP_CPRC_VEC64
;
3629 if (*base_type
== VFP_CPRC_UNKNOWN
)
3630 *base_type
= VFP_CPRC_VEC128
;
3641 count
= arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t
),
3645 if (TYPE_LENGTH (t
) == 0)
3647 gdb_assert (count
== 0);
3650 else if (count
== 0)
3652 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3653 gdb_assert ((TYPE_LENGTH (t
) % unitlen
) == 0);
3654 return TYPE_LENGTH (t
) / unitlen
;
3659 case TYPE_CODE_STRUCT
:
3664 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3666 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3668 if (sub_count
== -1)
3672 if (TYPE_LENGTH (t
) == 0)
3674 gdb_assert (count
== 0);
3677 else if (count
== 0)
3679 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3680 if (TYPE_LENGTH (t
) != unitlen
* count
)
3685 case TYPE_CODE_UNION
:
3690 for (i
= 0; i
< TYPE_NFIELDS (t
); i
++)
3692 int sub_count
= arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t
, i
),
3694 if (sub_count
== -1)
3696 count
= (count
> sub_count
? count
: sub_count
);
3698 if (TYPE_LENGTH (t
) == 0)
3700 gdb_assert (count
== 0);
3703 else if (count
== 0)
3705 unitlen
= arm_vfp_cprc_unit_length (*base_type
);
3706 if (TYPE_LENGTH (t
) != unitlen
* count
)
3718 /* Determine whether T is a VFP co-processor register candidate (CPRC)
3719 if passed to or returned from a non-variadic function with the VFP
3720 ABI in effect. Return 1 if it is, 0 otherwise. If it is, set
3721 *BASE_TYPE to the base type for T and *COUNT to the number of
3722 elements of that base type before returning. */
3725 arm_vfp_call_candidate (struct type
*t
, enum arm_vfp_cprc_base_type
*base_type
,
3728 enum arm_vfp_cprc_base_type b
= VFP_CPRC_UNKNOWN
;
3729 int c
= arm_vfp_cprc_sub_candidate (t
, &b
);
3730 if (c
<= 0 || c
> 4)
3737 /* Return 1 if the VFP ABI should be used for passing arguments to and
3738 returning values from a function of type FUNC_TYPE, 0
3742 arm_vfp_abi_for_function (struct gdbarch
*gdbarch
, struct type
*func_type
)
3744 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3745 /* Variadic functions always use the base ABI. Assume that functions
3746 without debug info are not variadic. */
3747 if (func_type
&& TYPE_VARARGS (check_typedef (func_type
)))
3749 /* The VFP ABI is only supported as a variant of AAPCS. */
3750 if (tdep
->arm_abi
!= ARM_ABI_AAPCS
)
3752 return gdbarch_tdep (gdbarch
)->fp_model
== ARM_FLOAT_VFP
;
3755 /* We currently only support passing parameters in integer registers, which
3756 conforms with GCC's default model, and VFP argument passing following
3757 the VFP variant of AAPCS. Several other variants exist and
3758 we should probably support some of them based on the selected ABI. */
3761 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3762 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
3763 struct value
**args
, CORE_ADDR sp
, int struct_return
,
3764 CORE_ADDR struct_addr
)
3766 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3770 struct stack_item
*si
= NULL
;
3773 unsigned vfp_regs_free
= (1 << 16) - 1;
3775 /* Determine the type of this function and whether the VFP ABI
3777 ftype
= check_typedef (value_type (function
));
3778 if (TYPE_CODE (ftype
) == TYPE_CODE_PTR
)
3779 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
3780 use_vfp_abi
= arm_vfp_abi_for_function (gdbarch
, ftype
);
3782 /* Set the return address. For the ARM, the return breakpoint is
3783 always at BP_ADDR. */
3784 if (arm_pc_is_thumb (gdbarch
, bp_addr
))
3786 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
3788 /* Walk through the list of args and determine how large a temporary
3789 stack is required. Need to take care here as structs may be
3790 passed on the stack, and we have to push them. */
3793 argreg
= ARM_A1_REGNUM
;
3796 /* The struct_return pointer occupies the first parameter
3797 passing register. */
3801 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = %s\n",
3802 gdbarch_register_name (gdbarch
, argreg
),
3803 paddress (gdbarch
, struct_addr
));
3804 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
3808 for (argnum
= 0; argnum
< nargs
; argnum
++)
3811 struct type
*arg_type
;
3812 struct type
*target_type
;
3813 enum type_code typecode
;
3814 const bfd_byte
*val
;
3816 enum arm_vfp_cprc_base_type vfp_base_type
;
3818 int may_use_core_reg
= 1;
3820 arg_type
= check_typedef (value_type (args
[argnum
]));
3821 len
= TYPE_LENGTH (arg_type
);
3822 target_type
= TYPE_TARGET_TYPE (arg_type
);
3823 typecode
= TYPE_CODE (arg_type
);
3824 val
= value_contents (args
[argnum
]);
3826 align
= arm_type_align (arg_type
);
3827 /* Round alignment up to a whole number of words. */
3828 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
3829 /* Different ABIs have different maximum alignments. */
3830 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
3832 /* The APCS ABI only requires word alignment. */
3833 align
= INT_REGISTER_SIZE
;
3837 /* The AAPCS requires at most doubleword alignment. */
3838 if (align
> INT_REGISTER_SIZE
* 2)
3839 align
= INT_REGISTER_SIZE
* 2;
3843 && arm_vfp_call_candidate (arg_type
, &vfp_base_type
,
3851 /* Because this is a CPRC it cannot go in a core register or
3852 cause a core register to be skipped for alignment.
3853 Either it goes in VFP registers and the rest of this loop
3854 iteration is skipped for this argument, or it goes on the
3855 stack (and the stack alignment code is correct for this
3857 may_use_core_reg
= 0;
3859 unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
3860 shift
= unit_length
/ 4;
3861 mask
= (1 << (shift
* vfp_base_count
)) - 1;
3862 for (regno
= 0; regno
< 16; regno
+= shift
)
3863 if (((vfp_regs_free
>> regno
) & mask
) == mask
)
3872 vfp_regs_free
&= ~(mask
<< regno
);
3873 reg_scaled
= regno
/ shift
;
3874 reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
3875 for (i
= 0; i
< vfp_base_count
; i
++)
3879 if (reg_char
== 'q')
3880 arm_neon_quad_write (gdbarch
, regcache
, reg_scaled
+ i
,
3881 val
+ i
* unit_length
);
3884 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d",
3885 reg_char
, reg_scaled
+ i
);
3886 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
3888 regcache_cooked_write (regcache
, regnum
,
3889 val
+ i
* unit_length
);
3896 /* This CPRC could not go in VFP registers, so all VFP
3897 registers are now marked as used. */
3902 /* Push stack padding for dowubleword alignment. */
3903 if (nstack
& (align
- 1))
3905 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
3906 nstack
+= INT_REGISTER_SIZE
;
3909 /* Doubleword aligned quantities must go in even register pairs. */
3910 if (may_use_core_reg
3911 && argreg
<= ARM_LAST_ARG_REGNUM
3912 && align
> INT_REGISTER_SIZE
3916 /* If the argument is a pointer to a function, and it is a
3917 Thumb function, create a LOCAL copy of the value and set
3918 the THUMB bit in it. */
3919 if (TYPE_CODE_PTR
== typecode
3920 && target_type
!= NULL
3921 && TYPE_CODE_FUNC
== TYPE_CODE (check_typedef (target_type
)))
3923 CORE_ADDR regval
= extract_unsigned_integer (val
, len
, byte_order
);
3924 if (arm_pc_is_thumb (gdbarch
, regval
))
3926 bfd_byte
*copy
= (bfd_byte
*) alloca (len
);
3927 store_unsigned_integer (copy
, len
, byte_order
,
3928 MAKE_THUMB_ADDR (regval
));
3933 /* Copy the argument to general registers or the stack in
3934 register-sized pieces. Large arguments are split between
3935 registers and stack. */
3938 int partial_len
= len
< INT_REGISTER_SIZE
? len
: INT_REGISTER_SIZE
;
3940 = extract_unsigned_integer (val
, partial_len
, byte_order
);
3942 if (may_use_core_reg
&& argreg
<= ARM_LAST_ARG_REGNUM
)
3944 /* The argument is being passed in a general purpose
3946 if (byte_order
== BFD_ENDIAN_BIG
)
3947 regval
<<= (INT_REGISTER_SIZE
- partial_len
) * 8;
3949 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
3951 gdbarch_register_name
3953 phex (regval
, INT_REGISTER_SIZE
));
3954 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3959 gdb_byte buf
[INT_REGISTER_SIZE
];
3961 memset (buf
, 0, sizeof (buf
));
3962 store_unsigned_integer (buf
, partial_len
, byte_order
, regval
);
3964 /* Push the arguments onto the stack. */
3966 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
3968 si
= push_stack_item (si
, buf
, INT_REGISTER_SIZE
);
3969 nstack
+= INT_REGISTER_SIZE
;
3976 /* If we have an odd number of words to push, then decrement the stack
3977 by one word now, so first stack argument will be dword aligned. */
3984 write_memory (sp
, si
->data
, si
->len
);
3985 si
= pop_stack_item (si
);
3988 /* Finally, update teh SP register. */
3989 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
3995 /* Always align the frame to an 8-byte boundary. This is required on
3996 some platforms and harmless on the rest. */
3999 arm_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
4001 /* Align the stack to eight bytes. */
4002 return sp
& ~ (CORE_ADDR
) 7;
4006 print_fpu_flags (struct ui_file
*file
, int flags
)
4008 if (flags
& (1 << 0))
4009 fputs_filtered ("IVO ", file
);
4010 if (flags
& (1 << 1))
4011 fputs_filtered ("DVZ ", file
);
4012 if (flags
& (1 << 2))
4013 fputs_filtered ("OFL ", file
);
4014 if (flags
& (1 << 3))
4015 fputs_filtered ("UFL ", file
);
4016 if (flags
& (1 << 4))
4017 fputs_filtered ("INX ", file
);
4018 fputc_filtered ('\n', file
);
4021 /* Print interesting information about the floating point processor
4022 (if present) or emulator. */
4024 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4025 struct frame_info
*frame
, const char *args
)
4027 unsigned long status
= get_frame_register_unsigned (frame
, ARM_FPS_REGNUM
);
4030 type
= (status
>> 24) & 127;
4031 if (status
& (1 << 31))
4032 fprintf_filtered (file
, _("Hardware FPU type %d\n"), type
);
4034 fprintf_filtered (file
, _("Software FPU type %d\n"), type
);
4035 /* i18n: [floating point unit] mask */
4036 fputs_filtered (_("mask: "), file
);
4037 print_fpu_flags (file
, status
>> 16);
4038 /* i18n: [floating point unit] flags */
4039 fputs_filtered (_("flags: "), file
);
4040 print_fpu_flags (file
, status
);
4043 /* Construct the ARM extended floating point type. */
4044 static struct type
*
4045 arm_ext_type (struct gdbarch
*gdbarch
)
4047 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4049 if (!tdep
->arm_ext_type
)
4051 = arch_float_type (gdbarch
, -1, "builtin_type_arm_ext",
4052 floatformats_arm_ext
);
4054 return tdep
->arm_ext_type
;
4057 static struct type
*
4058 arm_neon_double_type (struct gdbarch
*gdbarch
)
4060 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4062 if (tdep
->neon_double_type
== NULL
)
4064 struct type
*t
, *elem
;
4066 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_d",
4068 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4069 append_composite_type_field (t
, "u8", init_vector_type (elem
, 8));
4070 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4071 append_composite_type_field (t
, "u16", init_vector_type (elem
, 4));
4072 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4073 append_composite_type_field (t
, "u32", init_vector_type (elem
, 2));
4074 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4075 append_composite_type_field (t
, "u64", elem
);
4076 elem
= builtin_type (gdbarch
)->builtin_float
;
4077 append_composite_type_field (t
, "f32", init_vector_type (elem
, 2));
4078 elem
= builtin_type (gdbarch
)->builtin_double
;
4079 append_composite_type_field (t
, "f64", elem
);
4081 TYPE_VECTOR (t
) = 1;
4082 TYPE_NAME (t
) = "neon_d";
4083 tdep
->neon_double_type
= t
;
4086 return tdep
->neon_double_type
;
4089 /* FIXME: The vector types are not correctly ordered on big-endian
4090 targets. Just as s0 is the low bits of d0, d0[0] is also the low
4091 bits of d0 - regardless of what unit size is being held in d0. So
4092 the offset of the first uint8 in d0 is 7, but the offset of the
4093 first float is 4. This code works as-is for little-endian
4096 static struct type
*
4097 arm_neon_quad_type (struct gdbarch
*gdbarch
)
4099 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4101 if (tdep
->neon_quad_type
== NULL
)
4103 struct type
*t
, *elem
;
4105 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_neon_q",
4107 elem
= builtin_type (gdbarch
)->builtin_uint8
;
4108 append_composite_type_field (t
, "u8", init_vector_type (elem
, 16));
4109 elem
= builtin_type (gdbarch
)->builtin_uint16
;
4110 append_composite_type_field (t
, "u16", init_vector_type (elem
, 8));
4111 elem
= builtin_type (gdbarch
)->builtin_uint32
;
4112 append_composite_type_field (t
, "u32", init_vector_type (elem
, 4));
4113 elem
= builtin_type (gdbarch
)->builtin_uint64
;
4114 append_composite_type_field (t
, "u64", init_vector_type (elem
, 2));
4115 elem
= builtin_type (gdbarch
)->builtin_float
;
4116 append_composite_type_field (t
, "f32", init_vector_type (elem
, 4));
4117 elem
= builtin_type (gdbarch
)->builtin_double
;
4118 append_composite_type_field (t
, "f64", init_vector_type (elem
, 2));
4120 TYPE_VECTOR (t
) = 1;
4121 TYPE_NAME (t
) = "neon_q";
4122 tdep
->neon_quad_type
= t
;
4125 return tdep
->neon_quad_type
;
4128 /* Return the GDB type object for the "standard" data type of data in
4131 static struct type
*
4132 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
4134 int num_regs
= gdbarch_num_regs (gdbarch
);
4136 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
4137 && regnum
>= num_regs
&& regnum
< num_regs
+ 32)
4138 return builtin_type (gdbarch
)->builtin_float
;
4140 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
4141 && regnum
>= num_regs
+ 32 && regnum
< num_regs
+ 32 + 16)
4142 return arm_neon_quad_type (gdbarch
);
4144 /* If the target description has register information, we are only
4145 in this function so that we can override the types of
4146 double-precision registers for NEON. */
4147 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
4149 struct type
*t
= tdesc_register_type (gdbarch
, regnum
);
4151 if (regnum
>= ARM_D0_REGNUM
&& regnum
< ARM_D0_REGNUM
+ 32
4152 && TYPE_CODE (t
) == TYPE_CODE_FLT
4153 && gdbarch_tdep (gdbarch
)->have_neon
)
4154 return arm_neon_double_type (gdbarch
);
4159 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
4161 if (!gdbarch_tdep (gdbarch
)->have_fpa_registers
)
4162 return builtin_type (gdbarch
)->builtin_void
;
4164 return arm_ext_type (gdbarch
);
4166 else if (regnum
== ARM_SP_REGNUM
)
4167 return builtin_type (gdbarch
)->builtin_data_ptr
;
4168 else if (regnum
== ARM_PC_REGNUM
)
4169 return builtin_type (gdbarch
)->builtin_func_ptr
;
4170 else if (regnum
>= ARRAY_SIZE (arm_register_names
))
4171 /* These registers are only supported on targets which supply
4172 an XML description. */
4173 return builtin_type (gdbarch
)->builtin_int0
;
4175 return builtin_type (gdbarch
)->builtin_uint32
;
4178 /* Map a DWARF register REGNUM onto the appropriate GDB register
4182 arm_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
4184 /* Core integer regs. */
4185 if (reg
>= 0 && reg
<= 15)
4188 /* Legacy FPA encoding. These were once used in a way which
4189 overlapped with VFP register numbering, so their use is
4190 discouraged, but GDB doesn't support the ARM toolchain
4191 which used them for VFP. */
4192 if (reg
>= 16 && reg
<= 23)
4193 return ARM_F0_REGNUM
+ reg
- 16;
4195 /* New assignments for the FPA registers. */
4196 if (reg
>= 96 && reg
<= 103)
4197 return ARM_F0_REGNUM
+ reg
- 96;
4199 /* WMMX register assignments. */
4200 if (reg
>= 104 && reg
<= 111)
4201 return ARM_WCGR0_REGNUM
+ reg
- 104;
4203 if (reg
>= 112 && reg
<= 127)
4204 return ARM_WR0_REGNUM
+ reg
- 112;
4206 if (reg
>= 192 && reg
<= 199)
4207 return ARM_WC0_REGNUM
+ reg
- 192;
4209 /* VFP v2 registers. A double precision value is actually
4210 in d1 rather than s2, but the ABI only defines numbering
4211 for the single precision registers. This will "just work"
4212 in GDB for little endian targets (we'll read eight bytes,
4213 starting in s0 and then progressing to s1), but will be
4214 reversed on big endian targets with VFP. This won't
4215 be a problem for the new Neon quad registers; you're supposed
4216 to use DW_OP_piece for those. */
4217 if (reg
>= 64 && reg
<= 95)
4221 xsnprintf (name_buf
, sizeof (name_buf
), "s%d", reg
- 64);
4222 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4226 /* VFP v3 / Neon registers. This range is also used for VFP v2
4227 registers, except that it now describes d0 instead of s0. */
4228 if (reg
>= 256 && reg
<= 287)
4232 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", reg
- 256);
4233 return user_reg_map_name_to_regnum (gdbarch
, name_buf
,
4240 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
4242 arm_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
4245 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
4247 if (regnum
>= ARM_WR0_REGNUM
&& regnum
<= ARM_WR15_REGNUM
)
4248 return regnum
- ARM_WR0_REGNUM
+ SIM_ARM_IWMMXT_COP0R0_REGNUM
;
4250 if (regnum
>= ARM_WC0_REGNUM
&& regnum
<= ARM_WC7_REGNUM
)
4251 return regnum
- ARM_WC0_REGNUM
+ SIM_ARM_IWMMXT_COP1R0_REGNUM
;
4253 if (regnum
>= ARM_WCGR0_REGNUM
&& regnum
<= ARM_WCGR7_REGNUM
)
4254 return regnum
- ARM_WCGR0_REGNUM
+ SIM_ARM_IWMMXT_COP1R8_REGNUM
;
4256 if (reg
< NUM_GREGS
)
4257 return SIM_ARM_R0_REGNUM
+ reg
;
4260 if (reg
< NUM_FREGS
)
4261 return SIM_ARM_FP0_REGNUM
+ reg
;
4264 if (reg
< NUM_SREGS
)
4265 return SIM_ARM_FPS_REGNUM
+ reg
;
4268 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
4271 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
4272 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
4273 It is thought that this is is the floating-point register format on
4274 little-endian systems. */
4277 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
4278 void *dbl
, int endianess
)
4282 if (endianess
== BFD_ENDIAN_BIG
)
4283 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
4285 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4287 floatformat_from_doublest (fmt
, &d
, dbl
);
4291 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
,
4296 floatformat_to_doublest (fmt
, ptr
, &d
);
4297 if (endianess
== BFD_ENDIAN_BIG
)
4298 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
4300 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
4304 static unsigned long
4305 shifted_reg_val (struct frame_info
*frame
, unsigned long inst
, int carry
,
4306 unsigned long pc_val
, unsigned long status_reg
)
4308 unsigned long res
, shift
;
4309 int rm
= bits (inst
, 0, 3);
4310 unsigned long shifttype
= bits (inst
, 5, 6);
4314 int rs
= bits (inst
, 8, 11);
4315 shift
= (rs
== 15 ? pc_val
+ 8
4316 : get_frame_register_unsigned (frame
, rs
)) & 0xFF;
4319 shift
= bits (inst
, 7, 11);
4321 res
= (rm
== ARM_PC_REGNUM
4322 ? (pc_val
+ (bit (inst
, 4) ? 12 : 8))
4323 : get_frame_register_unsigned (frame
, rm
));
4328 res
= shift
>= 32 ? 0 : res
<< shift
;
4332 res
= shift
>= 32 ? 0 : res
>> shift
;
4338 res
= ((res
& 0x80000000L
)
4339 ? ~((~res
) >> shift
) : res
>> shift
);
4342 case 3: /* ROR/RRX */
4345 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
4347 res
= (res
>> shift
) | (res
<< (32 - shift
));
4351 return res
& 0xffffffff;
4355 thumb_advance_itstate (unsigned int itstate
)
4357 /* Preserve IT[7:5], the first three bits of the condition. Shift
4358 the upcoming condition flags left by one bit. */
4359 itstate
= (itstate
& 0xe0) | ((itstate
<< 1) & 0x1f);
4361 /* If we have finished the IT block, clear the state. */
4362 if ((itstate
& 0x0f) == 0)
4368 /* Find the next PC after the current instruction executes. In some
4369 cases we can not statically determine the answer (see the IT state
4370 handling in this function); in that case, a breakpoint may be
4371 inserted in addition to the returned PC, which will be used to set
4372 another breakpoint by our caller. */
4375 thumb_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
)
4377 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4378 struct address_space
*aspace
= get_frame_address_space (frame
);
4379 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4380 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4381 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
4382 unsigned short inst1
;
4383 CORE_ADDR nextpc
= pc
+ 2; /* Default is next instruction. */
4384 unsigned long offset
;
4385 ULONGEST status
, itstate
;
4387 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4388 pc_val
= MAKE_THUMB_ADDR (pc_val
);
4390 inst1
= read_memory_unsigned_integer (pc
, 2, byte_order_for_code
);
4392 /* Thumb-2 conditional execution support. There are eight bits in
4393 the CPSR which describe conditional execution state. Once
4394 reconstructed (they're in a funny order), the low five bits
4395 describe the low bit of the condition for each instruction and
4396 how many instructions remain. The high three bits describe the
4397 base condition. One of the low four bits will be set if an IT
4398 block is active. These bits read as zero on earlier
4400 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
4401 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
4403 /* If-Then handling. On GNU/Linux, where this routine is used, we
4404 use an undefined instruction as a breakpoint. Unlike BKPT, IT
4405 can disable execution of the undefined instruction. So we might
4406 miss the breakpoint if we set it on a skipped conditional
4407 instruction. Because conditional instructions can change the
4408 flags, affecting the execution of further instructions, we may
4409 need to set two breakpoints. */
4411 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
!= NULL
)
4413 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
4415 /* An IT instruction. Because this instruction does not
4416 modify the flags, we can accurately predict the next
4417 executed instruction. */
4418 itstate
= inst1
& 0x00ff;
4419 pc
+= thumb_insn_size (inst1
);
4421 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
4423 inst1
= read_memory_unsigned_integer (pc
, 2,
4424 byte_order_for_code
);
4425 pc
+= thumb_insn_size (inst1
);
4426 itstate
= thumb_advance_itstate (itstate
);
4429 return MAKE_THUMB_ADDR (pc
);
4431 else if (itstate
!= 0)
4433 /* We are in a conditional block. Check the condition. */
4434 if (! condition_true (itstate
>> 4, status
))
4436 /* Advance to the next executed instruction. */
4437 pc
+= thumb_insn_size (inst1
);
4438 itstate
= thumb_advance_itstate (itstate
);
4440 while (itstate
!= 0 && ! condition_true (itstate
>> 4, status
))
4442 inst1
= read_memory_unsigned_integer (pc
, 2,
4443 byte_order_for_code
);
4444 pc
+= thumb_insn_size (inst1
);
4445 itstate
= thumb_advance_itstate (itstate
);
4448 return MAKE_THUMB_ADDR (pc
);
4450 else if ((itstate
& 0x0f) == 0x08)
4452 /* This is the last instruction of the conditional
4453 block, and it is executed. We can handle it normally
4454 because the following instruction is not conditional,
4455 and we must handle it normally because it is
4456 permitted to branch. Fall through. */
4462 /* There are conditional instructions after this one.
4463 If this instruction modifies the flags, then we can
4464 not predict what the next executed instruction will
4465 be. Fortunately, this instruction is architecturally
4466 forbidden to branch; we know it will fall through.
4467 Start by skipping past it. */
4468 pc
+= thumb_insn_size (inst1
);
4469 itstate
= thumb_advance_itstate (itstate
);
4471 /* Set a breakpoint on the following instruction. */
4472 gdb_assert ((itstate
& 0x0f) != 0);
4473 arm_insert_single_step_breakpoint (gdbarch
, aspace
,
4474 MAKE_THUMB_ADDR (pc
));
4475 cond_negated
= (itstate
>> 4) & 1;
4477 /* Skip all following instructions with the same
4478 condition. If there is a later instruction in the IT
4479 block with the opposite condition, set the other
4480 breakpoint there. If not, then set a breakpoint on
4481 the instruction after the IT block. */
4484 inst1
= read_memory_unsigned_integer (pc
, 2,
4485 byte_order_for_code
);
4486 pc
+= thumb_insn_size (inst1
);
4487 itstate
= thumb_advance_itstate (itstate
);
4489 while (itstate
!= 0 && ((itstate
>> 4) & 1) == cond_negated
);
4491 return MAKE_THUMB_ADDR (pc
);
4495 else if (itstate
& 0x0f)
4497 /* We are in a conditional block. Check the condition. */
4498 int cond
= itstate
>> 4;
4500 if (! condition_true (cond
, status
))
4501 /* Advance to the next instruction. All the 32-bit
4502 instructions share a common prefix. */
4503 return MAKE_THUMB_ADDR (pc
+ thumb_insn_size (inst1
));
4505 /* Otherwise, handle the instruction normally. */
4508 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
4512 /* Fetch the saved PC from the stack. It's stored above
4513 all of the other registers. */
4514 offset
= bitcount (bits (inst1
, 0, 7)) * INT_REGISTER_SIZE
;
4515 sp
= get_frame_register_unsigned (frame
, ARM_SP_REGNUM
);
4516 nextpc
= read_memory_unsigned_integer (sp
+ offset
, 4, byte_order
);
4518 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
4520 unsigned long cond
= bits (inst1
, 8, 11);
4521 if (cond
== 0x0f) /* 0x0f = SWI */
4523 struct gdbarch_tdep
*tdep
;
4524 tdep
= gdbarch_tdep (gdbarch
);
4526 if (tdep
->syscall_next_pc
!= NULL
)
4527 nextpc
= tdep
->syscall_next_pc (frame
);
4530 else if (cond
!= 0x0f && condition_true (cond
, status
))
4531 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
4533 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
4535 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
4537 else if (thumb_insn_size (inst1
) == 4) /* 32-bit instruction */
4539 unsigned short inst2
;
4540 inst2
= read_memory_unsigned_integer (pc
+ 2, 2, byte_order_for_code
);
4542 /* Default to the next instruction. */
4544 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4546 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
4548 /* Branches and miscellaneous control instructions. */
4550 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
4553 int j1
, j2
, imm1
, imm2
;
4555 imm1
= sbits (inst1
, 0, 10);
4556 imm2
= bits (inst2
, 0, 10);
4557 j1
= bit (inst2
, 13);
4558 j2
= bit (inst2
, 11);
4560 offset
= ((imm1
<< 12) + (imm2
<< 1));
4561 offset
^= ((!j2
) << 22) | ((!j1
) << 23);
4563 nextpc
= pc_val
+ offset
;
4564 /* For BLX make sure to clear the low bits. */
4565 if (bit (inst2
, 12) == 0)
4566 nextpc
= nextpc
& 0xfffffffc;
4568 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
4570 /* SUBS PC, LR, #imm8. */
4571 nextpc
= get_frame_register_unsigned (frame
, ARM_LR_REGNUM
);
4572 nextpc
-= inst2
& 0x00ff;
4574 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
4576 /* Conditional branch. */
4577 if (condition_true (bits (inst1
, 6, 9), status
))
4579 int sign
, j1
, j2
, imm1
, imm2
;
4581 sign
= sbits (inst1
, 10, 10);
4582 imm1
= bits (inst1
, 0, 5);
4583 imm2
= bits (inst2
, 0, 10);
4584 j1
= bit (inst2
, 13);
4585 j2
= bit (inst2
, 11);
4587 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
4588 offset
+= (imm1
<< 12) + (imm2
<< 1);
4590 nextpc
= pc_val
+ offset
;
4594 else if ((inst1
& 0xfe50) == 0xe810)
4596 /* Load multiple or RFE. */
4597 int rn
, offset
, load_pc
= 1;
4599 rn
= bits (inst1
, 0, 3);
4600 if (bit (inst1
, 7) && !bit (inst1
, 8))
4603 if (!bit (inst2
, 15))
4605 offset
= bitcount (inst2
) * 4 - 4;
4607 else if (!bit (inst1
, 7) && bit (inst1
, 8))
4610 if (!bit (inst2
, 15))
4614 else if (bit (inst1
, 7) && bit (inst1
, 8))
4619 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
4629 CORE_ADDR addr
= get_frame_register_unsigned (frame
, rn
);
4630 nextpc
= get_frame_memory_unsigned (frame
, addr
+ offset
, 4);
4633 else if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
4635 /* MOV PC or MOVS PC. */
4636 nextpc
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4637 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4639 else if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
4643 int rn
, load_pc
= 1;
4645 rn
= bits (inst1
, 0, 3);
4646 base
= get_frame_register_unsigned (frame
, rn
);
4647 if (rn
== ARM_PC_REGNUM
)
4649 base
= (base
+ 4) & ~(CORE_ADDR
) 0x3;
4651 base
+= bits (inst2
, 0, 11);
4653 base
-= bits (inst2
, 0, 11);
4655 else if (bit (inst1
, 7))
4656 base
+= bits (inst2
, 0, 11);
4657 else if (bit (inst2
, 11))
4659 if (bit (inst2
, 10))
4662 base
+= bits (inst2
, 0, 7);
4664 base
-= bits (inst2
, 0, 7);
4667 else if ((inst2
& 0x0fc0) == 0x0000)
4669 int shift
= bits (inst2
, 4, 5), rm
= bits (inst2
, 0, 3);
4670 base
+= get_frame_register_unsigned (frame
, rm
) << shift
;
4677 nextpc
= get_frame_memory_unsigned (frame
, base
, 4);
4679 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
4682 CORE_ADDR tbl_reg
, table
, offset
, length
;
4684 tbl_reg
= bits (inst1
, 0, 3);
4685 if (tbl_reg
== 0x0f)
4686 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
4688 table
= get_frame_register_unsigned (frame
, tbl_reg
);
4690 offset
= get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4691 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 1);
4692 nextpc
= pc_val
+ length
;
4694 else if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
4697 CORE_ADDR tbl_reg
, table
, offset
, length
;
4699 tbl_reg
= bits (inst1
, 0, 3);
4700 if (tbl_reg
== 0x0f)
4701 table
= pc
+ 4; /* Regcache copy of PC isn't right yet. */
4703 table
= get_frame_register_unsigned (frame
, tbl_reg
);
4705 offset
= 2 * get_frame_register_unsigned (frame
, bits (inst2
, 0, 3));
4706 length
= 2 * get_frame_memory_unsigned (frame
, table
+ offset
, 2);
4707 nextpc
= pc_val
+ length
;
4710 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
4712 if (bits (inst1
, 3, 6) == 0x0f)
4713 nextpc
= UNMAKE_THUMB_ADDR (pc_val
);
4715 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
4717 else if ((inst1
& 0xff87) == 0x4687) /* mov pc, REG */
4719 if (bits (inst1
, 3, 6) == 0x0f)
4722 nextpc
= get_frame_register_unsigned (frame
, bits (inst1
, 3, 6));
4724 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4726 else if ((inst1
& 0xf500) == 0xb100)
4729 int imm
= (bit (inst1
, 9) << 6) + (bits (inst1
, 3, 7) << 1);
4730 ULONGEST reg
= get_frame_register_unsigned (frame
, bits (inst1
, 0, 2));
4732 if (bit (inst1
, 11) && reg
!= 0)
4733 nextpc
= pc_val
+ imm
;
4734 else if (!bit (inst1
, 11) && reg
== 0)
4735 nextpc
= pc_val
+ imm
;
4740 /* Get the raw next address. PC is the current program counter, in
4741 FRAME, which is assumed to be executing in ARM mode.
4743 The value returned has the execution state of the next instruction
4744 encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is
4745 in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
4749 arm_get_next_pc_raw (struct frame_info
*frame
, CORE_ADDR pc
)
4751 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4752 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4753 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
4754 unsigned long pc_val
;
4755 unsigned long this_instr
;
4756 unsigned long status
;
4759 pc_val
= (unsigned long) pc
;
4760 this_instr
= read_memory_unsigned_integer (pc
, 4, byte_order_for_code
);
4762 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
4763 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
4765 if (bits (this_instr
, 28, 31) == INST_NV
)
4766 switch (bits (this_instr
, 24, 27))
4771 /* Branch with Link and change to Thumb. */
4772 nextpc
= BranchDest (pc
, this_instr
);
4773 nextpc
|= bit (this_instr
, 24) << 1;
4774 nextpc
= MAKE_THUMB_ADDR (nextpc
);
4780 /* Coprocessor register transfer. */
4781 if (bits (this_instr
, 12, 15) == 15)
4782 error (_("Invalid update to pc in instruction"));
4785 else if (condition_true (bits (this_instr
, 28, 31), status
))
4787 switch (bits (this_instr
, 24, 27))
4790 case 0x1: /* data processing */
4794 unsigned long operand1
, operand2
, result
= 0;
4798 if (bits (this_instr
, 12, 15) != 15)
4801 if (bits (this_instr
, 22, 25) == 0
4802 && bits (this_instr
, 4, 7) == 9) /* multiply */
4803 error (_("Invalid update to pc in instruction"));
4805 /* BX <reg>, BLX <reg> */
4806 if (bits (this_instr
, 4, 27) == 0x12fff1
4807 || bits (this_instr
, 4, 27) == 0x12fff3)
4809 rn
= bits (this_instr
, 0, 3);
4810 nextpc
= ((rn
== ARM_PC_REGNUM
)
4812 : get_frame_register_unsigned (frame
, rn
));
4817 /* Multiply into PC. */
4818 c
= (status
& FLAG_C
) ? 1 : 0;
4819 rn
= bits (this_instr
, 16, 19);
4820 operand1
= ((rn
== ARM_PC_REGNUM
)
4822 : get_frame_register_unsigned (frame
, rn
));
4824 if (bit (this_instr
, 25))
4826 unsigned long immval
= bits (this_instr
, 0, 7);
4827 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
4828 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
4831 else /* operand 2 is a shifted register. */
4832 operand2
= shifted_reg_val (frame
, this_instr
, c
,
4835 switch (bits (this_instr
, 21, 24))
4838 result
= operand1
& operand2
;
4842 result
= operand1
^ operand2
;
4846 result
= operand1
- operand2
;
4850 result
= operand2
- operand1
;
4854 result
= operand1
+ operand2
;
4858 result
= operand1
+ operand2
+ c
;
4862 result
= operand1
- operand2
+ c
;
4866 result
= operand2
- operand1
+ c
;
4872 case 0xb: /* tst, teq, cmp, cmn */
4873 result
= (unsigned long) nextpc
;
4877 result
= operand1
| operand2
;
4881 /* Always step into a function. */
4886 result
= operand1
& ~operand2
;
4894 /* In 26-bit APCS the bottom two bits of the result are
4895 ignored, and we always end up in ARM state. */
4897 nextpc
= arm_addr_bits_remove (gdbarch
, result
);
4905 case 0x5: /* data transfer */
4908 if (bits (this_instr
, 25, 27) == 0x3 && bit (this_instr
, 4) == 1)
4910 /* Media instructions and architecturally undefined
4915 if (bit (this_instr
, 20))
4918 if (bits (this_instr
, 12, 15) == 15)
4924 if (bit (this_instr
, 22))
4925 error (_("Invalid update to pc in instruction"));
4927 /* byte write to PC */
4928 rn
= bits (this_instr
, 16, 19);
4929 base
= ((rn
== ARM_PC_REGNUM
)
4931 : get_frame_register_unsigned (frame
, rn
));
4933 if (bit (this_instr
, 24))
4936 int c
= (status
& FLAG_C
) ? 1 : 0;
4937 unsigned long offset
=
4938 (bit (this_instr
, 25)
4939 ? shifted_reg_val (frame
, this_instr
, c
, pc_val
, status
)
4940 : bits (this_instr
, 0, 11));
4942 if (bit (this_instr
, 23))
4948 (CORE_ADDR
) read_memory_unsigned_integer ((CORE_ADDR
) base
,
4955 case 0x9: /* block transfer */
4956 if (bit (this_instr
, 20))
4959 if (bit (this_instr
, 15))
4963 unsigned long rn_val
4964 = get_frame_register_unsigned (frame
,
4965 bits (this_instr
, 16, 19));
4967 if (bit (this_instr
, 23))
4970 unsigned long reglist
= bits (this_instr
, 0, 14);
4971 offset
= bitcount (reglist
) * 4;
4972 if (bit (this_instr
, 24)) /* pre */
4975 else if (bit (this_instr
, 24))
4979 (CORE_ADDR
) read_memory_unsigned_integer ((CORE_ADDR
)
4986 case 0xb: /* branch & link */
4987 case 0xa: /* branch */
4989 nextpc
= BranchDest (pc
, this_instr
);
4995 case 0xe: /* coproc ops */
4999 struct gdbarch_tdep
*tdep
;
5000 tdep
= gdbarch_tdep (gdbarch
);
5002 if (tdep
->syscall_next_pc
!= NULL
)
5003 nextpc
= tdep
->syscall_next_pc (frame
);
5009 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
5017 /* Determine next PC after current instruction executes. Will call either
5018 arm_get_next_pc_raw or thumb_get_next_pc_raw. Error out if infinite
5019 loop is detected. */
5022 arm_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
5026 if (arm_frame_is_thumb (frame
))
5027 nextpc
= thumb_get_next_pc_raw (frame
, pc
);
5029 nextpc
= arm_get_next_pc_raw (frame
, pc
);
5034 /* Like insert_single_step_breakpoint, but make sure we use a breakpoint
5035 of the appropriate mode (as encoded in the PC value), even if this
5036 differs from what would be expected according to the symbol tables. */
5039 arm_insert_single_step_breakpoint (struct gdbarch
*gdbarch
,
5040 struct address_space
*aspace
,
5043 struct cleanup
*old_chain
5044 = make_cleanup_restore_integer (&arm_override_mode
);
5046 arm_override_mode
= IS_THUMB_ADDR (pc
);
5047 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
5049 insert_single_step_breakpoint (gdbarch
, aspace
, pc
);
5051 do_cleanups (old_chain
);
5054 /* Checks for an atomic sequence of instructions beginning with a LDREX{,B,H,D}
5055 instruction and ending with a STREX{,B,H,D} instruction. If such a sequence
5056 is found, attempt to step through it. A breakpoint is placed at the end of
5060 thumb_deal_with_atomic_sequence_raw (struct frame_info
*frame
)
5062 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5063 struct address_space
*aspace
= get_frame_address_space (frame
);
5064 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5065 CORE_ADDR pc
= get_frame_pc (frame
);
5066 CORE_ADDR breaks
[2] = {-1, -1};
5068 unsigned short insn1
, insn2
;
5071 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
5072 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
5073 ULONGEST status
, itstate
;
5075 /* We currently do not support atomic sequences within an IT block. */
5076 status
= get_frame_register_unsigned (frame
, ARM_PS_REGNUM
);
5077 itstate
= ((status
>> 8) & 0xfc) | ((status
>> 25) & 0x3);
5081 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. */
5082 insn1
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5084 if (thumb_insn_size (insn1
) != 4)
5087 insn2
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5089 if (!((insn1
& 0xfff0) == 0xe850
5090 || ((insn1
& 0xfff0) == 0xe8d0 && (insn2
& 0x00c0) == 0x0040)))
5093 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5095 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
5097 insn1
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5100 if (thumb_insn_size (insn1
) != 4)
5102 /* Assume that there is at most one conditional branch in the
5103 atomic sequence. If a conditional branch is found, put a
5104 breakpoint in its destination address. */
5105 if ((insn1
& 0xf000) == 0xd000 && bits (insn1
, 8, 11) != 0x0f)
5107 if (last_breakpoint
> 0)
5108 return 0; /* More than one conditional branch found,
5109 fallback to the standard code. */
5111 breaks
[1] = loc
+ 2 + (sbits (insn1
, 0, 7) << 1);
5115 /* We do not support atomic sequences that use any *other*
5116 instructions but conditional branches to change the PC.
5117 Fall back to standard code to avoid losing control of
5119 else if (thumb_instruction_changes_pc (insn1
))
5124 insn2
= read_memory_unsigned_integer (loc
, 2, byte_order_for_code
);
5127 /* Assume that there is at most one conditional branch in the
5128 atomic sequence. If a conditional branch is found, put a
5129 breakpoint in its destination address. */
5130 if ((insn1
& 0xf800) == 0xf000
5131 && (insn2
& 0xd000) == 0x8000
5132 && (insn1
& 0x0380) != 0x0380)
5134 int sign
, j1
, j2
, imm1
, imm2
;
5135 unsigned int offset
;
5137 sign
= sbits (insn1
, 10, 10);
5138 imm1
= bits (insn1
, 0, 5);
5139 imm2
= bits (insn2
, 0, 10);
5140 j1
= bit (insn2
, 13);
5141 j2
= bit (insn2
, 11);
5143 offset
= (sign
<< 20) + (j2
<< 19) + (j1
<< 18);
5144 offset
+= (imm1
<< 12) + (imm2
<< 1);
5146 if (last_breakpoint
> 0)
5147 return 0; /* More than one conditional branch found,
5148 fallback to the standard code. */
5150 breaks
[1] = loc
+ offset
;
5154 /* We do not support atomic sequences that use any *other*
5155 instructions but conditional branches to change the PC.
5156 Fall back to standard code to avoid losing control of
5158 else if (thumb2_instruction_changes_pc (insn1
, insn2
))
5161 /* If we find a strex{,b,h,d}, we're done. */
5162 if ((insn1
& 0xfff0) == 0xe840
5163 || ((insn1
& 0xfff0) == 0xe8c0 && (insn2
& 0x00c0) == 0x0040))
5168 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5169 if (insn_count
== atomic_sequence_length
)
5172 /* Insert a breakpoint right after the end of the atomic sequence. */
5175 /* Check for duplicated breakpoints. Check also for a breakpoint
5176 placed (branch instruction's destination) anywhere in sequence. */
5178 && (breaks
[1] == breaks
[0]
5179 || (breaks
[1] >= pc
&& breaks
[1] < loc
)))
5180 last_breakpoint
= 0;
5182 /* Effectively inserts the breakpoints. */
5183 for (index
= 0; index
<= last_breakpoint
; index
++)
5184 arm_insert_single_step_breakpoint (gdbarch
, aspace
,
5185 MAKE_THUMB_ADDR (breaks
[index
]));
5191 arm_deal_with_atomic_sequence_raw (struct frame_info
*frame
)
5193 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5194 struct address_space
*aspace
= get_frame_address_space (frame
);
5195 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
5196 CORE_ADDR pc
= get_frame_pc (frame
);
5197 CORE_ADDR breaks
[2] = {-1, -1};
5202 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
5203 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
5205 /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction.
5206 Note that we do not currently support conditionally executed atomic
5208 insn
= read_memory_unsigned_integer (loc
, 4, byte_order_for_code
);
5210 if ((insn
& 0xff9000f0) != 0xe1900090)
5213 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
5215 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
5217 insn
= read_memory_unsigned_integer (loc
, 4, byte_order_for_code
);
5220 /* Assume that there is at most one conditional branch in the atomic
5221 sequence. If a conditional branch is found, put a breakpoint in
5222 its destination address. */
5223 if (bits (insn
, 24, 27) == 0xa)
5225 if (last_breakpoint
> 0)
5226 return 0; /* More than one conditional branch found, fallback
5227 to the standard single-step code. */
5229 breaks
[1] = BranchDest (loc
- 4, insn
);
5233 /* We do not support atomic sequences that use any *other* instructions
5234 but conditional branches to change the PC. Fall back to standard
5235 code to avoid losing control of execution. */
5236 else if (arm_instruction_changes_pc (insn
))
5239 /* If we find a strex{,b,h,d}, we're done. */
5240 if ((insn
& 0xff9000f0) == 0xe1800090)
5244 /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
5245 if (insn_count
== atomic_sequence_length
)
5248 /* Insert a breakpoint right after the end of the atomic sequence. */
5251 /* Check for duplicated breakpoints. Check also for a breakpoint
5252 placed (branch instruction's destination) anywhere in sequence. */
5254 && (breaks
[1] == breaks
[0]
5255 || (breaks
[1] >= pc
&& breaks
[1] < loc
)))
5256 last_breakpoint
= 0;
5258 /* Effectively inserts the breakpoints. */
5259 for (index
= 0; index
<= last_breakpoint
; index
++)
5260 arm_insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
5266 arm_deal_with_atomic_sequence (struct frame_info
*frame
)
5268 if (arm_frame_is_thumb (frame
))
5269 return thumb_deal_with_atomic_sequence_raw (frame
);
5271 return arm_deal_with_atomic_sequence_raw (frame
);
5274 /* single_step() is called just before we want to resume the inferior,
5275 if we want to single-step it but there is no hardware or kernel
5276 single-step support. We find the target of the coming instruction
5277 and breakpoint it. */
5280 arm_software_single_step (struct frame_info
*frame
)
5282 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5283 struct address_space
*aspace
= get_frame_address_space (frame
);
5286 if (arm_deal_with_atomic_sequence (frame
))
5289 next_pc
= arm_get_next_pc (frame
, get_frame_pc (frame
));
5290 arm_insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
5295 /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
5296 the buffer to be NEW_LEN bytes ending at ENDADDR. Return
5297 NULL if an error occurs. BUF is freed. */
5300 extend_buffer_earlier (gdb_byte
*buf
, CORE_ADDR endaddr
,
5301 int old_len
, int new_len
)
5304 int bytes_to_read
= new_len
- old_len
;
5306 new_buf
= (gdb_byte
*) xmalloc (new_len
);
5307 memcpy (new_buf
+ bytes_to_read
, buf
, old_len
);
5309 if (target_read_memory (endaddr
- new_len
, new_buf
, bytes_to_read
) != 0)
5317 /* An IT block is at most the 2-byte IT instruction followed by
5318 four 4-byte instructions. The furthest back we must search to
5319 find an IT block that affects the current instruction is thus
5320 2 + 3 * 4 == 14 bytes. */
5321 #define MAX_IT_BLOCK_PREFIX 14
5323 /* Use a quick scan if there are more than this many bytes of
5325 #define IT_SCAN_THRESHOLD 32
5327 /* Adjust a breakpoint's address to move breakpoints out of IT blocks.
5328 A breakpoint in an IT block may not be hit, depending on the
5331 arm_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
5335 CORE_ADDR boundary
, func_start
;
5337 enum bfd_endian order
= gdbarch_byte_order_for_code (gdbarch
);
5338 int i
, any
, last_it
, last_it_count
;
5340 /* If we are using BKPT breakpoints, none of this is necessary. */
5341 if (gdbarch_tdep (gdbarch
)->thumb2_breakpoint
== NULL
)
5344 /* ARM mode does not have this problem. */
5345 if (!arm_pc_is_thumb (gdbarch
, bpaddr
))
5348 /* We are setting a breakpoint in Thumb code that could potentially
5349 contain an IT block. The first step is to find how much Thumb
5350 code there is; we do not need to read outside of known Thumb
5352 map_type
= arm_find_mapping_symbol (bpaddr
, &boundary
);
5354 /* Thumb-2 code must have mapping symbols to have a chance. */
5357 bpaddr
= gdbarch_addr_bits_remove (gdbarch
, bpaddr
);
5359 if (find_pc_partial_function (bpaddr
, NULL
, &func_start
, NULL
)
5360 && func_start
> boundary
)
5361 boundary
= func_start
;
5363 /* Search for a candidate IT instruction. We have to do some fancy
5364 footwork to distinguish a real IT instruction from the second
5365 half of a 32-bit instruction, but there is no need for that if
5366 there's no candidate. */
5367 buf_len
= min (bpaddr
- boundary
, MAX_IT_BLOCK_PREFIX
);
5369 /* No room for an IT instruction. */
5372 buf
= (gdb_byte
*) xmalloc (buf_len
);
5373 if (target_read_memory (bpaddr
- buf_len
, buf
, buf_len
) != 0)
5376 for (i
= 0; i
< buf_len
; i
+= 2)
5378 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5379 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
5391 /* OK, the code bytes before this instruction contain at least one
5392 halfword which resembles an IT instruction. We know that it's
5393 Thumb code, but there are still two possibilities. Either the
5394 halfword really is an IT instruction, or it is the second half of
5395 a 32-bit Thumb instruction. The only way we can tell is to
5396 scan forwards from a known instruction boundary. */
5397 if (bpaddr
- boundary
> IT_SCAN_THRESHOLD
)
5401 /* There's a lot of code before this instruction. Start with an
5402 optimistic search; it's easy to recognize halfwords that can
5403 not be the start of a 32-bit instruction, and use that to
5404 lock on to the instruction boundaries. */
5405 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, IT_SCAN_THRESHOLD
);
5408 buf_len
= IT_SCAN_THRESHOLD
;
5411 for (i
= 0; i
< buf_len
- sizeof (buf
) && ! definite
; i
+= 2)
5413 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5414 if (thumb_insn_size (inst1
) == 2)
5421 /* At this point, if DEFINITE, BUF[I] is the first place we
5422 are sure that we know the instruction boundaries, and it is far
5423 enough from BPADDR that we could not miss an IT instruction
5424 affecting BPADDR. If ! DEFINITE, give up - start from a
5428 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
,
5432 buf_len
= bpaddr
- boundary
;
5438 buf
= extend_buffer_earlier (buf
, bpaddr
, buf_len
, bpaddr
- boundary
);
5441 buf_len
= bpaddr
- boundary
;
5445 /* Scan forwards. Find the last IT instruction before BPADDR. */
5450 unsigned short inst1
= extract_unsigned_integer (&buf
[i
], 2, order
);
5452 if ((inst1
& 0xff00) == 0xbf00 && (inst1
& 0x000f) != 0)
5457 else if (inst1
& 0x0002)
5459 else if (inst1
& 0x0004)
5464 i
+= thumb_insn_size (inst1
);
5470 /* There wasn't really an IT instruction after all. */
5473 if (last_it_count
< 1)
5474 /* It was too far away. */
5477 /* This really is a trouble spot. Move the breakpoint to the IT
5479 return bpaddr
- buf_len
+ last_it
;
5482 /* ARM displaced stepping support.
5484 Generally ARM displaced stepping works as follows:
5486 1. When an instruction is to be single-stepped, it is first decoded by
5487 arm_process_displaced_insn (called from arm_displaced_step_copy_insn).
5488 Depending on the type of instruction, it is then copied to a scratch
5489 location, possibly in a modified form. The copy_* set of functions
5490 performs such modification, as necessary. A breakpoint is placed after
5491 the modified instruction in the scratch space to return control to GDB.
5492 Note in particular that instructions which modify the PC will no longer
5493 do so after modification.
5495 2. The instruction is single-stepped, by setting the PC to the scratch
5496 location address, and resuming. Control returns to GDB when the
5499 3. A cleanup function (cleanup_*) is called corresponding to the copy_*
5500 function used for the current instruction. This function's job is to
5501 put the CPU/memory state back to what it would have been if the
5502 instruction had been executed unmodified in its original location. */
5504 /* NOP instruction (mov r0, r0). */
5505 #define ARM_NOP 0xe1a00000
5506 #define THUMB_NOP 0x4600
5508 /* Helper for register reads for displaced stepping. In particular, this
5509 returns the PC as it would be seen by the instruction at its original
5513 displaced_read_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5517 CORE_ADDR from
= dsc
->insn_addr
;
5519 if (regno
== ARM_PC_REGNUM
)
5521 /* Compute pipeline offset:
5522 - When executing an ARM instruction, PC reads as the address of the
5523 current instruction plus 8.
5524 - When executing a Thumb instruction, PC reads as the address of the
5525 current instruction plus 4. */
5532 if (debug_displaced
)
5533 fprintf_unfiltered (gdb_stdlog
, "displaced: read pc value %.8lx\n",
5534 (unsigned long) from
);
5535 return (ULONGEST
) from
;
5539 regcache_cooked_read_unsigned (regs
, regno
, &ret
);
5540 if (debug_displaced
)
5541 fprintf_unfiltered (gdb_stdlog
, "displaced: read r%d value %.8lx\n",
5542 regno
, (unsigned long) ret
);
5548 displaced_in_arm_mode (struct regcache
*regs
)
5551 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
5553 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
5555 return (ps
& t_bit
) == 0;
5558 /* Write to the PC as from a branch instruction. */
5561 branch_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5565 /* Note: If bits 0/1 are set, this branch would be unpredictable for
5566 architecture versions < 6. */
5567 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
5568 val
& ~(ULONGEST
) 0x3);
5570 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
5571 val
& ~(ULONGEST
) 0x1);
5574 /* Write to the PC as from a branch-exchange instruction. */
5577 bx_write_pc (struct regcache
*regs
, ULONGEST val
)
5580 ULONGEST t_bit
= arm_psr_thumb_bit (get_regcache_arch (regs
));
5582 regcache_cooked_read_unsigned (regs
, ARM_PS_REGNUM
, &ps
);
5586 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
| t_bit
);
5587 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffe);
5589 else if ((val
& 2) == 0)
5591 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
5592 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
);
5596 /* Unpredictable behaviour. Try to do something sensible (switch to ARM
5597 mode, align dest to 4 bytes). */
5598 warning (_("Single-stepping BX to non-word-aligned ARM instruction."));
5599 regcache_cooked_write_unsigned (regs
, ARM_PS_REGNUM
, ps
& ~t_bit
);
5600 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
, val
& 0xfffffffc);
5604 /* Write to the PC as if from a load instruction. */
5607 load_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5610 if (DISPLACED_STEPPING_ARCH_VERSION
>= 5)
5611 bx_write_pc (regs
, val
);
5613 branch_write_pc (regs
, dsc
, val
);
5616 /* Write to the PC as if from an ALU instruction. */
5619 alu_write_pc (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5622 if (DISPLACED_STEPPING_ARCH_VERSION
>= 7 && !dsc
->is_thumb
)
5623 bx_write_pc (regs
, val
);
5625 branch_write_pc (regs
, dsc
, val
);
5628 /* Helper for writing to registers for displaced stepping. Writing to the PC
5629 has a varying effects depending on the instruction which does the write:
5630 this is controlled by the WRITE_PC argument. */
5633 displaced_write_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
5634 int regno
, ULONGEST val
, enum pc_write_style write_pc
)
5636 if (regno
== ARM_PC_REGNUM
)
5638 if (debug_displaced
)
5639 fprintf_unfiltered (gdb_stdlog
, "displaced: writing pc %.8lx\n",
5640 (unsigned long) val
);
5643 case BRANCH_WRITE_PC
:
5644 branch_write_pc (regs
, dsc
, val
);
5648 bx_write_pc (regs
, val
);
5652 load_write_pc (regs
, dsc
, val
);
5656 alu_write_pc (regs
, dsc
, val
);
5659 case CANNOT_WRITE_PC
:
5660 warning (_("Instruction wrote to PC in an unexpected way when "
5661 "single-stepping"));
5665 internal_error (__FILE__
, __LINE__
,
5666 _("Invalid argument to displaced_write_reg"));
5669 dsc
->wrote_to_pc
= 1;
5673 if (debug_displaced
)
5674 fprintf_unfiltered (gdb_stdlog
, "displaced: writing r%d value %.8lx\n",
5675 regno
, (unsigned long) val
);
5676 regcache_cooked_write_unsigned (regs
, regno
, val
);
5680 /* This function is used to concisely determine if an instruction INSN
5681 references PC. Register fields of interest in INSN should have the
5682 corresponding fields of BITMASK set to 0b1111. The function
5683 returns return 1 if any of these fields in INSN reference the PC
5684 (also 0b1111, r15), else it returns 0. */
5687 insn_references_pc (uint32_t insn
, uint32_t bitmask
)
5689 uint32_t lowbit
= 1;
5691 while (bitmask
!= 0)
5695 for (; lowbit
&& (bitmask
& lowbit
) == 0; lowbit
<<= 1)
5701 mask
= lowbit
* 0xf;
5703 if ((insn
& mask
) == mask
)
5712 /* The simplest copy function. Many instructions have the same effect no
5713 matter what address they are executed at: in those cases, use this. */
5716 arm_copy_unmodified (struct gdbarch
*gdbarch
, uint32_t insn
,
5717 const char *iname
, struct displaced_step_closure
*dsc
)
5719 if (debug_displaced
)
5720 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx, "
5721 "opcode/class '%s' unmodified\n", (unsigned long) insn
,
5724 dsc
->modinsn
[0] = insn
;
5730 thumb_copy_unmodified_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
5731 uint16_t insn2
, const char *iname
,
5732 struct displaced_step_closure
*dsc
)
5734 if (debug_displaced
)
5735 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x %.4x, "
5736 "opcode/class '%s' unmodified\n", insn1
, insn2
,
5739 dsc
->modinsn
[0] = insn1
;
5740 dsc
->modinsn
[1] = insn2
;
5746 /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any
5749 thumb_copy_unmodified_16bit (struct gdbarch
*gdbarch
, unsigned int insn
,
5751 struct displaced_step_closure
*dsc
)
5753 if (debug_displaced
)
5754 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x, "
5755 "opcode/class '%s' unmodified\n", insn
,
5758 dsc
->modinsn
[0] = insn
;
5763 /* Preload instructions with immediate offset. */
5766 cleanup_preload (struct gdbarch
*gdbarch
,
5767 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5769 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5770 if (!dsc
->u
.preload
.immed
)
5771 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
5775 install_preload (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5776 struct displaced_step_closure
*dsc
, unsigned int rn
)
5779 /* Preload instructions:
5781 {pli/pld} [rn, #+/-imm]
5783 {pli/pld} [r0, #+/-imm]. */
5785 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5786 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5787 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5788 dsc
->u
.preload
.immed
= 1;
5790 dsc
->cleanup
= &cleanup_preload
;
5794 arm_copy_preload (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
5795 struct displaced_step_closure
*dsc
)
5797 unsigned int rn
= bits (insn
, 16, 19);
5799 if (!insn_references_pc (insn
, 0x000f0000ul
))
5800 return arm_copy_unmodified (gdbarch
, insn
, "preload", dsc
);
5802 if (debug_displaced
)
5803 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
5804 (unsigned long) insn
);
5806 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
5808 install_preload (gdbarch
, regs
, dsc
, rn
);
5814 thumb2_copy_preload (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
5815 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
5817 unsigned int rn
= bits (insn1
, 0, 3);
5818 unsigned int u_bit
= bit (insn1
, 7);
5819 int imm12
= bits (insn2
, 0, 11);
5822 if (rn
!= ARM_PC_REGNUM
)
5823 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "preload", dsc
);
5825 /* PC is only allowed to use in PLI (immediate,literal) Encoding T3, and
5826 PLD (literal) Encoding T1. */
5827 if (debug_displaced
)
5828 fprintf_unfiltered (gdb_stdlog
,
5829 "displaced: copying pld/pli pc (0x%x) %c imm12 %.4x\n",
5830 (unsigned int) dsc
->insn_addr
, u_bit
? '+' : '-',
5836 /* Rewrite instruction {pli/pld} PC imm12 into:
5837 Prepare: tmp[0] <- r0, tmp[1] <- r1, r0 <- pc, r1 <- imm12
5841 Cleanup: r0 <- tmp[0], r1 <- tmp[1]. */
5843 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5844 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5846 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
5848 displaced_write_reg (regs
, dsc
, 0, pc_val
, CANNOT_WRITE_PC
);
5849 displaced_write_reg (regs
, dsc
, 1, imm12
, CANNOT_WRITE_PC
);
5850 dsc
->u
.preload
.immed
= 0;
5852 /* {pli/pld} [r0, r1] */
5853 dsc
->modinsn
[0] = insn1
& 0xfff0;
5854 dsc
->modinsn
[1] = 0xf001;
5857 dsc
->cleanup
= &cleanup_preload
;
5861 /* Preload instructions with register offset. */
5864 install_preload_reg(struct gdbarch
*gdbarch
, struct regcache
*regs
,
5865 struct displaced_step_closure
*dsc
, unsigned int rn
,
5868 ULONGEST rn_val
, rm_val
;
5870 /* Preload register-offset instructions:
5872 {pli/pld} [rn, rm {, shift}]
5874 {pli/pld} [r0, r1 {, shift}]. */
5876 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5877 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
5878 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5879 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
5880 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5881 displaced_write_reg (regs
, dsc
, 1, rm_val
, CANNOT_WRITE_PC
);
5882 dsc
->u
.preload
.immed
= 0;
5884 dsc
->cleanup
= &cleanup_preload
;
5888 arm_copy_preload_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
5889 struct regcache
*regs
,
5890 struct displaced_step_closure
*dsc
)
5892 unsigned int rn
= bits (insn
, 16, 19);
5893 unsigned int rm
= bits (insn
, 0, 3);
5896 if (!insn_references_pc (insn
, 0x000f000ful
))
5897 return arm_copy_unmodified (gdbarch
, insn
, "preload reg", dsc
);
5899 if (debug_displaced
)
5900 fprintf_unfiltered (gdb_stdlog
, "displaced: copying preload insn %.8lx\n",
5901 (unsigned long) insn
);
5903 dsc
->modinsn
[0] = (insn
& 0xfff0fff0) | 0x1;
5905 install_preload_reg (gdbarch
, regs
, dsc
, rn
, rm
);
5909 /* Copy/cleanup coprocessor load and store instructions. */
5912 cleanup_copro_load_store (struct gdbarch
*gdbarch
,
5913 struct regcache
*regs
,
5914 struct displaced_step_closure
*dsc
)
5916 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 0);
5918 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
5920 if (dsc
->u
.ldst
.writeback
)
5921 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, LOAD_WRITE_PC
);
5925 install_copro_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
5926 struct displaced_step_closure
*dsc
,
5927 int writeback
, unsigned int rn
)
5931 /* Coprocessor load/store instructions:
5933 {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes)
5935 {stc/stc2} [r0, #+/-imm].
5937 ldc/ldc2 are handled identically. */
5939 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
5940 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
5941 /* PC should be 4-byte aligned. */
5942 rn_val
= rn_val
& 0xfffffffc;
5943 displaced_write_reg (regs
, dsc
, 0, rn_val
, CANNOT_WRITE_PC
);
5945 dsc
->u
.ldst
.writeback
= writeback
;
5946 dsc
->u
.ldst
.rn
= rn
;
5948 dsc
->cleanup
= &cleanup_copro_load_store
;
5952 arm_copy_copro_load_store (struct gdbarch
*gdbarch
, uint32_t insn
,
5953 struct regcache
*regs
,
5954 struct displaced_step_closure
*dsc
)
5956 unsigned int rn
= bits (insn
, 16, 19);
5958 if (!insn_references_pc (insn
, 0x000f0000ul
))
5959 return arm_copy_unmodified (gdbarch
, insn
, "copro load/store", dsc
);
5961 if (debug_displaced
)
5962 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
5963 "load/store insn %.8lx\n", (unsigned long) insn
);
5965 dsc
->modinsn
[0] = insn
& 0xfff0ffff;
5967 install_copro_load_store (gdbarch
, regs
, dsc
, bit (insn
, 25), rn
);
5973 thumb2_copy_copro_load_store (struct gdbarch
*gdbarch
, uint16_t insn1
,
5974 uint16_t insn2
, struct regcache
*regs
,
5975 struct displaced_step_closure
*dsc
)
5977 unsigned int rn
= bits (insn1
, 0, 3);
5979 if (rn
!= ARM_PC_REGNUM
)
5980 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
5981 "copro load/store", dsc
);
5983 if (debug_displaced
)
5984 fprintf_unfiltered (gdb_stdlog
, "displaced: copying coprocessor "
5985 "load/store insn %.4x%.4x\n", insn1
, insn2
);
5987 dsc
->modinsn
[0] = insn1
& 0xfff0;
5988 dsc
->modinsn
[1] = insn2
;
5991 /* This function is called for copying instruction LDC/LDC2/VLDR, which
5992 doesn't support writeback, so pass 0. */
5993 install_copro_load_store (gdbarch
, regs
, dsc
, 0, rn
);
5998 /* Clean up branch instructions (actually perform the branch, by setting
6002 cleanup_branch (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6003 struct displaced_step_closure
*dsc
)
6005 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6006 int branch_taken
= condition_true (dsc
->u
.branch
.cond
, status
);
6007 enum pc_write_style write_pc
= dsc
->u
.branch
.exchange
6008 ? BX_WRITE_PC
: BRANCH_WRITE_PC
;
6013 if (dsc
->u
.branch
.link
)
6015 /* The value of LR should be the next insn of current one. In order
6016 not to confuse logic hanlding later insn `bx lr', if current insn mode
6017 is Thumb, the bit 0 of LR value should be set to 1. */
6018 ULONGEST next_insn_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
6021 next_insn_addr
|= 0x1;
6023 displaced_write_reg (regs
, dsc
, ARM_LR_REGNUM
, next_insn_addr
,
6027 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, dsc
->u
.branch
.dest
, write_pc
);
6030 /* Copy B/BL/BLX instructions with immediate destinations. */
6033 install_b_bl_blx (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6034 struct displaced_step_closure
*dsc
,
6035 unsigned int cond
, int exchange
, int link
, long offset
)
6037 /* Implement "BL<cond> <label>" as:
6039 Preparation: cond <- instruction condition
6040 Insn: mov r0, r0 (nop)
6041 Cleanup: if (condition true) { r14 <- pc; pc <- label }.
6043 B<cond> similar, but don't set r14 in cleanup. */
6045 dsc
->u
.branch
.cond
= cond
;
6046 dsc
->u
.branch
.link
= link
;
6047 dsc
->u
.branch
.exchange
= exchange
;
6049 dsc
->u
.branch
.dest
= dsc
->insn_addr
;
6050 if (link
&& exchange
)
6051 /* For BLX, offset is computed from the Align (PC, 4). */
6052 dsc
->u
.branch
.dest
= dsc
->u
.branch
.dest
& 0xfffffffc;
6055 dsc
->u
.branch
.dest
+= 4 + offset
;
6057 dsc
->u
.branch
.dest
+= 8 + offset
;
6059 dsc
->cleanup
= &cleanup_branch
;
6062 arm_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint32_t insn
,
6063 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6065 unsigned int cond
= bits (insn
, 28, 31);
6066 int exchange
= (cond
== 0xf);
6067 int link
= exchange
|| bit (insn
, 24);
6070 if (debug_displaced
)
6071 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s immediate insn "
6072 "%.8lx\n", (exchange
) ? "blx" : (link
) ? "bl" : "b",
6073 (unsigned long) insn
);
6075 /* For BLX, set bit 0 of the destination. The cleanup_branch function will
6076 then arrange the switch into Thumb mode. */
6077 offset
= (bits (insn
, 0, 23) << 2) | (bit (insn
, 24) << 1) | 1;
6079 offset
= bits (insn
, 0, 23) << 2;
6081 if (bit (offset
, 25))
6082 offset
= offset
| ~0x3ffffff;
6084 dsc
->modinsn
[0] = ARM_NOP
;
6086 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
6091 thumb2_copy_b_bl_blx (struct gdbarch
*gdbarch
, uint16_t insn1
,
6092 uint16_t insn2
, struct regcache
*regs
,
6093 struct displaced_step_closure
*dsc
)
6095 int link
= bit (insn2
, 14);
6096 int exchange
= link
&& !bit (insn2
, 12);
6099 int j1
= bit (insn2
, 13);
6100 int j2
= bit (insn2
, 11);
6101 int s
= sbits (insn1
, 10, 10);
6102 int i1
= !(j1
^ bit (insn1
, 10));
6103 int i2
= !(j2
^ bit (insn1
, 10));
6105 if (!link
&& !exchange
) /* B */
6107 offset
= (bits (insn2
, 0, 10) << 1);
6108 if (bit (insn2
, 12)) /* Encoding T4 */
6110 offset
|= (bits (insn1
, 0, 9) << 12)
6116 else /* Encoding T3 */
6118 offset
|= (bits (insn1
, 0, 5) << 12)
6122 cond
= bits (insn1
, 6, 9);
6127 offset
= (bits (insn1
, 0, 9) << 12);
6128 offset
|= ((i2
<< 22) | (i1
<< 23) | (s
<< 24));
6129 offset
|= exchange
?
6130 (bits (insn2
, 1, 10) << 2) : (bits (insn2
, 0, 10) << 1);
6133 if (debug_displaced
)
6134 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s insn "
6135 "%.4x %.4x with offset %.8lx\n",
6136 link
? (exchange
) ? "blx" : "bl" : "b",
6137 insn1
, insn2
, offset
);
6139 dsc
->modinsn
[0] = THUMB_NOP
;
6141 install_b_bl_blx (gdbarch
, regs
, dsc
, cond
, exchange
, link
, offset
);
6145 /* Copy B Thumb instructions. */
6147 thumb_copy_b (struct gdbarch
*gdbarch
, unsigned short insn
,
6148 struct displaced_step_closure
*dsc
)
6150 unsigned int cond
= 0;
6152 unsigned short bit_12_15
= bits (insn
, 12, 15);
6153 CORE_ADDR from
= dsc
->insn_addr
;
6155 if (bit_12_15
== 0xd)
6157 /* offset = SignExtend (imm8:0, 32) */
6158 offset
= sbits ((insn
<< 1), 0, 8);
6159 cond
= bits (insn
, 8, 11);
6161 else if (bit_12_15
== 0xe) /* Encoding T2 */
6163 offset
= sbits ((insn
<< 1), 0, 11);
6167 if (debug_displaced
)
6168 fprintf_unfiltered (gdb_stdlog
,
6169 "displaced: copying b immediate insn %.4x "
6170 "with offset %d\n", insn
, offset
);
6172 dsc
->u
.branch
.cond
= cond
;
6173 dsc
->u
.branch
.link
= 0;
6174 dsc
->u
.branch
.exchange
= 0;
6175 dsc
->u
.branch
.dest
= from
+ 4 + offset
;
6177 dsc
->modinsn
[0] = THUMB_NOP
;
6179 dsc
->cleanup
= &cleanup_branch
;
6184 /* Copy BX/BLX with register-specified destinations. */
6187 install_bx_blx_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6188 struct displaced_step_closure
*dsc
, int link
,
6189 unsigned int cond
, unsigned int rm
)
6191 /* Implement {BX,BLX}<cond> <reg>" as:
6193 Preparation: cond <- instruction condition
6194 Insn: mov r0, r0 (nop)
6195 Cleanup: if (condition true) { r14 <- pc; pc <- dest; }.
6197 Don't set r14 in cleanup for BX. */
6199 dsc
->u
.branch
.dest
= displaced_read_reg (regs
, dsc
, rm
);
6201 dsc
->u
.branch
.cond
= cond
;
6202 dsc
->u
.branch
.link
= link
;
6204 dsc
->u
.branch
.exchange
= 1;
6206 dsc
->cleanup
= &cleanup_branch
;
6210 arm_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
6211 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6213 unsigned int cond
= bits (insn
, 28, 31);
6216 int link
= bit (insn
, 5);
6217 unsigned int rm
= bits (insn
, 0, 3);
6219 if (debug_displaced
)
6220 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.8lx",
6221 (unsigned long) insn
);
6223 dsc
->modinsn
[0] = ARM_NOP
;
6225 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, cond
, rm
);
6230 thumb_copy_bx_blx_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
6231 struct regcache
*regs
,
6232 struct displaced_step_closure
*dsc
)
6234 int link
= bit (insn
, 7);
6235 unsigned int rm
= bits (insn
, 3, 6);
6237 if (debug_displaced
)
6238 fprintf_unfiltered (gdb_stdlog
, "displaced: copying insn %.4x",
6239 (unsigned short) insn
);
6241 dsc
->modinsn
[0] = THUMB_NOP
;
6243 install_bx_blx_reg (gdbarch
, regs
, dsc
, link
, INST_AL
, rm
);
6249 /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */
6252 cleanup_alu_imm (struct gdbarch
*gdbarch
,
6253 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6255 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
6256 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6257 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6258 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6262 arm_copy_alu_imm (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
6263 struct displaced_step_closure
*dsc
)
6265 unsigned int rn
= bits (insn
, 16, 19);
6266 unsigned int rd
= bits (insn
, 12, 15);
6267 unsigned int op
= bits (insn
, 21, 24);
6268 int is_mov
= (op
== 0xd);
6269 ULONGEST rd_val
, rn_val
;
6271 if (!insn_references_pc (insn
, 0x000ff000ul
))
6272 return arm_copy_unmodified (gdbarch
, insn
, "ALU immediate", dsc
);
6274 if (debug_displaced
)
6275 fprintf_unfiltered (gdb_stdlog
, "displaced: copying immediate %s insn "
6276 "%.8lx\n", is_mov
? "move" : "ALU",
6277 (unsigned long) insn
);
6279 /* Instruction is of form:
6281 <op><cond> rd, [rn,] #imm
6285 Preparation: tmp1, tmp2 <- r0, r1;
6287 Insn: <op><cond> r0, r1, #imm
6288 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6291 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6292 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6293 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6294 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6295 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6296 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6300 dsc
->modinsn
[0] = insn
& 0xfff00fff;
6302 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x10000;
6304 dsc
->cleanup
= &cleanup_alu_imm
;
6310 thumb2_copy_alu_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
6311 uint16_t insn2
, struct regcache
*regs
,
6312 struct displaced_step_closure
*dsc
)
6314 unsigned int op
= bits (insn1
, 5, 8);
6315 unsigned int rn
, rm
, rd
;
6316 ULONGEST rd_val
, rn_val
;
6318 rn
= bits (insn1
, 0, 3); /* Rn */
6319 rm
= bits (insn2
, 0, 3); /* Rm */
6320 rd
= bits (insn2
, 8, 11); /* Rd */
6322 /* This routine is only called for instruction MOV. */
6323 gdb_assert (op
== 0x2 && rn
== 0xf);
6325 if (rm
!= ARM_PC_REGNUM
&& rd
!= ARM_PC_REGNUM
)
6326 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ALU imm", dsc
);
6328 if (debug_displaced
)
6329 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.4x%.4x\n",
6330 "ALU", insn1
, insn2
);
6332 /* Instruction is of form:
6334 <op><cond> rd, [rn,] #imm
6338 Preparation: tmp1, tmp2 <- r0, r1;
6340 Insn: <op><cond> r0, r1, #imm
6341 Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2
6344 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6345 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6346 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6347 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6348 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6349 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6352 dsc
->modinsn
[0] = insn1
;
6353 dsc
->modinsn
[1] = ((insn2
& 0xf0f0) | 0x1);
6356 dsc
->cleanup
= &cleanup_alu_imm
;
6361 /* Copy/cleanup arithmetic/logic insns with register RHS. */
6364 cleanup_alu_reg (struct gdbarch
*gdbarch
,
6365 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6370 rd_val
= displaced_read_reg (regs
, dsc
, 0);
6372 for (i
= 0; i
< 3; i
++)
6373 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
6375 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6379 install_alu_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6380 struct displaced_step_closure
*dsc
,
6381 unsigned int rd
, unsigned int rn
, unsigned int rm
)
6383 ULONGEST rd_val
, rn_val
, rm_val
;
6385 /* Instruction is of form:
6387 <op><cond> rd, [rn,] rm [, <shift>]
6391 Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2;
6392 r0, r1, r2 <- rd, rn, rm
6393 Insn: <op><cond> r0, [r1,] r2 [, <shift>]
6394 Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3
6397 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6398 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6399 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6400 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6401 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6402 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6403 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6404 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6405 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
6408 dsc
->cleanup
= &cleanup_alu_reg
;
6412 arm_copy_alu_reg (struct gdbarch
*gdbarch
, uint32_t insn
, struct regcache
*regs
,
6413 struct displaced_step_closure
*dsc
)
6415 unsigned int op
= bits (insn
, 21, 24);
6416 int is_mov
= (op
== 0xd);
6418 if (!insn_references_pc (insn
, 0x000ff00ful
))
6419 return arm_copy_unmodified (gdbarch
, insn
, "ALU reg", dsc
);
6421 if (debug_displaced
)
6422 fprintf_unfiltered (gdb_stdlog
, "displaced: copying reg %s insn %.8lx\n",
6423 is_mov
? "move" : "ALU", (unsigned long) insn
);
6426 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x2;
6428 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x10002;
6430 install_alu_reg (gdbarch
, regs
, dsc
, bits (insn
, 12, 15), bits (insn
, 16, 19),
6436 thumb_copy_alu_reg (struct gdbarch
*gdbarch
, uint16_t insn
,
6437 struct regcache
*regs
,
6438 struct displaced_step_closure
*dsc
)
6442 rm
= bits (insn
, 3, 6);
6443 rd
= (bit (insn
, 7) << 3) | bits (insn
, 0, 2);
6445 if (rd
!= ARM_PC_REGNUM
&& rm
!= ARM_PC_REGNUM
)
6446 return thumb_copy_unmodified_16bit (gdbarch
, insn
, "ALU reg", dsc
);
6448 if (debug_displaced
)
6449 fprintf_unfiltered (gdb_stdlog
, "displaced: copying ALU reg insn %.4x\n",
6450 (unsigned short) insn
);
6452 dsc
->modinsn
[0] = ((insn
& 0xff00) | 0x10);
6454 install_alu_reg (gdbarch
, regs
, dsc
, rd
, rd
, rm
);
6459 /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */
6462 cleanup_alu_shifted_reg (struct gdbarch
*gdbarch
,
6463 struct regcache
*regs
,
6464 struct displaced_step_closure
*dsc
)
6466 ULONGEST rd_val
= displaced_read_reg (regs
, dsc
, 0);
6469 for (i
= 0; i
< 4; i
++)
6470 displaced_write_reg (regs
, dsc
, i
, dsc
->tmp
[i
], CANNOT_WRITE_PC
);
6472 displaced_write_reg (regs
, dsc
, dsc
->rd
, rd_val
, ALU_WRITE_PC
);
6476 install_alu_shifted_reg (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6477 struct displaced_step_closure
*dsc
,
6478 unsigned int rd
, unsigned int rn
, unsigned int rm
,
6482 ULONGEST rd_val
, rn_val
, rm_val
, rs_val
;
6484 /* Instruction is of form:
6486 <op><cond> rd, [rn,] rm, <shift> rs
6490 Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3
6491 r0, r1, r2, r3 <- rd, rn, rm, rs
6492 Insn: <op><cond> r0, r1, r2, <shift> r3
6494 r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4
6498 for (i
= 0; i
< 4; i
++)
6499 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
6501 rd_val
= displaced_read_reg (regs
, dsc
, rd
);
6502 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6503 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6504 rs_val
= displaced_read_reg (regs
, dsc
, rs
);
6505 displaced_write_reg (regs
, dsc
, 0, rd_val
, CANNOT_WRITE_PC
);
6506 displaced_write_reg (regs
, dsc
, 1, rn_val
, CANNOT_WRITE_PC
);
6507 displaced_write_reg (regs
, dsc
, 2, rm_val
, CANNOT_WRITE_PC
);
6508 displaced_write_reg (regs
, dsc
, 3, rs_val
, CANNOT_WRITE_PC
);
6510 dsc
->cleanup
= &cleanup_alu_shifted_reg
;
6514 arm_copy_alu_shifted_reg (struct gdbarch
*gdbarch
, uint32_t insn
,
6515 struct regcache
*regs
,
6516 struct displaced_step_closure
*dsc
)
6518 unsigned int op
= bits (insn
, 21, 24);
6519 int is_mov
= (op
== 0xd);
6520 unsigned int rd
, rn
, rm
, rs
;
6522 if (!insn_references_pc (insn
, 0x000fff0ful
))
6523 return arm_copy_unmodified (gdbarch
, insn
, "ALU shifted reg", dsc
);
6525 if (debug_displaced
)
6526 fprintf_unfiltered (gdb_stdlog
, "displaced: copying shifted reg %s insn "
6527 "%.8lx\n", is_mov
? "move" : "ALU",
6528 (unsigned long) insn
);
6530 rn
= bits (insn
, 16, 19);
6531 rm
= bits (insn
, 0, 3);
6532 rs
= bits (insn
, 8, 11);
6533 rd
= bits (insn
, 12, 15);
6536 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x302;
6538 dsc
->modinsn
[0] = (insn
& 0xfff000f0) | 0x10302;
6540 install_alu_shifted_reg (gdbarch
, regs
, dsc
, rd
, rn
, rm
, rs
);
6545 /* Clean up load instructions. */
6548 cleanup_load (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6549 struct displaced_step_closure
*dsc
)
6551 ULONGEST rt_val
, rt_val2
= 0, rn_val
;
6553 rt_val
= displaced_read_reg (regs
, dsc
, 0);
6554 if (dsc
->u
.ldst
.xfersize
== 8)
6555 rt_val2
= displaced_read_reg (regs
, dsc
, 1);
6556 rn_val
= displaced_read_reg (regs
, dsc
, 2);
6558 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6559 if (dsc
->u
.ldst
.xfersize
> 4)
6560 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6561 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
6562 if (!dsc
->u
.ldst
.immed
)
6563 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
6565 /* Handle register writeback. */
6566 if (dsc
->u
.ldst
.writeback
)
6567 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
6568 /* Put result in right place. */
6569 displaced_write_reg (regs
, dsc
, dsc
->rd
, rt_val
, LOAD_WRITE_PC
);
6570 if (dsc
->u
.ldst
.xfersize
== 8)
6571 displaced_write_reg (regs
, dsc
, dsc
->rd
+ 1, rt_val2
, LOAD_WRITE_PC
);
6574 /* Clean up store instructions. */
6577 cleanup_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6578 struct displaced_step_closure
*dsc
)
6580 ULONGEST rn_val
= displaced_read_reg (regs
, dsc
, 2);
6582 displaced_write_reg (regs
, dsc
, 0, dsc
->tmp
[0], CANNOT_WRITE_PC
);
6583 if (dsc
->u
.ldst
.xfersize
> 4)
6584 displaced_write_reg (regs
, dsc
, 1, dsc
->tmp
[1], CANNOT_WRITE_PC
);
6585 displaced_write_reg (regs
, dsc
, 2, dsc
->tmp
[2], CANNOT_WRITE_PC
);
6586 if (!dsc
->u
.ldst
.immed
)
6587 displaced_write_reg (regs
, dsc
, 3, dsc
->tmp
[3], CANNOT_WRITE_PC
);
6588 if (!dsc
->u
.ldst
.restore_r4
)
6589 displaced_write_reg (regs
, dsc
, 4, dsc
->tmp
[4], CANNOT_WRITE_PC
);
6592 if (dsc
->u
.ldst
.writeback
)
6593 displaced_write_reg (regs
, dsc
, dsc
->u
.ldst
.rn
, rn_val
, CANNOT_WRITE_PC
);
6596 /* Copy "extra" load/store instructions. These are halfword/doubleword
6597 transfers, which have a different encoding to byte/word transfers. */
6600 arm_copy_extra_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
, int unpriveleged
,
6601 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
6603 unsigned int op1
= bits (insn
, 20, 24);
6604 unsigned int op2
= bits (insn
, 5, 6);
6605 unsigned int rt
= bits (insn
, 12, 15);
6606 unsigned int rn
= bits (insn
, 16, 19);
6607 unsigned int rm
= bits (insn
, 0, 3);
6608 char load
[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1};
6609 char bytesize
[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2};
6610 int immed
= (op1
& 0x4) != 0;
6612 ULONGEST rt_val
, rt_val2
= 0, rn_val
, rm_val
= 0;
6614 if (!insn_references_pc (insn
, 0x000ff00ful
))
6615 return arm_copy_unmodified (gdbarch
, insn
, "extra load/store", dsc
);
6617 if (debug_displaced
)
6618 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %sextra load/store "
6619 "insn %.8lx\n", unpriveleged
? "unpriveleged " : "",
6620 (unsigned long) insn
);
6622 opcode
= ((op2
<< 2) | (op1
& 0x1) | ((op1
& 0x4) >> 1)) - 4;
6625 internal_error (__FILE__
, __LINE__
,
6626 _("copy_extra_ld_st: instruction decode error"));
6628 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6629 dsc
->tmp
[1] = displaced_read_reg (regs
, dsc
, 1);
6630 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6632 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6634 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
6635 if (bytesize
[opcode
] == 8)
6636 rt_val2
= displaced_read_reg (regs
, dsc
, rt
+ 1);
6637 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6639 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6641 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
6642 if (bytesize
[opcode
] == 8)
6643 displaced_write_reg (regs
, dsc
, 1, rt_val2
, CANNOT_WRITE_PC
);
6644 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
6646 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
6649 dsc
->u
.ldst
.xfersize
= bytesize
[opcode
];
6650 dsc
->u
.ldst
.rn
= rn
;
6651 dsc
->u
.ldst
.immed
= immed
;
6652 dsc
->u
.ldst
.writeback
= bit (insn
, 24) == 0 || bit (insn
, 21) != 0;
6653 dsc
->u
.ldst
.restore_r4
= 0;
6656 /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm]
6658 {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */
6659 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
6661 /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm]
6663 {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */
6664 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
6666 dsc
->cleanup
= load
[opcode
] ? &cleanup_load
: &cleanup_store
;
6671 /* Copy byte/half word/word loads and stores. */
6674 install_load_store (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6675 struct displaced_step_closure
*dsc
, int load
,
6676 int immed
, int writeback
, int size
, int usermode
,
6677 int rt
, int rm
, int rn
)
6679 ULONGEST rt_val
, rn_val
, rm_val
= 0;
6681 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6682 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6684 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6686 dsc
->tmp
[4] = displaced_read_reg (regs
, dsc
, 4);
6688 rt_val
= displaced_read_reg (regs
, dsc
, rt
);
6689 rn_val
= displaced_read_reg (regs
, dsc
, rn
);
6691 rm_val
= displaced_read_reg (regs
, dsc
, rm
);
6693 displaced_write_reg (regs
, dsc
, 0, rt_val
, CANNOT_WRITE_PC
);
6694 displaced_write_reg (regs
, dsc
, 2, rn_val
, CANNOT_WRITE_PC
);
6696 displaced_write_reg (regs
, dsc
, 3, rm_val
, CANNOT_WRITE_PC
);
6698 dsc
->u
.ldst
.xfersize
= size
;
6699 dsc
->u
.ldst
.rn
= rn
;
6700 dsc
->u
.ldst
.immed
= immed
;
6701 dsc
->u
.ldst
.writeback
= writeback
;
6703 /* To write PC we can do:
6705 Before this sequence of instructions:
6706 r0 is the PC value got from displaced_read_reg, so r0 = from + 8;
6707 r2 is the Rn value got from dispalced_read_reg.
6709 Insn1: push {pc} Write address of STR instruction + offset on stack
6710 Insn2: pop {r4} Read it back from stack, r4 = addr(Insn1) + offset
6711 Insn3: sub r4, r4, pc r4 = addr(Insn1) + offset - pc
6712 = addr(Insn1) + offset - addr(Insn3) - 8
6714 Insn4: add r4, r4, #8 r4 = offset - 8
6715 Insn5: add r0, r0, r4 r0 = from + 8 + offset - 8
6717 Insn6: str r0, [r2, #imm] (or str r0, [r2, r3])
6719 Otherwise we don't know what value to write for PC, since the offset is
6720 architecture-dependent (sometimes PC+8, sometimes PC+12). More details
6721 of this can be found in Section "Saving from r15" in
6722 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/Cihbjifh.html */
6724 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
6729 thumb2_copy_load_literal (struct gdbarch
*gdbarch
, uint16_t insn1
,
6730 uint16_t insn2
, struct regcache
*regs
,
6731 struct displaced_step_closure
*dsc
, int size
)
6733 unsigned int u_bit
= bit (insn1
, 7);
6734 unsigned int rt
= bits (insn2
, 12, 15);
6735 int imm12
= bits (insn2
, 0, 11);
6738 if (debug_displaced
)
6739 fprintf_unfiltered (gdb_stdlog
,
6740 "displaced: copying ldr pc (0x%x) R%d %c imm12 %.4x\n",
6741 (unsigned int) dsc
->insn_addr
, rt
, u_bit
? '+' : '-',
6747 /* Rewrite instruction LDR Rt imm12 into:
6749 Prepare: tmp[0] <- r0, tmp[1] <- r2, tmp[2] <- r3, r2 <- pc, r3 <- imm12
6753 Cleanup: rt <- r0, r0 <- tmp[0], r2 <- tmp[1], r3 <- tmp[2]. */
6756 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
6757 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
6758 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
6760 pc_val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
6762 pc_val
= pc_val
& 0xfffffffc;
6764 displaced_write_reg (regs
, dsc
, 2, pc_val
, CANNOT_WRITE_PC
);
6765 displaced_write_reg (regs
, dsc
, 3, imm12
, CANNOT_WRITE_PC
);
6769 dsc
->u
.ldst
.xfersize
= size
;
6770 dsc
->u
.ldst
.immed
= 0;
6771 dsc
->u
.ldst
.writeback
= 0;
6772 dsc
->u
.ldst
.restore_r4
= 0;
6774 /* LDR R0, R2, R3 */
6775 dsc
->modinsn
[0] = 0xf852;
6776 dsc
->modinsn
[1] = 0x3;
6779 dsc
->cleanup
= &cleanup_load
;
6785 thumb2_copy_load_reg_imm (struct gdbarch
*gdbarch
, uint16_t insn1
,
6786 uint16_t insn2
, struct regcache
*regs
,
6787 struct displaced_step_closure
*dsc
,
6788 int writeback
, int immed
)
6790 unsigned int rt
= bits (insn2
, 12, 15);
6791 unsigned int rn
= bits (insn1
, 0, 3);
6792 unsigned int rm
= bits (insn2
, 0, 3); /* Only valid if !immed. */
6793 /* In LDR (register), there is also a register Rm, which is not allowed to
6794 be PC, so we don't have to check it. */
6796 if (rt
!= ARM_PC_REGNUM
&& rn
!= ARM_PC_REGNUM
)
6797 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "load",
6800 if (debug_displaced
)
6801 fprintf_unfiltered (gdb_stdlog
,
6802 "displaced: copying ldr r%d [r%d] insn %.4x%.4x\n",
6803 rt
, rn
, insn1
, insn2
);
6805 install_load_store (gdbarch
, regs
, dsc
, 1, immed
, writeback
, 4,
6808 dsc
->u
.ldst
.restore_r4
= 0;
6811 /* ldr[b]<cond> rt, [rn, #imm], etc.
6813 ldr[b]<cond> r0, [r2, #imm]. */
6815 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
6816 dsc
->modinsn
[1] = insn2
& 0x0fff;
6819 /* ldr[b]<cond> rt, [rn, rm], etc.
6821 ldr[b]<cond> r0, [r2, r3]. */
6823 dsc
->modinsn
[0] = (insn1
& 0xfff0) | 0x2;
6824 dsc
->modinsn
[1] = (insn2
& 0x0ff0) | 0x3;
6834 arm_copy_ldr_str_ldrb_strb (struct gdbarch
*gdbarch
, uint32_t insn
,
6835 struct regcache
*regs
,
6836 struct displaced_step_closure
*dsc
,
6837 int load
, int size
, int usermode
)
6839 int immed
= !bit (insn
, 25);
6840 int writeback
= (bit (insn
, 24) == 0 || bit (insn
, 21) != 0);
6841 unsigned int rt
= bits (insn
, 12, 15);
6842 unsigned int rn
= bits (insn
, 16, 19);
6843 unsigned int rm
= bits (insn
, 0, 3); /* Only valid if !immed. */
6845 if (!insn_references_pc (insn
, 0x000ff00ful
))
6846 return arm_copy_unmodified (gdbarch
, insn
, "load/store", dsc
);
6848 if (debug_displaced
)
6849 fprintf_unfiltered (gdb_stdlog
,
6850 "displaced: copying %s%s r%d [r%d] insn %.8lx\n",
6851 load
? (size
== 1 ? "ldrb" : "ldr")
6852 : (size
== 1 ? "strb" : "str"), usermode
? "t" : "",
6854 (unsigned long) insn
);
6856 install_load_store (gdbarch
, regs
, dsc
, load
, immed
, writeback
, size
,
6857 usermode
, rt
, rm
, rn
);
6859 if (load
|| rt
!= ARM_PC_REGNUM
)
6861 dsc
->u
.ldst
.restore_r4
= 0;
6864 /* {ldr,str}[b]<cond> rt, [rn, #imm], etc.
6866 {ldr,str}[b]<cond> r0, [r2, #imm]. */
6867 dsc
->modinsn
[0] = (insn
& 0xfff00fff) | 0x20000;
6869 /* {ldr,str}[b]<cond> rt, [rn, rm], etc.
6871 {ldr,str}[b]<cond> r0, [r2, r3]. */
6872 dsc
->modinsn
[0] = (insn
& 0xfff00ff0) | 0x20003;
6876 /* We need to use r4 as scratch. Make sure it's restored afterwards. */
6877 dsc
->u
.ldst
.restore_r4
= 1;
6878 dsc
->modinsn
[0] = 0xe92d8000; /* push {pc} */
6879 dsc
->modinsn
[1] = 0xe8bd0010; /* pop {r4} */
6880 dsc
->modinsn
[2] = 0xe044400f; /* sub r4, r4, pc. */
6881 dsc
->modinsn
[3] = 0xe2844008; /* add r4, r4, #8. */
6882 dsc
->modinsn
[4] = 0xe0800004; /* add r0, r0, r4. */
6886 dsc
->modinsn
[5] = (insn
& 0xfff00fff) | 0x20000;
6888 dsc
->modinsn
[5] = (insn
& 0xfff00ff0) | 0x20003;
6893 dsc
->cleanup
= load
? &cleanup_load
: &cleanup_store
;
6898 /* Cleanup LDM instructions with fully-populated register list. This is an
6899 unfortunate corner case: it's impossible to implement correctly by modifying
6900 the instruction. The issue is as follows: we have an instruction,
6904 which we must rewrite to avoid loading PC. A possible solution would be to
6905 do the load in two halves, something like (with suitable cleanup
6909 ldm[id][ab] r8!, {r0-r7}
6911 ldm[id][ab] r8, {r7-r14}
6914 but at present there's no suitable place for <temp>, since the scratch space
6915 is overwritten before the cleanup routine is called. For now, we simply
6916 emulate the instruction. */
6919 cleanup_block_load_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6920 struct displaced_step_closure
*dsc
)
6922 int inc
= dsc
->u
.block
.increment
;
6923 int bump_before
= dsc
->u
.block
.before
? (inc
? 4 : -4) : 0;
6924 int bump_after
= dsc
->u
.block
.before
? 0 : (inc
? 4 : -4);
6925 uint32_t regmask
= dsc
->u
.block
.regmask
;
6926 int regno
= inc
? 0 : 15;
6927 CORE_ADDR xfer_addr
= dsc
->u
.block
.xfer_addr
;
6928 int exception_return
= dsc
->u
.block
.load
&& dsc
->u
.block
.user
6929 && (regmask
& 0x8000) != 0;
6930 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6931 int do_transfer
= condition_true (dsc
->u
.block
.cond
, status
);
6932 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6937 /* If the instruction is ldm rN, {...pc}^, I don't think there's anything
6938 sensible we can do here. Complain loudly. */
6939 if (exception_return
)
6940 error (_("Cannot single-step exception return"));
6942 /* We don't handle any stores here for now. */
6943 gdb_assert (dsc
->u
.block
.load
!= 0);
6945 if (debug_displaced
)
6946 fprintf_unfiltered (gdb_stdlog
, "displaced: emulating block transfer: "
6947 "%s %s %s\n", dsc
->u
.block
.load
? "ldm" : "stm",
6948 dsc
->u
.block
.increment
? "inc" : "dec",
6949 dsc
->u
.block
.before
? "before" : "after");
6956 while (regno
<= ARM_PC_REGNUM
&& (regmask
& (1 << regno
)) == 0)
6959 while (regno
>= 0 && (regmask
& (1 << regno
)) == 0)
6962 xfer_addr
+= bump_before
;
6964 memword
= read_memory_unsigned_integer (xfer_addr
, 4, byte_order
);
6965 displaced_write_reg (regs
, dsc
, regno
, memword
, LOAD_WRITE_PC
);
6967 xfer_addr
+= bump_after
;
6969 regmask
&= ~(1 << regno
);
6972 if (dsc
->u
.block
.writeback
)
6973 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, xfer_addr
,
6977 /* Clean up an STM which included the PC in the register list. */
6980 cleanup_block_store_pc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
6981 struct displaced_step_closure
*dsc
)
6983 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
6984 int store_executed
= condition_true (dsc
->u
.block
.cond
, status
);
6985 CORE_ADDR pc_stored_at
, transferred_regs
= bitcount (dsc
->u
.block
.regmask
);
6986 CORE_ADDR stm_insn_addr
;
6989 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6991 /* If condition code fails, there's nothing else to do. */
6992 if (!store_executed
)
6995 if (dsc
->u
.block
.increment
)
6997 pc_stored_at
= dsc
->u
.block
.xfer_addr
+ 4 * transferred_regs
;
6999 if (dsc
->u
.block
.before
)
7004 pc_stored_at
= dsc
->u
.block
.xfer_addr
;
7006 if (dsc
->u
.block
.before
)
7010 pc_val
= read_memory_unsigned_integer (pc_stored_at
, 4, byte_order
);
7011 stm_insn_addr
= dsc
->scratch_base
;
7012 offset
= pc_val
- stm_insn_addr
;
7014 if (debug_displaced
)
7015 fprintf_unfiltered (gdb_stdlog
, "displaced: detected PC offset %.8lx for "
7016 "STM instruction\n", offset
);
7018 /* Rewrite the stored PC to the proper value for the non-displaced original
7020 write_memory_unsigned_integer (pc_stored_at
, 4, byte_order
,
7021 dsc
->insn_addr
+ offset
);
7024 /* Clean up an LDM which includes the PC in the register list. We clumped all
7025 the registers in the transferred list into a contiguous range r0...rX (to
7026 avoid loading PC directly and losing control of the debugged program), so we
7027 must undo that here. */
7030 cleanup_block_load_pc (struct gdbarch
*gdbarch
,
7031 struct regcache
*regs
,
7032 struct displaced_step_closure
*dsc
)
7034 uint32_t status
= displaced_read_reg (regs
, dsc
, ARM_PS_REGNUM
);
7035 int load_executed
= condition_true (dsc
->u
.block
.cond
, status
);
7036 unsigned int mask
= dsc
->u
.block
.regmask
, write_reg
= ARM_PC_REGNUM
;
7037 unsigned int regs_loaded
= bitcount (mask
);
7038 unsigned int num_to_shuffle
= regs_loaded
, clobbered
;
7040 /* The method employed here will fail if the register list is fully populated
7041 (we need to avoid loading PC directly). */
7042 gdb_assert (num_to_shuffle
< 16);
7047 clobbered
= (1 << num_to_shuffle
) - 1;
7049 while (num_to_shuffle
> 0)
7051 if ((mask
& (1 << write_reg
)) != 0)
7053 unsigned int read_reg
= num_to_shuffle
- 1;
7055 if (read_reg
!= write_reg
)
7057 ULONGEST rval
= displaced_read_reg (regs
, dsc
, read_reg
);
7058 displaced_write_reg (regs
, dsc
, write_reg
, rval
, LOAD_WRITE_PC
);
7059 if (debug_displaced
)
7060 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: move "
7061 "loaded register r%d to r%d\n"), read_reg
,
7064 else if (debug_displaced
)
7065 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: register "
7066 "r%d already in the right place\n"),
7069 clobbered
&= ~(1 << write_reg
);
7077 /* Restore any registers we scribbled over. */
7078 for (write_reg
= 0; clobbered
!= 0; write_reg
++)
7080 if ((clobbered
& (1 << write_reg
)) != 0)
7082 displaced_write_reg (regs
, dsc
, write_reg
, dsc
->tmp
[write_reg
],
7084 if (debug_displaced
)
7085 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM: restored "
7086 "clobbered register r%d\n"), write_reg
);
7087 clobbered
&= ~(1 << write_reg
);
7091 /* Perform register writeback manually. */
7092 if (dsc
->u
.block
.writeback
)
7094 ULONGEST new_rn_val
= dsc
->u
.block
.xfer_addr
;
7096 if (dsc
->u
.block
.increment
)
7097 new_rn_val
+= regs_loaded
* 4;
7099 new_rn_val
-= regs_loaded
* 4;
7101 displaced_write_reg (regs
, dsc
, dsc
->u
.block
.rn
, new_rn_val
,
7106 /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur
7107 in user-level code (in particular exception return, ldm rn, {...pc}^). */
7110 arm_copy_block_xfer (struct gdbarch
*gdbarch
, uint32_t insn
,
7111 struct regcache
*regs
,
7112 struct displaced_step_closure
*dsc
)
7114 int load
= bit (insn
, 20);
7115 int user
= bit (insn
, 22);
7116 int increment
= bit (insn
, 23);
7117 int before
= bit (insn
, 24);
7118 int writeback
= bit (insn
, 21);
7119 int rn
= bits (insn
, 16, 19);
7121 /* Block transfers which don't mention PC can be run directly
7123 if (rn
!= ARM_PC_REGNUM
&& (insn
& 0x8000) == 0)
7124 return arm_copy_unmodified (gdbarch
, insn
, "ldm/stm", dsc
);
7126 if (rn
== ARM_PC_REGNUM
)
7128 warning (_("displaced: Unpredictable LDM or STM with "
7129 "base register r15"));
7130 return arm_copy_unmodified (gdbarch
, insn
, "unpredictable ldm/stm", dsc
);
7133 if (debug_displaced
)
7134 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
7135 "%.8lx\n", (unsigned long) insn
);
7137 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
7138 dsc
->u
.block
.rn
= rn
;
7140 dsc
->u
.block
.load
= load
;
7141 dsc
->u
.block
.user
= user
;
7142 dsc
->u
.block
.increment
= increment
;
7143 dsc
->u
.block
.before
= before
;
7144 dsc
->u
.block
.writeback
= writeback
;
7145 dsc
->u
.block
.cond
= bits (insn
, 28, 31);
7147 dsc
->u
.block
.regmask
= insn
& 0xffff;
7151 if ((insn
& 0xffff) == 0xffff)
7153 /* LDM with a fully-populated register list. This case is
7154 particularly tricky. Implement for now by fully emulating the
7155 instruction (which might not behave perfectly in all cases, but
7156 these instructions should be rare enough for that not to matter
7158 dsc
->modinsn
[0] = ARM_NOP
;
7160 dsc
->cleanup
= &cleanup_block_load_all
;
7164 /* LDM of a list of registers which includes PC. Implement by
7165 rewriting the list of registers to be transferred into a
7166 contiguous chunk r0...rX before doing the transfer, then shuffling
7167 registers into the correct places in the cleanup routine. */
7168 unsigned int regmask
= insn
& 0xffff;
7169 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
7170 unsigned int to
= 0, from
= 0, i
, new_rn
;
7172 for (i
= 0; i
< num_in_list
; i
++)
7173 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7175 /* Writeback makes things complicated. We need to avoid clobbering
7176 the base register with one of the registers in our modified
7177 register list, but just using a different register can't work in
7180 ldm r14!, {r0-r13,pc}
7182 which would need to be rewritten as:
7186 but that can't work, because there's no free register for N.
7188 Solve this by turning off the writeback bit, and emulating
7189 writeback manually in the cleanup routine. */
7194 new_regmask
= (1 << num_in_list
) - 1;
7196 if (debug_displaced
)
7197 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
7198 "{..., pc}: original reg list %.4x, modified "
7199 "list %.4x\n"), rn
, writeback
? "!" : "",
7200 (int) insn
& 0xffff, new_regmask
);
7202 dsc
->modinsn
[0] = (insn
& ~0xffff) | (new_regmask
& 0xffff);
7204 dsc
->cleanup
= &cleanup_block_load_pc
;
7209 /* STM of a list of registers which includes PC. Run the instruction
7210 as-is, but out of line: this will store the wrong value for the PC,
7211 so we must manually fix up the memory in the cleanup routine.
7212 Doing things this way has the advantage that we can auto-detect
7213 the offset of the PC write (which is architecture-dependent) in
7214 the cleanup routine. */
7215 dsc
->modinsn
[0] = insn
;
7217 dsc
->cleanup
= &cleanup_block_store_pc
;
7224 thumb2_copy_block_xfer (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
7225 struct regcache
*regs
,
7226 struct displaced_step_closure
*dsc
)
7228 int rn
= bits (insn1
, 0, 3);
7229 int load
= bit (insn1
, 4);
7230 int writeback
= bit (insn1
, 5);
7232 /* Block transfers which don't mention PC can be run directly
7234 if (rn
!= ARM_PC_REGNUM
&& (insn2
& 0x8000) == 0)
7235 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "ldm/stm", dsc
);
7237 if (rn
== ARM_PC_REGNUM
)
7239 warning (_("displaced: Unpredictable LDM or STM with "
7240 "base register r15"));
7241 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7242 "unpredictable ldm/stm", dsc
);
7245 if (debug_displaced
)
7246 fprintf_unfiltered (gdb_stdlog
, "displaced: copying block transfer insn "
7247 "%.4x%.4x\n", insn1
, insn2
);
7249 /* Clear bit 13, since it should be always zero. */
7250 dsc
->u
.block
.regmask
= (insn2
& 0xdfff);
7251 dsc
->u
.block
.rn
= rn
;
7253 dsc
->u
.block
.load
= load
;
7254 dsc
->u
.block
.user
= 0;
7255 dsc
->u
.block
.increment
= bit (insn1
, 7);
7256 dsc
->u
.block
.before
= bit (insn1
, 8);
7257 dsc
->u
.block
.writeback
= writeback
;
7258 dsc
->u
.block
.cond
= INST_AL
;
7259 dsc
->u
.block
.xfer_addr
= displaced_read_reg (regs
, dsc
, rn
);
7263 if (dsc
->u
.block
.regmask
== 0xffff)
7265 /* This branch is impossible to happen. */
7270 unsigned int regmask
= dsc
->u
.block
.regmask
;
7271 unsigned int num_in_list
= bitcount (regmask
), new_regmask
, bit
= 1;
7272 unsigned int to
= 0, from
= 0, i
, new_rn
;
7274 for (i
= 0; i
< num_in_list
; i
++)
7275 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
7280 new_regmask
= (1 << num_in_list
) - 1;
7282 if (debug_displaced
)
7283 fprintf_unfiltered (gdb_stdlog
, _("displaced: LDM r%d%s, "
7284 "{..., pc}: original reg list %.4x, modified "
7285 "list %.4x\n"), rn
, writeback
? "!" : "",
7286 (int) dsc
->u
.block
.regmask
, new_regmask
);
7288 dsc
->modinsn
[0] = insn1
;
7289 dsc
->modinsn
[1] = (new_regmask
& 0xffff);
7292 dsc
->cleanup
= &cleanup_block_load_pc
;
7297 dsc
->modinsn
[0] = insn1
;
7298 dsc
->modinsn
[1] = insn2
;
7300 dsc
->cleanup
= &cleanup_block_store_pc
;
7305 /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
7306 for Linux, where some SVC instructions must be treated specially. */
7309 cleanup_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7310 struct displaced_step_closure
*dsc
)
7312 CORE_ADDR resume_addr
= dsc
->insn_addr
+ dsc
->insn_size
;
7314 if (debug_displaced
)
7315 fprintf_unfiltered (gdb_stdlog
, "displaced: cleanup for svc, resume at "
7316 "%.8lx\n", (unsigned long) resume_addr
);
7318 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, resume_addr
, BRANCH_WRITE_PC
);
7322 /* Common copy routine for svc instruciton. */
7325 install_svc (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7326 struct displaced_step_closure
*dsc
)
7328 /* Preparation: none.
7329 Insn: unmodified svc.
7330 Cleanup: pc <- insn_addr + insn_size. */
7332 /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next
7334 dsc
->wrote_to_pc
= 1;
7336 /* Allow OS-specific code to override SVC handling. */
7337 if (dsc
->u
.svc
.copy_svc_os
)
7338 return dsc
->u
.svc
.copy_svc_os (gdbarch
, regs
, dsc
);
7341 dsc
->cleanup
= &cleanup_svc
;
7347 arm_copy_svc (struct gdbarch
*gdbarch
, uint32_t insn
,
7348 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7351 if (debug_displaced
)
7352 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.8lx\n",
7353 (unsigned long) insn
);
7355 dsc
->modinsn
[0] = insn
;
7357 return install_svc (gdbarch
, regs
, dsc
);
7361 thumb_copy_svc (struct gdbarch
*gdbarch
, uint16_t insn
,
7362 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7365 if (debug_displaced
)
7366 fprintf_unfiltered (gdb_stdlog
, "displaced: copying svc insn %.4x\n",
7369 dsc
->modinsn
[0] = insn
;
7371 return install_svc (gdbarch
, regs
, dsc
);
7374 /* Copy undefined instructions. */
7377 arm_copy_undef (struct gdbarch
*gdbarch
, uint32_t insn
,
7378 struct displaced_step_closure
*dsc
)
7380 if (debug_displaced
)
7381 fprintf_unfiltered (gdb_stdlog
,
7382 "displaced: copying undefined insn %.8lx\n",
7383 (unsigned long) insn
);
7385 dsc
->modinsn
[0] = insn
;
7391 thumb_32bit_copy_undef (struct gdbarch
*gdbarch
, uint16_t insn1
, uint16_t insn2
,
7392 struct displaced_step_closure
*dsc
)
7395 if (debug_displaced
)
7396 fprintf_unfiltered (gdb_stdlog
, "displaced: copying undefined insn "
7397 "%.4x %.4x\n", (unsigned short) insn1
,
7398 (unsigned short) insn2
);
7400 dsc
->modinsn
[0] = insn1
;
7401 dsc
->modinsn
[1] = insn2
;
7407 /* Copy unpredictable instructions. */
7410 arm_copy_unpred (struct gdbarch
*gdbarch
, uint32_t insn
,
7411 struct displaced_step_closure
*dsc
)
7413 if (debug_displaced
)
7414 fprintf_unfiltered (gdb_stdlog
, "displaced: copying unpredictable insn "
7415 "%.8lx\n", (unsigned long) insn
);
7417 dsc
->modinsn
[0] = insn
;
7422 /* The decode_* functions are instruction decoding helpers. They mostly follow
7423 the presentation in the ARM ARM. */
7426 arm_decode_misc_memhint_neon (struct gdbarch
*gdbarch
, uint32_t insn
,
7427 struct regcache
*regs
,
7428 struct displaced_step_closure
*dsc
)
7430 unsigned int op1
= bits (insn
, 20, 26), op2
= bits (insn
, 4, 7);
7431 unsigned int rn
= bits (insn
, 16, 19);
7433 if (op1
== 0x10 && (op2
& 0x2) == 0x0 && (rn
& 0xe) == 0x0)
7434 return arm_copy_unmodified (gdbarch
, insn
, "cps", dsc
);
7435 else if (op1
== 0x10 && op2
== 0x0 && (rn
& 0xe) == 0x1)
7436 return arm_copy_unmodified (gdbarch
, insn
, "setend", dsc
);
7437 else if ((op1
& 0x60) == 0x20)
7438 return arm_copy_unmodified (gdbarch
, insn
, "neon dataproc", dsc
);
7439 else if ((op1
& 0x71) == 0x40)
7440 return arm_copy_unmodified (gdbarch
, insn
, "neon elt/struct load/store",
7442 else if ((op1
& 0x77) == 0x41)
7443 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
7444 else if ((op1
& 0x77) == 0x45)
7445 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pli. */
7446 else if ((op1
& 0x77) == 0x51)
7449 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
7451 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7453 else if ((op1
& 0x77) == 0x55)
7454 return arm_copy_preload (gdbarch
, insn
, regs
, dsc
); /* pld/pldw. */
7455 else if (op1
== 0x57)
7458 case 0x1: return arm_copy_unmodified (gdbarch
, insn
, "clrex", dsc
);
7459 case 0x4: return arm_copy_unmodified (gdbarch
, insn
, "dsb", dsc
);
7460 case 0x5: return arm_copy_unmodified (gdbarch
, insn
, "dmb", dsc
);
7461 case 0x6: return arm_copy_unmodified (gdbarch
, insn
, "isb", dsc
);
7462 default: return arm_copy_unpred (gdbarch
, insn
, dsc
);
7464 else if ((op1
& 0x63) == 0x43)
7465 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7466 else if ((op2
& 0x1) == 0x0)
7467 switch (op1
& ~0x80)
7470 return arm_copy_unmodified (gdbarch
, insn
, "unallocated mem hint", dsc
);
7472 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
); /* pli reg. */
7473 case 0x71: case 0x75:
7475 return arm_copy_preload_reg (gdbarch
, insn
, regs
, dsc
);
7476 case 0x63: case 0x67: case 0x73: case 0x77:
7477 return arm_copy_unpred (gdbarch
, insn
, dsc
);
7479 return arm_copy_undef (gdbarch
, insn
, dsc
);
7482 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Probably unreachable. */
7486 arm_decode_unconditional (struct gdbarch
*gdbarch
, uint32_t insn
,
7487 struct regcache
*regs
,
7488 struct displaced_step_closure
*dsc
)
7490 if (bit (insn
, 27) == 0)
7491 return arm_decode_misc_memhint_neon (gdbarch
, insn
, regs
, dsc
);
7492 /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */
7493 else switch (((insn
& 0x7000000) >> 23) | ((insn
& 0x100000) >> 20))
7496 return arm_copy_unmodified (gdbarch
, insn
, "srs", dsc
);
7499 return arm_copy_unmodified (gdbarch
, insn
, "rfe", dsc
);
7501 case 0x4: case 0x5: case 0x6: case 0x7:
7502 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
7505 switch ((insn
& 0xe00000) >> 21)
7507 case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
7509 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7512 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
7515 return arm_copy_undef (gdbarch
, insn
, dsc
);
7520 int rn_f
= (bits (insn
, 16, 19) == 0xf);
7521 switch ((insn
& 0xe00000) >> 21)
7524 /* ldc/ldc2 imm (undefined for rn == pc). */
7525 return rn_f
? arm_copy_undef (gdbarch
, insn
, dsc
)
7526 : arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7529 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
7531 case 0x4: case 0x5: case 0x6: case 0x7:
7532 /* ldc/ldc2 lit (undefined for rn != pc). */
7533 return rn_f
? arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
)
7534 : arm_copy_undef (gdbarch
, insn
, dsc
);
7537 return arm_copy_undef (gdbarch
, insn
, dsc
);
7542 return arm_copy_unmodified (gdbarch
, insn
, "stc/stc2", dsc
);
7545 if (bits (insn
, 16, 19) == 0xf)
7547 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7549 return arm_copy_undef (gdbarch
, insn
, dsc
);
7553 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
7555 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7559 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
7561 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7564 return arm_copy_undef (gdbarch
, insn
, dsc
);
7568 /* Decode miscellaneous instructions in dp/misc encoding space. */
7571 arm_decode_miscellaneous (struct gdbarch
*gdbarch
, uint32_t insn
,
7572 struct regcache
*regs
,
7573 struct displaced_step_closure
*dsc
)
7575 unsigned int op2
= bits (insn
, 4, 6);
7576 unsigned int op
= bits (insn
, 21, 22);
7577 unsigned int op1
= bits (insn
, 16, 19);
7582 return arm_copy_unmodified (gdbarch
, insn
, "mrs/msr", dsc
);
7585 if (op
== 0x1) /* bx. */
7586 return arm_copy_bx_blx_reg (gdbarch
, insn
, regs
, dsc
);
7588 return arm_copy_unmodified (gdbarch
, insn
, "clz", dsc
);
7590 return arm_copy_undef (gdbarch
, insn
, dsc
);
7594 /* Not really supported. */
7595 return arm_copy_unmodified (gdbarch
, insn
, "bxj", dsc
);
7597 return arm_copy_undef (gdbarch
, insn
, dsc
);
7601 return arm_copy_bx_blx_reg (gdbarch
, insn
,
7602 regs
, dsc
); /* blx register. */
7604 return arm_copy_undef (gdbarch
, insn
, dsc
);
7607 return arm_copy_unmodified (gdbarch
, insn
, "saturating add/sub", dsc
);
7611 return arm_copy_unmodified (gdbarch
, insn
, "bkpt", dsc
);
7613 /* Not really supported. */
7614 return arm_copy_unmodified (gdbarch
, insn
, "smc", dsc
);
7617 return arm_copy_undef (gdbarch
, insn
, dsc
);
7622 arm_decode_dp_misc (struct gdbarch
*gdbarch
, uint32_t insn
,
7623 struct regcache
*regs
,
7624 struct displaced_step_closure
*dsc
)
7627 switch (bits (insn
, 20, 24))
7630 return arm_copy_unmodified (gdbarch
, insn
, "movw", dsc
);
7633 return arm_copy_unmodified (gdbarch
, insn
, "movt", dsc
);
7635 case 0x12: case 0x16:
7636 return arm_copy_unmodified (gdbarch
, insn
, "msr imm", dsc
);
7639 return arm_copy_alu_imm (gdbarch
, insn
, regs
, dsc
);
7643 uint32_t op1
= bits (insn
, 20, 24), op2
= bits (insn
, 4, 7);
7645 if ((op1
& 0x19) != 0x10 && (op2
& 0x1) == 0x0)
7646 return arm_copy_alu_reg (gdbarch
, insn
, regs
, dsc
);
7647 else if ((op1
& 0x19) != 0x10 && (op2
& 0x9) == 0x1)
7648 return arm_copy_alu_shifted_reg (gdbarch
, insn
, regs
, dsc
);
7649 else if ((op1
& 0x19) == 0x10 && (op2
& 0x8) == 0x0)
7650 return arm_decode_miscellaneous (gdbarch
, insn
, regs
, dsc
);
7651 else if ((op1
& 0x19) == 0x10 && (op2
& 0x9) == 0x8)
7652 return arm_copy_unmodified (gdbarch
, insn
, "halfword mul/mla", dsc
);
7653 else if ((op1
& 0x10) == 0x00 && op2
== 0x9)
7654 return arm_copy_unmodified (gdbarch
, insn
, "mul/mla", dsc
);
7655 else if ((op1
& 0x10) == 0x10 && op2
== 0x9)
7656 return arm_copy_unmodified (gdbarch
, insn
, "synch", dsc
);
7657 else if (op2
== 0xb || (op2
& 0xd) == 0xd)
7658 /* 2nd arg means "unpriveleged". */
7659 return arm_copy_extra_ld_st (gdbarch
, insn
, (op1
& 0x12) == 0x02, regs
,
7663 /* Should be unreachable. */
7668 arm_decode_ld_st_word_ubyte (struct gdbarch
*gdbarch
, uint32_t insn
,
7669 struct regcache
*regs
,
7670 struct displaced_step_closure
*dsc
)
7672 int a
= bit (insn
, 25), b
= bit (insn
, 4);
7673 uint32_t op1
= bits (insn
, 20, 24);
7674 int rn_f
= bits (insn
, 16, 19) == 0xf;
7676 if ((!a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02)
7677 || (a
&& (op1
& 0x05) == 0x00 && (op1
& 0x17) != 0x02 && !b
))
7678 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 0);
7679 else if ((!a
&& (op1
& 0x17) == 0x02)
7680 || (a
&& (op1
& 0x17) == 0x02 && !b
))
7681 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 4, 1);
7682 else if ((!a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03)
7683 || (a
&& (op1
& 0x05) == 0x01 && (op1
& 0x17) != 0x03 && !b
))
7684 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 0);
7685 else if ((!a
&& (op1
& 0x17) == 0x03)
7686 || (a
&& (op1
& 0x17) == 0x03 && !b
))
7687 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 4, 1);
7688 else if ((!a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06)
7689 || (a
&& (op1
& 0x05) == 0x04 && (op1
& 0x17) != 0x06 && !b
))
7690 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 0);
7691 else if ((!a
&& (op1
& 0x17) == 0x06)
7692 || (a
&& (op1
& 0x17) == 0x06 && !b
))
7693 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 0, 1, 1);
7694 else if ((!a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07)
7695 || (a
&& (op1
& 0x05) == 0x05 && (op1
& 0x17) != 0x07 && !b
))
7696 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 0);
7697 else if ((!a
&& (op1
& 0x17) == 0x07)
7698 || (a
&& (op1
& 0x17) == 0x07 && !b
))
7699 return arm_copy_ldr_str_ldrb_strb (gdbarch
, insn
, regs
, dsc
, 1, 1, 1);
7701 /* Should be unreachable. */
7706 arm_decode_media (struct gdbarch
*gdbarch
, uint32_t insn
,
7707 struct displaced_step_closure
*dsc
)
7709 switch (bits (insn
, 20, 24))
7711 case 0x00: case 0x01: case 0x02: case 0x03:
7712 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub signed", dsc
);
7714 case 0x04: case 0x05: case 0x06: case 0x07:
7715 return arm_copy_unmodified (gdbarch
, insn
, "parallel add/sub unsigned", dsc
);
7717 case 0x08: case 0x09: case 0x0a: case 0x0b:
7718 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
7719 return arm_copy_unmodified (gdbarch
, insn
,
7720 "decode/pack/unpack/saturate/reverse", dsc
);
7723 if (bits (insn
, 5, 7) == 0) /* op2. */
7725 if (bits (insn
, 12, 15) == 0xf)
7726 return arm_copy_unmodified (gdbarch
, insn
, "usad8", dsc
);
7728 return arm_copy_unmodified (gdbarch
, insn
, "usada8", dsc
);
7731 return arm_copy_undef (gdbarch
, insn
, dsc
);
7733 case 0x1a: case 0x1b:
7734 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
7735 return arm_copy_unmodified (gdbarch
, insn
, "sbfx", dsc
);
7737 return arm_copy_undef (gdbarch
, insn
, dsc
);
7739 case 0x1c: case 0x1d:
7740 if (bits (insn
, 5, 6) == 0x0) /* op2[1:0]. */
7742 if (bits (insn
, 0, 3) == 0xf)
7743 return arm_copy_unmodified (gdbarch
, insn
, "bfc", dsc
);
7745 return arm_copy_unmodified (gdbarch
, insn
, "bfi", dsc
);
7748 return arm_copy_undef (gdbarch
, insn
, dsc
);
7750 case 0x1e: case 0x1f:
7751 if (bits (insn
, 5, 6) == 0x2) /* op2[1:0]. */
7752 return arm_copy_unmodified (gdbarch
, insn
, "ubfx", dsc
);
7754 return arm_copy_undef (gdbarch
, insn
, dsc
);
7757 /* Should be unreachable. */
7762 arm_decode_b_bl_ldmstm (struct gdbarch
*gdbarch
, int32_t insn
,
7763 struct regcache
*regs
,
7764 struct displaced_step_closure
*dsc
)
7767 return arm_copy_b_bl_blx (gdbarch
, insn
, regs
, dsc
);
7769 return arm_copy_block_xfer (gdbarch
, insn
, regs
, dsc
);
7773 arm_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint32_t insn
,
7774 struct regcache
*regs
,
7775 struct displaced_step_closure
*dsc
)
7777 unsigned int opcode
= bits (insn
, 20, 24);
7781 case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */
7782 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon mrrc/mcrr", dsc
);
7784 case 0x08: case 0x0a: case 0x0c: case 0x0e:
7785 case 0x12: case 0x16:
7786 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vstm/vpush", dsc
);
7788 case 0x09: case 0x0b: case 0x0d: case 0x0f:
7789 case 0x13: case 0x17:
7790 return arm_copy_unmodified (gdbarch
, insn
, "vfp/neon vldm/vpop", dsc
);
7792 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7793 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7794 /* Note: no writeback for these instructions. Bit 25 will always be
7795 zero though (via caller), so the following works OK. */
7796 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7799 /* Should be unreachable. */
7803 /* Decode shifted register instructions. */
7806 thumb2_decode_dp_shift_reg (struct gdbarch
*gdbarch
, uint16_t insn1
,
7807 uint16_t insn2
, struct regcache
*regs
,
7808 struct displaced_step_closure
*dsc
)
7810 /* PC is only allowed to be used in instruction MOV. */
7812 unsigned int op
= bits (insn1
, 5, 8);
7813 unsigned int rn
= bits (insn1
, 0, 3);
7815 if (op
== 0x2 && rn
== 0xf) /* MOV */
7816 return thumb2_copy_alu_imm (gdbarch
, insn1
, insn2
, regs
, dsc
);
7818 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7819 "dp (shift reg)", dsc
);
7823 /* Decode extension register load/store. Exactly the same as
7824 arm_decode_ext_reg_ld_st. */
7827 thumb2_decode_ext_reg_ld_st (struct gdbarch
*gdbarch
, uint16_t insn1
,
7828 uint16_t insn2
, struct regcache
*regs
,
7829 struct displaced_step_closure
*dsc
)
7831 unsigned int opcode
= bits (insn1
, 4, 8);
7835 case 0x04: case 0x05:
7836 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7837 "vfp/neon vmov", dsc
);
7839 case 0x08: case 0x0c: /* 01x00 */
7840 case 0x0a: case 0x0e: /* 01x10 */
7841 case 0x12: case 0x16: /* 10x10 */
7842 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7843 "vfp/neon vstm/vpush", dsc
);
7845 case 0x09: case 0x0d: /* 01x01 */
7846 case 0x0b: case 0x0f: /* 01x11 */
7847 case 0x13: case 0x17: /* 10x11 */
7848 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7849 "vfp/neon vldm/vpop", dsc
);
7851 case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */
7852 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7854 case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */
7855 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
, regs
, dsc
);
7858 /* Should be unreachable. */
7863 arm_decode_svc_copro (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
7864 struct regcache
*regs
, struct displaced_step_closure
*dsc
)
7866 unsigned int op1
= bits (insn
, 20, 25);
7867 int op
= bit (insn
, 4);
7868 unsigned int coproc
= bits (insn
, 8, 11);
7869 unsigned int rn
= bits (insn
, 16, 19);
7871 if ((op1
& 0x20) == 0x00 && (op1
& 0x3a) != 0x00 && (coproc
& 0xe) == 0xa)
7872 return arm_decode_ext_reg_ld_st (gdbarch
, insn
, regs
, dsc
);
7873 else if ((op1
& 0x21) == 0x00 && (op1
& 0x3a) != 0x00
7874 && (coproc
& 0xe) != 0xa)
7876 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7877 else if ((op1
& 0x21) == 0x01 && (op1
& 0x3a) != 0x00
7878 && (coproc
& 0xe) != 0xa)
7879 /* ldc/ldc2 imm/lit. */
7880 return arm_copy_copro_load_store (gdbarch
, insn
, regs
, dsc
);
7881 else if ((op1
& 0x3e) == 0x00)
7882 return arm_copy_undef (gdbarch
, insn
, dsc
);
7883 else if ((op1
& 0x3e) == 0x04 && (coproc
& 0xe) == 0xa)
7884 return arm_copy_unmodified (gdbarch
, insn
, "neon 64bit xfer", dsc
);
7885 else if (op1
== 0x04 && (coproc
& 0xe) != 0xa)
7886 return arm_copy_unmodified (gdbarch
, insn
, "mcrr/mcrr2", dsc
);
7887 else if (op1
== 0x05 && (coproc
& 0xe) != 0xa)
7888 return arm_copy_unmodified (gdbarch
, insn
, "mrrc/mrrc2", dsc
);
7889 else if ((op1
& 0x30) == 0x20 && !op
)
7891 if ((coproc
& 0xe) == 0xa)
7892 return arm_copy_unmodified (gdbarch
, insn
, "vfp dataproc", dsc
);
7894 return arm_copy_unmodified (gdbarch
, insn
, "cdp/cdp2", dsc
);
7896 else if ((op1
& 0x30) == 0x20 && op
)
7897 return arm_copy_unmodified (gdbarch
, insn
, "neon 8/16/32 bit xfer", dsc
);
7898 else if ((op1
& 0x31) == 0x20 && op
&& (coproc
& 0xe) != 0xa)
7899 return arm_copy_unmodified (gdbarch
, insn
, "mcr/mcr2", dsc
);
7900 else if ((op1
& 0x31) == 0x21 && op
&& (coproc
& 0xe) != 0xa)
7901 return arm_copy_unmodified (gdbarch
, insn
, "mrc/mrc2", dsc
);
7902 else if ((op1
& 0x30) == 0x30)
7903 return arm_copy_svc (gdbarch
, insn
, regs
, dsc
);
7905 return arm_copy_undef (gdbarch
, insn
, dsc
); /* Possibly unreachable. */
7909 thumb2_decode_svc_copro (struct gdbarch
*gdbarch
, uint16_t insn1
,
7910 uint16_t insn2
, struct regcache
*regs
,
7911 struct displaced_step_closure
*dsc
)
7913 unsigned int coproc
= bits (insn2
, 8, 11);
7914 unsigned int op1
= bits (insn1
, 4, 9);
7915 unsigned int bit_5_8
= bits (insn1
, 5, 8);
7916 unsigned int bit_9
= bit (insn1
, 9);
7917 unsigned int bit_4
= bit (insn1
, 4);
7918 unsigned int rn
= bits (insn1
, 0, 3);
7923 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7924 "neon 64bit xfer/mrrc/mrrc2/mcrr/mcrr2",
7926 else if (bit_5_8
== 0) /* UNDEFINED. */
7927 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
7930 /*coproc is 101x. SIMD/VFP, ext registers load/store. */
7931 if ((coproc
& 0xe) == 0xa)
7932 return thumb2_decode_ext_reg_ld_st (gdbarch
, insn1
, insn2
, regs
,
7934 else /* coproc is not 101x. */
7936 if (bit_4
== 0) /* STC/STC2. */
7937 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
7939 else /* LDC/LDC2 {literal, immeidate}. */
7940 return thumb2_copy_copro_load_store (gdbarch
, insn1
, insn2
,
7946 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
, "coproc", dsc
);
7952 install_pc_relative (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7953 struct displaced_step_closure
*dsc
, int rd
)
7959 Preparation: Rd <- PC
7965 int val
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
7966 displaced_write_reg (regs
, dsc
, rd
, val
, CANNOT_WRITE_PC
);
7970 thumb_copy_pc_relative_16bit (struct gdbarch
*gdbarch
, struct regcache
*regs
,
7971 struct displaced_step_closure
*dsc
,
7972 int rd
, unsigned int imm
)
7975 /* Encoding T2: ADDS Rd, #imm */
7976 dsc
->modinsn
[0] = (0x3000 | (rd
<< 8) | imm
);
7978 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
7984 thumb_decode_pc_relative_16bit (struct gdbarch
*gdbarch
, uint16_t insn
,
7985 struct regcache
*regs
,
7986 struct displaced_step_closure
*dsc
)
7988 unsigned int rd
= bits (insn
, 8, 10);
7989 unsigned int imm8
= bits (insn
, 0, 7);
7991 if (debug_displaced
)
7992 fprintf_unfiltered (gdb_stdlog
,
7993 "displaced: copying thumb adr r%d, #%d insn %.4x\n",
7996 return thumb_copy_pc_relative_16bit (gdbarch
, regs
, dsc
, rd
, imm8
);
8000 thumb_copy_pc_relative_32bit (struct gdbarch
*gdbarch
, uint16_t insn1
,
8001 uint16_t insn2
, struct regcache
*regs
,
8002 struct displaced_step_closure
*dsc
)
8004 unsigned int rd
= bits (insn2
, 8, 11);
8005 /* Since immediate has the same encoding in ADR ADD and SUB, so we simply
8006 extract raw immediate encoding rather than computing immediate. When
8007 generating ADD or SUB instruction, we can simply perform OR operation to
8008 set immediate into ADD. */
8009 unsigned int imm_3_8
= insn2
& 0x70ff;
8010 unsigned int imm_i
= insn1
& 0x0400; /* Clear all bits except bit 10. */
8012 if (debug_displaced
)
8013 fprintf_unfiltered (gdb_stdlog
,
8014 "displaced: copying thumb adr r%d, #%d:%d insn %.4x%.4x\n",
8015 rd
, imm_i
, imm_3_8
, insn1
, insn2
);
8017 if (bit (insn1
, 7)) /* Encoding T2 */
8019 /* Encoding T3: SUB Rd, Rd, #imm */
8020 dsc
->modinsn
[0] = (0xf1a0 | rd
| imm_i
);
8021 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
8023 else /* Encoding T3 */
8025 /* Encoding T3: ADD Rd, Rd, #imm */
8026 dsc
->modinsn
[0] = (0xf100 | rd
| imm_i
);
8027 dsc
->modinsn
[1] = ((rd
<< 8) | imm_3_8
);
8031 install_pc_relative (gdbarch
, regs
, dsc
, rd
);
8037 thumb_copy_16bit_ldr_literal (struct gdbarch
*gdbarch
, unsigned short insn1
,
8038 struct regcache
*regs
,
8039 struct displaced_step_closure
*dsc
)
8041 unsigned int rt
= bits (insn1
, 8, 10);
8043 int imm8
= (bits (insn1
, 0, 7) << 2);
8044 CORE_ADDR from
= dsc
->insn_addr
;
8050 Preparation: tmp0 <- R0, tmp2 <- R2, tmp3 <- R3, R2 <- PC, R3 <- #imm8;
8052 Insn: LDR R0, [R2, R3];
8053 Cleanup: R2 <- tmp2, R3 <- tmp3, Rd <- R0, R0 <- tmp0 */
8055 if (debug_displaced
)
8056 fprintf_unfiltered (gdb_stdlog
,
8057 "displaced: copying thumb ldr r%d [pc #%d]\n"
8060 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 0);
8061 dsc
->tmp
[2] = displaced_read_reg (regs
, dsc
, 2);
8062 dsc
->tmp
[3] = displaced_read_reg (regs
, dsc
, 3);
8063 pc
= displaced_read_reg (regs
, dsc
, ARM_PC_REGNUM
);
8064 /* The assembler calculates the required value of the offset from the
8065 Align(PC,4) value of this instruction to the label. */
8066 pc
= pc
& 0xfffffffc;
8068 displaced_write_reg (regs
, dsc
, 2, pc
, CANNOT_WRITE_PC
);
8069 displaced_write_reg (regs
, dsc
, 3, imm8
, CANNOT_WRITE_PC
);
8072 dsc
->u
.ldst
.xfersize
= 4;
8074 dsc
->u
.ldst
.immed
= 0;
8075 dsc
->u
.ldst
.writeback
= 0;
8076 dsc
->u
.ldst
.restore_r4
= 0;
8078 dsc
->modinsn
[0] = 0x58d0; /* ldr r0, [r2, r3]*/
8080 dsc
->cleanup
= &cleanup_load
;
8085 /* Copy Thumb cbnz/cbz insruction. */
8088 thumb_copy_cbnz_cbz (struct gdbarch
*gdbarch
, uint16_t insn1
,
8089 struct regcache
*regs
,
8090 struct displaced_step_closure
*dsc
)
8092 int non_zero
= bit (insn1
, 11);
8093 unsigned int imm5
= (bit (insn1
, 9) << 6) | (bits (insn1
, 3, 7) << 1);
8094 CORE_ADDR from
= dsc
->insn_addr
;
8095 int rn
= bits (insn1
, 0, 2);
8096 int rn_val
= displaced_read_reg (regs
, dsc
, rn
);
8098 dsc
->u
.branch
.cond
= (rn_val
&& non_zero
) || (!rn_val
&& !non_zero
);
8099 /* CBNZ and CBZ do not affect the condition flags. If condition is true,
8100 set it INST_AL, so cleanup_branch will know branch is taken, otherwise,
8101 condition is false, let it be, cleanup_branch will do nothing. */
8102 if (dsc
->u
.branch
.cond
)
8104 dsc
->u
.branch
.cond
= INST_AL
;
8105 dsc
->u
.branch
.dest
= from
+ 4 + imm5
;
8108 dsc
->u
.branch
.dest
= from
+ 2;
8110 dsc
->u
.branch
.link
= 0;
8111 dsc
->u
.branch
.exchange
= 0;
8113 if (debug_displaced
)
8114 fprintf_unfiltered (gdb_stdlog
, "displaced: copying %s [r%d = 0x%x]"
8115 " insn %.4x to %.8lx\n", non_zero
? "cbnz" : "cbz",
8116 rn
, rn_val
, insn1
, dsc
->u
.branch
.dest
);
8118 dsc
->modinsn
[0] = THUMB_NOP
;
8120 dsc
->cleanup
= &cleanup_branch
;
8124 /* Copy Table Branch Byte/Halfword */
8126 thumb2_copy_table_branch (struct gdbarch
*gdbarch
, uint16_t insn1
,
8127 uint16_t insn2
, struct regcache
*regs
,
8128 struct displaced_step_closure
*dsc
)
8130 ULONGEST rn_val
, rm_val
;
8131 int is_tbh
= bit (insn2
, 4);
8132 CORE_ADDR halfwords
= 0;
8133 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8135 rn_val
= displaced_read_reg (regs
, dsc
, bits (insn1
, 0, 3));
8136 rm_val
= displaced_read_reg (regs
, dsc
, bits (insn2
, 0, 3));
8142 target_read_memory (rn_val
+ 2 * rm_val
, buf
, 2);
8143 halfwords
= extract_unsigned_integer (buf
, 2, byte_order
);
8149 target_read_memory (rn_val
+ rm_val
, buf
, 1);
8150 halfwords
= extract_unsigned_integer (buf
, 1, byte_order
);
8153 if (debug_displaced
)
8154 fprintf_unfiltered (gdb_stdlog
, "displaced: %s base 0x%x offset 0x%x"
8155 " offset 0x%x\n", is_tbh
? "tbh" : "tbb",
8156 (unsigned int) rn_val
, (unsigned int) rm_val
,
8157 (unsigned int) halfwords
);
8159 dsc
->u
.branch
.cond
= INST_AL
;
8160 dsc
->u
.branch
.link
= 0;
8161 dsc
->u
.branch
.exchange
= 0;
8162 dsc
->u
.branch
.dest
= dsc
->insn_addr
+ 4 + 2 * halfwords
;
8164 dsc
->cleanup
= &cleanup_branch
;
8170 cleanup_pop_pc_16bit_all (struct gdbarch
*gdbarch
, struct regcache
*regs
,
8171 struct displaced_step_closure
*dsc
)
8174 int val
= displaced_read_reg (regs
, dsc
, 7);
8175 displaced_write_reg (regs
, dsc
, ARM_PC_REGNUM
, val
, BX_WRITE_PC
);
8178 val
= displaced_read_reg (regs
, dsc
, 8);
8179 displaced_write_reg (regs
, dsc
, 7, val
, CANNOT_WRITE_PC
);
8182 displaced_write_reg (regs
, dsc
, 8, dsc
->tmp
[0], CANNOT_WRITE_PC
);
8187 thumb_copy_pop_pc_16bit (struct gdbarch
*gdbarch
, unsigned short insn1
,
8188 struct regcache
*regs
,
8189 struct displaced_step_closure
*dsc
)
8191 dsc
->u
.block
.regmask
= insn1
& 0x00ff;
8193 /* Rewrite instruction: POP {rX, rY, ...,rZ, PC}
8196 (1) register list is full, that is, r0-r7 are used.
8197 Prepare: tmp[0] <- r8
8199 POP {r0, r1, ...., r6, r7}; remove PC from reglist
8200 MOV r8, r7; Move value of r7 to r8;
8201 POP {r7}; Store PC value into r7.
8203 Cleanup: PC <- r7, r7 <- r8, r8 <-tmp[0]
8205 (2) register list is not full, supposing there are N registers in
8206 register list (except PC, 0 <= N <= 7).
8207 Prepare: for each i, 0 - N, tmp[i] <- ri.
8209 POP {r0, r1, ...., rN};
8211 Cleanup: Set registers in original reglist from r0 - rN. Restore r0 - rN
8212 from tmp[] properly.
8214 if (debug_displaced
)
8215 fprintf_unfiltered (gdb_stdlog
,
8216 "displaced: copying thumb pop {%.8x, pc} insn %.4x\n",
8217 dsc
->u
.block
.regmask
, insn1
);
8219 if (dsc
->u
.block
.regmask
== 0xff)
8221 dsc
->tmp
[0] = displaced_read_reg (regs
, dsc
, 8);
8223 dsc
->modinsn
[0] = (insn1
& 0xfeff); /* POP {r0,r1,...,r6, r7} */
8224 dsc
->modinsn
[1] = 0x46b8; /* MOV r8, r7 */
8225 dsc
->modinsn
[2] = 0xbc80; /* POP {r7} */
8228 dsc
->cleanup
= &cleanup_pop_pc_16bit_all
;
8232 unsigned int num_in_list
= bitcount (dsc
->u
.block
.regmask
);
8233 unsigned int new_regmask
, bit
= 1;
8234 unsigned int to
= 0, from
= 0, i
, new_rn
;
8236 for (i
= 0; i
< num_in_list
+ 1; i
++)
8237 dsc
->tmp
[i
] = displaced_read_reg (regs
, dsc
, i
);
8239 new_regmask
= (1 << (num_in_list
+ 1)) - 1;
8241 if (debug_displaced
)
8242 fprintf_unfiltered (gdb_stdlog
, _("displaced: POP "
8243 "{..., pc}: original reg list %.4x,"
8244 " modified list %.4x\n"),
8245 (int) dsc
->u
.block
.regmask
, new_regmask
);
8247 dsc
->u
.block
.regmask
|= 0x8000;
8248 dsc
->u
.block
.writeback
= 0;
8249 dsc
->u
.block
.cond
= INST_AL
;
8251 dsc
->modinsn
[0] = (insn1
& ~0x1ff) | (new_regmask
& 0xff);
8253 dsc
->cleanup
= &cleanup_block_load_pc
;
8260 thumb_process_displaced_16bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
8261 struct regcache
*regs
,
8262 struct displaced_step_closure
*dsc
)
8264 unsigned short op_bit_12_15
= bits (insn1
, 12, 15);
8265 unsigned short op_bit_10_11
= bits (insn1
, 10, 11);
8268 /* 16-bit thumb instructions. */
8269 switch (op_bit_12_15
)
8271 /* Shift (imme), add, subtract, move and compare. */
8272 case 0: case 1: case 2: case 3:
8273 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
8274 "shift/add/sub/mov/cmp",
8278 switch (op_bit_10_11
)
8280 case 0: /* Data-processing */
8281 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
,
8285 case 1: /* Special data instructions and branch and exchange. */
8287 unsigned short op
= bits (insn1
, 7, 9);
8288 if (op
== 6 || op
== 7) /* BX or BLX */
8289 err
= thumb_copy_bx_blx_reg (gdbarch
, insn1
, regs
, dsc
);
8290 else if (bits (insn1
, 6, 7) != 0) /* ADD/MOV/CMP high registers. */
8291 err
= thumb_copy_alu_reg (gdbarch
, insn1
, regs
, dsc
);
8293 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "special data",
8297 default: /* LDR (literal) */
8298 err
= thumb_copy_16bit_ldr_literal (gdbarch
, insn1
, regs
, dsc
);
8301 case 5: case 6: case 7: case 8: case 9: /* Load/Store single data item */
8302 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldr/str", dsc
);
8305 if (op_bit_10_11
< 2) /* Generate PC-relative address */
8306 err
= thumb_decode_pc_relative_16bit (gdbarch
, insn1
, regs
, dsc
);
8307 else /* Generate SP-relative address */
8308 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "sp-relative", dsc
);
8310 case 11: /* Misc 16-bit instructions */
8312 switch (bits (insn1
, 8, 11))
8314 case 1: case 3: case 9: case 11: /* CBNZ, CBZ */
8315 err
= thumb_copy_cbnz_cbz (gdbarch
, insn1
, regs
, dsc
);
8317 case 12: case 13: /* POP */
8318 if (bit (insn1
, 8)) /* PC is in register list. */
8319 err
= thumb_copy_pop_pc_16bit (gdbarch
, insn1
, regs
, dsc
);
8321 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "pop", dsc
);
8323 case 15: /* If-Then, and hints */
8324 if (bits (insn1
, 0, 3))
8325 /* If-Then makes up to four following instructions conditional.
8326 IT instruction itself is not conditional, so handle it as a
8327 common unmodified instruction. */
8328 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "If-Then",
8331 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "hints", dsc
);
8334 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "misc", dsc
);
8339 if (op_bit_10_11
< 2) /* Store multiple registers */
8340 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "stm", dsc
);
8341 else /* Load multiple registers */
8342 err
= thumb_copy_unmodified_16bit (gdbarch
, insn1
, "ldm", dsc
);
8344 case 13: /* Conditional branch and supervisor call */
8345 if (bits (insn1
, 9, 11) != 7) /* conditional branch */
8346 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
8348 err
= thumb_copy_svc (gdbarch
, insn1
, regs
, dsc
);
8350 case 14: /* Unconditional branch */
8351 err
= thumb_copy_b (gdbarch
, insn1
, dsc
);
8358 internal_error (__FILE__
, __LINE__
,
8359 _("thumb_process_displaced_16bit_insn: Instruction decode error"));
8363 decode_thumb_32bit_ld_mem_hints (struct gdbarch
*gdbarch
,
8364 uint16_t insn1
, uint16_t insn2
,
8365 struct regcache
*regs
,
8366 struct displaced_step_closure
*dsc
)
8368 int rt
= bits (insn2
, 12, 15);
8369 int rn
= bits (insn1
, 0, 3);
8370 int op1
= bits (insn1
, 7, 8);
8373 switch (bits (insn1
, 5, 6))
8375 case 0: /* Load byte and memory hints */
8376 if (rt
== 0xf) /* PLD/PLI */
8379 /* PLD literal or Encoding T3 of PLI(immediate, literal). */
8380 return thumb2_copy_preload (gdbarch
, insn1
, insn2
, regs
, dsc
);
8382 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8387 if (rn
== 0xf) /* LDRB/LDRSB (literal) */
8388 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
8391 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8392 "ldrb{reg, immediate}/ldrbt",
8397 case 1: /* Load halfword and memory hints. */
8398 if (rt
== 0xf) /* PLD{W} and Unalloc memory hint. */
8399 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8400 "pld/unalloc memhint", dsc
);
8404 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
,
8407 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8411 case 2: /* Load word */
8413 int insn2_bit_8_11
= bits (insn2
, 8, 11);
8416 return thumb2_copy_load_literal (gdbarch
, insn1
, insn2
, regs
, dsc
, 4);
8417 else if (op1
== 0x1) /* Encoding T3 */
8418 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
, dsc
,
8420 else /* op1 == 0x0 */
8422 if (insn2_bit_8_11
== 0xc || (insn2_bit_8_11
& 0x9) == 0x9)
8423 /* LDR (immediate) */
8424 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
8425 dsc
, bit (insn2
, 8), 1);
8426 else if (insn2_bit_8_11
== 0xe) /* LDRT */
8427 return thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8430 /* LDR (register) */
8431 return thumb2_copy_load_reg_imm (gdbarch
, insn1
, insn2
, regs
,
8437 return thumb_32bit_copy_undef (gdbarch
, insn1
, insn2
, dsc
);
8444 thumb_process_displaced_32bit_insn (struct gdbarch
*gdbarch
, uint16_t insn1
,
8445 uint16_t insn2
, struct regcache
*regs
,
8446 struct displaced_step_closure
*dsc
)
8449 unsigned short op
= bit (insn2
, 15);
8450 unsigned int op1
= bits (insn1
, 11, 12);
8456 switch (bits (insn1
, 9, 10))
8461 /* Load/store {dual, execlusive}, table branch. */
8462 if (bits (insn1
, 7, 8) == 1 && bits (insn1
, 4, 5) == 1
8463 && bits (insn2
, 5, 7) == 0)
8464 err
= thumb2_copy_table_branch (gdbarch
, insn1
, insn2
, regs
,
8467 /* PC is not allowed to use in load/store {dual, exclusive}
8469 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8470 "load/store dual/ex", dsc
);
8472 else /* load/store multiple */
8474 switch (bits (insn1
, 7, 8))
8476 case 0: case 3: /* SRS, RFE */
8477 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8480 case 1: case 2: /* LDM/STM/PUSH/POP */
8481 err
= thumb2_copy_block_xfer (gdbarch
, insn1
, insn2
, regs
, dsc
);
8488 /* Data-processing (shift register). */
8489 err
= thumb2_decode_dp_shift_reg (gdbarch
, insn1
, insn2
, regs
,
8492 default: /* Coprocessor instructions. */
8493 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
8498 case 2: /* op1 = 2 */
8499 if (op
) /* Branch and misc control. */
8501 if (bit (insn2
, 14) /* BLX/BL */
8502 || bit (insn2
, 12) /* Unconditional branch */
8503 || (bits (insn1
, 7, 9) != 0x7)) /* Conditional branch */
8504 err
= thumb2_copy_b_bl_blx (gdbarch
, insn1
, insn2
, regs
, dsc
);
8506 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8511 if (bit (insn1
, 9)) /* Data processing (plain binary imm). */
8513 int op
= bits (insn1
, 4, 8);
8514 int rn
= bits (insn1
, 0, 3);
8515 if ((op
== 0 || op
== 0xa) && rn
== 0xf)
8516 err
= thumb_copy_pc_relative_32bit (gdbarch
, insn1
, insn2
,
8519 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8522 else /* Data processing (modified immeidate) */
8523 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8527 case 3: /* op1 = 3 */
8528 switch (bits (insn1
, 9, 10))
8532 err
= decode_thumb_32bit_ld_mem_hints (gdbarch
, insn1
, insn2
,
8534 else /* NEON Load/Store and Store single data item */
8535 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8536 "neon elt/struct load/store",
8539 case 1: /* op1 = 3, bits (9, 10) == 1 */
8540 switch (bits (insn1
, 7, 8))
8542 case 0: case 1: /* Data processing (register) */
8543 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8546 case 2: /* Multiply and absolute difference */
8547 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8548 "mul/mua/diff", dsc
);
8550 case 3: /* Long multiply and divide */
8551 err
= thumb_copy_unmodified_32bit (gdbarch
, insn1
, insn2
,
8556 default: /* Coprocessor instructions */
8557 err
= thumb2_decode_svc_copro (gdbarch
, insn1
, insn2
, regs
, dsc
);
8566 internal_error (__FILE__
, __LINE__
,
8567 _("thumb_process_displaced_32bit_insn: Instruction decode error"));
8572 thumb_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8573 CORE_ADDR to
, struct regcache
*regs
,
8574 struct displaced_step_closure
*dsc
)
8576 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8578 = read_memory_unsigned_integer (from
, 2, byte_order_for_code
);
8580 if (debug_displaced
)
8581 fprintf_unfiltered (gdb_stdlog
, "displaced: process thumb insn %.4x "
8582 "at %.8lx\n", insn1
, (unsigned long) from
);
8585 dsc
->insn_size
= thumb_insn_size (insn1
);
8586 if (thumb_insn_size (insn1
) == 4)
8589 = read_memory_unsigned_integer (from
+ 2, 2, byte_order_for_code
);
8590 thumb_process_displaced_32bit_insn (gdbarch
, insn1
, insn2
, regs
, dsc
);
8593 thumb_process_displaced_16bit_insn (gdbarch
, insn1
, regs
, dsc
);
8597 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8598 CORE_ADDR to
, struct regcache
*regs
,
8599 struct displaced_step_closure
*dsc
)
8602 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8605 /* Most displaced instructions use a 1-instruction scratch space, so set this
8606 here and override below if/when necessary. */
8608 dsc
->insn_addr
= from
;
8609 dsc
->scratch_base
= to
;
8610 dsc
->cleanup
= NULL
;
8611 dsc
->wrote_to_pc
= 0;
8613 if (!displaced_in_arm_mode (regs
))
8614 return thumb_process_displaced_insn (gdbarch
, from
, to
, regs
, dsc
);
8618 insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
8619 if (debug_displaced
)
8620 fprintf_unfiltered (gdb_stdlog
, "displaced: stepping insn %.8lx "
8621 "at %.8lx\n", (unsigned long) insn
,
8622 (unsigned long) from
);
8624 if ((insn
& 0xf0000000) == 0xf0000000)
8625 err
= arm_decode_unconditional (gdbarch
, insn
, regs
, dsc
);
8626 else switch (((insn
& 0x10) >> 4) | ((insn
& 0xe000000) >> 24))
8628 case 0x0: case 0x1: case 0x2: case 0x3:
8629 err
= arm_decode_dp_misc (gdbarch
, insn
, regs
, dsc
);
8632 case 0x4: case 0x5: case 0x6:
8633 err
= arm_decode_ld_st_word_ubyte (gdbarch
, insn
, regs
, dsc
);
8637 err
= arm_decode_media (gdbarch
, insn
, dsc
);
8640 case 0x8: case 0x9: case 0xa: case 0xb:
8641 err
= arm_decode_b_bl_ldmstm (gdbarch
, insn
, regs
, dsc
);
8644 case 0xc: case 0xd: case 0xe: case 0xf:
8645 err
= arm_decode_svc_copro (gdbarch
, insn
, to
, regs
, dsc
);
8650 internal_error (__FILE__
, __LINE__
,
8651 _("arm_process_displaced_insn: Instruction decode error"));
8654 /* Actually set up the scratch space for a displaced instruction. */
8657 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
8658 CORE_ADDR to
, struct displaced_step_closure
*dsc
)
8660 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8661 unsigned int i
, len
, offset
;
8662 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8663 int size
= dsc
->is_thumb
? 2 : 4;
8664 const gdb_byte
*bkp_insn
;
8667 /* Poke modified instruction(s). */
8668 for (i
= 0; i
< dsc
->numinsns
; i
++)
8670 if (debug_displaced
)
8672 fprintf_unfiltered (gdb_stdlog
, "displaced: writing insn ");
8674 fprintf_unfiltered (gdb_stdlog
, "%.8lx",
8677 fprintf_unfiltered (gdb_stdlog
, "%.4x",
8678 (unsigned short)dsc
->modinsn
[i
]);
8680 fprintf_unfiltered (gdb_stdlog
, " at %.8lx\n",
8681 (unsigned long) to
+ offset
);
8684 write_memory_unsigned_integer (to
+ offset
, size
,
8685 byte_order_for_code
,
8690 /* Choose the correct breakpoint instruction. */
8693 bkp_insn
= tdep
->thumb_breakpoint
;
8694 len
= tdep
->thumb_breakpoint_size
;
8698 bkp_insn
= tdep
->arm_breakpoint
;
8699 len
= tdep
->arm_breakpoint_size
;
8702 /* Put breakpoint afterwards. */
8703 write_memory (to
+ offset
, bkp_insn
, len
);
8705 if (debug_displaced
)
8706 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
8707 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
8710 /* Entry point for copying an instruction into scratch space for displaced
8713 struct displaced_step_closure
*
8714 arm_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
8715 CORE_ADDR from
, CORE_ADDR to
,
8716 struct regcache
*regs
)
8718 struct displaced_step_closure
*dsc
= XNEW (struct displaced_step_closure
);
8720 arm_process_displaced_insn (gdbarch
, from
, to
, regs
, dsc
);
8721 arm_displaced_init_closure (gdbarch
, from
, to
, dsc
);
8726 /* Entry point for cleaning things up after a displaced instruction has been
8730 arm_displaced_step_fixup (struct gdbarch
*gdbarch
,
8731 struct displaced_step_closure
*dsc
,
8732 CORE_ADDR from
, CORE_ADDR to
,
8733 struct regcache
*regs
)
8736 dsc
->cleanup (gdbarch
, regs
, dsc
);
8738 if (!dsc
->wrote_to_pc
)
8739 regcache_cooked_write_unsigned (regs
, ARM_PC_REGNUM
,
8740 dsc
->insn_addr
+ dsc
->insn_size
);
8744 #include "bfd-in2.h"
8745 #include "libcoff.h"
8748 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
8750 struct gdbarch
*gdbarch
= (struct gdbarch
*) info
->application_data
;
8752 if (arm_pc_is_thumb (gdbarch
, memaddr
))
8754 static asymbol
*asym
;
8755 static combined_entry_type ce
;
8756 static struct coff_symbol_struct csym
;
8757 static struct bfd fake_bfd
;
8758 static bfd_target fake_target
;
8760 if (csym
.native
== NULL
)
8762 /* Create a fake symbol vector containing a Thumb symbol.
8763 This is solely so that the code in print_insn_little_arm()
8764 and print_insn_big_arm() in opcodes/arm-dis.c will detect
8765 the presence of a Thumb symbol and switch to decoding
8766 Thumb instructions. */
8768 fake_target
.flavour
= bfd_target_coff_flavour
;
8769 fake_bfd
.xvec
= &fake_target
;
8770 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
8772 csym
.symbol
.the_bfd
= &fake_bfd
;
8773 csym
.symbol
.name
= "fake";
8774 asym
= (asymbol
*) & csym
;
8777 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
8778 info
->symbols
= &asym
;
8781 info
->symbols
= NULL
;
8783 if (info
->endian
== BFD_ENDIAN_BIG
)
8784 return print_insn_big_arm (memaddr
, info
);
8786 return print_insn_little_arm (memaddr
, info
);
8789 /* The following define instruction sequences that will cause ARM
8790 cpu's to take an undefined instruction trap. These are used to
8791 signal a breakpoint to GDB.
8793 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
8794 modes. A different instruction is required for each mode. The ARM
8795 cpu's can also be big or little endian. Thus four different
8796 instructions are needed to support all cases.
8798 Note: ARMv4 defines several new instructions that will take the
8799 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
8800 not in fact add the new instructions. The new undefined
8801 instructions in ARMv4 are all instructions that had no defined
8802 behaviour in earlier chips. There is no guarantee that they will
8803 raise an exception, but may be treated as NOP's. In practice, it
8804 may only safe to rely on instructions matching:
8806 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
8807 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
8808 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
8810 Even this may only true if the condition predicate is true. The
8811 following use a condition predicate of ALWAYS so it is always TRUE.
8813 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
8814 and NetBSD all use a software interrupt rather than an undefined
8815 instruction to force a trap. This can be handled by by the
8816 abi-specific code during establishment of the gdbarch vector. */
8818 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
8819 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
8820 #define THUMB_LE_BREAKPOINT {0xbe,0xbe}
8821 #define THUMB_BE_BREAKPOINT {0xbe,0xbe}
8823 static const gdb_byte arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
8824 static const gdb_byte arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
8825 static const gdb_byte arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
8826 static const gdb_byte arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
8828 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
8829 the program counter value to determine whether a 16-bit or 32-bit
8830 breakpoint should be used. It returns a pointer to a string of
8831 bytes that encode a breakpoint instruction, stores the length of
8832 the string to *lenptr, and adjusts the program counter (if
8833 necessary) to point to the actual memory location where the
8834 breakpoint should be inserted. */
8836 static const unsigned char *
8837 arm_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
8839 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8840 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
8842 if (arm_pc_is_thumb (gdbarch
, *pcptr
))
8844 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
8846 /* If we have a separate 32-bit breakpoint instruction for Thumb-2,
8847 check whether we are replacing a 32-bit instruction. */
8848 if (tdep
->thumb2_breakpoint
!= NULL
)
8851 if (target_read_memory (*pcptr
, buf
, 2) == 0)
8853 unsigned short inst1
;
8854 inst1
= extract_unsigned_integer (buf
, 2, byte_order_for_code
);
8855 if (thumb_insn_size (inst1
) == 4)
8857 *lenptr
= tdep
->thumb2_breakpoint_size
;
8858 return tdep
->thumb2_breakpoint
;
8863 *lenptr
= tdep
->thumb_breakpoint_size
;
8864 return tdep
->thumb_breakpoint
;
8868 *lenptr
= tdep
->arm_breakpoint_size
;
8869 return tdep
->arm_breakpoint
;
8874 arm_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
8877 arm_breakpoint_from_pc (gdbarch
, pcptr
, kindptr
);
8879 if (arm_pc_is_thumb (gdbarch
, *pcptr
) && *kindptr
== 4)
8880 /* The documented magic value for a 32-bit Thumb-2 breakpoint, so
8881 that this is not confused with a 32-bit ARM breakpoint. */
8885 /* Extract from an array REGBUF containing the (raw) register state a
8886 function return value of type TYPE, and copy that, in virtual
8887 format, into VALBUF. */
8890 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
8893 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
8894 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8896 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
8898 switch (gdbarch_tdep (gdbarch
)->fp_model
)
8902 /* The value is in register F0 in internal format. We need to
8903 extract the raw value and then convert it to the desired
8905 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
8907 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
8908 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
8909 valbuf
, gdbarch_byte_order (gdbarch
));
8913 case ARM_FLOAT_SOFT_FPA
:
8914 case ARM_FLOAT_SOFT_VFP
:
8915 /* ARM_FLOAT_VFP can arise if this is a variadic function so
8916 not using the VFP ABI code. */
8918 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
8919 if (TYPE_LENGTH (type
) > 4)
8920 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
8921 valbuf
+ INT_REGISTER_SIZE
);
8925 internal_error (__FILE__
, __LINE__
,
8926 _("arm_extract_return_value: "
8927 "Floating point model not supported"));
8931 else if (TYPE_CODE (type
) == TYPE_CODE_INT
8932 || TYPE_CODE (type
) == TYPE_CODE_CHAR
8933 || TYPE_CODE (type
) == TYPE_CODE_BOOL
8934 || TYPE_CODE (type
) == TYPE_CODE_PTR
8935 || TYPE_CODE (type
) == TYPE_CODE_REF
8936 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
8938 /* If the type is a plain integer, then the access is
8939 straight-forward. Otherwise we have to play around a bit
8941 int len
= TYPE_LENGTH (type
);
8942 int regno
= ARM_A1_REGNUM
;
8947 /* By using store_unsigned_integer we avoid having to do
8948 anything special for small big-endian values. */
8949 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
8950 store_unsigned_integer (valbuf
,
8951 (len
> INT_REGISTER_SIZE
8952 ? INT_REGISTER_SIZE
: len
),
8954 len
-= INT_REGISTER_SIZE
;
8955 valbuf
+= INT_REGISTER_SIZE
;
8960 /* For a structure or union the behaviour is as if the value had
8961 been stored to word-aligned memory and then loaded into
8962 registers with 32-bit load instruction(s). */
8963 int len
= TYPE_LENGTH (type
);
8964 int regno
= ARM_A1_REGNUM
;
8965 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
8969 regcache_cooked_read (regs
, regno
++, tmpbuf
);
8970 memcpy (valbuf
, tmpbuf
,
8971 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
8972 len
-= INT_REGISTER_SIZE
;
8973 valbuf
+= INT_REGISTER_SIZE
;
8979 /* Will a function return an aggregate type in memory or in a
8980 register? Return 0 if an aggregate type can be returned in a
8981 register, 1 if it must be returned in memory. */
8984 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
8986 enum type_code code
;
8988 type
= check_typedef (type
);
8990 /* Simple, non-aggregate types (ie not including vectors and
8991 complex) are always returned in a register (or registers). */
8992 code
= TYPE_CODE (type
);
8993 if (TYPE_CODE_STRUCT
!= code
&& TYPE_CODE_UNION
!= code
8994 && TYPE_CODE_ARRAY
!= code
&& TYPE_CODE_COMPLEX
!= code
)
8997 if (TYPE_CODE_ARRAY
== code
&& TYPE_VECTOR (type
))
8999 /* Vector values should be returned using ARM registers if they
9000 are not over 16 bytes. */
9001 return (TYPE_LENGTH (type
) > 16);
9004 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
9006 /* The AAPCS says all aggregates not larger than a word are returned
9008 if (TYPE_LENGTH (type
) <= INT_REGISTER_SIZE
)
9017 /* All aggregate types that won't fit in a register must be returned
9019 if (TYPE_LENGTH (type
) > INT_REGISTER_SIZE
)
9022 /* In the ARM ABI, "integer" like aggregate types are returned in
9023 registers. For an aggregate type to be integer like, its size
9024 must be less than or equal to INT_REGISTER_SIZE and the
9025 offset of each addressable subfield must be zero. Note that bit
9026 fields are not addressable, and all addressable subfields of
9027 unions always start at offset zero.
9029 This function is based on the behaviour of GCC 2.95.1.
9030 See: gcc/arm.c: arm_return_in_memory() for details.
9032 Note: All versions of GCC before GCC 2.95.2 do not set up the
9033 parameters correctly for a function returning the following
9034 structure: struct { float f;}; This should be returned in memory,
9035 not a register. Richard Earnshaw sent me a patch, but I do not
9036 know of any way to detect if a function like the above has been
9037 compiled with the correct calling convention. */
9039 /* Assume all other aggregate types can be returned in a register.
9040 Run a check for structures, unions and arrays. */
9043 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
9046 /* Need to check if this struct/union is "integer" like. For
9047 this to be true, its size must be less than or equal to
9048 INT_REGISTER_SIZE and the offset of each addressable
9049 subfield must be zero. Note that bit fields are not
9050 addressable, and unions always start at offset zero. If any
9051 of the subfields is a floating point type, the struct/union
9052 cannot be an integer type. */
9054 /* For each field in the object, check:
9055 1) Is it FP? --> yes, nRc = 1;
9056 2) Is it addressable (bitpos != 0) and
9057 not packed (bitsize == 0)?
9061 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
9063 enum type_code field_type_code
;
9066 = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
,
9069 /* Is it a floating point type field? */
9070 if (field_type_code
== TYPE_CODE_FLT
)
9076 /* If bitpos != 0, then we have to care about it. */
9077 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
9079 /* Bitfields are not addressable. If the field bitsize is
9080 zero, then the field is not packed. Hence it cannot be
9081 a bitfield or any other packed type. */
9082 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
9095 /* Write into appropriate registers a function return value of type
9096 TYPE, given in virtual format. */
9099 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
9100 const gdb_byte
*valbuf
)
9102 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
9103 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
9105 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
9107 gdb_byte buf
[MAX_REGISTER_SIZE
];
9109 switch (gdbarch_tdep (gdbarch
)->fp_model
)
9113 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
,
9114 gdbarch_byte_order (gdbarch
));
9115 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
9118 case ARM_FLOAT_SOFT_FPA
:
9119 case ARM_FLOAT_SOFT_VFP
:
9120 /* ARM_FLOAT_VFP can arise if this is a variadic function so
9121 not using the VFP ABI code. */
9123 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
9124 if (TYPE_LENGTH (type
) > 4)
9125 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
9126 valbuf
+ INT_REGISTER_SIZE
);
9130 internal_error (__FILE__
, __LINE__
,
9131 _("arm_store_return_value: Floating "
9132 "point model not supported"));
9136 else if (TYPE_CODE (type
) == TYPE_CODE_INT
9137 || TYPE_CODE (type
) == TYPE_CODE_CHAR
9138 || TYPE_CODE (type
) == TYPE_CODE_BOOL
9139 || TYPE_CODE (type
) == TYPE_CODE_PTR
9140 || TYPE_CODE (type
) == TYPE_CODE_REF
9141 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
9143 if (TYPE_LENGTH (type
) <= 4)
9145 /* Values of one word or less are zero/sign-extended and
9147 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
9148 LONGEST val
= unpack_long (type
, valbuf
);
9150 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, byte_order
, val
);
9151 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
9155 /* Integral values greater than one word are stored in consecutive
9156 registers starting with r0. This will always be a multiple of
9157 the regiser size. */
9158 int len
= TYPE_LENGTH (type
);
9159 int regno
= ARM_A1_REGNUM
;
9163 regcache_cooked_write (regs
, regno
++, valbuf
);
9164 len
-= INT_REGISTER_SIZE
;
9165 valbuf
+= INT_REGISTER_SIZE
;
9171 /* For a structure or union the behaviour is as if the value had
9172 been stored to word-aligned memory and then loaded into
9173 registers with 32-bit load instruction(s). */
9174 int len
= TYPE_LENGTH (type
);
9175 int regno
= ARM_A1_REGNUM
;
9176 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
9180 memcpy (tmpbuf
, valbuf
,
9181 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
9182 regcache_cooked_write (regs
, regno
++, tmpbuf
);
9183 len
-= INT_REGISTER_SIZE
;
9184 valbuf
+= INT_REGISTER_SIZE
;
9190 /* Handle function return values. */
9192 static enum return_value_convention
9193 arm_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
9194 struct type
*valtype
, struct regcache
*regcache
,
9195 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
9197 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9198 struct type
*func_type
= function
? value_type (function
) : NULL
;
9199 enum arm_vfp_cprc_base_type vfp_base_type
;
9202 if (arm_vfp_abi_for_function (gdbarch
, func_type
)
9203 && arm_vfp_call_candidate (valtype
, &vfp_base_type
, &vfp_base_count
))
9205 int reg_char
= arm_vfp_cprc_reg_char (vfp_base_type
);
9206 int unit_length
= arm_vfp_cprc_unit_length (vfp_base_type
);
9208 for (i
= 0; i
< vfp_base_count
; i
++)
9210 if (reg_char
== 'q')
9213 arm_neon_quad_write (gdbarch
, regcache
, i
,
9214 writebuf
+ i
* unit_length
);
9217 arm_neon_quad_read (gdbarch
, regcache
, i
,
9218 readbuf
+ i
* unit_length
);
9225 xsnprintf (name_buf
, sizeof (name_buf
), "%c%d", reg_char
, i
);
9226 regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9229 regcache_cooked_write (regcache
, regnum
,
9230 writebuf
+ i
* unit_length
);
9232 regcache_cooked_read (regcache
, regnum
,
9233 readbuf
+ i
* unit_length
);
9236 return RETURN_VALUE_REGISTER_CONVENTION
;
9239 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
9240 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
9241 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
9243 if (tdep
->struct_return
== pcc_struct_return
9244 || arm_return_in_memory (gdbarch
, valtype
))
9245 return RETURN_VALUE_STRUCT_CONVENTION
;
9247 else if (TYPE_CODE (valtype
) == TYPE_CODE_COMPLEX
)
9249 if (arm_return_in_memory (gdbarch
, valtype
))
9250 return RETURN_VALUE_STRUCT_CONVENTION
;
9254 arm_store_return_value (valtype
, regcache
, writebuf
);
9257 arm_extract_return_value (valtype
, regcache
, readbuf
);
9259 return RETURN_VALUE_REGISTER_CONVENTION
;
9264 arm_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
9266 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
9267 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
9268 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
9270 gdb_byte buf
[INT_REGISTER_SIZE
];
9272 jb_addr
= get_frame_register_unsigned (frame
, ARM_A1_REGNUM
);
9274 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
9278 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
, byte_order
);
9282 /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
9283 return the target PC. Otherwise return 0. */
9286 arm_skip_stub (struct frame_info
*frame
, CORE_ADDR pc
)
9290 CORE_ADDR start_addr
;
9292 /* Find the starting address and name of the function containing the PC. */
9293 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
9295 /* Trampoline 'bx reg' doesn't belong to any functions. Do the
9297 start_addr
= arm_skip_bx_reg (frame
, pc
);
9298 if (start_addr
!= 0)
9304 /* If PC is in a Thumb call or return stub, return the address of the
9305 target PC, which is in a register. The thunk functions are called
9306 _call_via_xx, where x is the register name. The possible names
9307 are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar
9308 functions, named __ARM_call_via_r[0-7]. */
9309 if (startswith (name
, "_call_via_")
9310 || startswith (name
, "__ARM_call_via_"))
9312 /* Use the name suffix to determine which register contains the
9314 static char *table
[15] =
9315 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
9316 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
9319 int offset
= strlen (name
) - 2;
9321 for (regno
= 0; regno
<= 14; regno
++)
9322 if (strcmp (&name
[offset
], table
[regno
]) == 0)
9323 return get_frame_register_unsigned (frame
, regno
);
9326 /* GNU ld generates __foo_from_arm or __foo_from_thumb for
9327 non-interworking calls to foo. We could decode the stubs
9328 to find the target but it's easier to use the symbol table. */
9329 namelen
= strlen (name
);
9330 if (name
[0] == '_' && name
[1] == '_'
9331 && ((namelen
> 2 + strlen ("_from_thumb")
9332 && startswith (name
+ namelen
- strlen ("_from_thumb"), "_from_thumb"))
9333 || (namelen
> 2 + strlen ("_from_arm")
9334 && startswith (name
+ namelen
- strlen ("_from_arm"), "_from_arm"))))
9337 int target_len
= namelen
- 2;
9338 struct bound_minimal_symbol minsym
;
9339 struct objfile
*objfile
;
9340 struct obj_section
*sec
;
9342 if (name
[namelen
- 1] == 'b')
9343 target_len
-= strlen ("_from_thumb");
9345 target_len
-= strlen ("_from_arm");
9347 target_name
= (char *) alloca (target_len
+ 1);
9348 memcpy (target_name
, name
+ 2, target_len
);
9349 target_name
[target_len
] = '\0';
9351 sec
= find_pc_section (pc
);
9352 objfile
= (sec
== NULL
) ? NULL
: sec
->objfile
;
9353 minsym
= lookup_minimal_symbol (target_name
, NULL
, objfile
);
9354 if (minsym
.minsym
!= NULL
)
9355 return BMSYMBOL_VALUE_ADDRESS (minsym
);
9360 return 0; /* not a stub */
9364 set_arm_command (char *args
, int from_tty
)
9366 printf_unfiltered (_("\
9367 \"set arm\" must be followed by an apporpriate subcommand.\n"));
9368 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
9372 show_arm_command (char *args
, int from_tty
)
9374 cmd_show_list (showarmcmdlist
, from_tty
, "");
9378 arm_update_current_architecture (void)
9380 struct gdbarch_info info
;
9382 /* If the current architecture is not ARM, we have nothing to do. */
9383 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_arm
)
9386 /* Update the architecture. */
9387 gdbarch_info_init (&info
);
9389 if (!gdbarch_update_p (info
))
9390 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
9394 set_fp_model_sfunc (char *args
, int from_tty
,
9395 struct cmd_list_element
*c
)
9399 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
9400 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
9402 arm_fp_model
= (enum arm_float_model
) fp_model
;
9406 if (fp_model
== ARM_FLOAT_LAST
)
9407 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
9410 arm_update_current_architecture ();
9414 show_fp_model (struct ui_file
*file
, int from_tty
,
9415 struct cmd_list_element
*c
, const char *value
)
9417 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
9419 if (arm_fp_model
== ARM_FLOAT_AUTO
9420 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
9421 fprintf_filtered (file
, _("\
9422 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
9423 fp_model_strings
[tdep
->fp_model
]);
9425 fprintf_filtered (file
, _("\
9426 The current ARM floating point model is \"%s\".\n"),
9427 fp_model_strings
[arm_fp_model
]);
9431 arm_set_abi (char *args
, int from_tty
,
9432 struct cmd_list_element
*c
)
9436 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
9437 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
9439 arm_abi_global
= (enum arm_abi_kind
) arm_abi
;
9443 if (arm_abi
== ARM_ABI_LAST
)
9444 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
9447 arm_update_current_architecture ();
9451 arm_show_abi (struct ui_file
*file
, int from_tty
,
9452 struct cmd_list_element
*c
, const char *value
)
9454 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
9456 if (arm_abi_global
== ARM_ABI_AUTO
9457 && gdbarch_bfd_arch_info (target_gdbarch ())->arch
== bfd_arch_arm
)
9458 fprintf_filtered (file
, _("\
9459 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
9460 arm_abi_strings
[tdep
->arm_abi
]);
9462 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
9467 arm_show_fallback_mode (struct ui_file
*file
, int from_tty
,
9468 struct cmd_list_element
*c
, const char *value
)
9470 fprintf_filtered (file
,
9471 _("The current execution mode assumed "
9472 "(when symbols are unavailable) is \"%s\".\n"),
9473 arm_fallback_mode_string
);
9477 arm_show_force_mode (struct ui_file
*file
, int from_tty
,
9478 struct cmd_list_element
*c
, const char *value
)
9480 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
9482 fprintf_filtered (file
,
9483 _("The current execution mode assumed "
9484 "(even when symbols are available) is \"%s\".\n"),
9485 arm_force_mode_string
);
9488 /* If the user changes the register disassembly style used for info
9489 register and other commands, we have to also switch the style used
9490 in opcodes for disassembly output. This function is run in the "set
9491 arm disassembly" command, and does that. */
9494 set_disassembly_style_sfunc (char *args
, int from_tty
,
9495 struct cmd_list_element
*c
)
9497 set_disassembly_style ();
9500 /* Return the ARM register name corresponding to register I. */
9502 arm_register_name (struct gdbarch
*gdbarch
, int i
)
9504 const int num_regs
= gdbarch_num_regs (gdbarch
);
9506 if (gdbarch_tdep (gdbarch
)->have_vfp_pseudos
9507 && i
>= num_regs
&& i
< num_regs
+ 32)
9509 static const char *const vfp_pseudo_names
[] = {
9510 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
9511 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
9512 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
9513 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
9516 return vfp_pseudo_names
[i
- num_regs
];
9519 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
9520 && i
>= num_regs
+ 32 && i
< num_regs
+ 32 + 16)
9522 static const char *const neon_pseudo_names
[] = {
9523 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
9524 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
9527 return neon_pseudo_names
[i
- num_regs
- 32];
9530 if (i
>= ARRAY_SIZE (arm_register_names
))
9531 /* These registers are only supported on targets which supply
9532 an XML description. */
9535 return arm_register_names
[i
];
9539 set_disassembly_style (void)
9543 /* Find the style that the user wants. */
9544 for (current
= 0; current
< num_disassembly_options
; current
++)
9545 if (disassembly_style
== valid_disassembly_styles
[current
])
9547 gdb_assert (current
< num_disassembly_options
);
9549 /* Synchronize the disassembler. */
9550 set_arm_regname_option (current
);
9553 /* Test whether the coff symbol specific value corresponds to a Thumb
9557 coff_sym_is_thumb (int val
)
9559 return (val
== C_THUMBEXT
9560 || val
== C_THUMBSTAT
9561 || val
== C_THUMBEXTFUNC
9562 || val
== C_THUMBSTATFUNC
9563 || val
== C_THUMBLABEL
);
9566 /* arm_coff_make_msymbol_special()
9567 arm_elf_make_msymbol_special()
9569 These functions test whether the COFF or ELF symbol corresponds to
9570 an address in thumb code, and set a "special" bit in a minimal
9571 symbol to indicate that it does. */
9574 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
9576 if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type
*)sym
)->internal_elf_sym
)
9577 == ST_BRANCH_TO_THUMB
)
9578 MSYMBOL_SET_SPECIAL (msym
);
9582 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
9584 if (coff_sym_is_thumb (val
))
9585 MSYMBOL_SET_SPECIAL (msym
);
9589 arm_objfile_data_free (struct objfile
*objfile
, void *arg
)
9591 struct arm_per_objfile
*data
= (struct arm_per_objfile
*) arg
;
9594 for (i
= 0; i
< objfile
->obfd
->section_count
; i
++)
9595 VEC_free (arm_mapping_symbol_s
, data
->section_maps
[i
]);
9599 arm_record_special_symbol (struct gdbarch
*gdbarch
, struct objfile
*objfile
,
9602 const char *name
= bfd_asymbol_name (sym
);
9603 struct arm_per_objfile
*data
;
9604 VEC(arm_mapping_symbol_s
) **map_p
;
9605 struct arm_mapping_symbol new_map_sym
;
9607 gdb_assert (name
[0] == '$');
9608 if (name
[1] != 'a' && name
[1] != 't' && name
[1] != 'd')
9611 data
= (struct arm_per_objfile
*) objfile_data (objfile
,
9612 arm_objfile_data_key
);
9615 data
= OBSTACK_ZALLOC (&objfile
->objfile_obstack
,
9616 struct arm_per_objfile
);
9617 set_objfile_data (objfile
, arm_objfile_data_key
, data
);
9618 data
->section_maps
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
9619 objfile
->obfd
->section_count
,
9620 VEC(arm_mapping_symbol_s
) *);
9622 map_p
= &data
->section_maps
[bfd_get_section (sym
)->index
];
9624 new_map_sym
.value
= sym
->value
;
9625 new_map_sym
.type
= name
[1];
9627 /* Assume that most mapping symbols appear in order of increasing
9628 value. If they were randomly distributed, it would be faster to
9629 always push here and then sort at first use. */
9630 if (!VEC_empty (arm_mapping_symbol_s
, *map_p
))
9632 struct arm_mapping_symbol
*prev_map_sym
;
9634 prev_map_sym
= VEC_last (arm_mapping_symbol_s
, *map_p
);
9635 if (prev_map_sym
->value
>= sym
->value
)
9638 idx
= VEC_lower_bound (arm_mapping_symbol_s
, *map_p
, &new_map_sym
,
9639 arm_compare_mapping_symbols
);
9640 VEC_safe_insert (arm_mapping_symbol_s
, *map_p
, idx
, &new_map_sym
);
9645 VEC_safe_push (arm_mapping_symbol_s
, *map_p
, &new_map_sym
);
9649 arm_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
9651 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
9652 regcache_cooked_write_unsigned (regcache
, ARM_PC_REGNUM
, pc
);
9654 /* If necessary, set the T bit. */
9657 ULONGEST val
, t_bit
;
9658 regcache_cooked_read_unsigned (regcache
, ARM_PS_REGNUM
, &val
);
9659 t_bit
= arm_psr_thumb_bit (gdbarch
);
9660 if (arm_pc_is_thumb (gdbarch
, pc
))
9661 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
9664 regcache_cooked_write_unsigned (regcache
, ARM_PS_REGNUM
,
9669 /* Read the contents of a NEON quad register, by reading from two
9670 double registers. This is used to implement the quad pseudo
9671 registers, and for argument passing in case the quad registers are
9672 missing; vectors are passed in quad registers when using the VFP
9673 ABI, even if a NEON unit is not present. REGNUM is the index of
9674 the quad register, in [0, 15]. */
9676 static enum register_status
9677 arm_neon_quad_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9678 int regnum
, gdb_byte
*buf
)
9681 gdb_byte reg_buf
[8];
9682 int offset
, double_regnum
;
9683 enum register_status status
;
9685 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
9686 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9689 /* d0 is always the least significant half of q0. */
9690 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9695 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9696 if (status
!= REG_VALID
)
9698 memcpy (buf
+ offset
, reg_buf
, 8);
9700 offset
= 8 - offset
;
9701 status
= regcache_raw_read (regcache
, double_regnum
+ 1, reg_buf
);
9702 if (status
!= REG_VALID
)
9704 memcpy (buf
+ offset
, reg_buf
, 8);
9709 static enum register_status
9710 arm_pseudo_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9711 int regnum
, gdb_byte
*buf
)
9713 const int num_regs
= gdbarch_num_regs (gdbarch
);
9715 gdb_byte reg_buf
[8];
9716 int offset
, double_regnum
;
9718 gdb_assert (regnum
>= num_regs
);
9721 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
9722 /* Quad-precision register. */
9723 return arm_neon_quad_read (gdbarch
, regcache
, regnum
- 32, buf
);
9726 enum register_status status
;
9728 /* Single-precision register. */
9729 gdb_assert (regnum
< 32);
9731 /* s0 is always the least significant half of d0. */
9732 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9733 offset
= (regnum
& 1) ? 0 : 4;
9735 offset
= (regnum
& 1) ? 4 : 0;
9737 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
9738 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9741 status
= regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9742 if (status
== REG_VALID
)
9743 memcpy (buf
, reg_buf
+ offset
, 4);
9748 /* Store the contents of BUF to a NEON quad register, by writing to
9749 two double registers. This is used to implement the quad pseudo
9750 registers, and for argument passing in case the quad registers are
9751 missing; vectors are passed in quad registers when using the VFP
9752 ABI, even if a NEON unit is not present. REGNUM is the index
9753 of the quad register, in [0, 15]. */
9756 arm_neon_quad_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9757 int regnum
, const gdb_byte
*buf
)
9760 int offset
, double_regnum
;
9762 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
<< 1);
9763 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9766 /* d0 is always the least significant half of q0. */
9767 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9772 regcache_raw_write (regcache
, double_regnum
, buf
+ offset
);
9773 offset
= 8 - offset
;
9774 regcache_raw_write (regcache
, double_regnum
+ 1, buf
+ offset
);
9778 arm_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
9779 int regnum
, const gdb_byte
*buf
)
9781 const int num_regs
= gdbarch_num_regs (gdbarch
);
9783 gdb_byte reg_buf
[8];
9784 int offset
, double_regnum
;
9786 gdb_assert (regnum
>= num_regs
);
9789 if (gdbarch_tdep (gdbarch
)->have_neon_pseudos
&& regnum
>= 32 && regnum
< 48)
9790 /* Quad-precision register. */
9791 arm_neon_quad_write (gdbarch
, regcache
, regnum
- 32, buf
);
9794 /* Single-precision register. */
9795 gdb_assert (regnum
< 32);
9797 /* s0 is always the least significant half of d0. */
9798 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
9799 offset
= (regnum
& 1) ? 0 : 4;
9801 offset
= (regnum
& 1) ? 4 : 0;
9803 xsnprintf (name_buf
, sizeof (name_buf
), "d%d", regnum
>> 1);
9804 double_regnum
= user_reg_map_name_to_regnum (gdbarch
, name_buf
,
9807 regcache_raw_read (regcache
, double_regnum
, reg_buf
);
9808 memcpy (reg_buf
+ offset
, buf
, 4);
9809 regcache_raw_write (regcache
, double_regnum
, reg_buf
);
9813 static struct value
*
9814 value_of_arm_user_reg (struct frame_info
*frame
, const void *baton
)
9816 const int *reg_p
= (const int *) baton
;
9817 return value_of_register (*reg_p
, frame
);
9820 static enum gdb_osabi
9821 arm_elf_osabi_sniffer (bfd
*abfd
)
9823 unsigned int elfosabi
;
9824 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
9826 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
9828 if (elfosabi
== ELFOSABI_ARM
)
9829 /* GNU tools use this value. Check note sections in this case,
9831 bfd_map_over_sections (abfd
,
9832 generic_elf_osabi_sniff_abi_tag_sections
,
9835 /* Anything else will be handled by the generic ELF sniffer. */
9840 arm_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
9841 struct reggroup
*group
)
9843 /* FPS register's type is INT, but belongs to float_reggroup. Beside
9844 this, FPS register belongs to save_regroup, restore_reggroup, and
9845 all_reggroup, of course. */
9846 if (regnum
== ARM_FPS_REGNUM
)
9847 return (group
== float_reggroup
9848 || group
== save_reggroup
9849 || group
== restore_reggroup
9850 || group
== all_reggroup
);
9852 return default_register_reggroup_p (gdbarch
, regnum
, group
);
9856 /* For backward-compatibility we allow two 'g' packet lengths with
9857 the remote protocol depending on whether FPA registers are
9858 supplied. M-profile targets do not have FPA registers, but some
9859 stubs already exist in the wild which use a 'g' packet which
9860 supplies them albeit with dummy values. The packet format which
9861 includes FPA registers should be considered deprecated for
9862 M-profile targets. */
9865 arm_register_g_packet_guesses (struct gdbarch
*gdbarch
)
9867 if (gdbarch_tdep (gdbarch
)->is_m
)
9869 /* If we know from the executable this is an M-profile target,
9870 cater for remote targets whose register set layout is the
9871 same as the FPA layout. */
9872 register_remote_g_packet_guess (gdbarch
,
9873 /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
9874 (16 * INT_REGISTER_SIZE
)
9875 + (8 * FP_REGISTER_SIZE
)
9876 + (2 * INT_REGISTER_SIZE
),
9877 tdesc_arm_with_m_fpa_layout
);
9879 /* The regular M-profile layout. */
9880 register_remote_g_packet_guess (gdbarch
,
9881 /* r0-r12,sp,lr,pc; xpsr */
9882 (16 * INT_REGISTER_SIZE
)
9883 + INT_REGISTER_SIZE
,
9886 /* M-profile plus M4F VFP. */
9887 register_remote_g_packet_guess (gdbarch
,
9888 /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
9889 (16 * INT_REGISTER_SIZE
)
9890 + (16 * VFP_REGISTER_SIZE
)
9891 + (2 * INT_REGISTER_SIZE
),
9892 tdesc_arm_with_m_vfp_d16
);
9895 /* Otherwise we don't have a useful guess. */
9899 /* Initialize the current architecture based on INFO. If possible,
9900 re-use an architecture from ARCHES, which is a list of
9901 architectures already created during this debugging session.
9903 Called e.g. at program startup, when reading a core file, and when
9904 reading a binary file. */
9906 static struct gdbarch
*
9907 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
9909 struct gdbarch_tdep
*tdep
;
9910 struct gdbarch
*gdbarch
;
9911 struct gdbarch_list
*best_arch
;
9912 enum arm_abi_kind arm_abi
= arm_abi_global
;
9913 enum arm_float_model fp_model
= arm_fp_model
;
9914 struct tdesc_arch_data
*tdesc_data
= NULL
;
9916 int vfp_register_count
= 0, have_vfp_pseudos
= 0, have_neon_pseudos
= 0;
9917 int have_wmmx_registers
= 0;
9919 int have_fpa_registers
= 1;
9920 const struct target_desc
*tdesc
= info
.target_desc
;
9922 /* If we have an object to base this architecture on, try to determine
9925 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
9927 int ei_osabi
, e_flags
;
9929 switch (bfd_get_flavour (info
.abfd
))
9931 case bfd_target_aout_flavour
:
9932 /* Assume it's an old APCS-style ABI. */
9933 arm_abi
= ARM_ABI_APCS
;
9936 case bfd_target_coff_flavour
:
9937 /* Assume it's an old APCS-style ABI. */
9939 arm_abi
= ARM_ABI_APCS
;
9942 case bfd_target_elf_flavour
:
9943 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
9944 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
9946 if (ei_osabi
== ELFOSABI_ARM
)
9948 /* GNU tools used to use this value, but do not for EABI
9949 objects. There's nowhere to tag an EABI version
9950 anyway, so assume APCS. */
9951 arm_abi
= ARM_ABI_APCS
;
9953 else if (ei_osabi
== ELFOSABI_NONE
|| ei_osabi
== ELFOSABI_GNU
)
9955 int eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
9956 int attr_arch
, attr_profile
;
9960 case EF_ARM_EABI_UNKNOWN
:
9961 /* Assume GNU tools. */
9962 arm_abi
= ARM_ABI_APCS
;
9965 case EF_ARM_EABI_VER4
:
9966 case EF_ARM_EABI_VER5
:
9967 arm_abi
= ARM_ABI_AAPCS
;
9968 /* EABI binaries default to VFP float ordering.
9969 They may also contain build attributes that can
9970 be used to identify if the VFP argument-passing
9972 if (fp_model
== ARM_FLOAT_AUTO
)
9975 switch (bfd_elf_get_obj_attr_int (info
.abfd
,
9979 case AEABI_VFP_args_base
:
9980 /* "The user intended FP parameter/result
9981 passing to conform to AAPCS, base
9983 fp_model
= ARM_FLOAT_SOFT_VFP
;
9985 case AEABI_VFP_args_vfp
:
9986 /* "The user intended FP parameter/result
9987 passing to conform to AAPCS, VFP
9989 fp_model
= ARM_FLOAT_VFP
;
9991 case AEABI_VFP_args_toolchain
:
9992 /* "The user intended FP parameter/result
9993 passing to conform to tool chain-specific
9994 conventions" - we don't know any such
9995 conventions, so leave it as "auto". */
9997 case AEABI_VFP_args_compatible
:
9998 /* "Code is compatible with both the base
9999 and VFP variants; the user did not permit
10000 non-variadic functions to pass FP
10001 parameters/results" - leave it as
10005 /* Attribute value not mentioned in the
10006 November 2012 ABI, so leave it as
10011 fp_model
= ARM_FLOAT_SOFT_VFP
;
10017 /* Leave it as "auto". */
10018 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
10023 /* Detect M-profile programs. This only works if the
10024 executable file includes build attributes; GCC does
10025 copy them to the executable, but e.g. RealView does
10027 attr_arch
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_PROC
,
10029 attr_profile
= bfd_elf_get_obj_attr_int (info
.abfd
,
10031 Tag_CPU_arch_profile
);
10032 /* GCC specifies the profile for v6-M; RealView only
10033 specifies the profile for architectures starting with
10034 V7 (as opposed to architectures with a tag
10035 numerically greater than TAG_CPU_ARCH_V7). */
10036 if (!tdesc_has_registers (tdesc
)
10037 && (attr_arch
== TAG_CPU_ARCH_V6_M
10038 || attr_arch
== TAG_CPU_ARCH_V6S_M
10039 || attr_profile
== 'M'))
10044 if (fp_model
== ARM_FLOAT_AUTO
)
10046 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
10048 switch (e_flags
& (EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
))
10051 /* Leave it as "auto". Strictly speaking this case
10052 means FPA, but almost nobody uses that now, and
10053 many toolchains fail to set the appropriate bits
10054 for the floating-point model they use. */
10056 case EF_ARM_SOFT_FLOAT
:
10057 fp_model
= ARM_FLOAT_SOFT_FPA
;
10059 case EF_ARM_VFP_FLOAT
:
10060 fp_model
= ARM_FLOAT_VFP
;
10062 case EF_ARM_SOFT_FLOAT
| EF_ARM_VFP_FLOAT
:
10063 fp_model
= ARM_FLOAT_SOFT_VFP
;
10068 if (e_flags
& EF_ARM_BE8
)
10069 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
10074 /* Leave it as "auto". */
10079 /* Check any target description for validity. */
10080 if (tdesc_has_registers (tdesc
))
10082 /* For most registers we require GDB's default names; but also allow
10083 the numeric names for sp / lr / pc, as a convenience. */
10084 static const char *const arm_sp_names
[] = { "r13", "sp", NULL
};
10085 static const char *const arm_lr_names
[] = { "r14", "lr", NULL
};
10086 static const char *const arm_pc_names
[] = { "r15", "pc", NULL
};
10088 const struct tdesc_feature
*feature
;
10091 feature
= tdesc_find_feature (tdesc
,
10092 "org.gnu.gdb.arm.core");
10093 if (feature
== NULL
)
10095 feature
= tdesc_find_feature (tdesc
,
10096 "org.gnu.gdb.arm.m-profile");
10097 if (feature
== NULL
)
10103 tdesc_data
= tdesc_data_alloc ();
10106 for (i
= 0; i
< ARM_SP_REGNUM
; i
++)
10107 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
10108 arm_register_names
[i
]);
10109 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
10112 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
10115 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
10119 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10120 ARM_PS_REGNUM
, "xpsr");
10122 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10123 ARM_PS_REGNUM
, "cpsr");
10127 tdesc_data_cleanup (tdesc_data
);
10131 feature
= tdesc_find_feature (tdesc
,
10132 "org.gnu.gdb.arm.fpa");
10133 if (feature
!= NULL
)
10136 for (i
= ARM_F0_REGNUM
; i
<= ARM_FPS_REGNUM
; i
++)
10137 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
10138 arm_register_names
[i
]);
10141 tdesc_data_cleanup (tdesc_data
);
10146 have_fpa_registers
= 0;
10148 feature
= tdesc_find_feature (tdesc
,
10149 "org.gnu.gdb.xscale.iwmmxt");
10150 if (feature
!= NULL
)
10152 static const char *const iwmmxt_names
[] = {
10153 "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
10154 "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
10155 "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
10156 "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
10160 for (i
= ARM_WR0_REGNUM
; i
<= ARM_WR15_REGNUM
; i
++)
10162 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
10163 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
10165 /* Check for the control registers, but do not fail if they
10167 for (i
= ARM_WC0_REGNUM
; i
<= ARM_WCASF_REGNUM
; i
++)
10168 tdesc_numbered_register (feature
, tdesc_data
, i
,
10169 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
10171 for (i
= ARM_WCGR0_REGNUM
; i
<= ARM_WCGR3_REGNUM
; i
++)
10173 &= tdesc_numbered_register (feature
, tdesc_data
, i
,
10174 iwmmxt_names
[i
- ARM_WR0_REGNUM
]);
10178 tdesc_data_cleanup (tdesc_data
);
10182 have_wmmx_registers
= 1;
10185 /* If we have a VFP unit, check whether the single precision registers
10186 are present. If not, then we will synthesize them as pseudo
10188 feature
= tdesc_find_feature (tdesc
,
10189 "org.gnu.gdb.arm.vfp");
10190 if (feature
!= NULL
)
10192 static const char *const vfp_double_names
[] = {
10193 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
10194 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
10195 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
10196 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
10199 /* Require the double precision registers. There must be either
10202 for (i
= 0; i
< 32; i
++)
10204 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10206 vfp_double_names
[i
]);
10210 if (!valid_p
&& i
== 16)
10213 /* Also require FPSCR. */
10214 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
10215 ARM_FPSCR_REGNUM
, "fpscr");
10218 tdesc_data_cleanup (tdesc_data
);
10222 if (tdesc_unnumbered_register (feature
, "s0") == 0)
10223 have_vfp_pseudos
= 1;
10225 vfp_register_count
= i
;
10227 /* If we have VFP, also check for NEON. The architecture allows
10228 NEON without VFP (integer vector operations only), but GDB
10229 does not support that. */
10230 feature
= tdesc_find_feature (tdesc
,
10231 "org.gnu.gdb.arm.neon");
10232 if (feature
!= NULL
)
10234 /* NEON requires 32 double-precision registers. */
10237 tdesc_data_cleanup (tdesc_data
);
10241 /* If there are quad registers defined by the stub, use
10242 their type; otherwise (normally) provide them with
10243 the default type. */
10244 if (tdesc_unnumbered_register (feature
, "q0") == 0)
10245 have_neon_pseudos
= 1;
10252 /* If there is already a candidate, use it. */
10253 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
10255 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
10257 if (arm_abi
!= ARM_ABI_AUTO
10258 && arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
10261 if (fp_model
!= ARM_FLOAT_AUTO
10262 && fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
10265 /* There are various other properties in tdep that we do not
10266 need to check here: those derived from a target description,
10267 since gdbarches with a different target description are
10268 automatically disqualified. */
10270 /* Do check is_m, though, since it might come from the binary. */
10271 if (is_m
!= gdbarch_tdep (best_arch
->gdbarch
)->is_m
)
10274 /* Found a match. */
10278 if (best_arch
!= NULL
)
10280 if (tdesc_data
!= NULL
)
10281 tdesc_data_cleanup (tdesc_data
);
10282 return best_arch
->gdbarch
;
10285 tdep
= XCNEW (struct gdbarch_tdep
);
10286 gdbarch
= gdbarch_alloc (&info
, tdep
);
10288 /* Record additional information about the architecture we are defining.
10289 These are gdbarch discriminators, like the OSABI. */
10290 tdep
->arm_abi
= arm_abi
;
10291 tdep
->fp_model
= fp_model
;
10293 tdep
->have_fpa_registers
= have_fpa_registers
;
10294 tdep
->have_wmmx_registers
= have_wmmx_registers
;
10295 gdb_assert (vfp_register_count
== 0
10296 || vfp_register_count
== 16
10297 || vfp_register_count
== 32);
10298 tdep
->vfp_register_count
= vfp_register_count
;
10299 tdep
->have_vfp_pseudos
= have_vfp_pseudos
;
10300 tdep
->have_neon_pseudos
= have_neon_pseudos
;
10301 tdep
->have_neon
= have_neon
;
10303 arm_register_g_packet_guesses (gdbarch
);
10306 switch (info
.byte_order_for_code
)
10308 case BFD_ENDIAN_BIG
:
10309 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
10310 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
10311 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
10312 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
10316 case BFD_ENDIAN_LITTLE
:
10317 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
10318 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
10319 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
10320 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
10325 internal_error (__FILE__
, __LINE__
,
10326 _("arm_gdbarch_init: bad byte order for float format"));
10329 /* On ARM targets char defaults to unsigned. */
10330 set_gdbarch_char_signed (gdbarch
, 0);
10332 /* Note: for displaced stepping, this includes the breakpoint, and one word
10333 of additional scratch space. This setting isn't used for anything beside
10334 displaced stepping at present. */
10335 set_gdbarch_max_insn_length (gdbarch
, 4 * DISPLACED_MODIFIED_INSNS
);
10337 /* This should be low enough for everything. */
10338 tdep
->lowest_pc
= 0x20;
10339 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
10341 /* The default, for both APCS and AAPCS, is to return small
10342 structures in registers. */
10343 tdep
->struct_return
= reg_struct_return
;
10345 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
10346 set_gdbarch_frame_align (gdbarch
, arm_frame_align
);
10348 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
10350 /* Frame handling. */
10351 set_gdbarch_dummy_id (gdbarch
, arm_dummy_id
);
10352 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
10353 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
10355 frame_base_set_default (gdbarch
, &arm_normal_base
);
10357 /* Address manipulation. */
10358 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
10360 /* Advance PC across function entry code. */
10361 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
10363 /* Detect whether PC is at a point where the stack has been destroyed. */
10364 set_gdbarch_stack_frame_destroyed_p (gdbarch
, arm_stack_frame_destroyed_p
);
10366 /* Skip trampolines. */
10367 set_gdbarch_skip_trampoline_code (gdbarch
, arm_skip_stub
);
10369 /* The stack grows downward. */
10370 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
10372 /* Breakpoint manipulation. */
10373 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
10374 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
10375 arm_remote_breakpoint_from_pc
);
10377 /* Information about registers, etc. */
10378 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
10379 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
10380 set_gdbarch_num_regs (gdbarch
, ARM_NUM_REGS
);
10381 set_gdbarch_register_type (gdbarch
, arm_register_type
);
10382 set_gdbarch_register_reggroup_p (gdbarch
, arm_register_reggroup_p
);
10384 /* This "info float" is FPA-specific. Use the generic version if we
10385 do not have FPA. */
10386 if (gdbarch_tdep (gdbarch
)->have_fpa_registers
)
10387 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
10389 /* Internal <-> external register number maps. */
10390 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, arm_dwarf_reg_to_regnum
);
10391 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
10393 set_gdbarch_register_name (gdbarch
, arm_register_name
);
10395 /* Returning results. */
10396 set_gdbarch_return_value (gdbarch
, arm_return_value
);
10399 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
10401 /* Minsymbol frobbing. */
10402 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
10403 set_gdbarch_coff_make_msymbol_special (gdbarch
,
10404 arm_coff_make_msymbol_special
);
10405 set_gdbarch_record_special_symbol (gdbarch
, arm_record_special_symbol
);
10407 /* Thumb-2 IT block support. */
10408 set_gdbarch_adjust_breakpoint_address (gdbarch
,
10409 arm_adjust_breakpoint_address
);
10411 /* Virtual tables. */
10412 set_gdbarch_vbit_in_delta (gdbarch
, 1);
10414 /* Hook in the ABI-specific overrides, if they have been registered. */
10415 gdbarch_init_osabi (info
, gdbarch
);
10417 dwarf2_frame_set_init_reg (gdbarch
, arm_dwarf2_frame_init_reg
);
10419 /* Add some default predicates. */
10421 frame_unwind_append_unwinder (gdbarch
, &arm_m_exception_unwind
);
10422 frame_unwind_append_unwinder (gdbarch
, &arm_stub_unwind
);
10423 dwarf2_append_unwinders (gdbarch
);
10424 frame_unwind_append_unwinder (gdbarch
, &arm_exidx_unwind
);
10425 frame_unwind_append_unwinder (gdbarch
, &arm_prologue_unwind
);
10427 /* Now we have tuned the configuration, set a few final things,
10428 based on what the OS ABI has told us. */
10430 /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
10431 binaries are always marked. */
10432 if (tdep
->arm_abi
== ARM_ABI_AUTO
)
10433 tdep
->arm_abi
= ARM_ABI_APCS
;
10435 /* Watchpoints are not steppable. */
10436 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
10438 /* We used to default to FPA for generic ARM, but almost nobody
10439 uses that now, and we now provide a way for the user to force
10440 the model. So default to the most useful variant. */
10441 if (tdep
->fp_model
== ARM_FLOAT_AUTO
)
10442 tdep
->fp_model
= ARM_FLOAT_SOFT_FPA
;
10444 if (tdep
->jb_pc
>= 0)
10445 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
10447 /* Floating point sizes and format. */
10448 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
10449 if (tdep
->fp_model
== ARM_FLOAT_SOFT_FPA
|| tdep
->fp_model
== ARM_FLOAT_FPA
)
10451 set_gdbarch_double_format
10452 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
10453 set_gdbarch_long_double_format
10454 (gdbarch
, floatformats_ieee_double_littlebyte_bigword
);
10458 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
10459 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
10462 if (have_vfp_pseudos
)
10464 /* NOTE: These are the only pseudo registers used by
10465 the ARM target at the moment. If more are added, a
10466 little more care in numbering will be needed. */
10468 int num_pseudos
= 32;
10469 if (have_neon_pseudos
)
10471 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudos
);
10472 set_gdbarch_pseudo_register_read (gdbarch
, arm_pseudo_read
);
10473 set_gdbarch_pseudo_register_write (gdbarch
, arm_pseudo_write
);
10478 set_tdesc_pseudo_register_name (gdbarch
, arm_register_name
);
10480 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
10482 /* Override tdesc_register_type to adjust the types of VFP
10483 registers for NEON. */
10484 set_gdbarch_register_type (gdbarch
, arm_register_type
);
10487 /* Add standard register aliases. We add aliases even for those
10488 nanes which are used by the current architecture - it's simpler,
10489 and does no harm, since nothing ever lists user registers. */
10490 for (i
= 0; i
< ARRAY_SIZE (arm_register_aliases
); i
++)
10491 user_reg_add (gdbarch
, arm_register_aliases
[i
].name
,
10492 value_of_arm_user_reg
, &arm_register_aliases
[i
].regnum
);
10498 arm_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
10500 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
10505 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
10506 (unsigned long) tdep
->lowest_pc
);
10509 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
10512 _initialize_arm_tdep (void)
10514 struct ui_file
*stb
;
10516 struct cmd_list_element
*new_set
, *new_show
;
10517 const char *setname
;
10518 const char *setdesc
;
10519 const char *const *regnames
;
10521 static char *helptext
;
10522 char regdesc
[1024], *rdptr
= regdesc
;
10523 size_t rest
= sizeof (regdesc
);
10525 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
10527 arm_objfile_data_key
10528 = register_objfile_data_with_cleanup (NULL
, arm_objfile_data_free
);
10530 /* Add ourselves to objfile event chain. */
10531 observer_attach_new_objfile (arm_exidx_new_objfile
);
10533 = register_objfile_data_with_cleanup (NULL
, arm_exidx_data_free
);
10535 /* Register an ELF OS ABI sniffer for ARM binaries. */
10536 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
10537 bfd_target_elf_flavour
,
10538 arm_elf_osabi_sniffer
);
10540 /* Initialize the standard target descriptions. */
10541 initialize_tdesc_arm_with_m ();
10542 initialize_tdesc_arm_with_m_fpa_layout ();
10543 initialize_tdesc_arm_with_m_vfp_d16 ();
10544 initialize_tdesc_arm_with_iwmmxt ();
10545 initialize_tdesc_arm_with_vfpv2 ();
10546 initialize_tdesc_arm_with_vfpv3 ();
10547 initialize_tdesc_arm_with_neon ();
10549 /* Get the number of possible sets of register names defined in opcodes. */
10550 num_disassembly_options
= get_arm_regname_num_options ();
10552 /* Add root prefix command for all "set arm"/"show arm" commands. */
10553 add_prefix_cmd ("arm", no_class
, set_arm_command
,
10554 _("Various ARM-specific commands."),
10555 &setarmcmdlist
, "set arm ", 0, &setlist
);
10557 add_prefix_cmd ("arm", no_class
, show_arm_command
,
10558 _("Various ARM-specific commands."),
10559 &showarmcmdlist
, "show arm ", 0, &showlist
);
10561 /* Sync the opcode insn printer with our register viewer. */
10562 parse_arm_disassembler_option ("reg-names-std");
10564 /* Initialize the array that will be passed to
10565 add_setshow_enum_cmd(). */
10566 valid_disassembly_styles
= XNEWVEC (const char *,
10567 num_disassembly_options
+ 1);
10568 for (i
= 0; i
< num_disassembly_options
; i
++)
10570 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
10571 valid_disassembly_styles
[i
] = setname
;
10572 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
10575 /* When we find the default names, tell the disassembler to use
10577 if (!strcmp (setname
, "std"))
10579 disassembly_style
= setname
;
10580 set_arm_regname_option (i
);
10583 /* Mark the end of valid options. */
10584 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
10586 /* Create the help text. */
10587 stb
= mem_fileopen ();
10588 fprintf_unfiltered (stb
, "%s%s%s",
10589 _("The valid values are:\n"),
10591 _("The default is \"std\"."));
10592 helptext
= ui_file_xstrdup (stb
, NULL
);
10593 ui_file_delete (stb
);
10595 add_setshow_enum_cmd("disassembler", no_class
,
10596 valid_disassembly_styles
, &disassembly_style
,
10597 _("Set the disassembly style."),
10598 _("Show the disassembly style."),
10600 set_disassembly_style_sfunc
,
10601 NULL
, /* FIXME: i18n: The disassembly style is
10603 &setarmcmdlist
, &showarmcmdlist
);
10605 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
10606 _("Set usage of ARM 32-bit mode."),
10607 _("Show usage of ARM 32-bit mode."),
10608 _("When off, a 26-bit PC will be used."),
10610 NULL
, /* FIXME: i18n: Usage of ARM 32-bit
10612 &setarmcmdlist
, &showarmcmdlist
);
10614 /* Add a command to allow the user to force the FPU model. */
10615 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
10616 _("Set the floating point type."),
10617 _("Show the floating point type."),
10618 _("auto - Determine the FP typefrom the OS-ABI.\n\
10619 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
10620 fpa - FPA co-processor (GCC compiled).\n\
10621 softvfp - Software FP with pure-endian doubles.\n\
10622 vfp - VFP co-processor."),
10623 set_fp_model_sfunc
, show_fp_model
,
10624 &setarmcmdlist
, &showarmcmdlist
);
10626 /* Add a command to allow the user to force the ABI. */
10627 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
10629 _("Show the ABI."),
10630 NULL
, arm_set_abi
, arm_show_abi
,
10631 &setarmcmdlist
, &showarmcmdlist
);
10633 /* Add two commands to allow the user to force the assumed
10635 add_setshow_enum_cmd ("fallback-mode", class_support
,
10636 arm_mode_strings
, &arm_fallback_mode_string
,
10637 _("Set the mode assumed when symbols are unavailable."),
10638 _("Show the mode assumed when symbols are unavailable."),
10639 NULL
, NULL
, arm_show_fallback_mode
,
10640 &setarmcmdlist
, &showarmcmdlist
);
10641 add_setshow_enum_cmd ("force-mode", class_support
,
10642 arm_mode_strings
, &arm_force_mode_string
,
10643 _("Set the mode assumed even when symbols are available."),
10644 _("Show the mode assumed even when symbols are available."),
10645 NULL
, NULL
, arm_show_force_mode
,
10646 &setarmcmdlist
, &showarmcmdlist
);
10648 /* Debugging flag. */
10649 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
10650 _("Set ARM debugging."),
10651 _("Show ARM debugging."),
10652 _("When on, arm-specific debugging is enabled."),
10654 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
10655 &setdebuglist
, &showdebuglist
);
10658 /* ARM-reversible process record data structures. */
10660 #define ARM_INSN_SIZE_BYTES 4
10661 #define THUMB_INSN_SIZE_BYTES 2
10662 #define THUMB2_INSN_SIZE_BYTES 4
10665 /* Position of the bit within a 32-bit ARM instruction
10666 that defines whether the instruction is a load or store. */
10667 #define INSN_S_L_BIT_NUM 20
10669 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
10672 unsigned int reg_len = LENGTH; \
10675 REGS = XNEWVEC (uint32_t, reg_len); \
10676 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
10681 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
10684 unsigned int mem_len = LENGTH; \
10687 MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
10688 memcpy(&MEMS->len, &RECORD_BUF[0], \
10689 sizeof(struct arm_mem_r) * LENGTH); \
10694 /* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
10695 #define INSN_RECORDED(ARM_RECORD) \
10696 (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
10698 /* ARM memory record structure. */
10701 uint32_t len
; /* Record length. */
10702 uint32_t addr
; /* Memory address. */
10705 /* ARM instruction record contains opcode of current insn
10706 and execution state (before entry to decode_insn()),
10707 contains list of to-be-modified registers and
10708 memory blocks (on return from decode_insn()). */
10710 typedef struct insn_decode_record_t
10712 struct gdbarch
*gdbarch
;
10713 struct regcache
*regcache
;
10714 CORE_ADDR this_addr
; /* Address of the insn being decoded. */
10715 uint32_t arm_insn
; /* Should accommodate thumb. */
10716 uint32_t cond
; /* Condition code. */
10717 uint32_t opcode
; /* Insn opcode. */
10718 uint32_t decode
; /* Insn decode bits. */
10719 uint32_t mem_rec_count
; /* No of mem records. */
10720 uint32_t reg_rec_count
; /* No of reg records. */
10721 uint32_t *arm_regs
; /* Registers to be saved for this record. */
10722 struct arm_mem_r
*arm_mems
; /* Memory to be saved for this record. */
10723 } insn_decode_record
;
10726 /* Checks ARM SBZ and SBO mandatory fields. */
10729 sbo_sbz (uint32_t insn
, uint32_t bit_num
, uint32_t len
, uint32_t sbo
)
10731 uint32_t ones
= bits (insn
, bit_num
- 1, (bit_num
-1) + (len
- 1));
10750 enum arm_record_result
10752 ARM_RECORD_SUCCESS
= 0,
10753 ARM_RECORD_FAILURE
= 1
10760 } arm_record_strx_t
;
10771 arm_record_strx (insn_decode_record
*arm_insn_r
, uint32_t *record_buf
,
10772 uint32_t *record_buf_mem
, arm_record_strx_t str_type
)
10775 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10776 ULONGEST u_regval
[2]= {0};
10778 uint32_t reg_src1
= 0, reg_src2
= 0;
10779 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
10780 uint32_t opcode1
= 0;
10782 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
10783 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
10784 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
10787 if (14 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
10789 /* 1) Handle misc store, immediate offset. */
10790 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
10791 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
10792 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10793 regcache_raw_read_unsigned (reg_cache
, reg_src1
,
10795 if (ARM_PC_REGNUM
== reg_src1
)
10797 /* If R15 was used as Rn, hence current PC+8. */
10798 u_regval
[0] = u_regval
[0] + 8;
10800 offset_8
= (immed_high
<< 4) | immed_low
;
10801 /* Calculate target store address. */
10802 if (14 == arm_insn_r
->opcode
)
10804 tgt_mem_addr
= u_regval
[0] + offset_8
;
10808 tgt_mem_addr
= u_regval
[0] - offset_8
;
10810 if (ARM_RECORD_STRH
== str_type
)
10812 record_buf_mem
[0] = 2;
10813 record_buf_mem
[1] = tgt_mem_addr
;
10814 arm_insn_r
->mem_rec_count
= 1;
10816 else if (ARM_RECORD_STRD
== str_type
)
10818 record_buf_mem
[0] = 4;
10819 record_buf_mem
[1] = tgt_mem_addr
;
10820 record_buf_mem
[2] = 4;
10821 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10822 arm_insn_r
->mem_rec_count
= 2;
10825 else if (12 == arm_insn_r
->opcode
|| 8 == arm_insn_r
->opcode
)
10827 /* 2) Store, register offset. */
10829 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10831 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10832 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10833 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10834 if (15 == reg_src2
)
10836 /* If R15 was used as Rn, hence current PC+8. */
10837 u_regval
[0] = u_regval
[0] + 8;
10839 /* Calculate target store address, Rn +/- Rm, register offset. */
10840 if (12 == arm_insn_r
->opcode
)
10842 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10846 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10848 if (ARM_RECORD_STRH
== str_type
)
10850 record_buf_mem
[0] = 2;
10851 record_buf_mem
[1] = tgt_mem_addr
;
10852 arm_insn_r
->mem_rec_count
= 1;
10854 else if (ARM_RECORD_STRD
== str_type
)
10856 record_buf_mem
[0] = 4;
10857 record_buf_mem
[1] = tgt_mem_addr
;
10858 record_buf_mem
[2] = 4;
10859 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10860 arm_insn_r
->mem_rec_count
= 2;
10863 else if (11 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
10864 || 2 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
10866 /* 3) Store, immediate pre-indexed. */
10867 /* 5) Store, immediate post-indexed. */
10868 immed_low
= bits (arm_insn_r
->arm_insn
, 0, 3);
10869 immed_high
= bits (arm_insn_r
->arm_insn
, 8, 11);
10870 offset_8
= (immed_high
<< 4) | immed_low
;
10871 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
10872 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10873 /* Calculate target store address, Rn +/- Rm, register offset. */
10874 if (15 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
)
10876 tgt_mem_addr
= u_regval
[0] + offset_8
;
10880 tgt_mem_addr
= u_regval
[0] - offset_8
;
10882 if (ARM_RECORD_STRH
== str_type
)
10884 record_buf_mem
[0] = 2;
10885 record_buf_mem
[1] = tgt_mem_addr
;
10886 arm_insn_r
->mem_rec_count
= 1;
10888 else if (ARM_RECORD_STRD
== str_type
)
10890 record_buf_mem
[0] = 4;
10891 record_buf_mem
[1] = tgt_mem_addr
;
10892 record_buf_mem
[2] = 4;
10893 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10894 arm_insn_r
->mem_rec_count
= 2;
10896 /* Record Rn also as it changes. */
10897 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
10898 arm_insn_r
->reg_rec_count
= 1;
10900 else if (9 == arm_insn_r
->opcode
|| 13 == arm_insn_r
->opcode
10901 || 0 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
10903 /* 4) Store, register pre-indexed. */
10904 /* 6) Store, register post -indexed. */
10905 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
10906 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
10907 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
10908 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
10909 /* Calculate target store address, Rn +/- Rm, register offset. */
10910 if (13 == arm_insn_r
->opcode
|| 4 == arm_insn_r
->opcode
)
10912 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
10916 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
10918 if (ARM_RECORD_STRH
== str_type
)
10920 record_buf_mem
[0] = 2;
10921 record_buf_mem
[1] = tgt_mem_addr
;
10922 arm_insn_r
->mem_rec_count
= 1;
10924 else if (ARM_RECORD_STRD
== str_type
)
10926 record_buf_mem
[0] = 4;
10927 record_buf_mem
[1] = tgt_mem_addr
;
10928 record_buf_mem
[2] = 4;
10929 record_buf_mem
[3] = tgt_mem_addr
+ 4;
10930 arm_insn_r
->mem_rec_count
= 2;
10932 /* Record Rn also as it changes. */
10933 *(record_buf
) = bits (arm_insn_r
->arm_insn
, 16, 19);
10934 arm_insn_r
->reg_rec_count
= 1;
10939 /* Handling ARM extension space insns. */
10942 arm_record_extension_space (insn_decode_record
*arm_insn_r
)
10944 uint32_t ret
= 0; /* Return value: -1:record failure ; 0:success */
10945 uint32_t opcode1
= 0, opcode2
= 0, insn_op1
= 0;
10946 uint32_t record_buf
[8], record_buf_mem
[8];
10947 uint32_t reg_src1
= 0;
10948 uint32_t immed_high
= 0, immed_low
= 0,offset_8
= 0, tgt_mem_addr
= 0;
10949 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
10950 ULONGEST u_regval
= 0;
10952 gdb_assert (!INSN_RECORDED(arm_insn_r
));
10953 /* Handle unconditional insn extension space. */
10955 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 27);
10956 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10957 if (arm_insn_r
->cond
)
10959 /* PLD has no affect on architectural state, it just affects
10961 if (5 == ((opcode1
& 0xE0) >> 5))
10964 record_buf
[0] = ARM_PS_REGNUM
;
10965 record_buf
[1] = ARM_LR_REGNUM
;
10966 arm_insn_r
->reg_rec_count
= 2;
10968 /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
10972 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
10973 if (3 == opcode1
&& bit (arm_insn_r
->arm_insn
, 4))
10976 /* Undefined instruction on ARM V5; need to handle if later
10977 versions define it. */
10980 opcode1
= bits (arm_insn_r
->arm_insn
, 24, 27);
10981 opcode2
= bits (arm_insn_r
->arm_insn
, 4, 7);
10982 insn_op1
= bits (arm_insn_r
->arm_insn
, 20, 23);
10984 /* Handle arithmetic insn extension space. */
10985 if (!opcode1
&& 9 == opcode2
&& 1 != arm_insn_r
->cond
10986 && !INSN_RECORDED(arm_insn_r
))
10988 /* Handle MLA(S) and MUL(S). */
10989 if (0 <= insn_op1
&& 3 >= insn_op1
)
10991 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
10992 record_buf
[1] = ARM_PS_REGNUM
;
10993 arm_insn_r
->reg_rec_count
= 2;
10995 else if (4 <= insn_op1
&& 15 >= insn_op1
)
10997 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
10998 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
10999 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
11000 record_buf
[2] = ARM_PS_REGNUM
;
11001 arm_insn_r
->reg_rec_count
= 3;
11005 opcode1
= bits (arm_insn_r
->arm_insn
, 26, 27);
11006 opcode2
= bits (arm_insn_r
->arm_insn
, 23, 24);
11007 insn_op1
= bits (arm_insn_r
->arm_insn
, 21, 22);
11009 /* Handle control insn extension space. */
11011 if (!opcode1
&& 2 == opcode2
&& !bit (arm_insn_r
->arm_insn
, 20)
11012 && 1 != arm_insn_r
->cond
&& !INSN_RECORDED(arm_insn_r
))
11014 if (!bit (arm_insn_r
->arm_insn
,25))
11016 if (!bits (arm_insn_r
->arm_insn
, 4, 7))
11018 if ((0 == insn_op1
) || (2 == insn_op1
))
11021 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11022 arm_insn_r
->reg_rec_count
= 1;
11024 else if (1 == insn_op1
)
11026 /* CSPR is going to be changed. */
11027 record_buf
[0] = ARM_PS_REGNUM
;
11028 arm_insn_r
->reg_rec_count
= 1;
11030 else if (3 == insn_op1
)
11032 /* SPSR is going to be changed. */
11033 /* We need to get SPSR value, which is yet to be done. */
11034 printf_unfiltered (_("Process record does not support "
11035 "instruction 0x%0x at address %s.\n"),
11036 arm_insn_r
->arm_insn
,
11037 paddress (arm_insn_r
->gdbarch
,
11038 arm_insn_r
->this_addr
));
11042 else if (1 == bits (arm_insn_r
->arm_insn
, 4, 7))
11047 record_buf
[0] = ARM_PS_REGNUM
;
11048 arm_insn_r
->reg_rec_count
= 1;
11050 else if (3 == insn_op1
)
11053 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11054 arm_insn_r
->reg_rec_count
= 1;
11057 else if (3 == bits (arm_insn_r
->arm_insn
, 4, 7))
11060 record_buf
[0] = ARM_PS_REGNUM
;
11061 record_buf
[1] = ARM_LR_REGNUM
;
11062 arm_insn_r
->reg_rec_count
= 2;
11064 else if (5 == bits (arm_insn_r
->arm_insn
, 4, 7))
11066 /* QADD, QSUB, QDADD, QDSUB */
11067 record_buf
[0] = ARM_PS_REGNUM
;
11068 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
11069 arm_insn_r
->reg_rec_count
= 2;
11071 else if (7 == bits (arm_insn_r
->arm_insn
, 4, 7))
11074 record_buf
[0] = ARM_PS_REGNUM
;
11075 record_buf
[1] = ARM_LR_REGNUM
;
11076 arm_insn_r
->reg_rec_count
= 2;
11078 /* Save SPSR also;how? */
11079 printf_unfiltered (_("Process record does not support "
11080 "instruction 0x%0x at address %s.\n"),
11081 arm_insn_r
->arm_insn
,
11082 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11085 else if(8 == bits (arm_insn_r
->arm_insn
, 4, 7)
11086 || 10 == bits (arm_insn_r
->arm_insn
, 4, 7)
11087 || 12 == bits (arm_insn_r
->arm_insn
, 4, 7)
11088 || 14 == bits (arm_insn_r
->arm_insn
, 4, 7)
11091 if (0 == insn_op1
|| 1 == insn_op1
)
11093 /* SMLA<x><y>, SMLAW<y>, SMULW<y>. */
11094 /* We dont do optimization for SMULW<y> where we
11096 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11097 record_buf
[1] = ARM_PS_REGNUM
;
11098 arm_insn_r
->reg_rec_count
= 2;
11100 else if (2 == insn_op1
)
11103 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11104 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
11105 arm_insn_r
->reg_rec_count
= 2;
11107 else if (3 == insn_op1
)
11110 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11111 arm_insn_r
->reg_rec_count
= 1;
11117 /* MSR : immediate form. */
11120 /* CSPR is going to be changed. */
11121 record_buf
[0] = ARM_PS_REGNUM
;
11122 arm_insn_r
->reg_rec_count
= 1;
11124 else if (3 == insn_op1
)
11126 /* SPSR is going to be changed. */
11127 /* we need to get SPSR value, which is yet to be done */
11128 printf_unfiltered (_("Process record does not support "
11129 "instruction 0x%0x at address %s.\n"),
11130 arm_insn_r
->arm_insn
,
11131 paddress (arm_insn_r
->gdbarch
,
11132 arm_insn_r
->this_addr
));
11138 opcode1
= bits (arm_insn_r
->arm_insn
, 25, 27);
11139 opcode2
= bits (arm_insn_r
->arm_insn
, 20, 24);
11140 insn_op1
= bits (arm_insn_r
->arm_insn
, 5, 6);
11142 /* Handle load/store insn extension space. */
11144 if (!opcode1
&& bit (arm_insn_r
->arm_insn
, 7)
11145 && bit (arm_insn_r
->arm_insn
, 4) && 1 != arm_insn_r
->cond
11146 && !INSN_RECORDED(arm_insn_r
))
11151 /* These insn, changes register and memory as well. */
11152 /* SWP or SWPB insn. */
11153 /* Get memory address given by Rn. */
11154 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11155 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
11156 /* SWP insn ?, swaps word. */
11157 if (8 == arm_insn_r
->opcode
)
11159 record_buf_mem
[0] = 4;
11163 /* SWPB insn, swaps only byte. */
11164 record_buf_mem
[0] = 1;
11166 record_buf_mem
[1] = u_regval
;
11167 arm_insn_r
->mem_rec_count
= 1;
11168 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11169 arm_insn_r
->reg_rec_count
= 1;
11171 else if (1 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
11174 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11177 else if (2 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
11180 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11181 record_buf
[1] = record_buf
[0] + 1;
11182 arm_insn_r
->reg_rec_count
= 2;
11184 else if (3 == insn_op1
&& !bit (arm_insn_r
->arm_insn
, 20))
11187 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11190 else if (bit (arm_insn_r
->arm_insn
, 20) && insn_op1
<= 3)
11192 /* LDRH, LDRSB, LDRSH. */
11193 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11194 arm_insn_r
->reg_rec_count
= 1;
11199 opcode1
= bits (arm_insn_r
->arm_insn
, 23, 27);
11200 if (24 == opcode1
&& bit (arm_insn_r
->arm_insn
, 21)
11201 && !INSN_RECORDED(arm_insn_r
))
11204 /* Handle coprocessor insn extension space. */
11207 /* To be done for ARMv5 and later; as of now we return -1. */
11209 printf_unfiltered (_("Process record does not support instruction x%0x "
11210 "at address %s.\n"),arm_insn_r
->arm_insn
,
11211 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11214 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11215 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11220 /* Handling opcode 000 insns. */
11223 arm_record_data_proc_misc_ld_str (insn_decode_record
*arm_insn_r
)
11225 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11226 uint32_t record_buf
[8], record_buf_mem
[8];
11227 ULONGEST u_regval
[2] = {0};
11229 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
11230 uint32_t immed_high
= 0, immed_low
= 0, offset_8
= 0, tgt_mem_addr
= 0;
11231 uint32_t opcode1
= 0;
11233 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11234 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11235 opcode1
= bits (arm_insn_r
->arm_insn
, 20, 24);
11237 /* Data processing insn /multiply insn. */
11238 if (9 == arm_insn_r
->decode
11239 && ((4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
11240 || (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)))
11242 /* Handle multiply instructions. */
11243 /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
11244 if (0 == arm_insn_r
->opcode
|| 1 == arm_insn_r
->opcode
)
11246 /* Handle MLA and MUL. */
11247 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
11248 record_buf
[1] = ARM_PS_REGNUM
;
11249 arm_insn_r
->reg_rec_count
= 2;
11251 else if (4 <= arm_insn_r
->opcode
&& 7 >= arm_insn_r
->opcode
)
11253 /* Handle SMLAL, SMULL, UMLAL, UMULL. */
11254 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 16, 19);
11255 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 12, 15);
11256 record_buf
[2] = ARM_PS_REGNUM
;
11257 arm_insn_r
->reg_rec_count
= 3;
11260 else if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
11261 && (11 == arm_insn_r
->decode
|| 13 == arm_insn_r
->decode
))
11263 /* Handle misc load insns, as 20th bit (L = 1). */
11264 /* LDR insn has a capability to do branching, if
11265 MOV LR, PC is precceded by LDR insn having Rn as R15
11266 in that case, it emulates branch and link insn, and hence we
11267 need to save CSPR and PC as well. I am not sure this is right
11268 place; as opcode = 010 LDR insn make this happen, if R15 was
11270 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11271 if (15 != reg_dest
)
11273 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11274 arm_insn_r
->reg_rec_count
= 1;
11278 record_buf
[0] = reg_dest
;
11279 record_buf
[1] = ARM_PS_REGNUM
;
11280 arm_insn_r
->reg_rec_count
= 2;
11283 else if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
11284 && sbo_sbz (arm_insn_r
->arm_insn
, 5, 12, 0)
11285 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
11286 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21))
11288 /* Handle MSR insn. */
11289 if (9 == arm_insn_r
->opcode
)
11291 /* CSPR is going to be changed. */
11292 record_buf
[0] = ARM_PS_REGNUM
;
11293 arm_insn_r
->reg_rec_count
= 1;
11297 /* SPSR is going to be changed. */
11298 /* How to read SPSR value? */
11299 printf_unfiltered (_("Process record does not support instruction "
11300 "0x%0x at address %s.\n"),
11301 arm_insn_r
->arm_insn
,
11302 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11306 else if (9 == arm_insn_r
->decode
11307 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
11308 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11310 /* Handling SWP, SWPB. */
11311 /* These insn, changes register and memory as well. */
11312 /* SWP or SWPB insn. */
11314 reg_src1
= bits (arm_insn_r
->arm_insn
, 16, 19);
11315 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11316 /* SWP insn ?, swaps word. */
11317 if (8 == arm_insn_r
->opcode
)
11319 record_buf_mem
[0] = 4;
11323 /* SWPB insn, swaps only byte. */
11324 record_buf_mem
[0] = 1;
11326 record_buf_mem
[1] = u_regval
[0];
11327 arm_insn_r
->mem_rec_count
= 1;
11328 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11329 arm_insn_r
->reg_rec_count
= 1;
11331 else if (3 == arm_insn_r
->decode
&& 0x12 == opcode1
11332 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
11334 /* Handle BLX, branch and link/exchange. */
11335 if (9 == arm_insn_r
->opcode
)
11337 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
11338 and R14 stores the return address. */
11339 record_buf
[0] = ARM_PS_REGNUM
;
11340 record_buf
[1] = ARM_LR_REGNUM
;
11341 arm_insn_r
->reg_rec_count
= 2;
11344 else if (7 == arm_insn_r
->decode
&& 0x12 == opcode1
)
11346 /* Handle enhanced software breakpoint insn, BKPT. */
11347 /* CPSR is changed to be executed in ARM state, disabling normal
11348 interrupts, entering abort mode. */
11349 /* According to high vector configuration PC is set. */
11350 /* user hit breakpoint and type reverse, in
11351 that case, we need to go back with previous CPSR and
11352 Program Counter. */
11353 record_buf
[0] = ARM_PS_REGNUM
;
11354 record_buf
[1] = ARM_LR_REGNUM
;
11355 arm_insn_r
->reg_rec_count
= 2;
11357 /* Save SPSR also; how? */
11358 printf_unfiltered (_("Process record does not support instruction "
11359 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11360 paddress (arm_insn_r
->gdbarch
,
11361 arm_insn_r
->this_addr
));
11364 else if (11 == arm_insn_r
->decode
11365 && !bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11367 /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
11369 /* Handle str(x) insn */
11370 arm_record_strx(arm_insn_r
, &record_buf
[0], &record_buf_mem
[0],
11373 else if (1 == arm_insn_r
->decode
&& 0x12 == opcode1
11374 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 12, 1))
11376 /* Handle BX, branch and link/exchange. */
11377 /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
11378 record_buf
[0] = ARM_PS_REGNUM
;
11379 arm_insn_r
->reg_rec_count
= 1;
11381 else if (1 == arm_insn_r
->decode
&& 0x16 == opcode1
11382 && sbo_sbz (arm_insn_r
->arm_insn
, 9, 4, 1)
11383 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1))
11385 /* Count leading zeros: CLZ. */
11386 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11387 arm_insn_r
->reg_rec_count
= 1;
11389 else if (!bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
)
11390 && (8 == arm_insn_r
->opcode
|| 10 == arm_insn_r
->opcode
)
11391 && sbo_sbz (arm_insn_r
->arm_insn
, 17, 4, 1)
11392 && sbo_sbz (arm_insn_r
->arm_insn
, 1, 12, 0)
11395 /* Handle MRS insn. */
11396 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11397 arm_insn_r
->reg_rec_count
= 1;
11399 else if (arm_insn_r
->opcode
<= 15)
11401 /* Normal data processing insns. */
11402 /* Out of 11 shifter operands mode, all the insn modifies destination
11403 register, which is specified by 13-16 decode. */
11404 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11405 record_buf
[1] = ARM_PS_REGNUM
;
11406 arm_insn_r
->reg_rec_count
= 2;
11413 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11414 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11418 /* Handling opcode 001 insns. */
11421 arm_record_data_proc_imm (insn_decode_record
*arm_insn_r
)
11423 uint32_t record_buf
[8], record_buf_mem
[8];
11425 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11426 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11428 if ((9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
)
11429 && 2 == bits (arm_insn_r
->arm_insn
, 20, 21)
11430 && sbo_sbz (arm_insn_r
->arm_insn
, 13, 4, 1)
11433 /* Handle MSR insn. */
11434 if (9 == arm_insn_r
->opcode
)
11436 /* CSPR is going to be changed. */
11437 record_buf
[0] = ARM_PS_REGNUM
;
11438 arm_insn_r
->reg_rec_count
= 1;
11442 /* SPSR is going to be changed. */
11445 else if (arm_insn_r
->opcode
<= 15)
11447 /* Normal data processing insns. */
11448 /* Out of 11 shifter operands mode, all the insn modifies destination
11449 register, which is specified by 13-16 decode. */
11450 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11451 record_buf
[1] = ARM_PS_REGNUM
;
11452 arm_insn_r
->reg_rec_count
= 2;
11459 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11460 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11464 /* Handle ARM mode instructions with opcode 010. */
11467 arm_record_ld_st_imm_offset (insn_decode_record
*arm_insn_r
)
11469 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11471 uint32_t reg_base
, reg_dest
;
11472 uint32_t offset_12
, tgt_mem_addr
;
11473 uint32_t record_buf
[8], record_buf_mem
[8];
11474 unsigned char wback
;
11477 /* Calculate wback. */
11478 wback
= (bit (arm_insn_r
->arm_insn
, 24) == 0)
11479 || (bit (arm_insn_r
->arm_insn
, 21) == 1);
11481 arm_insn_r
->reg_rec_count
= 0;
11482 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
11484 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11486 /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT
11489 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11490 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_dest
;
11492 /* The LDR instruction is capable of doing branching. If MOV LR, PC
11493 preceeds a LDR instruction having R15 as reg_base, it
11494 emulates a branch and link instruction, and hence we need to save
11495 CPSR and PC as well. */
11496 if (ARM_PC_REGNUM
== reg_dest
)
11497 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
11499 /* If wback is true, also save the base register, which is going to be
11502 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11506 /* STR (immediate), STRB (immediate), STRBT and STRT. */
11508 offset_12
= bits (arm_insn_r
->arm_insn
, 0, 11);
11509 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
11511 /* Handle bit U. */
11512 if (bit (arm_insn_r
->arm_insn
, 23))
11514 /* U == 1: Add the offset. */
11515 tgt_mem_addr
= (uint32_t) u_regval
+ offset_12
;
11519 /* U == 0: subtract the offset. */
11520 tgt_mem_addr
= (uint32_t) u_regval
- offset_12
;
11523 /* Bit 22 tells us whether the store instruction writes 1 byte or 4
11525 if (bit (arm_insn_r
->arm_insn
, 22))
11527 /* STRB and STRBT: 1 byte. */
11528 record_buf_mem
[0] = 1;
11532 /* STR and STRT: 4 bytes. */
11533 record_buf_mem
[0] = 4;
11536 /* Handle bit P. */
11537 if (bit (arm_insn_r
->arm_insn
, 24))
11538 record_buf_mem
[1] = tgt_mem_addr
;
11540 record_buf_mem
[1] = (uint32_t) u_regval
;
11542 arm_insn_r
->mem_rec_count
= 1;
11544 /* If wback is true, also save the base register, which is going to be
11547 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11550 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11551 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11555 /* Handling opcode 011 insns. */
11558 arm_record_ld_st_reg_offset (insn_decode_record
*arm_insn_r
)
11560 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11562 uint32_t shift_imm
= 0;
11563 uint32_t reg_src1
= 0, reg_src2
= 0, reg_dest
= 0;
11564 uint32_t offset_12
= 0, tgt_mem_addr
= 0;
11565 uint32_t record_buf
[8], record_buf_mem
[8];
11568 ULONGEST u_regval
[2];
11570 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 21, 24);
11571 arm_insn_r
->decode
= bits (arm_insn_r
->arm_insn
, 4, 7);
11573 /* Handle enhanced store insns and LDRD DSP insn,
11574 order begins according to addressing modes for store insns
11578 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11580 reg_dest
= bits (arm_insn_r
->arm_insn
, 12, 15);
11581 /* LDR insn has a capability to do branching, if
11582 MOV LR, PC is precedded by LDR insn having Rn as R15
11583 in that case, it emulates branch and link insn, and hence we
11584 need to save CSPR and PC as well. */
11585 if (15 != reg_dest
)
11587 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
11588 arm_insn_r
->reg_rec_count
= 1;
11592 record_buf
[0] = reg_dest
;
11593 record_buf
[1] = ARM_PS_REGNUM
;
11594 arm_insn_r
->reg_rec_count
= 2;
11599 if (! bits (arm_insn_r
->arm_insn
, 4, 11))
11601 /* Store insn, register offset and register pre-indexed,
11602 register post-indexed. */
11604 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
11606 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11607 regcache_raw_read_unsigned (reg_cache
, reg_src1
11609 regcache_raw_read_unsigned (reg_cache
, reg_src2
11611 if (15 == reg_src2
)
11613 /* If R15 was used as Rn, hence current PC+8. */
11614 /* Pre-indexed mode doesnt reach here ; illegal insn. */
11615 u_regval
[0] = u_regval
[0] + 8;
11617 /* Calculate target store address, Rn +/- Rm, register offset. */
11619 if (bit (arm_insn_r
->arm_insn
, 23))
11621 tgt_mem_addr
= u_regval
[0] + u_regval
[1];
11625 tgt_mem_addr
= u_regval
[1] - u_regval
[0];
11628 switch (arm_insn_r
->opcode
)
11642 record_buf_mem
[0] = 4;
11657 record_buf_mem
[0] = 1;
11661 gdb_assert_not_reached ("no decoding pattern found");
11664 record_buf_mem
[1] = tgt_mem_addr
;
11665 arm_insn_r
->mem_rec_count
= 1;
11667 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
11668 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
11669 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
11670 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
11671 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
11672 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
11675 /* Rn is going to be changed in pre-indexed mode and
11676 post-indexed mode as well. */
11677 record_buf
[0] = reg_src2
;
11678 arm_insn_r
->reg_rec_count
= 1;
11683 /* Store insn, scaled register offset; scaled pre-indexed. */
11684 offset_12
= bits (arm_insn_r
->arm_insn
, 5, 6);
11686 reg_src1
= bits (arm_insn_r
->arm_insn
, 0, 3);
11688 reg_src2
= bits (arm_insn_r
->arm_insn
, 16, 19);
11689 /* Get shift_imm. */
11690 shift_imm
= bits (arm_insn_r
->arm_insn
, 7, 11);
11691 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
11692 regcache_raw_read_signed (reg_cache
, reg_src1
, &s_word
);
11693 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11694 /* Offset_12 used as shift. */
11698 /* Offset_12 used as index. */
11699 offset_12
= u_regval
[0] << shift_imm
;
11703 offset_12
= (!shift_imm
)?0:u_regval
[0] >> shift_imm
;
11709 if (bit (u_regval
[0], 31))
11711 offset_12
= 0xFFFFFFFF;
11720 /* This is arithmetic shift. */
11721 offset_12
= s_word
>> shift_imm
;
11728 regcache_raw_read_unsigned (reg_cache
, ARM_PS_REGNUM
,
11730 /* Get C flag value and shift it by 31. */
11731 offset_12
= (((bit (u_regval
[1], 29)) << 31) \
11732 | (u_regval
[0]) >> 1);
11736 offset_12
= (u_regval
[0] >> shift_imm
) \
11738 (sizeof(uint32_t) - shift_imm
));
11743 gdb_assert_not_reached ("no decoding pattern found");
11747 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
11749 if (bit (arm_insn_r
->arm_insn
, 23))
11751 tgt_mem_addr
= u_regval
[1] + offset_12
;
11755 tgt_mem_addr
= u_regval
[1] - offset_12
;
11758 switch (arm_insn_r
->opcode
)
11772 record_buf_mem
[0] = 4;
11787 record_buf_mem
[0] = 1;
11791 gdb_assert_not_reached ("no decoding pattern found");
11794 record_buf_mem
[1] = tgt_mem_addr
;
11795 arm_insn_r
->mem_rec_count
= 1;
11797 if (9 == arm_insn_r
->opcode
|| 11 == arm_insn_r
->opcode
11798 || 13 == arm_insn_r
->opcode
|| 15 == arm_insn_r
->opcode
11799 || 0 == arm_insn_r
->opcode
|| 2 == arm_insn_r
->opcode
11800 || 4 == arm_insn_r
->opcode
|| 6 == arm_insn_r
->opcode
11801 || 1 == arm_insn_r
->opcode
|| 3 == arm_insn_r
->opcode
11802 || 5 == arm_insn_r
->opcode
|| 7 == arm_insn_r
->opcode
11805 /* Rn is going to be changed in register scaled pre-indexed
11806 mode,and scaled post indexed mode. */
11807 record_buf
[0] = reg_src2
;
11808 arm_insn_r
->reg_rec_count
= 1;
11813 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11814 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11818 /* Handle ARM mode instructions with opcode 100. */
11821 arm_record_ld_st_multiple (insn_decode_record
*arm_insn_r
)
11823 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
11824 uint32_t register_count
= 0, register_bits
;
11825 uint32_t reg_base
, addr_mode
;
11826 uint32_t record_buf
[24], record_buf_mem
[48];
11830 /* Fetch the list of registers. */
11831 register_bits
= bits (arm_insn_r
->arm_insn
, 0, 15);
11832 arm_insn_r
->reg_rec_count
= 0;
11834 /* Fetch the base register that contains the address we are loading data
11836 reg_base
= bits (arm_insn_r
->arm_insn
, 16, 19);
11838 /* Calculate wback. */
11839 wback
= (bit (arm_insn_r
->arm_insn
, 21) == 1);
11841 if (bit (arm_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
11843 /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */
11845 /* Find out which registers are going to be loaded from memory. */
11846 while (register_bits
)
11848 if (register_bits
& 0x00000001)
11849 record_buf
[arm_insn_r
->reg_rec_count
++] = register_count
;
11850 register_bits
= register_bits
>> 1;
11855 /* If wback is true, also save the base register, which is going to be
11858 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11860 /* Save the CPSR register. */
11861 record_buf
[arm_insn_r
->reg_rec_count
++] = ARM_PS_REGNUM
;
11865 /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */
11867 addr_mode
= bits (arm_insn_r
->arm_insn
, 23, 24);
11869 regcache_raw_read_unsigned (reg_cache
, reg_base
, &u_regval
);
11871 /* Find out how many registers are going to be stored to memory. */
11872 while (register_bits
)
11874 if (register_bits
& 0x00000001)
11876 register_bits
= register_bits
>> 1;
11881 /* STMDA (STMED): Decrement after. */
11883 record_buf_mem
[1] = (uint32_t) u_regval
11884 - register_count
* INT_REGISTER_SIZE
+ 4;
11886 /* STM (STMIA, STMEA): Increment after. */
11888 record_buf_mem
[1] = (uint32_t) u_regval
;
11890 /* STMDB (STMFD): Decrement before. */
11892 record_buf_mem
[1] = (uint32_t) u_regval
11893 - register_count
* INT_REGISTER_SIZE
;
11895 /* STMIB (STMFA): Increment before. */
11897 record_buf_mem
[1] = (uint32_t) u_regval
+ INT_REGISTER_SIZE
;
11900 gdb_assert_not_reached ("no decoding pattern found");
11904 record_buf_mem
[0] = register_count
* INT_REGISTER_SIZE
;
11905 arm_insn_r
->mem_rec_count
= 1;
11907 /* If wback is true, also save the base register, which is going to be
11910 record_buf
[arm_insn_r
->reg_rec_count
++] = reg_base
;
11913 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11914 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
11918 /* Handling opcode 101 insns. */
11921 arm_record_b_bl (insn_decode_record
*arm_insn_r
)
11923 uint32_t record_buf
[8];
11925 /* Handle B, BL, BLX(1) insns. */
11926 /* B simply branches so we do nothing here. */
11927 /* Note: BLX(1) doesnt fall here but instead it falls into
11928 extension space. */
11929 if (bit (arm_insn_r
->arm_insn
, 24))
11931 record_buf
[0] = ARM_LR_REGNUM
;
11932 arm_insn_r
->reg_rec_count
= 1;
11935 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
11940 /* Handling opcode 110 insns. */
11943 arm_record_unsupported_insn (insn_decode_record
*arm_insn_r
)
11945 printf_unfiltered (_("Process record does not support instruction "
11946 "0x%0x at address %s.\n"),arm_insn_r
->arm_insn
,
11947 paddress (arm_insn_r
->gdbarch
, arm_insn_r
->this_addr
));
11952 /* Record handler for vector data transfer instructions. */
11955 arm_record_vdata_transfer_insn (insn_decode_record
*arm_insn_r
)
11957 uint32_t bits_a
, bit_c
, bit_l
, reg_t
, reg_v
;
11958 uint32_t record_buf
[4];
11960 const int num_regs
= gdbarch_num_regs (arm_insn_r
->gdbarch
);
11961 reg_t
= bits (arm_insn_r
->arm_insn
, 12, 15);
11962 reg_v
= bits (arm_insn_r
->arm_insn
, 21, 23);
11963 bits_a
= bits (arm_insn_r
->arm_insn
, 21, 23);
11964 bit_l
= bit (arm_insn_r
->arm_insn
, 20);
11965 bit_c
= bit (arm_insn_r
->arm_insn
, 8);
11967 /* Handle VMOV instruction. */
11968 if (bit_l
&& bit_c
)
11970 record_buf
[0] = reg_t
;
11971 arm_insn_r
->reg_rec_count
= 1;
11973 else if (bit_l
&& !bit_c
)
11975 /* Handle VMOV instruction. */
11976 if (bits_a
== 0x00)
11978 if (bit (arm_insn_r
->arm_insn
, 20))
11979 record_buf
[0] = reg_t
;
11981 record_buf
[0] = num_regs
+ (bit (arm_insn_r
->arm_insn
, 7) |
11984 arm_insn_r
->reg_rec_count
= 1;
11986 /* Handle VMRS instruction. */
11987 else if (bits_a
== 0x07)
11990 reg_t
= ARM_PS_REGNUM
;
11992 record_buf
[0] = reg_t
;
11993 arm_insn_r
->reg_rec_count
= 1;
11996 else if (!bit_l
&& !bit_c
)
11998 /* Handle VMOV instruction. */
11999 if (bits_a
== 0x00)
12001 if (bit (arm_insn_r
->arm_insn
, 20))
12002 record_buf
[0] = reg_t
;
12004 record_buf
[0] = num_regs
+ (bit (arm_insn_r
->arm_insn
, 7) |
12007 arm_insn_r
->reg_rec_count
= 1;
12009 /* Handle VMSR instruction. */
12010 else if (bits_a
== 0x07)
12012 record_buf
[0] = ARM_FPSCR_REGNUM
;
12013 arm_insn_r
->reg_rec_count
= 1;
12016 else if (!bit_l
&& bit_c
)
12018 /* Handle VMOV instruction. */
12019 if (!(bits_a
& 0x04))
12021 record_buf
[0] = (reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4))
12023 arm_insn_r
->reg_rec_count
= 1;
12025 /* Handle VDUP instruction. */
12028 if (bit (arm_insn_r
->arm_insn
, 21))
12030 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
12031 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
12032 record_buf
[1] = reg_v
+ ARM_D0_REGNUM
+ 1;
12033 arm_insn_r
->reg_rec_count
= 2;
12037 reg_v
= reg_v
| (bit (arm_insn_r
->arm_insn
, 7) << 4);
12038 record_buf
[0] = reg_v
+ ARM_D0_REGNUM
;
12039 arm_insn_r
->reg_rec_count
= 1;
12044 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
12048 /* Record handler for extension register load/store instructions. */
12051 arm_record_exreg_ld_st_insn (insn_decode_record
*arm_insn_r
)
12053 uint32_t opcode
, single_reg
;
12054 uint8_t op_vldm_vstm
;
12055 uint32_t record_buf
[8], record_buf_mem
[128];
12056 ULONGEST u_regval
= 0;
12058 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
12059 const int num_regs
= gdbarch_num_regs (arm_insn_r
->gdbarch
);
12061 opcode
= bits (arm_insn_r
->arm_insn
, 20, 24);
12062 single_reg
= bit (arm_insn_r
->arm_insn
, 8);
12063 op_vldm_vstm
= opcode
& 0x1b;
12065 /* Handle VMOV instructions. */
12066 if ((opcode
& 0x1e) == 0x04)
12068 if (bit (arm_insn_r
->arm_insn
, 4))
12070 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
12071 record_buf
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
12072 arm_insn_r
->reg_rec_count
= 2;
12076 uint8_t reg_m
= (bits (arm_insn_r
->arm_insn
, 0, 3) << 1)
12077 | bit (arm_insn_r
->arm_insn
, 5);
12081 record_buf
[0] = num_regs
+ reg_m
;
12082 record_buf
[1] = num_regs
+ reg_m
+ 1;
12083 arm_insn_r
->reg_rec_count
= 2;
12087 record_buf
[0] = reg_m
+ ARM_D0_REGNUM
;
12088 arm_insn_r
->reg_rec_count
= 1;
12092 /* Handle VSTM and VPUSH instructions. */
12093 else if (op_vldm_vstm
== 0x08 || op_vldm_vstm
== 0x0a
12094 || op_vldm_vstm
== 0x12)
12096 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
12097 uint32_t memory_index
= 0;
12099 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
12100 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12101 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
12102 imm_off32
= imm_off8
<< 24;
12103 memory_count
= imm_off8
;
12105 if (bit (arm_insn_r
->arm_insn
, 23))
12106 start_address
= u_regval
;
12108 start_address
= u_regval
- imm_off32
;
12110 if (bit (arm_insn_r
->arm_insn
, 21))
12112 record_buf
[0] = reg_rn
;
12113 arm_insn_r
->reg_rec_count
= 1;
12116 while (memory_count
> 0)
12120 record_buf_mem
[memory_index
] = start_address
;
12121 record_buf_mem
[memory_index
+ 1] = 4;
12122 start_address
= start_address
+ 4;
12123 memory_index
= memory_index
+ 2;
12127 record_buf_mem
[memory_index
] = start_address
;
12128 record_buf_mem
[memory_index
+ 1] = 4;
12129 record_buf_mem
[memory_index
+ 2] = start_address
+ 4;
12130 record_buf_mem
[memory_index
+ 3] = 4;
12131 start_address
= start_address
+ 8;
12132 memory_index
= memory_index
+ 4;
12136 arm_insn_r
->mem_rec_count
= (memory_index
>> 1);
12138 /* Handle VLDM instructions. */
12139 else if (op_vldm_vstm
== 0x09 || op_vldm_vstm
== 0x0b
12140 || op_vldm_vstm
== 0x13)
12142 uint32_t reg_count
, reg_vd
;
12143 uint32_t reg_index
= 0;
12145 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
12146 reg_count
= bits (arm_insn_r
->arm_insn
, 0, 7);
12149 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
12151 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
12153 if (bit (arm_insn_r
->arm_insn
, 21))
12154 record_buf
[reg_index
++] = bits (arm_insn_r
->arm_insn
, 16, 19);
12156 while (reg_count
> 0)
12159 record_buf
[reg_index
++] = num_regs
+ reg_vd
+ reg_count
- 1;
12161 record_buf
[reg_index
++] = ARM_D0_REGNUM
+ reg_vd
+ reg_count
- 1;
12165 arm_insn_r
->reg_rec_count
= reg_index
;
12167 /* VSTR Vector store register. */
12168 else if ((opcode
& 0x13) == 0x10)
12170 uint32_t start_address
, reg_rn
, imm_off32
, imm_off8
, memory_count
;
12171 uint32_t memory_index
= 0;
12173 reg_rn
= bits (arm_insn_r
->arm_insn
, 16, 19);
12174 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
12175 imm_off8
= bits (arm_insn_r
->arm_insn
, 0, 7);
12176 imm_off32
= imm_off8
<< 24;
12177 memory_count
= imm_off8
;
12179 if (bit (arm_insn_r
->arm_insn
, 23))
12180 start_address
= u_regval
+ imm_off32
;
12182 start_address
= u_regval
- imm_off32
;
12186 record_buf_mem
[memory_index
] = start_address
;
12187 record_buf_mem
[memory_index
+ 1] = 4;
12188 arm_insn_r
->mem_rec_count
= 1;
12192 record_buf_mem
[memory_index
] = start_address
;
12193 record_buf_mem
[memory_index
+ 1] = 4;
12194 record_buf_mem
[memory_index
+ 2] = start_address
+ 4;
12195 record_buf_mem
[memory_index
+ 3] = 4;
12196 arm_insn_r
->mem_rec_count
= 2;
12199 /* VLDR Vector load register. */
12200 else if ((opcode
& 0x13) == 0x11)
12202 uint32_t reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
12206 reg_vd
= reg_vd
| (bit (arm_insn_r
->arm_insn
, 22) << 4);
12207 record_buf
[0] = ARM_D0_REGNUM
+ reg_vd
;
12211 reg_vd
= (reg_vd
<< 1) | bit (arm_insn_r
->arm_insn
, 22);
12212 record_buf
[0] = num_regs
+ reg_vd
;
12214 arm_insn_r
->reg_rec_count
= 1;
12217 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
12218 MEM_ALLOC (arm_insn_r
->arm_mems
, arm_insn_r
->mem_rec_count
, record_buf_mem
);
12222 /* Record handler for arm/thumb mode VFP data processing instructions. */
12225 arm_record_vfp_data_proc_insn (insn_decode_record
*arm_insn_r
)
12227 uint32_t opc1
, opc2
, opc3
, dp_op_sz
, bit_d
, reg_vd
;
12228 uint32_t record_buf
[4];
12229 enum insn_types
{INSN_T0
, INSN_T1
, INSN_T2
, INSN_T3
, INSN_INV
};
12230 enum insn_types curr_insn_type
= INSN_INV
;
12232 reg_vd
= bits (arm_insn_r
->arm_insn
, 12, 15);
12233 opc1
= bits (arm_insn_r
->arm_insn
, 20, 23);
12234 opc2
= bits (arm_insn_r
->arm_insn
, 16, 19);
12235 opc3
= bits (arm_insn_r
->arm_insn
, 6, 7);
12236 dp_op_sz
= bit (arm_insn_r
->arm_insn
, 8);
12237 bit_d
= bit (arm_insn_r
->arm_insn
, 22);
12238 opc1
= opc1
& 0x04;
12240 /* Handle VMLA, VMLS. */
12243 if (bit (arm_insn_r
->arm_insn
, 10))
12245 if (bit (arm_insn_r
->arm_insn
, 6))
12246 curr_insn_type
= INSN_T0
;
12248 curr_insn_type
= INSN_T1
;
12253 curr_insn_type
= INSN_T1
;
12255 curr_insn_type
= INSN_T2
;
12258 /* Handle VNMLA, VNMLS, VNMUL. */
12259 else if (opc1
== 0x01)
12262 curr_insn_type
= INSN_T1
;
12264 curr_insn_type
= INSN_T2
;
12267 else if (opc1
== 0x02 && !(opc3
& 0x01))
12269 if (bit (arm_insn_r
->arm_insn
, 10))
12271 if (bit (arm_insn_r
->arm_insn
, 6))
12272 curr_insn_type
= INSN_T0
;
12274 curr_insn_type
= INSN_T1
;
12279 curr_insn_type
= INSN_T1
;
12281 curr_insn_type
= INSN_T2
;
12284 /* Handle VADD, VSUB. */
12285 else if (opc1
== 0x03)
12287 if (!bit (arm_insn_r
->arm_insn
, 9))
12289 if (bit (arm_insn_r
->arm_insn
, 6))
12290 curr_insn_type
= INSN_T0
;
12292 curr_insn_type
= INSN_T1
;
12297 curr_insn_type
= INSN_T1
;
12299 curr_insn_type
= INSN_T2
;
12303 else if (opc1
== 0x0b)
12306 curr_insn_type
= INSN_T1
;
12308 curr_insn_type
= INSN_T2
;
12310 /* Handle all other vfp data processing instructions. */
12311 else if (opc1
== 0x0b)
12314 if (!(opc3
& 0x01) || (opc2
== 0x00 && opc3
== 0x01))
12316 if (bit (arm_insn_r
->arm_insn
, 4))
12318 if (bit (arm_insn_r
->arm_insn
, 6))
12319 curr_insn_type
= INSN_T0
;
12321 curr_insn_type
= INSN_T1
;
12326 curr_insn_type
= INSN_T1
;
12328 curr_insn_type
= INSN_T2
;
12331 /* Handle VNEG and VABS. */
12332 else if ((opc2
== 0x01 && opc3
== 0x01)
12333 || (opc2
== 0x00 && opc3
== 0x03))
12335 if (!bit (arm_insn_r
->arm_insn
, 11))
12337 if (bit (arm_insn_r
->arm_insn
, 6))
12338 curr_insn_type
= INSN_T0
;
12340 curr_insn_type
= INSN_T1
;
12345 curr_insn_type
= INSN_T1
;
12347 curr_insn_type
= INSN_T2
;
12350 /* Handle VSQRT. */
12351 else if (opc2
== 0x01 && opc3
== 0x03)
12354 curr_insn_type
= INSN_T1
;
12356 curr_insn_type
= INSN_T2
;
12359 else if (opc2
== 0x07 && opc3
== 0x03)
12362 curr_insn_type
= INSN_T1
;
12364 curr_insn_type
= INSN_T2
;
12366 else if (opc3
& 0x01)
12369 if ((opc2
== 0x08) || (opc2
& 0x0e) == 0x0c)
12371 if (!bit (arm_insn_r
->arm_insn
, 18))
12372 curr_insn_type
= INSN_T2
;
12376 curr_insn_type
= INSN_T1
;
12378 curr_insn_type
= INSN_T2
;
12382 else if ((opc2
& 0x0e) == 0x0a || (opc2
& 0x0e) == 0x0e)
12385 curr_insn_type
= INSN_T1
;
12387 curr_insn_type
= INSN_T2
;
12389 /* Handle VCVTB, VCVTT. */
12390 else if ((opc2
& 0x0e) == 0x02)
12391 curr_insn_type
= INSN_T2
;
12392 /* Handle VCMP, VCMPE. */
12393 else if ((opc2
& 0x0e) == 0x04)
12394 curr_insn_type
= INSN_T3
;
12398 switch (curr_insn_type
)
12401 reg_vd
= reg_vd
| (bit_d
<< 4);
12402 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
12403 record_buf
[1] = reg_vd
+ ARM_D0_REGNUM
+ 1;
12404 arm_insn_r
->reg_rec_count
= 2;
12408 reg_vd
= reg_vd
| (bit_d
<< 4);
12409 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
12410 arm_insn_r
->reg_rec_count
= 1;
12414 reg_vd
= (reg_vd
<< 1) | bit_d
;
12415 record_buf
[0] = reg_vd
+ ARM_D0_REGNUM
;
12416 arm_insn_r
->reg_rec_count
= 1;
12420 record_buf
[0] = ARM_FPSCR_REGNUM
;
12421 arm_insn_r
->reg_rec_count
= 1;
12425 gdb_assert_not_reached ("no decoding pattern found");
12429 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, record_buf
);
12433 /* Handling opcode 110 insns. */
12436 arm_record_asimd_vfp_coproc (insn_decode_record
*arm_insn_r
)
12438 uint32_t op
, op1
, op1_sbit
, op1_ebit
, coproc
;
12440 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
12441 op1
= bits (arm_insn_r
->arm_insn
, 20, 25);
12442 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
12444 if ((coproc
& 0x0e) == 0x0a)
12446 /* Handle extension register ld/st instructions. */
12448 return arm_record_exreg_ld_st_insn (arm_insn_r
);
12450 /* 64-bit transfers between arm core and extension registers. */
12451 if ((op1
& 0x3e) == 0x04)
12452 return arm_record_exreg_ld_st_insn (arm_insn_r
);
12456 /* Handle coprocessor ld/st instructions. */
12461 return arm_record_unsupported_insn (arm_insn_r
);
12464 return arm_record_unsupported_insn (arm_insn_r
);
12467 /* Move to coprocessor from two arm core registers. */
12469 return arm_record_unsupported_insn (arm_insn_r
);
12471 /* Move to two arm core registers from coprocessor. */
12476 reg_t
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
12477 reg_t
[1] = bits (arm_insn_r
->arm_insn
, 16, 19);
12478 arm_insn_r
->reg_rec_count
= 2;
12480 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
, reg_t
);
12484 return arm_record_unsupported_insn (arm_insn_r
);
12487 /* Handling opcode 111 insns. */
12490 arm_record_coproc_data_proc (insn_decode_record
*arm_insn_r
)
12492 uint32_t op
, op1_sbit
, op1_ebit
, coproc
;
12493 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arm_insn_r
->gdbarch
);
12494 struct regcache
*reg_cache
= arm_insn_r
->regcache
;
12495 ULONGEST u_regval
= 0;
12497 arm_insn_r
->opcode
= bits (arm_insn_r
->arm_insn
, 24, 27);
12498 coproc
= bits (arm_insn_r
->arm_insn
, 8, 11);
12499 op1_sbit
= bit (arm_insn_r
->arm_insn
, 24);
12500 op1_ebit
= bit (arm_insn_r
->arm_insn
, 20);
12501 op
= bit (arm_insn_r
->arm_insn
, 4);
12503 /* Handle arm SWI/SVC system call instructions. */
12506 if (tdep
->arm_syscall_record
!= NULL
)
12508 ULONGEST svc_operand
, svc_number
;
12510 svc_operand
= (0x00ffffff & arm_insn_r
->arm_insn
);
12512 if (svc_operand
) /* OABI. */
12513 svc_number
= svc_operand
- 0x900000;
12515 regcache_raw_read_unsigned (reg_cache
, 7, &svc_number
);
12517 return tdep
->arm_syscall_record (reg_cache
, svc_number
);
12521 printf_unfiltered (_("no syscall record support\n"));
12526 if ((coproc
& 0x0e) == 0x0a)
12528 /* VFP data-processing instructions. */
12529 if (!op1_sbit
&& !op
)
12530 return arm_record_vfp_data_proc_insn (arm_insn_r
);
12532 /* Advanced SIMD, VFP instructions. */
12533 if (!op1_sbit
&& op
)
12534 return arm_record_vdata_transfer_insn (arm_insn_r
);
12538 /* Coprocessor data operations. */
12539 if (!op1_sbit
&& !op
)
12540 return arm_record_unsupported_insn (arm_insn_r
);
12542 /* Move to Coprocessor from ARM core register. */
12543 if (!op1_sbit
&& !op1_ebit
&& op
)
12544 return arm_record_unsupported_insn (arm_insn_r
);
12546 /* Move to arm core register from coprocessor. */
12547 if (!op1_sbit
&& op1_ebit
&& op
)
12549 uint32_t record_buf
[1];
12551 record_buf
[0] = bits (arm_insn_r
->arm_insn
, 12, 15);
12552 if (record_buf
[0] == 15)
12553 record_buf
[0] = ARM_PS_REGNUM
;
12555 arm_insn_r
->reg_rec_count
= 1;
12556 REG_ALLOC (arm_insn_r
->arm_regs
, arm_insn_r
->reg_rec_count
,
12562 return arm_record_unsupported_insn (arm_insn_r
);
12565 /* Handling opcode 000 insns. */
12568 thumb_record_shift_add_sub (insn_decode_record
*thumb_insn_r
)
12570 uint32_t record_buf
[8];
12571 uint32_t reg_src1
= 0;
12573 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12575 record_buf
[0] = ARM_PS_REGNUM
;
12576 record_buf
[1] = reg_src1
;
12577 thumb_insn_r
->reg_rec_count
= 2;
12579 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12585 /* Handling opcode 001 insns. */
12588 thumb_record_add_sub_cmp_mov (insn_decode_record
*thumb_insn_r
)
12590 uint32_t record_buf
[8];
12591 uint32_t reg_src1
= 0;
12593 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12595 record_buf
[0] = ARM_PS_REGNUM
;
12596 record_buf
[1] = reg_src1
;
12597 thumb_insn_r
->reg_rec_count
= 2;
12599 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12604 /* Handling opcode 010 insns. */
12607 thumb_record_ld_st_reg_offset (insn_decode_record
*thumb_insn_r
)
12609 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12610 uint32_t record_buf
[8], record_buf_mem
[8];
12612 uint32_t reg_src1
= 0, reg_src2
= 0;
12613 uint32_t opcode1
= 0, opcode2
= 0, opcode3
= 0;
12615 ULONGEST u_regval
[2] = {0};
12617 opcode1
= bits (thumb_insn_r
->arm_insn
, 10, 12);
12619 if (bit (thumb_insn_r
->arm_insn
, 12))
12621 /* Handle load/store register offset. */
12622 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 10);
12623 if (opcode2
>= 12 && opcode2
<= 15)
12625 /* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
12626 reg_src1
= bits (thumb_insn_r
->arm_insn
,0, 2);
12627 record_buf
[0] = reg_src1
;
12628 thumb_insn_r
->reg_rec_count
= 1;
12630 else if (opcode2
>= 8 && opcode2
<= 10)
12632 /* STR(2), STRB(2), STRH(2) . */
12633 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12634 reg_src2
= bits (thumb_insn_r
->arm_insn
, 6, 8);
12635 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
[0]);
12636 regcache_raw_read_unsigned (reg_cache
, reg_src2
, &u_regval
[1]);
12638 record_buf_mem
[0] = 4; /* STR (2). */
12639 else if (10 == opcode2
)
12640 record_buf_mem
[0] = 1; /* STRB (2). */
12641 else if (9 == opcode2
)
12642 record_buf_mem
[0] = 2; /* STRH (2). */
12643 record_buf_mem
[1] = u_regval
[0] + u_regval
[1];
12644 thumb_insn_r
->mem_rec_count
= 1;
12647 else if (bit (thumb_insn_r
->arm_insn
, 11))
12649 /* Handle load from literal pool. */
12651 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12652 record_buf
[0] = reg_src1
;
12653 thumb_insn_r
->reg_rec_count
= 1;
12657 opcode2
= bits (thumb_insn_r
->arm_insn
, 8, 9);
12658 opcode3
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12659 if ((3 == opcode2
) && (!opcode3
))
12661 /* Branch with exchange. */
12662 record_buf
[0] = ARM_PS_REGNUM
;
12663 thumb_insn_r
->reg_rec_count
= 1;
12667 /* Format 8; special data processing insns. */
12668 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12669 record_buf
[0] = ARM_PS_REGNUM
;
12670 record_buf
[1] = reg_src1
;
12671 thumb_insn_r
->reg_rec_count
= 2;
12676 /* Format 5; data processing insns. */
12677 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12678 if (bit (thumb_insn_r
->arm_insn
, 7))
12680 reg_src1
= reg_src1
+ 8;
12682 record_buf
[0] = ARM_PS_REGNUM
;
12683 record_buf
[1] = reg_src1
;
12684 thumb_insn_r
->reg_rec_count
= 2;
12687 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12688 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12694 /* Handling opcode 001 insns. */
12697 thumb_record_ld_st_imm_offset (insn_decode_record
*thumb_insn_r
)
12699 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12700 uint32_t record_buf
[8], record_buf_mem
[8];
12702 uint32_t reg_src1
= 0;
12703 uint32_t opcode
= 0, immed_5
= 0;
12705 ULONGEST u_regval
= 0;
12707 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12712 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12713 record_buf
[0] = reg_src1
;
12714 thumb_insn_r
->reg_rec_count
= 1;
12719 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12720 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
12721 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12722 record_buf_mem
[0] = 4;
12723 record_buf_mem
[1] = u_regval
+ (immed_5
* 4);
12724 thumb_insn_r
->mem_rec_count
= 1;
12727 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12728 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12734 /* Handling opcode 100 insns. */
12737 thumb_record_ld_st_stack (insn_decode_record
*thumb_insn_r
)
12739 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12740 uint32_t record_buf
[8], record_buf_mem
[8];
12742 uint32_t reg_src1
= 0;
12743 uint32_t opcode
= 0, immed_8
= 0, immed_5
= 0;
12745 ULONGEST u_regval
= 0;
12747 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12752 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12753 record_buf
[0] = reg_src1
;
12754 thumb_insn_r
->reg_rec_count
= 1;
12756 else if (1 == opcode
)
12759 reg_src1
= bits (thumb_insn_r
->arm_insn
, 0, 2);
12760 record_buf
[0] = reg_src1
;
12761 thumb_insn_r
->reg_rec_count
= 1;
12763 else if (2 == opcode
)
12766 immed_8
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12767 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
12768 record_buf_mem
[0] = 4;
12769 record_buf_mem
[1] = u_regval
+ (immed_8
* 4);
12770 thumb_insn_r
->mem_rec_count
= 1;
12772 else if (0 == opcode
)
12775 immed_5
= bits (thumb_insn_r
->arm_insn
, 6, 10);
12776 reg_src1
= bits (thumb_insn_r
->arm_insn
, 3, 5);
12777 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12778 record_buf_mem
[0] = 2;
12779 record_buf_mem
[1] = u_regval
+ (immed_5
* 2);
12780 thumb_insn_r
->mem_rec_count
= 1;
12783 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12784 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12790 /* Handling opcode 101 insns. */
12793 thumb_record_misc (insn_decode_record
*thumb_insn_r
)
12795 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12797 uint32_t opcode
= 0, opcode1
= 0, opcode2
= 0;
12798 uint32_t register_bits
= 0, register_count
= 0;
12799 uint32_t register_list
[8] = {0}, index
= 0, start_address
= 0;
12800 uint32_t record_buf
[24], record_buf_mem
[48];
12803 ULONGEST u_regval
= 0;
12805 opcode
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12806 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12807 opcode2
= bits (thumb_insn_r
->arm_insn
, 9, 12);
12812 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12813 while (register_bits
)
12815 if (register_bits
& 0x00000001)
12816 record_buf
[index
++] = register_count
;
12817 register_bits
= register_bits
>> 1;
12820 record_buf
[index
++] = ARM_PS_REGNUM
;
12821 record_buf
[index
++] = ARM_SP_REGNUM
;
12822 thumb_insn_r
->reg_rec_count
= index
;
12824 else if (10 == opcode2
)
12827 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12828 regcache_raw_read_unsigned (reg_cache
, ARM_SP_REGNUM
, &u_regval
);
12829 while (register_bits
)
12831 if (register_bits
& 0x00000001)
12833 register_bits
= register_bits
>> 1;
12835 start_address
= u_regval
- \
12836 (4 * (bit (thumb_insn_r
->arm_insn
, 8) + register_count
));
12837 thumb_insn_r
->mem_rec_count
= register_count
;
12838 while (register_count
)
12840 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12841 record_buf_mem
[(register_count
* 2) - 2] = 4;
12842 start_address
= start_address
+ 4;
12845 record_buf
[0] = ARM_SP_REGNUM
;
12846 thumb_insn_r
->reg_rec_count
= 1;
12848 else if (0x1E == opcode1
)
12851 /* Handle enhanced software breakpoint insn, BKPT. */
12852 /* CPSR is changed to be executed in ARM state, disabling normal
12853 interrupts, entering abort mode. */
12854 /* According to high vector configuration PC is set. */
12855 /* User hits breakpoint and type reverse, in that case, we need to go back with
12856 previous CPSR and Program Counter. */
12857 record_buf
[0] = ARM_PS_REGNUM
;
12858 record_buf
[1] = ARM_LR_REGNUM
;
12859 thumb_insn_r
->reg_rec_count
= 2;
12860 /* We need to save SPSR value, which is not yet done. */
12861 printf_unfiltered (_("Process record does not support instruction "
12862 "0x%0x at address %s.\n"),
12863 thumb_insn_r
->arm_insn
,
12864 paddress (thumb_insn_r
->gdbarch
,
12865 thumb_insn_r
->this_addr
));
12868 else if ((0 == opcode
) || (1 == opcode
))
12870 /* ADD(5), ADD(6). */
12871 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12872 record_buf
[0] = reg_src1
;
12873 thumb_insn_r
->reg_rec_count
= 1;
12875 else if (2 == opcode
)
12877 /* ADD(7), SUB(4). */
12878 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12879 record_buf
[0] = ARM_SP_REGNUM
;
12880 thumb_insn_r
->reg_rec_count
= 1;
12883 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12884 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12890 /* Handling opcode 110 insns. */
12893 thumb_record_ldm_stm_swi (insn_decode_record
*thumb_insn_r
)
12895 struct gdbarch_tdep
*tdep
= gdbarch_tdep (thumb_insn_r
->gdbarch
);
12896 struct regcache
*reg_cache
= thumb_insn_r
->regcache
;
12898 uint32_t ret
= 0; /* function return value: -1:record failure ; 0:success */
12899 uint32_t reg_src1
= 0;
12900 uint32_t opcode1
= 0, opcode2
= 0, register_bits
= 0, register_count
= 0;
12901 uint32_t register_list
[8] = {0}, index
= 0, start_address
= 0;
12902 uint32_t record_buf
[24], record_buf_mem
[48];
12904 ULONGEST u_regval
= 0;
12906 opcode1
= bits (thumb_insn_r
->arm_insn
, 8, 12);
12907 opcode2
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12913 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12915 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12916 while (register_bits
)
12918 if (register_bits
& 0x00000001)
12919 record_buf
[index
++] = register_count
;
12920 register_bits
= register_bits
>> 1;
12923 record_buf
[index
++] = reg_src1
;
12924 thumb_insn_r
->reg_rec_count
= index
;
12926 else if (0 == opcode2
)
12928 /* It handles both STMIA. */
12929 register_bits
= bits (thumb_insn_r
->arm_insn
, 0, 7);
12931 reg_src1
= bits (thumb_insn_r
->arm_insn
, 8, 10);
12932 regcache_raw_read_unsigned (reg_cache
, reg_src1
, &u_regval
);
12933 while (register_bits
)
12935 if (register_bits
& 0x00000001)
12937 register_bits
= register_bits
>> 1;
12939 start_address
= u_regval
;
12940 thumb_insn_r
->mem_rec_count
= register_count
;
12941 while (register_count
)
12943 record_buf_mem
[(register_count
* 2) - 1] = start_address
;
12944 record_buf_mem
[(register_count
* 2) - 2] = 4;
12945 start_address
= start_address
+ 4;
12949 else if (0x1F == opcode1
)
12951 /* Handle arm syscall insn. */
12952 if (tdep
->arm_syscall_record
!= NULL
)
12954 regcache_raw_read_unsigned (reg_cache
, 7, &u_regval
);
12955 ret
= tdep
->arm_syscall_record (reg_cache
, u_regval
);
12959 printf_unfiltered (_("no syscall record support\n"));
12964 /* B (1), conditional branch is automatically taken care in process_record,
12965 as PC is saved there. */
12967 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
12968 MEM_ALLOC (thumb_insn_r
->arm_mems
, thumb_insn_r
->mem_rec_count
,
12974 /* Handling opcode 111 insns. */
12977 thumb_record_branch (insn_decode_record
*thumb_insn_r
)
12979 uint32_t record_buf
[8];
12980 uint32_t bits_h
= 0;
12982 bits_h
= bits (thumb_insn_r
->arm_insn
, 11, 12);
12984 if (2 == bits_h
|| 3 == bits_h
)
12987 record_buf
[0] = ARM_LR_REGNUM
;
12988 thumb_insn_r
->reg_rec_count
= 1;
12990 else if (1 == bits_h
)
12993 record_buf
[0] = ARM_PS_REGNUM
;
12994 record_buf
[1] = ARM_LR_REGNUM
;
12995 thumb_insn_r
->reg_rec_count
= 2;
12998 /* B(2) is automatically taken care in process_record, as PC is
13001 REG_ALLOC (thumb_insn_r
->arm_regs
, thumb_insn_r
->reg_rec_count
, record_buf
);
13006 /* Handler for thumb2 load/store multiple instructions. */
13009 thumb2_record_ld_st_multiple (insn_decode_record
*thumb2_insn_r
)
13011 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13013 uint32_t reg_rn
, op
;
13014 uint32_t register_bits
= 0, register_count
= 0;
13015 uint32_t index
= 0, start_address
= 0;
13016 uint32_t record_buf
[24], record_buf_mem
[48];
13018 ULONGEST u_regval
= 0;
13020 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13021 op
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
13023 if (0 == op
|| 3 == op
)
13025 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
13027 /* Handle RFE instruction. */
13028 record_buf
[0] = ARM_PS_REGNUM
;
13029 thumb2_insn_r
->reg_rec_count
= 1;
13033 /* Handle SRS instruction after reading banked SP. */
13034 return arm_record_unsupported_insn (thumb2_insn_r
);
13037 else if (1 == op
|| 2 == op
)
13039 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
13041 /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
13042 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
13043 while (register_bits
)
13045 if (register_bits
& 0x00000001)
13046 record_buf
[index
++] = register_count
;
13049 register_bits
= register_bits
>> 1;
13051 record_buf
[index
++] = reg_rn
;
13052 record_buf
[index
++] = ARM_PS_REGNUM
;
13053 thumb2_insn_r
->reg_rec_count
= index
;
13057 /* Handle STM/STMIA/STMEA and STMDB/STMFD. */
13058 register_bits
= bits (thumb2_insn_r
->arm_insn
, 0, 15);
13059 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
13060 while (register_bits
)
13062 if (register_bits
& 0x00000001)
13065 register_bits
= register_bits
>> 1;
13070 /* Start address calculation for LDMDB/LDMEA. */
13071 start_address
= u_regval
;
13075 /* Start address calculation for LDMDB/LDMEA. */
13076 start_address
= u_regval
- register_count
* 4;
13079 thumb2_insn_r
->mem_rec_count
= register_count
;
13080 while (register_count
)
13082 record_buf_mem
[register_count
* 2 - 1] = start_address
;
13083 record_buf_mem
[register_count
* 2 - 2] = 4;
13084 start_address
= start_address
+ 4;
13087 record_buf
[0] = reg_rn
;
13088 record_buf
[1] = ARM_PS_REGNUM
;
13089 thumb2_insn_r
->reg_rec_count
= 2;
13093 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13095 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13097 return ARM_RECORD_SUCCESS
;
13100 /* Handler for thumb2 load/store (dual/exclusive) and table branch
13104 thumb2_record_ld_st_dual_ex_tbb (insn_decode_record
*thumb2_insn_r
)
13106 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13108 uint32_t reg_rd
, reg_rn
, offset_imm
;
13109 uint32_t reg_dest1
, reg_dest2
;
13110 uint32_t address
, offset_addr
;
13111 uint32_t record_buf
[8], record_buf_mem
[8];
13112 uint32_t op1
, op2
, op3
;
13115 ULONGEST u_regval
[2];
13117 op1
= bits (thumb2_insn_r
->arm_insn
, 23, 24);
13118 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 21);
13119 op3
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
13121 if (bit (thumb2_insn_r
->arm_insn
, INSN_S_L_BIT_NUM
))
13123 if(!(1 == op1
&& 1 == op2
&& (0 == op3
|| 1 == op3
)))
13125 reg_dest1
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
13126 record_buf
[0] = reg_dest1
;
13127 record_buf
[1] = ARM_PS_REGNUM
;
13128 thumb2_insn_r
->reg_rec_count
= 2;
13131 if (3 == op2
|| (op1
& 2) || (1 == op1
&& 1 == op2
&& 7 == op3
))
13133 reg_dest2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13134 record_buf
[2] = reg_dest2
;
13135 thumb2_insn_r
->reg_rec_count
= 3;
13140 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13141 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
13143 if (0 == op1
&& 0 == op2
)
13145 /* Handle STREX. */
13146 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
13147 address
= u_regval
[0] + (offset_imm
* 4);
13148 record_buf_mem
[0] = 4;
13149 record_buf_mem
[1] = address
;
13150 thumb2_insn_r
->mem_rec_count
= 1;
13151 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
13152 record_buf
[0] = reg_rd
;
13153 thumb2_insn_r
->reg_rec_count
= 1;
13155 else if (1 == op1
&& 0 == op2
)
13157 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
13158 record_buf
[0] = reg_rd
;
13159 thumb2_insn_r
->reg_rec_count
= 1;
13160 address
= u_regval
[0];
13161 record_buf_mem
[1] = address
;
13165 /* Handle STREXB. */
13166 record_buf_mem
[0] = 1;
13167 thumb2_insn_r
->mem_rec_count
= 1;
13171 /* Handle STREXH. */
13172 record_buf_mem
[0] = 2 ;
13173 thumb2_insn_r
->mem_rec_count
= 1;
13177 /* Handle STREXD. */
13178 address
= u_regval
[0];
13179 record_buf_mem
[0] = 4;
13180 record_buf_mem
[2] = 4;
13181 record_buf_mem
[3] = address
+ 4;
13182 thumb2_insn_r
->mem_rec_count
= 2;
13187 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
13189 if (bit (thumb2_insn_r
->arm_insn
, 24))
13191 if (bit (thumb2_insn_r
->arm_insn
, 23))
13192 offset_addr
= u_regval
[0] + (offset_imm
* 4);
13194 offset_addr
= u_regval
[0] - (offset_imm
* 4);
13196 address
= offset_addr
;
13199 address
= u_regval
[0];
13201 record_buf_mem
[0] = 4;
13202 record_buf_mem
[1] = address
;
13203 record_buf_mem
[2] = 4;
13204 record_buf_mem
[3] = address
+ 4;
13205 thumb2_insn_r
->mem_rec_count
= 2;
13206 record_buf
[0] = reg_rn
;
13207 thumb2_insn_r
->reg_rec_count
= 1;
13211 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13213 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13215 return ARM_RECORD_SUCCESS
;
13218 /* Handler for thumb2 data processing (shift register and modified immediate)
13222 thumb2_record_data_proc_sreg_mimm (insn_decode_record
*thumb2_insn_r
)
13224 uint32_t reg_rd
, op
;
13225 uint32_t record_buf
[8];
13227 op
= bits (thumb2_insn_r
->arm_insn
, 21, 24);
13228 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13230 if ((0 == op
|| 4 == op
|| 8 == op
|| 13 == op
) && 15 == reg_rd
)
13232 record_buf
[0] = ARM_PS_REGNUM
;
13233 thumb2_insn_r
->reg_rec_count
= 1;
13237 record_buf
[0] = reg_rd
;
13238 record_buf
[1] = ARM_PS_REGNUM
;
13239 thumb2_insn_r
->reg_rec_count
= 2;
13242 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13244 return ARM_RECORD_SUCCESS
;
13247 /* Generic handler for thumb2 instructions which effect destination and PS
13251 thumb2_record_ps_dest_generic (insn_decode_record
*thumb2_insn_r
)
13254 uint32_t record_buf
[8];
13256 reg_rd
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13258 record_buf
[0] = reg_rd
;
13259 record_buf
[1] = ARM_PS_REGNUM
;
13260 thumb2_insn_r
->reg_rec_count
= 2;
13262 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13264 return ARM_RECORD_SUCCESS
;
13267 /* Handler for thumb2 branch and miscellaneous control instructions. */
13270 thumb2_record_branch_misc_cntrl (insn_decode_record
*thumb2_insn_r
)
13272 uint32_t op
, op1
, op2
;
13273 uint32_t record_buf
[8];
13275 op
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
13276 op1
= bits (thumb2_insn_r
->arm_insn
, 12, 14);
13277 op2
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13279 /* Handle MSR insn. */
13280 if (!(op1
& 0x2) && 0x38 == op
)
13284 /* CPSR is going to be changed. */
13285 record_buf
[0] = ARM_PS_REGNUM
;
13286 thumb2_insn_r
->reg_rec_count
= 1;
13290 arm_record_unsupported_insn(thumb2_insn_r
);
13294 else if (4 == (op1
& 0x5) || 5 == (op1
& 0x5))
13297 record_buf
[0] = ARM_PS_REGNUM
;
13298 record_buf
[1] = ARM_LR_REGNUM
;
13299 thumb2_insn_r
->reg_rec_count
= 2;
13302 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13304 return ARM_RECORD_SUCCESS
;
13307 /* Handler for thumb2 store single data item instructions. */
13310 thumb2_record_str_single_data (insn_decode_record
*thumb2_insn_r
)
13312 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13314 uint32_t reg_rn
, reg_rm
, offset_imm
, shift_imm
;
13315 uint32_t address
, offset_addr
;
13316 uint32_t record_buf
[8], record_buf_mem
[8];
13319 ULONGEST u_regval
[2];
13321 op1
= bits (thumb2_insn_r
->arm_insn
, 21, 23);
13322 op2
= bits (thumb2_insn_r
->arm_insn
, 6, 11);
13323 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13324 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
[0]);
13326 if (bit (thumb2_insn_r
->arm_insn
, 23))
13329 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 11);
13330 offset_addr
= u_regval
[0] + offset_imm
;
13331 address
= offset_addr
;
13336 if ((0 == op1
|| 1 == op1
|| 2 == op1
) && !(op2
& 0x20))
13338 /* Handle STRB (register). */
13339 reg_rm
= bits (thumb2_insn_r
->arm_insn
, 0, 3);
13340 regcache_raw_read_unsigned (reg_cache
, reg_rm
, &u_regval
[1]);
13341 shift_imm
= bits (thumb2_insn_r
->arm_insn
, 4, 5);
13342 offset_addr
= u_regval
[1] << shift_imm
;
13343 address
= u_regval
[0] + offset_addr
;
13347 offset_imm
= bits (thumb2_insn_r
->arm_insn
, 0, 7);
13348 if (bit (thumb2_insn_r
->arm_insn
, 10))
13350 if (bit (thumb2_insn_r
->arm_insn
, 9))
13351 offset_addr
= u_regval
[0] + offset_imm
;
13353 offset_addr
= u_regval
[0] - offset_imm
;
13355 address
= offset_addr
;
13358 address
= u_regval
[0];
13364 /* Store byte instructions. */
13367 record_buf_mem
[0] = 1;
13369 /* Store half word instructions. */
13372 record_buf_mem
[0] = 2;
13374 /* Store word instructions. */
13377 record_buf_mem
[0] = 4;
13381 gdb_assert_not_reached ("no decoding pattern found");
13385 record_buf_mem
[1] = address
;
13386 thumb2_insn_r
->mem_rec_count
= 1;
13387 record_buf
[0] = reg_rn
;
13388 thumb2_insn_r
->reg_rec_count
= 1;
13390 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13392 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13394 return ARM_RECORD_SUCCESS
;
13397 /* Handler for thumb2 load memory hints instructions. */
13400 thumb2_record_ld_mem_hints (insn_decode_record
*thumb2_insn_r
)
13402 uint32_t record_buf
[8];
13403 uint32_t reg_rt
, reg_rn
;
13405 reg_rt
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
13406 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13408 if (ARM_PC_REGNUM
!= reg_rt
)
13410 record_buf
[0] = reg_rt
;
13411 record_buf
[1] = reg_rn
;
13412 record_buf
[2] = ARM_PS_REGNUM
;
13413 thumb2_insn_r
->reg_rec_count
= 3;
13415 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13417 return ARM_RECORD_SUCCESS
;
13420 return ARM_RECORD_FAILURE
;
13423 /* Handler for thumb2 load word instructions. */
13426 thumb2_record_ld_word (insn_decode_record
*thumb2_insn_r
)
13428 uint32_t opcode1
= 0, opcode2
= 0;
13429 uint32_t record_buf
[8];
13431 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
13432 record_buf
[1] = ARM_PS_REGNUM
;
13433 thumb2_insn_r
->reg_rec_count
= 2;
13435 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13437 return ARM_RECORD_SUCCESS
;
13440 /* Handler for thumb2 long multiply, long multiply accumulate, and
13441 divide instructions. */
13444 thumb2_record_lmul_lmla_div (insn_decode_record
*thumb2_insn_r
)
13446 uint32_t opcode1
= 0, opcode2
= 0;
13447 uint32_t record_buf
[8];
13448 uint32_t reg_src1
= 0;
13450 opcode1
= bits (thumb2_insn_r
->arm_insn
, 20, 22);
13451 opcode2
= bits (thumb2_insn_r
->arm_insn
, 4, 7);
13453 if (0 == opcode1
|| 2 == opcode1
|| (opcode1
>= 4 && opcode1
<= 6))
13455 /* Handle SMULL, UMULL, SMULAL. */
13456 /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
13457 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
13458 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
13459 record_buf
[2] = ARM_PS_REGNUM
;
13460 thumb2_insn_r
->reg_rec_count
= 3;
13462 else if (1 == opcode1
|| 3 == opcode2
)
13464 /* Handle SDIV and UDIV. */
13465 record_buf
[0] = bits (thumb2_insn_r
->arm_insn
, 16, 19);
13466 record_buf
[1] = bits (thumb2_insn_r
->arm_insn
, 12, 15);
13467 record_buf
[2] = ARM_PS_REGNUM
;
13468 thumb2_insn_r
->reg_rec_count
= 3;
13471 return ARM_RECORD_FAILURE
;
13473 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13475 return ARM_RECORD_SUCCESS
;
13478 /* Record handler for thumb32 coprocessor instructions. */
13481 thumb2_record_coproc_insn (insn_decode_record
*thumb2_insn_r
)
13483 if (bit (thumb2_insn_r
->arm_insn
, 25))
13484 return arm_record_coproc_data_proc (thumb2_insn_r
);
13486 return arm_record_asimd_vfp_coproc (thumb2_insn_r
);
13489 /* Record handler for advance SIMD structure load/store instructions. */
13492 thumb2_record_asimd_struct_ld_st (insn_decode_record
*thumb2_insn_r
)
13494 struct regcache
*reg_cache
= thumb2_insn_r
->regcache
;
13495 uint32_t l_bit
, a_bit
, b_bits
;
13496 uint32_t record_buf
[128], record_buf_mem
[128];
13497 uint32_t reg_rn
, reg_vd
, address
, f_esize
, f_elem
;
13498 uint32_t index_r
= 0, index_e
= 0, bf_regs
= 0, index_m
= 0, loop_t
= 0;
13501 l_bit
= bit (thumb2_insn_r
->arm_insn
, 21);
13502 a_bit
= bit (thumb2_insn_r
->arm_insn
, 23);
13503 b_bits
= bits (thumb2_insn_r
->arm_insn
, 8, 11);
13504 reg_rn
= bits (thumb2_insn_r
->arm_insn
, 16, 19);
13505 reg_vd
= bits (thumb2_insn_r
->arm_insn
, 12, 15);
13506 reg_vd
= (bit (thumb2_insn_r
->arm_insn
, 22) << 4) | reg_vd
;
13507 f_ebytes
= (1 << bits (thumb2_insn_r
->arm_insn
, 6, 7));
13508 f_esize
= 8 * f_ebytes
;
13509 f_elem
= 8 / f_ebytes
;
13513 ULONGEST u_regval
= 0;
13514 regcache_raw_read_unsigned (reg_cache
, reg_rn
, &u_regval
);
13515 address
= u_regval
;
13520 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
13522 if (b_bits
== 0x07)
13524 else if (b_bits
== 0x0a)
13526 else if (b_bits
== 0x06)
13528 else if (b_bits
== 0x02)
13533 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
13535 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13537 record_buf_mem
[index_m
++] = f_ebytes
;
13538 record_buf_mem
[index_m
++] = address
;
13539 address
= address
+ f_ebytes
;
13540 thumb2_insn_r
->mem_rec_count
+= 1;
13545 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
13547 if (b_bits
== 0x09 || b_bits
== 0x08)
13549 else if (b_bits
== 0x03)
13554 for (index_r
= 0; index_r
< bf_regs
; index_r
++)
13555 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13557 for (loop_t
= 0; loop_t
< 2; loop_t
++)
13559 record_buf_mem
[index_m
++] = f_ebytes
;
13560 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
13561 thumb2_insn_r
->mem_rec_count
+= 1;
13563 address
= address
+ (2 * f_ebytes
);
13567 else if ((b_bits
& 0x0e) == 0x04)
13569 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13571 for (loop_t
= 0; loop_t
< 3; loop_t
++)
13573 record_buf_mem
[index_m
++] = f_ebytes
;
13574 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
13575 thumb2_insn_r
->mem_rec_count
+= 1;
13577 address
= address
+ (3 * f_ebytes
);
13581 else if (!(b_bits
& 0x0e))
13583 for (index_e
= 0; index_e
< f_elem
; index_e
++)
13585 for (loop_t
= 0; loop_t
< 4; loop_t
++)
13587 record_buf_mem
[index_m
++] = f_ebytes
;
13588 record_buf_mem
[index_m
++] = address
+ (loop_t
* f_ebytes
);
13589 thumb2_insn_r
->mem_rec_count
+= 1;
13591 address
= address
+ (4 * f_ebytes
);
13597 uint8_t bft_size
= bits (thumb2_insn_r
->arm_insn
, 10, 11);
13599 if (bft_size
== 0x00)
13601 else if (bft_size
== 0x01)
13603 else if (bft_size
== 0x02)
13609 if (!(b_bits
& 0x0b) || b_bits
== 0x08)
13610 thumb2_insn_r
->mem_rec_count
= 1;
13612 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09)
13613 thumb2_insn_r
->mem_rec_count
= 2;
13615 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a)
13616 thumb2_insn_r
->mem_rec_count
= 3;
13618 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b)
13619 thumb2_insn_r
->mem_rec_count
= 4;
13621 for (index_m
= 0; index_m
< thumb2_insn_r
->mem_rec_count
; index_m
++)
13623 record_buf_mem
[index_m
] = f_ebytes
;
13624 record_buf_mem
[index_m
] = address
+ (index_m
* f_ebytes
);
13633 if (b_bits
== 0x02 || b_bits
== 0x0a || (b_bits
& 0x0e) == 0x06)
13634 thumb2_insn_r
->reg_rec_count
= 1;
13636 else if (b_bits
== 0x03 || (b_bits
& 0x0e) == 0x08)
13637 thumb2_insn_r
->reg_rec_count
= 2;
13639 else if ((b_bits
& 0x0e) == 0x04)
13640 thumb2_insn_r
->reg_rec_count
= 3;
13642 else if (!(b_bits
& 0x0e))
13643 thumb2_insn_r
->reg_rec_count
= 4;
13648 if (!(b_bits
& 0x0b) || b_bits
== 0x08 || b_bits
== 0x0c)
13649 thumb2_insn_r
->reg_rec_count
= 1;
13651 else if ((b_bits
& 0x0b) == 0x01 || b_bits
== 0x09 || b_bits
== 0x0d)
13652 thumb2_insn_r
->reg_rec_count
= 2;
13654 else if ((b_bits
& 0x0b) == 0x02 || b_bits
== 0x0a || b_bits
== 0x0e)
13655 thumb2_insn_r
->reg_rec_count
= 3;
13657 else if ((b_bits
& 0x0b) == 0x03 || b_bits
== 0x0b || b_bits
== 0x0f)
13658 thumb2_insn_r
->reg_rec_count
= 4;
13660 for (index_r
= 0; index_r
< thumb2_insn_r
->reg_rec_count
; index_r
++)
13661 record_buf
[index_r
] = reg_vd
+ ARM_D0_REGNUM
+ index_r
;
13665 if (bits (thumb2_insn_r
->arm_insn
, 0, 3) != 15)
13667 record_buf
[index_r
] = reg_rn
;
13668 thumb2_insn_r
->reg_rec_count
+= 1;
13671 REG_ALLOC (thumb2_insn_r
->arm_regs
, thumb2_insn_r
->reg_rec_count
,
13673 MEM_ALLOC (thumb2_insn_r
->arm_mems
, thumb2_insn_r
->mem_rec_count
,
13678 /* Decodes thumb2 instruction type and invokes its record handler. */
13680 static unsigned int
13681 thumb2_record_decode_insn_handler (insn_decode_record
*thumb2_insn_r
)
13683 uint32_t op
, op1
, op2
;
13685 op
= bit (thumb2_insn_r
->arm_insn
, 15);
13686 op1
= bits (thumb2_insn_r
->arm_insn
, 27, 28);
13687 op2
= bits (thumb2_insn_r
->arm_insn
, 20, 26);
13691 if (!(op2
& 0x64 ))
13693 /* Load/store multiple instruction. */
13694 return thumb2_record_ld_st_multiple (thumb2_insn_r
);
13696 else if (!((op2
& 0x64) ^ 0x04))
13698 /* Load/store (dual/exclusive) and table branch instruction. */
13699 return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r
);
13701 else if (!((op2
& 0x20) ^ 0x20))
13703 /* Data-processing (shifted register). */
13704 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
13706 else if (op2
& 0x40)
13708 /* Co-processor instructions. */
13709 return thumb2_record_coproc_insn (thumb2_insn_r
);
13712 else if (op1
== 0x02)
13716 /* Branches and miscellaneous control instructions. */
13717 return thumb2_record_branch_misc_cntrl (thumb2_insn_r
);
13719 else if (op2
& 0x20)
13721 /* Data-processing (plain binary immediate) instruction. */
13722 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
13726 /* Data-processing (modified immediate). */
13727 return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r
);
13730 else if (op1
== 0x03)
13732 if (!(op2
& 0x71 ))
13734 /* Store single data item. */
13735 return thumb2_record_str_single_data (thumb2_insn_r
);
13737 else if (!((op2
& 0x71) ^ 0x10))
13739 /* Advanced SIMD or structure load/store instructions. */
13740 return thumb2_record_asimd_struct_ld_st (thumb2_insn_r
);
13742 else if (!((op2
& 0x67) ^ 0x01))
13744 /* Load byte, memory hints instruction. */
13745 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
13747 else if (!((op2
& 0x67) ^ 0x03))
13749 /* Load halfword, memory hints instruction. */
13750 return thumb2_record_ld_mem_hints (thumb2_insn_r
);
13752 else if (!((op2
& 0x67) ^ 0x05))
13754 /* Load word instruction. */
13755 return thumb2_record_ld_word (thumb2_insn_r
);
13757 else if (!((op2
& 0x70) ^ 0x20))
13759 /* Data-processing (register) instruction. */
13760 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
13762 else if (!((op2
& 0x78) ^ 0x30))
13764 /* Multiply, multiply accumulate, abs diff instruction. */
13765 return thumb2_record_ps_dest_generic (thumb2_insn_r
);
13767 else if (!((op2
& 0x78) ^ 0x38))
13769 /* Long multiply, long multiply accumulate, and divide. */
13770 return thumb2_record_lmul_lmla_div (thumb2_insn_r
);
13772 else if (op2
& 0x40)
13774 /* Co-processor instructions. */
13775 return thumb2_record_coproc_insn (thumb2_insn_r
);
13782 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
13783 and positive val on fauilure. */
13786 extract_arm_insn (insn_decode_record
*insn_record
, uint32_t insn_size
)
13788 gdb_byte buf
[insn_size
];
13790 memset (&buf
[0], 0, insn_size
);
13792 if (target_read_memory (insn_record
->this_addr
, &buf
[0], insn_size
))
13794 insn_record
->arm_insn
= (uint32_t) extract_unsigned_integer (&buf
[0],
13796 gdbarch_byte_order_for_code (insn_record
->gdbarch
));
13800 typedef int (*sti_arm_hdl_fp_t
) (insn_decode_record
*);
13802 /* Decode arm/thumb insn depending on condition cods and opcodes; and
13806 decode_insn (insn_decode_record
*arm_record
, record_type_t record_type
,
13807 uint32_t insn_size
)
13810 /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */
13811 static const sti_arm_hdl_fp_t arm_handle_insn
[8] =
13813 arm_record_data_proc_misc_ld_str
, /* 000. */
13814 arm_record_data_proc_imm
, /* 001. */
13815 arm_record_ld_st_imm_offset
, /* 010. */
13816 arm_record_ld_st_reg_offset
, /* 011. */
13817 arm_record_ld_st_multiple
, /* 100. */
13818 arm_record_b_bl
, /* 101. */
13819 arm_record_asimd_vfp_coproc
, /* 110. */
13820 arm_record_coproc_data_proc
/* 111. */
13823 /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */
13824 static const sti_arm_hdl_fp_t thumb_handle_insn
[8] =
13826 thumb_record_shift_add_sub
, /* 000. */
13827 thumb_record_add_sub_cmp_mov
, /* 001. */
13828 thumb_record_ld_st_reg_offset
, /* 010. */
13829 thumb_record_ld_st_imm_offset
, /* 011. */
13830 thumb_record_ld_st_stack
, /* 100. */
13831 thumb_record_misc
, /* 101. */
13832 thumb_record_ldm_stm_swi
, /* 110. */
13833 thumb_record_branch
/* 111. */
13836 uint32_t ret
= 0; /* return value: negative:failure 0:success. */
13837 uint32_t insn_id
= 0;
13839 if (extract_arm_insn (arm_record
, insn_size
))
13843 printf_unfiltered (_("Process record: error reading memory at "
13844 "addr %s len = %d.\n"),
13845 paddress (arm_record
->gdbarch
, arm_record
->this_addr
), insn_size
);
13849 else if (ARM_RECORD
== record_type
)
13851 arm_record
->cond
= bits (arm_record
->arm_insn
, 28, 31);
13852 insn_id
= bits (arm_record
->arm_insn
, 25, 27);
13853 ret
= arm_record_extension_space (arm_record
);
13854 /* If this insn has fallen into extension space
13855 then we need not decode it anymore. */
13856 if (ret
!= -1 && !INSN_RECORDED(arm_record
))
13858 ret
= arm_handle_insn
[insn_id
] (arm_record
);
13861 else if (THUMB_RECORD
== record_type
)
13863 /* As thumb does not have condition codes, we set negative. */
13864 arm_record
->cond
= -1;
13865 insn_id
= bits (arm_record
->arm_insn
, 13, 15);
13866 ret
= thumb_handle_insn
[insn_id
] (arm_record
);
13868 else if (THUMB2_RECORD
== record_type
)
13870 /* As thumb does not have condition codes, we set negative. */
13871 arm_record
->cond
= -1;
13873 /* Swap first half of 32bit thumb instruction with second half. */
13874 arm_record
->arm_insn
13875 = (arm_record
->arm_insn
>> 16) | (arm_record
->arm_insn
<< 16);
13877 insn_id
= thumb2_record_decode_insn_handler (arm_record
);
13879 if (insn_id
!= ARM_RECORD_SUCCESS
)
13881 arm_record_unsupported_insn (arm_record
);
13887 /* Throw assertion. */
13888 gdb_assert_not_reached ("not a valid instruction, could not decode");
13895 /* Cleans up local record registers and memory allocations. */
13898 deallocate_reg_mem (insn_decode_record
*record
)
13900 xfree (record
->arm_regs
);
13901 xfree (record
->arm_mems
);
13905 /* Parse the current instruction and record the values of the registers and
13906 memory that will be changed in current instruction to record_arch_list".
13907 Return -1 if something is wrong. */
13910 arm_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
13911 CORE_ADDR insn_addr
)
13914 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
13915 uint32_t no_of_rec
= 0;
13916 uint32_t ret
= 0; /* return value: -1:record failure ; 0:success */
13917 ULONGEST t_bit
= 0, insn_id
= 0;
13919 ULONGEST u_regval
= 0;
13921 insn_decode_record arm_record
;
13923 memset (&arm_record
, 0, sizeof (insn_decode_record
));
13924 arm_record
.regcache
= regcache
;
13925 arm_record
.this_addr
= insn_addr
;
13926 arm_record
.gdbarch
= gdbarch
;
13929 if (record_debug
> 1)
13931 fprintf_unfiltered (gdb_stdlog
, "Process record: arm_process_record "
13933 paddress (gdbarch
, arm_record
.this_addr
));
13936 if (extract_arm_insn (&arm_record
, 2))
13940 printf_unfiltered (_("Process record: error reading memory at "
13941 "addr %s len = %d.\n"),
13942 paddress (arm_record
.gdbarch
,
13943 arm_record
.this_addr
), 2);
13948 /* Check the insn, whether it is thumb or arm one. */
13950 t_bit
= arm_psr_thumb_bit (arm_record
.gdbarch
);
13951 regcache_raw_read_unsigned (arm_record
.regcache
, ARM_PS_REGNUM
, &u_regval
);
13954 if (!(u_regval
& t_bit
))
13956 /* We are decoding arm insn. */
13957 ret
= decode_insn (&arm_record
, ARM_RECORD
, ARM_INSN_SIZE_BYTES
);
13961 insn_id
= bits (arm_record
.arm_insn
, 11, 15);
13962 /* is it thumb2 insn? */
13963 if ((0x1D == insn_id
) || (0x1E == insn_id
) || (0x1F == insn_id
))
13965 ret
= decode_insn (&arm_record
, THUMB2_RECORD
,
13966 THUMB2_INSN_SIZE_BYTES
);
13970 /* We are decoding thumb insn. */
13971 ret
= decode_insn (&arm_record
, THUMB_RECORD
, THUMB_INSN_SIZE_BYTES
);
13977 /* Record registers. */
13978 record_full_arch_list_add_reg (arm_record
.regcache
, ARM_PC_REGNUM
);
13979 if (arm_record
.arm_regs
)
13981 for (no_of_rec
= 0; no_of_rec
< arm_record
.reg_rec_count
; no_of_rec
++)
13983 if (record_full_arch_list_add_reg
13984 (arm_record
.regcache
, arm_record
.arm_regs
[no_of_rec
]))
13988 /* Record memories. */
13989 if (arm_record
.arm_mems
)
13991 for (no_of_rec
= 0; no_of_rec
< arm_record
.mem_rec_count
; no_of_rec
++)
13993 if (record_full_arch_list_add_mem
13994 ((CORE_ADDR
)arm_record
.arm_mems
[no_of_rec
].addr
,
13995 arm_record
.arm_mems
[no_of_rec
].len
))
14000 if (record_full_arch_list_add_end ())
14005 deallocate_reg_mem (&arm_record
);