1 /* Common target dependent code for GDB on ARM systems.
2 Copyright (C) 2002, 2003, 2007, 2008, 2009, 2010
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 /* Forward declarations. */
27 /* Register numbers of various important registers. */
30 ARM_A1_REGNUM
= 0, /* first integer-like argument */
31 ARM_A4_REGNUM
= 3, /* last integer-like argument */
34 ARM_SP_REGNUM
= 13, /* Contains address of top of stack */
35 ARM_LR_REGNUM
= 14, /* address to return to from a function call */
36 ARM_PC_REGNUM
= 15, /* Contains program counter */
37 ARM_F0_REGNUM
= 16, /* first floating point register */
38 ARM_F3_REGNUM
= 19, /* last floating point argument register */
39 ARM_F7_REGNUM
= 23, /* last floating point register */
40 ARM_FPS_REGNUM
= 24, /* floating point status register */
41 ARM_PS_REGNUM
= 25, /* Contains processor status */
42 ARM_WR0_REGNUM
, /* WMMX data registers. */
43 ARM_WR15_REGNUM
= ARM_WR0_REGNUM
+ 15,
44 ARM_WC0_REGNUM
, /* WMMX control registers. */
45 ARM_WCSSF_REGNUM
= ARM_WC0_REGNUM
+ 2,
46 ARM_WCASF_REGNUM
= ARM_WC0_REGNUM
+ 3,
47 ARM_WC7_REGNUM
= ARM_WC0_REGNUM
+ 7,
48 ARM_WCGR0_REGNUM
, /* WMMX general purpose registers. */
49 ARM_WCGR3_REGNUM
= ARM_WCGR0_REGNUM
+ 3,
50 ARM_WCGR7_REGNUM
= ARM_WCGR0_REGNUM
+ 7,
51 ARM_D0_REGNUM
, /* VFP double-precision registers. */
52 ARM_D31_REGNUM
= ARM_D0_REGNUM
+ 31,
56 /* Other useful registers. */
57 ARM_FP_REGNUM
= 11, /* Frame register in ARM code, if used. */
58 THUMB_FP_REGNUM
= 7, /* Frame register in Thumb code, if used. */
60 ARM_LAST_ARG_REGNUM
= ARM_A4_REGNUM
,
61 ARM_NUM_FP_ARG_REGS
= 4,
62 ARM_LAST_FP_ARG_REGNUM
= ARM_F3_REGNUM
65 /* Size of integer registers. */
66 #define INT_REGISTER_SIZE 4
68 /* Say how long FP registers are. Used for documentation purposes and
69 code readability in this header. IEEE extended doubles are 80
70 bits. DWORD aligned they use 96 bits. */
71 #define FP_REGISTER_SIZE 12
73 /* Number of machine registers. The only define actually required
74 is gdbarch_num_regs. The other definitions are used for documentation
75 purposes and code readability. */
76 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
77 (and called PS for processor status) so the status bits can be cleared
78 from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed
80 #define NUM_FREGS 8 /* Number of floating point registers. */
81 #define NUM_SREGS 2 /* Number of status registers. */
82 #define NUM_GREGS 16 /* Number of general purpose registers. */
85 /* Instruction condition field values. */
103 #define FLAG_N 0x80000000
104 #define FLAG_Z 0x40000000
105 #define FLAG_C 0x20000000
106 #define FLAG_V 0x10000000
110 /* Type of floating-point code in use by inferior. There are really 3 models
111 that are traditionally supported (plus the endianness issue), but gcc can
112 only generate 2 of those. The third is APCS_FLOAT, where arguments to
113 functions are passed in floating-point registers.
115 In addition to the traditional models, VFP adds two more.
117 If you update this enum, don't forget to update fp_model_strings in
122 ARM_FLOAT_AUTO
, /* Automatic detection. Do not set in tdep. */
123 ARM_FLOAT_SOFT_FPA
, /* Traditional soft-float (mixed-endian on LE ARM). */
124 ARM_FLOAT_FPA
, /* FPA co-processor. GCC calling convention. */
125 ARM_FLOAT_SOFT_VFP
, /* Soft-float with pure-endian doubles. */
126 ARM_FLOAT_VFP
, /* Full VFP calling convention. */
127 ARM_FLOAT_LAST
/* Keep at end. */
130 /* ABI used by the inferior. */
139 /* Convention for returning structures. */
143 pcc_struct_return
, /* Return "short" structures in memory. */
144 reg_struct_return
/* Return "short" structures in registers. */
147 /* Target-dependent structure in gdbarch. */
150 /* The ABI for this architecture. It should never be set to
152 enum arm_abi_kind arm_abi
;
154 enum arm_float_model fp_model
; /* Floating point calling conventions. */
156 int have_fpa_registers
; /* Does the target report the FPA registers? */
157 int have_vfp_registers
; /* Does the target report the VFP registers? */
158 int have_vfp_pseudos
; /* Are we synthesizing the single precision
160 int have_neon_pseudos
; /* Are we synthesizing the quad precision
161 NEON registers? Requires
163 int have_neon
; /* Do we have a NEON unit? */
165 CORE_ADDR lowest_pc
; /* Lowest address at which instructions
168 const char *arm_breakpoint
; /* Breakpoint pattern for an ARM insn. */
169 int arm_breakpoint_size
; /* And its size. */
170 const char *thumb_breakpoint
; /* Breakpoint pattern for an ARM insn. */
171 int thumb_breakpoint_size
; /* And its size. */
173 int jb_pc
; /* Offset to PC value in jump buffer.
174 If this is negative, longjmp support
176 size_t jb_elt_size
; /* And the size of each entry in the buf. */
178 /* Convention for returning structures. */
179 enum struct_return struct_return
;
181 /* Cached core file helpers. */
182 struct regset
*gregset
, *fpregset
;
184 /* ISA-specific data types. */
185 struct type
*arm_ext_type
;
186 struct type
*neon_double_type
;
187 struct type
*neon_quad_type
;
190 /* Structures used for displaced stepping. */
192 /* The maximum number of temporaries available for displaced instructions. */
193 #define DISPLACED_TEMPS 16
194 /* The maximum number of modified instructions generated for one single-stepped
195 instruction, including the breakpoint (usually at the end of the instruction
196 sequence) and any scratch words, etc. */
197 #define DISPLACED_MODIFIED_INSNS 8
199 struct displaced_step_closure
201 ULONGEST tmp
[DISPLACED_TEMPS
];
209 int rn
; /* Writeback register. */
210 unsigned int immed
: 1; /* Offset is immediate. */
211 unsigned int writeback
: 1; /* Perform base-register writeback. */
212 unsigned int restore_r4
: 1; /* Used r4 as scratch. */
218 unsigned int link
: 1;
219 unsigned int exchange
: 1;
220 unsigned int cond
: 4;
225 unsigned int regmask
;
228 unsigned int load
: 1;
229 unsigned int user
: 1;
230 unsigned int increment
: 1;
231 unsigned int before
: 1;
232 unsigned int writeback
: 1;
233 unsigned int cond
: 4;
238 unsigned int immed
: 1;
243 /* If non-NULL, override generic SVC handling (e.g. for a particular
245 int (*copy_svc_os
) (struct gdbarch
*gdbarch
, uint32_t insn
, CORE_ADDR to
,
246 struct regcache
*regs
,
247 struct displaced_step_closure
*dsc
);
250 unsigned long modinsn
[DISPLACED_MODIFIED_INSNS
];
253 CORE_ADDR scratch_base
;
254 void (*cleanup
) (struct gdbarch
*, struct regcache
*,
255 struct displaced_step_closure
*);
258 /* Values for the WRITE_PC argument to displaced_write_reg. If the register
259 write may write to the PC, specifies the way the CPSR T bit, etc. is
260 modified by the instruction. */
272 arm_process_displaced_insn (struct gdbarch
*gdbarch
, uint32_t insn
,
273 CORE_ADDR from
, CORE_ADDR to
,
274 struct regcache
*regs
,
275 struct displaced_step_closure
*dsc
);
277 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
278 CORE_ADDR to
, struct displaced_step_closure
*dsc
);
280 displaced_read_reg (struct regcache
*regs
, CORE_ADDR from
, int regno
);
282 displaced_write_reg (struct regcache
*regs
,
283 struct displaced_step_closure
*dsc
, int regno
,
284 ULONGEST val
, enum pc_write_style write_pc
);
286 CORE_ADDR
arm_skip_stub (struct frame_info
*, CORE_ADDR
);
287 CORE_ADDR
arm_get_next_pc (struct frame_info
*, CORE_ADDR
);
288 int arm_software_single_step (struct frame_info
*);
290 extern struct displaced_step_closure
*
291 arm_displaced_step_copy_insn (struct gdbarch
*, CORE_ADDR
, CORE_ADDR
,
293 extern void arm_displaced_step_fixup (struct gdbarch
*,
294 struct displaced_step_closure
*,
295 CORE_ADDR
, CORE_ADDR
, struct regcache
*);
297 /* Functions exported from armbsd-tdep.h. */
299 /* Return the appropriate register set for the core section identified
300 by SECT_NAME and SECT_SIZE. */
302 extern const struct regset
*
303 armbsd_regset_from_core_section (struct gdbarch
*gdbarch
,
304 const char *sect_name
, size_t sect_size
);
306 #endif /* arm-tdep.h */