1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 2002, 2003 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
21 /* Register numbers of various important registers. Note that some of
22 these values are "real" register numbers, and correspond to the
23 general registers of the machine, and some are "phony" register
24 numbers which are too large to be actual register numbers as far as
25 the user is concerned but do serve to get the desired values when
26 passed to read_register. */
29 ARM_A1_REGNUM
= 0, /* first integer-like argument */
30 ARM_A4_REGNUM
= 3, /* last integer-like argument */
32 ARM_SP_REGNUM
= 13, /* Contains address of top of stack */
33 ARM_LR_REGNUM
= 14, /* address to return to from a function call */
34 ARM_PC_REGNUM
= 15, /* Contains program counter */
35 ARM_F0_REGNUM
= 16, /* first floating point register */
36 ARM_F3_REGNUM
= 19, /* last floating point argument register */
37 ARM_F7_REGNUM
= 23, /* last floating point register */
38 ARM_FPS_REGNUM
= 24, /* floating point status register */
39 ARM_PS_REGNUM
= 25, /* Contains processor status */
40 ARM_FP_REGNUM
= 11, /* Frame register in ARM code, if used. */
41 THUMB_FP_REGNUM
= 7, /* Frame register in Thumb code, if used. */
43 ARM_LAST_ARG_REGNUM
= ARM_A4_REGNUM
,
44 ARM_NUM_FP_ARG_REGS
= 4,
45 ARM_LAST_FP_ARG_REGNUM
= ARM_F3_REGNUM
48 /* Used in target-specific code when we need to know the size of the
49 largest type of register we need to handle. */
50 #define ARM_MAX_REGISTER_RAW_SIZE 12
51 #define ARM_MAX_REGISTER_VIRTUAL_SIZE 8
53 /* Size of integer registers. */
54 #define INT_REGISTER_RAW_SIZE 4
55 #define INT_REGISTER_VIRTUAL_SIZE 4
57 /* Say how long FP registers are. Used for documentation purposes and
58 code readability in this header. IEEE extended doubles are 80
59 bits. DWORD aligned they use 96 bits. */
60 #define FP_REGISTER_RAW_SIZE 12
62 /* GCC doesn't support long doubles (extended IEEE values). The FP
63 register virtual size is therefore 64 bits. Used for documentation
64 purposes and code readability in this header. */
65 #define FP_REGISTER_VIRTUAL_SIZE 8
67 /* Status registers are the same size as general purpose registers.
68 Used for documentation purposes and code readability in this
70 #define STATUS_REGISTER_SIZE 4
72 /* Number of machine registers. The only define actually required
73 is NUM_REGS. The other definitions are used for documentation
74 purposes and code readability. */
75 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
76 (and called PS for processor status) so the status bits can be cleared
77 from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed
79 #define NUM_FREGS 8 /* Number of floating point registers. */
80 #define NUM_SREGS 2 /* Number of status registers. */
81 #define NUM_GREGS 16 /* Number of general purpose registers. */
84 /* Instruction condition field values. */
102 #define FLAG_N 0x80000000
103 #define FLAG_Z 0x40000000
104 #define FLAG_C 0x20000000
105 #define FLAG_V 0x10000000
107 /* Type of floating-point code in use by inferior. There are really 3 models
108 that are traditionally supported (plus the endianness issue), but gcc can
109 only generate 2 of those. The third is APCS_FLOAT, where arguments to
110 functions are passed in floating-point registers.
112 In addition to the traditional models, VFP adds two more.
114 If you update this enum, don't forget to update fp_model_strings in
119 ARM_FLOAT_AUTO
, /* Automatic detection. Do not set in tdep. */
120 ARM_FLOAT_SOFT_FPA
, /* Traditional soft-float (mixed-endian on LE ARM). */
121 ARM_FLOAT_FPA
, /* FPA co-processor. GCC calling convention. */
122 ARM_FLOAT_SOFT_VFP
, /* Soft-float with pure-endian doubles. */
123 ARM_FLOAT_VFP
, /* Full VFP calling convention. */
124 ARM_FLOAT_LAST
/* Keep at end. */
127 /* A method to the setting based on user's choice and ABI setting. */
128 enum arm_float_model
arm_get_fp_model (struct gdbarch
*);
130 /* Target-dependent structure in gdbarch. */
133 enum arm_float_model fp_model
; /* Floating point calling conventions. */
135 CORE_ADDR lowest_pc
; /* Lowest address at which instructions
138 const char *arm_breakpoint
; /* Breakpoint pattern for an ARM insn. */
139 int arm_breakpoint_size
; /* And its size. */
140 const char *thumb_breakpoint
; /* Breakpoint pattern for an ARM insn. */
141 int thumb_breakpoint_size
; /* And its size. */
143 int jb_pc
; /* Offset to PC value in jump buffer.
144 If this is negative, longjmp support
146 size_t jb_elt_size
; /* And the size of each entry in the buf. */
150 #define LOWEST_PC (gdbarch_tdep (current_gdbarch)->lowest_pc)
153 /* Prototypes for internal interfaces needed by more than one MD file. */
154 int arm_pc_is_thumb_dummy (CORE_ADDR
);
156 int arm_pc_is_thumb (CORE_ADDR
);
158 CORE_ADDR
thumb_get_next_pc (CORE_ADDR
);
160 CORE_ADDR
arm_get_next_pc (CORE_ADDR
);
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