1 /* Common target dependent code for GDB on ARM systems.
2 Copyright (C) 2002-2016 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 /* Forward declarations. */
27 struct arm_get_next_pcs
;
28 struct gdb_get_next_pcs
;
32 /* Say how long FP registers are. Used for documentation purposes and
33 code readability in this header. IEEE extended doubles are 80
34 bits. DWORD aligned they use 96 bits. */
35 #define FP_REGISTER_SIZE 12
37 /* Say how long VFP double precision registers are. Used for documentation
38 purposes and code readability. These are fixed at 64 bits. */
39 #define VFP_REGISTER_SIZE 8
41 /* Number of machine registers. The only define actually required
42 is gdbarch_num_regs. The other definitions are used for documentation
43 purposes and code readability. */
44 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
45 (and called PS for processor status) so the status bits can be cleared
46 from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed
48 #define NUM_FREGS 8 /* Number of floating point registers. */
49 #define NUM_SREGS 2 /* Number of status registers. */
50 #define NUM_GREGS 16 /* Number of general purpose registers. */
54 /* Type of floating-point code in use by inferior. There are really 3 models
55 that are traditionally supported (plus the endianness issue), but gcc can
56 only generate 2 of those. The third is APCS_FLOAT, where arguments to
57 functions are passed in floating-point registers.
59 In addition to the traditional models, VFP adds two more.
61 If you update this enum, don't forget to update fp_model_strings in
66 ARM_FLOAT_AUTO
, /* Automatic detection. Do not set in tdep. */
67 ARM_FLOAT_SOFT_FPA
, /* Traditional soft-float (mixed-endian on LE ARM). */
68 ARM_FLOAT_FPA
, /* FPA co-processor. GCC calling convention. */
69 ARM_FLOAT_SOFT_VFP
, /* Soft-float with pure-endian doubles. */
70 ARM_FLOAT_VFP
, /* Full VFP calling convention. */
71 ARM_FLOAT_LAST
/* Keep at end. */
74 /* ABI used by the inferior. */
83 /* Convention for returning structures. */
87 pcc_struct_return
, /* Return "short" structures in memory. */
88 reg_struct_return
/* Return "short" structures in registers. */
91 /* Target-dependent structure in gdbarch. */
94 /* The ABI for this architecture. It should never be set to
96 enum arm_abi_kind arm_abi
;
98 enum arm_float_model fp_model
; /* Floating point calling conventions. */
100 int have_fpa_registers
; /* Does the target report the FPA registers? */
101 int have_wmmx_registers
; /* Does the target report the WMMX registers? */
102 /* The number of VFP registers reported by the target. It is zero
103 if VFP registers are not supported. */
104 int vfp_register_count
;
105 int have_vfp_pseudos
; /* Are we synthesizing the single precision
107 int have_neon_pseudos
; /* Are we synthesizing the quad precision
108 NEON registers? Requires
110 int have_neon
; /* Do we have a NEON unit? */
112 int is_m
; /* Does the target follow the "M" profile. */
113 CORE_ADDR lowest_pc
; /* Lowest address at which instructions
116 const gdb_byte
*arm_breakpoint
; /* Breakpoint pattern for an ARM insn. */
117 int arm_breakpoint_size
; /* And its size. */
118 const gdb_byte
*thumb_breakpoint
; /* Breakpoint pattern for a Thumb insn. */
119 int thumb_breakpoint_size
; /* And its size. */
121 /* If the Thumb breakpoint is an undefined instruction (which is
122 affected by IT blocks) rather than a BKPT instruction (which is
123 not), then we need a 32-bit Thumb breakpoint to preserve the
124 instruction count in IT blocks. */
125 const gdb_byte
*thumb2_breakpoint
;
126 int thumb2_breakpoint_size
;
128 int jb_pc
; /* Offset to PC value in jump buffer.
129 If this is negative, longjmp support
131 size_t jb_elt_size
; /* And the size of each entry in the buf. */
133 /* Convention for returning structures. */
134 enum struct_return struct_return
;
136 /* ISA-specific data types. */
137 struct type
*arm_ext_type
;
138 struct type
*neon_double_type
;
139 struct type
*neon_quad_type
;
141 /* syscall record. */
142 int (*arm_syscall_record
) (struct regcache
*regcache
, unsigned long svc_number
);
145 /* Structures used for displaced stepping. */
147 /* The maximum number of temporaries available for displaced instructions. */
148 #define DISPLACED_TEMPS 16
149 /* The maximum number of modified instructions generated for one single-stepped
150 instruction, including the breakpoint (usually at the end of the instruction
151 sequence) and any scratch words, etc. */
152 #define DISPLACED_MODIFIED_INSNS 8
154 struct displaced_step_closure
156 ULONGEST tmp
[DISPLACED_TEMPS
];
164 int rn
; /* Writeback register. */
165 unsigned int immed
: 1; /* Offset is immediate. */
166 unsigned int writeback
: 1; /* Perform base-register writeback. */
167 unsigned int restore_r4
: 1; /* Used r4 as scratch. */
173 unsigned int link
: 1;
174 unsigned int exchange
: 1;
175 unsigned int cond
: 4;
180 unsigned int regmask
;
183 unsigned int load
: 1;
184 unsigned int user
: 1;
185 unsigned int increment
: 1;
186 unsigned int before
: 1;
187 unsigned int writeback
: 1;
188 unsigned int cond
: 4;
193 unsigned int immed
: 1;
198 /* If non-NULL, override generic SVC handling (e.g. for a particular
200 int (*copy_svc_os
) (struct gdbarch
*gdbarch
, struct regcache
*regs
,
201 struct displaced_step_closure
*dsc
);
205 /* The size of original instruction, 2 or 4. */
206 unsigned int insn_size
;
207 /* True if the original insn (and thus all replacement insns) are Thumb
209 unsigned int is_thumb
;
211 /* The slots in the array is used in this way below,
212 - ARM instruction occupies one slot,
213 - Thumb 16 bit instruction occupies one slot,
214 - Thumb 32-bit instruction occupies *two* slots, one part for each. */
215 unsigned long modinsn
[DISPLACED_MODIFIED_INSNS
];
218 CORE_ADDR scratch_base
;
219 void (*cleanup
) (struct gdbarch
*, struct regcache
*,
220 struct displaced_step_closure
*);
223 /* Values for the WRITE_PC argument to displaced_write_reg. If the register
224 write may write to the PC, specifies the way the CPSR T bit, etc. is
225 modified by the instruction. */
237 arm_process_displaced_insn (struct gdbarch
*gdbarch
, CORE_ADDR from
,
238 CORE_ADDR to
, struct regcache
*regs
,
239 struct displaced_step_closure
*dsc
);
241 arm_displaced_init_closure (struct gdbarch
*gdbarch
, CORE_ADDR from
,
242 CORE_ADDR to
, struct displaced_step_closure
*dsc
);
244 displaced_read_reg (struct regcache
*regs
, struct displaced_step_closure
*dsc
,
247 displaced_write_reg (struct regcache
*regs
,
248 struct displaced_step_closure
*dsc
, int regno
,
249 ULONGEST val
, enum pc_write_style write_pc
);
251 CORE_ADDR
arm_skip_stub (struct frame_info
*, CORE_ADDR
);
253 ULONGEST
arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr
,
257 CORE_ADDR
arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs
*self
,
260 int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs
*self
);
262 void arm_insert_single_step_breakpoint (struct gdbarch
*,
263 struct address_space
*, CORE_ADDR
);
264 int arm_software_single_step (struct frame_info
*);
265 int arm_is_thumb (struct regcache
*regcache
);
266 int arm_frame_is_thumb (struct frame_info
*frame
);
268 extern void arm_displaced_step_fixup (struct gdbarch
*,
269 struct displaced_step_closure
*,
270 CORE_ADDR
, CORE_ADDR
, struct regcache
*);
272 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
273 extern int arm_psr_thumb_bit (struct gdbarch
*);
275 /* Is the instruction at the given memory address a Thumb or ARM
277 extern int arm_pc_is_thumb (struct gdbarch
*, CORE_ADDR
);
279 extern int arm_process_record (struct gdbarch
*gdbarch
,
280 struct regcache
*regcache
, CORE_ADDR addr
);
281 /* Functions exported from armbsd-tdep.h. */
283 /* Return the appropriate register set for the core section identified
284 by SECT_NAME and SECT_SIZE. */
287 armbsd_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
288 iterate_over_regset_sections_cb
*cb
,
290 const struct regcache
*regcache
);
292 /* Target descriptions. */
293 extern struct target_desc
*tdesc_arm_with_m
;
294 extern struct target_desc
*tdesc_arm_with_iwmmxt
;
295 extern struct target_desc
*tdesc_arm_with_vfpv2
;
296 extern struct target_desc
*tdesc_arm_with_vfpv3
;
297 extern struct target_desc
*tdesc_arm_with_neon
;
299 #endif /* arm-tdep.h */