gdb/common/i386-gcc-cpuid.h

   1 /*
   2  * Helper cpuid.h file copied from gcc-4.8.0.  Code in gdb should not
   3  * include this directly, but pull in i386-cpuid.h and use that func.
   4  */
   5 /*
   6  * Copyright (C) 2007-2013 Free Software Foundation, Inc.
   7  *
   8  * This file is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License as published by the
  10  * Free Software Foundation; either version 3, or (at your option) any
  11  * later version.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * Under Section 7 of GPL version 3, you are granted additional
  19  * permissions described in the GCC Runtime Library Exception, version
  20  * 3.1, as published by the Free Software Foundation.
  21  *
  22  * You should have received a copy of the GNU General Public License and
  23  * a copy of the GCC Runtime Library Exception along with this program;
  24  * see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  25  * <http://www.gnu.org/licenses/>.
  26  */
  27
  28 /* %ecx */
  29 #define bit_SSE3        (1 << 0)
  30 #define bit_PCLMUL      (1 << 1)
  31 #define bit_LZCNT       (1 << 5)
  32 #define bit_SSSE3       (1 << 9)
  33 #define bit_FMA         (1 << 12)
  34 #define bit_CMPXCHG16B  (1 << 13)
  35 #define bit_SSE4_1      (1 << 19)
  36 #define bit_SSE4_2      (1 << 20)
  37 #define bit_MOVBE       (1 << 22)
  38 #define bit_POPCNT      (1 << 23)
  39 #define bit_AES         (1 << 25)
  40 #define bit_XSAVE       (1 << 26)
  41 #define bit_OSXSAVE     (1 << 27)
  42 #define bit_AVX         (1 << 28)
  43 #define bit_F16C        (1 << 29)
  44 #define bit_RDRND       (1 << 30)
  45
  46 /* %edx */
  47 #define bit_CMPXCHG8B   (1 << 8)
  48 #define bit_CMOV        (1 << 15)
  49 #define bit_MMX         (1 << 23)
  50 #define bit_FXSAVE      (1 << 24)
  51 #define bit_SSE         (1 << 25)
  52 #define bit_SSE2        (1 << 26)
  53
  54 /* Extended Features */
  55 /* %ecx */
  56 #define bit_LAHF_LM     (1 << 0)
  57 #define bit_ABM         (1 << 5)
  58 #define bit_SSE4a       (1 << 6)
  59 #define bit_PRFCHW      (1 << 8)
  60 #define bit_XOP         (1 << 11)
  61 #define bit_LWP         (1 << 15)
  62 #define bit_FMA4        (1 << 16)
  63 #define bit_TBM         (1 << 21)
  64
  65 /* %edx */
  66 #define bit_MMXEXT      (1 << 22)
  67 #define bit_LM          (1 << 29)
  68 #define bit_3DNOWP      (1 << 30)
  69 #define bit_3DNOW       (1 << 31)
  70
  71 /* Extended Features (%eax == 7) */
  72 #define bit_FSGSBASE    (1 << 0)
  73 #define bit_BMI (1 << 3)
  74 #define bit_HLE (1 << 4)
  75 #define bit_AVX2        (1 << 5)
  76 #define bit_BMI2        (1 << 8)
  77 #define bit_RTM (1 << 11)
  78 #define bit_RDSEED      (1 << 18)
  79 #define bit_ADX (1 << 19)
  80
  81 /* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
  82 #define bit_XSAVEOPT    (1 << 0)
  83
  84 /* Signatures for different CPU implementations as returned in uses
  85    of cpuid with level 0.  */
  86 #define signature_AMD_ebx       0x68747541
  87 #define signature_AMD_ecx       0x444d4163
  88 #define signature_AMD_edx       0x69746e65
  89
  90 #define signature_CENTAUR_ebx   0x746e6543
  91 #define signature_CENTAUR_ecx   0x736c7561
  92 #define signature_CENTAUR_edx   0x48727561
  93
  94 #define signature_CYRIX_ebx     0x69727943
  95 #define signature_CYRIX_ecx     0x64616574
  96 #define signature_CYRIX_edx     0x736e4978
  97
  98 #define signature_INTEL_ebx     0x756e6547
  99 #define signature_INTEL_ecx     0x6c65746e
 100 #define signature_INTEL_edx     0x49656e69
 101
 102 #define signature_TM1_ebx       0x6e617254
 103 #define signature_TM1_ecx       0x55504361
 104 #define signature_TM1_edx       0x74656d73
 105
 106 #define signature_TM2_ebx       0x756e6547
 107 #define signature_TM2_ecx       0x3638784d
 108 #define signature_TM2_edx       0x54656e69
 109
 110 #define signature_NSC_ebx       0x646f6547
 111 #define signature_NSC_ecx       0x43534e20
 112 #define signature_NSC_edx       0x79622065
 113
 114 #define signature_NEXGEN_ebx    0x4778654e
 115 #define signature_NEXGEN_ecx    0x6e657669
 116 #define signature_NEXGEN_edx    0x72446e65
 117
 118 #define signature_RISE_ebx      0x65736952
 119 #define signature_RISE_ecx      0x65736952
 120 #define signature_RISE_edx      0x65736952
 121
 122 #define signature_SIS_ebx       0x20536953
 123 #define signature_SIS_ecx       0x20536953
 124 #define signature_SIS_edx       0x20536953
 125
 126 #define signature_UMC_ebx       0x20434d55
 127 #define signature_UMC_ecx       0x20434d55
 128 #define signature_UMC_edx       0x20434d55
 129
 130 #define signature_VIA_ebx       0x20414956
 131 #define signature_VIA_ecx       0x20414956
 132 #define signature_VIA_edx       0x20414956
 133
 134 #define signature_VORTEX_ebx    0x74726f56
 135 #define signature_VORTEX_ecx    0x436f5320
 136 #define signature_VORTEX_edx    0x36387865
 137
 138 #if defined(__i386__) && defined(__PIC__)
 139 /* %ebx may be the PIC register.  */
 140 #if __GNUC__ >= 3
 141 #define __cpuid(level, a, b, c, d)                      \
 142   __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t"                  \
 143            "cpuid\n\t"                                  \
 144            "xchg{l}\t{%%}ebx, %k1\n\t"                  \
 145            : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)    \
 146            : "0" (level))
 147
 148 #define __cpuid_count(level, count, a, b, c, d)         \
 149   __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t"                  \
 150            "cpuid\n\t"                                  \
 151            "xchg{l}\t{%%}ebx, %k1\n\t"                  \
 152            : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)    \
 153            : "0" (level), "2" (count))
 154 #else
 155 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
 156    nor alternatives in i386 code.  */
 157 #define __cpuid(level, a, b, c, d)                      \
 158   __asm__ ("xchgl\t%%ebx, %k1\n\t"                      \
 159            "cpuid\n\t"                                  \
 160            "xchgl\t%%ebx, %k1\n\t"                      \
 161            : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)    \
 162            : "0" (level))
 163
 164 #define __cpuid_count(level, count, a, b, c, d)         \
 165   __asm__ ("xchgl\t%%ebx, %k1\n\t"                      \
 166            "cpuid\n\t"                                  \
 167            "xchgl\t%%ebx, %k1\n\t"                      \
 168            : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)    \
 169            : "0" (level), "2" (count))
 170 #endif
 171 #elif defined(__x86_64__) && (defined(__code_model_medium__) || defined(__code_model_large__)) && defined(__PIC__)
 172 /* %rbx may be the PIC register.  */
 173 #define __cpuid(level, a, b, c, d)                      \
 174   __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t"                  \
 175            "cpuid\n\t"                                  \
 176            "xchg{q}\t{%%}rbx, %q1\n\t"                  \
 177            : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)    \
 178            : "0" (level))
 179
 180 #define __cpuid_count(level, count, a, b, c, d)         \
 181   __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t"                  \
 182            "cpuid\n\t"                                  \
 183            "xchg{q}\t{%%}rbx, %q1\n\t"                  \
 184            : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)    \
 185            : "0" (level), "2" (count))
 186 #else
 187 #define __cpuid(level, a, b, c, d)                      \
 188   __asm__ ("cpuid\n\t"                                  \
 189            : "=a" (a), "=b" (b), "=c" (c), "=d" (d)     \
 190            : "0" (level))
 191
 192 #define __cpuid_count(level, count, a, b, c, d)         \
 193   __asm__ ("cpuid\n\t"                                  \
 194            : "=a" (a), "=b" (b), "=c" (c), "=d" (d)     \
 195            : "0" (level), "2" (count))
 196 #endif
 197
 198 /* Return highest supported input value for cpuid instruction.  ext can
 199    be either 0x0 or 0x8000000 to return highest supported value for
 200    basic or extended cpuid information.  Function returns 0 if cpuid
 201    is not supported or whatever cpuid returns in eax register.  If sig
 202    pointer is non-null, then first four bytes of the signature
 203    (as found in ebx register) are returned in location pointed by sig.  */
 204
 205 static __inline unsigned int
 206 __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
 207 {
 208   unsigned int __eax, __ebx, __ecx, __edx;
 209
 210 #ifdef __i386__
 211   /* See if we can use cpuid.  On AMD64 we always can.  */
 212 #if __GNUC__ >= 3
 213   __asm__ ("pushf{l|d}\n\t"
 214            "pushf{l|d}\n\t"
 215            "pop{l}\t%0\n\t"
 216            "mov{l}\t{%0, %1|%1, %0}\n\t"
 217            "xor{l}\t{%2, %0|%0, %2}\n\t"
 218            "push{l}\t%0\n\t"
 219            "popf{l|d}\n\t"
 220            "pushf{l|d}\n\t"
 221            "pop{l}\t%0\n\t"
 222            "popf{l|d}\n\t"
 223            : "=&r" (__eax), "=&r" (__ebx)
 224            : "i" (0x00200000));
 225 #else
 226 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
 227    nor alternatives in i386 code.  */
 228   __asm__ ("pushfl\n\t"
 229            "pushfl\n\t"
 230            "popl\t%0\n\t"
 231            "movl\t%0, %1\n\t"
 232            "xorl\t%2, %0\n\t"
 233            "pushl\t%0\n\t"
 234            "popfl\n\t"
 235            "pushfl\n\t"
 236            "popl\t%0\n\t"
 237            "popfl\n\t"
 238            : "=&r" (__eax), "=&r" (__ebx)
 239            : "i" (0x00200000));
 240 #endif
 241
 242   if (!((__eax ^ __ebx) & 0x00200000))
 243     return 0;
 244 #endif
 245
 246   /* Host supports cpuid.  Return highest supported cpuid input value.  */
 247   __cpuid (__ext, __eax, __ebx, __ecx, __edx);
 248
 249   if (__sig)
 250     *__sig = __ebx;
 251
 252   return __eax;
 253 }
 254
 255 /* Return cpuid data for requested cpuid level, as found in returned
 256    eax, ebx, ecx and edx registers.  The function checks if cpuid is
 257    supported and returns 1 for valid cpuid information or 0 for
 258    unsupported cpuid level.  All pointers are required to be non-null.  */
 259
 260 static __inline int
 261 __get_cpuid (unsigned int __level,
 262              unsigned int *__eax, unsigned int *__ebx,
 263              unsigned int *__ecx, unsigned int *__edx)
 264 {
 265   unsigned int __ext = __level & 0x80000000;
 266
 267   if (__get_cpuid_max (__ext, 0) < __level)
 268     return 0;
 269
 270   __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx);
 271   return 1;
 272 }