gdb/config/arm/tm-arm.h

   1 /* Definitions to target GDB to ARM targets.
   2    Copyright 1986, 1987, 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997,
   3    1998, 1999, 2000 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place - Suite 330,
  20    Boston, MA 02111-1307, USA.  */
  21
  22 #ifndef TM_ARM_H
  23 #define TM_ARM_H
  24
  25 #include "regcache.h"
  26
  27 /* Forward declarations for prototypes.  */
  28 struct type;
  29 struct value;
  30
  31 /* Target byte order on ARM defaults to selectable, and defaults to
  32    little endian.  */
  33 #define TARGET_BYTE_ORDER_SELECTABLE_P  1
  34 #define TARGET_BYTE_ORDER_DEFAULT       LITTLE_ENDIAN
  35
  36 /* IEEE format floating point.  */
  37 #define IEEE_FLOAT (1)
  38 #define TARGET_DOUBLE_FORMAT  (target_byte_order == BIG_ENDIAN \
  39                                ? &floatformat_ieee_double_big    \
  40                                : &floatformat_ieee_double_littlebyte_bigword)
  41
  42 /* When reading symbols, we need to zap the low bit of the address,
  43    which may be set to 1 for Thumb functions.  */
  44
  45 #define SMASH_TEXT_ADDRESS(addr) ((addr) &= ~0x1)
  46
  47 /* Remove useless bits from addresses in a running program.  */
  48
  49 CORE_ADDR arm_addr_bits_remove (CORE_ADDR);
  50
  51 #define ADDR_BITS_REMOVE(val)   (arm_addr_bits_remove (val))
  52
  53 /* Offset from address of function to start of its code.  Zero on most
  54    machines.  */
  55
  56 #define FUNCTION_START_OFFSET   0
  57
  58 /* Advance PC across any function entry prologue instructions to reach
  59    some "real" code.  */
  60
  61 extern CORE_ADDR arm_skip_prologue (CORE_ADDR pc);
  62
  63 #define SKIP_PROLOGUE(pc)  (arm_skip_prologue (pc))
  64
  65 /* Immediately after a function call, return the saved pc.  Can't
  66    always go through the frames for this because on some machines the
  67    new frame is not set up until the new function executes some
  68    instructions.  */
  69
  70 #define SAVED_PC_AFTER_CALL(frame)  arm_saved_pc_after_call (frame)
  71 struct frame_info;
  72 extern CORE_ADDR arm_saved_pc_after_call (struct frame_info *);
  73
  74 /* The following define instruction sequences that will cause ARM
  75    cpu's to take an undefined instruction trap.  These are used to
  76    signal a breakpoint to GDB.
  77
  78    The newer ARMv4T cpu's are capable of operating in ARM or Thumb
  79    modes.  A different instruction is required for each mode.  The ARM
  80    cpu's can also be big or little endian.  Thus four different
  81    instructions are needed to support all cases.
  82
  83    Note: ARMv4 defines several new instructions that will take the
  84    undefined instruction trap.  ARM7TDMI is nominally ARMv4T, but does
  85    not in fact add the new instructions.  The new undefined
  86    instructions in ARMv4 are all instructions that had no defined
  87    behaviour in earlier chips.  There is no guarantee that they will
  88    raise an exception, but may be treated as NOP's.  In practice, it
  89    may only safe to rely on instructions matching:
  90
  91    3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
  92    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
  93    C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
  94
  95    Even this may only true if the condition predicate is true. The
  96    following use a condition predicate of ALWAYS so it is always TRUE.
  97
  98    There are other ways of forcing a breakpoint.  ARM Linux, RisciX,
  99    and I suspect NetBSD will all use a software interrupt rather than
 100    an undefined instruction to force a trap.  This can be handled by
 101    redefining some or all of the following in a target dependent
 102    fashion.  */
 103
 104 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
 105 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
 106 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
 107 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
 108
 109 /* Stack grows downward.  */
 110
 111 #define INNER_THAN(lhs,rhs) ((lhs) < (rhs))
 112
 113 /* !!!! if we're using RDP, then we're inserting breakpoints and
 114    storing their handles instread of what was in memory.  It is nice
 115    that this is the same size as a handle - otherwise remote-rdp will
 116    have to change. */
 117
 118 /* BREAKPOINT_FROM_PC uses the program counter value to determine
 119    whether a 16- or 32-bit breakpoint should be used.  It returns a
 120    pointer to a string of bytes that encode a breakpoint instruction,
 121    stores the length of the string to *lenptr, and adjusts the pc (if
 122    necessary) to point to the actual memory location where the
 123    breakpoint should be inserted.  */
 124
 125 extern breakpoint_from_pc_fn arm_breakpoint_from_pc;
 126 #define BREAKPOINT_FROM_PC(pcptr, lenptr) arm_breakpoint_from_pc (pcptr, lenptr)
 127
 128 /* Amount PC must be decremented by after a breakpoint.  This is often
 129    the number of bytes in BREAKPOINT but not always.  */
 130
 131 #define DECR_PC_AFTER_BREAK 0
 132
 133 /* Code to execute to print interesting information about the floating
 134    point processor (if any) or emulator.  No need to define if there
 135    is nothing to do. */
 136 extern void arm_float_info (void);
 137
 138 #define FLOAT_INFO      { arm_float_info (); }
 139
 140 /* Say how long (ordinary) registers are.  This is a piece of bogosity
 141    used in push_word and a few other places; REGISTER_RAW_SIZE is the
 142    real way to know how big a register is.  */
 143
 144 #define REGISTER_SIZE   4
 145
 146 /* Say how long FP registers are.  Used for documentation purposes and
 147    code readability in this header.  IEEE extended doubles are 80
 148    bits.  DWORD aligned they use 96 bits.  */
 149 #define FP_REGISTER_RAW_SIZE    12
 150
 151 /* GCC doesn't support long doubles (extended IEEE values).  The FP
 152    register virtual size is therefore 64 bits.  Used for documentation
 153    purposes and code readability in this header.  */
 154 #define FP_REGISTER_VIRTUAL_SIZE        8
 155
 156 /* Status registers are the same size as general purpose registers.
 157    Used for documentation purposes and code readability in this
 158    header.  */
 159 #define STATUS_REGISTER_SIZE    REGISTER_SIZE
 160
 161 /* Number of machine registers.  The only define actually required
 162    is NUM_REGS.  The other definitions are used for documentation
 163    purposes and code readability.  */
 164 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
 165    (and called PS for processor status) so the status bits can be cleared
 166    from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
 167    in PS.  */
 168 #define NUM_FREGS       8       /* Number of floating point registers.  */
 169 #define NUM_SREGS       2       /* Number of status registers.  */
 170 #define NUM_GREGS       16      /* Number of general purpose registers.  */
 171 #define NUM_REGS        (NUM_GREGS + NUM_FREGS + NUM_SREGS)
 172
 173 /* An array of names of registers. */
 174 extern char **arm_register_names;
 175
 176 #define REGISTER_NAME(i) arm_register_names[i]
 177
 178 /* Register numbers of various important registers.  Note that some of
 179    these values are "real" register numbers, and correspond to the
 180    general registers of the machine, and some are "phony" register
 181    numbers which are too large to be actual register numbers as far as
 182    the user is concerned but do serve to get the desired values when
 183    passed to read_register.  */
 184
 185 #define A1_REGNUM 0             /* first integer-like argument */
 186 #define A4_REGNUM 3             /* last integer-like argument */
 187 #define AP_REGNUM 11
 188 #define FP_REGNUM 11            /* Contains address of executing stack frame */
 189 #define SP_REGNUM 13            /* Contains address of top of stack */
 190 #define LR_REGNUM 14            /* address to return to from a function call */
 191 #define PC_REGNUM 15            /* Contains program counter */
 192 #define F0_REGNUM 16            /* first floating point register */
 193 #define F3_REGNUM 19            /* last floating point argument register */
 194 #define F7_REGNUM 23            /* last floating point register */
 195 #define FPS_REGNUM 24           /* floating point status register */
 196 #define PS_REGNUM 25            /* Contains processor status */
 197
 198 #define THUMB_FP_REGNUM 7       /* R7 is frame register on Thumb */
 199
 200 #define ARM_NUM_ARG_REGS        4
 201 #define ARM_LAST_ARG_REGNUM     A4_REGNUM
 202 #define ARM_NUM_FP_ARG_REGS     4
 203 #define ARM_LAST_FP_ARG_REGNUM  F3_REGNUM
 204
 205 /* Instruction condition field values.  */
 206 #define INST_EQ         0x0
 207 #define INST_NE         0x1
 208 #define INST_CS         0x2
 209 #define INST_CC         0x3
 210 #define INST_MI         0x4
 211 #define INST_PL         0x5
 212 #define INST_VS         0x6
 213 #define INST_VC         0x7
 214 #define INST_HI         0x8
 215 #define INST_LS         0x9
 216 #define INST_GE         0xa
 217 #define INST_LT         0xb
 218 #define INST_GT         0xc
 219 #define INST_LE         0xd
 220 #define INST_AL         0xe
 221 #define INST_NV         0xf
 222
 223 #define FLAG_N          0x80000000
 224 #define FLAG_Z          0x40000000
 225 #define FLAG_C          0x20000000
 226 #define FLAG_V          0x10000000
 227
 228
 229
 230 /* Total amount of space needed to store our copies of the machine's
 231    register state, the array `registers'.  */
 232
 233 #define REGISTER_BYTES ((NUM_GREGS * REGISTER_SIZE) + \
 234                         (NUM_FREGS * FP_REGISTER_RAW_SIZE) + \
 235                         (NUM_SREGS * STATUS_REGISTER_SIZE))
 236
 237 /* Index within `registers' of the first byte of the space for
 238    register N.  */
 239
 240 #define REGISTER_BYTE(N) \
 241      ((N) < F0_REGNUM \
 242       ? (N) * REGISTER_SIZE \
 243       : ((N) < PS_REGNUM \
 244          ? (NUM_GREGS * REGISTER_SIZE + \
 245             ((N) - F0_REGNUM) * FP_REGISTER_RAW_SIZE) \
 246          : (NUM_GREGS * REGISTER_SIZE + \
 247             NUM_FREGS * FP_REGISTER_RAW_SIZE + \
 248             ((N) - FPS_REGNUM) * STATUS_REGISTER_SIZE)))
 249
 250 /* Number of bytes of storage in the actual machine representation for
 251    register N.  All registers are 4 bytes, except fp0 - fp7, which are
 252    12 bytes in length.  */
 253 #define REGISTER_RAW_SIZE(N) \
 254      ((N) < F0_REGNUM ? REGISTER_SIZE : \
 255       (N) < FPS_REGNUM ? FP_REGISTER_RAW_SIZE : STATUS_REGISTER_SIZE)
 256
 257 /* Number of bytes of storage in a program's representation
 258    for register N.  */
 259 #define REGISTER_VIRTUAL_SIZE(N) \
 260         ((N) < F0_REGNUM ? REGISTER_SIZE : \
 261          (N) < FPS_REGNUM ? FP_REGISTER_VIRTUAL_SIZE : STATUS_REGISTER_SIZE)
 262
 263 /* Largest value REGISTER_RAW_SIZE can have.  */
 264
 265 #define MAX_REGISTER_RAW_SIZE FP_REGISTER_RAW_SIZE
 266
 267 /* Largest value REGISTER_VIRTUAL_SIZE can have.  */
 268 #define MAX_REGISTER_VIRTUAL_SIZE FP_REGISTER_VIRTUAL_SIZE
 269
 270 /* Nonzero if register N requires conversion from raw format to
 271    virtual format. */
 272 extern int arm_register_convertible (unsigned int);
 273 #define REGISTER_CONVERTIBLE(REGNUM) (arm_register_convertible (REGNUM))
 274
 275 /* Convert data from raw format for register REGNUM in buffer FROM to
 276    virtual format with type TYPE in buffer TO. */
 277
 278 extern void arm_register_convert_to_virtual (unsigned int regnum,
 279                                              struct type *type,
 280                                              void *from, void *to);
 281 #define REGISTER_CONVERT_TO_VIRTUAL(REGNUM,TYPE,FROM,TO) \
 282      arm_register_convert_to_virtual (REGNUM, TYPE, FROM, TO)
 283
 284 /* Convert data from virtual format with type TYPE in buffer FROM to
 285    raw format for register REGNUM in buffer TO.  */
 286
 287 extern void arm_register_convert_to_raw (unsigned int regnum,
 288                                          struct type *type,
 289                                          void *from, void *to);
 290 #define REGISTER_CONVERT_TO_RAW(TYPE,REGNUM,FROM,TO) \
 291      arm_register_convert_to_raw (REGNUM, TYPE, FROM, TO)
 292
 293 /* Return the GDB type object for the "standard" data type of data in
 294    register N.  */
 295
 296 #define REGISTER_VIRTUAL_TYPE(N) \
 297      (((unsigned)(N) - F0_REGNUM) < NUM_FREGS \
 298       ? builtin_type_double : builtin_type_int)
 299
 300 /* The system C compiler uses a similar structure return convention to gcc */
 301 extern use_struct_convention_fn arm_use_struct_convention;
 302 #define USE_STRUCT_CONVENTION(gcc_p, type) \
 303      arm_use_struct_convention (gcc_p, type)
 304
 305 /* Store the address of the place in which to copy the structure the
 306    subroutine will return.  This is called from call_function. */
 307
 308 #define STORE_STRUCT_RETURN(ADDR, SP) \
 309      write_register (A1_REGNUM, (ADDR))
 310
 311 /* Extract from an array REGBUF containing the (raw) register state a
 312    function return value of type TYPE, and copy that, in virtual
 313    format, into VALBUF.  */
 314
 315 extern void arm_extract_return_value (struct type *, char[], char *);
 316 #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
 317      arm_extract_return_value ((TYPE), (REGBUF), (VALBUF))
 318
 319 /* Write into appropriate registers a function return value of type
 320    TYPE, given in virtual format.  */
 321
 322 extern void convert_to_extended (void *dbl, void *ptr);
 323 #define STORE_RETURN_VALUE(TYPE,VALBUF) \
 324   if (TYPE_CODE (TYPE) == TYPE_CODE_FLT) {                              \
 325     char _buf[MAX_REGISTER_RAW_SIZE];                                   \
 326     convert_to_extended (VALBUF, _buf);                                         \
 327     write_register_bytes (REGISTER_BYTE (F0_REGNUM), _buf, MAX_REGISTER_RAW_SIZE); \
 328   } else                                                                \
 329     write_register_bytes (0, VALBUF, TYPE_LENGTH (TYPE))
 330
 331 /* Extract from an array REGBUF containing the (raw) register state
 332    the address in which a function should return its structure value,
 333    as a CORE_ADDR (or an expression that can be used as one).  */
 334
 335 #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
 336   (extract_address ((PTR)(REGBUF), REGISTER_RAW_SIZE(0)))
 337
 338 /* Specify that for the native compiler variables for a particular
 339    lexical context are listed after the beginning LBRAC instead of
 340    before in the executables list of symbols.  */
 341 #define VARIABLES_INSIDE_BLOCK(desc, gcc_p) (!(gcc_p))
 342 \f
 343
 344 /* Define other aspects of the stack frame.  We keep the offsets of
 345    all saved registers, 'cause we need 'em a lot!  We also keep the
 346    current size of the stack frame, and the offset of the frame
 347    pointer from the stack pointer (for frameless functions, and when
 348    we're still in the prologue of a function with a frame) */
 349
 350 #define EXTRA_FRAME_INFO        \
 351   struct frame_saved_regs fsr;  \
 352   int framesize;                \
 353   int frameoffset;              \
 354   int framereg;
 355
 356 extern void arm_init_extra_frame_info (int fromleaf, struct frame_info * fi);
 357 #define INIT_EXTRA_FRAME_INFO(fromleaf, fi) \
 358         arm_init_extra_frame_info ((fromleaf), (fi))
 359
 360 /* Return the frame address.  On ARM, it is R11; on Thumb it is R7.  */
 361 CORE_ADDR arm_target_read_fp (void);
 362 #define TARGET_READ_FP() arm_target_read_fp ()
 363
 364 /* Describe the pointer in each stack frame to the previous stack
 365    frame (its caller).  */
 366
 367 /* FRAME_CHAIN takes a frame's nominal address and produces the
 368    frame's chain-pointer.
 369
 370    However, if FRAME_CHAIN_VALID returns zero,
 371    it means the given frame is the outermost one and has no caller.  */
 372
 373 #define FRAME_CHAIN(thisframe) arm_frame_chain (thisframe)
 374 extern CORE_ADDR arm_frame_chain (struct frame_info *);
 375
 376 extern int arm_frame_chain_valid (CORE_ADDR, struct frame_info *);
 377 #define FRAME_CHAIN_VALID(chain, thisframe) \
 378      arm_frame_chain_valid (chain, thisframe)
 379
 380 /* Define other aspects of the stack frame.  */
 381
 382 /* A macro that tells us whether the function invocation represented
 383    by FI does not have a frame on the stack associated with it.  If it
 384    does not, FRAMELESS is set to 1, else 0.
 385
 386    Sometimes we have functions that do a little setup (like saving the
 387    vN registers with the stmdb instruction, but DO NOT set up a frame.
 388    The symbol table will report this as a prologue.  However, it is
 389    important not to try to parse these partial frames as frames, or we
 390    will get really confused.
 391
 392    So I will demand 3 instructions between the start & end of the
 393    prologue before I call it a real prologue, i.e. at least
 394          mov ip, sp,
 395          stmdb sp!, {}
 396          sub sp, ip, #4. */
 397
 398 extern int arm_frameless_function_invocation (struct frame_info *fi);
 399 #define FRAMELESS_FUNCTION_INVOCATION(FI) \
 400 (arm_frameless_function_invocation (FI))
 401
 402 /* Saved Pc.  */
 403
 404 #define FRAME_SAVED_PC(FRAME)   arm_frame_saved_pc (FRAME)
 405 extern CORE_ADDR arm_frame_saved_pc (struct frame_info *);
 406
 407 #define FRAME_ARGS_ADDRESS(fi) (fi->frame)
 408
 409 #define FRAME_LOCALS_ADDRESS(fi) ((fi)->frame)
 410
 411 /* Return number of args passed to a frame.
 412    Can return -1, meaning no way to tell.  */
 413
 414 #define FRAME_NUM_ARGS(fi) (-1)
 415
 416 /* Return number of bytes at start of arglist that are not really args. */
 417
 418 #define FRAME_ARGS_SKIP 0
 419
 420 /* Put here the code to store, into a struct frame_saved_regs, the
 421    addresses of the saved registers of frame described by FRAME_INFO.
 422    This includes special registers such as pc and fp saved in special
 423    ways in the stack frame.  sp is even more special: the address we
 424    return for it IS the sp for the next frame.  */
 425
 426 struct frame_saved_regs;
 427 struct frame_info;
 428 void arm_frame_find_saved_regs (struct frame_info * fi,
 429                                 struct frame_saved_regs * fsr);
 430
 431 #define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \
 432         arm_frame_find_saved_regs (frame_info, &(frame_saved_regs));
 433
 434 /* Things needed for making the inferior call functions.  */
 435
 436 #define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
 437      sp = arm_push_arguments ((nargs), (args), (sp), (struct_return), (struct_addr))
 438 extern CORE_ADDR arm_push_arguments (int, struct value **, CORE_ADDR, int,
 439                                      CORE_ADDR);
 440
 441 /* Push an empty stack frame, to record the current PC, etc.  */
 442
 443 void arm_push_dummy_frame (void);
 444
 445 #define PUSH_DUMMY_FRAME arm_push_dummy_frame ()
 446
 447 /* Discard from the stack the innermost frame, restoring all registers.  */
 448
 449 void arm_pop_frame (void);
 450
 451 #define POP_FRAME arm_pop_frame ()
 452
 453 /* This sequence of words is the instructions
 454
 455    mov  lr,pc
 456    mov  pc,r4
 457    illegal
 458
 459    Note this is 12 bytes.  */
 460
 461 #define CALL_DUMMY {0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe}
 462 #define CALL_DUMMY_START_OFFSET  0      /* Start execution at beginning of dummy */
 463
 464 #define CALL_DUMMY_BREAKPOINT_OFFSET arm_call_dummy_breakpoint_offset()
 465 extern int arm_call_dummy_breakpoint_offset (void);
 466
 467 /* Insert the specified number of args and function address into a
 468    call sequence of the above form stored at DUMMYNAME.  */
 469
 470 #define FIX_CALL_DUMMY(dummyname, pc, fun, nargs, args, type, gcc_p) \
 471    arm_fix_call_dummy ((dummyname), (pc), (fun), (nargs), (args), (type), (gcc_p))
 472
 473 void arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun,
 474                          int nargs, struct value ** args,
 475                          struct type * type, int gcc_p);
 476
 477 CORE_ADDR arm_get_next_pc (CORE_ADDR pc);
 478
 479 /* Macros for setting and testing a bit in a minimal symbol that marks
 480    it as Thumb function.  The MSB of the minimal symbol's "info" field
 481    is used for this purpose. This field is already being used to store
 482    the symbol size, so the assumption is that the symbol size cannot
 483    exceed 2^31.
 484
 485    COFF_MAKE_MSYMBOL_SPECIAL
 486    ELF_MAKE_MSYMBOL_SPECIAL
 487
 488    These macros test whether the COFF or ELF symbol corresponds to a
 489    thumb function, and set a "special" bit in a minimal symbol to
 490    indicate that it does.
 491
 492    MSYMBOL_SET_SPECIAL  Actually sets the "special" bit.
 493    MSYMBOL_IS_SPECIAL   Tests the "special" bit in a minimal symbol.
 494    MSYMBOL_SIZE         Returns the size of the minimal symbol,
 495                         i.e. the "info" field with the "special" bit
 496                         masked out
 497    */
 498
 499 extern int coff_sym_is_thumb (int val);
 500
 501 #define MSYMBOL_SET_SPECIAL(msym) \
 502         MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000)
 503 #define MSYMBOL_IS_SPECIAL(msym) \
 504   (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
 505 #define MSYMBOL_SIZE(msym) \
 506   ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
 507
 508 /* Thumb symbols are of type STT_LOPROC, (synonymous with STT_ARM_TFUNC) */
 509 #define ELF_MAKE_MSYMBOL_SPECIAL(sym,msym) \
 510         { if(ELF_ST_TYPE(((elf_symbol_type *)(sym))->internal_elf_sym.st_info) == STT_LOPROC) \
 511                 MSYMBOL_SET_SPECIAL(msym); }
 512
 513 #define COFF_MAKE_MSYMBOL_SPECIAL(val,msym) \
 514  { if(coff_sym_is_thumb(val)) MSYMBOL_SET_SPECIAL(msym); }
 515
 516 /* The first 0x20 bytes are the trap vectors.  */
 517 #define LOWEST_PC       0x20
 518
 519 /* Function to determine whether MEMADDR is in a Thumb function.  */
 520 extern int arm_pc_is_thumb (bfd_vma memaddr);
 521
 522 /* Function to determine whether MEMADDR is in a call dummy called from
 523    a Thumb function.  */
 524 extern int arm_pc_is_thumb_dummy (bfd_vma memaddr);
 525
 526 #endif /* TM_ARM_H */